17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 57c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 67c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 77c478bd9Sstevel@tonic-gate * with the License. 87c478bd9Sstevel@tonic-gate * 97c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 107c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 117c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 127c478bd9Sstevel@tonic-gate * and limitations under the License. 137c478bd9Sstevel@tonic-gate * 147c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 157c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 167c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 177c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 187c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 197c478bd9Sstevel@tonic-gate * 207c478bd9Sstevel@tonic-gate * CDDL HEADER END 217c478bd9Sstevel@tonic-gate */ 227c478bd9Sstevel@tonic-gate /* 237c478bd9Sstevel@tonic-gate * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 247c478bd9Sstevel@tonic-gate * All rights reserved. 257c478bd9Sstevel@tonic-gate */ 267c478bd9Sstevel@tonic-gate 277c478bd9Sstevel@tonic-gate /* 287c478bd9Sstevel@tonic-gate * hci1394_extern.c 297c478bd9Sstevel@tonic-gate * Central location for externs. There are two exceptions to this, 307c478bd9Sstevel@tonic-gate * hci1394_statep (located in hci1394.c) and hci1394_evts (located in 317c478bd9Sstevel@tonic-gate * hci1394_s1394if.c). 327c478bd9Sstevel@tonic-gate */ 337c478bd9Sstevel@tonic-gate 347c478bd9Sstevel@tonic-gate #include <sys/conf.h> 357c478bd9Sstevel@tonic-gate #include <sys/ddi.h> 367c478bd9Sstevel@tonic-gate #include <sys/modctl.h> 377c478bd9Sstevel@tonic-gate #include <sys/stat.h> 387c478bd9Sstevel@tonic-gate 397c478bd9Sstevel@tonic-gate #include <sys/1394/h1394.h> 407c478bd9Sstevel@tonic-gate 417c478bd9Sstevel@tonic-gate #include <sys/1394/adapters/hci1394.h> 427c478bd9Sstevel@tonic-gate 437c478bd9Sstevel@tonic-gate 447c478bd9Sstevel@tonic-gate 457c478bd9Sstevel@tonic-gate /* 467c478bd9Sstevel@tonic-gate * The 1394 bus ticks are in 125uS increments. split_timeout is represented in 477c478bd9Sstevel@tonic-gate * 1394 bus ticks. 800 bus ticks is 100mS. 487c478bd9Sstevel@tonic-gate */ 497c478bd9Sstevel@tonic-gate uint32_t hci1394_split_timeout = 800; 507c478bd9Sstevel@tonic-gate 517c478bd9Sstevel@tonic-gate 527c478bd9Sstevel@tonic-gate /* 53*0778188fSHengqing Hu * 1394 address map for OpenHCI adapters. 547c478bd9Sstevel@tonic-gate * 557c478bd9Sstevel@tonic-gate * This is what is reported to the services layer. The hci1394 driver does not 567c478bd9Sstevel@tonic-gate * modify the HW to reflect this. This should reflect what the OpenHCI 1.0 HW 577c478bd9Sstevel@tonic-gate * is set to. The comments below give the actual address ranges where the 587c478bd9Sstevel@tonic-gate * actual structure has the format of - start address, size, type. 597c478bd9Sstevel@tonic-gate * 607c478bd9Sstevel@tonic-gate * physical => 0x0000000000000000 - 0x00000000FFFFFFFF 617c478bd9Sstevel@tonic-gate * posted write => 0x0000000100000000 - 0x0000FFFEFFFFFFFF 627c478bd9Sstevel@tonic-gate * normal => 0x0000FFFF00000000 - 0x0000FFFFEFFFFFFF 637c478bd9Sstevel@tonic-gate * csr => 0x0000FFFFF0000000 - 0x0000FFFFFFFFFFFF 647c478bd9Sstevel@tonic-gate */ 657c478bd9Sstevel@tonic-gate h1394_addr_map_t hci1394_addr_map[HCI1394_ADDR_MAP_SIZE] = { 667c478bd9Sstevel@tonic-gate {0x0000000000000000, 0x0000000100000000, H1394_ADDR_PHYSICAL}, 677c478bd9Sstevel@tonic-gate {0x0000000100000000, 0x0000FFFE00000000, H1394_ADDR_POSTED_WRITE}, 687c478bd9Sstevel@tonic-gate {0x0000FFFF00000000, 0x00000000F0000000, H1394_ADDR_NORMAL}, 697c478bd9Sstevel@tonic-gate {0x0000FFFFF0000000, 0x0000000010000000, H1394_ADDR_CSR} 707c478bd9Sstevel@tonic-gate }; 717c478bd9Sstevel@tonic-gate 727c478bd9Sstevel@tonic-gate 737c478bd9Sstevel@tonic-gate /* Max number of uS to wait for phy reads & writes to finish */ 747c478bd9Sstevel@tonic-gate uint_t hci1394_phy_delay_uS = 10; 757c478bd9Sstevel@tonic-gate 767c478bd9Sstevel@tonic-gate /* 777c478bd9Sstevel@tonic-gate * Time to wait for PHY to SCLK to be stable. There does not seem to be standard 787c478bd9Sstevel@tonic-gate * time for how long wait for the PHY to come up. The problem is that the PHY 797c478bd9Sstevel@tonic-gate * provides a clock to the link layer and if that is not stable, we could get a 807c478bd9Sstevel@tonic-gate * PCI timeout error when reading/writing a phy register (and maybe an OpenHCI 817c478bd9Sstevel@tonic-gate * register?) This used to be set to 10mS which works for just about every 827c478bd9Sstevel@tonic-gate * adapter we tested on. We got a new TI adapter which would crash the system 837c478bd9Sstevel@tonic-gate * once in a while if nothing (1394 device) was plugged into the adapter? 847c478bd9Sstevel@tonic-gate * Changing this delay to 50mS made that problem go away. 857c478bd9Sstevel@tonic-gate * 867c478bd9Sstevel@tonic-gate * NOTE: Do not this delay unless you know what your doing!!!! 877c478bd9Sstevel@tonic-gate */ 887c478bd9Sstevel@tonic-gate uint_t hci1394_phy_stabilization_delay_uS = 50000; 89