1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright (c) 2018, Joyent, Inc. 14 * Copyright 2023 Oxide Computer Company 15 */ 16 17 #ifndef _LIBJEDEC_H 18 #define _LIBJEDEC_H 19 20 /* 21 * Library routines that support various JEDEC standards: 22 * 23 * o JEDEC JEP-106 vendor data 24 * o Temperature range and Measurement Standards for Components and Modules 25 * (JESD402-1) 26 * o DDR4 Serial Presence Detect (SPD) decoding 27 * o DDR5 Serial Presence Detect (SPD) decoding 28 */ 29 30 #include <sys/types.h> 31 #include <stdint.h> 32 #include <libnvpair.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /* 39 * Decode a JEDEC continuation ID (without parity) and a group ID. 40 */ 41 extern const char *libjedec_vendor_string(uint_t, uint_t); 42 43 /* 44 * JEDEC operating temperature ranges. These are defined in JESD402-1A (March 45 * 2022). 46 */ 47 typedef enum { 48 /* 49 * Case Operating Temperature Ranges 50 */ 51 JEDEC_TEMP_CASE_A1T, 52 JEDEC_TEMP_CASE_A2T, 53 JEDEC_TEMP_CASE_A3T, 54 JEDEC_TEMP_CASE_IT, 55 JEDEC_TEMP_CASE_ET, 56 JEDEC_TEMP_CASE_ST, 57 JEDEC_TEMP_CASE_XT, 58 JEDEC_TEMP_CASE_NT, 59 JEDEC_TEMP_CASE_RT, 60 /* 61 * Operating Ambient Temperature Ranges 62 */ 63 JEDEC_TEMP_AMB_CT, 64 JEDEC_TEMP_AMB_IOT, 65 JEDEC_TEMP_AMB_IPT, 66 JEDEC_TEMP_AMB_IXT, 67 JEDEC_TEMP_AMB_AO3T, 68 JEDEC_TEMP_AMB_AO2T, 69 JEDEC_TEMP_AMB_AO1T, 70 /* 71 * Storage temperature ranges 72 */ 73 JEDEC_TEMP_STOR_2, 74 JEDEC_TEMP_STOR_1B, 75 JEDEC_TEMP_STOR_1A, 76 JEDEC_TEMP_STOR_ST 77 } libjedec_temp_range_t; 78 extern boolean_t libjedec_temp_range(libjedec_temp_range_t, int32_t *, 79 int32_t *); 80 81 /* 82 * This is a series of error codes that libjedec may produce while trying to 83 * parse the overall SPD data structure. These represent a top-level failure and 84 * have meaning when no nvlist_t is returned. 85 */ 86 typedef enum { 87 /* 88 * Indicates that we didn't encounter a fatal error; however, we may 89 * have a specific parsing error that relates to a key in the nvlist. 90 */ 91 LIBJEDEC_SPD_OK = 0, 92 /* 93 * Indicates that we did not have enough memory while trying to 94 * construct the generated nvlist_t. 95 */ 96 LIBJEDEC_SPD_NOMEM, 97 /* 98 * Indicates that the data that we found was insufficient to 99 * successfully parse basic information. The required size varies per 100 * SPD key byte type. 101 */ 102 LIBJEDEC_SPD_TOOSHORT, 103 /* 104 * Indicates that we found an unsupported type of SPD data and therefore 105 * cannot parse this. 106 */ 107 LIBJEDEC_SPD_UNSUP_TYPE, 108 /* 109 * Indicates that while we found a supported type of SPD data, we do not 110 * understand its revision. 111 */ 112 LIBJEDEC_SPD_UNSUP_REV 113 } spd_error_t; 114 115 /* 116 * Decode a binary payload of SPD data, if possible. The returned nvlist is made 117 * up of a series of keys described below. Parsing errors are broken into two 118 * categories. Fatal errors set a value in the spd_error_t below. Non-fatal 119 * errors, such as encountering a value which we don't have a translation for, 120 * are in a nested errors nvlist_t indexed by key. 121 * 122 * The keys are all dot delineated to create a few different top-level 123 * namespaces. These include: 124 * 125 * "meta" -- Which includes information about the SPD, encoding, and things like 126 * the type of module. 127 * 128 * "dram" -- Parameters that are specific to the SDRAM dies present. What one 129 * thinks of as a stick of DRAM consists of several different SDRAM dies on the 130 * PCB. This includes things like the row and columns bits and timing 131 * information. 132 * 133 * "ddr4", "ddr5" -- These include information which is specific to the general 134 * DDR standard. While we have tried to consolidate information between them 135 * where applicable, some things are specific to the standard. 136 * 137 * "module" -- Parameters that are specific to the broader module and PCB 138 * itself. This includes information like the height or devices present. 139 * 140 * "ddr4.rdimm", "ddr4.lrdimm", "ddr5.rdimm", etc. -- These are parameter that 141 * are specific to a module being both the combination of a specific DDR 142 * standard and a specific type of module. Common parameters are often in the 143 * "module" section. 144 * 145 * "mfg" -- Manufacturing related information. 146 * 147 * "errors" -- The key for the errors nvlist_t. See the spd_error_kind_t 148 * definition later on. Each error has both a numeric code and a string message. 149 */ 150 extern nvlist_t *libjedec_spd(const uint8_t *, size_t, spd_error_t *); 151 152 /* 153 * The following are keys in the metadata nvlist_t. The SPD_KEY_NBYTES_TOTAL is 154 * present in DDR4 and DDR5. The SPD_KEY_NBYTES_USED is only present on DDR4 155 * right now. All supported SPD encodings have the raw revision information. If 156 * the values for the total bytes or used bytes are set to undefined, then they 157 * will not be present. 158 * 159 * DDR5 introduces an idea of a public beta level that gets reset between 160 * external releases. It theoretically modifies every scion. DDR5 also 161 * introduces a second revision that is for the module information. This will 162 * not be present on systems prior to DDR5. 163 */ 164 #define SPD_KEY_NBYTES_TOTAL "meta.total-bytes" /* uint32_t */ 165 #define SPD_KEY_NBYTES_USED "meta.used-bytes" /* uint32_t */ 166 #define SPD_KEY_REV_ENC "meta.revision-encoding" /* uint32_t */ 167 #define SPD_KEY_REV_ADD "meta.revision-additions" /* uint32_t */ 168 #define SPD_KEY_BETA "meta.beta-version" /* uint32_t */ 169 #define SPD_KEY_MOD_REV_ENC "meta.module-revision-encoding" /* uint32_t */ 170 #define SPD_KEY_MOD_REV_ADD "meta.module-revision-additions" /* uint32_t */ 171 172 /* 173 * DRAM Type information. This indicates the standard that the device conforms 174 * to. This enumeration's values match the JEDEC specification's values. This is 175 * present for everything. 176 */ 177 typedef enum { 178 SPD_DT_FAST_PAGE_MODE = 0x01, 179 SPD_DT_EDO = 0x02, 180 SPD_DT_PIPE_NIBBLE = 0x03, 181 SPD_DT_SDRAM = 0x04, 182 SPD_DT_ROM = 0x05, 183 SPD_DT_DDR_SGRAM = 0x06, 184 SPD_DT_DDR_SDRAM = 0x07, 185 SPD_DT_DDR2_SDRAM = 0x08, 186 SPD_DT_DDR2_SDRAM_FBDIMM = 0x09, 187 SPD_DT_DDR2_SDRAM_FDIMM_P = 0x0a, 188 SPD_DT_DDR3_SDRAM = 0x0b, 189 SPD_DT_DDR4_SDRAM = 0x0c, 190 SPD_DT_DDR4E_SDRAM = 0x0e, 191 SPD_DT_LPDDR3_SDRAM = 0x0f, 192 SPD_DT_LPDDR4_SDRAM = 0x10, 193 SPD_DT_LPDDR4X_SDRAM = 0x11, 194 SPD_DT_DDR5_SDRAM = 0x12, 195 SPD_DT_LPDDR5_SDRAM = 0x13, 196 SPD_DT_DDR5_NVDIMM_P = 0x14, 197 SPD_DT_LPDDR5X_SDRAM = 0x15 198 } spd_dram_type_t; 199 #define SPD_KEY_DRAM_TYPE "meta.dram-type" /* uint32_t (enum) */ 200 201 typedef enum { 202 SPD_MOD_TYPE_RDIMM, 203 SPD_MOD_TYPE_UDIMM, 204 SPD_MOD_TYPE_SODIMM, 205 SPD_MOD_TYPE_LRDIMM, 206 SPD_MOD_TYPE_MRDIMM, 207 SPD_MOD_TYPE_DDIMM, 208 SPD_MOD_TYPE_SOLDER, 209 SPD_MOD_TYPE_MINI_RDIMM, 210 SPD_MOD_TYPE_MINI_UDIMM, 211 SPD_MOD_TYPE_72b_SO_RDIMM, 212 SPD_MOD_TYPE_72b_SO_UDIMM, 213 SPD_MOD_TYPE_16b_SO_DIMM, 214 SPD_MOD_TYPE_32b_SO_DIMM 215 } spd_module_type_t; 216 #define SPD_KEY_MOD_TYPE "meta.module-type" /* uint32_t (enum) */ 217 typedef enum { 218 SPD_MOD_NOT_HYBRID, 219 SPD_MOD_HYBRID_NVDIMMM 220 } spd_module_hybrid_t; 221 #define SPD_KEY_MOD_HYBRID_TYPE "meta.hybrid-type" /* uint32_t */ 222 223 typedef enum { 224 SPD_MOD_TYPE_NVDIMM_N, 225 SPD_MOD_TYPE_NVDIMM_P, 226 SPD_MOD_TYPE_NVDIMM_H 227 } spd_module_nvdimm_type_t; 228 #define SPD_KEY_MOD_NVDIMM_TYPE "meta.nvdimm-type" /* uint32_t */ 229 230 /* 231 * Different SPD standards have different integrity rules. The regions covered 232 * by the CRCs also vary. We end up with per-spec keys. All data types for these 233 * are uint32_t's so that way we can record the expected CRC. We use a uint32_t 234 * for consistency even though the data only fits in a uint16_t. Note, callers 235 * must check to see if these exist. If there are keys with these names in the 236 * errors object, then the rest of the data should be considered suspect, but we 237 * will have attempted to parse everything we can. 238 */ 239 #define SPD_KEY_CRC_DDR4_BASE "meta.crc-ddr4-base" /* uint32_t */ 240 #define SPD_KEY_CRC_DDR4_BLK1 "meta.crc-ddr4-block1" /* uint32_t */ 241 #define SPD_KEY_CRC_DDR5 "meta.crc-ddr5" /* uint32_t */ 242 243 /* 244 * DDR5 adds a field in the SPD to describe how data should be hashed to compute 245 * and compare to an attribute certification to authenticate modules. This is 246 * only present in DDR5. We only add a value here if this is actually supported. 247 */ 248 typedef enum { 249 SPD_HASH_SEQ_ALG_1 250 } spd_hash_seq_alg_t; 251 #define SPD_KEY_HASH_SEQ "meta.hash-sequence-algorithm" /* uint32_t */ 252 253 /* 254 * This section contains information related to DRAM technology. 255 */ 256 257 /* 258 * Bank, bank group, row, and column bits. These are all present in both DDR4 259 * and DDR5. DDR4 allows cases where there are no bank groups. If no bits are 260 * used, then this item is empty. 261 */ 262 #define SPD_KEY_NROW_BITS "dram.num-row-bits" /* uint32_t */ 263 #define SPD_KEY_NCOL_BITS "dram.num-column-bits" /* uint32_t */ 264 #define SPD_KEY_NBANK_BITS "dram.num-bank-bits" /* uint32_t */ 265 #define SPD_KEY_NBGRP_BITS "dram.num-bank-group-bits" /* uint32_t */ 266 #define SPD_KEY_SEC_NROW_BITS "dram.sec-num-row-bits" /* uint32_t */ 267 #define SPD_KEY_SEC_NCOL_BITS "dram.sec-num-column-bits" /* uint32_t */ 268 #define SPD_KEY_SEC_NBANK_BITS "dram.sec-num-bank-bits" /* uint32_t */ 269 #define SPD_KEY_SEC_NBGRP_BITS "dram.sec-num-bank-group-bits" /* uint32_t */ 270 271 /* 272 * Die Density. This is the capacity that each die contains in bits. 273 */ 274 #define SPD_KEY_DIE_SIZE "dram.die-bit-size" /* uint64_t */ 275 #define SPD_KEY_SEC_DIE_SIZE "dram.sec-die-bit-size" /* uint64_t */ 276 277 /* 278 * Package information. DRAM may be made up of a monolithic package type or 279 * several different types. There is a boolean property present to indicate that 280 * it is not monolithic. For these there is a die count and then a separate 281 * notion of what the signal loading type is. If the property is present then we 282 * will also have the die count and loading type for the secondary. Note, these 283 * loading parameters are considered at the device balls as opposed to specific 284 * signals. 285 */ 286 #define SPD_KEY_PKG_NOT_MONO "meta.non-monolithic-package" /* key only */ 287 #define SPD_KEY_PKG_NDIE "dram.package-die-count" /* uint32_t */ 288 #define SPD_KEY_SEC_PKG_NDIE "dram.sec-package-die-count" /* uint32_t */ 289 typedef enum { 290 SPD_SL_UNSPECIFIED, 291 SPD_SL_MUTLI_STACK, 292 SPD_SL_3DS 293 } spd_signal_loading_t; 294 #define SPD_KEY_PKG_SL "dram.package-sig-loading" /* uint32_t */ 295 #define SPD_KEY_SEC_PKG_SL "dram.sec-package-sig-loading" /* uint32_t */ 296 297 /* 298 * Post-package Repair. PPR is supported in DDR4 and DDR5. A key is used to 299 * indicate If PPR is not supported, then this will not be present. 300 */ 301 typedef enum { 302 SPD_PPR_F_HARD_PPR = 1 << 0, 303 SPD_PPR_F_SOFT_PPR = 1 << 2, 304 SPD_PPR_F_MBIST_PPR = 1 << 3, 305 SPD_PPR_F_PPR_UNDO = 1 << 4 306 } spd_ppr_flags_t; 307 308 typedef enum { 309 SPD_PPR_GRAN_BANK_GROUP, 310 SPD_PPR_GRAN_BANK 311 } spd_ppr_gran_t; 312 #define SPD_KEY_PPR "dram.ppr-flags" /* uint32_t (enum) */ 313 #define SPD_KEY_PPR_GRAN "dram.ppr-gran" /* uint32_t (enum) */ 314 315 /* 316 * Voltages in mV. This is an array of nominal voltages that are supported. DDR3 317 * defines multiple voltages, but DDR4 and DDR5 only have a single voltage 318 * (specific to the supply). DDR3 and DDR4 only defined V~DD~ in SPD. While 319 * V~DQ~ and V~PP~ are defined in DDR5. 320 */ 321 #define SPD_KEY_NOM_VDD "dram.nominal-vdd" /* uint32_t[] */ 322 #define SPD_KEY_NOM_VDDQ "dram.nominal-vddq" /* uint32_t[] */ 323 #define SPD_KEY_NOM_VPP "dram.nominal-vpp" /* uint32_t[] */ 324 325 /* 326 * DRAM module organization. This describes the number of ranks that exist on 327 * the device. In DDR5 this refers to the sub-channel. In DDR4, it refers to the 328 * entire channel. The rank mix may be symmetrical or asymmetrical. A key will 329 * be set if that's the case. 330 */ 331 #define SPD_KEY_RANK_ASYM "dram.asymmetrical-ranks" /* key */ 332 #define SPD_KEY_NRANKS "dram.num-ranks" /* uint32_t */ 333 334 /* 335 * DRAM and Module widths. The module width is what we think of of when we think 336 * of an entire stick, e.g. the DDR4 72-bit (64-bit data, 8-bit ECC) bus. 337 * Separately the individual DRAM dies themselves have a width which is 338 * SPD_KEY_DRAM_WIDTH. The main bus width is split between the primary data size 339 * and the ecc data size. In DDR4 and earlier this is the entire channel. In 340 * DDR5 this is duplicated for each sub-channel. 341 */ 342 #define SPD_KEY_DRAM_WIDTH "dram.width" /* uint32_t */ 343 #define SPD_KEY_SEC_DRAM_WIDTH "dram.sec-width" /* uint32_t */ 344 #define SPD_KEY_NSUBCHAN "module.num-subchan" /* uint32_t */ 345 #define SPD_KEY_DATA_WIDTH "module.data-width" /* uint32_t */ 346 #define SPD_KEY_ECC_WIDTH "module.ecc-width" /* uint32_t */ 347 348 /* 349 * DDR3 and DDR4 specify specific timebases in the SPD data. DDR5 just requires 350 * a specific timebase. In the case of DDR5 we just set both values to be the 351 * same. This like all other time values is explicitly in ps. 352 */ 353 #define SPD_KEY_MTB "dram.median-time-base" /* uint32_t */ 354 #define SPD_KEY_FTB "dram.fine-time-base" /* uint32_t */ 355 356 /* 357 * Supported CAS Latencies. This is an array of integers to indicate which index 358 * CAS latencies are possible. 359 */ 360 #define SPD_KEY_CAS "dram.cas-latencies" /* uint32_t [] */ 361 362 /* 363 * Time parameters. These are all in picoseconds. All values are uint64_t. 364 */ 365 #define SPD_KEY_TCKAVG_MIN "dram.t~CKAVG~min" 366 #define SPD_KEY_TCKAVG_MAX "dram.t~CKAVG~max" 367 #define SPD_KEY_TAA_MIN "dram.t~AA~min" 368 #define SPD_KEY_TRCD_MIN "dram.t~RCD~min" 369 #define SPD_KEY_TRP_MIN "dram.t~RP~min" 370 #define SPD_KEY_TRAS_MIN "dram.t~RAS~min" 371 #define SPD_KEY_TRC_MIN "dram.t~RC~min" 372 #define SPD_KEY_TRFC1_MIN "dram.t~RFC1~min" 373 #define SPD_KEY_TRFC2_MIN "dram.t~RFC2~min" 374 #define SPD_KEY_TFAW "dram.t~FAW~" 375 #define SPD_KEY_TRRD_L_MIN "dram.t~RRD_S~min" 376 #define SPD_KEY_TCCD_L_MIN "dram.t~CCD_S~min" 377 #define SPD_KEY_TWR_MIN "dram.t~WR~min" 378 379 /* 380 * The following time are only used in DDR4. While some of the DDR4 and DDR5 381 * write to read or write to write parameters are similar, because they use 382 * different names for times, we distinguish them as different values. 383 */ 384 #define SPD_KEY_TRFC4_MIN "dram.t~RFC4~min" 385 #define SPD_KEY_TRRD_S_MIN "dram.t~RRD_S~min" 386 #define SPD_KEY_TWTRS_MIN "dram.t~WTR_S~min" 387 #define SPD_KEY_TWTRL_MIN "dram.t~WTR_L~min" 388 389 /* 390 * The following times are specific to DDR5. t~CCD_L_WTR~ in DDR5 is the 391 * equivalent to t~WTRS_L~min, same with t~CCD_S_WTR~. 392 */ 393 #define SPD_KEY_TCCDLWR "dram.t~CCD_L_WR" 394 #define SPD_KEY_TCCDLWR2 "dram.t~CCD_L_WR2" 395 #define SPD_KEY_TCCDLWTR "dram.t~CCD_L_WTR" 396 #define SPD_KEY_TCCDSWTR "dram.t~CCD_S_WTR" 397 #define SPD_KEY_TRTP "dram.t~RTP~" 398 399 /* 400 * While prior DDR standards did have minimum clock times for certain 401 * activities, these were first added to the SPD data in DDR5. All values for 402 * these are uint32_t's and are in clock cycles. 403 */ 404 #define SPD_KEY_TRRDL_NCK "dram.t~RRD_L~nCK" 405 #define SPD_KEY_TCCDL_NCK "dram.t~CCD_L~nCK" 406 #define SPD_KEY_TCCDLWR_NCK "dram.t~CCD_L_WR~nCK" 407 #define SPD_KEY_TCCDLWR2_NCK "dram.t~CCD_L_WR2~nCK" 408 #define SPD_KEY_TFAW_NCK "dram.t~FAW~nCK" 409 #define SPD_KEY_TCCDLWTR_NCK "dram.t~CCD_L_WTR~nCK" 410 #define SPD_KEY_TCCDSWTR_NCK "dram.t~CCD_S_WTR~nCK" 411 #define SPD_KEY_TRTP_NCK "dram.t~RTP~nCK" 412 413 /* 414 * The following times are only used in DDR5. The RFCx_dlr values are for 3DS 415 * RDIMMs. 416 */ 417 #define SPD_KEY_TRFCSB "dram.t~RFCsb~" 418 #define SPD_KEY_TRFC1_DLR "dram.3ds-t~RFC1_dlr~" 419 #define SPD_KEY_TRFC2_DLR "dram.3ds-t~RFC2_dlr~" 420 #define SPD_KEY_TRFCSB_DLR "dram.3ds-t~RFCsb_dlr~" 421 422 /* 423 * The following are DDR4 specific properties, so they are prefixed with "ddr4". 424 * These refer to the maximum activate window and the maximum activate count. In 425 * cases where the MAC is unknown no key will be present. 426 */ 427 #define SPD_KEY_DDR4_MAW "ddr4.maw" /* uint32_t */ 428 #define SPD_KEY_DDR4_MAC "ddr4.mac" /* uint32_t */ 429 #define SPD_KEY_DDR4_MAC_UNLIMITED UINT32_MAX 430 431 /* 432 * The following are DDR5 specific properties. BL32 indicates whether burst 433 * length 32 mode is supported, which is a key. Along with the partial array 434 * self refresh. The Duty Cycle Adjustor is an enumeration because there are 435 * multiple modes. The wide temperature sensing is another DDR5 bit represented 436 * as a key as well as an enum of fault handling. 437 */ 438 #define SPD_KEY_DDR5_BL32 "ddr5.bl32" /* key */ 439 #define SPD_KEY_DDR5_PASR "ddr5.pasr" /* key */ 440 typedef enum { 441 SPD_DCA_UNSPPORTED, 442 SPD_DCA_1_OR_2_PHASE, 443 SPD_DCA_4_PHASE 444 } spd_dca_t; 445 #define SPD_KEY_DDR5_DCA "ddr5.dca" /* uint32_t */ 446 #define SPD_KEY_DDR5_WIDE_TS "ddr5.wide-temp-sense" /* key */ 447 typedef enum { 448 SPD_FLT_BOUNDED = 1 << 0, 449 SPD_FLT_WRSUP_MR9 = 1 << 1, 450 SPD_FLT_WRSUP_MR15 = 1 << 2 451 } spd_fault_t; 452 #define SPD_KEY_DDR5_FLT "ddr5.fault-handling" /* uint32_t */ 453 454 /* 455 * DDR5 allows for non-standard core timing options. This is indicated by a 456 * single key that acts as a flag. 457 */ 458 #define SPD_KEY_DDR5_NONSTD_TIME "ddr5.non-standard-timing" /* key */ 459 460 /* 461 * DDR5 adds information about refresh management. This is split into 462 * information about general refresh management and then optional adaptive 463 * refresh management. There are three levels of adaptive refresh management 464 * titled A, B, and C. Both the general refresh management and the adaptive 465 * refresh management exist for both the primary and secondary types in 466 * asymmetrical modules. All values here are uint32_t's. 467 */ 468 typedef enum { 469 SPD_RFM_F_REQUIRED = 1 << 0, 470 SPD_RFM_F_DRFM_SUP = 1 << 1, 471 } spd_rfm_flags_t; 472 #define SPD_KEY_DDR5_RFM_FLAGS_PRI "ddr5.rfm.flags" 473 #define SPD_KEY_DDR5_RFM_RAAIMT_PRI "ddr5.rfm.raaimt" 474 #define SPD_KEY_DDR5_RFM_RAAIMT_FGR_PRI "ddr5.rfm.raaimt-fgr" 475 #define SPD_KEY_DDR5_RFM_RAAMMT_PRI "ddr5.rfm.raammt" 476 #define SPD_KEY_DDR5_RFM_RAAMMT_FGR_PRI "ddr5.rfm.raammt-fgr" 477 #define SPD_KEY_DDR5_RFM_BRC_CFG_PRI "ddr5.rfm.brc-config" 478 479 typedef enum { 480 SPD_BRC_F_LVL_2 = 1 << 0, 481 SPD_BRC_F_LVL_3 = 1 << 1, 482 SPD_BRC_F_LVL_4 = 1 << 2 483 } spd_brc_flags_t; 484 #define SPD_KEY_DDR5_RFM_BRC_SUP_PRI "ddr5.rfm.brc-level" 485 #define SPD_KEY_DDR5_RFM_RAA_DEC_PRI "ddr5.rfm.raa-dec" 486 #define SPD_KEY_DDR5_RFM_FLAGS_SEC "ddr5.rfm.sec-flags" 487 #define SPD_KEY_DDR5_RFM_RAAIMT_SEC "ddr5.rfm.sec-raaimt" 488 #define SPD_KEY_DDR5_RFM_RAAIMT_FGR_SEC "ddr5.rfm.sec-raaimt-fgr" 489 #define SPD_KEY_DDR5_RFM_RAAMMT_SEC "ddr5.rfm.sec-raammt" 490 #define SPD_KEY_DDR5_RFM_RAAMMT_FGR_SEC "ddr5.rfm.sec-raammt-fgr" 491 #define SPD_KEY_DDR5_RFM_BRC_CFG_SEC "ddr5.rfm.sec-brc-config" 492 #define SPD_KEY_DDR5_RFM_BRC_SUP_SEC "ddr5.rfm.sec-brc-level" 493 #define SPD_KEY_DDR5_RFM_RAA_DEC_SEC "ddr5.rfm.sec-raa-dec" 494 495 #define SPD_KEY_DDR5_ARFMA_FLAGS_PRI "ddr5.arfm-a.flags" 496 #define SPD_KEY_DDR5_ARFMA_RAAIMT_PRI "ddr5.arfm-a.raaimt" 497 #define SPD_KEY_DDR5_ARFMA_RAAIMT_FGR_PRI "ddr5.arfm-a.raaimt-fgr" 498 #define SPD_KEY_DDR5_ARFMA_RAAMMT_PRI "ddr5.arfm-a.raammt" 499 #define SPD_KEY_DDR5_ARFMA_RAAMMT_FGR_PRI "ddr5.arfm-a.raammt-fgr" 500 #define SPD_KEY_DDR5_ARFMA_BRC_CFG_PRI "ddr5.arfm-a.brc-config" 501 #define SPD_KEY_DDR5_ARFMA_BRC_SUP_PRI "ddr5.arfm-a.brc-level" 502 #define SPD_KEY_DDR5_ARFMA_RAA_DEC_PRI "ddr5.arfm-a.raa-dec" 503 #define SPD_KEY_DDR5_ARFMA_FLAGS_SEC "ddr5.arfm-a.sec-flags" 504 #define SPD_KEY_DDR5_ARFMA_RAAIMT_SEC "ddr5.arfm-a.sec-raaimt" 505 #define SPD_KEY_DDR5_ARFMA_RAAIMT_FGR_SEC "ddr5.arfm-a.sec-raaimt-fgr" 506 #define SPD_KEY_DDR5_ARFMA_RAAMMT_SEC "ddr5.arfm-a.sec-raammt" 507 #define SPD_KEY_DDR5_ARFMA_RAAMMT_FGR_SEC "ddr5.arfm-a.sec-raammt-fgr" 508 #define SPD_KEY_DDR5_ARFMA_BRC_CFG_SEC "ddr5.arfm-a.sec-brc-config" 509 #define SPD_KEY_DDR5_ARFMA_BRC_SUP_SEC "ddr5.arfm-a.sec-brc-level" 510 #define SPD_KEY_DDR5_ARFMA_RAA_DEC_SEC "ddr5.arfm-a.sec-raa-dec" 511 512 #define SPD_KEY_DDR5_ARFMB_FLAGS_PRI "ddr5.arfm-b.flags" 513 #define SPD_KEY_DDR5_ARFMB_RAAIMT_PRI "ddr5.arfm-b.raaimt" 514 #define SPD_KEY_DDR5_ARFMB_RAAIMT_FGR_PRI "ddr5.arfm-b.raaimt-fgr" 515 #define SPD_KEY_DDR5_ARFMB_RAAMMT_PRI "ddr5.arfm-b.raammt" 516 #define SPD_KEY_DDR5_ARFMB_RAAMMT_FGR_PRI "ddr5.arfm-b.raammt-fgr" 517 #define SPD_KEY_DDR5_ARFMB_BRC_CFG_PRI "ddr5.arfm-b.brc-config" 518 #define SPD_KEY_DDR5_ARFMB_BRC_SUP_PRI "ddr5.arfm-b.brc-level" 519 #define SPD_KEY_DDR5_ARFMB_RAA_DEC_PRI "ddr5.arfm-b.raa-dec" 520 #define SPD_KEY_DDR5_ARFMB_FLAGS_SEC "ddr5.arfm-b.sec-flags" 521 #define SPD_KEY_DDR5_ARFMB_RAAIMT_SEC "ddr5.arfm-b.sec-raaimt" 522 #define SPD_KEY_DDR5_ARFMB_RAAIMT_FGR_SEC "ddr5.arfm-b.sec-raaimt-fgr" 523 #define SPD_KEY_DDR5_ARFMB_RAAMMT_SEC "ddr5.arfm-b.sec-raammt" 524 #define SPD_KEY_DDR5_ARFMB_RAAMMT_FGR_SEC "ddr5.arfm-b.sec-raammt-fgr" 525 #define SPD_KEY_DDR5_ARFMB_BRC_CFG_SEC "ddr5.arfm-b.sec-brc-config" 526 #define SPD_KEY_DDR5_ARFMB_BRC_SUP_SEC "ddr5.arfm-b.sec-brc-level" 527 #define SPD_KEY_DDR5_ARFMB_RAA_DEC_SEC "ddr5.arfm-b.sec-raa-dec" 528 529 #define SPD_KEY_DDR5_ARFMC_FLAGS_PRI "ddr5.arfm-c.flags" 530 #define SPD_KEY_DDR5_ARFMC_RAAIMT_PRI "ddr5.arfm-c.raaimt" 531 #define SPD_KEY_DDR5_ARFMC_RAAIMT_FGR_PRI "ddr5.arfm-c.raaimt-fgr" 532 #define SPD_KEY_DDR5_ARFMC_RAAMMT_PRI "ddr5.arfm-c.raammt" 533 #define SPD_KEY_DDR5_ARFMC_RAAMMT_FGR_PRI "ddr5.arfm-c.raammt-fgr" 534 #define SPD_KEY_DDR5_ARFMC_BRC_CFG_PRI "ddr5.arfm-c.brc-config" 535 #define SPD_KEY_DDR5_ARFMC_BRC_SUP_PRI "ddr5.arfm-c.brc-level" 536 #define SPD_KEY_DDR5_ARFMC_RAA_DEC_PRI "ddr5.arfm-c.raa-dec" 537 #define SPD_KEY_DDR5_ARFMC_FLAGS_SEC "ddr5.arfm-c.sec-flags" 538 #define SPD_KEY_DDR5_ARFMC_RAAIMT_SEC "ddr5.arfm-c.sec-raaimt" 539 #define SPD_KEY_DDR5_ARFMC_RAAIMT_FGR_SEC "ddr5.arfm-c.sec-raaimt-fgr" 540 #define SPD_KEY_DDR5_ARFMC_RAAMMT_SEC "ddr5.arfm-c.sec-raammt" 541 #define SPD_KEY_DDR5_ARFMC_RAAMMT_FGR_SEC "ddr5.arfm-c.sec-raammt-fgr" 542 #define SPD_KEY_DDR5_ARFMC_BRC_CFG_SEC "ddr5.arfm-c.sec-brc-config" 543 #define SPD_KEY_DDR5_ARFMC_BRC_SUP_SEC "ddr5.arfm-c.sec-brc-level" 544 #define SPD_KEY_DDR5_ARFMC_RAA_DEC_SEC "ddr5.arfm-c.sec-raa-dec" 545 /* 546 * Module-type specific keys and values. These are often the intersection of 547 * both the DDR standard and the module type. That is, a DDR4 and DDR5 RDIMM 548 * expose some information that isn't quite the same. These often contain things 549 * that are drive strengths and slew rates. These kinds of items fall into two 550 * categories. Ones where there is a fixed resistance and one where there is a 551 * qualitative range that depends on things like the specific parts present. 552 */ 553 typedef enum { 554 SPD_DRIVE_LIGHT, 555 SPD_DRIVE_MODERATE, 556 SPD_DRIVE_STRONG, 557 SPD_DRIVE_VERY_STRONG 558 } spd_drive_t; 559 560 typedef enum { 561 SPD_SLEW_SLOW, 562 SPD_SLEW_MODERATE, 563 SPD_SLEW_FAST 564 } spd_slew_t; 565 566 /* 567 * DDR4 RDIMM drive strengths. These all use the spd_drive_t. These are all on 568 * the RCD. There is also a key for whether or not slew-control is supported. 569 */ 570 #define SPD_KEY_DDR4_RCD_SLEW "ddr4.rdimm.rcd-slew-control" /* key */ 571 #define SPD_KEY_DDR4_RCD_DS_CKE "ddr4.rdimm.cke-drive-strength" 572 #define SPD_KEY_DDR4_RCD_DS_ODT "ddr4.rdimm.odt-drive-strength" 573 #define SPD_KEY_DDR4_RCD_DS_CA "ddr4.rdimm.ca-drive-strength" 574 #define SPD_KEY_DDR4_RCD_DS_CS "ddr4.rdimm.cs-drive-strength" 575 #define SPD_KEY_DDR4_RCD_DS_Y0 "ddr4.rdimm.y0-drive-strength" 576 #define SPD_KEY_DDR4_RCD_DS_Y1 "ddr4.rdimm.y1-drive-strength" 577 #define SPD_KEY_DDR4_RCD_DS_BCOM "ddr4.lrdimm.bcom-drive-strength" 578 #define SPD_KEY_DDR4_RCD_DS_BCK "ddr4.lrdimm.bck-drive-strength" 579 580 /* 581 * DDR4 LRDIMMs specify the VrefDQ for each package rank. These are communicated 582 * in terms of the DDR4 spec which specifies them as a percentage of the actual 583 * voltage. This is always phrased in the spec as AB.CD%, so for example 60.25%. 584 * We treat this percentage as a four digit unsigned value rather than trying to 585 * play games with whether or not the value can be represented in floating 586 * point. Divide the value by 100 to get the percentage. That is, 47.60% will be 587 * encoded as 4760. All of these values are a uint32_t. 588 */ 589 #define SPD_KEY_DDR4_VREFDQ_R0 "ddr4.lrdimm.VrefDQ-rank0" 590 #define SPD_KEY_DDR4_VREFDQ_R1 "ddr4.lrdimm.VrefDQ-rank1" 591 #define SPD_KEY_DDR4_VREFDQ_R2 "ddr4.lrdimm.VrefDQ-rank2" 592 #define SPD_KEY_DDR4_VREFDQ_R3 "ddr4.lrdimm.VrefDQ-rank3" 593 #define SPD_KEY_DDR4_VREFDQ_DB "ddr4.lrdimm.VrefDQ-db" 594 595 /* 596 * DDR4 LRDIMMs define the data buffer drive strength and termination in terms 597 * of various data rate ranges. Specifically (0, 1866], (1866, 2400], and (2400, 598 * 3200]. All of these values are measured in terms of Ohms. As such, all of 599 * these values are an array of three uint32_t's whose values correspond to each 600 * of those ranges. We define a few additional values for these to represent 601 * cases where they are disabled or high-impedance. 602 */ 603 #define SPD_KEY_DDR4_TERM_DISABLED 0 604 #define SPD_KEY_DDR4_TERM_HIZ UINT32_MAX 605 #define SPD_KEY_DDR4_MDQ_RTT "ddr4.lrdimm.mdq-read-termination" 606 #define SPD_KEY_DDR4_MDQ_DS "ddr4.lrdimm.mdq-drive-strength" 607 #define SPD_KEY_DDR4_DRAM_DS "ddr4.lrdimm.dram-drive-strength" 608 #define SPD_KEY_DDR4_RTT_WR "ddr4.lrdimm.odt-read-termination-wr" 609 #define SPD_KEY_DDR4_RTT_NOM "ddr4.lrdimm.odt-read-termination-nom" 610 #define SPD_KEY_DDR4_RTT_PARK_R0 "ddr4.lrdimm.odt-r0_1-rtt-park" 611 #define SPD_KEY_DDR4_RTT_PARK_R2 "ddr4.lrdimm.odt-r2_3-rtt-park" 612 613 /* 614 * The last DDR4 LRDIMM specific component is whether or not the data buffer's 615 * gain and decision feedback equalization are supported. These both are keys. 616 */ 617 #define SPD_KEY_DDR4_DB_GAIN "ddr4.lrdimm.db-gain-adjustment" 618 #define SPD_KEY_DDR4_DB_DFE "ddr4.lrdimm.decision-feedback-eq" 619 620 /* 621 * DDR5 RDIMMs and LRDIMMs have specific enables for groups of pins. There are 622 * then 623 * differential impedence measurements. These are all in Ohms. Separately there 624 * are slew rates, those use the spd_slew_t. Because these use different units 625 * between DDR4 and DDR5, we treat them as different keys. 626 */ 627 #define SPD_KEY_DDR5_RCD_QACK_EN "ddr5.rdimm.rcd-qack-enabled" 628 #define SPD_KEY_DDR5_RCD_QBCK_EN "ddr5.rdimm.rcd-qbck-enabled" 629 #define SPD_KEY_DDR5_RCD_QCCK_EN "ddr5.rdimm.rcd-qcck-enabled" 630 #define SPD_KEY_DDR5_RCD_QDCK_EN "ddr5.rdimm.rcd-qdck-enabled" 631 #define SPD_KEY_DDR5_RCD_BCK_EN "ddr5.rdimm.rcd-bck-enabled" 632 #define SPD_KEY_DDR5_RCD_QACA_EN "ddr5.rdimm.rcd-qaca-enabled" 633 #define SPD_KEY_DDR5_RCD_QBCA_EN "ddr5.rdimm.rcd-qbca-enabled" 634 #define SPD_KEY_DDR5_RCD_DCS1_EN "ddr5.rdimm.rcd-dcs1-enabled" 635 #define SPD_KEY_DDR5_RCD_QxCA13_EN "ddr5.rdimm.rcd-qxca13-enabled" 636 #define SPD_KEY_DDR5_RCD_QACS_EN "ddr5.rdimm.rcd-qacs-enabled" 637 #define SPD_KEY_DDR5_RCD_QBCS_EN "ddr5.rdimm.rcd-qbcs-enabled" 638 639 /* Impedence measurements are uint32_t's in Ohms */ 640 #define SPD_KEY_DDR5_RCD_QACK_IMP "ddr5.rdimm.rcd-qack-impedance" 641 #define SPD_KEY_DDR5_RCD_QBCK_IMP "ddr5.rdimm.rcd-qbck-impedance" 642 #define SPD_KEY_DDR5_RCD_QCCK_IMP "ddr5.rdimm.rcd-qcck-impedance" 643 #define SPD_KEY_DDR5_RCD_QDCK_IMP "ddr5.rdimm.rcd-qdck-impedance" 644 #define SPD_KEY_DDR5_RCD_CS_IMP "ddr5.rdimm.rcd-cs-impedance" 645 #define SPD_KEY_DDR5_RCD_CA_IMP "ddr5.rdimm.rcd-ca-impedance" 646 647 /* Slew rates use the spd_rate_t encoded as a uint32_t */ 648 #define SPD_KEY_DDR5_RCD_QCK_SLEW "ddr5.rdimm.rcd-qck-slew" 649 #define SPD_KEY_DDR5_RCD_QCA_SLEW "ddr5.rdimm.rcd-qck-slew" 650 #define SPD_KEY_DDR5_RCD_QCS_SLEW "ddr5.rdimm.rcd-qcs-slew" 651 652 /* 653 * These are all speific to DDR5 LRDIMMs. The values are the same as above. In 654 * particular, the DWS RTT values are also in Ohms. If RTT termination is 655 * disabled then the key will not be present. 656 */ 657 #define SPD_KEY_DDR5_RCD_BCS_EN "ddr5.lrdimm.rcd-bcs-enabled" /* key */ 658 #define SPD_KEY_DDR5_RCD_BCOM_IMP "ddr5.lrdimm.rcd-bcom-impedance" 659 #define SPD_KEY_DDR5_RCD_BCK_IMP "ddr5.lrdimm.rcd-bck-impedance" 660 #define SPD_KEY_DDR5_RCD_RTT_TERM "ddr5.lrdimm.rcd-dqs-rtt" 661 #define SPD_KEY_DDR5_RCD_BCOM_SLEW "ddr5.lrdimm.rcd-bcom-slew" 662 #define SPD_KEY_DDR5_RCD_BCK_SLEW "ddr5.lrdimm.rcd-bck-slew" 663 664 665 /* 666 * Module Properties. These are items that generally relate to the module as a 667 * whole. 668 */ 669 670 /* 671 * Connection Mapping. In DDR4 there is the ability to remap groups of pins from 672 * the connector to the various package SDRAMs. Every 4 bits can be remapped to 673 * either another upper or lower nibble in a package. Separately bits can also 674 * be flipped between packages. These exist for all 64-bits of DQ and 8 bits of 675 * CBs. If mirroring is set, then a key will be added for that pin group. For 676 * each pin group, the mapping to a specific type of rewriting will be done. We 677 * conventionally use 0, 1, 2, and 3 as the lower nibble and 4, 5, 6, 7 as the 678 * upper nibble, though the actual pins will vary based on where they are. 679 */ 680 #define SPD_KEY_DDR4_MAP_DQ0 "module.dq0-map" /* uint32_t [4] */ 681 #define SPD_KEY_DDR4_MAP_DQ4 "module.dq4-map" /* uint32_t [4] */ 682 #define SPD_KEY_DDR4_MAP_DQ8 "module.dq8-map" /* uint32_t [4] */ 683 #define SPD_KEY_DDR4_MAP_DQ12 "module.dq12-map" /* uint32_t [4] */ 684 #define SPD_KEY_DDR4_MAP_DQ16 "module.dq16-map" /* uint32_t [4] */ 685 #define SPD_KEY_DDR4_MAP_DQ20 "module.dq20-map" /* uint32_t [4] */ 686 #define SPD_KEY_DDR4_MAP_DQ24 "module.dq24-map" /* uint32_t [4] */ 687 #define SPD_KEY_DDR4_MAP_DQ28 "module.dq28-map" /* uint32_t [4] */ 688 #define SPD_KEY_DDR4_MAP_DQ32 "module.dq32-map" /* uint32_t [4] */ 689 #define SPD_KEY_DDR4_MAP_DQ36 "module.dq36-map" /* uint36_t [4] */ 690 #define SPD_KEY_DDR4_MAP_DQ40 "module.dq40-map" /* uint32_t [4] */ 691 #define SPD_KEY_DDR4_MAP_DQ44 "module.dq44-map" /* uint32_t [4] */ 692 #define SPD_KEY_DDR4_MAP_DQ48 "module.dq48-map" /* uint32_t [4] */ 693 #define SPD_KEY_DDR4_MAP_DQ52 "module.dq52-map" /* uint32_t [4] */ 694 #define SPD_KEY_DDR4_MAP_DQ56 "module.dq56-map" /* uint32_t [4] */ 695 #define SPD_KEY_DDR4_MAP_DQ60 "module.dq60-map" /* uint32_t [4] */ 696 #define SPD_KEY_DDR4_MAP_CB0 "module.dq0-map" /* uint32_t [4] */ 697 #define SPD_KEY_DDR4_MAP_CB4 "module.dq4-map" /* uint32_t [4] */ 698 699 /* 700 * In addition, there is module level mapping in DDR4 that is used to indicate 701 * that odd ranks are mirrored. This is between the edge connector and the DRAM 702 * itself. We only add a key when it is mirrored. 703 */ 704 #define SPD_KEY_DDR4_MIRROR "module.edge-odd-mirror" /* key */ 705 706 /* 707 * Present devices. Modules often have multiple additional types of devices 708 * present like temperature sensors, voltage regulators, registers, etc. The 709 * following key indicates what all is present on this DIMM. Depending on the 710 * DDR revision, we will then have additional keys with its ID, revision, name, 711 * and compliant type. In a few cases we will define the type and presence based 712 * on information. For example, DDR4 only allows a single type of temperature 713 * sensor or SPD device. Even though we don't know the manufacturer, we will 714 * still note this. 715 * 716 * Each of these items will have four keys. One for the manufacturer ID, one for 717 * their string name, one for the device type, and one for the revision. Note, 718 * while TS1 and TS2 are both flags in DDR5, they share common manufacturer 719 * information, which is why there is only one entry here. 720 * 721 * For each device type there is a separate enum with supported types of devices 722 * that can be present for these. 723 */ 724 typedef enum { 725 SPD_DEVICE_TEMP_1 = 1 << 0, 726 SPD_DEVICE_TEMP_2 = 1 << 1, 727 SPD_DEVICE_HS = 1 << 2, 728 SPD_DEVICE_PMIC_0 = 1 << 3, 729 SPD_DEVICE_PMIC_1 = 1 << 4, 730 SPD_DEVICE_PMIC_2 = 1 << 5, 731 SPD_DEVICE_CD = 1 << 6, 732 SPD_DEVICE_RCD = 1 << 7, 733 SPD_DEVICE_DB = 1 << 8, 734 SPD_DEVICE_MRCD = 1 << 9, 735 SPD_DEVICE_MDB = 1 << 10, 736 SPD_DEVICE_DMB = 1 << 11, 737 SPD_DEVICE_SPD = 1 << 12 738 } spd_device_t; 739 #define SPD_KEY_DEVS "module.devices" /* uint32_t */ 740 741 typedef enum { 742 /* DDR3 */ 743 SPD_TEMP_T_TSE2002, 744 /* DDR4 and LPDDR4 */ 745 SPD_TEMP_T_TSE2004av, 746 /* DDR5 */ 747 SPD_TEMP_T_TS5111, 748 SPD_TEMP_T_TS5110 749 } spd_temp_type_t; 750 751 typedef enum { 752 /* DDR5 */ 753 SPD_PMIC_T_PMIC5000, 754 SPD_PMIC_T_PMIC5010, 755 SPD_PMIC_T_PMIC5100 756 } spd_pmic_type_t; 757 758 typedef enum { 759 /* DDR5 */ 760 SPD_CD_T_DDR5CK01 761 } spd_cd_type_t; 762 763 typedef enum { 764 /* DDR3 */ 765 SPD_RCD_T_SSTE32882, 766 /* DDR4 */ 767 SPD_RCD_T_DDR4RCD01, 768 SPD_RCD_T_DDR4RCD02, 769 /* DDR5 */ 770 SPD_RCD_T_DDR5RCD01, 771 SPD_RCD_T_DDR5RCD02, 772 SPD_RCD_T_DDR5RCD03 773 } spd_rcd_type_t; 774 775 typedef enum { 776 /* DDR4 */ 777 SPD_DB_T_DDR4DB01, 778 SPD_DB_T_DDR4DB02, 779 /* DDR5 */ 780 SPD_DB_T_DDR5DB01, 781 SPD_DB_T_DDR5DB02 782 } spd_db_type_t; 783 784 typedef enum { 785 /* DDR5 */ 786 SPD_MRCD_T_DDR5MRCD01 787 } spd_mrcd_type_t; 788 789 typedef enum { 790 /* DDR5 */ 791 SPD_MDB_T_DDR5MDB01 792 } spd_mdb_type_t; 793 794 typedef enum { 795 /* DDR5 */ 796 SPD_DMB_T_DMB5011 797 } spd_dmb_type_t; 798 799 typedef enum { 800 /* DDR4 */ 801 SPD_SPD_T_EE1004, 802 /* DDR5 */ 803 SPD_SPD_T_SPD5118, 804 SPD_SPD_T_ESPD5216 805 } spd_spd_type_t; 806 807 #define SPD_KEY_DEV_TEMP_MFG "module.temp.mfg-id" /* uint32_t [2] */ 808 #define SPD_KEY_DEV_TEMP_MFG_NAME "module.temp.mfg-name" /* string */ 809 #define SPD_KEY_DEV_TEMP_TYPE "module.temp.type" /* uint32_t */ 810 #define SPD_KEY_DEV_TEMP_REV "module.temp.revision" /* string */ 811 812 #define SPD_KEY_DEV_PMIC0_MFG "module.pmic0.mfg-id" /* uint32_t [2] */ 813 #define SPD_KEY_DEV_PMIC0_MFG_NAME "module.pmic0.mfg-name" /* string */ 814 #define SPD_KEY_DEV_PMIC0_TYPE "module.pmic0.type" /* uint32_t */ 815 #define SPD_KEY_DEV_PMIC0_REV "module.pmic0.revision" /* string */ 816 #define SPD_KEY_DEV_PMIC1_MFG "module.pmic1.mfg-id" /* uint32_t [2] */ 817 #define SPD_KEY_DEV_PMIC1_MFG_NAME "module.pmic1.mfg-name" /* string */ 818 #define SPD_KEY_DEV_PMIC1_TYPE "module.pmic1.type" /* uint32_t */ 819 #define SPD_KEY_DEV_PMIC1_REV "module.pmic1.revision" /* string */ 820 #define SPD_KEY_DEV_PMIC2_MFG "module.pmic2.mfg-id" /* uint32_t [2] */ 821 #define SPD_KEY_DEV_PMIC2_MFG_NAME "module.pmic2.mfg-name" /* string */ 822 #define SPD_KEY_DEV_PMIC2_TYPE "module.pmic2.type" /* uint32_t */ 823 #define SPD_KEY_DEV_PMIC2_REV "module.pmic2.revision" /* string */ 824 825 #define SPD_KEY_DEV_CD_MFG "module.cd.mfg-id" /* uint32_t [2] */ 826 #define SPD_KEY_DEV_CD_MFG_NAME "module.cd.mfg-name" /* string */ 827 #define SPD_KEY_DEV_CD_TYPE "module.cd.type" /* uint32_t */ 828 #define SPD_KEY_DEV_CD_REV "module.cd.revision" /* string */ 829 830 #define SPD_KEY_DEV_RCD_MFG "module.rcd.mfg-id" /* uint32_t [2] */ 831 #define SPD_KEY_DEV_RCD_MFG_NAME "module.rcd.mfg-name" /* string */ 832 #define SPD_KEY_DEV_RCD_TYPE "module.rcd.type" /* uint32_t */ 833 #define SPD_KEY_DEV_RCD_REV "module.rcd.revision" /* string */ 834 835 #define SPD_KEY_DEV_DB_MFG "module.db.mfg-id" /* uint32_t [2] */ 836 #define SPD_KEY_DEV_DB_MFG_NAME "module.db.mfg-name" /* string */ 837 #define SPD_KEY_DEV_DB_TYPE "module.db.type" /* uint32_t */ 838 #define SPD_KEY_DEV_DB_REV "module.db.revision" /* string */ 839 840 #define SPD_KEY_DEV_MRCD_MFG "module.mrcd.mfg-id" /* uint32_t [2] */ 841 #define SPD_KEY_DEV_MRCD_MFG_NAME "module.mrcd.mfg-name" /* string */ 842 #define SPD_KEY_DEV_MRCD_TYPE "module.mrcd.type" /* uint32_t */ 843 #define SPD_KEY_DEV_MRCD_REV "module.mrcd.revision" /* string */ 844 845 #define SPD_KEY_DEV_MDB_MFG "module.mdb.mfg-id" /* uint32_t [2] */ 846 #define SPD_KEY_DEV_MDB_MFG_NAME "module.mdb.mfg-name" /* string */ 847 #define SPD_KEY_DEV_MDB_TYPE "module.mdb.type" /* uint32_t */ 848 #define SPD_KEY_DEV_MDB_REV "module.mdb.revision" /* string */ 849 850 #define SPD_KEY_DEV_DMB_MFG "module.dmb.mfg-id" /* uint32_t [2] */ 851 #define SPD_KEY_DEV_DMB_MFG_NAME "module.dmb.mfg-name" /* string */ 852 #define SPD_KEY_DEV_DMB_TYPE "module.dmb.type" /* uint32_t */ 853 #define SPD_KEY_DEV_DMB_REV "module.dmb.revision" /* string */ 854 855 #define SPD_KEY_DEV_SPD_MFG "module.spd.mfg-id" /* uint32_t [2] */ 856 #define SPD_KEY_DEV_SPD_MFG_NAME "module.spd.mfg-name" /* string */ 857 #define SPD_KEY_DEV_SPD_TYPE "module.spd.type" /* uint32_t */ 858 #define SPD_KEY_DEV_SPD_REV "module.spd.revision" /* string */ 859 860 /* 861 * Module physical dimensions. DRAM modules provide information about their 862 * height and their front and back thicknesses. All values are in millimeters. 863 * In general, values are defined as 1 mm ranges in the form such as 18mm < 864 * height <= 19mm or 2mm < thickness <= 3mm. As such in all these ranges we 865 * encode it as the less than or equal to side of the thickness or height. 866 * 867 * However, at the extremes of thickness and height, it can be arbitrary. The 868 * minimum height can be any value <= 15mm and the maximum is just > 45mm. 869 * Similarly the maximum thickness is just any value greater than 15mm. For 870 * these values, we define aliases that can be used to indicate we're in these 871 * conditions for the height and thickness, allowing this to otherwise be the 872 * common well understood value. 873 */ 874 #define SPD_MOD_HEIGHT_LT15MM 15 875 #define SPD_MOD_HEIGHT_GT45MM 46 876 #define SPD_KEY_MOD_HEIGHT "module.height" /* uint32_t */ 877 #define SPD_MOD_THICK_GT15MM 16 878 #define SPD_KEY_MOD_FRONT_THICK "module.front-thickness" /* uint32_t */ 879 #define SPD_KEY_MOD_BACK_THICK "module.back-thickness" /* uint32_t */ 880 881 /* 882 * This is the number of rows of DRAM dies on the module. In addition, DDR4 883 * provides the number of registers present on the device. This is not present 884 * in DDR5. 885 */ 886 #define SPD_KEY_MOD_NROWS "module.dram-die-rows" /* uint32_t */ 887 #define SPD_KEY_MOD_NREGS "module.total-registers" /* uint32_t */ 888 889 /* 890 * Operating temperature ranges. These ranges are defined by JEDEC. The code can 891 * be translated with libjedec_temp_range() to transform it into a pair of 892 * values. 893 */ 894 895 #define SPD_KEY_MOD_OPER_TEMP "module.operating-temperature" /* uint32_t */ 896 897 /* 898 * Module reference card and design revision. JEDEC provides various reference 899 * designs for modules and revisions of those. 900 */ 901 #define SPD_KEY_MOD_REF_DESIGN "module.reference-design" /* string */ 902 #define SPD_KEY_MOD_DESIGN_REV "module.design-revision" /* uint32_t */ 903 904 /* 905 * Manufacturing Section. These keys are present if manufacturing related 906 * information is made available. This space is not DIMM-revision specific. All 907 * fields are defined in DDR4 and DDR5. Note, the SPD_KEY_MFG_DRAM_STEP is 908 * optional and therefore an invalid value will result in this not being 909 * present. 910 */ 911 #define SPD_KEY_MFG_MOD_MFG_ID "mfg.module-mfg-id" /* uint32[2] */ 912 #define SPD_KEY_MFG_MOD_MFG_NAME "mfg.module-mfg-name" /* string */ 913 #define SPD_KEY_MFG_DRAM_MFG_ID "mfg.dram-mfg-id" /* uint32[2] */ 914 #define SPD_KEY_MFG_DRAM_MFG_NAME "mfg.dram-mfg-name" /* string */ 915 #define SPD_KEY_MFG_MOD_LOC_ID "mfg.module-loc-id" /* uint32 */ 916 #define SPD_KEY_MFG_MOD_YEAR "mfg.module-year" /* string */ 917 #define SPD_KEY_MFG_MOD_WEEK "mfg.module-week" /* string */ 918 #define SPD_KEY_MFG_MOD_PN "mfg.module-pn" /* string */ 919 #define SPD_KEY_MFG_MOD_SN "mfg.module-sn" /* string */ 920 #define SPD_KEY_MFG_MOD_REV "mfg.module-rev" /* string */ 921 #define SPD_KEY_MFG_DRAM_STEP "mfg.dram-step" /* string */ 922 923 /* 924 * The errors nvlist_t is designed such that it is a nested nvlist_t in the 925 * returned data. Each key in that nvlist_t corresponds to a key that we would 926 * otherwise produce. Each key is an nvlist_t that has two keys, a 'code' and a 927 * 'message'. 928 * 929 * There is currently an additional top-level special key. This is the 930 * 'incomplete' key. When data is too short to process an entry, rather than 931 * flag every possible missing key (as most times the consumer will know the 932 * amount of data they have), for the time being we will insert a single 933 * incomplete key with a uint32_t whose value indicates the starting offset of 934 * the key that we could not process. Note, this may not be the first byte that 935 * was missing (if we had 100 bytes and a 20 byte key at offset 90, we would 936 * insert 90). 937 */ 938 typedef enum { 939 /* 940 * Indicates that the error occurred because we could not translate a 941 * given piece of information. For example, a value that we didn't know 942 * or a failure to look up something in a string table. 943 */ 944 SPD_ERROR_NO_XLATE, 945 /* 946 * This indicates that we encountered an non-ASCII or unprintable 947 * character in an SPD string which should not be allowed per se. 948 */ 949 SPD_ERROR_UNPRINT, 950 /* 951 * This indicates that there was no data for a given key. For example, a 952 * string that was all padded spaces. 953 */ 954 SPD_ERROR_NO_DATA, 955 /* 956 * Indicates that some kind of internal error occurred. 957 */ 958 SPD_ERROR_INTERNAL, 959 /* 960 * This indicates that there's something suspicious or weird to us about 961 * the data in question. The most common case is a bad CRC. 962 */ 963 SPD_ERROR_BAD_DATA 964 } spd_error_kind_t; 965 #define SPD_KEY_INCOMPLETE "incomplete" /* uint32_t */ 966 #define SPD_KEY_ERRS "errors" /* nvlist_t */ 967 #define SPD_KEY_ERRS_CODE "code" /* uint32_t */ 968 #define SPD_KEY_ERRS_MSG "message" /* string */ 969 970 #ifdef __cplusplus 971 } 972 #endif 973 974 #endif /* _LIBJEDEC_H */ 975