27c478bdstevel@tonic-gate * CDDL HEADER START
37c478bdstevel@tonic-gate *
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207c478bdstevel@tonic-gate * CDDL HEADER END
217c478bdstevel@tonic-gate */
237c478bdstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
247c478bdstevel@tonic-gate * Use is subject to license terms.
257c478bdstevel@tonic-gate */
277c478bdstevel@tonic-gate#ifndef	_DT_PCB_H
287c478bdstevel@tonic-gate#define	_DT_PCB_H
307c478bdstevel@tonic-gate#pragma ident	"%Z%%M%	%I%	%E% SMI"
327c478bdstevel@tonic-gate#include <dtrace.h>
337c478bdstevel@tonic-gate#include <setjmp.h>
347c478bdstevel@tonic-gate#include <stdio.h>
367c478bdstevel@tonic-gate#ifdef	__cplusplus
377c478bdstevel@tonic-gateextern "C" {
407c478bdstevel@tonic-gate#include <dt_parser.h>
417c478bdstevel@tonic-gate#include <dt_regset.h>
427c478bdstevel@tonic-gate#include <dt_inttab.h>
437c478bdstevel@tonic-gate#include <dt_strtab.h>
447c478bdstevel@tonic-gate#include <dt_decl.h>
457c478bdstevel@tonic-gate#include <dt_as.h>
477c478bdstevel@tonic-gatetypedef struct dt_pcb {
487c478bdstevel@tonic-gate	dtrace_hdl_t *pcb_hdl;	/* pointer to library handle */
497c478bdstevel@tonic-gate	struct dt_pcb *pcb_prev; /* pointer to previous pcb in stack */
507c478bdstevel@tonic-gate	FILE *pcb_fileptr;	/* pointer to input file (or NULL) */
517c478bdstevel@tonic-gate	char *pcb_filetag;	/* optional file name string (or NULL) */
527c478bdstevel@tonic-gate	const char *pcb_string;	/* pointer to input string (or NULL) */
537c478bdstevel@tonic-gate	const char *pcb_strptr;	/* pointer to input position */
547c478bdstevel@tonic-gate	size_t pcb_strlen;	/* length of pcb_string */
557c478bdstevel@tonic-gate	int pcb_sargc;		/* number of script arguments (if any) */
567c478bdstevel@tonic-gate	char *const *pcb_sargv;	/* script argument strings (if any) */
577c478bdstevel@tonic-gate	ushort_t *pcb_sflagv;	/* script argument flags (DT_IDFLG_* bits) */
587c478bdstevel@tonic-gate	dt_scope_t pcb_dstack;	/* declaration processing stack */
597c478bdstevel@tonic-gate	dt_node_t *pcb_list;	/* list of allocated parse tree nodes */
607c478bdstevel@tonic-gate	dt_node_t *pcb_hold;	/* parse tree nodes on hold until end of defn */
617c478bdstevel@tonic-gate	dt_node_t *pcb_root;	/* root of current parse tree */
627c478bdstevel@tonic-gate	dt_idstack_t pcb_globals; /* stack of global identifier hash tables */
637c478bdstevel@tonic-gate	dt_idhash_t *pcb_locals; /* current hash table of local identifiers */
647c478bdstevel@tonic-gate	dt_idhash_t *pcb_idents; /* current hash table of ambiguous idents */
657c478bdstevel@tonic-gate	dt_idhash_t *pcb_pragmas; /* current hash table of pending pragmas */
667c478bdstevel@tonic-gate	dt_inttab_t *pcb_inttab; /* integer table for constant references */
677c478bdstevel@tonic-gate	dt_strtab_t *pcb_strtab; /* string table for string references */
687c478bdstevel@tonic-gate	dt_regset_t *pcb_regs;	/* register set for code generation */
697c478bdstevel@tonic-gate	dt_irlist_t pcb_ir;	/* list of unrelocated IR instructions */
701a7c1b7mws	uint_t pcb_asvidx;	/* assembler vartab index (see dt_as.c) */
711a7c1b7mws	ulong_t **pcb_asxrefs;	/* assembler imported xlators (see dt_as.c) */
721a7c1b7mws	uint_t pcb_asxreflen;	/* assembler xlator map length (see dt_as.c) */
737c478bdstevel@tonic-gate	const dtrace_probedesc_t *pcb_pdesc; /* probedesc for current context */
747c478bdstevel@tonic-gate	struct dt_probe *pcb_probe; /* probe associated with current context */
757c478bdstevel@tonic-gate	dtrace_probeinfo_t pcb_pinfo; /* info associated with current context */
767c478bdstevel@tonic-gate	dtrace_attribute_t pcb_amin; /* stability minimum for compilation */
777c478bdstevel@tonic-gate	dt_node_t *pcb_dret;	/* node containing return type for assembler */
787c478bdstevel@tonic-gate	dtrace_difo_t *pcb_difo; /* intermediate DIF object made by assembler */
797c478bdstevel@tonic-gate	dtrace_prog_t *pcb_prog; /* intermediate program made by compiler */
807c478bdstevel@tonic-gate	dtrace_stmtdesc_t *pcb_stmt; /* intermediate stmt made by compiler */
817c478bdstevel@tonic-gate	dtrace_ecbdesc_t *pcb_ecbdesc; /* intermediate ecbdesc made by cmplr */
827c478bdstevel@tonic-gate	jmp_buf pcb_jmpbuf;	/* setjmp(3C) buffer for error return */
837c478bdstevel@tonic-gate	const char *pcb_region;	/* optional region name for yyerror() suffix */
847c478bdstevel@tonic-gate	dtrace_probespec_t pcb_pspec; /* probe description evaluation context */
857c478bdstevel@tonic-gate	uint_t pcb_cflags;	/* optional compilation flags (see dtrace.h) */
867c478bdstevel@tonic-gate	uint_t pcb_idepth;	/* preprocessor #include nesting depth */
877c478bdstevel@tonic-gate	yystate_t pcb_yystate;	/* lex/yacc parsing state (see yybegin()) */
887c478bdstevel@tonic-gate	int pcb_context;	/* yyparse() rules context (DT_CTX_* value) */
897c478bdstevel@tonic-gate	int pcb_token;		/* token to be returned by yylex() (if != 0) */
907c478bdstevel@tonic-gate	int pcb_cstate;		/* state to be restored by lexer at state end */
917c478bdstevel@tonic-gate	int pcb_braces;		/* number of open curly braces in lexer */
927c478bdstevel@tonic-gate	int pcb_brackets;	/* number of open square brackets in lexer */
937c478bdstevel@tonic-gate	int pcb_parens;		/* number of open parentheses in lexer */
947c478bdstevel@tonic-gate} dt_pcb_t;
967c478bdstevel@tonic-gateextern void dt_pcb_push(dtrace_hdl_t *, dt_pcb_t *);
977c478bdstevel@tonic-gateextern void dt_pcb_pop(dtrace_hdl_t *, int);
997c478bdstevel@tonic-gate#ifdef	__cplusplus
1037c478bdstevel@tonic-gate#endif	/* _DT_PCB_H */