1a2bb96e7Sjmcp /* 2a2bb96e7Sjmcp * CDDL HEADER START 3a2bb96e7Sjmcp * 4a2bb96e7Sjmcp * The contents of this file are subject to the terms of the 5a2bb96e7Sjmcp * Common Development and Distribution License (the "License"). 6a2bb96e7Sjmcp * You may not use this file except in compliance with the License. 7a2bb96e7Sjmcp * 8a2bb96e7Sjmcp * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9a2bb96e7Sjmcp * or http://www.opensolaris.org/os/licensing. 10a2bb96e7Sjmcp * See the License for the specific language governing permissions 11a2bb96e7Sjmcp * and limitations under the License. 12a2bb96e7Sjmcp * 13a2bb96e7Sjmcp * When distributing Covered Code, include this CDDL HEADER in each 14a2bb96e7Sjmcp * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15a2bb96e7Sjmcp * If applicable, add the following below this CDDL HEADER, with the 16a2bb96e7Sjmcp * fields enclosed by brackets "[]" replaced with your own identifying 17a2bb96e7Sjmcp * information: Portions Copyright [yyyy] [name of copyright owner] 18a2bb96e7Sjmcp * 19a2bb96e7Sjmcp * CDDL HEADER END 20a2bb96e7Sjmcp */ 21a2bb96e7Sjmcp 22a2bb96e7Sjmcp /* 23a2bb96e7Sjmcp * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24a2bb96e7Sjmcp * Use is subject to license terms. 25a2bb96e7Sjmcp */ 26a2bb96e7Sjmcp 27a2bb96e7Sjmcp /* 28a2bb96e7Sjmcp * Copyright 2007 Jason King. All rights reserved. 29a2bb96e7Sjmcp * Use is subject to license terms. 30a2bb96e7Sjmcp */ 31a2bb96e7Sjmcp 32a2bb96e7Sjmcp #ifndef _DIS_SPARC_FMT_H 33a2bb96e7Sjmcp #define _DIS_SPARC_FMT_H 34a2bb96e7Sjmcp 35a2bb96e7Sjmcp #ifdef __cplusplus 36a2bb96e7Sjmcp extern "C" { 37a2bb96e7Sjmcp #endif 38a2bb96e7Sjmcp 39a2bb96e7Sjmcp #include <sys/types.h> 40a2bb96e7Sjmcp #include "libdisasm.h" 41a2bb96e7Sjmcp #include "dis_sparc.h" 42a2bb96e7Sjmcp 43a2bb96e7Sjmcp /* which set of registers are used with an instruction */ 44a2bb96e7Sjmcp #define REG_INT 0x00 /* regular integer registers */ 45a2bb96e7Sjmcp #define REG_FP 0x01 /* single-precision fp registers */ 46a2bb96e7Sjmcp #define REG_FPD 0x02 /* double-precision fp registers */ 47a2bb96e7Sjmcp #define REG_FPQ 0x03 /* quad-precision fp registers */ 48a2bb96e7Sjmcp #define REG_CP 0x04 /* coprocessor registers (v8) */ 49a2bb96e7Sjmcp #define REG_ICC 0x05 /* %icc / % xcc */ 50a2bb96e7Sjmcp #define REG_FCC 0x06 /* %fccn */ 51a2bb96e7Sjmcp #define REG_FSR 0x07 /* %fsr */ 52a2bb96e7Sjmcp #define REG_CSR 0x08 /* %csr */ 53a2bb96e7Sjmcp #define REG_CQ 0x09 /* %cq */ 54a2bb96e7Sjmcp #define REG_NONE 0x0a /* no registers */ 55a2bb96e7Sjmcp 56a2bb96e7Sjmcp /* the size fo the displacement for branches */ 57a2bb96e7Sjmcp #define DISP22 0x00 58a2bb96e7Sjmcp #define DISP19 0x01 59a2bb96e7Sjmcp #define DISP16 0x02 60a2bb96e7Sjmcp #define CONST22 0x03 61a2bb96e7Sjmcp 62a2bb96e7Sjmcp /* get/set the register set name for the rd field of an instruction */ 63a2bb96e7Sjmcp #define FLG_RD(x) (x) 64a2bb96e7Sjmcp #define FLG_RD_VAL(x) (x & 0xfL) 65a2bb96e7Sjmcp 66a2bb96e7Sjmcp #define FLG_STORE (0x1L << 24) /* the instruction is not a load */ 67a2bb96e7Sjmcp #define FLG_ASI (0x2L << 24) /* the load/store includes an asi value */ 68a2bb96e7Sjmcp 69a2bb96e7Sjmcp 70a2bb96e7Sjmcp /* flags for ALU instructions */ 71a2bb96e7Sjmcp 72a2bb96e7Sjmcp /* set/get register set name for 1st argument position */ 73a2bb96e7Sjmcp #define FLG_P1(x) (x << 8) 74a2bb96e7Sjmcp #define FLG_P1_VAL(x) ((x >> 8) & 0xfL) 75a2bb96e7Sjmcp 76a2bb96e7Sjmcp /* get/set reg set for 2nd argument position */ 77a2bb96e7Sjmcp #define FLG_P2(x) (x << 4) 78a2bb96e7Sjmcp #define FLG_P2_VAL(x) ((x >> 4) & 0xfL) 79a2bb96e7Sjmcp 80a2bb96e7Sjmcp /* get/set for 3rd argument position */ 81a2bb96e7Sjmcp #define FLG_P3(x) (x) 82a2bb96e7Sjmcp #define FLG_P3_VAL(x) (x & 0xfL) 83a2bb96e7Sjmcp 84a2bb96e7Sjmcp /* set if the arguments do not contain immediate values */ 85a2bb96e7Sjmcp #define FLG_NOIMM (0x01L << 24) 86a2bb96e7Sjmcp 87a2bb96e7Sjmcp 88a2bb96e7Sjmcp 89a2bb96e7Sjmcp /* flags for branch instructions */ 90a2bb96e7Sjmcp 91a2bb96e7Sjmcp /* has branch prediction */ 92a2bb96e7Sjmcp #define FLG_PRED (0x01L << 24) 93a2bb96e7Sjmcp 94a2bb96e7Sjmcp /* get/set condition code register set -- usually REG_NONE */ 95a2bb96e7Sjmcp #define FLG_RS1(x) (x) 96a2bb96e7Sjmcp #define FLG_RS1_VAL(x) (x & 0xfL) 97a2bb96e7Sjmcp 98a2bb96e7Sjmcp /* get/set displacement size */ 99a2bb96e7Sjmcp #define FLG_DISP(x) (x << 4L) 100a2bb96e7Sjmcp #define FLG_DISP_VAL(x) ((x >> 4L) & 0x0fL) 101a2bb96e7Sjmcp 102a2bb96e7Sjmcp 103a2bb96e7Sjmcp int fmt_call(dis_handle_t *, uint32_t, const inst_t *, int); 104a2bb96e7Sjmcp int fmt_ls(dis_handle_t *, uint32_t, const inst_t *, int); 105a2bb96e7Sjmcp int fmt_alu(dis_handle_t *, uint32_t, const inst_t *, int); 106a2bb96e7Sjmcp int fmt_branch(dis_handle_t *, uint32_t, const inst_t *, int); 107a2bb96e7Sjmcp int fmt_sethi(dis_handle_t *, uint32_t, const inst_t *, int); 108a2bb96e7Sjmcp int fmt_fpop1(dis_handle_t *, uint32_t, const inst_t *, int); 109a2bb96e7Sjmcp int fmt_fpop2(dis_handle_t *, uint32_t, const inst_t *, int); 110a2bb96e7Sjmcp int fmt_vis(dis_handle_t *, uint32_t, const inst_t *, int); 111a2bb96e7Sjmcp int fmt_trap(dis_handle_t *, uint32_t, const inst_t *, int); 112a2bb96e7Sjmcp int fmt_regwin(dis_handle_t *, uint32_t, const inst_t *, int); 113a2bb96e7Sjmcp int fmt_trap_ret(dis_handle_t *, uint32_t, const inst_t *, int); 114a2bb96e7Sjmcp int fmt_movcc(dis_handle_t *, uint32_t, const inst_t *, int); 115a2bb96e7Sjmcp int fmt_movr(dis_handle_t *, uint32_t, const inst_t *, int); 116a2bb96e7Sjmcp int fmt_fused(dis_handle_t *, uint32_t, const inst_t *, int); 117a2bb96e7Sjmcp 118a2bb96e7Sjmcp #ifdef __cplusplus 119a2bb96e7Sjmcp } 120a2bb96e7Sjmcp #endif 121a2bb96e7Sjmcp 122a2bb96e7Sjmcp #endif /* _DIS_SPARC_FMT_H */ 123