120c794b3Sgavinm /*
220c794b3Sgavinm  * CDDL HEADER START
320c794b3Sgavinm  *
420c794b3Sgavinm  * The contents of this file are subject to the terms of the
520c794b3Sgavinm  * Common Development and Distribution License (the "License").
620c794b3Sgavinm  * You may not use this file except in compliance with the License.
720c794b3Sgavinm  *
820c794b3Sgavinm  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
920c794b3Sgavinm  * or http://www.opensolaris.org/os/licensing.
1020c794b3Sgavinm  * See the License for the specific language governing permissions
1120c794b3Sgavinm  * and limitations under the License.
1220c794b3Sgavinm  *
1320c794b3Sgavinm  * When distributing Covered Code, include this CDDL HEADER in each
1420c794b3Sgavinm  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1520c794b3Sgavinm  * If applicable, add the following below this CDDL HEADER, with the
1620c794b3Sgavinm  * fields enclosed by brackets "[]" replaced with your own identifying
1720c794b3Sgavinm  * information: Portions Copyright [yyyy] [name of copyright owner]
1820c794b3Sgavinm  *
1920c794b3Sgavinm  * CDDL HEADER END
2020c794b3Sgavinm  */
2120c794b3Sgavinm 
2220c794b3Sgavinm /*
2320c794b3Sgavinm  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
2420c794b3Sgavinm  * Use is subject to license terms.
2520c794b3Sgavinm  */
2620c794b3Sgavinm 
2720c794b3Sgavinm #pragma ident	"%Z%%M%	%I%	%E% SMI"
2820c794b3Sgavinm 
2920c794b3Sgavinm /*
3020c794b3Sgavinm  * AMD memory enumeration
3120c794b3Sgavinm  */
3220c794b3Sgavinm 
3320c794b3Sgavinm #include <sys/types.h>
3420c794b3Sgavinm #include <unistd.h>
3520c794b3Sgavinm #include <stropts.h>
3620c794b3Sgavinm #include <sys/fm/protocol.h>
3720c794b3Sgavinm #include <sys/mc.h>
3820c794b3Sgavinm #include <sys/mc_amd.h>
3920c794b3Sgavinm #include <fm/topo_mod.h>
4020c794b3Sgavinm #include <strings.h>
4120c794b3Sgavinm #include <sys/stat.h>
4220c794b3Sgavinm #include <fcntl.h>
4320c794b3Sgavinm 
4420c794b3Sgavinm #include "chip.h"
4520c794b3Sgavinm 
4620c794b3Sgavinm #define	MAX_CHANNUM	1
4720c794b3Sgavinm #define	MAX_DIMMNUM	7
4820c794b3Sgavinm #define	MAX_CSNUM	7
4920c794b3Sgavinm 
5020c794b3Sgavinm static const topo_pgroup_info_t cs_pgroup =
5120c794b3Sgavinm 	{ PGNAME(CS), TOPO_STABILITY_PRIVATE, TOPO_STABILITY_PRIVATE, 1 };
5220c794b3Sgavinm static const topo_pgroup_info_t dimm_pgroup =
5320c794b3Sgavinm 	{ PGNAME(DIMM), TOPO_STABILITY_PRIVATE, TOPO_STABILITY_PRIVATE, 1 };
5420c794b3Sgavinm static const topo_pgroup_info_t mc_pgroup =
5520c794b3Sgavinm 	{ PGNAME(MCT), TOPO_STABILITY_PRIVATE, TOPO_STABILITY_PRIVATE, 1 };
5620c794b3Sgavinm static const topo_pgroup_info_t rank_pgroup =
5720c794b3Sgavinm 	{ PGNAME(RANK), TOPO_STABILITY_PRIVATE, TOPO_STABILITY_PRIVATE, 1 };
5820c794b3Sgavinm static const topo_pgroup_info_t chan_pgroup =
5920c794b3Sgavinm 	{ PGNAME(CHAN), TOPO_STABILITY_PRIVATE, TOPO_STABILITY_PRIVATE, 1 };
6020c794b3Sgavinm 
6120c794b3Sgavinm static const topo_method_t dimm_methods[] = {
6220c794b3Sgavinm 	{ SIMPLE_DIMM_LBL, "Property method", 0,
6320c794b3Sgavinm 	    TOPO_STABILITY_INTERNAL, simple_dimm_label},
6420c794b3Sgavinm 	{ SIMPLE_DIMM_LBL_MP, "Property method", 0,
6520c794b3Sgavinm 	    TOPO_STABILITY_INTERNAL, simple_dimm_label_mp},
6620c794b3Sgavinm 	{ SEQ_DIMM_LBL, "Property method", 0,
6720c794b3Sgavinm 	    TOPO_STABILITY_INTERNAL, seq_dimm_label},
6820c794b3Sgavinm 	{ NULL }
6920c794b3Sgavinm };
7020c794b3Sgavinm 
7120c794b3Sgavinm static const topo_method_t rank_methods[] = {
7220c794b3Sgavinm 	{ TOPO_METH_ASRU_COMPUTE, TOPO_METH_ASRU_COMPUTE_DESC,
7320c794b3Sgavinm 	    TOPO_METH_ASRU_COMPUTE_VERSION, TOPO_STABILITY_INTERNAL,
7420c794b3Sgavinm 	    mem_asru_compute },
7520c794b3Sgavinm 	{ NULL }
7620c794b3Sgavinm };
7720c794b3Sgavinm 
7820c794b3Sgavinm static const topo_method_t gen_cs_methods[] = {
7920c794b3Sgavinm 	{ TOPO_METH_ASRU_COMPUTE, TOPO_METH_ASRU_COMPUTE_DESC,
8020c794b3Sgavinm 	    TOPO_METH_ASRU_COMPUTE_VERSION, TOPO_STABILITY_INTERNAL,
8120c794b3Sgavinm 	    mem_asru_compute },
82*5108f83cSrobj 	{ SIMPLE_CS_LBL_MP, "Property method", 0,
83*5108f83cSrobj 	    TOPO_STABILITY_INTERNAL, simple_cs_label_mp},
8420c794b3Sgavinm 	{ NULL }
8520c794b3Sgavinm };
8620c794b3Sgavinm 
8720c794b3Sgavinm static nvlist_t *cs_fmri[MC_CHIP_NCS];
8820c794b3Sgavinm 
8920c794b3Sgavinm /*
9020c794b3Sgavinm  * Called when there is no memory-controller driver to provide topology
9120c794b3Sgavinm  * information.  Generate a maximal memory topology that is appropriate
9220c794b3Sgavinm  * for the chip revision.  The memory-controller node has already been
9320c794b3Sgavinm  * bound as mcnode, and the parent of that is cnode.
9420c794b3Sgavinm  *
9520c794b3Sgavinm  * We create a tree of dram-channel and chip-select nodes below the
9620c794b3Sgavinm  * memory-controller node.  There will be two dram channels and 8 chip-selects
9720c794b3Sgavinm  * below each, regardless of actual socket type, processor revision and so on.
9820c794b3Sgavinm  * This is adequate for generic diagnosis up to family 0x10 revision C.
9920c794b3Sgavinm  * When support for revision D is implemented (or maybe C) we should take
10020c794b3Sgavinm  * the opportunity to rework the topology tree completely (socket change will
10120c794b3Sgavinm  * mean there can be no diagnosis history tied to the topology).
10220c794b3Sgavinm  */
10320c794b3Sgavinm /*ARGSUSED*/
10420c794b3Sgavinm static int
10520c794b3Sgavinm amd_generic_mc_create(topo_mod_t *mod, tnode_t *cnode, tnode_t *mcnode,
10620c794b3Sgavinm     int family, int model, int stepping, nvlist_t *auth)
10720c794b3Sgavinm {
10820c794b3Sgavinm 	int chan, cs;
10920c794b3Sgavinm 
11020c794b3Sgavinm 	/*
11120c794b3Sgavinm 	 * Elsewhere we have already returned for families less than 0xf.
11220c794b3Sgavinm 	 * This "generic" topology is adequate for all of family 0xf and
11320c794b3Sgavinm 	 * for revisions A, B and C of family 0x10 (A = model 0, B = model 1,
11420c794b3Sgavinm 	 * we'll guess C = model 3 at this point).
11520c794b3Sgavinm 	 */
11620c794b3Sgavinm 	if (family > 0x10 || (family == 0x10 && model > 3))
11720c794b3Sgavinm 		return (1);
11820c794b3Sgavinm 
11920c794b3Sgavinm 	if (topo_node_range_create(mod, mcnode, CHAN_NODE_NAME, 0,
12020c794b3Sgavinm 	    MAX_CHANNUM) < 0) {
12120c794b3Sgavinm 		whinge(mod, NULL, "amd_generic_mc_create: range create for "
12220c794b3Sgavinm 		    "channels failed\n");
12320c794b3Sgavinm 		return (-1);
12420c794b3Sgavinm 	}
12520c794b3Sgavinm 
12620c794b3Sgavinm 	for (chan = 0; chan <= MAX_CHANNUM; chan++) {
12720c794b3Sgavinm 		tnode_t *chnode;
12820c794b3Sgavinm 		nvlist_t *fmri;
12920c794b3Sgavinm 		int err;
13020c794b3Sgavinm 
13120c794b3Sgavinm 		if (mkrsrc(mod, mcnode, CHAN_NODE_NAME, chan, auth,
13220c794b3Sgavinm 		    &fmri) != 0) {
13320c794b3Sgavinm 			whinge(mod, NULL, "amd_generic_mc_create: mkrsrc "
13420c794b3Sgavinm 			    "failed\n");
13520c794b3Sgavinm 			return (-1);
13620c794b3Sgavinm 		}
13720c794b3Sgavinm 
13820c794b3Sgavinm 		if ((chnode = topo_node_bind(mod, mcnode, CHAN_NODE_NAME,
13920c794b3Sgavinm 		    chan, fmri)) == NULL) {
14020c794b3Sgavinm 			nvlist_free(fmri);
14120c794b3Sgavinm 			whinge(mod, NULL, "amd_generic_mc_create: node "
14220c794b3Sgavinm 			    "bind failed\n");
14320c794b3Sgavinm 			return (-1);
14420c794b3Sgavinm 		}
14520c794b3Sgavinm 
14620c794b3Sgavinm 		nvlist_free(fmri);
14720c794b3Sgavinm 
14820c794b3Sgavinm 		(void) topo_pgroup_create(chnode, &chan_pgroup, &err);
14920c794b3Sgavinm 
15020c794b3Sgavinm 		(void) topo_prop_set_string(chnode, PGNAME(CHAN), "channel",
15120c794b3Sgavinm 		    TOPO_PROP_IMMUTABLE, chan == 0 ? "A" : "B", &err);
15220c794b3Sgavinm 
15320c794b3Sgavinm 		if (topo_node_range_create(mod, chnode, CS_NODE_NAME,
15420c794b3Sgavinm 		    0, MAX_CSNUM) < 0) {
15520c794b3Sgavinm 			whinge(mod, NULL, "amd_generic_mc_create: "
15620c794b3Sgavinm 			    "range create for cs failed\n");
15720c794b3Sgavinm 			return (-1);
15820c794b3Sgavinm 		}
15920c794b3Sgavinm 
16020c794b3Sgavinm 		for (cs = 0; cs <= MAX_CSNUM; cs++) {
16120c794b3Sgavinm 			tnode_t *csnode;
16220c794b3Sgavinm 
16320c794b3Sgavinm 			if (mkrsrc(mod, chnode, CS_NODE_NAME, cs, auth,
16420c794b3Sgavinm 			    &fmri) != 0) {
16520c794b3Sgavinm 				whinge(mod, NULL, "amd_generic_mc_create: "
16620c794b3Sgavinm 				    "mkrsrc for cs failed\n");
16720c794b3Sgavinm 				return (-1);
16820c794b3Sgavinm 			}
16920c794b3Sgavinm 
17020c794b3Sgavinm 			if ((csnode = topo_node_bind(mod, chnode, CS_NODE_NAME,
17120c794b3Sgavinm 			    cs, fmri)) == NULL) {
17220c794b3Sgavinm 				nvlist_free(fmri);
17320c794b3Sgavinm 				whinge(mod, NULL, "amd_generic_mc_create: "
17420c794b3Sgavinm 				    "bind for cs failed\n");
17520c794b3Sgavinm 				return (-1);
17620c794b3Sgavinm 			}
17720c794b3Sgavinm 
17820c794b3Sgavinm 			/*
17920c794b3Sgavinm 			 * Dynamic ASRU for page faults within a chip-select.
18020c794b3Sgavinm 			 * The topology does not represent pages (there are
18120c794b3Sgavinm 			 * too many) so when a page is faulted we generate
18220c794b3Sgavinm 			 * an ASRU to represent the individual page.
18320c794b3Sgavinm 			 */
18420c794b3Sgavinm 			if (topo_method_register(mod, csnode,
18520c794b3Sgavinm 			    gen_cs_methods) < 0)
18620c794b3Sgavinm 				whinge(mod, NULL, "amd_generic_mc_create: "
18720c794b3Sgavinm 				    "method registration failed\n");
18820c794b3Sgavinm 
18920c794b3Sgavinm 			(void) topo_node_asru_set(csnode, fmri,
19020c794b3Sgavinm 			    TOPO_ASRU_COMPUTE, &err);
19120c794b3Sgavinm 
19220c794b3Sgavinm 			nvlist_free(fmri);
19320c794b3Sgavinm 		}
19420c794b3Sgavinm 	}
19520c794b3Sgavinm 
19620c794b3Sgavinm 	return (0);
19720c794b3Sgavinm }
19820c794b3Sgavinm 
19920c794b3Sgavinm static nvlist_t *
20020c794b3Sgavinm amd_lookup_by_mcid(topo_mod_t *mod, topo_instance_t id)
20120c794b3Sgavinm {
20220c794b3Sgavinm 	mc_snapshot_info_t mcs;
20320c794b3Sgavinm 	void *buf = NULL;
20420c794b3Sgavinm 	uint8_t ver;
20520c794b3Sgavinm 
20620c794b3Sgavinm 	nvlist_t *nvl = NULL;
20720c794b3Sgavinm 	char path[64];
20820c794b3Sgavinm 	int fd, err;
20920c794b3Sgavinm 
21020c794b3Sgavinm 	(void) snprintf(path, sizeof (path), "/dev/mc/mc%d", id);
21120c794b3Sgavinm 	fd = open(path, O_RDONLY);
21220c794b3Sgavinm 
21320c794b3Sgavinm 	if (fd == -1) {
21420c794b3Sgavinm 		/*
21520c794b3Sgavinm 		 * Some v20z and v40z systems may have had the 3rd-party
21620c794b3Sgavinm 		 * NWSnps packagae installed which installs a /dev/mc
21720c794b3Sgavinm 		 * link.  So try again via /devices.
21820c794b3Sgavinm 		 */
21920c794b3Sgavinm 		(void) snprintf(path, sizeof (path),
22020c794b3Sgavinm 		    "/devices/pci@0,0/pci1022,1102@%x,2:mc-amd",
22120c794b3Sgavinm 		    MC_AMD_DEV_OFFSET + id);
22220c794b3Sgavinm 		fd = open(path, O_RDONLY);
22320c794b3Sgavinm 	}
22420c794b3Sgavinm 
22520c794b3Sgavinm 	if (fd == -1)
22620c794b3Sgavinm 		return (NULL);	/* do not whinge */
22720c794b3Sgavinm 
22820c794b3Sgavinm 	if (ioctl(fd, MC_IOC_SNAPSHOT_INFO, &mcs) == -1 ||
22920c794b3Sgavinm 	    (buf = topo_mod_alloc(mod, mcs.mcs_size)) == NULL ||
23020c794b3Sgavinm 	    ioctl(fd, MC_IOC_SNAPSHOT, buf) == -1) {
23120c794b3Sgavinm 
23220c794b3Sgavinm 		whinge(mod, NULL, "mc failed to snapshot %s: %s\n",
23320c794b3Sgavinm 		    path, strerror(errno));
23420c794b3Sgavinm 
23520c794b3Sgavinm 		free(buf);
23620c794b3Sgavinm 		(void) close(fd);
23720c794b3Sgavinm 		return (NULL);
23820c794b3Sgavinm 	}
23920c794b3Sgavinm 
24020c794b3Sgavinm 	(void) close(fd);
24120c794b3Sgavinm 	err = nvlist_unpack(buf, mcs.mcs_size, &nvl, 0);
24220c794b3Sgavinm 	topo_mod_free(mod, buf, mcs.mcs_size);
24320c794b3Sgavinm 
24420c794b3Sgavinm 
24520c794b3Sgavinm 	if (nvlist_lookup_uint8(nvl, MC_NVLIST_VERSTR, &ver) != 0) {
24620c794b3Sgavinm 		whinge(mod, NULL, "mc nvlist is not versioned\n");
24720c794b3Sgavinm 		nvlist_free(nvl);
24820c794b3Sgavinm 		return (NULL);
24920c794b3Sgavinm 	} else if (ver != MC_NVLIST_VERS1) {
25020c794b3Sgavinm 		whinge(mod, NULL, "mc nvlist version mismatch\n");
25120c794b3Sgavinm 		nvlist_free(nvl);
25220c794b3Sgavinm 		return (NULL);
25320c794b3Sgavinm 	}
25420c794b3Sgavinm 
25520c794b3Sgavinm 	return (err ? NULL : nvl);
25620c794b3Sgavinm }
25720c794b3Sgavinm 
25820c794b3Sgavinm int
25920c794b3Sgavinm amd_rank_create(topo_mod_t *mod, tnode_t *pnode, nvlist_t *dimmnvl,
26020c794b3Sgavinm     nvlist_t *auth)
26120c794b3Sgavinm {
26220c794b3Sgavinm 	uint64_t *csnumarr;
26320c794b3Sgavinm 	char **csnamearr;
26420c794b3Sgavinm 	uint_t ncs, ncsname;
26520c794b3Sgavinm 	tnode_t *ranknode;
26620c794b3Sgavinm 	nvlist_t *fmri, *pfmri = NULL;
26720c794b3Sgavinm 	uint64_t dsz, rsz;
26820c794b3Sgavinm 	int nerr = 0;
26920c794b3Sgavinm 	int err;
27020c794b3Sgavinm 	int i;
27120c794b3Sgavinm 
27220c794b3Sgavinm 	if (nvlist_lookup_uint64_array(dimmnvl, "csnums", &csnumarr,
27320c794b3Sgavinm 	    &ncs) != 0 || nvlist_lookup_string_array(dimmnvl, "csnames",
27420c794b3Sgavinm 	    &csnamearr, &ncsname) != 0 || ncs != ncsname) {
27520c794b3Sgavinm 		whinge(mod, &nerr, "amd_rank_create: "
27620c794b3Sgavinm 		    "csnums/csnames extraction failed\n");
27720c794b3Sgavinm 		return (nerr);
27820c794b3Sgavinm 	}
27920c794b3Sgavinm 
28020c794b3Sgavinm 	if (topo_node_resource(pnode, &pfmri, &err) < 0) {
28120c794b3Sgavinm 		whinge(mod, &nerr, "amd_rank_create: parent fmri lookup "
28220c794b3Sgavinm 		    "failed\n");
28320c794b3Sgavinm 		return (nerr);
28420c794b3Sgavinm 	}
28520c794b3Sgavinm 
28620c794b3Sgavinm 	if (topo_node_range_create(mod, pnode, RANK_NODE_NAME, 0, ncs) < 0) {
28720c794b3Sgavinm 		whinge(mod, &nerr, "amd_rank_create: range create failed\n");
28820c794b3Sgavinm 		nvlist_free(pfmri);
28920c794b3Sgavinm 		return (nerr);
29020c794b3Sgavinm 	}
29120c794b3Sgavinm 
29220c794b3Sgavinm 	if (topo_prop_get_uint64(pnode, PGNAME(DIMM), "size", &dsz,
29320c794b3Sgavinm 	    &err) == 0) {
29420c794b3Sgavinm 		rsz = dsz / ncs;
29520c794b3Sgavinm 	} else {
29620c794b3Sgavinm 		whinge(mod, &nerr, "amd_rank_create: parent dimm has no "
29720c794b3Sgavinm 		    "size\n");
29820c794b3Sgavinm 		return (nerr);
29920c794b3Sgavinm 	}
30020c794b3Sgavinm 
30120c794b3Sgavinm 	for (i = 0; i < ncs; i++) {
30220c794b3Sgavinm 		if (mkrsrc(mod, pnode, RANK_NODE_NAME, i, auth, &fmri) < 0) {
30320c794b3Sgavinm 			whinge(mod, &nerr, "amd_rank_create: mkrsrc failed\n");
30420c794b3Sgavinm 			continue;
30520c794b3Sgavinm 		}
30620c794b3Sgavinm 
30720c794b3Sgavinm 		if ((ranknode = topo_node_bind(mod, pnode, RANK_NODE_NAME, i,
30820c794b3Sgavinm 		    fmri)) == NULL) {
30920c794b3Sgavinm 			nvlist_free(fmri);
31020c794b3Sgavinm 			whinge(mod, &nerr, "amd_rank_create: node bind "
31120c794b3Sgavinm 			    "failed\n");
31220c794b3Sgavinm 			continue;
31320c794b3Sgavinm 		}
31420c794b3Sgavinm 
31520c794b3Sgavinm 		nvlist_free(fmri);
31620c794b3Sgavinm 
31720c794b3Sgavinm 		(void) topo_node_fru_set(ranknode, pfmri, 0, &err);
31820c794b3Sgavinm 
31920c794b3Sgavinm 		/*
32020c794b3Sgavinm 		 * If a rank is faulted the asru is the associated
32120c794b3Sgavinm 		 * chip-select, but if a page within a rank is faulted
32220c794b3Sgavinm 		 * the asru is just that page.  Hence the dual preconstructed
32320c794b3Sgavinm 		 * and computed ASRU.
32420c794b3Sgavinm 		 */
32520c794b3Sgavinm 		if (topo_method_register(mod, ranknode, rank_methods) < 0)
32620c794b3Sgavinm 			whinge(mod, &nerr, "amd_rank_create: "
32720c794b3Sgavinm 			    "topo_method_register failed");
32820c794b3Sgavinm 
32920c794b3Sgavinm 		(void) topo_node_asru_set(ranknode, cs_fmri[csnumarr[i]],
33020c794b3Sgavinm 		    TOPO_ASRU_COMPUTE, &err);
33120c794b3Sgavinm 
33220c794b3Sgavinm 		(void) topo_pgroup_create(ranknode, &rank_pgroup, &err);
33320c794b3Sgavinm 
33420c794b3Sgavinm 		(void) topo_prop_set_uint64(ranknode, PGNAME(RANK), "size",
33520c794b3Sgavinm 		    TOPO_PROP_IMMUTABLE, rsz, &err);
33620c794b3Sgavinm 
33720c794b3Sgavinm 		(void) topo_prop_set_string(ranknode, PGNAME(RANK), "csname",
33820c794b3Sgavinm 		    TOPO_PROP_IMMUTABLE, csnamearr[i], &err);
33920c794b3Sgavinm 
34020c794b3Sgavinm 		(void) topo_prop_set_uint64(ranknode, PGNAME(RANK), "csnum",
34120c794b3Sgavinm 		    TOPO_PROP_IMMUTABLE, csnumarr[i], &err);
34220c794b3Sgavinm 	}
34320c794b3Sgavinm 
34420c794b3Sgavinm 	nvlist_free(pfmri);
34520c794b3Sgavinm 
34620c794b3Sgavinm 	return (nerr);
34720c794b3Sgavinm }
34820c794b3Sgavinm 
34920c794b3Sgavinm static int
35020c794b3Sgavinm amd_dimm_create(topo_mod_t *mod, tnode_t *pnode, const char *name,
35120c794b3Sgavinm     nvlist_t *mc, nvlist_t *auth)
35220c794b3Sgavinm {
35320c794b3Sgavinm 	int i, err, nerr = 0;
35420c794b3Sgavinm 	nvpair_t *nvp;
35520c794b3Sgavinm 	tnode_t *dimmnode;
35620c794b3Sgavinm 	nvlist_t *fmri, *asru, **dimmarr = NULL;
35720c794b3Sgavinm 	uint64_t num;
35820c794b3Sgavinm 	uint_t ndimm;
35920c794b3Sgavinm 
36020c794b3Sgavinm 	if (nvlist_lookup_nvlist_array(mc, "dimmlist", &dimmarr, &ndimm) != 0) {
36120c794b3Sgavinm 		whinge(mod, NULL, "amd_dimm_create: dimmlist lookup failed\n");
36220c794b3Sgavinm 		return (-1);
36320c794b3Sgavinm 	}
36420c794b3Sgavinm 
36520c794b3Sgavinm 	if (ndimm == 0)
36620c794b3Sgavinm 		return (0);	/* no dimms present on this node */
36720c794b3Sgavinm 
36820c794b3Sgavinm 	if (topo_node_range_create(mod, pnode, name, 0, MAX_DIMMNUM) < 0) {
36920c794b3Sgavinm 		whinge(mod, NULL, "amd_dimm_create: range create failed\n");
37020c794b3Sgavinm 		return (-1);
37120c794b3Sgavinm 	}
37220c794b3Sgavinm 
37320c794b3Sgavinm 	for (i = 0; i < ndimm; i++) {
37420c794b3Sgavinm 		if (nvlist_lookup_uint64(dimmarr[i], "num", &num) != 0) {
37520c794b3Sgavinm 			whinge(mod, &nerr, "amd_dimm_create: dimm num property "
37620c794b3Sgavinm 			    "missing\n");
37720c794b3Sgavinm 			continue;
37820c794b3Sgavinm 		}
37920c794b3Sgavinm 
38020c794b3Sgavinm 		if (mkrsrc(mod, pnode, name, num, auth, &fmri) < 0) {
38120c794b3Sgavinm 			whinge(mod, &nerr, "amd_dimm_create: mkrsrc failed\n");
38220c794b3Sgavinm 			continue;
38320c794b3Sgavinm 		}
38420c794b3Sgavinm 
38520c794b3Sgavinm 		if ((dimmnode = topo_node_bind(mod, pnode, name, num, fmri))
38620c794b3Sgavinm 		    == NULL) {
38720c794b3Sgavinm 			nvlist_free(fmri);
38820c794b3Sgavinm 			whinge(mod, &nerr, "amd_dimm_create: node bind "
38920c794b3Sgavinm 			    "failed\n");
39020c794b3Sgavinm 			continue;
39120c794b3Sgavinm 		}
39220c794b3Sgavinm 
39320c794b3Sgavinm 		if (topo_method_register(mod, dimmnode, dimm_methods) < 0)
39420c794b3Sgavinm 			whinge(mod, &nerr, "dimm_create: "
39520c794b3Sgavinm 			    "topo_method_register failed");
39620c794b3Sgavinm 
39720c794b3Sgavinm 		/*
39820c794b3Sgavinm 		 * Use the mem computation method directly to publish the asru
39920c794b3Sgavinm 		 * in the "mem" scheme.
40020c794b3Sgavinm 		 */
40120c794b3Sgavinm 		if (mem_asru_create(mod, fmri, &asru) == 0) {
40220c794b3Sgavinm 			(void) topo_node_asru_set(dimmnode, asru, 0, &err);
40320c794b3Sgavinm 			nvlist_free(asru);
40420c794b3Sgavinm 		} else {
40520c794b3Sgavinm 
40620c794b3Sgavinm 			nvlist_free(fmri);
40720c794b3Sgavinm 			whinge(mod, &nerr, "amd_dimm_create: "
40820c794b3Sgavinm 			    "mem_asru_create failed\n");
40920c794b3Sgavinm 			continue;
41020c794b3Sgavinm 		}
41120c794b3Sgavinm 
41220c794b3Sgavinm 		(void) topo_node_fru_set(dimmnode, fmri, 0, &err);
41320c794b3Sgavinm 
41420c794b3Sgavinm 		nvlist_free(fmri);
41520c794b3Sgavinm 
41620c794b3Sgavinm 		(void) topo_pgroup_create(dimmnode, &dimm_pgroup, &err);
41720c794b3Sgavinm 
41820c794b3Sgavinm 		for (nvp = nvlist_next_nvpair(dimmarr[i], NULL); nvp != NULL;
41920c794b3Sgavinm 		    nvp = nvlist_next_nvpair(dimmarr[i], nvp)) {
42020c794b3Sgavinm 			if (nvpair_type(nvp) == DATA_TYPE_UINT64_ARRAY &&
42120c794b3Sgavinm 			    strcmp(nvpair_name(nvp), "csnums") == 0 ||
42220c794b3Sgavinm 			    nvpair_type(nvp) == DATA_TYPE_STRING_ARRAY &&
42320c794b3Sgavinm 			    strcmp(nvpair_name(nvp), "csnames") == 0)
42420c794b3Sgavinm 				continue;	/* used in amd_rank_create() */
42520c794b3Sgavinm 
42620c794b3Sgavinm 			nerr += nvprop_add(mod, nvp, PGNAME(DIMM), dimmnode);
42720c794b3Sgavinm 		}
42820c794b3Sgavinm 
42920c794b3Sgavinm 		nerr += amd_rank_create(mod, dimmnode, dimmarr[i], auth);
43020c794b3Sgavinm 	}
43120c794b3Sgavinm 
43220c794b3Sgavinm 	return (nerr == 0 ? 0 : -1);
43320c794b3Sgavinm }
43420c794b3Sgavinm 
43520c794b3Sgavinm static int
43620c794b3Sgavinm amd_cs_create(topo_mod_t *mod, tnode_t *pnode, const char *name, nvlist_t *mc,
43720c794b3Sgavinm     nvlist_t *auth)
43820c794b3Sgavinm {
43920c794b3Sgavinm 	int i, err, nerr = 0;
44020c794b3Sgavinm 	nvpair_t *nvp;
44120c794b3Sgavinm 	tnode_t *csnode;
44220c794b3Sgavinm 	nvlist_t *fmri, **csarr = NULL;
44320c794b3Sgavinm 	uint64_t csnum;
44420c794b3Sgavinm 	uint_t ncs;
44520c794b3Sgavinm 
44620c794b3Sgavinm 	if (nvlist_lookup_nvlist_array(mc, "cslist", &csarr, &ncs) != 0)
44720c794b3Sgavinm 		return (-1);
44820c794b3Sgavinm 
44920c794b3Sgavinm 	if (ncs == 0)
45020c794b3Sgavinm 		return (0);	/* no chip-selects configured on this node */
45120c794b3Sgavinm 
45220c794b3Sgavinm 	if (topo_node_range_create(mod, pnode, name, 0, MAX_CSNUM) < 0)
45320c794b3Sgavinm 		return (-1);
45420c794b3Sgavinm 
45520c794b3Sgavinm 	for (i = 0; i < ncs; i++) {
45620c794b3Sgavinm 		if (nvlist_lookup_uint64(csarr[i], "num", &csnum) != 0) {
45720c794b3Sgavinm 			whinge(mod, &nerr, "amd_cs_create: cs num property "
45820c794b3Sgavinm 			    "missing\n");
45920c794b3Sgavinm 			continue;
46020c794b3Sgavinm 		}
46120c794b3Sgavinm 
46220c794b3Sgavinm 		if (mkrsrc(mod, pnode, name, csnum, auth, &fmri) != 0) {
46320c794b3Sgavinm 			whinge(mod, &nerr, "amd_cs_create: mkrsrc failed\n");
46420c794b3Sgavinm 			continue;
46520c794b3Sgavinm 		}
46620c794b3Sgavinm 
46720c794b3Sgavinm 		if ((csnode = topo_node_bind(mod, pnode, name, csnum, fmri))
46820c794b3Sgavinm 		    == NULL) {
46920c794b3Sgavinm 			nvlist_free(fmri);
47020c794b3Sgavinm 			whinge(mod, &nerr, "amd_cs_create: node bind failed\n");
47120c794b3Sgavinm 			continue;
47220c794b3Sgavinm 		}
47320c794b3Sgavinm 
47420c794b3Sgavinm 		cs_fmri[csnum] = fmri;	/* nvlist will be freed in mc_create */
47520c794b3Sgavinm 
47620c794b3Sgavinm 		(void) topo_node_asru_set(csnode, fmri, 0, &err);
47720c794b3Sgavinm 
47820c794b3Sgavinm 		(void) topo_pgroup_create(csnode, &cs_pgroup, &err);
47920c794b3Sgavinm 
48020c794b3Sgavinm 		for (nvp = nvlist_next_nvpair(csarr[i], NULL); nvp != NULL;
48120c794b3Sgavinm 		    nvp = nvlist_next_nvpair(csarr[i], nvp)) {
48220c794b3Sgavinm 			nerr += nvprop_add(mod, nvp, PGNAME(CS), csnode);
48320c794b3Sgavinm 		}
48420c794b3Sgavinm 	}
48520c794b3Sgavinm 
48620c794b3Sgavinm 	return (nerr == 0 ? 0 : -1);
48720c794b3Sgavinm }
48820c794b3Sgavinm 
48920c794b3Sgavinm static int
49020c794b3Sgavinm amd_dramchan_create(topo_mod_t *mod, tnode_t *pnode, const char *name,
49120c794b3Sgavinm     nvlist_t *auth)
49220c794b3Sgavinm {
49320c794b3Sgavinm 	tnode_t *chnode;
49420c794b3Sgavinm 	nvlist_t *fmri;
49520c794b3Sgavinm 	char *socket;
49620c794b3Sgavinm 	int i, nchan;
49720c794b3Sgavinm 	int err, nerr = 0;
49820c794b3Sgavinm 
49920c794b3Sgavinm 	/*
50020c794b3Sgavinm 	 * We will enumerate the number of channels present even if only
50120c794b3Sgavinm 	 * channel A is in use (i.e., running in 64-bit mode).  Only
50220c794b3Sgavinm 	 * the socket 754 package has a single channel.
50320c794b3Sgavinm 	 */
50420c794b3Sgavinm 	if (topo_prop_get_string(pnode, PGNAME(MCT), "socket",
50520c794b3Sgavinm 	    &socket, &err) == 0 && strcmp(socket, "Socket 754") == 0)
50620c794b3Sgavinm 		nchan = 1;
50720c794b3Sgavinm 	else
50820c794b3Sgavinm 		nchan = 2;
50920c794b3Sgavinm 
51020c794b3Sgavinm 	topo_mod_strfree(mod, socket);
51120c794b3Sgavinm 
51220c794b3Sgavinm 	if (topo_node_range_create(mod, pnode, name, 0, nchan - 1) < 0)
51320c794b3Sgavinm 		return (-1);
51420c794b3Sgavinm 
51520c794b3Sgavinm 	for (i = 0; i < nchan; i++) {
51620c794b3Sgavinm 		if (mkrsrc(mod, pnode, name, i, auth, &fmri) != 0) {
51720c794b3Sgavinm 			whinge(mod, &nerr, "amd_dramchan_create: mkrsrc "
51820c794b3Sgavinm 			    "failed\n");
51920c794b3Sgavinm 			continue;
52020c794b3Sgavinm 		}
52120c794b3Sgavinm 
52220c794b3Sgavinm 		if ((chnode = topo_node_bind(mod, pnode, name, i, fmri))
52320c794b3Sgavinm 		    == NULL) {
52420c794b3Sgavinm 			nvlist_free(fmri);
52520c794b3Sgavinm 			whinge(mod, &nerr, "amd_dramchan_create: node bind "
52620c794b3Sgavinm 			    "failed\n");
52720c794b3Sgavinm 			continue;
52820c794b3Sgavinm 		}
52920c794b3Sgavinm 
53020c794b3Sgavinm 		nvlist_free(fmri);
53120c794b3Sgavinm 
53220c794b3Sgavinm 		(void) topo_pgroup_create(chnode, &chan_pgroup, &err);
53320c794b3Sgavinm 
53420c794b3Sgavinm 		(void) topo_prop_set_string(chnode, PGNAME(CHAN), "channel",
53520c794b3Sgavinm 		    TOPO_PROP_IMMUTABLE, i == 0 ? "A" : "B", &err);
53620c794b3Sgavinm 	}
53720c794b3Sgavinm 
53820c794b3Sgavinm 	return (nerr == 0 ? 0 : -1);
53920c794b3Sgavinm }
54020c794b3Sgavinm 
54120c794b3Sgavinm static int
54220c794b3Sgavinm amd_htconfig(topo_mod_t *mod, tnode_t *cnode, nvlist_t *htnvl)
54320c794b3Sgavinm {
54420c794b3Sgavinm 	nvpair_t *nvp;
54520c794b3Sgavinm 	int nerr = 0;
54620c794b3Sgavinm 
54720c794b3Sgavinm 	if (strcmp(topo_node_name(cnode), CHIP_NODE_NAME) != 0) {
54820c794b3Sgavinm 		whinge(mod, &nerr, "amd_htconfig: must pass a chip node!");
54920c794b3Sgavinm 		return (-1);
55020c794b3Sgavinm 	}
55120c794b3Sgavinm 
55220c794b3Sgavinm 	for (nvp = nvlist_next_nvpair(htnvl, NULL); nvp != NULL;
55320c794b3Sgavinm 	    nvp = nvlist_next_nvpair(htnvl, nvp)) {
55420c794b3Sgavinm 		if (nvprop_add(mod, nvp, PGNAME(CHIP), cnode) != 0)
55520c794b3Sgavinm 			nerr++;
55620c794b3Sgavinm 	}
55720c794b3Sgavinm 
55820c794b3Sgavinm 	return (nerr == 0 ? 0 : -1);
55920c794b3Sgavinm }
56020c794b3Sgavinm 
56120c794b3Sgavinm void
56220c794b3Sgavinm amd_mc_create(topo_mod_t *mod, tnode_t *pnode, const char *name, nvlist_t *auth,
56320c794b3Sgavinm     int family, int model, int stepping, int *nerrp)
56420c794b3Sgavinm {
56520c794b3Sgavinm 	tnode_t *mcnode;
56620c794b3Sgavinm 	nvlist_t *fmri;
56720c794b3Sgavinm 	nvpair_t *nvp;
56820c794b3Sgavinm 	nvlist_t *mc = NULL;
56920c794b3Sgavinm 	int i;
57020c794b3Sgavinm 
57120c794b3Sgavinm 	/*
57220c794b3Sgavinm 	 * Return with no error for anything before AMD family 0xf - we
57320c794b3Sgavinm 	 * won't generate even a generic memory topolofy for earlier
57420c794b3Sgavinm 	 * families.
57520c794b3Sgavinm 	 */
57620c794b3Sgavinm 	if (family < 0xf)
57720c794b3Sgavinm 		return;
57820c794b3Sgavinm 
57920c794b3Sgavinm 	if (mkrsrc(mod, pnode, name, 0, auth, &fmri) != 0) {
58020c794b3Sgavinm 		whinge(mod, nerrp, "mc_create: mkrsrc failed\n");
58120c794b3Sgavinm 		return;
58220c794b3Sgavinm 	}
58320c794b3Sgavinm 
58420c794b3Sgavinm 	if (topo_node_range_create(mod, pnode, name, 0, 0) < 0) {
58520c794b3Sgavinm 		nvlist_free(fmri);
58620c794b3Sgavinm 		whinge(mod, nerrp, "mc_create: node range create failed\n");
58720c794b3Sgavinm 		return;
58820c794b3Sgavinm 	}
58920c794b3Sgavinm 
59020c794b3Sgavinm 	if ((mcnode = topo_node_bind(mod, pnode, name, 0,
59120c794b3Sgavinm 	    fmri)) == NULL) {
59220c794b3Sgavinm 		nvlist_free(mc);
59320c794b3Sgavinm 		topo_node_range_destroy(pnode, name);
59420c794b3Sgavinm 		nvlist_free(fmri);
59520c794b3Sgavinm 		whinge(mod, nerrp, "mc_create: mc bind failed\n");
59620c794b3Sgavinm 		return;
59720c794b3Sgavinm 	}
59820c794b3Sgavinm 	(void) topo_node_fru_set(mcnode, NULL, 0, nerrp);
59920c794b3Sgavinm 	nvlist_free(fmri);
60020c794b3Sgavinm 
60120c794b3Sgavinm 	if ((mc = amd_lookup_by_mcid(mod, topo_node_instance(pnode))) == NULL) {
60220c794b3Sgavinm 		/*
60320c794b3Sgavinm 		 * If a memory-controller driver exists for this chip model
60420c794b3Sgavinm 		 * it has not attached or has otherwise malfunctioned;
60520c794b3Sgavinm 		 * alternatively no memory-controller driver exists for this
60620c794b3Sgavinm 		 * (presumably newly-released) cpu model.  We fallback to
60720c794b3Sgavinm 		 * creating a generic maximal topology.
60820c794b3Sgavinm 		 */
60920c794b3Sgavinm 		if (amd_generic_mc_create(mod, pnode, mcnode,
61020c794b3Sgavinm 		    family, model, stepping, auth) != 0)
61120c794b3Sgavinm 			++*nerrp;
61220c794b3Sgavinm 		return;
61320c794b3Sgavinm 	}
61420c794b3Sgavinm 
61520c794b3Sgavinm 	/*
61620c794b3Sgavinm 	 * Add memory controller properties
61720c794b3Sgavinm 	 */
61820c794b3Sgavinm 	(void) topo_pgroup_create(mcnode, &mc_pgroup, nerrp);
61920c794b3Sgavinm 
62020c794b3Sgavinm 	for (nvp = nvlist_next_nvpair(mc, NULL); nvp != NULL;
62120c794b3Sgavinm 	    nvp = nvlist_next_nvpair(mc, nvp)) {
62220c794b3Sgavinm 		char *name = nvpair_name(nvp);
62320c794b3Sgavinm 		data_type_t type = nvpair_type(nvp);
62420c794b3Sgavinm 
62520c794b3Sgavinm 		if (type == DATA_TYPE_NVLIST_ARRAY &&
62620c794b3Sgavinm 		    (strcmp(name, "cslist") == 0 ||
62720c794b3Sgavinm 		    strcmp(name, "dimmlist") == 0)) {
62820c794b3Sgavinm 			continue;
62920c794b3Sgavinm 		} else if (type == DATA_TYPE_UINT8 &&
63020c794b3Sgavinm 		    strcmp(name, MC_NVLIST_VERSTR) == 0) {
63120c794b3Sgavinm 			continue;
63220c794b3Sgavinm 		} else if (type == DATA_TYPE_NVLIST &&
63320c794b3Sgavinm 		    strcmp(name, "htconfig") == 0) {
63420c794b3Sgavinm 			nvlist_t *htnvl;
63520c794b3Sgavinm 
63620c794b3Sgavinm 			(void) nvpair_value_nvlist(nvp, &htnvl);
63720c794b3Sgavinm 			if (amd_htconfig(mod, pnode, htnvl) != 0)
63820c794b3Sgavinm 				++*nerrp;
63920c794b3Sgavinm 		} else {
64020c794b3Sgavinm 			if (nvprop_add(mod, nvp, PGNAME(MCT), mcnode) != 0)
64120c794b3Sgavinm 				++*nerrp;
64220c794b3Sgavinm 		}
64320c794b3Sgavinm 	}
64420c794b3Sgavinm 
64520c794b3Sgavinm 	if (amd_dramchan_create(mod, mcnode, CHAN_NODE_NAME, auth) != 0 ||
64620c794b3Sgavinm 	    amd_cs_create(mod, mcnode, CS_NODE_NAME, mc, auth) != 0 ||
64720c794b3Sgavinm 	    amd_dimm_create(mod, mcnode, DIMM_NODE_NAME, mc, auth) != 0)
64820c794b3Sgavinm 		++*nerrp;
64920c794b3Sgavinm 
65020c794b3Sgavinm 	/*
65120c794b3Sgavinm 	 * Free the fmris for the chip-selects allocated in amd_cs_create
65220c794b3Sgavinm 	 */
65320c794b3Sgavinm 	for (i = 0; i < MC_CHIP_NCS; i++) {
65420c794b3Sgavinm 		if (cs_fmri[i] != NULL) {
65520c794b3Sgavinm 			nvlist_free(cs_fmri[i]);
65620c794b3Sgavinm 			cs_fmri[i] = NULL;
65720c794b3Sgavinm 		}
65820c794b3Sgavinm 	}
65920c794b3Sgavinm 
66020c794b3Sgavinm 	nvlist_free(mc);
66120c794b3Sgavinm }
662