17c478bdstevel@tonic-gate/**************************************************************************
27c478bdstevel@tonic-gateEtherboot -  BOOTP/TFTP Bootstrap Program
37c478bdstevel@tonic-gateInter Pro 1000 for Etherboot
47c478bdstevel@tonic-gateDrivers are port from Intel's Linux driver e1000-4.3.15
57c478bdstevel@tonic-gate
67c478bdstevel@tonic-gate***************************************************************************/
77c478bdstevel@tonic-gate/*******************************************************************************
87c478bdstevel@tonic-gate
97c478bdstevel@tonic-gate
107c478bdstevel@tonic-gate  Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
117c478bdstevel@tonic-gate
127c478bdstevel@tonic-gate  This program is free software; you can redistribute it and/or modify it
137c478bdstevel@tonic-gate  under the terms of the GNU General Public License as published by the Free
147c478bdstevel@tonic-gate  Software Foundation; either version 2 of the License, or (at your option)
157c478bdstevel@tonic-gate  any later version.
167c478bdstevel@tonic-gate
177c478bdstevel@tonic-gate  This program is distributed in the hope that it will be useful, but WITHOUT
187c478bdstevel@tonic-gate  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
197c478bdstevel@tonic-gate  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
207c478bdstevel@tonic-gate  more details.
217c478bdstevel@tonic-gate
227c478bdstevel@tonic-gate  You should have received a copy of the GNU General Public License along with
237c478bdstevel@tonic-gate  this program; if not, write to the Free Software Foundation, Inc., 59
247c478bdstevel@tonic-gate  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
257c478bdstevel@tonic-gate
267c478bdstevel@tonic-gate  The full GNU General Public License is included in this distribution in the
277c478bdstevel@tonic-gate  file called LICENSE.
287c478bdstevel@tonic-gate
297c478bdstevel@tonic-gate  Contact Information:
307c478bdstevel@tonic-gate  Linux NICS <linux.nics@intel.com>
317c478bdstevel@tonic-gate  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
327c478bdstevel@tonic-gate
337c478bdstevel@tonic-gate*******************************************************************************/
347c478bdstevel@tonic-gate/*
357c478bdstevel@tonic-gate *  Copyright (C) Archway Digital Solutions.
367c478bdstevel@tonic-gate *
377c478bdstevel@tonic-gate *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
387c478bdstevel@tonic-gate *  2/9/2002
397c478bdstevel@tonic-gate *
407c478bdstevel@tonic-gate *  Copyright (C) Linux Networx.
417c478bdstevel@tonic-gate *  Massive upgrade to work with the new intel gigabit NICs.
427c478bdstevel@tonic-gate *  <ebiederman at lnxi dot com>
437c478bdstevel@tonic-gate *
447c478bdstevel@tonic-gate *  Support for 82541ei & 82547ei chips from Intel's Linux driver 5.1.13 added by
457c478bdstevel@tonic-gate *  Georg Baum <gbaum@users.sf.net>, sponsored by PetaMem GmbH and linkLINE Communications, Inc.
467c478bdstevel@tonic-gate *
477c478bdstevel@tonic-gate *  01/2004: Updated to Linux driver 5.2.22 by Georg Baum <gbaum@users.sf.net>
487c478bdstevel@tonic-gate */
497c478bdstevel@tonic-gate
507c478bdstevel@tonic-gate/* to get some global routines like printf */
517c478bdstevel@tonic-gate#include "etherboot.h"
527c478bdstevel@tonic-gate/* to get the interface to the body of the program */
537c478bdstevel@tonic-gate#include "nic.h"
547c478bdstevel@tonic-gate/* to get the PCI support functions, if this is a PCI NIC */
557c478bdstevel@tonic-gate#include "pci.h"
567c478bdstevel@tonic-gate#include "timer.h"
577c478bdstevel@tonic-gate
587c478bdstevel@tonic-gatetypedef unsigned char *dma_addr_t;
597c478bdstevel@tonic-gate
607c478bdstevel@tonic-gatetypedef enum {
617c478bdstevel@tonic-gate	FALSE = 0,
627c478bdstevel@tonic-gate	TRUE = 1
637c478bdstevel@tonic-gate} boolean_t;
647c478bdstevel@tonic-gate
657c478bdstevel@tonic-gate#define DEBUG 0
667c478bdstevel@tonic-gate
677c478bdstevel@tonic-gate
687c478bdstevel@tonic-gate/* Some pieces of code are disabled with #if 0 ... #endif.
697c478bdstevel@tonic-gate * They are not deleted to show where the etherboot driver differs
707c478bdstevel@tonic-gate * from the linux driver below the function level.
717c478bdstevel@tonic-gate * Some member variables of the hw struct have been eliminated
727c478bdstevel@tonic-gate * and the corresponding inplace checks inserted instead.
737c478bdstevel@tonic-gate * Pieces such as LED handling that we definitely don't need are deleted.
747c478bdstevel@tonic-gate *
757c478bdstevel@tonic-gate * The following defines should not be needed normally,
767c478bdstevel@tonic-gate * but may be helpful for debugging purposes. */
777c478bdstevel@tonic-gate
787c478bdstevel@tonic-gate/* Define this if you want to program the transmission control register
797c478bdstevel@tonic-gate * the way the Linux driver does it. */
807c478bdstevel@tonic-gate#undef LINUX_DRIVER_TCTL
817c478bdstevel@tonic-gate
827c478bdstevel@tonic-gate/* Define this to behave more like the Linux driver. */
837c478bdstevel@tonic-gate#undef LINUX_DRIVER
847c478bdstevel@tonic-gate
857c478bdstevel@tonic-gate#include "e1000_hw.h"
867c478bdstevel@tonic-gate
877c478bdstevel@tonic-gate/* NIC specific static variables go here */
887c478bdstevel@tonic-gatestatic struct e1000_hw hw;
897c478bdstevel@tonic-gatestatic char tx_pool[128 + 16];
907c478bdstevel@tonic-gatestatic char rx_pool[128 + 16];
917c478bdstevel@tonic-gatestatic char packet[2096];
927c478bdstevel@tonic-gate
937c478bdstevel@tonic-gatestatic struct e1000_tx_desc *tx_base;
947c478bdstevel@tonic-gatestatic struct e1000_rx_desc *rx_base;
957c478bdstevel@tonic-gate
967c478bdstevel@tonic-gatestatic int tx_tail;
977c478bdstevel@tonic-gatestatic int rx_tail, rx_last;
987c478bdstevel@tonic-gate
997c478bdstevel@tonic-gate/* Function forward declarations */
1007c478bdstevel@tonic-gatestatic int e1000_setup_link(struct e1000_hw *hw);
1017c478bdstevel@tonic-gatestatic int e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
1027c478bdstevel@tonic-gatestatic int e1000_setup_copper_link(struct e1000_hw *hw);
1037c478bdstevel@tonic-gatestatic int e1000_phy_setup_autoneg(struct e1000_hw *hw);
1047c478bdstevel@tonic-gatestatic void e1000_config_collision_dist(struct e1000_hw *hw);
1057c478bdstevel@tonic-gatestatic int e1000_config_mac_to_phy(struct e1000_hw *hw);
1067c478bdstevel@tonic-gatestatic int e1000_config_fc_after_link_up(struct e1000_hw *hw);
1077c478bdstevel@tonic-gatestatic int e1000_check_for_link(struct e1000_hw *hw);
1087c478bdstevel@tonic-gatestatic int e1000_wait_autoneg(struct e1000_hw *hw);
1097c478bdstevel@tonic-gatestatic void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex);
1107c478bdstevel@tonic-gatestatic int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
1117c478bdstevel@tonic-gatestatic int e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
1127c478bdstevel@tonic-gatestatic int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
1137c478bdstevel@tonic-gatestatic int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
1147c478bdstevel@tonic-gatestatic void e1000_phy_hw_reset(struct e1000_hw *hw);
1157c478bdstevel@tonic-gatestatic int e1000_phy_reset(struct e1000_hw *hw);
1167c478bdstevel@tonic-gatestatic int e1000_detect_gig_phy(struct e1000_hw *hw);
1177c478bdstevel@tonic-gate
1187c478bdstevel@tonic-gate/* Printing macros... */
1197c478bdstevel@tonic-gate
1207c478bdstevel@tonic-gate#define E1000_ERR(args...) printf("e1000: " args)
1217c478bdstevel@tonic-gate
1227c478bdstevel@tonic-gate#if DEBUG >= 3
1237c478bdstevel@tonic-gate#define E1000_DBG(args...) printf("e1000: " args)
1247c478bdstevel@tonic-gate#else
1257c478bdstevel@tonic-gate#define E1000_DBG(args...)
1267c478bdstevel@tonic-gate#endif
1277c478bdstevel@tonic-gate
1287c478bdstevel@tonic-gate#define MSGOUT(S, A, B)     printk(S "\n", A, B)
1297c478bdstevel@tonic-gate#if DEBUG >= 2
1307c478bdstevel@tonic-gate#define DEBUGFUNC(F)        DEBUGOUT(F "\n");
1317c478bdstevel@tonic-gate#else
1327c478bdstevel@tonic-gate#define DEBUGFUNC(F)
1337c478bdstevel@tonic-gate#endif
1347c478bdstevel@tonic-gate#if DEBUG >= 1
1357c478bdstevel@tonic-gate#define DEBUGOUT(S) printf(S)
1367c478bdstevel@tonic-gate#define DEBUGOUT1(S,A) printf(S,A)
1377c478bdstevel@tonic-gate#define DEBUGOUT2(S,A,B) printf(S,A,B)
1387c478bdstevel@tonic-gate#define DEBUGOUT3(S,A,B,C) printf(S,A,B,C)
1397c478bdstevel@tonic-gate#define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S,A,B,C,D,E,F,G)
1407c478bdstevel@tonic-gate#else
1417c478bdstevel@tonic-gate#define DEBUGOUT(S)
1427c478bdstevel@tonic-gate#define DEBUGOUT1(S,A)
1437c478bdstevel@tonic-gate#define DEBUGOUT2(S,A,B)
1447c478bdstevel@tonic-gate#define DEBUGOUT3(S,A,B,C)
1457c478bdstevel@tonic-gate#define DEBUGOUT7(S,A,B,C,D,E,F,G)
1467c478bdstevel@tonic-gate#endif
1477c478bdstevel@tonic-gate
1487c478bdstevel@tonic-gate#define E1000_WRITE_REG(a, reg, value) ( \
1497c478bdstevel@tonic-gate    ((a)->mac_type >= e1000_82543) ? \
1507c478bdstevel@tonic-gate        (writel((value), ((a)->hw_addr + E1000_##reg))) : \
1517c478bdstevel@tonic-gate        (writel((value), ((a)->hw_addr + E1000_82542_##reg))))
1527c478bdstevel@tonic-gate
1537c478bdstevel@tonic-gate#define E1000_READ_REG(a, reg) ( \
1547c478bdstevel@tonic-gate    ((a)->mac_type >= e1000_82543) ? \
1557c478bdstevel@tonic-gate        readl((a)->hw_addr + E1000_##reg) : \
1567c478bdstevel@tonic-gate        readl((a)->hw_addr + E1000_82542_##reg))
1577c478bdstevel@tonic-gate
1587c478bdstevel@tonic-gate#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
1597c478bdstevel@tonic-gate    ((a)->mac_type >= e1000_82543) ? \
1607c478bdstevel@tonic-gate        writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \
1617c478bdstevel@tonic-gate        writel((value), ((a)->hw_addr + E1000_82542_##reg + ((offset) << 2))))
1627c478bdstevel@tonic-gate
1637c478bdstevel@tonic-gate#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
1647c478bdstevel@tonic-gate    ((a)->mac_type >= e1000_82543) ? \
1657c478bdstevel@tonic-gate        readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) : \
1667c478bdstevel@tonic-gate        readl((a)->hw_addr + E1000_82542_##reg + ((offset) << 2)))
1677c478bdstevel@tonic-gate
1687c478bdstevel@tonic-gate#define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
1697c478bdstevel@tonic-gate
1707c478bdstevel@tonic-gateuint32_t
1717c478bdstevel@tonic-gatee1000_io_read(struct e1000_hw *hw __unused, uint32_t port)
1727c478bdstevel@tonic-gate{
1737c478bdstevel@tonic-gate        return inl(port);
1747c478bdstevel@tonic-gate}
1757c478bdstevel@tonic-gate
1767c478bdstevel@tonic-gatevoid
1777c478bdstevel@tonic-gatee1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value)
1787c478bdstevel@tonic-gate{
1797c478bdstevel@tonic-gate        outl(value, port);
1807c478bdstevel@tonic-gate}
1817c478bdstevel@tonic-gate
1827c478bdstevel@tonic-gatestatic inline void e1000_pci_set_mwi(struct e1000_hw *hw)
1837c478bdstevel@tonic-gate{
1847c478bdstevel@tonic-gate	pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1857c478bdstevel@tonic-gate}
1867c478bdstevel@tonic-gate
1877c478bdstevel@tonic-gatestatic inline void e1000_pci_clear_mwi(struct e1000_hw *hw)
1887c478bdstevel@tonic-gate{
1897c478bdstevel@tonic-gate	pci_write_config_word(hw->pdev, PCI_COMMAND,
1907c478bdstevel@tonic-gate			      hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1917c478bdstevel@tonic-gate}
1927c478bdstevel@tonic-gate
1937c478bdstevel@tonic-gate/******************************************************************************
1947c478bdstevel@tonic-gate * Raises the EEPROM's clock input.
1957c478bdstevel@tonic-gate *
1967c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
1977c478bdstevel@tonic-gate * eecd - EECD's current value
1987c478bdstevel@tonic-gate *****************************************************************************/
1997c478bdstevel@tonic-gatestatic void
2007c478bdstevel@tonic-gatee1000_raise_ee_clk(struct e1000_hw *hw,
2017c478bdstevel@tonic-gate                   uint32_t *eecd)
2027c478bdstevel@tonic-gate{
2037c478bdstevel@tonic-gate	/* Raise the clock input to the EEPROM (by setting the SK bit), and then
2047c478bdstevel@tonic-gate	 * wait <delay> microseconds.
2057c478bdstevel@tonic-gate	 */
2067c478bdstevel@tonic-gate	*eecd = *eecd | E1000_EECD_SK;
2077c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, EECD, *eecd);
2087c478bdstevel@tonic-gate	E1000_WRITE_FLUSH(hw);
2097c478bdstevel@tonic-gate	udelay(hw->eeprom.delay_usec);
2107c478bdstevel@tonic-gate}
2117c478bdstevel@tonic-gate
2127c478bdstevel@tonic-gate/******************************************************************************
2137c478bdstevel@tonic-gate * Lowers the EEPROM's clock input.
2147c478bdstevel@tonic-gate *
2157c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
2167c478bdstevel@tonic-gate * eecd - EECD's current value
2177c478bdstevel@tonic-gate *****************************************************************************/
2187c478bdstevel@tonic-gatestatic void
2197c478bdstevel@tonic-gatee1000_lower_ee_clk(struct e1000_hw *hw,
2207c478bdstevel@tonic-gate                   uint32_t *eecd)
2217c478bdstevel@tonic-gate{
2227c478bdstevel@tonic-gate	/* Lower the clock input to the EEPROM (by clearing the SK bit), and then
2237c478bdstevel@tonic-gate	 * wait 50 microseconds.
2247c478bdstevel@tonic-gate	 */
2257c478bdstevel@tonic-gate	*eecd = *eecd & ~E1000_EECD_SK;
2267c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, EECD, *eecd);
2277c478bdstevel@tonic-gate	E1000_WRITE_FLUSH(hw);
2287c478bdstevel@tonic-gate	udelay(hw->eeprom.delay_usec);
2297c478bdstevel@tonic-gate}
2307c478bdstevel@tonic-gate
2317c478bdstevel@tonic-gate/******************************************************************************
2327c478bdstevel@tonic-gate * Shift data bits out to the EEPROM.
2337c478bdstevel@tonic-gate *
2347c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
2357c478bdstevel@tonic-gate * data - data to send to the EEPROM
2367c478bdstevel@tonic-gate * count - number of bits to shift out
2377c478bdstevel@tonic-gate *****************************************************************************/
2387c478bdstevel@tonic-gatestatic void
2397c478bdstevel@tonic-gatee1000_shift_out_ee_bits(struct e1000_hw *hw,
2407c478bdstevel@tonic-gate                        uint16_t data,
2417c478bdstevel@tonic-gate                        uint16_t count)
2427c478bdstevel@tonic-gate{
2437c478bdstevel@tonic-gate	struct e1000_eeprom_info *eeprom = &hw->eeprom;
2447c478bdstevel@tonic-gate	uint32_t eecd;
2457c478bdstevel@tonic-gate	uint32_t mask;
2467c478bdstevel@tonic-gate
2477c478bdstevel@tonic-gate	/* We need to shift "count" bits out to the EEPROM. So, value in the
2487c478bdstevel@tonic-gate	 * "data" parameter will be shifted out to the EEPROM one bit at a time.
2497c478bdstevel@tonic-gate	 * In order to do this, "data" must be broken down into bits.
2507c478bdstevel@tonic-gate	 */
2517c478bdstevel@tonic-gate	mask = 0x01 << (count - 1);
2527c478bdstevel@tonic-gate	eecd = E1000_READ_REG(hw, EECD);
2537c478bdstevel@tonic-gate	if (eeprom->type == e1000_eeprom_microwire) {
2547c478bdstevel@tonic-gate		eecd &= ~E1000_EECD_DO;
2557c478bdstevel@tonic-gate	} else if (eeprom->type == e1000_eeprom_spi) {
2567c478bdstevel@tonic-gate		eecd |= E1000_EECD_DO;
2577c478bdstevel@tonic-gate	}
2587c478bdstevel@tonic-gate	do {
2597c478bdstevel@tonic-gate		/* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
2607c478bdstevel@tonic-gate		 * and then raising and then lowering the clock (the SK bit controls
2617c478bdstevel@tonic-gate		 * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
2627c478bdstevel@tonic-gate		 * by setting "DI" to "0" and then raising and then lowering the clock.
2637c478bdstevel@tonic-gate		 */
2647c478bdstevel@tonic-gate		eecd &= ~E1000_EECD_DI;
2657c478bdstevel@tonic-gate
2667c478bdstevel@tonic-gate		if(data & mask)
2677c478bdstevel@tonic-gate			eecd |= E1000_EECD_DI;
2687c478bdstevel@tonic-gate
2697c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, EECD, eecd);
2707c478bdstevel@tonic-gate		E1000_WRITE_FLUSH(hw);
2717c478bdstevel@tonic-gate
2727c478bdstevel@tonic-gate		udelay(eeprom->delay_usec);
2737c478bdstevel@tonic-gate
2747c478bdstevel@tonic-gate		e1000_raise_ee_clk(hw, &eecd);
2757c478bdstevel@tonic-gate		e1000_lower_ee_clk(hw, &eecd);
2767c478bdstevel@tonic-gate
2777c478bdstevel@tonic-gate		mask = mask >> 1;
2787c478bdstevel@tonic-gate
2797c478bdstevel@tonic-gate	} while(mask);
2807c478bdstevel@tonic-gate
2817c478bdstevel@tonic-gate	/* We leave the "DI" bit set to "0" when we leave this routine. */
2827c478bdstevel@tonic-gate	eecd &= ~E1000_EECD_DI;
2837c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, EECD, eecd);
2847c478bdstevel@tonic-gate}
2857c478bdstevel@tonic-gate
2867c478bdstevel@tonic-gate/******************************************************************************
2877c478bdstevel@tonic-gate * Shift data bits in from the EEPROM
2887c478bdstevel@tonic-gate *
2897c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
2907c478bdstevel@tonic-gate *****************************************************************************/
2917c478bdstevel@tonic-gatestatic uint16_t
2927c478bdstevel@tonic-gatee1000_shift_in_ee_bits(struct e1000_hw *hw,
2937c478bdstevel@tonic-gate                       uint16_t count)
2947c478bdstevel@tonic-gate{
2957c478bdstevel@tonic-gate	uint32_t eecd;
2967c478bdstevel@tonic-gate	uint32_t i;
2977c478bdstevel@tonic-gate	uint16_t data;
2987c478bdstevel@tonic-gate
2997c478bdstevel@tonic-gate	/* In order to read a register from the EEPROM, we need to shift 'count'
3007c478bdstevel@tonic-gate	 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3017c478bdstevel@tonic-gate	 * input to the EEPROM (setting the SK bit), and then reading the value of
3027c478bdstevel@tonic-gate	 * the "DO" bit.  During this "shifting in" process the "DI" bit should
3037c478bdstevel@tonic-gate	 * always be clear.
3047c478bdstevel@tonic-gate	 */
3057c478bdstevel@tonic-gate
3067c478bdstevel@tonic-gate	eecd = E1000_READ_REG(hw, EECD);
3077c478bdstevel@tonic-gate
3087c478bdstevel@tonic-gate	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3097c478bdstevel@tonic-gate	data = 0;
3107c478bdstevel@tonic-gate
3117c478bdstevel@tonic-gate	for(i = 0; i < count; i++) {
3127c478bdstevel@tonic-gate		data = data << 1;
3137c478bdstevel@tonic-gate		e1000_raise_ee_clk(hw, &eecd);
3147c478bdstevel@tonic-gate
3157c478bdstevel@tonic-gate		eecd = E1000_READ_REG(hw, EECD);
3167c478bdstevel@tonic-gate
3177c478bdstevel@tonic-gate		eecd &= ~(E1000_EECD_DI);
3187c478bdstevel@tonic-gate		if(eecd & E1000_EECD_DO)
3197c478bdstevel@tonic-gate			data |= 1;
3207c478bdstevel@tonic-gate
3217c478bdstevel@tonic-gate		e1000_lower_ee_clk(hw, &eecd);
3227c478bdstevel@tonic-gate	}
3237c478bdstevel@tonic-gate
3247c478bdstevel@tonic-gate	return data;
3257c478bdstevel@tonic-gate}
3267c478bdstevel@tonic-gate
3277c478bdstevel@tonic-gate/******************************************************************************
3287c478bdstevel@tonic-gate * Prepares EEPROM for access
3297c478bdstevel@tonic-gate *
3307c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
3317c478bdstevel@tonic-gate *
3327c478bdstevel@tonic-gate * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3337c478bdstevel@tonic-gate * function should be called before issuing a command to the EEPROM.
3347c478bdstevel@tonic-gate *****************************************************************************/
3357c478bdstevel@tonic-gatestatic int32_t
3367c478bdstevel@tonic-gatee1000_acquire_eeprom(struct e1000_hw *hw)
3377c478bdstevel@tonic-gate{
3387c478bdstevel@tonic-gate	struct e1000_eeprom_info *eeprom = &hw->eeprom;
3397c478bdstevel@tonic-gate	uint32_t eecd, i=0;
3407c478bdstevel@tonic-gate
3417c478bdstevel@tonic-gate	eecd = E1000_READ_REG(hw, EECD);
3427c478bdstevel@tonic-gate
3437c478bdstevel@tonic-gate	/* Request EEPROM Access */
3447c478bdstevel@tonic-gate	if(hw->mac_type > e1000_82544) {
3457c478bdstevel@tonic-gate		eecd |= E1000_EECD_REQ;
3467c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, EECD, eecd);
3477c478bdstevel@tonic-gate		eecd = E1000_READ_REG(hw, EECD);
3487c478bdstevel@tonic-gate		while((!(eecd & E1000_EECD_GNT)) &&
3497c478bdstevel@tonic-gate		      (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3507c478bdstevel@tonic-gate			i++;
3517c478bdstevel@tonic-gate			udelay(5);
3527c478bdstevel@tonic-gate			eecd = E1000_READ_REG(hw, EECD);
3537c478bdstevel@tonic-gate		}
3547c478bdstevel@tonic-gate		if(!(eecd & E1000_EECD_GNT)) {
3557c478bdstevel@tonic-gate			eecd &= ~E1000_EECD_REQ;
3567c478bdstevel@tonic-gate			E1000_WRITE_REG(hw, EECD, eecd);
3577c478bdstevel@tonic-gate			DEBUGOUT("Could not acquire EEPROM grant\n");
3587c478bdstevel@tonic-gate			return -E1000_ERR_EEPROM;
3597c478bdstevel@tonic-gate		}
3607c478bdstevel@tonic-gate	}
3617c478bdstevel@tonic-gate
3627c478bdstevel@tonic-gate	/* Setup EEPROM for Read/Write */
3637c478bdstevel@tonic-gate
3647c478bdstevel@tonic-gate	if (eeprom->type == e1000_eeprom_microwire) {
3657c478bdstevel@tonic-gate		/* Clear SK and DI */
3667c478bdstevel@tonic-gate		eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3677c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, EECD, eecd);
3687c478bdstevel@tonic-gate
3697c478bdstevel@tonic-gate		/* Set CS */
3707c478bdstevel@tonic-gate		eecd |= E1000_EECD_CS;
3717c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, EECD, eecd);
3727c478bdstevel@tonic-gate	} else if (eeprom->type == e1000_eeprom_spi) {
3737c478bdstevel@tonic-gate		/* Clear SK and CS */
3747c478bdstevel@tonic-gate		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3757c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, EECD, eecd);
3767c478bdstevel@tonic-gate		udelay(1);
3777c478bdstevel@tonic-gate	}
3787c478bdstevel@tonic-gate
3797c478bdstevel@tonic-gate	return E1000_SUCCESS;
3807c478bdstevel@tonic-gate}
3817c478bdstevel@tonic-gate
3827c478bdstevel@tonic-gate/******************************************************************************
3837c478bdstevel@tonic-gate * Returns EEPROM to a "standby" state
3847c478bdstevel@tonic-gate *
3857c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
3867c478bdstevel@tonic-gate *****************************************************************************/
3877c478bdstevel@tonic-gatestatic void
3887c478bdstevel@tonic-gatee1000_standby_eeprom(struct e1000_hw *hw)
3897c478bdstevel@tonic-gate{
3907c478bdstevel@tonic-gate	struct e1000_eeprom_info *eeprom = &hw->eeprom;
3917c478bdstevel@tonic-gate	uint32_t eecd;
3927c478bdstevel@tonic-gate
3937c478bdstevel@tonic-gate	eecd = E1000_READ_REG(hw, EECD);
3947c478bdstevel@tonic-gate
3957c478bdstevel@tonic-gate	if(eeprom->type == e1000_eeprom_microwire) {
3967c478bdstevel@tonic-gate
3977c478bdstevel@tonic-gate		/* Deselect EEPROM */
3987c478bdstevel@tonic-gate		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3997c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, EECD, eecd);
4007c478bdstevel@tonic-gate		E1000_WRITE_FLUSH(hw);
4017c478bdstevel@tonic-gate		udelay(eeprom->delay_usec);
4027c478bdstevel@tonic-gate
4037c478bdstevel@tonic-gate		/* Clock high */
4047c478bdstevel@tonic-gate		eecd |= E1000_EECD_SK;
4057c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, EECD, eecd);
4067c478bdstevel@tonic-gate		E1000_WRITE_FLUSH(hw);
4077c478bdstevel@tonic-gate		udelay(eeprom->delay_usec);
4087c478bdstevel@tonic-gate
4097c478bdstevel@tonic-gate		/* Select EEPROM */
4107c478bdstevel@tonic-gate		eecd |= E1000_EECD_CS;
4117c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, EECD, eecd);
4127c478bdstevel@tonic-gate		E1000_WRITE_FLUSH(hw);
4137c478bdstevel@tonic-gate		udelay(eeprom->delay_usec);
4147c478bdstevel@tonic-gate
4157c478bdstevel@tonic-gate		/* Clock low */
4167c478bdstevel@tonic-gate		eecd &= ~E1000_EECD_SK;
4177c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, EECD, eecd);
4187c478bdstevel@tonic-gate		E1000_WRITE_FLUSH(hw);
4197c478bdstevel@tonic-gate		udelay(eeprom->delay_usec);
4207c478bdstevel@tonic-gate	} else if(eeprom->type == e1000_eeprom_spi) {
4217c478bdstevel@tonic-gate		/* Toggle CS to flush commands */
4227c478bdstevel@tonic-gate		eecd |= E1000_EECD_CS;
4237c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, EECD, eecd);
4247c478bdstevel@tonic-gate		E1000_WRITE_FLUSH(hw);
4257c478bdstevel@tonic-gate		udelay(eeprom->delay_usec);
4267c478bdstevel@tonic-gate		eecd &= ~E1000_EECD_CS;
4277c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, EECD, eecd);
4287c478bdstevel@tonic-gate		E1000_WRITE_FLUSH(hw);
4297c478bdstevel@tonic-gate		udelay(eeprom->delay_usec);
4307c478bdstevel@tonic-gate	}
4317c478bdstevel@tonic-gate}
4327c478bdstevel@tonic-gate
4337c478bdstevel@tonic-gate/******************************************************************************
4347c478bdstevel@tonic-gate * Terminates a command by inverting the EEPROM's chip select pin
4357c478bdstevel@tonic-gate *
4367c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
4377c478bdstevel@tonic-gate *****************************************************************************/
4387c478bdstevel@tonic-gatestatic void
4397c478bdstevel@tonic-gatee1000_release_eeprom(struct e1000_hw *hw)
4407c478bdstevel@tonic-gate{
4417c478bdstevel@tonic-gate	uint32_t eecd;
4427c478bdstevel@tonic-gate
4437c478bdstevel@tonic-gate	eecd = E1000_READ_REG(hw, EECD);
4447c478bdstevel@tonic-gate
4457c478bdstevel@tonic-gate	if (hw->eeprom.type == e1000_eeprom_spi) {
4467c478bdstevel@tonic-gate		eecd |= E1000_EECD_CS;  /* Pull CS high */
4477c478bdstevel@tonic-gate		eecd &= ~E1000_EECD_SK; /* Lower SCK */
4487c478bdstevel@tonic-gate
4497c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, EECD, eecd);
4507c478bdstevel@tonic-gate
4517c478bdstevel@tonic-gate		udelay(hw->eeprom.delay_usec);
4527c478bdstevel@tonic-gate	} else if(hw->eeprom.type == e1000_eeprom_microwire) {
4537c478bdstevel@tonic-gate		/* cleanup eeprom */
4547c478bdstevel@tonic-gate
4557c478bdstevel@tonic-gate		/* CS on Microwire is active-high */
4567c478bdstevel@tonic-gate		eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4577c478bdstevel@tonic-gate
4587c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, EECD, eecd);
4597c478bdstevel@tonic-gate
4607c478bdstevel@tonic-gate		/* Rising edge of clock */
4617c478bdstevel@tonic-gate		eecd |= E1000_EECD_SK;
4627c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, EECD, eecd);
4637c478bdstevel@tonic-gate		E1000_WRITE_FLUSH(hw);
4647c478bdstevel@tonic-gate		udelay(hw->eeprom.delay_usec);
4657c478bdstevel@tonic-gate
4667c478bdstevel@tonic-gate		/* Falling edge of clock */
4677c478bdstevel@tonic-gate		eecd &= ~E1000_EECD_SK;
4687c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, EECD, eecd);
4697c478bdstevel@tonic-gate		E1000_WRITE_FLUSH(hw);
4707c478bdstevel@tonic-gate		udelay(hw->eeprom.delay_usec);
4717c478bdstevel@tonic-gate	}
4727c478bdstevel@tonic-gate
4737c478bdstevel@tonic-gate	/* Stop requesting EEPROM access */
4747c478bdstevel@tonic-gate	if(hw->mac_type > e1000_82544) {
4757c478bdstevel@tonic-gate		eecd &= ~E1000_EECD_REQ;
4767c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, EECD, eecd);
4777c478bdstevel@tonic-gate	}
4787c478bdstevel@tonic-gate}
4797c478bdstevel@tonic-gate
4807c478bdstevel@tonic-gate/******************************************************************************
4817c478bdstevel@tonic-gate * Reads a 16 bit word from the EEPROM.
4827c478bdstevel@tonic-gate *
4837c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
4847c478bdstevel@tonic-gate *****************************************************************************/
4857c478bdstevel@tonic-gatestatic int32_t
4867c478bdstevel@tonic-gatee1000_spi_eeprom_ready(struct e1000_hw *hw)
4877c478bdstevel@tonic-gate{
4887c478bdstevel@tonic-gate	uint16_t retry_count = 0;
4897c478bdstevel@tonic-gate	uint8_t spi_stat_reg;
4907c478bdstevel@tonic-gate
4917c478bdstevel@tonic-gate	/* Read "Status Register" repeatedly until the LSB is cleared.  The
4927c478bdstevel@tonic-gate	 * EEPROM will signal that the command has been completed by clearing
4937c478bdstevel@tonic-gate	 * bit 0 of the internal status register.  If it's not cleared within
4947c478bdstevel@tonic-gate	 * 5 milliseconds, then error out.
4957c478bdstevel@tonic-gate	 */
4967c478bdstevel@tonic-gate	retry_count = 0;
4977c478bdstevel@tonic-gate	do {
4987c478bdstevel@tonic-gate		e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4997c478bdstevel@tonic-gate		hw->eeprom.opcode_bits);
5007c478bdstevel@tonic-gate		spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
5017c478bdstevel@tonic-gate		if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
5027c478bdstevel@tonic-gate			break;
5037c478bdstevel@tonic-gate
5047c478bdstevel@tonic-gate		udelay(5);
5057c478bdstevel@tonic-gate		retry_count += 5;
5067c478bdstevel@tonic-gate
5077c478bdstevel@tonic-gate	} while(retry_count < EEPROM_MAX_RETRY_SPI);
5087c478bdstevel@tonic-gate
5097c478bdstevel@tonic-gate	/* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
5107c478bdstevel@tonic-gate	 * only 0-5mSec on 5V devices)
5117c478bdstevel@tonic-gate	 */
5127c478bdstevel@tonic-gate	if(retry_count >= EEPROM_MAX_RETRY_SPI) {
5137c478bdstevel@tonic-gate		DEBUGOUT("SPI EEPROM Status error\n");
5147c478bdstevel@tonic-gate		return -E1000_ERR_EEPROM;
5157c478bdstevel@tonic-gate	}
5167c478bdstevel@tonic-gate
5177c478bdstevel@tonic-gate	return E1000_SUCCESS;
5187c478bdstevel@tonic-gate}
5197c478bdstevel@tonic-gate
5207c478bdstevel@tonic-gate/******************************************************************************
5217c478bdstevel@tonic-gate * Reads a 16 bit word from the EEPROM.
5227c478bdstevel@tonic-gate *
5237c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
5247c478bdstevel@tonic-gate * offset - offset of  word in the EEPROM to read
5257c478bdstevel@tonic-gate * data - word read from the EEPROM
5267c478bdstevel@tonic-gate * words - number of words to read
5277c478bdstevel@tonic-gate *****************************************************************************/
5287c478bdstevel@tonic-gatestatic int
5297c478bdstevel@tonic-gatee1000_read_eeprom(struct e1000_hw *hw,
5307c478bdstevel@tonic-gate                  uint16_t offset,
5317c478bdstevel@tonic-gate		  uint16_t words,
5327c478bdstevel@tonic-gate                  uint16_t *data)
5337c478bdstevel@tonic-gate{
5347c478bdstevel@tonic-gate	struct e1000_eeprom_info *eeprom = &hw->eeprom;
5357c478bdstevel@tonic-gate	uint32_t i = 0;
5367c478bdstevel@tonic-gate
5377c478bdstevel@tonic-gate	DEBUGFUNC("e1000_read_eeprom");
5387c478bdstevel@tonic-gate
5397c478bdstevel@tonic-gate	/* A check for invalid values:  offset too large, too many words, and not
5407c478bdstevel@tonic-gate	 * enough words.
5417c478bdstevel@tonic-gate	 */
5427c478bdstevel@tonic-gate	if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
5437c478bdstevel@tonic-gate	   (words == 0)) {
5447c478bdstevel@tonic-gate		DEBUGOUT("\"words\" parameter out of bounds\n");
5457c478bdstevel@tonic-gate		return -E1000_ERR_EEPROM;
5467c478bdstevel@tonic-gate	}
5477c478bdstevel@tonic-gate
5487c478bdstevel@tonic-gate	/*  Prepare the EEPROM for reading  */
5497c478bdstevel@tonic-gate	if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5507c478bdstevel@tonic-gate		return -E1000_ERR_EEPROM;
5517c478bdstevel@tonic-gate
5527c478bdstevel@tonic-gate	if(eeprom->type == e1000_eeprom_spi) {
5537c478bdstevel@tonic-gate		uint16_t word_in;
5547c478bdstevel@tonic-gate		uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
5557c478bdstevel@tonic-gate
5567c478bdstevel@tonic-gate		if(e1000_spi_eeprom_ready(hw)) {
5577c478bdstevel@tonic-gate			e1000_release_eeprom(hw);
5587c478bdstevel@tonic-gate			return -E1000_ERR_EEPROM;
5597c478bdstevel@tonic-gate		}
5607c478bdstevel@tonic-gate
5617c478bdstevel@tonic-gate		e1000_standby_eeprom(hw);
5627c478bdstevel@tonic-gate
5637c478bdstevel@tonic-gate		/* Some SPI eeproms use the 8th address bit embedded in the opcode */
5647c478bdstevel@tonic-gate		if((eeprom->address_bits == 8) && (offset >= 128))
5657c478bdstevel@tonic-gate			read_opcode |= EEPROM_A8_OPCODE_SPI;
5667c478bdstevel@tonic-gate
5677c478bdstevel@tonic-gate		/* Send the READ command (opcode + addr)  */
5687c478bdstevel@tonic-gate		e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
5697c478bdstevel@tonic-gate		e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
5707c478bdstevel@tonic-gate
5717c478bdstevel@tonic-gate		/* Read the data.  The address of the eeprom internally increments with
5727c478bdstevel@tonic-gate		 * each byte (spi) being read, saving on the overhead of eeprom setup
5737c478bdstevel@tonic-gate		 * and tear-down.  The address counter will roll over if reading beyond
5747c478bdstevel@tonic-gate		 * the size of the eeprom, thus allowing the entire memory to be read
5757c478bdstevel@tonic-gate		 * starting from any offset. */
5767c478bdstevel@tonic-gate		for (i = 0; i < words; i++) {
5777c478bdstevel@tonic-gate			word_in = e1000_shift_in_ee_bits(hw, 16);
5787c478bdstevel@tonic-gate			data[i] = (word_in >> 8) | (word_in << 8);
5797c478bdstevel@tonic-gate		}
5807c478bdstevel@tonic-gate	} else if(eeprom->type == e1000_eeprom_microwire) {
5817c478bdstevel@tonic-gate		for (i = 0; i < words; i++) {
5827c478bdstevel@tonic-gate			/*  Send the READ command (opcode + addr)  */
5837c478bdstevel@tonic-gate			e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
5847c478bdstevel@tonic-gate						eeprom->opcode_bits);
5857c478bdstevel@tonic-gate			e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
5867c478bdstevel@tonic-gate			                        eeprom->address_bits);
5877c478bdstevel@tonic-gate
5887c478bdstevel@tonic-gate			/* Read the data.  For microwire, each word requires the overhead
5897c478bdstevel@tonic-gate			 * of eeprom setup and tear-down. */
5907c478bdstevel@tonic-gate			data[i] = e1000_shift_in_ee_bits(hw, 16);
5917c478bdstevel@tonic-gate			e1000_standby_eeprom(hw);
5927c478bdstevel@tonic-gate		}
5937c478bdstevel@tonic-gate	}
5947c478bdstevel@tonic-gate
5957c478bdstevel@tonic-gate	/* End this read operation */
5967c478bdstevel@tonic-gate	e1000_release_eeprom(hw);
5977c478bdstevel@tonic-gate
5987c478bdstevel@tonic-gate	return E1000_SUCCESS;
5997c478bdstevel@tonic-gate}
6007c478bdstevel@tonic-gate
6017c478bdstevel@tonic-gate/******************************************************************************
6027c478bdstevel@tonic-gate * Verifies that the EEPROM has a valid checksum
6037c478bdstevel@tonic-gate *
6047c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
6057c478bdstevel@tonic-gate *
6067c478bdstevel@tonic-gate * Reads the first 64 16 bit words of the EEPROM and sums the values read.
6077c478bdstevel@tonic-gate * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
6087c478bdstevel@tonic-gate * valid.
6097c478bdstevel@tonic-gate *****************************************************************************/
6107c478bdstevel@tonic-gatestatic int
6117c478bdstevel@tonic-gatee1000_validate_eeprom_checksum(struct e1000_hw *hw)
6127c478bdstevel@tonic-gate{
6137c478bdstevel@tonic-gate	uint16_t checksum = 0;
6147c478bdstevel@tonic-gate	uint16_t i, eeprom_data;
6157c478bdstevel@tonic-gate
6167c478bdstevel@tonic-gate	DEBUGFUNC("e1000_validate_eeprom_checksum");
6177c478bdstevel@tonic-gate
6187c478bdstevel@tonic-gate	for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
6197c478bdstevel@tonic-gate		if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
6207c478bdstevel@tonic-gate			DEBUGOUT("EEPROM Read Error\n");
6217c478bdstevel@tonic-gate			return -E1000_ERR_EEPROM;
6227c478bdstevel@tonic-gate		}
6237c478bdstevel@tonic-gate		checksum += eeprom_data;
6247c478bdstevel@tonic-gate	}
6257c478bdstevel@tonic-gate
6267c478bdstevel@tonic-gate	if(checksum == (uint16_t) EEPROM_SUM)
6277c478bdstevel@tonic-gate		return E1000_SUCCESS;
6287c478bdstevel@tonic-gate	else {
6297c478bdstevel@tonic-gate		DEBUGOUT("EEPROM Checksum Invalid\n");
6307c478bdstevel@tonic-gate		return -E1000_ERR_EEPROM;
6317c478bdstevel@tonic-gate	}
6327c478bdstevel@tonic-gate}
6337c478bdstevel@tonic-gate
6347c478bdstevel@tonic-gate/******************************************************************************
6357c478bdstevel@tonic-gate * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
6367c478bdstevel@tonic-gate * second function of dual function devices
6377c478bdstevel@tonic-gate *
6387c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
6397c478bdstevel@tonic-gate *****************************************************************************/
6407c478bdstevel@tonic-gatestatic int
6417c478bdstevel@tonic-gatee1000_read_mac_addr(struct e1000_hw *hw)
6427c478bdstevel@tonic-gate{
6437c478bdstevel@tonic-gate	uint16_t offset;
6447c478bdstevel@tonic-gate	uint16_t eeprom_data;
6457c478bdstevel@tonic-gate	int i;
6467c478bdstevel@tonic-gate
6477c478bdstevel@tonic-gate	DEBUGFUNC("e1000_read_mac_addr");
6487c478bdstevel@tonic-gate
6497c478bdstevel@tonic-gate	for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
6507c478bdstevel@tonic-gate		offset = i >> 1;
6517c478bdstevel@tonic-gate		if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
6527c478bdstevel@tonic-gate			DEBUGOUT("EEPROM Read Error\n");
6537c478bdstevel@tonic-gate			return -E1000_ERR_EEPROM;
6547c478bdstevel@tonic-gate		}
6557c478bdstevel@tonic-gate		hw->mac_addr[i] = eeprom_data & 0xff;
6567c478bdstevel@tonic-gate		hw->mac_addr[i+1] = (eeprom_data >> 8) & 0xff;
6577c478bdstevel@tonic-gate	}
6587c478bdstevel@tonic-gate	if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
6597c478bdstevel@tonic-gate		(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
6607c478bdstevel@tonic-gate		/* Invert the last bit if this is the second device */
6617c478bdstevel@tonic-gate		hw->mac_addr[5] ^= 1;
6627c478bdstevel@tonic-gate	return E1000_SUCCESS;
6637c478bdstevel@tonic-gate}
6647c478bdstevel@tonic-gate
6657c478bdstevel@tonic-gate/******************************************************************************
6667c478bdstevel@tonic-gate * Initializes receive address filters.
6677c478bdstevel@tonic-gate *
6687c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
6697c478bdstevel@tonic-gate *
6707c478bdstevel@tonic-gate * Places the MAC address in receive address register 0 and clears the rest
6717c478bdstevel@tonic-gate * of the receive addresss registers. Clears the multicast table. Assumes
6727c478bdstevel@tonic-gate * the receiver is in reset when the routine is called.
6737c478bdstevel@tonic-gate *****************************************************************************/
6747c478bdstevel@tonic-gatestatic void
6757c478bdstevel@tonic-gatee1000_init_rx_addrs(struct e1000_hw *hw)
6767c478bdstevel@tonic-gate{
6777c478bdstevel@tonic-gate	uint32_t i;
6787c478bdstevel@tonic-gate	uint32_t addr_low;
6797c478bdstevel@tonic-gate	uint32_t addr_high;
6807c478bdstevel@tonic-gate
6817c478bdstevel@tonic-gate	DEBUGFUNC("e1000_init_rx_addrs");
6827c478bdstevel@tonic-gate
6837c478bdstevel@tonic-gate	/* Setup the receive address. */
6847c478bdstevel@tonic-gate	DEBUGOUT("Programming MAC Address into RAR[0]\n");
6857c478bdstevel@tonic-gate	addr_low = (hw->mac_addr[0] |
6867c478bdstevel@tonic-gate		(hw->mac_addr[1] << 8) |
6877c478bdstevel@tonic-gate		(hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
6887c478bdstevel@tonic-gate
6897c478bdstevel@tonic-gate	addr_high = (hw->mac_addr[4] |
6907c478bdstevel@tonic-gate		(hw->mac_addr[5] << 8) | E1000_RAH_AV);
6917c478bdstevel@tonic-gate
6927c478bdstevel@tonic-gate	E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
6937c478bdstevel@tonic-gate	E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
6947c478bdstevel@tonic-gate
6957c478bdstevel@tonic-gate	/* Zero out the other 15 receive addresses. */
6967c478bdstevel@tonic-gate	DEBUGOUT("Clearing RAR[1-15]\n");
6977c478bdstevel@tonic-gate	for(i = 1; i < E1000_RAR_ENTRIES; i++) {
6987c478bdstevel@tonic-gate		E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
6997c478bdstevel@tonic-gate		E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
7007c478bdstevel@tonic-gate	}
7017c478bdstevel@tonic-gate}
7027c478bdstevel@tonic-gate
7037c478bdstevel@tonic-gate/******************************************************************************
7047c478bdstevel@tonic-gate * Clears the VLAN filer table
7057c478bdstevel@tonic-gate *
7067c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
7077c478bdstevel@tonic-gate *****************************************************************************/
7087c478bdstevel@tonic-gatestatic void
7097c478bdstevel@tonic-gatee1000_clear_vfta(struct e1000_hw *hw)
7107c478bdstevel@tonic-gate{
7117c478bdstevel@tonic-gate	uint32_t offset;
7127c478bdstevel@tonic-gate
7137c478bdstevel@tonic-gate	for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
7147c478bdstevel@tonic-gate		E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
7157c478bdstevel@tonic-gate}
7167c478bdstevel@tonic-gate
7177c478bdstevel@tonic-gate/******************************************************************************
7187c478bdstevel@tonic-gate* Writes a value to one of the devices registers using port I/O (as opposed to
7197c478bdstevel@tonic-gate* memory mapped I/O). Only 82544 and newer devices support port I/O. *
7207c478bdstevel@tonic-gate* hw - Struct containing variables accessed by shared code
7217c478bdstevel@tonic-gate* offset - offset to write to * value - value to write
7227c478bdstevel@tonic-gate*****************************************************************************/
7237c478bdstevel@tonic-gatevoid e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value){
7247c478bdstevel@tonic-gate	uint32_t io_addr = hw->io_base;
7257c478bdstevel@tonic-gate	uint32_t io_data = hw->io_base + 4;
7267c478bdstevel@tonic-gate	e1000_io_write(hw, io_addr, offset);
7277c478bdstevel@tonic-gate	e1000_io_write(hw, io_data, value);
7287c478bdstevel@tonic-gate}
7297c478bdstevel@tonic-gate
7307c478bdstevel@tonic-gate/******************************************************************************
7317c478bdstevel@tonic-gate * Set the phy type member in the hw struct.
7327c478bdstevel@tonic-gate *
7337c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
7347c478bdstevel@tonic-gate *****************************************************************************/
7357c478bdstevel@tonic-gatestatic int32_t
7367c478bdstevel@tonic-gatee1000_set_phy_type(struct e1000_hw *hw)
7377c478bdstevel@tonic-gate{
7387c478bdstevel@tonic-gate	DEBUGFUNC("e1000_set_phy_type");
7397c478bdstevel@tonic-gate
7407c478bdstevel@tonic-gate	switch(hw->phy_id) {
7417c478bdstevel@tonic-gate	case M88E1000_E_PHY_ID:
7427c478bdstevel@tonic-gate	case M88E1000_I_PHY_ID:
7437c478bdstevel@tonic-gate	case M88E1011_I_PHY_ID:
7447c478bdstevel@tonic-gate		hw->phy_type = e1000_phy_m88;
7457c478bdstevel@tonic-gate		break;
7467c478bdstevel@tonic-gate	case IGP01E1000_I_PHY_ID:
7477c478bdstevel@tonic-gate		hw->phy_type = e1000_phy_igp;
7487c478bdstevel@tonic-gate		break;
7497c478bdstevel@tonic-gate	default:
7507c478bdstevel@tonic-gate		/* Should never have loaded on this device */
7517c478bdstevel@tonic-gate		hw->phy_type = e1000_phy_undefined;
7527c478bdstevel@tonic-gate		return -E1000_ERR_PHY_TYPE;
7537c478bdstevel@tonic-gate	}
7547c478bdstevel@tonic-gate
7557c478bdstevel@tonic-gate	return E1000_SUCCESS;
7567c478bdstevel@tonic-gate}
7577c478bdstevel@tonic-gate
7587c478bdstevel@tonic-gate/******************************************************************************
7597c478bdstevel@tonic-gate * IGP phy init script - initializes the GbE PHY
7607c478bdstevel@tonic-gate *
7617c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
7627c478bdstevel@tonic-gate *****************************************************************************/
7637c478bdstevel@tonic-gatestatic void
7647c478bdstevel@tonic-gatee1000_phy_init_script(struct e1000_hw *hw)
7657c478bdstevel@tonic-gate{
7667c478bdstevel@tonic-gate	DEBUGFUNC("e1000_phy_init_script");
7677c478bdstevel@tonic-gate
7687c478bdstevel@tonic-gate#if 0
7697c478bdstevel@tonic-gate	/* See e1000_sw_init() of the Linux driver */
7707c478bdstevel@tonic-gate	if(hw->phy_init_script) {
7717c478bdstevel@tonic-gate#else
7727c478bdstevel@tonic-gate	if((hw->mac_type == e1000_82541) ||
7737c478bdstevel@tonic-gate	   (hw->mac_type == e1000_82547) ||
7747c478bdstevel@tonic-gate	   (hw->mac_type == e1000_82541_rev_2) ||
7757c478bdstevel@tonic-gate	   (hw->mac_type == e1000_82547_rev_2)) {
7767c478bdstevel@tonic-gate#endif
7777c478bdstevel@tonic-gate		mdelay(20);
7787c478bdstevel@tonic-gate
7797c478bdstevel@tonic-gate		e1000_write_phy_reg(hw,0x0000,0x0140);
7807c478bdstevel@tonic-gate
7817c478bdstevel@tonic-gate		mdelay(5);
7827c478bdstevel@tonic-gate
7837c478bdstevel@tonic-gate		if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) {
7847c478bdstevel@tonic-gate			e1000_write_phy_reg(hw, 0x1F95, 0x0001);
7857c478bdstevel@tonic-gate
7867c478bdstevel@tonic-gate			e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
7877c478bdstevel@tonic-gate
7887c478bdstevel@tonic-gate			e1000_write_phy_reg(hw, 0x1F79, 0x0018);
7897c478bdstevel@tonic-gate
7907c478bdstevel@tonic-gate			e1000_write_phy_reg(hw, 0x1F30, 0x1600);
7917c478bdstevel@tonic-gate
7927c478bdstevel@tonic-gate			e1000_write_phy_reg(hw, 0x1F31, 0x0014);
7937c478bdstevel@tonic-gate
7947c478bdstevel@tonic-gate			e1000_write_phy_reg(hw, 0x1F32, 0x161C);
7957c478bdstevel@tonic-gate
7967c478bdstevel@tonic-gate			e1000_write_phy_reg(hw, 0x1F94, 0x0003);
7977c478bdstevel@tonic-gate
7987c478bdstevel@tonic-gate			e1000_write_phy_reg(hw, 0x1F96, 0x003F);
7997c478bdstevel@tonic-gate
8007c478bdstevel@tonic-gate			e1000_write_phy_reg(hw, 0x2010, 0x0008);
8017c478bdstevel@tonic-gate		} else {
8027c478bdstevel@tonic-gate			e1000_write_phy_reg(hw, 0x1F73, 0x0099);
8037c478bdstevel@tonic-gate		}
8047c478bdstevel@tonic-gate
8057c478bdstevel@tonic-gate		e1000_write_phy_reg(hw, 0x0000, 0x3300);
8067c478bdstevel@tonic-gate
8077c478bdstevel@tonic-gate
8087c478bdstevel@tonic-gate		if(hw->mac_type == e1000_82547) {
8097c478bdstevel@tonic-gate			uint16_t fused, fine, coarse;
8107c478bdstevel@tonic-gate
8117c478bdstevel@tonic-gate			/* Move to analog registers page */
8127c478bdstevel@tonic-gate			e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
8137c478bdstevel@tonic-gate
8147c478bdstevel@tonic-gate			if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
8157c478bdstevel@tonic-gate				e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
8167c478bdstevel@tonic-gate
8177c478bdstevel@tonic-gate				fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
8187c478bdstevel@tonic-gate				coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
8197c478bdstevel@tonic-gate
8207c478bdstevel@tonic-gate				if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
8217c478bdstevel@tonic-gate					coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
8227c478bdstevel@tonic-gate					fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
8237c478bdstevel@tonic-gate				} else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
8247c478bdstevel@tonic-gate					fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
8257c478bdstevel@tonic-gate
8267c478bdstevel@tonic-gate				fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
8277c478bdstevel@tonic-gate					(fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
8287c478bdstevel@tonic-gate					(coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
8297c478bdstevel@tonic-gate
8307c478bdstevel@tonic-gate				e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
8317c478bdstevel@tonic-gate				e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
8327c478bdstevel@tonic-gate						IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
8337c478bdstevel@tonic-gate			}
8347c478bdstevel@tonic-gate		}
8357c478bdstevel@tonic-gate	}
8367c478bdstevel@tonic-gate}
8377c478bdstevel@tonic-gate
8387c478bdstevel@tonic-gate/******************************************************************************
8397c478bdstevel@tonic-gate * Set the mac type member in the hw struct.
8407c478bdstevel@tonic-gate *
8417c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
8427c478bdstevel@tonic-gate *****************************************************************************/
8437c478bdstevel@tonic-gatestatic int
8447c478bdstevel@tonic-gatee1000_set_mac_type(struct e1000_hw *hw)
8457c478bdstevel@tonic-gate{
8467c478bdstevel@tonic-gate	DEBUGFUNC("e1000_set_mac_type");
8477c478bdstevel@tonic-gate
8487c478bdstevel@tonic-gate	switch (hw->device_id) {
8497c478bdstevel@tonic-gate	case E1000_DEV_ID_82542:
8507c478bdstevel@tonic-gate		switch (hw->revision_id) {
8517c478bdstevel@tonic-gate		case E1000_82542_2_0_REV_ID:
8527c478bdstevel@tonic-gate			hw->mac_type = e1000_82542_rev2_0;
8537c478bdstevel@tonic-gate			break;
8547c478bdstevel@tonic-gate		case E1000_82542_2_1_REV_ID:
8557c478bdstevel@tonic-gate			hw->mac_type = e1000_82542_rev2_1;
8567c478bdstevel@tonic-gate			break;
8577c478bdstevel@tonic-gate		default:
8587c478bdstevel@tonic-gate			/* Invalid 82542 revision ID */
8597c478bdstevel@tonic-gate			return -E1000_ERR_MAC_TYPE;
8607c478bdstevel@tonic-gate		}
8617c478bdstevel@tonic-gate		break;
8627c478bdstevel@tonic-gate	case E1000_DEV_ID_82543GC_FIBER:
8637c478bdstevel@tonic-gate	case E1000_DEV_ID_82543GC_COPPER:
8647c478bdstevel@tonic-gate		hw->mac_type = e1000_82543;
8657c478bdstevel@tonic-gate		break;
8667c478bdstevel@tonic-gate	case E1000_DEV_ID_82544EI_COPPER:
8677c478bdstevel@tonic-gate	case E1000_DEV_ID_82544EI_FIBER:
8687c478bdstevel@tonic-gate	case E1000_DEV_ID_82544GC_COPPER:
8697c478bdstevel@tonic-gate	case E1000_DEV_ID_82544GC_LOM:
8707c478bdstevel@tonic-gate		hw->mac_type = e1000_82544;
8717c478bdstevel@tonic-gate		break;
8727c478bdstevel@tonic-gate	case E1000_DEV_ID_82540EM:
8737c478bdstevel@tonic-gate	case E1000_DEV_ID_82540EM_LOM:
8747c478bdstevel@tonic-gate	case E1000_DEV_ID_82540EP:
8757c478bdstevel@tonic-gate	case E1000_DEV_ID_82540EP_LOM:
8767c478bdstevel@tonic-gate	case E1000_DEV_ID_82540EP_LP:
8777c478bdstevel@tonic-gate		hw->mac_type = e1000_82540;
8787c478bdstevel@tonic-gate		break;
8797c478bdstevel@tonic-gate	case E1000_DEV_ID_82545EM_COPPER:
8807c478bdstevel@tonic-gate	case E1000_DEV_ID_82545EM_FIBER:
8817c478bdstevel@tonic-gate		hw->mac_type = e1000_82545;
8827c478bdstevel@tonic-gate		break;
8837c478bdstevel@tonic-gate	case E1000_DEV_ID_82545GM_COPPER:
8847c478bdstevel@tonic-gate	case E1000_DEV_ID_82545GM_FIBER:
8857c478bdstevel@tonic-gate	case E1000_DEV_ID_82545GM_SERDES:
8867c478bdstevel@tonic-gate		hw->mac_type = e1000_82545_rev_3;
8877c478bdstevel@tonic-gate		break;
8887c478bdstevel@tonic-gate	case E1000_DEV_ID_82546EB_COPPER:
8897c478bdstevel@tonic-gate	case E1000_DEV_ID_82546EB_FIBER:
8907c478bdstevel@tonic-gate	case E1000_DEV_ID_82546EB_QUAD_COPPER:
8917c478bdstevel@tonic-gate		hw->mac_type = e1000_82546;
8927c478bdstevel@tonic-gate		break;
8937c478bdstevel@tonic-gate	case E1000_DEV_ID_82546GB_COPPER:
8947c478bdstevel@tonic-gate	case E1000_DEV_ID_82546GB_FIBER:
8957c478bdstevel@tonic-gate	case E1000_DEV_ID_82546GB_SERDES:
8967c478bdstevel@tonic-gate		hw->mac_type = e1000_82546_rev_3;
8977c478bdstevel@tonic-gate		break;
8987c478bdstevel@tonic-gate	case E1000_DEV_ID_82541EI:
8997c478bdstevel@tonic-gate	case E1000_DEV_ID_82541EI_MOBILE:
9007c478bdstevel@tonic-gate		hw->mac_type = e1000_82541;
9017c478bdstevel@tonic-gate		break;
9027c478bdstevel@tonic-gate	case E1000_DEV_ID_82541ER:
9037c478bdstevel@tonic-gate	case E1000_DEV_ID_82541GI:
9047c478bdstevel@tonic-gate	case E1000_DEV_ID_82541GI_MOBILE:
9057c478bdstevel@tonic-gate		hw->mac_type = e1000_82541_rev_2;
9067c478bdstevel@tonic-gate		break;
9077c478bdstevel@tonic-gate	case E1000_DEV_ID_82547EI:
9087c478bdstevel@tonic-gate		hw->mac_type = e1000_82547;
9097c478bdstevel@tonic-gate		break;
9107c478bdstevel@tonic-gate	case E1000_DEV_ID_82547GI:
9117c478bdstevel@tonic-gate		hw->mac_type = e1000_82547_rev_2;
9127c478bdstevel@tonic-gate		break;
9137c478bdstevel@tonic-gate	default:
9147c478bdstevel@tonic-gate		/* Should never have loaded on this device */
9157c478bdstevel@tonic-gate		return -E1000_ERR_MAC_TYPE;
9167c478bdstevel@tonic-gate	}
9177c478bdstevel@tonic-gate
9187c478bdstevel@tonic-gate	return E1000_SUCCESS;
9197c478bdstevel@tonic-gate}
9207c478bdstevel@tonic-gate
9217c478bdstevel@tonic-gate/*****************************************************************************
9227c478bdstevel@tonic-gate * Set media type and TBI compatibility.
9237c478bdstevel@tonic-gate *
9247c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
9257c478bdstevel@tonic-gate * **************************************************************************/
9267c478bdstevel@tonic-gatestatic void
9277c478bdstevel@tonic-gatee1000_set_media_type(struct e1000_hw *hw)
9287c478bdstevel@tonic-gate{
9297c478bdstevel@tonic-gate	uint32_t status;
9307c478bdstevel@tonic-gate
9317c478bdstevel@tonic-gate	DEBUGFUNC("e1000_set_media_type");
9327c478bdstevel@tonic-gate
9337c478bdstevel@tonic-gate	if(hw->mac_type != e1000_82543) {
9347c478bdstevel@tonic-gate		/* tbi_compatibility is only valid on 82543 */
9357c478bdstevel@tonic-gate		hw->tbi_compatibility_en = FALSE;
9367c478bdstevel@tonic-gate	}
9377c478bdstevel@tonic-gate
9387c478bdstevel@tonic-gate	switch (hw->device_id) {
9397c478bdstevel@tonic-gate		case E1000_DEV_ID_82545GM_SERDES:
9407c478bdstevel@tonic-gate		case E1000_DEV_ID_82546GB_SERDES:
9417c478bdstevel@tonic-gate			hw->media_type = e1000_media_type_internal_serdes;
9427c478bdstevel@tonic-gate			break;
9437c478bdstevel@tonic-gate		default:
9447c478bdstevel@tonic-gate			if(hw->mac_type >= e1000_82543) {
9457c478bdstevel@tonic-gate				status = E1000_READ_REG(hw, STATUS);
9467c478bdstevel@tonic-gate				if(status & E1000_STATUS_TBIMODE) {
9477c478bdstevel@tonic-gate					hw->media_type = e1000_media_type_fiber;
9487c478bdstevel@tonic-gate					/* tbi_compatibility not valid on fiber */
9497c478bdstevel@tonic-gate					hw->tbi_compatibility_en = FALSE;
9507c478bdstevel@tonic-gate				} else {
9517c478bdstevel@tonic-gate					hw->media_type = e1000_media_type_copper;
9527c478bdstevel@tonic-gate				}
9537c478bdstevel@tonic-gate			} else {
9547c478bdstevel@tonic-gate				/* This is an 82542 (fiber only) */
9557c478bdstevel@tonic-gate				hw->media_type = e1000_media_type_fiber;
9567c478bdstevel@tonic-gate			}
9577c478bdstevel@tonic-gate	}
9587c478bdstevel@tonic-gate}
9597c478bdstevel@tonic-gate
9607c478bdstevel@tonic-gate/******************************************************************************
9617c478bdstevel@tonic-gate * Reset the transmit and receive units; mask and clear all interrupts.
9627c478bdstevel@tonic-gate *
9637c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
9647c478bdstevel@tonic-gate *****************************************************************************/
9657c478bdstevel@tonic-gatestatic void
9667c478bdstevel@tonic-gatee1000_reset_hw(struct e1000_hw *hw)
9677c478bdstevel@tonic-gate{
9687c478bdstevel@tonic-gate	uint32_t ctrl;
9697c478bdstevel@tonic-gate	uint32_t ctrl_ext;
9707c478bdstevel@tonic-gate	uint32_t icr;
9717c478bdstevel@tonic-gate	uint32_t manc;
9727c478bdstevel@tonic-gate
9737c478bdstevel@tonic-gate	DEBUGFUNC("e1000_reset_hw");
9747c478bdstevel@tonic-gate
9757c478bdstevel@tonic-gate	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
9767c478bdstevel@tonic-gate	if(hw->mac_type == e1000_82542_rev2_0) {
9777c478bdstevel@tonic-gate		DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
9787c478bdstevel@tonic-gate		e1000_pci_clear_mwi(hw);
9797c478bdstevel@tonic-gate	}
9807c478bdstevel@tonic-gate
9817c478bdstevel@tonic-gate	/* Clear interrupt mask to stop board from generating interrupts */
9827c478bdstevel@tonic-gate	DEBUGOUT("Masking off all interrupts\n");
9837c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, IMC, 0xffffffff);
9847c478bdstevel@tonic-gate
9857c478bdstevel@tonic-gate	/* Disable the Transmit and Receive units.  Then delay to allow
9867c478bdstevel@tonic-gate	 * any pending transactions to complete before we hit the MAC with
9877c478bdstevel@tonic-gate	 * the global reset.
9887c478bdstevel@tonic-gate	 */
9897c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, RCTL, 0);
9907c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
9917c478bdstevel@tonic-gate	E1000_WRITE_FLUSH(hw);
9927c478bdstevel@tonic-gate
9937c478bdstevel@tonic-gate	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
9947c478bdstevel@tonic-gate	hw->tbi_compatibility_on = FALSE;
9957c478bdstevel@tonic-gate
9967c478bdstevel@tonic-gate	/* Delay to allow any outstanding PCI transactions to complete before
9977c478bdstevel@tonic-gate	 * resetting the device
9987c478bdstevel@tonic-gate	 */
9997c478bdstevel@tonic-gate	mdelay(10);
10007c478bdstevel@tonic-gate
10017c478bdstevel@tonic-gate	ctrl = E1000_READ_REG(hw, CTRL);
10027c478bdstevel@tonic-gate
10037c478bdstevel@tonic-gate	/* Must reset the PHY before resetting the MAC */
10047c478bdstevel@tonic-gate	if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
10057c478bdstevel@tonic-gate		E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
10067c478bdstevel@tonic-gate		mdelay(5);
10077c478bdstevel@tonic-gate	}
10087c478bdstevel@tonic-gate
10097c478bdstevel@tonic-gate	/* Issue a global reset to the MAC.  This will reset the chip's
10107c478bdstevel@tonic-gate	 * transmit, receive, DMA, and link units.  It will not effect
10117c478bdstevel@tonic-gate	 * the current PCI configuration.  The global reset bit is self-
10127c478bdstevel@tonic-gate	 * clearing, and should clear within a microsecond.
10137c478bdstevel@tonic-gate	 */
10147c478bdstevel@tonic-gate	DEBUGOUT("Issuing a global reset to MAC\n");
10157c478bdstevel@tonic-gate
10167c478bdstevel@tonic-gate	switch(hw->mac_type) {
10177c478bdstevel@tonic-gate		case e1000_82544:
10187c478bdstevel@tonic-gate		case e1000_82540:
10197c478bdstevel@tonic-gate		case e1000_82545:
10207c478bdstevel@tonic-gate		case e1000_82546:
10217c478bdstevel@tonic-gate		case e1000_82541:
10227c478bdstevel@tonic-gate		case e1000_82541_rev_2:
10237c478bdstevel@tonic-gate			/* These controllers can't ack the 64-bit write when issuing the
10247c478bdstevel@tonic-gate			 * reset, so use IO-mapping as a workaround to issue the reset */
10257c478bdstevel@tonic-gate			E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
10267c478bdstevel@tonic-gate			break;
10277c478bdstevel@tonic-gate		case e1000_82545_rev_3:
10287c478bdstevel@tonic-gate		case e1000_82546_rev_3:
10297c478bdstevel@tonic-gate			/* Reset is performed on a shadow of the control register */
10307c478bdstevel@tonic-gate			E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
10317c478bdstevel@tonic-gate			break;
10327c478bdstevel@tonic-gate		default:
10337c478bdstevel@tonic-gate			E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
10347c478bdstevel@tonic-gate			break;
10357c478bdstevel@tonic-gate	}
10367c478bdstevel@tonic-gate
10377c478bdstevel@tonic-gate	/* After MAC reset, force reload of EEPROM to restore power-on settings to
10387c478bdstevel@tonic-gate	 * device.  Later controllers reload the EEPROM automatically, so just wait
10397c478bdstevel@tonic-gate	 * for reload to complete.
10407c478bdstevel@tonic-gate	 */
10417c478bdstevel@tonic-gate	switch(hw->mac_type) {
10427c478bdstevel@tonic-gate		case e1000_82542_rev2_0:
10437c478bdstevel@tonic-gate		case e1000_82542_rev2_1:
10447c478bdstevel@tonic-gate		case e1000_82543:
10457c478bdstevel@tonic-gate		case e1000_82544:
10467c478bdstevel@tonic-gate			/* Wait for reset to complete */
10477c478bdstevel@tonic-gate			udelay(10);
10487c478bdstevel@tonic-gate			ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
10497c478bdstevel@tonic-gate			ctrl_ext |= E1000_CTRL_EXT_EE_RST;
10507c478bdstevel@tonic-gate			E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
10517c478bdstevel@tonic-gate			E1000_WRITE_FLUSH(hw);
10527c478bdstevel@tonic-gate			/* Wait for EEPROM reload */
10537c478bdstevel@tonic-gate			mdelay(2);
10547c478bdstevel@tonic-gate			break;
10557c478bdstevel@tonic-gate		case e1000_82541:
10567c478bdstevel@tonic-gate		case e1000_82541_rev_2:
10577c478bdstevel@tonic-gate		case e1000_82547:
10587c478bdstevel@tonic-gate		case e1000_82547_rev_2:
10597c478bdstevel@tonic-gate			/* Wait for EEPROM reload */
10607c478bdstevel@tonic-gate			mdelay(20);
10617c478bdstevel@tonic-gate			break;
10627c478bdstevel@tonic-gate		default:
10637c478bdstevel@tonic-gate			/* Wait for EEPROM reload (it happens automatically) */
10647c478bdstevel@tonic-gate			mdelay(5);
10657c478bdstevel@tonic-gate			break;
10667c478bdstevel@tonic-gate	}
10677c478bdstevel@tonic-gate
10687c478bdstevel@tonic-gate	/* Disable HW ARPs on ASF enabled adapters */
10697c478bdstevel@tonic-gate	if(hw->mac_type >= e1000_82540) {
10707c478bdstevel@tonic-gate		manc = E1000_READ_REG(hw, MANC);
10717c478bdstevel@tonic-gate		manc &= ~(E1000_MANC_ARP_EN);
10727c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, MANC, manc);
10737c478bdstevel@tonic-gate	}
10747c478bdstevel@tonic-gate
10757c478bdstevel@tonic-gate	if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
10767c478bdstevel@tonic-gate		e1000_phy_init_script(hw);
10777c478bdstevel@tonic-gate	}
10787c478bdstevel@tonic-gate
10797c478bdstevel@tonic-gate	/* Clear interrupt mask to stop board from generating interrupts */
10807c478bdstevel@tonic-gate	DEBUGOUT("Masking off all interrupts\n");
10817c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, IMC, 0xffffffff);
10827c478bdstevel@tonic-gate
10837c478bdstevel@tonic-gate	/* Clear any pending interrupt events. */
10847c478bdstevel@tonic-gate	icr = E1000_READ_REG(hw, ICR);
10857c478bdstevel@tonic-gate
10867c478bdstevel@tonic-gate	/* If MWI was previously enabled, reenable it. */
10877c478bdstevel@tonic-gate	if(hw->mac_type == e1000_82542_rev2_0) {
10887c478bdstevel@tonic-gate#ifdef LINUX_DRIVER
10897c478bdstevel@tonic-gate		if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
10907c478bdstevel@tonic-gate#endif
10917c478bdstevel@tonic-gate			e1000_pci_set_mwi(hw);
10927c478bdstevel@tonic-gate	}
10937c478bdstevel@tonic-gate}
10947c478bdstevel@tonic-gate
10957c478bdstevel@tonic-gate/******************************************************************************
10967c478bdstevel@tonic-gate * Performs basic configuration of the adapter.
10977c478bdstevel@tonic-gate *
10987c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
10997c478bdstevel@tonic-gate *
11007c478bdstevel@tonic-gate * Assumes that the controller has previously been reset and is in a
11017c478bdstevel@tonic-gate * post-reset uninitialized state. Initializes the receive address registers,
11027c478bdstevel@tonic-gate * multicast table, and VLAN filter table. Calls routines to setup link
11037c478bdstevel@tonic-gate * configuration and flow control settings. Clears all on-chip counters. Leaves
11047c478bdstevel@tonic-gate * the transmit and receive units disabled and uninitialized.
11057c478bdstevel@tonic-gate *****************************************************************************/
11067c478bdstevel@tonic-gatestatic int
11077c478bdstevel@tonic-gatee1000_init_hw(struct e1000_hw *hw)
11087c478bdstevel@tonic-gate{
11097c478bdstevel@tonic-gate	uint32_t ctrl, status;
11107c478bdstevel@tonic-gate	uint32_t i;
11117c478bdstevel@tonic-gate	int32_t ret_val;
11127c478bdstevel@tonic-gate	uint16_t pcix_cmd_word;
11137c478bdstevel@tonic-gate	uint16_t pcix_stat_hi_word;
11147c478bdstevel@tonic-gate	uint16_t cmd_mmrbc;
11157c478bdstevel@tonic-gate	uint16_t stat_mmrbc;
11167c478bdstevel@tonic-gate	e1000_bus_type bus_type = e1000_bus_type_unknown;
11177c478bdstevel@tonic-gate
11187c478bdstevel@tonic-gate	DEBUGFUNC("e1000_init_hw");
11197c478bdstevel@tonic-gate
11207c478bdstevel@tonic-gate	/* Set the media type and TBI compatibility */
11217c478bdstevel@tonic-gate	e1000_set_media_type(hw);
11227c478bdstevel@tonic-gate
11237c478bdstevel@tonic-gate	/* Disabling VLAN filtering. */
11247c478bdstevel@tonic-gate	DEBUGOUT("Initializing the IEEE VLAN\n");
11257c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, VET, 0);
11267c478bdstevel@tonic-gate
11277c478bdstevel@tonic-gate	e1000_clear_vfta(hw);
11287c478bdstevel@tonic-gate
11297c478bdstevel@tonic-gate	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
11307c478bdstevel@tonic-gate	if(hw->mac_type == e1000_82542_rev2_0) {
11317c478bdstevel@tonic-gate		DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
11327c478bdstevel@tonic-gate		e1000_pci_clear_mwi(hw);
11337c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
11347c478bdstevel@tonic-gate		E1000_WRITE_FLUSH(hw);
11357c478bdstevel@tonic-gate		mdelay(5);
11367c478bdstevel@tonic-gate	}
11377c478bdstevel@tonic-gate
11387c478bdstevel@tonic-gate	/* Setup the receive address. This involves initializing all of the Receive
11397c478bdstevel@tonic-gate	 * Address Registers (RARs 0 - 15).
11407c478bdstevel@tonic-gate	 */
11417c478bdstevel@tonic-gate	e1000_init_rx_addrs(hw);
11427c478bdstevel@tonic-gate
11437c478bdstevel@tonic-gate	/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
11447c478bdstevel@tonic-gate	if(hw->mac_type == e1000_82542_rev2_0) {
11457c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, RCTL, 0);
11467c478bdstevel@tonic-gate		E1000_WRITE_FLUSH(hw);
11477c478bdstevel@tonic-gate		mdelay(1);
11487c478bdstevel@tonic-gate#ifdef LINUX_DRIVER
11497c478bdstevel@tonic-gate		if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
11507c478bdstevel@tonic-gate#endif
11517c478bdstevel@tonic-gate			e1000_pci_set_mwi(hw);
11527c478bdstevel@tonic-gate	}
11537c478bdstevel@tonic-gate
11547c478bdstevel@tonic-gate	/* Zero out the Multicast HASH table */
11557c478bdstevel@tonic-gate	DEBUGOUT("Zeroing the MTA\n");
11567c478bdstevel@tonic-gate	for(i = 0; i < E1000_MC_TBL_SIZE; i++)
11577c478bdstevel@tonic-gate		E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
11587c478bdstevel@tonic-gate
11597c478bdstevel@tonic-gate#if 0
11607c478bdstevel@tonic-gate	/* Set the PCI priority bit correctly in the CTRL register.  This
11617c478bdstevel@tonic-gate	 * determines if the adapter gives priority to receives, or if it
11627c478bdstevel@tonic-gate	 * gives equal priority to transmits and receives.
11637c478bdstevel@tonic-gate	 */
11647c478bdstevel@tonic-gate	if(hw->dma_fairness) {
11657c478bdstevel@tonic-gate		ctrl = E1000_READ_REG(hw, CTRL);
11667c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
11677c478bdstevel@tonic-gate	}
11687c478bdstevel@tonic-gate#endif
11697c478bdstevel@tonic-gate
11707c478bdstevel@tonic-gate	switch(hw->mac_type) {
11717c478bdstevel@tonic-gate		case e1000_82545_rev_3:
11727c478bdstevel@tonic-gate		case e1000_82546_rev_3:
11737c478bdstevel@tonic-gate			break;
11747c478bdstevel@tonic-gate		default:
11757c478bdstevel@tonic-gate			if (hw->mac_type >= e1000_82543) {
11767c478bdstevel@tonic-gate				/* See e1000_get_bus_info() of the Linux driver */
11777c478bdstevel@tonic-gate				status = E1000_READ_REG(hw, STATUS);
11787c478bdstevel@tonic-gate				bus_type = (status & E1000_STATUS_PCIX_MODE) ?
11797c478bdstevel@tonic-gate					e1000_bus_type_pcix : e1000_bus_type_pci;
11807c478bdstevel@tonic-gate			}
11817c478bdstevel@tonic-gate
11827c478bdstevel@tonic-gate			/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
11837c478bdstevel@tonic-gate			if(bus_type == e1000_bus_type_pcix) {
11847c478bdstevel@tonic-gate				pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
11857c478bdstevel@tonic-gate				pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
11867c478bdstevel@tonic-gate				cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
11877c478bdstevel@tonic-gate					PCIX_COMMAND_MMRBC_SHIFT;
11887c478bdstevel@tonic-gate				stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
11897c478bdstevel@tonic-gate					PCIX_STATUS_HI_MMRBC_SHIFT;
11907c478bdstevel@tonic-gate				if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
11917c478bdstevel@tonic-gate					stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
11927c478bdstevel@tonic-gate				if(cmd_mmrbc > stat_mmrbc) {
11937c478bdstevel@tonic-gate					pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
11947c478bdstevel@tonic-gate					pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
11957c478bdstevel@tonic-gate					pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word);
11967c478bdstevel@tonic-gate				}
11977c478bdstevel@tonic-gate			}
11987c478bdstevel@tonic-gate			break;
11997c478bdstevel@tonic-gate	}
12007c478bdstevel@tonic-gate
12017c478bdstevel@tonic-gate	/* Call a subroutine to configure the link and setup flow control. */
12027c478bdstevel@tonic-gate	ret_val = e1000_setup_link(hw);
12037c478bdstevel@tonic-gate
12047c478bdstevel@tonic-gate	/* Set the transmit descriptor write-back policy */
12057c478bdstevel@tonic-gate	if(hw->mac_type > e1000_82544) {
12067c478bdstevel@tonic-gate		ctrl = E1000_READ_REG(hw, TXDCTL);
12077c478bdstevel@tonic-gate		ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
12087c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, TXDCTL, ctrl);
12097c478bdstevel@tonic-gate	}
12107c478bdstevel@tonic-gate
12117c478bdstevel@tonic-gate#if 0
12127c478bdstevel@tonic-gate	/* Clear all of the statistics registers (clear on read).  It is
12137c478bdstevel@tonic-gate	 * important that we do this after we have tried to establish link
12147c478bdstevel@tonic-gate	 * because the symbol error count will increment wildly if there
12157c478bdstevel@tonic-gate	 * is no link.
12167c478bdstevel@tonic-gate	 */
12177c478bdstevel@tonic-gate	e1000_clear_hw_cntrs(hw);
12187c478bdstevel@tonic-gate#endif
12197c478bdstevel@tonic-gate
12207c478bdstevel@tonic-gate	return ret_val;
12217c478bdstevel@tonic-gate}
12227c478bdstevel@tonic-gate
12237c478bdstevel@tonic-gate/******************************************************************************
12247c478bdstevel@tonic-gate * Adjust SERDES output amplitude based on EEPROM setting.
12257c478bdstevel@tonic-gate *
12267c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code.
12277c478bdstevel@tonic-gate *****************************************************************************/
12287c478bdstevel@tonic-gatestatic int32_t
12297c478bdstevel@tonic-gatee1000_adjust_serdes_amplitude(struct e1000_hw *hw)
12307c478bdstevel@tonic-gate{
12317c478bdstevel@tonic-gate	uint16_t eeprom_data;
12327c478bdstevel@tonic-gate	int32_t  ret_val;
12337c478bdstevel@tonic-gate
12347c478bdstevel@tonic-gate	DEBUGFUNC("e1000_adjust_serdes_amplitude");
12357c478bdstevel@tonic-gate
12367c478bdstevel@tonic-gate	if(hw->media_type != e1000_media_type_internal_serdes)
12377c478bdstevel@tonic-gate		return E1000_SUCCESS;
12387c478bdstevel@tonic-gate
12397c478bdstevel@tonic-gate	switch(hw->mac_type) {
12407c478bdstevel@tonic-gate		case e1000_82545_rev_3:
12417c478bdstevel@tonic-gate		case e1000_82546_rev_3:
12427c478bdstevel@tonic-gate			break;
12437c478bdstevel@tonic-gate		default:
12447c478bdstevel@tonic-gate			return E1000_SUCCESS;
12457c478bdstevel@tonic-gate	}
12467c478bdstevel@tonic-gate
12477c478bdstevel@tonic-gate	if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
12487c478bdstevel@tonic-gate					&eeprom_data))) {
12497c478bdstevel@tonic-gate		return ret_val;
12507c478bdstevel@tonic-gate	}
12517c478bdstevel@tonic-gate
12527c478bdstevel@tonic-gate	if(eeprom_data != EEPROM_RESERVED_WORD) {
12537c478bdstevel@tonic-gate		/* Adjust SERDES output amplitude only. */
12547c478bdstevel@tonic-gate		eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
12557c478bdstevel@tonic-gate		if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
12567c478bdstevel@tonic-gate		                                  eeprom_data)))
12577c478bdstevel@tonic-gate			return ret_val;
12587c478bdstevel@tonic-gate	}
12597c478bdstevel@tonic-gate
12607c478bdstevel@tonic-gate	return E1000_SUCCESS;
12617c478bdstevel@tonic-gate}
12627c478bdstevel@tonic-gate
12637c478bdstevel@tonic-gate/******************************************************************************
12647c478bdstevel@tonic-gate * Configures flow control and link settings.
12657c478bdstevel@tonic-gate *
12667c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
12677c478bdstevel@tonic-gate *
12687c478bdstevel@tonic-gate * Determines which flow control settings to use. Calls the apropriate media-
12697c478bdstevel@tonic-gate * specific link configuration function. Configures the flow control settings.
12707c478bdstevel@tonic-gate * Assuming the adapter has a valid link partner, a valid link should be
12717c478bdstevel@tonic-gate * established. Assumes the hardware has previously been reset and the
12727c478bdstevel@tonic-gate * transmitter and receiver are not enabled.
12737c478bdstevel@tonic-gate *****************************************************************************/
12747c478bdstevel@tonic-gatestatic int
12757c478bdstevel@tonic-gatee1000_setup_link(struct e1000_hw *hw)
12767c478bdstevel@tonic-gate{
12777c478bdstevel@tonic-gate	uint32_t ctrl_ext;
12787c478bdstevel@tonic-gate	int32_t ret_val;
12797c478bdstevel@tonic-gate	uint16_t eeprom_data;
12807c478bdstevel@tonic-gate
12817c478bdstevel@tonic-gate	DEBUGFUNC("e1000_setup_link");
12827c478bdstevel@tonic-gate
12837c478bdstevel@tonic-gate	/* Read and store word 0x0F of the EEPROM. This word contains bits
12847c478bdstevel@tonic-gate	 * that determine the hardware's default PAUSE (flow control) mode,
12857c478bdstevel@tonic-gate	 * a bit that determines whether the HW defaults to enabling or
12867c478bdstevel@tonic-gate	 * disabling auto-negotiation, and the direction of the
12877c478bdstevel@tonic-gate	 * SW defined pins. If there is no SW over-ride of the flow
12887c478bdstevel@tonic-gate	 * control setting, then the variable hw->fc will
12897c478bdstevel@tonic-gate	 * be initialized based on a value in the EEPROM.
12907c478bdstevel@tonic-gate	 */
12917c478bdstevel@tonic-gate	if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
12927c478bdstevel@tonic-gate		DEBUGOUT("EEPROM Read Error\n");
12937c478bdstevel@tonic-gate		return -E1000_ERR_EEPROM;
12947c478bdstevel@tonic-gate	}
12957c478bdstevel@tonic-gate
12967c478bdstevel@tonic-gate	if(hw->fc == e1000_fc_default) {
12977c478bdstevel@tonic-gate		if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
12987c478bdstevel@tonic-gate			hw->fc = e1000_fc_none;
12997c478bdstevel@tonic-gate		else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
13007c478bdstevel@tonic-gate			EEPROM_WORD0F_ASM_DIR)
13017c478bdstevel@tonic-gate			hw->fc = e1000_fc_tx_pause;
13027c478bdstevel@tonic-gate		else
13037c478bdstevel@tonic-gate			hw->fc = e1000_fc_full;
13047c478bdstevel@tonic-gate	}
13057c478bdstevel@tonic-gate
13067c478bdstevel@tonic-gate	/* We want to save off the original Flow Control configuration just
13077c478bdstevel@tonic-gate	 * in case we get disconnected and then reconnected into a different
13087c478bdstevel@tonic-gate	 * hub or switch with different Flow Control capabilities.
13097c478bdstevel@tonic-gate	 */
13107c478bdstevel@tonic-gate	if(hw->mac_type == e1000_82542_rev2_0)
13117c478bdstevel@tonic-gate		hw->fc &= (~e1000_fc_tx_pause);
13127c478bdstevel@tonic-gate
13137c478bdstevel@tonic-gate#if 0
13147c478bdstevel@tonic-gate	/* See e1000_sw_init() of the Linux driver */
13157c478bdstevel@tonic-gate	if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
13167c478bdstevel@tonic-gate#else
13177c478bdstevel@tonic-gate	if((hw->mac_type < e1000_82543) && (hw->mac_type >= e1000_82543))
13187c478bdstevel@tonic-gate#endif
13197c478bdstevel@tonic-gate		hw->fc &= (~e1000_fc_rx_pause);
13207c478bdstevel@tonic-gate
13217c478bdstevel@tonic-gate#if 0
13227c478bdstevel@tonic-gate	hw->original_fc = hw->fc;
13237c478bdstevel@tonic-gate#endif
13247c478bdstevel@tonic-gate
13257c478bdstevel@tonic-gate	DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
13267c478bdstevel@tonic-gate
13277c478bdstevel@tonic-gate	/* Take the 4 bits from EEPROM word 0x0F that determine the initial
13287c478bdstevel@tonic-gate	 * polarity value for the SW controlled pins, and setup the
13297c478bdstevel@tonic-gate	 * Extended Device Control reg with that info.
13307c478bdstevel@tonic-gate	 * This is needed because one of the SW controlled pins is used for
13317c478bdstevel@tonic-gate	 * signal detection.  So this should be done before e1000_setup_pcs_link()
13327c478bdstevel@tonic-gate	 * or e1000_phy_setup() is called.
13337c478bdstevel@tonic-gate	 */
13347c478bdstevel@tonic-gate	if(hw->mac_type == e1000_82543) {
13357c478bdstevel@tonic-gate		ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
13367c478bdstevel@tonic-gate			SWDPIO__EXT_SHIFT);
13377c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
13387c478bdstevel@tonic-gate	}
13397c478bdstevel@tonic-gate
13407c478bdstevel@tonic-gate	/* Call the necessary subroutine to configure the link. */
13417c478bdstevel@tonic-gate	ret_val = (hw->media_type == e1000_media_type_copper) ?
13427c478bdstevel@tonic-gate		e1000_setup_copper_link(hw) :
13437c478bdstevel@tonic-gate		e1000_setup_fiber_serdes_link(hw);
13447c478bdstevel@tonic-gate	if (ret_val < 0) {
13457c478bdstevel@tonic-gate		return ret_val;
13467c478bdstevel@tonic-gate	}
13477c478bdstevel@tonic-gate
13487c478bdstevel@tonic-gate	/* Initialize the flow control address, type, and PAUSE timer
13497c478bdstevel@tonic-gate	 * registers to their default values.  This is done even if flow
13507c478bdstevel@tonic-gate	 * control is disabled, because it does not hurt anything to
13517c478bdstevel@tonic-gate	 * initialize these registers.
13527c478bdstevel@tonic-gate	 */
13537c478bdstevel@tonic-gate	DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
13547c478bdstevel@tonic-gate
13557c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
13567c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
13577c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
13587c478bdstevel@tonic-gate#if 0
13597c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
13607c478bdstevel@tonic-gate#else
13617c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, FCTTV, FC_DEFAULT_TX_TIMER);
13627c478bdstevel@tonic-gate#endif
13637c478bdstevel@tonic-gate
13647c478bdstevel@tonic-gate	/* Set the flow control receive threshold registers.  Normally,
13657c478bdstevel@tonic-gate	 * these registers will be set to a default threshold that may be
13667c478bdstevel@tonic-gate	 * adjusted later by the driver's runtime code.  However, if the
13677c478bdstevel@tonic-gate	 * ability to transmit pause frames in not enabled, then these
13687c478bdstevel@tonic-gate	 * registers will be set to 0.
13697c478bdstevel@tonic-gate	 */
13707c478bdstevel@tonic-gate	if(!(hw->fc & e1000_fc_tx_pause)) {
13717c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, FCRTL, 0);
13727c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, FCRTH, 0);
13737c478bdstevel@tonic-gate	} else {
13747c478bdstevel@tonic-gate		/* We need to set up the Receive Threshold high and low water marks
13757c478bdstevel@tonic-gate		 * as well as (optionally) enabling the transmission of XON frames.
13767c478bdstevel@tonic-gate		 */
13777c478bdstevel@tonic-gate#if 0
13787c478bdstevel@tonic-gate		if(hw->fc_send_xon) {
13797c478bdstevel@tonic-gate			E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
13807c478bdstevel@tonic-gate			E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
13817c478bdstevel@tonic-gate		} else {
13827c478bdstevel@tonic-gate			E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
13837c478bdstevel@tonic-gate			E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
13847c478bdstevel@tonic-gate		}
13857c478bdstevel@tonic-gate#else
13867c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, FCRTL, (FC_DEFAULT_LO_THRESH | E1000_FCRTL_XONE));
13877c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, FCRTH, FC_DEFAULT_HI_THRESH);
13887c478bdstevel@tonic-gate#endif
13897c478bdstevel@tonic-gate	}
13907c478bdstevel@tonic-gate	return ret_val;
13917c478bdstevel@tonic-gate}
13927c478bdstevel@tonic-gate
13937c478bdstevel@tonic-gate/******************************************************************************
13947c478bdstevel@tonic-gate * Sets up link for a fiber based or serdes based adapter
13957c478bdstevel@tonic-gate *
13967c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
13977c478bdstevel@tonic-gate *
13987c478bdstevel@tonic-gate * Manipulates Physical Coding Sublayer functions in order to configure
13997c478bdstevel@tonic-gate * link. Assumes the hardware has been previously reset and the transmitter
14007c478bdstevel@tonic-gate * and receiver are not enabled.
14017c478bdstevel@tonic-gate *****************************************************************************/
14027c478bdstevel@tonic-gatestatic int
14037c478bdstevel@tonic-gatee1000_setup_fiber_serdes_link(struct e1000_hw *hw)
14047c478bdstevel@tonic-gate{
14057c478bdstevel@tonic-gate	uint32_t ctrl;
14067c478bdstevel@tonic-gate	uint32_t status;
14077c478bdstevel@tonic-gate	uint32_t txcw = 0;
14087c478bdstevel@tonic-gate	uint32_t i;
14097c478bdstevel@tonic-gate	uint32_t signal = 0;
14107c478bdstevel@tonic-gate	int32_t ret_val;
14117c478bdstevel@tonic-gate
14127c478bdstevel@tonic-gate	DEBUGFUNC("e1000_setup_fiber_serdes_link");
14137c478bdstevel@tonic-gate
14147c478bdstevel@tonic-gate	/* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
14157c478bdstevel@tonic-gate	 * set when the optics detect a signal. On older adapters, it will be
14167c478bdstevel@tonic-gate	 * cleared when there is a signal.  This applies to fiber media only.
14177c478bdstevel@tonic-gate	 * If we're on serdes media, adjust the output amplitude to value set in
14187c478bdstevel@tonic-gate	 * the EEPROM.
14197c478bdstevel@tonic-gate	 */
14207c478bdstevel@tonic-gate	ctrl = E1000_READ_REG(hw, CTRL);
14217c478bdstevel@tonic-gate	if(hw->media_type == e1000_media_type_fiber)
14227c478bdstevel@tonic-gate		signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
14237c478bdstevel@tonic-gate
14247c478bdstevel@tonic-gate	if((ret_val = e1000_adjust_serdes_amplitude(hw)))
14257c478bdstevel@tonic-gate		return ret_val;
14267c478bdstevel@tonic-gate
14277c478bdstevel@tonic-gate	/* Take the link out of reset */
14287c478bdstevel@tonic-gate	ctrl &= ~(E1000_CTRL_LRST);
14297c478bdstevel@tonic-gate
14307c478bdstevel@tonic-gate#if 0
14317c478bdstevel@tonic-gate	/* Adjust VCO speed to improve BER performance */
14327c478bdstevel@tonic-gate	if((ret_val = e1000_set_vco_speed(hw)))
14337c478bdstevel@tonic-gate		return ret_val;
14347c478bdstevel@tonic-gate#endif
14357c478bdstevel@tonic-gate
14367c478bdstevel@tonic-gate	e1000_config_collision_dist(hw);
14377c478bdstevel@tonic-gate
14387c478bdstevel@tonic-gate	/* Check for a software override of the flow control settings, and setup
14397c478bdstevel@tonic-gate	 * the device accordingly.  If auto-negotiation is enabled, then software
14407c478bdstevel@tonic-gate	 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
14417c478bdstevel@tonic-gate	 * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
14427c478bdstevel@tonic-gate	 * auto-negotiation is disabled, then software will have to manually
14437c478bdstevel@tonic-gate	 * configure the two flow control enable bits in the CTRL register.
14447c478bdstevel@tonic-gate	 *
14457c478bdstevel@tonic-gate	 * The possible values of the "fc" parameter are:
14467c478bdstevel@tonic-gate	 *      0:  Flow control is completely disabled
14477c478bdstevel@tonic-gate	 *      1:  Rx flow control is enabled (we can receive pause frames, but
14487c478bdstevel@tonic-gate	 *          not send pause frames).
14497c478bdstevel@tonic-gate	 *      2:  Tx flow control is enabled (we can send pause frames but we do
14507c478bdstevel@tonic-gate	 *          not support receiving pause frames).
14517c478bdstevel@tonic-gate	 *      3:  Both Rx and TX flow control (symmetric) are enabled.
14527c478bdstevel@tonic-gate	 */
14537c478bdstevel@tonic-gate	switch (hw->fc) {
14547c478bdstevel@tonic-gate	case e1000_fc_none:
14557c478bdstevel@tonic-gate		/* Flow control is completely disabled by a software over-ride. */
14567c478bdstevel@tonic-gate		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
14577c478bdstevel@tonic-gate		break;
14587c478bdstevel@tonic-gate	case e1000_fc_rx_pause:
14597c478bdstevel@tonic-gate		/* RX Flow control is enabled and TX Flow control is disabled by a
14607c478bdstevel@tonic-gate		 * software over-ride. Since there really isn't a way to advertise
14617c478bdstevel@tonic-gate		 * that we are capable of RX Pause ONLY, we will advertise that we
14627c478bdstevel@tonic-gate		 * support both symmetric and asymmetric RX PAUSE. Later, we will
14637c478bdstevel@tonic-gate		 *  disable the adapter's ability to send PAUSE frames.
14647c478bdstevel@tonic-gate		 */
14657c478bdstevel@tonic-gate		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
14667c478bdstevel@tonic-gate		break;
14677c478bdstevel@tonic-gate	case e1000_fc_tx_pause:
14687c478bdstevel@tonic-gate		/* TX Flow control is enabled, and RX Flow control is disabled, by a
14697c478bdstevel@tonic-gate		 * software over-ride.
14707c478bdstevel@tonic-gate		 */
14717c478bdstevel@tonic-gate		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
14727c478bdstevel@tonic-gate		break;
14737c478bdstevel@tonic-gate	case e1000_fc_full:
14747c478bdstevel@tonic-gate		/* Flow control (both RX and TX) is enabled by a software over-ride. */
14757c478bdstevel@tonic-gate		txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
14767c478bdstevel@tonic-gate		break;
14777c478bdstevel@tonic-gate	default:
14787c478bdstevel@tonic-gate		DEBUGOUT("Flow control param set incorrectly\n");
14797c478bdstevel@tonic-gate		return -E1000_ERR_CONFIG;
14807c478bdstevel@tonic-gate		break;
14817c478bdstevel@tonic-gate	}
14827c478bdstevel@tonic-gate
14837c478bdstevel@tonic-gate	/* Since auto-negotiation is enabled, take the link out of reset (the link
14847c478bdstevel@tonic-gate	 * will be in reset, because we previously reset the chip). This will
14857c478bdstevel@tonic-gate	 * restart auto-negotiation.  If auto-neogtiation is successful then the
14867c478bdstevel@tonic-gate	 * link-up status bit will be set and the flow control enable bits (RFCE
14877c478bdstevel@tonic-gate	 * and TFCE) will be set according to their negotiated value.
14887c478bdstevel@tonic-gate	 */
14897c478bdstevel@tonic-gate	DEBUGOUT("Auto-negotiation enabled\n");
14907c478bdstevel@tonic-gate
14917c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, TXCW, txcw);
14927c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, CTRL, ctrl);
14937c478bdstevel@tonic-gate	E1000_WRITE_FLUSH(hw);
14947c478bdstevel@tonic-gate
14957c478bdstevel@tonic-gate	hw->txcw = txcw;
14967c478bdstevel@tonic-gate	mdelay(1);
14977c478bdstevel@tonic-gate
14987c478bdstevel@tonic-gate	/* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
14997c478bdstevel@tonic-gate	 * indication in the Device Status Register.  Time-out if a link isn't
15007c478bdstevel@tonic-gate	 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
15017c478bdstevel@tonic-gate	 * less than 500 milliseconds even if the other end is doing it in SW).
15027c478bdstevel@tonic-gate	 * For internal serdes, we just assume a signal is present, then poll.
15037c478bdstevel@tonic-gate	 */
15047c478bdstevel@tonic-gate	if(hw->media_type == e1000_media_type_internal_serdes ||
15057c478bdstevel@tonic-gate	   (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
15067c478bdstevel@tonic-gate		DEBUGOUT("Looking for Link\n");
15077c478bdstevel@tonic-gate		for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
15087c478bdstevel@tonic-gate			mdelay(10);
15097c478bdstevel@tonic-gate			status = E1000_READ_REG(hw, STATUS);
15107c478bdstevel@tonic-gate			if(status & E1000_STATUS_LU) break;
15117c478bdstevel@tonic-gate		}
15127c478bdstevel@tonic-gate		if(i == (LINK_UP_TIMEOUT / 10)) {
15137c478bdstevel@tonic-gate			DEBUGOUT("Never got a valid link from auto-neg!!!\n");
15147c478bdstevel@tonic-gate			hw->autoneg_failed = 1;
15157c478bdstevel@tonic-gate			/* AutoNeg failed to achieve a link, so we'll call
15167c478bdstevel@tonic-gate			 * e1000_check_for_link. This routine will force the link up if
15177c478bdstevel@tonic-gate			 * we detect a signal. This will allow us to communicate with
15187c478bdstevel@tonic-gate			 * non-autonegotiating link partners.
15197c478bdstevel@tonic-gate			 */
15207c478bdstevel@tonic-gate			if((ret_val = e1000_check_for_link(hw))) {
15217c478bdstevel@tonic-gate				DEBUGOUT("Error while checking for link\n");
15227c478bdstevel@tonic-gate				return ret_val;
15237c478bdstevel@tonic-gate			}
15247c478bdstevel@tonic-gate			hw->autoneg_failed = 0;
15257c478bdstevel@tonic-gate		} else {
15267c478bdstevel@tonic-gate			hw->autoneg_failed = 0;
15277c478bdstevel@tonic-gate			DEBUGOUT("Valid Link Found\n");
15287c478bdstevel@tonic-gate		}
15297c478bdstevel@tonic-gate	} else {
15307c478bdstevel@tonic-gate		DEBUGOUT("No Signal Detected\n");
15317c478bdstevel@tonic-gate	}
15327c478bdstevel@tonic-gate	return E1000_SUCCESS;
15337c478bdstevel@tonic-gate}
15347c478bdstevel@tonic-gate
15357c478bdstevel@tonic-gate/******************************************************************************
15367c478bdstevel@tonic-gate* Detects which PHY is present and the speed and duplex
15377c478bdstevel@tonic-gate*
15387c478bdstevel@tonic-gate* hw - Struct containing variables accessed by shared code
15397c478bdstevel@tonic-gate******************************************************************************/
15407c478bdstevel@tonic-gatestatic int
15417c478bdstevel@tonic-gatee1000_setup_copper_link(struct e1000_hw *hw)
15427c478bdstevel@tonic-gate{
15437c478bdstevel@tonic-gate	uint32_t ctrl;
15447c478bdstevel@tonic-gate	int32_t ret_val;
15457c478bdstevel@tonic-gate	uint16_t i;
15467c478bdstevel@tonic-gate	uint16_t phy_data;
15477c478bdstevel@tonic-gate
15487c478bdstevel@tonic-gate	DEBUGFUNC("e1000_setup_copper_link");
15497c478bdstevel@tonic-gate
15507c478bdstevel@tonic-gate	ctrl = E1000_READ_REG(hw, CTRL);
15517c478bdstevel@tonic-gate	/* With 82543, we need to force speed and duplex on the MAC equal to what
15527c478bdstevel@tonic-gate	 * the PHY speed and duplex configuration is. In addition, we need to
15537c478bdstevel@tonic-gate	 * perform a hardware reset on the PHY to take it out of reset.
15547c478bdstevel@tonic-gate	 */
15557c478bdstevel@tonic-gate	if(hw->mac_type > e1000_82543) {
15567c478bdstevel@tonic-gate		ctrl |= E1000_CTRL_SLU;
15577c478bdstevel@tonic-gate		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
15587c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, CTRL, ctrl);
15597c478bdstevel@tonic-gate	} else {
15607c478bdstevel@tonic-gate		ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
15617c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, CTRL, ctrl);
15627c478bdstevel@tonic-gate		e1000_phy_hw_reset(hw);
15637c478bdstevel@tonic-gate	}
15647c478bdstevel@tonic-gate
15657c478bdstevel@tonic-gate	/* Make sure we have a valid PHY */
15667c478bdstevel@tonic-gate	if((ret_val = e1000_detect_gig_phy(hw))) {
15677c478bdstevel@tonic-gate		DEBUGOUT("Error, did not detect valid phy.\n");
15687c478bdstevel@tonic-gate		return ret_val;
15697c478bdstevel@tonic-gate	}
15707c478bdstevel@tonic-gate	DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
15717c478bdstevel@tonic-gate
15727c478bdstevel@tonic-gate	if(hw->mac_type <= e1000_82543 ||
15737c478bdstevel@tonic-gate	   hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
15747c478bdstevel@tonic-gate#if 0
15757c478bdstevel@tonic-gate	   hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
15767c478bdstevel@tonic-gate		hw->phy_reset_disable = FALSE;
15777c478bdstevel@tonic-gate
15787c478bdstevel@tonic-gate	if(!hw->phy_reset_disable) {
15797c478bdstevel@tonic-gate#else
15807c478bdstevel@tonic-gate	   hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
15817c478bdstevel@tonic-gate#endif
15827c478bdstevel@tonic-gate	if (hw->phy_type == e1000_phy_igp) {
15837c478bdstevel@tonic-gate
15847c478bdstevel@tonic-gate		if((ret_val = e1000_phy_reset(hw))) {
15857c478bdstevel@tonic-gate			DEBUGOUT("Error Resetting the PHY\n");
15867c478bdstevel@tonic-gate			return ret_val;
15877c478bdstevel@tonic-gate		}
15887c478bdstevel@tonic-gate
15897c478bdstevel@tonic-gate		/* Wait 10ms for MAC to configure PHY from eeprom settings */
15907c478bdstevel@tonic-gate		mdelay(15);
15917c478bdstevel@tonic-gate
15927c478bdstevel@tonic-gate#if 0
15937c478bdstevel@tonic-gate		/* disable lplu d3 during driver init */
15947c478bdstevel@tonic-gate		if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) {
15957c478bdstevel@tonic-gate			DEBUGOUT("Error Disabling LPLU D3\n");
15967c478bdstevel@tonic-gate			return ret_val;
15977c478bdstevel@tonic-gate		}
15987c478bdstevel@tonic-gate
15997c478bdstevel@tonic-gate		/* Configure mdi-mdix settings */
16007c478bdstevel@tonic-gate		if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
16017c478bdstevel@tonic-gate		                                 &phy_data)))
16027c478bdstevel@tonic-gate			return ret_val;
16037c478bdstevel@tonic-gate
16047c478bdstevel@tonic-gate		if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
16057c478bdstevel@tonic-gate			hw->dsp_config_state = e1000_dsp_config_disabled;
16067c478bdstevel@tonic-gate			/* Force MDI for IGP B-0 PHY */
16077c478bdstevel@tonic-gate			phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
16087c478bdstevel@tonic-gate			              IGP01E1000_PSCR_FORCE_MDI_MDIX);
16097c478bdstevel@tonic-gate			hw->mdix = 1;
16107c478bdstevel@tonic-gate
16117c478bdstevel@tonic-gate		} else {
16127c478bdstevel@tonic-gate			hw->dsp_config_state = e1000_dsp_config_enabled;
16137c478bdstevel@tonic-gate			phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
16147c478bdstevel@tonic-gate
16157c478bdstevel@tonic-gate			switch (hw->mdix) {
16167c478bdstevel@tonic-gate			case 1:
16177c478bdstevel@tonic-gate				phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
16187c478bdstevel@tonic-gate				break;
16197c478bdstevel@tonic-gate			case 2:
16207c478bdstevel@tonic-gate				phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
16217c478bdstevel@tonic-gate				break;
16227c478bdstevel@tonic-gate			case 0:
16237c478bdstevel@tonic-gate			default:
16247c478bdstevel@tonic-gate				phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
16257c478bdstevel@tonic-gate				break;
16267c478bdstevel@tonic-gate			}
16277c478bdstevel@tonic-gate		}
16287c478bdstevel@tonic-gate		if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
16297c478bdstevel@tonic-gate		                                  phy_data)))
16307c478bdstevel@tonic-gate			return ret_val;
16317c478bdstevel@tonic-gate
16327c478bdstevel@tonic-gate		/* set auto-master slave resolution settings */
16337c478bdstevel@tonic-gate		e1000_ms_type phy_ms_setting = hw->master_slave;
16347c478bdstevel@tonic-gate
16357c478bdstevel@tonic-gate		if(hw->ffe_config_state == e1000_ffe_config_active)
16367c478bdstevel@tonic-gate			hw->ffe_config_state = e1000_ffe_config_enabled;
16377c478bdstevel@tonic-gate
16387c478bdstevel@tonic-gate		if(hw->dsp_config_state == e1000_dsp_config_activated)
16397c478bdstevel@tonic-gate			hw->dsp_config_state = e1000_dsp_config_enabled;
16407c478bdstevel@tonic-gate#endif
16417c478bdstevel@tonic-gate
16427c478bdstevel@tonic-gate		/* when autonegotiation advertisment is only 1000Mbps then we
16437c478bdstevel@tonic-gate		 * should disable SmartSpeed and enable Auto MasterSlave
16447c478bdstevel@tonic-gate		 * resolution as hardware default. */
16457c478bdstevel@tonic-gate		if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
16467c478bdstevel@tonic-gate			/* Disable SmartSpeed */
16477c478bdstevel@tonic-gate			if((ret_val = e1000_read_phy_reg(hw,
16487c478bdstevel@tonic-gate			                                 IGP01E1000_PHY_PORT_CONFIG,
16497c478bdstevel@tonic-gate			                                 &phy_data)))
16507c478bdstevel@tonic-gate				return ret_val;
16517c478bdstevel@tonic-gate			phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
16527c478bdstevel@tonic-gate			if((ret_val = e1000_write_phy_reg(hw,
16537c478bdstevel@tonic-gate			                                  IGP01E1000_PHY_PORT_CONFIG,
16547c478bdstevel@tonic-gate			                                  phy_data)))
16557c478bdstevel@tonic-gate				return ret_val;
16567c478bdstevel@tonic-gate			/* Set auto Master/Slave resolution process */
16577c478bdstevel@tonic-gate			if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
16587c478bdstevel@tonic-gate			                                 &phy_data)))
16597c478bdstevel@tonic-gate				return ret_val;
16607c478bdstevel@tonic-gate			phy_data &= ~CR_1000T_MS_ENABLE;
16617c478bdstevel@tonic-gate			if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
16627c478bdstevel@tonic-gate			                                  phy_data)))
16637c478bdstevel@tonic-gate				return ret_val;
16647c478bdstevel@tonic-gate		}
16657c478bdstevel@tonic-gate
16667c478bdstevel@tonic-gate		if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
16677c478bdstevel@tonic-gate		                                 &phy_data)))
16687c478bdstevel@tonic-gate			return ret_val;
16697c478bdstevel@tonic-gate
16707c478bdstevel@tonic-gate#if 0
16717c478bdstevel@tonic-gate		/* load defaults for future use */
16727c478bdstevel@tonic-gate		hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
16737c478bdstevel@tonic-gate		                            ((phy_data & CR_1000T_MS_VALUE) ?
16747c478bdstevel@tonic-gate		                             e1000_ms_force_master :
16757c478bdstevel@tonic-gate		                             e1000_ms_force_slave) :
16767c478bdstevel@tonic-gate		                             e1000_ms_auto;
16777c478bdstevel@tonic-gate
16787c478bdstevel@tonic-gate		switch (phy_ms_setting) {
16797c478bdstevel@tonic-gate		case e1000_ms_force_master:
16807c478bdstevel@tonic-gate			phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
16817c478bdstevel@tonic-gate			break;
16827c478bdstevel@tonic-gate		case e1000_ms_force_slave:
16837c478bdstevel@tonic-gate			phy_data |= CR_1000T_MS_ENABLE;
16847c478bdstevel@tonic-gate			phy_data &= ~(CR_1000T_MS_VALUE);
16857c478bdstevel@tonic-gate			break;
16867c478bdstevel@tonic-gate		case e1000_ms_auto:
16877c478bdstevel@tonic-gate			phy_data &= ~CR_1000T_MS_ENABLE;
16887c478bdstevel@tonic-gate		default:
16897c478bdstevel@tonic-gate			break;
16907c478bdstevel@tonic-gate		}
16917c478bdstevel@tonic-gate#endif
16927c478bdstevel@tonic-gate
16937c478bdstevel@tonic-gate		if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
16947c478bdstevel@tonic-gate		                                  phy_data)))
16957c478bdstevel@tonic-gate			return ret_val;
16967c478bdstevel@tonic-gate	} else {
16977c478bdstevel@tonic-gate		/* Enable CRS on TX. This must be set for half-duplex operation. */
16987c478bdstevel@tonic-gate		if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
16997c478bdstevel@tonic-gate		                                 &phy_data)))
17007c478bdstevel@tonic-gate			return ret_val;
17017c478bdstevel@tonic-gate
17027c478bdstevel@tonic-gate		phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
17037c478bdstevel@tonic-gate
17047c478bdstevel@tonic-gate		/* Options:
17057c478bdstevel@tonic-gate		 *   MDI/MDI-X = 0 (default)
17067c478bdstevel@tonic-gate		 *   0 - Auto for all speeds
17077c478bdstevel@tonic-gate		 *   1 - MDI mode
17087c478bdstevel@tonic-gate		 *   2 - MDI-X mode
17097c478bdstevel@tonic-gate		 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
17107c478bdstevel@tonic-gate		 */
17117c478bdstevel@tonic-gate#if 0
17127c478bdstevel@tonic-gate		phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
17137c478bdstevel@tonic-gate
17147c478bdstevel@tonic-gate		switch (hw->mdix) {
17157c478bdstevel@tonic-gate		case 1:
17167c478bdstevel@tonic-gate			phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
17177c478bdstevel@tonic-gate			break;
17187c478bdstevel@tonic-gate		case 2:
17197c478bdstevel@tonic-gate			phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
17207c478bdstevel@tonic-gate			break;
17217c478bdstevel@tonic-gate		case 3:
17227c478bdstevel@tonic-gate			phy_data |= M88E1000_PSCR_AUTO_X_1000T;
17237c478bdstevel@tonic-gate			break;
17247c478bdstevel@tonic-gate		case 0:
17257c478bdstevel@tonic-gate		default:
17267c478bdstevel@tonic-gate#endif
17277c478bdstevel@tonic-gate			phy_data |= M88E1000_PSCR_AUTO_X_MODE;
17287c478bdstevel@tonic-gate#if 0
17297c478bdstevel@tonic-gate			break;
17307c478bdstevel@tonic-gate		}
17317c478bdstevel@tonic-gate#endif
17327c478bdstevel@tonic-gate
17337c478bdstevel@tonic-gate		/* Options:
17347c478bdstevel@tonic-gate		 *   disable_polarity_correction = 0 (default)
17357c478bdstevel@tonic-gate		 *       Automatic Correction for Reversed Cable Polarity
17367c478bdstevel@tonic-gate		 *   0 - Disabled
17377c478bdstevel@tonic-gate		 *   1 - Enabled
17387c478bdstevel@tonic-gate		 */
17397c478bdstevel@tonic-gate		phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
17407c478bdstevel@tonic-gate		if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
17417c478bdstevel@tonic-gate		                                  phy_data)))
17427c478bdstevel@tonic-gate			return ret_val;
17437c478bdstevel@tonic-gate
17447c478bdstevel@tonic-gate		/* Force TX_CLK in the Extended PHY Specific Control Register
17457c478bdstevel@tonic-gate		 * to 25MHz clock.
17467c478bdstevel@tonic-gate		 */
17477c478bdstevel@tonic-gate		if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
17487c478bdstevel@tonic-gate		                                 &phy_data)))
17497c478bdstevel@tonic-gate			return ret_val;
17507c478bdstevel@tonic-gate
17517c478bdstevel@tonic-gate		phy_data |= M88E1000_EPSCR_TX_CLK_25;
17527c478bdstevel@tonic-gate
17537c478bdstevel@tonic-gate#ifdef LINUX_DRIVER
17547c478bdstevel@tonic-gate		if (hw->phy_revision < M88E1011_I_REV_4) {
17557c478bdstevel@tonic-gate#endif
17567c478bdstevel@tonic-gate			/* Configure Master and Slave downshift values */
17577c478bdstevel@tonic-gate			phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
17587c478bdstevel@tonic-gate				M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
17597c478bdstevel@tonic-gate			phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
17607c478bdstevel@tonic-gate				M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
17617c478bdstevel@tonic-gate			if((ret_val = e1000_write_phy_reg(hw,
17627c478bdstevel@tonic-gate			                                  M88E1000_EXT_PHY_SPEC_CTRL,
17637c478bdstevel@tonic-gate			                                  phy_data)))
17647c478bdstevel@tonic-gate				return ret_val;
17657c478bdstevel@tonic-gate		}
17667c478bdstevel@tonic-gate
17677c478bdstevel@tonic-gate		/* SW Reset the PHY so all changes take effect */
17687c478bdstevel@tonic-gate		if((ret_val = e1000_phy_reset(hw))) {
17697c478bdstevel@tonic-gate			DEBUGOUT("Error Resetting the PHY\n");
17707c478bdstevel@tonic-gate			return ret_val;
17717c478bdstevel@tonic-gate#ifdef LINUX_DRIVER
17727c478bdstevel@tonic-gate		}
17737c478bdstevel@tonic-gate#endif
17747c478bdstevel@tonic-gate	}
17757c478bdstevel@tonic-gate
17767c478bdstevel@tonic-gate	/* Options:
17777c478bdstevel@tonic-gate	 *   autoneg = 1 (default)
17787c478bdstevel@tonic-gate	 *      PHY will advertise value(s) parsed from
17797c478bdstevel@tonic-gate	 *      autoneg_advertised and fc
17807c478bdstevel@tonic-gate	 *   autoneg = 0
17817c478bdstevel@tonic-gate	 *      PHY will be set to 10H, 10F, 100H, or 100F
17827c478bdstevel@tonic-gate	 *      depending on value parsed from forced_speed_duplex.
17837c478bdstevel@tonic-gate	 */
17847c478bdstevel@tonic-gate
17857c478bdstevel@tonic-gate	/* Is autoneg enabled?  This is enabled by default or by software
17867c478bdstevel@tonic-gate	 * override.  If so, call e1000_phy_setup_autoneg routine to parse the
17877c478bdstevel@tonic-gate	 * autoneg_advertised and fc options. If autoneg is NOT enabled, then
17887c478bdstevel@tonic-gate	 * the user should have provided a speed/duplex override.  If so, then
17897c478bdstevel@tonic-gate	 * call e1000_phy_force_speed_duplex to parse and set this up.
17907c478bdstevel@tonic-gate	 */
17917c478bdstevel@tonic-gate	/* Perform some bounds checking on the hw->autoneg_advertised
17927c478bdstevel@tonic-gate	 * parameter.  If this variable is zero, then set it to the default.
17937c478bdstevel@tonic-gate	 */
17947c478bdstevel@tonic-gate	hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
17957c478bdstevel@tonic-gate
17967c478bdstevel@tonic-gate	/* If autoneg_advertised is zero, we assume it was not defaulted
17977c478bdstevel@tonic-gate	 * by the calling code so we set to advertise full capability.
17987c478bdstevel@tonic-gate	 */
17997c478bdstevel@tonic-gate	if(hw->autoneg_advertised == 0)
18007c478bdstevel@tonic-gate		hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
18017c478bdstevel@tonic-gate
18027c478bdstevel@tonic-gate	DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
18037c478bdstevel@tonic-gate	if((ret_val = e1000_phy_setup_autoneg(hw))) {
18047c478bdstevel@tonic-gate		DEBUGOUT("Error Setting up Auto-Negotiation\n");
18057c478bdstevel@tonic-gate		return ret_val;
18067c478bdstevel@tonic-gate	}
18077c478bdstevel@tonic-gate	DEBUGOUT("Restarting Auto-Neg\n");
18087c478bdstevel@tonic-gate
18097c478bdstevel@tonic-gate	/* Restart auto-negotiation by setting the Auto Neg Enable bit and
18107c478bdstevel@tonic-gate	 * the Auto Neg Restart bit in the PHY control register.
18117c478bdstevel@tonic-gate	 */
18127c478bdstevel@tonic-gate	if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
18137c478bdstevel@tonic-gate		return ret_val;
18147c478bdstevel@tonic-gate
18157c478bdstevel@tonic-gate	phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
18167c478bdstevel@tonic-gate	if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
18177c478bdstevel@tonic-gate		return ret_val;
18187c478bdstevel@tonic-gate
18197c478bdstevel@tonic-gate#if 0
18207c478bdstevel@tonic-gate	/* Does the user want to wait for Auto-Neg to complete here, or
18217c478bdstevel@tonic-gate	 * check at a later time (for example, callback routine).
18227c478bdstevel@tonic-gate	 */
18237c478bdstevel@tonic-gate	if(hw->wait_autoneg_complete) {
18247c478bdstevel@tonic-gate		if((ret_val = e1000_wait_autoneg(hw))) {
18257c478bdstevel@tonic-gate			DEBUGOUT("Error while waiting for autoneg to complete\n");
18267c478bdstevel@tonic-gate			return ret_val;
18277c478bdstevel@tonic-gate		}
18287c478bdstevel@tonic-gate	}
18297c478bdstevel@tonic-gate#else
18307c478bdstevel@tonic-gate	/* If we do not wait for autonegotiation to complete I
18317c478bdstevel@tonic-gate	 * do not see a valid link status.
18327c478bdstevel@tonic-gate	 */
18337c478bdstevel@tonic-gate	if((ret_val = e1000_wait_autoneg(hw))) {
18347c478bdstevel@tonic-gate		DEBUGOUT("Error while waiting for autoneg to complete\n");
18357c478bdstevel@tonic-gate		return ret_val;
18367c478bdstevel@tonic-gate	}
18377c478bdstevel@tonic-gate#endif
18387c478bdstevel@tonic-gate	} /* !hw->phy_reset_disable */
18397c478bdstevel@tonic-gate
18407c478bdstevel@tonic-gate	/* Check link status. Wait up to 100 microseconds for link to become
18417c478bdstevel@tonic-gate	 * valid.
18427c478bdstevel@tonic-gate	 */
18437c478bdstevel@tonic-gate	for(i = 0; i < 10; i++) {
18447c478bdstevel@tonic-gate		if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
18457c478bdstevel@tonic-gate			return ret_val;
18467c478bdstevel@tonic-gate		if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
18477c478bdstevel@tonic-gate			return ret_val;
18487c478bdstevel@tonic-gate
18497c478bdstevel@tonic-gate		if(phy_data & MII_SR_LINK_STATUS) {
18507c478bdstevel@tonic-gate			/* We have link, so we need to finish the config process:
18517c478bdstevel@tonic-gate			 *   1) Set up the MAC to the current PHY speed/duplex
18527c478bdstevel@tonic-gate			 *      if we are on 82543.  If we
18537c478bdstevel@tonic-gate			 *      are on newer silicon, we only need to configure
18547c478bdstevel@tonic-gate			 *      collision distance in the Transmit Control Register.
18557c478bdstevel@tonic-gate			 *   2) Set up flow control on the MAC to that established with
18567c478bdstevel@tonic-gate			 *      the link partner.
18577c478bdstevel@tonic-gate			 */
18587c478bdstevel@tonic-gate			if(hw->mac_type >= e1000_82544) {
18597c478bdstevel@tonic-gate				e1000_config_collision_dist(hw);
18607c478bdstevel@tonic-gate			} else {
18617c478bdstevel@tonic-gate				if((ret_val = e1000_config_mac_to_phy(hw))) {
18627c478bdstevel@tonic-gate					DEBUGOUT("Error configuring MAC to PHY settings\n");
18637c478bdstevel@tonic-gate					return ret_val;
18647c478bdstevel@tonic-gate				}
18657c478bdstevel@tonic-gate			}
18667c478bdstevel@tonic-gate			if((ret_val = e1000_config_fc_after_link_up(hw))) {
18677c478bdstevel@tonic-gate				DEBUGOUT("Error Configuring Flow Control\n");
18687c478bdstevel@tonic-gate				return ret_val;
18697c478bdstevel@tonic-gate			}
18707c478bdstevel@tonic-gate#if 0
18717c478bdstevel@tonic-gate			if(hw->phy_type == e1000_phy_igp) {
18727c478bdstevel@tonic-gate				if((ret_val = e1000_config_dsp_after_link_change(hw, TRUE))) {
18737c478bdstevel@tonic-gate					DEBUGOUT("Error Configuring DSP after link up\n");
18747c478bdstevel@tonic-gate					return ret_val;
18757c478bdstevel@tonic-gate				}
18767c478bdstevel@tonic-gate			}
18777c478bdstevel@tonic-gate#endif
18787c478bdstevel@tonic-gate			DEBUGOUT("Valid link established!!!\n");
18797c478bdstevel@tonic-gate			return E1000_SUCCESS;
18807c478bdstevel@tonic-gate		}
18817c478bdstevel@tonic-gate		udelay(10);
18827c478bdstevel@tonic-gate	}
18837c478bdstevel@tonic-gate
18847c478bdstevel@tonic-gate	DEBUGOUT("Unable to establish link!!!\n");
18857c478bdstevel@tonic-gate	return -E1000_ERR_NOLINK;
18867c478bdstevel@tonic-gate}
18877c478bdstevel@tonic-gate
18887c478bdstevel@tonic-gate/******************************************************************************
18897c478bdstevel@tonic-gate* Configures PHY autoneg and flow control advertisement settings
18907c478bdstevel@tonic-gate*
18917c478bdstevel@tonic-gate* hw - Struct containing variables accessed by shared code
18927c478bdstevel@tonic-gate******************************************************************************/
18937c478bdstevel@tonic-gatestatic int
18947c478bdstevel@tonic-gatee1000_phy_setup_autoneg(struct e1000_hw *hw)
18957c478bdstevel@tonic-gate{
18967c478bdstevel@tonic-gate	int32_t ret_val;
18977c478bdstevel@tonic-gate	uint16_t mii_autoneg_adv_reg;
18987c478bdstevel@tonic-gate	uint16_t mii_1000t_ctrl_reg;
18997c478bdstevel@tonic-gate
19007c478bdstevel@tonic-gate	DEBUGFUNC("e1000_phy_setup_autoneg");
19017c478bdstevel@tonic-gate
19027c478bdstevel@tonic-gate	/* Read the MII Auto-Neg Advertisement Register (Address 4). */
19037c478bdstevel@tonic-gate	if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
19047c478bdstevel@tonic-gate	                                 &mii_autoneg_adv_reg)))
19057c478bdstevel@tonic-gate		return ret_val;
19067c478bdstevel@tonic-gate
19077c478bdstevel@tonic-gate	/* Read the MII 1000Base-T Control Register (Address 9). */
19087c478bdstevel@tonic-gate	if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
19097c478bdstevel@tonic-gate		return ret_val;
19107c478bdstevel@tonic-gate
19117c478bdstevel@tonic-gate	/* Need to parse both autoneg_advertised and fc and set up
19127c478bdstevel@tonic-gate	 * the appropriate PHY registers.  First we will parse for
19137c478bdstevel@tonic-gate	 * autoneg_advertised software override.  Since we can advertise
19147c478bdstevel@tonic-gate	 * a plethora of combinations, we need to check each bit
19157c478bdstevel@tonic-gate	 * individually.
19167c478bdstevel@tonic-gate	 */
19177c478bdstevel@tonic-gate
19187c478bdstevel@tonic-gate	/* First we clear all the 10/100 mb speed bits in the Auto-Neg
19197c478bdstevel@tonic-gate	 * Advertisement Register (Address 4) and the 1000 mb speed bits in
19207c478bdstevel@tonic-gate	 * the  1000Base-T Control Register (Address 9).
19217c478bdstevel@tonic-gate	 */
19227c478bdstevel@tonic-gate	mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
19237c478bdstevel@tonic-gate	mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
19247c478bdstevel@tonic-gate
19257c478bdstevel@tonic-gate	DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
19267c478bdstevel@tonic-gate
19277c478bdstevel@tonic-gate	/* Do we want to advertise 10 Mb Half Duplex? */
19287c478bdstevel@tonic-gate	if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
19297c478bdstevel@tonic-gate		DEBUGOUT("Advertise 10mb Half duplex\n");
19307c478bdstevel@tonic-gate		mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
19317c478bdstevel@tonic-gate	}
19327c478bdstevel@tonic-gate
19337c478bdstevel@tonic-gate	/* Do we want to advertise 10 Mb Full Duplex? */
19347c478bdstevel@tonic-gate	if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
19357c478bdstevel@tonic-gate		DEBUGOUT("Advertise 10mb Full duplex\n");
19367c478bdstevel@tonic-gate		mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
19377c478bdstevel@tonic-gate	}
19387c478bdstevel@tonic-gate
19397c478bdstevel@tonic-gate	/* Do we want to advertise 100 Mb Half Duplex? */
19407c478bdstevel@tonic-gate	if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
19417c478bdstevel@tonic-gate		DEBUGOUT("Advertise 100mb Half duplex\n");
19427c478bdstevel@tonic-gate		mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
19437c478bdstevel@tonic-gate	}
19447c478bdstevel@tonic-gate
19457c478bdstevel@tonic-gate	/* Do we want to advertise 100 Mb Full Duplex? */
19467c478bdstevel@tonic-gate	if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
19477c478bdstevel@tonic-gate		DEBUGOUT("Advertise 100mb Full duplex\n");
19487c478bdstevel@tonic-gate		mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
19497c478bdstevel@tonic-gate	}
19507c478bdstevel@tonic-gate
19517c478bdstevel@tonic-gate	/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
19527c478bdstevel@tonic-gate	if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
19537c478bdstevel@tonic-gate		DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
19547c478bdstevel@tonic-gate	}
19557c478bdstevel@tonic-gate
19567c478bdstevel@tonic-gate	/* Do we want to advertise 1000 Mb Full Duplex? */
19577c478bdstevel@tonic-gate	if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
19587c478bdstevel@tonic-gate		DEBUGOUT("Advertise 1000mb Full duplex\n");
19597c478bdstevel@tonic-gate		mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
19607c478bdstevel@tonic-gate	}
19617c478bdstevel@tonic-gate
19627c478bdstevel@tonic-gate	/* Check for a software override of the flow control settings, and
19637c478bdstevel@tonic-gate	 * setup the PHY advertisement registers accordingly.  If
19647c478bdstevel@tonic-gate	 * auto-negotiation is enabled, then software will have to set the
19657c478bdstevel@tonic-gate	 * "PAUSE" bits to the correct value in the Auto-Negotiation
19667c478bdstevel@tonic-gate	 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
19677c478bdstevel@tonic-gate	 *
19687c478bdstevel@tonic-gate	 * The possible values of the "fc" parameter are:
19697c478bdstevel@tonic-gate	 *      0:  Flow control is completely disabled
19707c478bdstevel@tonic-gate	 *      1:  Rx flow control is enabled (we can receive pause frames
19717c478bdstevel@tonic-gate	 *          but not send pause frames).
19727c478bdstevel@tonic-gate	 *      2:  Tx flow control is enabled (we can send pause frames
19737c478bdstevel@tonic-gate	 *          but we do not support receiving pause frames).
19747c478bdstevel@tonic-gate	 *      3:  Both Rx and TX flow control (symmetric) are enabled.
19757c478bdstevel@tonic-gate	 *  other:  No software override.  The flow control configuration
19767c478bdstevel@tonic-gate	 *          in the EEPROM is used.
19777c478bdstevel@tonic-gate	 */
19787c478bdstevel@tonic-gate	switch (hw->fc) {
19797c478bdstevel@tonic-gate	case e1000_fc_none: /* 0 */
19807c478bdstevel@tonic-gate		/* Flow control (RX & TX) is completely disabled by a
19817c478bdstevel@tonic-gate		 * software over-ride.
19827c478bdstevel@tonic-gate		 */
19837c478bdstevel@tonic-gate		mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
19847c478bdstevel@tonic-gate		break;
19857c478bdstevel@tonic-gate	case e1000_fc_rx_pause: /* 1 */
19867c478bdstevel@tonic-gate		/* RX Flow control is enabled, and TX Flow control is
19877c478bdstevel@tonic-gate		 * disabled, by a software over-ride.
19887c478bdstevel@tonic-gate		 */
19897c478bdstevel@tonic-gate		/* Since there really isn't a way to advertise that we are
19907c478bdstevel@tonic-gate		 * capable of RX Pause ONLY, we will advertise that we
19917c478bdstevel@tonic-gate		 * support both symmetric and asymmetric RX PAUSE.  Later
19927c478bdstevel@tonic-gate		 * (in e1000_config_fc_after_link_up) we will disable the
19937c478bdstevel@tonic-gate		 *hw's ability to send PAUSE frames.
19947c478bdstevel@tonic-gate		 */
19957c478bdstevel@tonic-gate		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
19967c478bdstevel@tonic-gate		break;
19977c478bdstevel@tonic-gate	case e1000_fc_tx_pause: /* 2 */
19987c478bdstevel@tonic-gate		/* TX Flow control is enabled, and RX Flow control is
19997c478bdstevel@tonic-gate		 * disabled, by a software over-ride.
20007c478bdstevel@tonic-gate		 */
20017c478bdstevel@tonic-gate		mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
20027c478bdstevel@tonic-gate		mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
20037c478bdstevel@tonic-gate		break;
20047c478bdstevel@tonic-gate	case e1000_fc_full: /* 3 */
20057c478bdstevel@tonic-gate		/* Flow control (both RX and TX) is enabled by a software
20067c478bdstevel@tonic-gate		 * over-ride.
20077c478bdstevel@tonic-gate		 */
20087c478bdstevel@tonic-gate		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
20097c478bdstevel@tonic-gate		break;
20107c478bdstevel@tonic-gate	default:
20117c478bdstevel@tonic-gate		DEBUGOUT("Flow control param set incorrectly\n");
20127c478bdstevel@tonic-gate		return -E1000_ERR_CONFIG;
20137c478bdstevel@tonic-gate	}
20147c478bdstevel@tonic-gate
20157c478bdstevel@tonic-gate	if((ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV,
20167c478bdstevel@tonic-gate	                       mii_autoneg_adv_reg)))
20177c478bdstevel@tonic-gate		return ret_val;
20187c478bdstevel@tonic-gate
20197c478bdstevel@tonic-gate	DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
20207c478bdstevel@tonic-gate
20217c478bdstevel@tonic-gate	if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
20227c478bdstevel@tonic-gate		return ret_val;
20237c478bdstevel@tonic-gate
20247c478bdstevel@tonic-gate	return E1000_SUCCESS;
20257c478bdstevel@tonic-gate}
20267c478bdstevel@tonic-gate
20277c478bdstevel@tonic-gate/******************************************************************************
20287c478bdstevel@tonic-gate* Sets the collision distance in the Transmit Control register
20297c478bdstevel@tonic-gate*
20307c478bdstevel@tonic-gate* hw - Struct containing variables accessed by shared code
20317c478bdstevel@tonic-gate*
20327c478bdstevel@tonic-gate* Link should have been established previously. Reads the speed and duplex
20337c478bdstevel@tonic-gate* information from the Device Status register.
20347c478bdstevel@tonic-gate******************************************************************************/
20357c478bdstevel@tonic-gatestatic void
20367c478bdstevel@tonic-gatee1000_config_collision_dist(struct e1000_hw *hw)
20377c478bdstevel@tonic-gate{
20387c478bdstevel@tonic-gate	uint32_t tctl;
20397c478bdstevel@tonic-gate
20407c478bdstevel@tonic-gate	tctl = E1000_READ_REG(hw, TCTL);
20417c478bdstevel@tonic-gate
20427c478bdstevel@tonic-gate	tctl &= ~E1000_TCTL_COLD;
20437c478bdstevel@tonic-gate	tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
20447c478bdstevel@tonic-gate
20457c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, TCTL, tctl);
20467c478bdstevel@tonic-gate	E1000_WRITE_FLUSH(hw);
20477c478bdstevel@tonic-gate}
20487c478bdstevel@tonic-gate
20497c478bdstevel@tonic-gate/******************************************************************************
20507c478bdstevel@tonic-gate* Sets MAC speed and duplex settings to reflect the those in the PHY
20517c478bdstevel@tonic-gate*
20527c478bdstevel@tonic-gate* hw - Struct containing variables accessed by shared code
20537c478bdstevel@tonic-gate* mii_reg - data to write to the MII control register
20547c478bdstevel@tonic-gate*
20557c478bdstevel@tonic-gate* The contents of the PHY register containing the needed information need to
20567c478bdstevel@tonic-gate* be passed in.
20577c478bdstevel@tonic-gate******************************************************************************/
20587c478bdstevel@tonic-gatestatic int
20597c478bdstevel@tonic-gatee1000_config_mac_to_phy(struct e1000_hw *hw)
20607c478bdstevel@tonic-gate{
20617c478bdstevel@tonic-gate	uint32_t ctrl;
20627c478bdstevel@tonic-gate	int32_t ret_val;
20637c478bdstevel@tonic-gate	uint16_t phy_data;
20647c478bdstevel@tonic-gate
20657c478bdstevel@tonic-gate	DEBUGFUNC("e1000_config_mac_to_phy");
20667c478bdstevel@tonic-gate
20677c478bdstevel@tonic-gate	/* Read the Device Control Register and set the bits to Force Speed
20687c478bdstevel@tonic-gate	 * and Duplex.
20697c478bdstevel@tonic-gate	 */
20707c478bdstevel@tonic-gate	ctrl = E1000_READ_REG(hw, CTRL);
20717c478bdstevel@tonic-gate	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
20727c478bdstevel@tonic-gate	ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
20737c478bdstevel@tonic-gate
20747c478bdstevel@tonic-gate	/* Set up duplex in the Device Control and Transmit Control
20757c478bdstevel@tonic-gate	 * registers depending on negotiated values.
20767c478bdstevel@tonic-gate	 */
20777c478bdstevel@tonic-gate	if (hw->phy_type == e1000_phy_igp) {
20787c478bdstevel@tonic-gate		if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
20797c478bdstevel@tonic-gate		                                 &phy_data)))
20807c478bdstevel@tonic-gate			return ret_val;
20817c478bdstevel@tonic-gate
20827c478bdstevel@tonic-gate		if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
20837c478bdstevel@tonic-gate		else ctrl &= ~E1000_CTRL_FD;
20847c478bdstevel@tonic-gate
20857c478bdstevel@tonic-gate		e1000_config_collision_dist(hw);
20867c478bdstevel@tonic-gate
20877c478bdstevel@tonic-gate		/* Set up speed in the Device Control register depending on
20887c478bdstevel@tonic-gate		 * negotiated values.
20897c478bdstevel@tonic-gate		 */
20907c478bdstevel@tonic-gate		if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
20917c478bdstevel@tonic-gate		   IGP01E1000_PSSR_SPEED_1000MBPS)
20927c478bdstevel@tonic-gate			ctrl |= E1000_CTRL_SPD_1000;
20937c478bdstevel@tonic-gate		else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
20947c478bdstevel@tonic-gate			IGP01E1000_PSSR_SPEED_100MBPS)
20957c478bdstevel@tonic-gate			ctrl |= E1000_CTRL_SPD_100;
20967c478bdstevel@tonic-gate	} else {
20977c478bdstevel@tonic-gate		if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
20987c478bdstevel@tonic-gate		                                 &phy_data)))
20997c478bdstevel@tonic-gate			return ret_val;
21007c478bdstevel@tonic-gate
21017c478bdstevel@tonic-gate		if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
21027c478bdstevel@tonic-gate		else ctrl &= ~E1000_CTRL_FD;
21037c478bdstevel@tonic-gate
21047c478bdstevel@tonic-gate		e1000_config_collision_dist(hw);
21057c478bdstevel@tonic-gate
21067c478bdstevel@tonic-gate		/* Set up speed in the Device Control register depending on
21077c478bdstevel@tonic-gate		 * negotiated values.
21087c478bdstevel@tonic-gate		 */
21097c478bdstevel@tonic-gate		if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
21107c478bdstevel@tonic-gate			ctrl |= E1000_CTRL_SPD_1000;
21117c478bdstevel@tonic-gate		else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
21127c478bdstevel@tonic-gate			ctrl |= E1000_CTRL_SPD_100;
21137c478bdstevel@tonic-gate	}
21147c478bdstevel@tonic-gate	/* Write the configured values back to the Device Control Reg. */
21157c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, CTRL, ctrl);
21167c478bdstevel@tonic-gate	return E1000_SUCCESS;
21177c478bdstevel@tonic-gate}
21187c478bdstevel@tonic-gate
21197c478bdstevel@tonic-gate/******************************************************************************
21207c478bdstevel@tonic-gate * Forces the MAC's flow control settings.
21217c478bdstevel@tonic-gate *
21227c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
21237c478bdstevel@tonic-gate *
21247c478bdstevel@tonic-gate * Sets the TFCE and RFCE bits in the device control register to reflect
21257c478bdstevel@tonic-gate * the adapter settings. TFCE and RFCE need to be explicitly set by
21267c478bdstevel@tonic-gate * software when a Copper PHY is used because autonegotiation is managed
21277c478bdstevel@tonic-gate * by the PHY rather than the MAC. Software must also configure these
21287c478bdstevel@tonic-gate * bits when link is forced on a fiber connection.
21297c478bdstevel@tonic-gate *****************************************************************************/
21307c478bdstevel@tonic-gatestatic int
21317c478bdstevel@tonic-gatee1000_force_mac_fc(struct e1000_hw *hw)
21327c478bdstevel@tonic-gate{
21337c478bdstevel@tonic-gate	uint32_t ctrl;
21347c478bdstevel@tonic-gate
21357c478bdstevel@tonic-gate	DEBUGFUNC("e1000_force_mac_fc");
21367c478bdstevel@tonic-gate
21377c478bdstevel@tonic-gate	/* Get the current configuration of the Device Control Register */
21387c478bdstevel@tonic-gate	ctrl = E1000_READ_REG(hw, CTRL);
21397c478bdstevel@tonic-gate
21407c478bdstevel@tonic-gate	/* Because we didn't get link via the internal auto-negotiation
21417c478bdstevel@tonic-gate	 * mechanism (we either forced link or we got link via PHY
21427c478bdstevel@tonic-gate	 * auto-neg), we have to manually enable/disable transmit an
21437c478bdstevel@tonic-gate	 * receive flow control.
21447c478bdstevel@tonic-gate	 *
21457c478bdstevel@tonic-gate	 * The "Case" statement below enables/disable flow control
21467c478bdstevel@tonic-gate	 * according to the "hw->fc" parameter.
21477c478bdstevel@tonic-gate	 *
21487c478bdstevel@tonic-gate	 * The possible values of the "fc" parameter are:
21497c478bdstevel@tonic-gate	 *      0:  Flow control is completely disabled
21507c478bdstevel@tonic-gate	 *      1:  Rx flow control is enabled (we can receive pause
21517c478bdstevel@tonic-gate	 *          frames but not send pause frames).
21527c478bdstevel@tonic-gate	 *      2:  Tx flow control is enabled (we can send pause frames
21537c478bdstevel@tonic-gate	 *          frames but we do not receive pause frames).
21547c478bdstevel@tonic-gate	 *      3:  Both Rx and TX flow control (symmetric) is enabled.
21557c478bdstevel@tonic-gate	 *  other:  No other values should be possible at this point.
21567c478bdstevel@tonic-gate	 */
21577c478bdstevel@tonic-gate
21587c478bdstevel@tonic-gate	switch (hw->fc) {
21597c478bdstevel@tonic-gate	case e1000_fc_none:
21607c478bdstevel@tonic-gate		ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
21617c478bdstevel@tonic-gate		break;
21627c478bdstevel@tonic-gate	case e1000_fc_rx_pause:
21637c478bdstevel@tonic-gate		ctrl &= (~E1000_CTRL_TFCE);
21647c478bdstevel@tonic-gate		ctrl |= E1000_CTRL_RFCE;
21657c478bdstevel@tonic-gate		break;
21667c478bdstevel@tonic-gate	case e1000_fc_tx_pause:
21677c478bdstevel@tonic-gate		ctrl &= (~E1000_CTRL_RFCE);
21687c478bdstevel@tonic-gate		ctrl |= E1000_CTRL_TFCE;
21697c478bdstevel@tonic-gate		break;
21707c478bdstevel@tonic-gate	case e1000_fc_full:
21717c478bdstevel@tonic-gate		ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
21727c478bdstevel@tonic-gate		break;
21737c478bdstevel@tonic-gate	default:
21747c478bdstevel@tonic-gate		DEBUGOUT("Flow control param set incorrectly\n");
21757c478bdstevel@tonic-gate		return -E1000_ERR_CONFIG;
21767c478bdstevel@tonic-gate	}
21777c478bdstevel@tonic-gate
21787c478bdstevel@tonic-gate	/* Disable TX Flow Control for 82542 (rev 2.0) */
21797c478bdstevel@tonic-gate	if(hw->mac_type == e1000_82542_rev2_0)
21807c478bdstevel@tonic-gate		ctrl &= (~E1000_CTRL_TFCE);
21817c478bdstevel@tonic-gate
21827c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, CTRL, ctrl);
21837c478bdstevel@tonic-gate	return E1000_SUCCESS;
21847c478bdstevel@tonic-gate}
21857c478bdstevel@tonic-gate
21867c478bdstevel@tonic-gate/******************************************************************************
21877c478bdstevel@tonic-gate * Configures flow control settings after link is established
21887c478bdstevel@tonic-gate *
21897c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
21907c478bdstevel@tonic-gate *
21917c478bdstevel@tonic-gate * Should be called immediately after a valid link has been established.
21927c478bdstevel@tonic-gate * Forces MAC flow control settings if link was forced. When in MII/GMII mode
21937c478bdstevel@tonic-gate * and autonegotiation is enabled, the MAC flow control settings will be set
21947c478bdstevel@tonic-gate * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
21957c478bdstevel@tonic-gate * and RFCE bits will be automaticaly set to the negotiated flow control mode.
21967c478bdstevel@tonic-gate *****************************************************************************/
21977c478bdstevel@tonic-gatestatic int
21987c478bdstevel@tonic-gatee1000_config_fc_after_link_up(struct e1000_hw *hw)
21997c478bdstevel@tonic-gate{
22007c478bdstevel@tonic-gate	int32_t ret_val;
22017c478bdstevel@tonic-gate	uint16_t mii_status_reg;
22027c478bdstevel@tonic-gate	uint16_t mii_nway_adv_reg;
22037c478bdstevel@tonic-gate	uint16_t mii_nway_lp_ability_reg;
22047c478bdstevel@tonic-gate	uint16_t speed;
22057c478bdstevel@tonic-gate	uint16_t duplex;
22067c478bdstevel@tonic-gate
22077c478bdstevel@tonic-gate	DEBUGFUNC("e1000_config_fc_after_link_up");
22087c478bdstevel@tonic-gate
22097c478bdstevel@tonic-gate	/* Check for the case where we have fiber media and auto-neg failed
22107c478bdstevel@tonic-gate	 * so we had to force link.  In this case, we need to force the
22117c478bdstevel@tonic-gate	 * configuration of the MAC to match the "fc" parameter.
22127c478bdstevel@tonic-gate	 */
22137c478bdstevel@tonic-gate	if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
22147c478bdstevel@tonic-gate	   ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed))) {
22157c478bdstevel@tonic-gate		if((ret_val = e1000_force_mac_fc(hw))) {
22167c478bdstevel@tonic-gate			DEBUGOUT("Error forcing flow control settings\n");
22177c478bdstevel@tonic-gate			return ret_val;
22187c478bdstevel@tonic-gate		}
22197c478bdstevel@tonic-gate	}
22207c478bdstevel@tonic-gate
22217c478bdstevel@tonic-gate	/* Check for the case where we have copper media and auto-neg is
22227c478bdstevel@tonic-gate	 * enabled.  In this case, we need to check and see if Auto-Neg
22237c478bdstevel@tonic-gate	 * has completed, and if so, how the PHY and link partner has
22247c478bdstevel@tonic-gate	 * flow control configured.
22257c478bdstevel@tonic-gate	 */
22267c478bdstevel@tonic-gate	if(hw->media_type == e1000_media_type_copper) {
22277c478bdstevel@tonic-gate		/* Read the MII Status Register and check to see if AutoNeg
22287c478bdstevel@tonic-gate		 * has completed.  We read this twice because this reg has
22297c478bdstevel@tonic-gate		 * some "sticky" (latched) bits.
22307c478bdstevel@tonic-gate		 */
22317c478bdstevel@tonic-gate		if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
22327c478bdstevel@tonic-gate			return ret_val;
22337c478bdstevel@tonic-gate		if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
22347c478bdstevel@tonic-gate			return ret_val;
22357c478bdstevel@tonic-gate
22367c478bdstevel@tonic-gate		if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
22377c478bdstevel@tonic-gate			/* The AutoNeg process has completed, so we now need to
22387c478bdstevel@tonic-gate			 * read both the Auto Negotiation Advertisement Register
22397c478bdstevel@tonic-gate			 * (Address 4) and the Auto_Negotiation Base Page Ability
22407c478bdstevel@tonic-gate			 * Register (Address 5) to determine how flow control was
22417c478bdstevel@tonic-gate			 * negotiated.
22427c478bdstevel@tonic-gate			 */
22437c478bdstevel@tonic-gate			if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
22447c478bdstevel@tonic-gate			                                 &mii_nway_adv_reg)))
22457c478bdstevel@tonic-gate				return ret_val;
22467c478bdstevel@tonic-gate			if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
22477c478bdstevel@tonic-gate			                                 &mii_nway_lp_ability_reg)))
22487c478bdstevel@tonic-gate				return ret_val;
22497c478bdstevel@tonic-gate
22507c478bdstevel@tonic-gate			/* Two bits in the Auto Negotiation Advertisement Register
22517c478bdstevel@tonic-gate			 * (Address 4) and two bits in the Auto Negotiation Base
22527c478bdstevel@tonic-gate			 * Page Ability Register (Address 5) determine flow control
22537c478bdstevel@tonic-gate			 * for both the PHY and the link partner.  The following
22547c478bdstevel@tonic-gate			 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
22557c478bdstevel@tonic-gate			 * 1999, describes these PAUSE resolution bits and how flow
22567c478bdstevel@tonic-gate			 * control is determined based upon these settings.
22577c478bdstevel@tonic-gate			 * NOTE:  DC = Don't Care
22587c478bdstevel@tonic-gate			 *
22597c478bdstevel@tonic-gate			 *   LOCAL DEVICE  |   LINK PARTNER
22607c478bdstevel@tonic-gate			 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
22617c478bdstevel@tonic-gate			 *-------|---------|-------|---------|--------------------
22627c478bdstevel@tonic-gate			 *   0   |    0    |  DC   |   DC    | e1000_fc_none
22637c478bdstevel@tonic-gate			 *   0   |    1    |   0   |   DC    | e1000_fc_none
22647c478bdstevel@tonic-gate			 *   0   |    1    |   1   |    0    | e1000_fc_none
22657c478bdstevel@tonic-gate			 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
22667c478bdstevel@tonic-gate			 *   1   |    0    |   0   |   DC    | e1000_fc_none
22677c478bdstevel@tonic-gate			 *   1   |   DC    |   1   |   DC    | e1000_fc_full
22687c478bdstevel@tonic-gate			 *   1   |    1    |   0   |    0    | e1000_fc_none
22697c478bdstevel@tonic-gate			 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
22707c478bdstevel@tonic-gate			 *
22717c478bdstevel@tonic-gate			 */
22727c478bdstevel@tonic-gate			/* Are both PAUSE bits set to 1?  If so, this implies
22737c478bdstevel@tonic-gate			 * Symmetric Flow Control is enabled at both ends.  The
22747c478bdstevel@tonic-gate			 * ASM_DIR bits are irrelevant per the spec.
22757c478bdstevel@tonic-gate			 *
22767c478bdstevel@tonic-gate			 * For Symmetric Flow Control:
22777c478bdstevel@tonic-gate			 *
22787c478bdstevel@tonic-gate			 *   LOCAL DEVICE  |   LINK PARTNER
22797c478bdstevel@tonic-gate			 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
22807c478bdstevel@tonic-gate			 *-------|---------|-------|---------|--------------------
22817c478bdstevel@tonic-gate			 *   1   |   DC    |   1   |   DC    | e1000_fc_full
22827c478bdstevel@tonic-gate			 *
22837c478bdstevel@tonic-gate			 */
22847c478bdstevel@tonic-gate			if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
22857c478bdstevel@tonic-gate				(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
22867c478bdstevel@tonic-gate				/* Now we need to check if the user selected RX ONLY
22877c478bdstevel@tonic-gate				 * of pause frames.  In this case, we had to advertise
22887c478bdstevel@tonic-gate				 * FULL flow control because we could not advertise RX
22897c478bdstevel@tonic-gate				 * ONLY. Hence, we must now check to see if we need to
22907c478bdstevel@tonic-gate				 * turn OFF  the TRANSMISSION of PAUSE frames.
22917c478bdstevel@tonic-gate				 */
22927c478bdstevel@tonic-gate#if 0
22937c478bdstevel@tonic-gate				if(hw->original_fc == e1000_fc_full) {
22947c478bdstevel@tonic-gate					hw->fc = e1000_fc_full;
22957c478bdstevel@tonic-gate#else
22967c478bdstevel@tonic-gate				if(hw->fc == e1000_fc_full) {
22977c478bdstevel@tonic-gate#endif
22987c478bdstevel@tonic-gate					DEBUGOUT("Flow Control = FULL.\r\n");
22997c478bdstevel@tonic-gate				} else {
23007c478bdstevel@tonic-gate					hw->fc = e1000_fc_rx_pause;
23017c478bdstevel@tonic-gate					DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
23027c478bdstevel@tonic-gate				}
23037c478bdstevel@tonic-gate			}
23047c478bdstevel@tonic-gate			/* For receiving PAUSE frames ONLY.
23057c478bdstevel@tonic-gate			 *
23067c478bdstevel@tonic-gate			 *   LOCAL DEVICE  |   LINK PARTNER
23077c478bdstevel@tonic-gate			 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
23087c478bdstevel@tonic-gate			 *-------|---------|-------|---------|--------------------
23097c478bdstevel@tonic-gate			 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
23107c478bdstevel@tonic-gate			 *
23117c478bdstevel@tonic-gate			 */
23127c478bdstevel@tonic-gate			else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
23137c478bdstevel@tonic-gate				(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
23147c478bdstevel@tonic-gate				(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
23157c478bdstevel@tonic-gate				(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
23167c478bdstevel@tonic-gate				hw->fc = e1000_fc_tx_pause;
23177c478bdstevel@tonic-gate				DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
23187c478bdstevel@tonic-gate			}
23197c478bdstevel@tonic-gate			/* For transmitting PAUSE frames ONLY.
23207c478bdstevel@tonic-gate			 *
23217c478bdstevel@tonic-gate			 *   LOCAL DEVICE  |   LINK PARTNER
23227c478bdstevel@tonic-gate			 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
23237c478bdstevel@tonic-gate			 *-------|---------|-------|---------|--------------------
23247c478bdstevel@tonic-gate			 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
23257c478bdstevel@tonic-gate			 *
23267c478bdstevel@tonic-gate			 */
23277c478bdstevel@tonic-gate			else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
23287c478bdstevel@tonic-gate				(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
23297c478bdstevel@tonic-gate				!(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
23307c478bdstevel@tonic-gate				(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
23317c478bdstevel@tonic-gate				hw->fc = e1000_fc_rx_pause;
23327c478bdstevel@tonic-gate				DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
23337c478bdstevel@tonic-gate			}
23347c478bdstevel@tonic-gate			/* Per the IEEE spec, at this point flow control should be
23357c478bdstevel@tonic-gate			 * disabled.  However, we want to consider that we could
23367c478bdstevel@tonic-gate			 * be connected to a legacy switch that doesn't advertise
23377c478bdstevel@tonic-gate			 * desired flow control, but can be forced on the link
23387c478bdstevel@tonic-gate			 * partner.  So if we advertised no flow control, that is
23397c478bdstevel@tonic-gate			 * what we will resolve to.  If we advertised some kind of
23407c478bdstevel@tonic-gate			 * receive capability (Rx Pause Only or Full Flow Control)
23417c478bdstevel@tonic-gate			 * and the link partner advertised none, we will configure
23427c478bdstevel@tonic-gate			 * ourselves to enable Rx Flow Control only.  We can do
23437c478bdstevel@tonic-gate			 * this safely for two reasons:  If the link partner really
23447c478bdstevel@tonic-gate			 * didn't want flow control enabled, and we enable Rx, no
23457c478bdstevel@tonic-gate			 * harm done since we won't be receiving any PAUSE frames
23467c478bdstevel@tonic-gate			 * anyway.  If the intent on the link partner was to have
23477c478bdstevel@tonic-gate			 * flow control enabled, then by us enabling RX only, we
23487c478bdstevel@tonic-gate			 * can at least receive pause frames and process them.
23497c478bdstevel@tonic-gate			 * This is a good idea because in most cases, since we are
23507c478bdstevel@tonic-gate			 * predominantly a server NIC, more times than not we will
23517c478bdstevel@tonic-gate			 * be asked to delay transmission of packets than asking
23527c478bdstevel@tonic-gate			 * our link partner to pause transmission of frames.
23537c478bdstevel@tonic-gate			 */
23547c478bdstevel@tonic-gate#if 0
23557c478bdstevel@tonic-gate			else if(hw->original_fc == e1000_fc_none ||
23567c478bdstevel@tonic-gate				hw->original_fc == e1000_fc_tx_pause) {
23577c478bdstevel@tonic-gate#else
23587c478bdstevel@tonic-gate			else if(hw->fc == e1000_fc_none)
23597c478bdstevel@tonic-gate				DEBUGOUT("Flow Control = NONE.\r\n");
23607c478bdstevel@tonic-gate			else if(hw->fc == e1000_fc_tx_pause) {
23617c478bdstevel@tonic-gate#endif
23627c478bdstevel@tonic-gate				hw->fc = e1000_fc_none;
23637c478bdstevel@tonic-gate				DEBUGOUT("Flow Control = NONE.\r\n");
23647c478bdstevel@tonic-gate			} else {
23657c478bdstevel@tonic-gate				hw->fc = e1000_fc_rx_pause;
23667c478bdstevel@tonic-gate				DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
23677c478bdstevel@tonic-gate			}
23687c478bdstevel@tonic-gate
23697c478bdstevel@tonic-gate			/* Now we need to do one last check...  If we auto-
23707c478bdstevel@tonic-gate			 * negotiated to HALF DUPLEX, flow control should not be
23717c478bdstevel@tonic-gate			 * enabled per IEEE 802.3 spec.
23727c478bdstevel@tonic-gate			 */
23737c478bdstevel@tonic-gate			e1000_get_speed_and_duplex(hw, &speed, &duplex);
23747c478bdstevel@tonic-gate
23757c478bdstevel@tonic-gate			if(duplex == HALF_DUPLEX)
23767c478bdstevel@tonic-gate				hw->fc = e1000_fc_none;
23777c478bdstevel@tonic-gate
23787c478bdstevel@tonic-gate			/* Now we call a subroutine to actually force the MAC
23797c478bdstevel@tonic-gate			 * controller to use the correct flow control settings.
23807c478bdstevel@tonic-gate			 */
23817c478bdstevel@tonic-gate			if((ret_val = e1000_force_mac_fc(hw))) {
23827c478bdstevel@tonic-gate				DEBUGOUT("Error forcing flow control settings\n");
23837c478bdstevel@tonic-gate				return ret_val;
23847c478bdstevel@tonic-gate			}
23857c478bdstevel@tonic-gate		} else {
23867c478bdstevel@tonic-gate			DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
23877c478bdstevel@tonic-gate		}
23887c478bdstevel@tonic-gate	}
23897c478bdstevel@tonic-gate	return E1000_SUCCESS;
23907c478bdstevel@tonic-gate}
23917c478bdstevel@tonic-gate
23927c478bdstevel@tonic-gate/******************************************************************************
23937c478bdstevel@tonic-gate * Checks to see if the link status of the hardware has changed.
23947c478bdstevel@tonic-gate *
23957c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
23967c478bdstevel@tonic-gate *
23977c478bdstevel@tonic-gate * Called by any function that needs to check the link status of the adapter.
23987c478bdstevel@tonic-gate *****************************************************************************/
23997c478bdstevel@tonic-gatestatic int
24007c478bdstevel@tonic-gatee1000_check_for_link(struct e1000_hw *hw)
24017c478bdstevel@tonic-gate{
24027c478bdstevel@tonic-gate	uint32_t rxcw;
24037c478bdstevel@tonic-gate	uint32_t ctrl;
24047c478bdstevel@tonic-gate	uint32_t status;
24057c478bdstevel@tonic-gate	uint32_t rctl;
24067c478bdstevel@tonic-gate	uint32_t signal = 0;
24077c478bdstevel@tonic-gate	int32_t ret_val;
24087c478bdstevel@tonic-gate	uint16_t phy_data;
24097c478bdstevel@tonic-gate	uint16_t lp_capability;
24107c478bdstevel@tonic-gate
24117c478bdstevel@tonic-gate	DEBUGFUNC("e1000_check_for_link");
24127c478bdstevel@tonic-gate
24137c478bdstevel@tonic-gate	/* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
24147c478bdstevel@tonic-gate	 * set when the optics detect a signal. On older adapters, it will be
24157c478bdstevel@tonic-gate	 * cleared when there is a signal.  This applies to fiber media only.
24167c478bdstevel@tonic-gate	 */
24177c478bdstevel@tonic-gate	if(hw->media_type == e1000_media_type_fiber)
24187c478bdstevel@tonic-gate		signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
24197c478bdstevel@tonic-gate
24207c478bdstevel@tonic-gate	ctrl = E1000_READ_REG(hw, CTRL);
24217c478bdstevel@tonic-gate	status = E1000_READ_REG(hw, STATUS);
24227c478bdstevel@tonic-gate	rxcw = E1000_READ_REG(hw, RXCW);
24237c478bdstevel@tonic-gate
24247c478bdstevel@tonic-gate	/* If we have a copper PHY then we only want to go out to the PHY
24257c478bdstevel@tonic-gate	 * registers to see if Auto-Neg has completed and/or if our link
24267c478bdstevel@tonic-gate	 * status has changed.  The get_link_status flag will be set if we
24277c478bdstevel@tonic-gate	 * receive a Link Status Change interrupt or we have Rx Sequence
24287c478bdstevel@tonic-gate	 * Errors.
24297c478bdstevel@tonic-gate	 */
24307c478bdstevel@tonic-gate#if 0
24317c478bdstevel@tonic-gate	if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
24327c478bdstevel@tonic-gate#else
24337c478bdstevel@tonic-gate	if(hw->media_type == e1000_media_type_copper) {
24347c478bdstevel@tonic-gate#endif
24357c478bdstevel@tonic-gate		/* First we want to see if the MII Status Register reports
24367c478bdstevel@tonic-gate		 * link.  If so, then we want to get the current speed/duplex
24377c478bdstevel@tonic-gate		 * of the PHY.
24387c478bdstevel@tonic-gate		 * Read the register twice since the link bit is sticky.
24397c478bdstevel@tonic-gate		 */
24407c478bdstevel@tonic-gate		if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
24417c478bdstevel@tonic-gate			return ret_val;
24427c478bdstevel@tonic-gate		if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
24437c478bdstevel@tonic-gate			return ret_val;
24447c478bdstevel@tonic-gate
24457c478bdstevel@tonic-gate		if(phy_data & MII_SR_LINK_STATUS) {
24467c478bdstevel@tonic-gate#if 0
24477c478bdstevel@tonic-gate			hw->get_link_status = FALSE;
24487c478bdstevel@tonic-gate#endif
24497c478bdstevel@tonic-gate		} else {
24507c478bdstevel@tonic-gate			/* No link detected */
24517c478bdstevel@tonic-gate			return -E1000_ERR_NOLINK;
24527c478bdstevel@tonic-gate		}
24537c478bdstevel@tonic-gate
24547c478bdstevel@tonic-gate		/* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
24557c478bdstevel@tonic-gate		 * have Si on board that is 82544 or newer, Auto
24567c478bdstevel@tonic-gate		 * Speed Detection takes care of MAC speed/duplex
24577c478bdstevel@tonic-gate		 * configuration.  So we only need to configure Collision
24587c478bdstevel@tonic-gate		 * Distance in the MAC.  Otherwise, we need to force
24597c478bdstevel@tonic-gate		 * speed/duplex on the MAC to the current PHY speed/duplex
24607c478bdstevel@tonic-gate		 * settings.
24617c478bdstevel@tonic-gate		 */
24627c478bdstevel@tonic-gate		if(hw->mac_type >= e1000_82544)
24637c478bdstevel@tonic-gate			e1000_config_collision_dist(hw);
24647c478bdstevel@tonic-gate		else {
24657c478bdstevel@tonic-gate			if((ret_val = e1000_config_mac_to_phy(hw))) {
24667c478bdstevel@tonic-gate				DEBUGOUT("Error configuring MAC to PHY settings\n");
24677c478bdstevel@tonic-gate				return ret_val;
24687c478bdstevel@tonic-gate			}
24697c478bdstevel@tonic-gate		}
24707c478bdstevel@tonic-gate
24717c478bdstevel@tonic-gate		/* Configure Flow Control now that Auto-Neg has completed. First, we
24727c478bdstevel@tonic-gate		 * need to restore the desired flow control settings because we may
24737c478bdstevel@tonic-gate		 * have had to re-autoneg with a different link partner.
24747c478bdstevel@tonic-gate		 */
24757c478bdstevel@tonic-gate		if((ret_val = e1000_config_fc_after_link_up(hw))) {
24767c478bdstevel@tonic-gate			DEBUGOUT("Error configuring flow control\n");
24777c478bdstevel@tonic-gate			return ret_val;
24787c478bdstevel@tonic-gate		}
24797c478bdstevel@tonic-gate
24807c478bdstevel@tonic-gate		/* At this point we know that we are on copper and we have
24817c478bdstevel@tonic-gate		 * auto-negotiated link.  These are conditions for checking the link
24827c478bdstevel@tonic-gate		 * parter capability register.  We use the link partner capability to
24837c478bdstevel@tonic-gate		 * determine if TBI Compatibility needs to be turned on or off.  If
24847c478bdstevel@tonic-gate		 * the link partner advertises any speed in addition to Gigabit, then
24857c478bdstevel@tonic-gate		 * we assume that they are GMII-based, and TBI compatibility is not
24867c478bdstevel@tonic-gate		 * needed. If no other speeds are advertised, we assume the link
24877c478bdstevel@tonic-gate		 * partner is TBI-based, and we turn on TBI Compatibility.
24887c478bdstevel@tonic-gate		 */
24897c478bdstevel@tonic-gate		if(hw->tbi_compatibility_en) {
24907c478bdstevel@tonic-gate			if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
24917c478bdstevel@tonic-gate			                                 &lp_capability)))
24927c478bdstevel@tonic-gate				return ret_val;
24937c478bdstevel@tonic-gate			if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
24947c478bdstevel@tonic-gate                                NWAY_LPAR_10T_FD_CAPS |
24957c478bdstevel@tonic-gate                                NWAY_LPAR_100TX_HD_CAPS |
24967c478bdstevel@tonic-gate                                NWAY_LPAR_100TX_FD_CAPS |
24977c478bdstevel@tonic-gate                                NWAY_LPAR_100T4_CAPS)) {
24987c478bdstevel@tonic-gate				/* If our link partner advertises anything in addition to
24997c478bdstevel@tonic-gate				 * gigabit, we do not need to enable TBI compatibility.
25007c478bdstevel@tonic-gate				 */
25017c478bdstevel@tonic-gate				if(hw->tbi_compatibility_on) {
25027c478bdstevel@tonic-gate					/* If we previously were in the mode, turn it off. */
25037c478bdstevel@tonic-gate					rctl = E1000_READ_REG(hw, RCTL);
25047c478bdstevel@tonic-gate					rctl &= ~E1000_RCTL_SBP;
25057c478bdstevel@tonic-gate					E1000_WRITE_REG(hw, RCTL, rctl);
25067c478bdstevel@tonic-gate					hw->tbi_compatibility_on = FALSE;
25077c478bdstevel@tonic-gate				}
25087c478bdstevel@tonic-gate			} else {
25097c478bdstevel@tonic-gate				/* If TBI compatibility is was previously off, turn it on. For
25107c478bdstevel@tonic-gate				 * compatibility with a TBI link partner, we will store bad
25117c478bdstevel@tonic-gate				 * packets. Some frames have an additional byte on the end and
25127c478bdstevel@tonic-gate				 * will look like CRC errors to to the hardware.
25137c478bdstevel@tonic-gate				 */
25147c478bdstevel@tonic-gate				if(!hw->tbi_compatibility_on) {
25157c478bdstevel@tonic-gate					hw->tbi_compatibility_on = TRUE;
25167c478bdstevel@tonic-gate					rctl = E1000_READ_REG(hw, RCTL);
25177c478bdstevel@tonic-gate					rctl |= E1000_RCTL_SBP;
25187c478bdstevel@tonic-gate					E1000_WRITE_REG(hw, RCTL, rctl);
25197c478bdstevel@tonic-gate				}
25207c478bdstevel@tonic-gate			}
25217c478bdstevel@tonic-gate		}
25227c478bdstevel@tonic-gate	}
25237c478bdstevel@tonic-gate	/* If we don't have link (auto-negotiation failed or link partner cannot
25247c478bdstevel@tonic-gate	 * auto-negotiate), the cable is plugged in (we have signal), and our
25257c478bdstevel@tonic-gate	 * link partner is not trying to auto-negotiate with us (we are receiving
25267c478bdstevel@tonic-gate	 * idles or data), we need to force link up. We also need to give
25277c478bdstevel@tonic-gate	 * auto-negotiation time to complete, in case the cable was just plugged
25287c478bdstevel@tonic-gate	 * in. The autoneg_failed flag does this.
25297c478bdstevel@tonic-gate	 */
25307c478bdstevel@tonic-gate	else if((((hw->media_type == e1000_media_type_fiber) &&
25317c478bdstevel@tonic-gate	        ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
25327c478bdstevel@tonic-gate	        (hw->media_type == e1000_media_type_internal_serdes)) &&
25337c478bdstevel@tonic-gate		(!(status & E1000_STATUS_LU)) &&
25347c478bdstevel@tonic-gate		(!(rxcw & E1000_RXCW_C))) {
25357c478bdstevel@tonic-gate		if(hw->autoneg_failed == 0) {
25367c478bdstevel@tonic-gate			hw->autoneg_failed = 1;
25377c478bdstevel@tonic-gate			return 0;
25387c478bdstevel@tonic-gate		}
25397c478bdstevel@tonic-gate		DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
25407c478bdstevel@tonic-gate
25417c478bdstevel@tonic-gate		/* Disable auto-negotiation in the TXCW register */
25427c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
25437c478bdstevel@tonic-gate
25447c478bdstevel@tonic-gate		/* Force link-up and also force full-duplex. */
25457c478bdstevel@tonic-gate		ctrl = E1000_READ_REG(hw, CTRL);
25467c478bdstevel@tonic-gate		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
25477c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, CTRL, ctrl);
25487c478bdstevel@tonic-gate
25497c478bdstevel@tonic-gate		/* Configure Flow Control after forcing link up. */
25507c478bdstevel@tonic-gate		if((ret_val = e1000_config_fc_after_link_up(hw))) {
25517c478bdstevel@tonic-gate			DEBUGOUT("Error configuring flow control\n");
25527c478bdstevel@tonic-gate			return ret_val;
25537c478bdstevel@tonic-gate		}
25547c478bdstevel@tonic-gate	}
25557c478bdstevel@tonic-gate	/* If we are forcing link and we are receiving /C/ ordered sets, re-enable
25567c478bdstevel@tonic-gate	 * auto-negotiation in the TXCW register and disable forced link in the
25577c478bdstevel@tonic-gate	 * Device Control register in an attempt to auto-negotiate with our link
25587c478bdstevel@tonic-gate	 * partner.
25597c478bdstevel@tonic-gate	 */
25607c478bdstevel@tonic-gate	else if(((hw->media_type == e1000_media_type_fiber)  ||
25617c478bdstevel@tonic-gate	         (hw->media_type == e1000_media_type_internal_serdes)) &&
25627c478bdstevel@tonic-gate		(ctrl & E1000_CTRL_SLU) &&
25637c478bdstevel@tonic-gate		(rxcw & E1000_RXCW_C)) {
25647c478bdstevel@tonic-gate		DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
25657c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, TXCW, hw->txcw);
25667c478bdstevel@tonic-gate		E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
25677c478bdstevel@tonic-gate	}
25687c478bdstevel@tonic-gate#if 0
25697c478bdstevel@tonic-gate	/* If we force link for non-auto-negotiation switch, check link status
25707c478bdstevel@tonic-gate	 * based on MAC synchronization for internal serdes media type.
25717c478bdstevel@tonic-gate	 */
25727c478bdstevel@tonic-gate	else if((hw->media_type == e1000_media_type_internal_serdes) &&
25737c478bdstevel@tonic-gate			!(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
25747c478bdstevel@tonic-gate		/* SYNCH bit and IV bit are sticky. */
25757c478bdstevel@tonic-gate		udelay(10);
25767c478bdstevel@tonic-gate		if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
25777c478bdstevel@tonic-gate			if(!(rxcw & E1000_RXCW_IV)) {
25787c478bdstevel@tonic-gate				hw->serdes_link_down = FALSE;
25797c478bdstevel@tonic-gate				DEBUGOUT("SERDES: Link is up.\n");
25807c478bdstevel@tonic-gate			}
25817c478bdstevel@tonic-gate		} else {
25827c478bdstevel@tonic-gate			hw->serdes_link_down = TRUE;
25837c478bdstevel@tonic-gate			DEBUGOUT("SERDES: Link is down.\n");
25847c478bdstevel@tonic-gate		}
25857c478bdstevel@tonic-gate	}
25867c478bdstevel@tonic-gate#endif
25877c478bdstevel@tonic-gate	return E1000_SUCCESS;
25887c478bdstevel@tonic-gate}
25897c478bdstevel@tonic-gate
25907c478bdstevel@tonic-gate/******************************************************************************
25917c478bdstevel@tonic-gate * Detects the current speed and duplex settings of the hardware.
25927c478bdstevel@tonic-gate *
25937c478bdstevel@tonic-gate * hw - Struct containing variables accessed by shared code
25947c478bdstevel@tonic-gate * speed - Speed of the connection
25957c478bdstevel@tonic-gate * duplex - Duplex setting of the connection
25967c478bdstevel@tonic-gate *****************************************************************************/
25977c478bdstevel@tonic-gatestatic void
25987c478bdstevel@tonic-gatee1000_get_speed_and_duplex(struct e1000_hw *hw,
25997c478bdstevel@tonic-gate                           uint16_t *speed,
26007c478bdstevel@tonic-gate                           uint16_t *duplex)
26017c478bdstevel@tonic-gate{
26027c478bdstevel@tonic-gate	uint32_t status;
26037c478bdstevel@tonic-gate
26047c478bdstevel@tonic-gate	DEBUGFUNC("e1000_get_speed_and_duplex");
26057c478bdstevel@tonic-gate
26067c478bdstevel@tonic-gate	if(hw->mac_type >= e1000_82543) {
26077c478bdstevel@tonic-gate		status = E1000_READ_REG(hw, STATUS);
26087c478bdstevel@tonic-gate		if(status & E1000_STATUS_SPEED_1000) {
26097c478bdstevel@tonic-gate			*speed = SPEED_1000;
26107c478bdstevel@tonic-gate			DEBUGOUT("1000 Mbs, ");
26117c478bdstevel@tonic-gate		} else if(status & E1000_STATUS_SPEED_100) {
26127c478bdstevel@tonic-gate			*speed = SPEED_100;
26137c478bdstevel@tonic-gate			DEBUGOUT("100 Mbs, ");
26147c478bdstevel@tonic-gate		} else {
26157c478bdstevel@tonic-gate			*speed = SPEED_10;
26167c478bdstevel@tonic-gate			DEBUGOUT("10 Mbs, ");
26177c478bdstevel@tonic-gate		}
26187c478bdstevel@tonic-gate
26197c478bdstevel@tonic-gate		if(status & E1000_STATUS_FD) {
26207c478bdstevel@tonic-gate			*duplex = FULL_DUPLEX;
26217c478bdstevel@tonic-gate			DEBUGOUT("Full Duplex\r\n");
26227c478bdstevel@tonic-gate		} else {
26237c478bdstevel@tonic-gate			*duplex = HALF_DUPLEX;
26247c478bdstevel@tonic-gate			DEBUGOUT(" Half Duplex\r\n");
26257c478bdstevel@tonic-gate		}
26267c478bdstevel@tonic-gate	} else {
26277c478bdstevel@tonic-gate		DEBUGOUT("1000 Mbs, Full Duplex\r\n");
26287c478bdstevel@tonic-gate		*speed = SPEED_1000;
26297c478bdstevel@tonic-gate		*duplex = FULL_DUPLEX;
26307c478bdstevel@tonic-gate	}
26317c478bdstevel@tonic-gate}
26327c478bdstevel@tonic-gate
26337c478bdstevel@tonic-gate/******************************************************************************
26347c478bdstevel@tonic-gate* Blocks until autoneg completes or times out (~4.5 seconds)
26357c478bdstevel@tonic-gate*
26367c478bdstevel@tonic-gate* hw - Struct containing variables accessed by shared code
26377c478bdstevel@tonic-gate******************************************************************************/
26387c478bdstevel@tonic-gatestatic int
26397c478bdstevel@tonic-gatee1000_wait_autoneg(struct e1000_hw *hw)
26407c478bdstevel@tonic-gate{
26417c478bdstevel@tonic-gate	int32_t ret_val;
26427c478bdstevel@tonic-gate	uint16_t i;
26437c478bdstevel@tonic-gate	uint16_t phy_data;
26447c478bdstevel@tonic-gate
26457c478bdstevel@tonic-gate	DEBUGFUNC("e1000_wait_autoneg");
26467c478bdstevel@tonic-gate	DEBUGOUT("Waiting for Auto-Neg to complete.\n");
26477c478bdstevel@tonic-gate
26487c478bdstevel@tonic-gate	/* We will wait for autoneg to complete or 4.5 seconds to expire. */
26497c478bdstevel@tonic-gate	for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
26507c478bdstevel@tonic-gate		/* Read the MII Status Register and wait for Auto-Neg
26517c478bdstevel@tonic-gate		 * Complete bit to be set.
26527c478bdstevel@tonic-gate		 */
26537c478bdstevel@tonic-gate		if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
26547c478bdstevel@tonic-gate			return ret_val;
26557c478bdstevel@tonic-gate		if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
26567c478bdstevel@tonic-gate			return ret_val;
26577c478bdstevel@tonic-gate		if(phy_data & MII_SR_AUTONEG_COMPLETE) {
26587c478bdstevel@tonic-gate			DEBUGOUT("Auto-Neg complete.\n");
26597c478bdstevel@tonic-gate			return E1000_SUCCESS;
26607c478bdstevel@tonic-gate		}
26617c478bdstevel@tonic-gate		mdelay(100);
26627c478bdstevel@tonic-gate	}
26637c478bdstevel@tonic-gate	DEBUGOUT("Auto-Neg timedout.\n");
26647c478bdstevel@tonic-gate	return -E1000_ERR_TIMEOUT;
26657c478bdstevel@tonic-gate}
26667c478bdstevel@tonic-gate
26677c478bdstevel@tonic-gate/******************************************************************************
26687c478bdstevel@tonic-gate* Raises the Management Data Clock
26697c478bdstevel@tonic-gate*
26707c478bdstevel@tonic-gate* hw - Struct containing variables accessed by shared code
26717c478bdstevel@tonic-gate* ctrl - Device control register's current value
26727c478bdstevel@tonic-gate******************************************************************************/
26737c478bdstevel@tonic-gatestatic void
26747c478bdstevel@tonic-gatee1000_raise_mdi_clk(struct e1000_hw *hw,
26757c478bdstevel@tonic-gate                    uint32_t *ctrl)
26767c478bdstevel@tonic-gate{
26777c478bdstevel@tonic-gate	/* Raise the clock input to the Management Data Clock (by setting the MDC
26787c478bdstevel@tonic-gate	 * bit), and then delay 10 microseconds.
26797c478bdstevel@tonic-gate	 */
26807c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
26817c478bdstevel@tonic-gate	E1000_WRITE_FLUSH(hw);
26827c478bdstevel@tonic-gate	udelay(10);
26837c478bdstevel@tonic-gate}
26847c478bdstevel@tonic-gate
26857c478bdstevel@tonic-gate/******************************************************************************
26867c478bdstevel@tonic-gate* Lowers the Management Data Clock
26877c478bdstevel@tonic-gate*
26887c478bdstevel@tonic-gate* hw - Struct containing variables accessed by shared code
26897c478bdstevel@tonic-gate* ctrl - Device control register's current value
26907c478bdstevel@tonic-gate******************************************************************************/
26917c478bdstevel@tonic-gatestatic void
26927c478bdstevel@tonic-gatee1000_lower_mdi_clk(struct e1000_hw *hw,
26937c478bdstevel@tonic-gate                    uint32_t *ctrl)
26947c478bdstevel@tonic-gate{
26957c478bdstevel@tonic-gate	/* Lower the clock input to the Management Data Clock (by clearing the MDC
26967c478bdstevel@tonic-gate	 * bit), and then delay 10 microseconds.
26977c478bdstevel@tonic-gate	 */
26987c478bdstevel@tonic-gate	E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
26997c478bdstevel@tonic-gate	E1000_WRITE_FLUSH(hw);
27007c478bdstevel@tonic-gate	udelay(10);
27017c478bdstevel@tonic-gate}
27027c478bdstevel@tonic-gate
27037c478bdstevel@tonic-gate/******************************************************************************
27047c478bdstevel@tonic-gate* Shifts data bits out to the PHY
27057c478bdstevel@tonic-gate*
27067c478bdstevel@tonic-gate* hw - Struct containing variables accessed by shared code
27077c478bdstevel@tonic-gate* data - Data to send out to the PHY
27087c478bdstevel@tonic-gate* count - Number of bits to shift out
27097c478bdstevel@tonic-gate*
27107c478bdstevel@tonic-gate* Bits are shifted out in MSB to LSB order.
27117c478bdstevel@tonic-gate******************************************************************************/
27127c478bdstevel@tonic-gatestatic void
27137c478bdstevel@tonic-gatee1000_shift_out_mdi_bits(struct e1000_hw *hw,
27147c478bdstevel@tonic-gate                         uint32_t data,
27157c478bdstevel@tonic-gate                         uint16_t count)
27167c478bdstevel@tonic-gate{
27177c478bdstevel@tonic-gate	uint32_t ctrl;
27187c478bdstevel@tonic-gate	uint32_t mask;
27197c478bdstevel@tonic-gate
27207c478bdstevel@tonic-gate	/* We need to shift "count" number of bits out to the PHY. So, the value
27217c478bdstevel@tonic-gate	 * in the "data" parameter will be shifted out to the PHY one bit at a
27227c478bdstevel@tonic-gate	 * time. In order to do this, "data" must be broken down into bits.
27237c478bdstevel@tonic-gate	 */
27247c478bdstevel@tonic-gate	mask = 0x01;
27257c478bdstevel@tonic-gate	mask <<= (count - 1);
27267c478bdstevel@tonic-gate
27277c478bdstevel@tonic-gate	ctrl = E1000_READ_REG(hw, CTRL);
27287c478bdstevel@tonic-gate
27297c478bdstevel@tonic-gate	/* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
27307c478bdstevel@tonic-gate	ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
27317c478bdstevel@tonic-gate
27327c478bdstevel@tonic-gate	while(mask) {
27337c478bdstevel@tonic-gate		/* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
27347c478bdstevel@tonic-gate		 * then raising and lowering the Management Data Clock. A "0" is
2735