17c478bdstevel@tonic-gate#ifndef I386_BITS_CPU_H
27c478bdstevel@tonic-gate#define I386_BITS_CPU_H
37c478bdstevel@tonic-gate
47c478bdstevel@tonic-gate
57c478bdstevel@tonic-gate/* Sample usage: CPU_FEATURE_P(cpu.x86_capability, FPU) */
67c478bdstevel@tonic-gate#define CPU_FEATURE_P(CAP, FEATURE) \
77c478bdstevel@tonic-gate	(!!(CAP[(X86_FEATURE_##FEATURE)/32] & ((X86_FEATURE_##FEATURE) & 0x1f)))
87c478bdstevel@tonic-gate
97c478bdstevel@tonic-gate#define NCAPINTS	4	/* Currently we have 4 32-bit words worth of info */
107c478bdstevel@tonic-gate
117c478bdstevel@tonic-gate/* Intel-defined CPU features, CPUID level 0x00000001, word 0 */
127c478bdstevel@tonic-gate#define X86_FEATURE_FPU		(0*32+ 0) /* Onboard FPU */
137c478bdstevel@tonic-gate#define X86_FEATURE_VME		(0*32+ 1) /* Virtual Mode Extensions */
147c478bdstevel@tonic-gate#define X86_FEATURE_DE		(0*32+ 2) /* Debugging Extensions */
157c478bdstevel@tonic-gate#define X86_FEATURE_PSE 	(0*32+ 3) /* Page Size Extensions */
167c478bdstevel@tonic-gate#define X86_FEATURE_TSC		(0*32+ 4) /* Time Stamp Counter */
177c478bdstevel@tonic-gate#define X86_FEATURE_MSR		(0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
187c478bdstevel@tonic-gate#define X86_FEATURE_PAE		(0*32+ 6) /* Physical Address Extensions */
197c478bdstevel@tonic-gate#define X86_FEATURE_MCE		(0*32+ 7) /* Machine Check Architecture */
207c478bdstevel@tonic-gate#define X86_FEATURE_CX8		(0*32+ 8) /* CMPXCHG8 instruction */
217c478bdstevel@tonic-gate#define X86_FEATURE_APIC	(0*32+ 9) /* Onboard APIC */
227c478bdstevel@tonic-gate#define X86_FEATURE_SEP		(0*32+11) /* SYSENTER/SYSEXIT */
237c478bdstevel@tonic-gate#define X86_FEATURE_MTRR	(0*32+12) /* Memory Type Range Registers */
247c478bdstevel@tonic-gate#define X86_FEATURE_PGE		(0*32+13) /* Page Global Enable */
257c478bdstevel@tonic-gate#define X86_FEATURE_MCA		(0*32+14) /* Machine Check Architecture */
267c478bdstevel@tonic-gate#define X86_FEATURE_CMOV	(0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
277c478bdstevel@tonic-gate#define X86_FEATURE_PAT		(0*32+16) /* Page Attribute Table */
287c478bdstevel@tonic-gate#define X86_FEATURE_PSE36	(0*32+17) /* 36-bit PSEs */
297c478bdstevel@tonic-gate#define X86_FEATURE_PN		(0*32+18) /* Processor serial number */
307c478bdstevel@tonic-gate#define X86_FEATURE_CLFLSH	(0*32+19) /* Supports the CLFLUSH instruction */
317c478bdstevel@tonic-gate#define X86_FEATURE_DTES	(0*32+21) /* Debug Trace Store */
327c478bdstevel@tonic-gate#define X86_FEATURE_ACPI	(0*32+22) /* ACPI via MSR */
337c478bdstevel@tonic-gate#define X86_FEATURE_MMX		(0*32+23) /* Multimedia Extensions */
347c478bdstevel@tonic-gate#define X86_FEATURE_FXSR	(0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
357c478bdstevel@tonic-gate				          /* of FPU context), and CR4.OSFXSR available */
367c478bdstevel@tonic-gate#define X86_FEATURE_XMM		(0*32+25) /* Streaming SIMD Extensions */
377c478bdstevel@tonic-gate#define X86_FEATURE_XMM2	(0*32+26) /* Streaming SIMD Extensions-2 */
387c478bdstevel@tonic-gate#define X86_FEATURE_SELFSNOOP	(0*32+27) /* CPU self snoop */
397c478bdstevel@tonic-gate#define X86_FEATURE_HT		(0*32+28) /* Hyper-Threading */
407c478bdstevel@tonic-gate#define X86_FEATURE_ACC		(0*32+29) /* Automatic clock control */
417c478bdstevel@tonic-gate#define X86_FEATURE_IA64	(0*32+30) /* IA-64 processor */
427c478bdstevel@tonic-gate
437c478bdstevel@tonic-gate/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
447c478bdstevel@tonic-gate/* Don't duplicate feature flags which are redundant with Intel! */
457c478bdstevel@tonic-gate#define X86_FEATURE_SYSCALL	(1*32+11) /* SYSCALL/SYSRET */
467c478bdstevel@tonic-gate#define X86_FEATURE_MMXEXT	(1*32+22) /* AMD MMX extensions */
477c478bdstevel@tonic-gate#define X86_FEATURE_LM		(1*32+29) /* Long Mode (x86-64) */
487c478bdstevel@tonic-gate#define X86_FEATURE_3DNOWEXT	(1*32+30) /* AMD 3DNow! extensions */
497c478bdstevel@tonic-gate#define X86_FEATURE_3DNOW	(1*32+31) /* 3DNow! */
507c478bdstevel@tonic-gate
517c478bdstevel@tonic-gate/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
527c478bdstevel@tonic-gate#define X86_FEATURE_RECOVERY	(2*32+ 0) /* CPU in recovery mode */
537c478bdstevel@tonic-gate#define X86_FEATURE_LONGRUN	(2*32+ 1) /* Longrun power control */
547c478bdstevel@tonic-gate#define X86_FEATURE_LRTI	(2*32+ 3) /* LongRun table interface */
557c478bdstevel@tonic-gate
567c478bdstevel@tonic-gate/* Other features, Linux-defined mapping, word 3 */
577c478bdstevel@tonic-gate/* This range is used for feature bits which conflict or are synthesized */
587c478bdstevel@tonic-gate#define X86_FEATURE_CXMMX	(3*32+ 0) /* Cyrix MMX extensions */
597c478bdstevel@tonic-gate#define X86_FEATURE_K6_MTRR	(3*32+ 1) /* AMD K6 nonstandard MTRRs */
607c478bdstevel@tonic-gate#define X86_FEATURE_CYRIX_ARR	(3*32+ 2) /* Cyrix ARRs (= MTRRs) */
617c478bdstevel@tonic-gate#define X86_FEATURE_CENTAUR_MCR	(3*32+ 3) /* Centaur MCRs (= MTRRs) */
627c478bdstevel@tonic-gate
637c478bdstevel@tonic-gate#define MAX_X86_VENDOR_ID 16
647c478bdstevel@tonic-gatestruct cpuinfo_x86 {
657c478bdstevel@tonic-gate	uint8_t	 x86;		/* CPU family */
667c478bdstevel@tonic-gate	uint8_t	 x86_model;
677c478bdstevel@tonic-gate	uint8_t	 x86_mask;
687c478bdstevel@tonic-gate
697c478bdstevel@tonic-gate       	int	 cpuid_level;	/* Maximum supported CPUID level, -1=no CPUID */
707c478bdstevel@tonic-gate	unsigned x86_capability[NCAPINTS];
717c478bdstevel@tonic-gate	char	 x86_vendor_id[MAX_X86_VENDOR_ID];
727c478bdstevel@tonic-gate};
737c478bdstevel@tonic-gate
747c478bdstevel@tonic-gate
757c478bdstevel@tonic-gate#define X86_VENDOR_INTEL 0
767c478bdstevel@tonic-gate#define X86_VENDOR_CYRIX 1
777c478bdstevel@tonic-gate#define X86_VENDOR_AMD 2
787c478bdstevel@tonic-gate#define X86_VENDOR_UMC 3
797c478bdstevel@tonic-gate#define X86_VENDOR_NEXGEN 4
807c478bdstevel@tonic-gate#define X86_VENDOR_CENTAUR 5
817c478bdstevel@tonic-gate#define X86_VENDOR_RISE 6
827c478bdstevel@tonic-gate#define X86_VENDOR_TRANSMETA 7
837c478bdstevel@tonic-gate#define X86_VENDOR_NSC 8
847c478bdstevel@tonic-gate#define X86_VENDOR_UNKNOWN 0xff
857c478bdstevel@tonic-gate
867c478bdstevel@tonic-gate/*
877c478bdstevel@tonic-gate * EFLAGS bits
887c478bdstevel@tonic-gate */
897c478bdstevel@tonic-gate#define X86_EFLAGS_CF	0x00000001 /* Carry Flag */
907c478bdstevel@tonic-gate#define X86_EFLAGS_PF	0x00000004 /* Parity Flag */
917c478bdstevel@tonic-gate#define X86_EFLAGS_AF	0x00000010 /* Auxillary carry Flag */
927c478bdstevel@tonic-gate#define X86_EFLAGS_ZF	0x00000040 /* Zero Flag */
937c478bdstevel@tonic-gate#define X86_EFLAGS_SF	0x00000080 /* Sign Flag */
947c478bdstevel@tonic-gate#define X86_EFLAGS_TF	0x00000100 /* Trap Flag */
957c478bdstevel@tonic-gate#define X86_EFLAGS_IF	0x00000200 /* Interrupt Flag */
967c478bdstevel@tonic-gate#define X86_EFLAGS_DF	0x00000400 /* Direction Flag */
977c478bdstevel@tonic-gate#define X86_EFLAGS_OF	0x00000800 /* Overflow Flag */
987c478bdstevel@tonic-gate#define X86_EFLAGS_IOPL	0x00003000 /* IOPL mask */
997c478bdstevel@tonic-gate#define X86_EFLAGS_NT	0x00004000 /* Nested Task */
1007c478bdstevel@tonic-gate#define X86_EFLAGS_RF	0x00010000 /* Resume Flag */
1017c478bdstevel@tonic-gate#define X86_EFLAGS_VM	0x00020000 /* Virtual Mode */
1027c478bdstevel@tonic-gate#define X86_EFLAGS_AC	0x00040000 /* Alignment Check */
1037c478bdstevel@tonic-gate#define X86_EFLAGS_VIF	0x00080000 /* Virtual Interrupt Flag */
1047c478bdstevel@tonic-gate#define X86_EFLAGS_VIP	0x00100000 /* Virtual Interrupt Pending */
1057c478bdstevel@tonic-gate#define X86_EFLAGS_ID	0x00200000 /* CPUID detection flag */
1067c478bdstevel@tonic-gate
1077c478bdstevel@tonic-gate/*
1087c478bdstevel@tonic-gate * Generic CPUID function
1097c478bdstevel@tonic-gate */
1107c478bdstevel@tonic-gatestatic inline void cpuid(int op,
1117c478bdstevel@tonic-gate	unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
1127c478bdstevel@tonic-gate{
1137c478bdstevel@tonic-gate	__asm__("cpuid"
1147c478bdstevel@tonic-gate		: "=a" (*eax),
1157c478bdstevel@tonic-gate		  "=b" (*ebx),
1167c478bdstevel@tonic-gate		  "=c" (*ecx),
1177c478bdstevel@tonic-gate		  "=d" (*edx)
1187c478bdstevel@tonic-gate		: "0" (op));
1197c478bdstevel@tonic-gate}
1207c478bdstevel@tonic-gate
1217c478bdstevel@tonic-gate/*
1227c478bdstevel@tonic-gate * CPUID functions returning a single datum
1237c478bdstevel@tonic-gate */
1247c478bdstevel@tonic-gatestatic inline unsigned int cpuid_eax(unsigned int op)
1257c478bdstevel@tonic-gate{
1267c478bdstevel@tonic-gate	unsigned int eax;
1277c478bdstevel@tonic-gate
1287c478bdstevel@tonic-gate	__asm__("cpuid"
1297c478bdstevel@tonic-gate		: "=a" (eax)
1307c478bdstevel@tonic-gate		: "0" (op)
1317c478bdstevel@tonic-gate		: "bx", "cx", "dx");
1327c478bdstevel@tonic-gate	return eax;
1337c478bdstevel@tonic-gate}
1347c478bdstevel@tonic-gatestatic inline unsigned int cpuid_ebx(unsigned int op)
1357c478bdstevel@tonic-gate{
1367c478bdstevel@tonic-gate	unsigned int eax, ebx;
1377c478bdstevel@tonic-gate
1387c478bdstevel@tonic-gate	__asm__("cpuid"
1397c478bdstevel@tonic-gate		: "=a" (eax), "=b" (ebx)
1407c478bdstevel@tonic-gate		: "0" (op)
1417c478bdstevel@tonic-gate		: "cx", "dx" );
1427c478bdstevel@tonic-gate	return ebx;
1437c478bdstevel@tonic-gate}
1447c478bdstevel@tonic-gatestatic inline unsigned int cpuid_ecx(unsigned int op)
1457c478bdstevel@tonic-gate{
1467c478bdstevel@tonic-gate	unsigned int eax, ecx;
1477c478bdstevel@tonic-gate
1487c478bdstevel@tonic-gate	__asm__("cpuid"
1497c478bdstevel@tonic-gate		: "=a" (eax), "=c" (ecx)
1507c478bdstevel@tonic-gate		: "0" (op)
1517c478bdstevel@tonic-gate		: "bx", "dx" );
1527c478bdstevel@tonic-gate	return ecx;
1537c478bdstevel@tonic-gate}
1547c478bdstevel@tonic-gatestatic inline unsigned int cpuid_edx(unsigned int op)
1557c478bdstevel@tonic-gate{
1567c478bdstevel@tonic-gate	unsigned int eax, edx;
1577c478bdstevel@tonic-gate
1587c478bdstevel@tonic-gate	__asm__("cpuid"
1597c478bdstevel@tonic-gate		: "=a" (eax), "=d" (edx)
1607c478bdstevel@tonic-gate		: "0" (op)
1617c478bdstevel@tonic-gate		: "bx", "cx");
1627c478bdstevel@tonic-gate	return edx;
1637c478bdstevel@tonic-gate}
1647c478bdstevel@tonic-gate
1657c478bdstevel@tonic-gate/*
1667c478bdstevel@tonic-gate * Intel CPU features in CR4
1677c478bdstevel@tonic-gate */
1687c478bdstevel@tonic-gate#define X86_CR4_VME		0x0001	/* enable vm86 extensions */
1697c478bdstevel@tonic-gate#define X86_CR4_PVI		0x0002	/* virtual interrupts flag enable */
1707c478bdstevel@tonic-gate#define X86_CR4_TSD		0x0004	/* disable time stamp at ipl 3 */
1717c478bdstevel@tonic-gate#define X86_CR4_DE		0x0008	/* enable debugging extensions */
1727c478bdstevel@tonic-gate#define X86_CR4_PSE		0x0010	/* enable page size extensions */
1737c478bdstevel@tonic-gate#define X86_CR4_PAE		0x0020	/* enable physical address extensions */
1747c478bdstevel@tonic-gate#define X86_CR4_MCE		0x0040	/* Machine check enable */
1757c478bdstevel@tonic-gate#define X86_CR4_PGE		0x0080	/* enable global pages */
1767c478bdstevel@tonic-gate#define X86_CR4_PCE		0x0100	/* enable performance counters at ipl 3 */
1777c478bdstevel@tonic-gate#define X86_CR4_OSFXSR		0x0200	/* enable fast FPU save and restore */
1787c478bdstevel@tonic-gate#define X86_CR4_OSXMMEXCPT	0x0400	/* enable unmasked SSE exceptions */
1797c478bdstevel@tonic-gate
1807c478bdstevel@tonic-gate
1817c478bdstevel@tonic-gate#define MSR_K6_EFER			0xC0000080
1827c478bdstevel@tonic-gate/* EFER bits: */
1837c478bdstevel@tonic-gate#define _EFER_SCE 0  /* SYSCALL/SYSRET */
1847c478bdstevel@tonic-gate#define _EFER_LME 8  /* Long mode enable */
1857c478bdstevel@tonic-gate#define _EFER_LMA 10 /* Long mode active (read-only) */
1867c478bdstevel@tonic-gate#define _EFER_NX 11  /* No execute enable */
1877c478bdstevel@tonic-gate
1887c478bdstevel@tonic-gate#define EFER_SCE (1<<_EFER_SCE)
1897c478bdstevel@tonic-gate#define EFER_LME (1<<EFER_LME)
1907c478bdstevel@tonic-gate#define EFER_LMA (1<<EFER_LMA)
1917c478bdstevel@tonic-gate#define EFER_NX (1<<_EFER_NX)
1927c478bdstevel@tonic-gate
1937c478bdstevel@tonic-gate#define rdmsr(msr,val1,val2) \
1947c478bdstevel@tonic-gate     __asm__ __volatile__("rdmsr" \
1957c478bdstevel@tonic-gate			  : "=a" (val1), "=d" (val2) \
1967c478bdstevel@tonic-gate			  : "c" (msr))
1977c478bdstevel@tonic-gate
1987c478bdstevel@tonic-gate#define wrmsr(msr,val1,val2) \
1997c478bdstevel@tonic-gate     __asm__ __volatile__("wrmsr" \
2007c478bdstevel@tonic-gate			  : /* no outputs */ \
2017c478bdstevel@tonic-gate			  : "c" (msr), "a" (val1), "d" (val2))
2027c478bdstevel@tonic-gate
2037c478bdstevel@tonic-gate
2047c478bdstevel@tonic-gate#define read_cr0()	({ \
2057c478bdstevel@tonic-gate	unsigned int __dummy; \
2067c478bdstevel@tonic-gate	__asm__( \
2077c478bdstevel@tonic-gate		"movl %%cr0, %0\n\t" \
2087c478bdstevel@tonic-gate		:"=r" (__dummy)); \
2097c478bdstevel@tonic-gate	__dummy; \
2107c478bdstevel@tonic-gate})
2117c478bdstevel@tonic-gate#define write_cr0(x) \
2127c478bdstevel@tonic-gate	__asm__("movl %0,%%cr0": :"r" (x));
2137c478bdstevel@tonic-gate
2147c478bdstevel@tonic-gate#define read_cr3()	({ \
2157c478bdstevel@tonic-gate	unsigned int __dummy; \
2167c478bdstevel@tonic-gate	__asm__( \
2177c478bdstevel@tonic-gate		"movl %%cr3, %0\n\t" \
2187c478bdstevel@tonic-gate		:"=r" (__dummy)); \
2197c478bdstevel@tonic-gate	__dummy; \
2207c478bdstevel@tonic-gate})
2217c478bdstevel@tonic-gate#define write_cr3x(x) \
2227c478bdstevel@tonic-gate	__asm__("movl %0,%%cr3": :"r" (x));
2237c478bdstevel@tonic-gate
2247c478bdstevel@tonic-gate
2257c478bdstevel@tonic-gate#define read_cr4()	({ \
2267c478bdstevel@tonic-gate	unsigned int __dummy; \
2277c478bdstevel@tonic-gate	__asm__( \
2287c478bdstevel@tonic-gate		"movl %%cr4, %0\n\t" \
2297c478bdstevel@tonic-gate		:"=r" (__dummy)); \
2307c478bdstevel@tonic-gate	__dummy; \
2317c478bdstevel@tonic-gate})
2327c478bdstevel@tonic-gate#define write_cr4x(x) \
2337c478bdstevel@tonic-gate	__asm__("movl %0,%%cr4": :"r" (x));
2347c478bdstevel@tonic-gate
2357c478bdstevel@tonic-gate
2367c478bdstevel@tonic-gateextern struct cpuinfo_x86 cpu_info;
2377c478bdstevel@tonic-gate#ifdef CONFIG_X86_64
2387c478bdstevel@tonic-gateextern void cpu_setup(void);
2397c478bdstevel@tonic-gate#else
2407c478bdstevel@tonic-gate#define cpu_setup() do {} while(0)
2417c478bdstevel@tonic-gate#endif
2427c478bdstevel@tonic-gate
2437c478bdstevel@tonic-gate#endif /* I386_BITS_CPU_H */
244