xref: /illumos-gate/usr/src/data/perfmon/BDW-DE/broadwellde_core_v7.json (revision 7e3dbbac)

[
  {
    "EventCode": "0x00",
    "UMask": "0x01",
    "EventName": "INST_RETIRED.ANY",
    "BriefDescription": "Instructions retired from execution.",
    "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
    "Counter": "Fixed counter 0",
    "CounterHTOff": "Fixed counter 0",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x00",
    "UMask": "0x02",
    "EventName": "CPU_CLK_UNHALTED.THREAD",
    "BriefDescription": "Core cycles when the thread is not in halt state",
    "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
    "Counter": "Fixed counter 1",
    "CounterHTOff": "Fixed counter 1",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x00",
    "UMask": "0x02",
    "EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
    "Counter": "Fixed counter 1",
    "CounterHTOff": "Fixed counter 1",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x00",
    "UMask": "0x03",
    "EventName": "CPU_CLK_UNHALTED.REF_TSC",
    "BriefDescription": "Reference cycles when the core is not in halt state.",
    "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
    "Counter": "Fixed counter 2",
    "CounterHTOff": "Fixed counter 2",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x03",
    "UMask": "0x02",
    "EventName": "LD_BLOCKS.STORE_FORWARD",
    "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",
    "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x03",
    "UMask": "0x08",
    "EventName": "LD_BLOCKS.NO_SR",
    "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
    "PublicDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x05",
    "UMask": "0x01",
    "EventName": "MISALIGN_MEM_REF.LOADS",
    "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
    "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x05",
    "UMask": "0x02",
    "EventName": "MISALIGN_MEM_REF.STORES",
    "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
    "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x07",
    "UMask": "0x01",
    "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
    "BriefDescription": "False dependencies in MOB due to partial compare",
    "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x08",
    "UMask": "0x01",
    "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
    "BriefDescription": "Load misses in all DTLB levels that cause page walks",
    "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x08",
    "UMask": "0x02",
    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
    "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
    "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x08",
    "UMask": "0x04",
    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
    "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
    "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x08",
    "UMask": "0x08",
    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
    "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
    "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G  page size). The page walk can end with or without a fault.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x08",
    "UMask": "0x0e",
    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
    "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
    "PublicDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x08",
    "UMask": "0x10",
    "EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
    "BriefDescription": "Cycles when PMH is busy with page walks",
    "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x08",
    "UMask": "0x20",
    "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
    "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (4K).",
    "PublicDescription": "Load misses that miss the  DTLB and hit the STLB (4K).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x08",
    "UMask": "0x40",
    "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
    "BriefDescription": "Load misses that miss the  DTLB and hit the STLB (2M).",
    "PublicDescription": "Load misses that miss the  DTLB and hit the STLB (2M).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x08",
    "UMask": "0x60",
    "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
    "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
    "PublicDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x0D",
    "UMask": "0x03",
    "EventName": "INT_MISC.RECOVERY_CYCLES",
    "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
    "PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x0D",
    "UMask": "0x03",
    "EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
    "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
    "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x0D",
    "UMask": "0x08",
    "EventName": "INT_MISC.RAT_STALL_CYCLES",
    "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread",
    "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x0E",
    "UMask": "0x01",
    "EventName": "UOPS_ISSUED.ANY",
    "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
    "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x0E",
    "UMask": "0x01",
    "EventName": "UOPS_ISSUED.STALL_CYCLES",
    "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
    "PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "1",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x0E",
    "UMask": "0x10",
    "EventName": "UOPS_ISSUED.FLAGS_MERGE",
    "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",
    "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x0E",
    "UMask": "0x20",
    "EventName": "UOPS_ISSUED.SLOW_LEA",
    "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
    "PublicDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x0E",
    "UMask": "0x40",
    "EventName": "UOPS_ISSUED.SINGLE_MUL",
    "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.",
    "PublicDescription": "Number of Multiply packed/scalar single precision uops allocated.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x14",
    "UMask": "0x01",
    "EventName": "ARITH.FPU_DIV_ACTIVE",
    "BriefDescription": "Cycles when divider is busy executing divide operations",
    "PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x21",
    "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
    "BriefDescription": "Demand Data Read miss L2, no rejects",
    "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x22",
    "EventName": "L2_RQSTS.RFO_MISS",
    "BriefDescription": "RFO requests that miss L2 cache.",
    "PublicDescription": "RFO requests that miss L2 cache.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x24",
    "EventName": "L2_RQSTS.CODE_RD_MISS",
    "BriefDescription": "L2 cache misses when fetching instructions.",
    "PublicDescription": "L2 cache misses when fetching instructions.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x27",
    "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
    "BriefDescription": "Demand requests that miss L2 cache.",
    "PublicDescription": "Demand requests that miss L2 cache.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x30",
    "EventName": "L2_RQSTS.L2_PF_MISS",
    "BriefDescription": "L2 prefetch requests that miss L2 cache",
    "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x3F",
    "EventName": "L2_RQSTS.MISS",
    "BriefDescription": "All requests that miss L2 cache.",
    "PublicDescription": "All requests that miss L2 cache.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x41",
    "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
    "BriefDescription": "Demand Data Read requests that hit L2 cache",
    "PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x42",
    "EventName": "L2_RQSTS.RFO_HIT",
    "BriefDescription": "RFO requests that hit L2 cache.",
    "PublicDescription": "RFO requests that hit L2 cache.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x44",
    "EventName": "L2_RQSTS.CODE_RD_HIT",
    "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
    "PublicDescription": "L2 cache hits when fetching instructions, code reads.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x50",
    "EventName": "L2_RQSTS.L2_PF_HIT",
    "BriefDescription": "L2 prefetch requests that hit L2 cache",
    "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0xE1",
    "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
    "BriefDescription": "Demand Data Read requests",
    "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0xE2",
    "EventName": "L2_RQSTS.ALL_RFO",
    "BriefDescription": "RFO requests to L2 cache",
    "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0xE4",
    "EventName": "L2_RQSTS.ALL_CODE_RD",
    "BriefDescription": "L2 code requests",
    "PublicDescription": "This event counts the total number of L2 code requests.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0xe7",
    "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
    "BriefDescription": "Demand requests to L2 cache.",
    "PublicDescription": "Demand requests to L2 cache.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0xF8",
    "EventName": "L2_RQSTS.ALL_PF",
    "BriefDescription": "Requests from L2 hardware prefetchers",
    "PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0xFF",
    "EventName": "L2_RQSTS.REFERENCES",
    "BriefDescription": "All L2 requests.",
    "PublicDescription": "All L2 requests.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x27",
    "UMask": "0x50",
    "EventName": "L2_DEMAND_RQSTS.WB_HIT",
    "BriefDescription": "Not rejected writebacks that hit L2 cache",
    "PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x2E",
    "UMask": "0x41",
    "EventName": "LONGEST_LAT_CACHE.MISS",
    "BriefDescription": "Core-originated cacheable demand requests missed L3",
    "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x2E",
    "UMask": "0x4F",
    "EventName": "LONGEST_LAT_CACHE.REFERENCE",
    "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
    "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x3C",
    "UMask": "0x00",
    "EventName": "CPU_CLK_UNHALTED.THREAD_P",
    "BriefDescription": "Thread cycles when thread is not in halt state",
    "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x3C",
    "UMask": "0x00",
    "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
    "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
    "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x3C",
    "UMask": "0x01",
    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
    "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
    "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x3C",
    "UMask": "0x01",
    "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
    "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
    "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x3C",
    "UMask": "0x01",
    "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
    "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
    "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x3C",
    "UMask": "0x01",
    "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
    "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
    "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x3c",
    "UMask": "0x02",
    "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
    "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
    "PublicDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x3C",
    "UMask": "0x02",
    "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
    "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
    "PublicDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x48",
    "UMask": "0x01",
    "EventName": "L1D_PEND_MISS.PENDING",
    "BriefDescription": "L1D miss oustandings duration in cycles",
    "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
    "Counter": "2",
    "CounterHTOff": "2",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x48",
    "UMask": "0x01",
    "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
    "BriefDescription": "Cycles with L1D load Misses outstanding.",
    "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.",
    "Counter": "2",
    "CounterHTOff": "2",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x48",
    "UMask": "0x01",
    "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
    "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
    "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
    "Counter": "2",
    "CounterHTOff": "2",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x48",
    "UMask": "0x02",
    "EventName": "L1D_PEND_MISS.FB_FULL",
    "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
    "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x01",
    "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
    "BriefDescription": "Store misses in all DTLB levels that cause page walks",
    "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x02",
    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
    "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
    "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x04",
    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
    "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
    "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x08",
    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
    "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
    "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G  page size). The page walk can end with or without a fault.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x0e",
    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
    "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
    "PublicDescription": "Store misses in all DTLB levels that cause completed page walks.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x10",
    "EventName": "DTLB_STORE_MISSES.WALK_DURATION",
    "BriefDescription": "Cycles when PMH is busy with page walks",
    "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x20",
    "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
    "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (4K).",
    "PublicDescription": "Store misses that miss the  DTLB and hit the STLB (4K).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x40",
    "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
    "BriefDescription": "Store misses that miss the  DTLB and hit the STLB (2M).",
    "PublicDescription": "Store misses that miss the  DTLB and hit the STLB (2M).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x60",
    "EventName": "DTLB_STORE_MISSES.STLB_HIT",
    "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
    "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x4c",
    "UMask": "0x01",
    "EventName": "LOAD_HIT_PRE.SW_PF",
    "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
    "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x4C",
    "UMask": "0x02",
    "EventName": "LOAD_HIT_PRE.HW_PF",
    "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
    "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x4F",
    "UMask": "0x10",
    "EventName": "EPT.WALK_CYCLES",
    "BriefDescription": "Cycle count for an Extended Page table walk.",
    "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x51",
    "UMask": "0x01",
    "EventName": "L1D.REPLACEMENT",
    "BriefDescription": "L1D data line replacements",
    "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x54",
    "UMask": "0x01",
    "EventName": "TX_MEM.ABORT_CONFLICT",
    "BriefDescription": "Number of times a TSX line had a cache conflict",
    "PublicDescription": "Number of times a TSX line had a cache conflict.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x54",
    "UMask": "0x02",
    "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
    "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
    "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x54",
    "UMask": "0x04",
    "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
    "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
    "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x54",
    "UMask": "0x08",
    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
    "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
    "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x54",
    "UMask": "0x10",
    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
    "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
    "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x54",
    "UMask": "0x20",
    "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
    "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
    "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x54",
    "UMask": "0x40",
    "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
    "BriefDescription": "Number of times we could not allocate Lock Buffer",
    "PublicDescription": "Number of times we could not allocate Lock Buffer.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x58",
    "UMask": "0x01",
    "EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
    "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
    "PublicDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x58",
    "UMask": "0x02",
    "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
    "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
    "PublicDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x58",
    "UMask": "0x04",
    "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
    "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
    "PublicDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x58",
    "UMask": "0x08",
    "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
    "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
    "PublicDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x5C",
    "UMask": "0x01",
    "EventName": "CPL_CYCLES.RING0",
    "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
    "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x5C",
    "UMask": "0x01",
    "EventName": "CPL_CYCLES.RING0_TRANS",
    "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
    "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "1",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x5C",
    "UMask": "0x02",
    "EventName": "CPL_CYCLES.RING123",
    "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
    "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x5d",
    "UMask": "0x01",
    "EventName": "TX_EXEC.MISC1",
    "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
    "PublicDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x5d",
    "UMask": "0x02",
    "EventName": "TX_EXEC.MISC2",
    "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
    "PublicDescription": "Unfriendly TSX abort triggered by  a vzeroupper instruction.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x5d",
    "UMask": "0x04",
    "EventName": "TX_EXEC.MISC3",
    "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
    "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x5d",
    "UMask": "0x08",
    "EventName": "TX_EXEC.MISC4",
    "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
    "PublicDescription": "RTM region detected inside HLE.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x5d",
    "UMask": "0x10",
    "EventName": "TX_EXEC.MISC5",
    "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
    "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x5E",
    "UMask": "0x01",
    "EventName": "RS_EVENTS.EMPTY_CYCLES",
    "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
    "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x5E",
    "UMask": "0x01",
    "EventName": "RS_EVENTS.EMPTY_END",
    "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
    "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "1",
    "AnyThread": "0",
    "EdgeDetect": "1",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x60",
    "UMask": "0x01",
    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
    "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
    "PublicDescription": "This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is counted from the promotion point.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM76",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x60",
    "UMask": "0x01",
    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
    "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
    "PublicDescription": "This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM76",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x60",
    "UMask": "0x01",
    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
    "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
    "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "6",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM76",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x60",
    "UMask": "0x02",
    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
    "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
    "PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM76",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x60",
    "UMask": "0x04",
    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
    "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
    "PublicDescription": "This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM76",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x60",
    "UMask": "0x04",
    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
    "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
    "PublicDescription": "This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM76",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x60",
    "UMask": "0x08",
    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
    "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
    "PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM76",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x60",
    "UMask": "0x08",
    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
    "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
    "PublicDescription": "This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM76",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x63",
    "UMask": "0x01",
    "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
    "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
    "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x63",
    "UMask": "0x02",
    "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
    "BriefDescription": "Cycles when L1D is locked",
    "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x02",
    "EventName": "IDQ.EMPTY",
    "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
    "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end.  It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x04",
    "EventName": "IDQ.MITE_UOPS",
    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
    "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x04",
    "EventName": "IDQ.MITE_CYCLES",
    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
    "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x08",
    "EventName": "IDQ.DSB_UOPS",
    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
    "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x08",
    "EventName": "IDQ.DSB_CYCLES",
    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
    "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x10",
    "EventName": "IDQ.MS_DSB_UOPS",
    "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
    "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x10",
    "EventName": "IDQ.MS_DSB_CYCLES",
    "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
    "PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x10",
    "EventName": "IDQ.MS_DSB_OCCUR",
    "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
    "PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "1",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x18",
    "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
    "PublicDescription": "This event counts the number of cycles 4  uops were  delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "4",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x18",
    "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
    "PublicDescription": "This event counts the number of cycles  uops were  delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x20",
    "EventName": "IDQ.MS_MITE_UOPS",
    "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
    "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x24",
    "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
    "BriefDescription": "Cycles MITE is delivering 4 Uops",
    "PublicDescription": "This event counts the number of cycles 4  uops were  delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "4",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x24",
    "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
    "BriefDescription": "Cycles MITE is delivering any Uop",
    "PublicDescription": "This event counts the number of cycles  uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x30",
    "EventName": "IDQ.MS_UOPS",
    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
    "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x30",
    "EventName": "IDQ.MS_CYCLES",
    "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
    "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x30",
    "EventName": "IDQ.MS_SWITCHES",
    "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
    "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "1",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x3C",
    "EventName": "IDQ.MITE_ALL_UOPS",
    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
    "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x80",
    "UMask": "0x01",
    "EventName": "ICACHE.HIT",
    "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
    "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x80",
    "UMask": "0x02",
    "EventName": "ICACHE.MISSES",
    "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
    "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x80",
    "UMask": "0x04",
    "EventName": "ICACHE.IFDATA_STALL",
    "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
    "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x01",
    "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
    "BriefDescription": "Misses at all ITLB levels that cause page walks",
    "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x02",
    "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
    "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
    "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x04",
    "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
    "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
    "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x08",
    "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
    "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
    "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G  page size). The page walk can end with or without a fault.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x0e",
    "EventName": "ITLB_MISSES.WALK_COMPLETED",
    "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
    "PublicDescription": "Misses in all ITLB levels that cause completed page walks.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x10",
    "EventName": "ITLB_MISSES.WALK_DURATION",
    "BriefDescription": "Cycles when PMH is busy with page walks",
    "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x20",
    "EventName": "ITLB_MISSES.STLB_HIT_4K",
    "BriefDescription": "Core misses that miss the  DTLB and hit the STLB (4K).",
    "PublicDescription": "Core misses that miss the  DTLB and hit the STLB (4K).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x40",
    "EventName": "ITLB_MISSES.STLB_HIT_2M",
    "BriefDescription": "Code misses that miss the  DTLB and hit the STLB (2M).",
    "PublicDescription": "Code misses that miss the  DTLB and hit the STLB (2M).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x60",
    "EventName": "ITLB_MISSES.STLB_HIT",
    "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
    "PublicDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x87",
    "UMask": "0x01",
    "EventName": "ILD_STALL.LCP",
    "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
    "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0x41",
    "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
    "BriefDescription": "Not taken macro-conditional branches",
    "PublicDescription": "This event counts not taken macro-conditional branch instructions.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0x81",
    "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
    "BriefDescription": "Taken speculative and retired macro-conditional branches",
    "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0x82",
    "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
    "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",
    "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0x84",
    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
    "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",
    "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0x88",
    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
    "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",
    "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0x90",
    "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
    "BriefDescription": "Taken speculative and retired direct near calls",
    "PublicDescription": "This event counts taken speculative and retired direct near calls.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0xA0",
    "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
    "BriefDescription": "Taken speculative and retired indirect calls",
    "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0xC1",
    "EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
    "BriefDescription": "Speculative and retired macro-conditional branches",
    "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0xC2",
    "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
    "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",
    "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0xC4",
    "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
    "BriefDescription": "Speculative and retired indirect branches excluding calls and returns",
    "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0xC8",
    "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
    "BriefDescription": "Speculative and retired indirect return branches.",
    "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0xD0",
    "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
    "BriefDescription": "Speculative and retired direct near calls",
    "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x88",
    "UMask": "0xFF",
    "EventName": "BR_INST_EXEC.ALL_BRANCHES",
    "BriefDescription": "Speculative and retired  branches",
    "PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x89",
    "UMask": "0x41",
    "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
    "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",
    "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x89",
    "UMask": "0x81",
    "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
    "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",
    "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x89",
    "UMask": "0x84",
    "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
    "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",
    "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x89",
    "UMask": "0x88",
    "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
    "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",
    "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x89",
    "UMask": "0xA0",
    "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
    "BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
    "PublicDescription": "Taken speculative and retired mispredicted indirect calls.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x89",
    "UMask": "0xC1",
    "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
    "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
    "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x89",
    "UMask": "0xC4",
    "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
    "BriefDescription": "Mispredicted indirect branches excluding calls and returns",
    "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x89",
    "UMask": "0xFF",
    "EventName": "BR_MISP_EXEC.ALL_BRANCHES",
    "BriefDescription": "Speculative and retired mispredicted macro conditional branches",
    "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x9C",
    "UMask": "0x01",
    "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
    "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
    "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4  x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x9C",
    "UMask": "0x01",
    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
    "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
    "PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "4",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x9C",
    "UMask": "0x01",
    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
    "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
    "PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is  delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "3",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x9C",
    "UMask": "0x01",
    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
    "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
    "PublicDescription": "Cycles with less than 2 uops delivered by the front end.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "2",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x9C",
    "UMask": "0x01",
    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
    "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
    "PublicDescription": "Cycles with less than 3 uops delivered by the front end.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x9C",
    "UMask": "0x01",
    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
    "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
    "PublicDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "1",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA0",
    "UMask": "0x03",
    "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",
    "BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",
    "PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file.  The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*.  See the Broadwell Optimization Guide for more information.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x01",
    "EventName": "UOPS_DISPATCHED_PORT.PORT_0",
    "BriefDescription": "Cycles per thread when uops are executed in port 0",
    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x01",
    "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",
    "BriefDescription": "Cycles per core when uops are exectuted in port 0.",
    "PublicDescription": "Cycles per core when uops are exectuted in port 0.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x01",
    "EventName": "UOPS_EXECUTED_PORT.PORT_0",
    "BriefDescription": "Cycles per thread when uops are executed in port 0",
    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x02",
    "EventName": "UOPS_DISPATCHED_PORT.PORT_1",
    "BriefDescription": "Cycles per thread when uops are executed in port 1",
    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x02",
    "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
    "BriefDescription": "Cycles per core when uops are exectuted in port 1.",
    "PublicDescription": "Cycles per core when uops are exectuted in port 1.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x02",
    "EventName": "UOPS_EXECUTED_PORT.PORT_1",
    "BriefDescription": "Cycles per thread when uops are executed in port 1",
    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x04",
    "EventName": "UOPS_DISPATCHED_PORT.PORT_2",
    "BriefDescription": "Cycles per thread when uops are executed in port 2",
    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x04",
    "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",
    "BriefDescription": "Cycles per core when uops are dispatched to port 2.",
    "PublicDescription": "Cycles per core when uops are dispatched to port 2.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x04",
    "EventName": "UOPS_EXECUTED_PORT.PORT_2",
    "BriefDescription": "Cycles per thread when uops are executed in port 2",
    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x08",
    "EventName": "UOPS_DISPATCHED_PORT.PORT_3",
    "BriefDescription": "Cycles per thread when uops are executed in port 3",
    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x08",
    "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",
    "BriefDescription": "Cycles per core when uops are dispatched to port 3.",
    "PublicDescription": "Cycles per core when uops are dispatched to port 3.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x08",
    "EventName": "UOPS_EXECUTED_PORT.PORT_3",
    "BriefDescription": "Cycles per thread when uops are executed in port 3",
    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x10",
    "EventName": "UOPS_DISPATCHED_PORT.PORT_4",
    "BriefDescription": "Cycles per thread when uops are executed in port 4",
    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x10",
    "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
    "BriefDescription": "Cycles per core when uops are exectuted in port 4.",
    "PublicDescription": "Cycles per core when uops are exectuted in port 4.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x10",
    "EventName": "UOPS_EXECUTED_PORT.PORT_4",
    "BriefDescription": "Cycles per thread when uops are executed in port 4",
    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x20",
    "EventName": "UOPS_DISPATCHED_PORT.PORT_5",
    "BriefDescription": "Cycles per thread when uops are executed in port 5",
    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x20",
    "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
    "BriefDescription": "Cycles per core when uops are exectuted in port 5.",
    "PublicDescription": "Cycles per core when uops are exectuted in port 5.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x20",
    "EventName": "UOPS_EXECUTED_PORT.PORT_5",
    "BriefDescription": "Cycles per thread when uops are executed in port 5",
    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x40",
    "EventName": "UOPS_DISPATCHED_PORT.PORT_6",
    "BriefDescription": "Cycles per thread when uops are executed in port 6",
    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x40",
    "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
    "BriefDescription": "Cycles per core when uops are exectuted in port 6.",
    "PublicDescription": "Cycles per core when uops are exectuted in port 6.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x40",
    "EventName": "UOPS_EXECUTED_PORT.PORT_6",
    "BriefDescription": "Cycles per thread when uops are executed in port 6",
    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x80",
    "EventName": "UOPS_DISPATCHED_PORT.PORT_7",
    "BriefDescription": "Cycles per thread when uops are executed in port 7",
    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x80",
    "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",
    "BriefDescription": "Cycles per core when uops are dispatched to port 7.",
    "PublicDescription": "Cycles per core when uops are dispatched to port 7.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA1",
    "UMask": "0x80",
    "EventName": "UOPS_EXECUTED_PORT.PORT_7",
    "BriefDescription": "Cycles per thread when uops are executed in port 7",
    "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA2",
    "UMask": "0x01",
    "EventName": "RESOURCE_STALLS.ANY",
    "BriefDescription": "Resource-related stall cycles",
    "PublicDescription": "This event counts resource-related stall cycles. Reasons for stalls can be as follows:\n - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)\n - *any* u-arch structure got empty (like INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA2",
    "UMask": "0x04",
    "EventName": "RESOURCE_STALLS.RS",
    "BriefDescription": "Cycles stalled due to no eligible RS entry available.",
    "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA2",
    "UMask": "0x08",
    "EventName": "RESOURCE_STALLS.SB",
    "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
    "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA2",
    "UMask": "0x10",
    "EventName": "RESOURCE_STALLS.ROB",
    "BriefDescription": "Cycles stalled due to re-order buffer full.",
    "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x01",
    "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
    "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
    "PublicDescription": "Counts number of cycles the CPU has at least one pending  demand* load request missing the L2 cache.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x01",
    "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
    "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
    "PublicDescription": "Cycles while L2 cache miss demand load is outstanding.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x02",
    "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
    "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
    "PublicDescription": "Counts number of cycles the CPU has at least one pending  demand load request (that is cycles with non-completed load waiting for its data from memory subsystem).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "2",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x02",
    "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
    "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
    "PublicDescription": "Cycles while memory subsystem has an outstanding load.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "2",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x04",
    "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
    "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
    "PublicDescription": "Counts number of cycles nothing is executed on any execution port.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "4",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x04",
    "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
    "BriefDescription": "Total execution stalls.",
    "PublicDescription": "Total execution stalls.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "4",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x05",
    "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
    "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
    "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "5",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x05",
    "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
    "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
    "PublicDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "5",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x06",
    "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
    "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
    "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "6",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x06",
    "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
    "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
    "PublicDescription": "Execution stalls while memory subsystem has an outstanding load.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "6",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x08",
    "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
    "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
    "PublicDescription": "Counts number of cycles the CPU has at least one pending  demand load request missing the L1 data cache.",
    "Counter": "2",
    "CounterHTOff": "2",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "8",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x08",
    "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
    "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
    "PublicDescription": "Cycles while L1 cache miss demand load is outstanding.",
    "Counter": "2",
    "CounterHTOff": "2",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "8",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x0C",
    "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
    "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
    "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.",
    "Counter": "2",
    "CounterHTOff": "2",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "12",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x0C",
    "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
    "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
    "PublicDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
    "Counter": "2",
    "CounterHTOff": "2",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "12",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA8",
    "UMask": "0x01",
    "EventName": "LSD.UOPS",
    "BriefDescription": "Number of Uops delivered by the LSD.",
    "PublicDescription": "Number of Uops delivered by the LSD.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA8",
    "UMask": "0x01",
    "EventName": "LSD.CYCLES_4_UOPS",
    "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
    "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "4",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA8",
    "UMask": "0x01",
    "EventName": "LSD.CYCLES_ACTIVE",
    "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
    "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xAB",
    "UMask": "0x02",
    "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
    "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
    "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xAE",
    "UMask": "0x01",
    "EventName": "ITLB.ITLB_FLUSH",
    "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
    "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB0",
    "UMask": "0x01",
    "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
    "BriefDescription": "Demand Data Read requests sent to uncore",
    "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB0",
    "UMask": "0x02",
    "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
    "BriefDescription": "Cacheable and noncachaeble code read requests",
    "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB0",
    "UMask": "0x04",
    "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
    "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
    "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB0",
    "UMask": "0x08",
    "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
    "BriefDescription": "Demand and prefetch data reads",
    "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x01",
    "EventName": "UOPS_EXECUTED.THREAD",
    "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
    "PublicDescription": "Number of uops to be executed per-thread each cycle.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x01",
    "EventName": "UOPS_EXECUTED.STALL_CYCLES",
    "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
    "PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "1",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x01",
    "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
    "BriefDescription": "Cycles where at least 1 uop was executed per-thread.",
    "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x01",
    "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
    "BriefDescription": "Cycles where at least 2 uops were executed per-thread.",
    "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "2",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x01",
    "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
    "BriefDescription": "Cycles where at least 3 uops were executed per-thread.",
    "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "3",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x01",
    "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
    "BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
    "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "4",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x02",
    "EventName": "UOPS_EXECUTED.CORE",
    "BriefDescription": "Number of uops executed on the core.",
    "PublicDescription": "Number of uops executed from any thread.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xb1",
    "UMask": "0x02",
    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
    "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xb1",
    "UMask": "0x02",
    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
    "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "2",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xb1",
    "UMask": "0x02",
    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
    "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "3",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xb1",
    "UMask": "0x02",
    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
    "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "4",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xb1",
    "UMask": "0x02",
    "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
    "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
    "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "1",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xb2",
    "UMask": "0x01",
    "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
    "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
    "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB7, 0xBB",
    "UMask": "0x01",
    "EventName": "OFFCORE_RESPONSE",
    "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
    "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xBC",
    "UMask": "0x11",
    "EventName": "PAGE_WALKER_LOADS.DTLB_L1",
    "BriefDescription": "Number of DTLB page walker hits in the L1+FB.",
    "PublicDescription": "Number of DTLB page walker hits in the L1+FB.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69, BDM98",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xBC",
    "UMask": "0x12",
    "EventName": "PAGE_WALKER_LOADS.DTLB_L2",
    "BriefDescription": "Number of DTLB page walker hits in the L2.",
    "PublicDescription": "Number of DTLB page walker hits in the L2.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69, BDM98",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xBC",
    "UMask": "0x14",
    "EventName": "PAGE_WALKER_LOADS.DTLB_L3",
    "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
    "PublicDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69, BDM98",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xBC",
    "UMask": "0x18",
    "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
    "BriefDescription": "Number of DTLB page walker hits in Memory.",
    "PublicDescription": "Number of DTLB page walker hits in Memory.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69, BDM98",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xBC",
    "UMask": "0x21",
    "EventName": "PAGE_WALKER_LOADS.ITLB_L1",
    "BriefDescription": "Number of ITLB page walker hits in the L1+FB.",
    "PublicDescription": "Number of ITLB page walker hits in the L1+FB.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69, BDM98",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xBC",
    "UMask": "0x22",
    "EventName": "PAGE_WALKER_LOADS.ITLB_L2",
    "BriefDescription": "Number of ITLB page walker hits in the L2.",
    "PublicDescription": "Number of ITLB page walker hits in the L2.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69, BDM98",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xBC",
    "UMask": "0x24",
    "EventName": "PAGE_WALKER_LOADS.ITLB_L3",
    "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
    "PublicDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM69, BDM98",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xBD",
    "UMask": "0x01",
    "EventName": "TLB_FLUSH.DTLB_THREAD",
    "BriefDescription": "DTLB flush attempts of the thread-specific entries",
    "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xBD",
    "UMask": "0x20",
    "EventName": "TLB_FLUSH.STLB_ANY",
    "BriefDescription": "STLB flush attempts",
    "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC0",
    "UMask": "0x00",
    "EventName": "INST_RETIRED.ANY_P",
    "BriefDescription": "Number of instructions retired. General Counter   - architectural event",
    "PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM61",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC0",
    "UMask": "0x01",
    "EventName": "INST_RETIRED.PREC_DIST",
    "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.",
    "Counter": "1",
    "CounterHTOff": "1",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM11, BDM55",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC0",
    "UMask": "0x02",
    "EventName": "INST_RETIRED.X87",
    "BriefDescription": "FP operations  retired. X87 FP operations that have no exceptions:",
    "PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC1",
    "UMask": "0x08",
    "EventName": "OTHER_ASSISTS.AVX_TO_SSE",
    "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
    "PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM30",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC1",
    "UMask": "0x10",
    "EventName": "OTHER_ASSISTS.SSE_TO_AVX",
    "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
    "PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM30",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC1",
    "UMask": "0x40",
    "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
    "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
    "PublicDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC2",
    "UMask": "0x01",
    "EventName": "UOPS_RETIRED.ALL",
    "BriefDescription": "Actually retired uops. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC2",
    "UMask": "0x01",
    "EventName": "UOPS_RETIRED.STALL_CYCLES",
    "BriefDescription": "Cycles without actually retired uops.",
    "PublicDescription": "This event counts cycles without actually retired uops.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "1",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC2",
    "UMask": "0x01",
    "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
    "BriefDescription": "Cycles with less than 10 actually retired uops.",
    "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "10",
    "Invert": "1",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC2",
    "UMask": "0x02",
    "EventName": "UOPS_RETIRED.RETIRE_SLOTS",
    "BriefDescription": "Retirement slots used. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of retirement slots used.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC3",
    "UMask": "0x01",
    "EventName": "MACHINE_CLEARS.CYCLES",
    "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",
    "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC3",
    "UMask": "0x01",
    "EventName": "MACHINE_CLEARS.COUNT",
    "BriefDescription": "Number of machine clears (nukes) of any type.",
    "PublicDescription": "Number of machine clears (nukes) of any type.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "1",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC3",
    "UMask": "0x02",
    "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
    "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
    "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC3",
    "UMask": "0x04",
    "EventName": "MACHINE_CLEARS.SMC",
    "BriefDescription": "Self-modifying code (SMC) detected.",
    "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC3",
    "UMask": "0x20",
    "EventName": "MACHINE_CLEARS.MASKMOV",
    "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
    "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC4",
    "UMask": "0x00",
    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
    "BriefDescription": "All (macro) branch instructions retired.",
    "PublicDescription": "This event counts all (macro) branch instructions retired.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "400009",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC4",
    "UMask": "0x01",
    "EventName": "BR_INST_RETIRED.CONDITIONAL",
    "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "400009",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC4",
    "UMask": "0x02",
    "EventName": "BR_INST_RETIRED.NEAR_CALL",
    "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC4",
    "UMask": "0x02",
    "EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
    "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect macro near call instructions retired (captured in ring 3).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC4",
    "UMask": "0x04",
    "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
    "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "400009",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDW98",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC4",
    "UMask": "0x08",
    "EventName": "BR_INST_RETIRED.NEAR_RETURN",
    "BriefDescription": "Return instructions retired. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts return instructions retired.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC4",
    "UMask": "0x10",
    "EventName": "BR_INST_RETIRED.NOT_TAKEN",
    "BriefDescription": "Not taken branch instructions retired.",
    "PublicDescription": "This event counts not taken branch instructions retired.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "400009",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC4",
    "UMask": "0x20",
    "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
    "BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "400009",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC4",
    "UMask": "0x40",
    "EventName": "BR_INST_RETIRED.FAR_BRANCH",
    "BriefDescription": "Far branch instructions retired.",
    "PublicDescription": "This event counts far branch instructions retired.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDW98",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC5",
    "UMask": "0x00",
    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
    "BriefDescription": "All mispredicted macro branch instructions retired.",
    "PublicDescription": "This event counts all mispredicted macro branch instructions retired.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "400009",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC5",
    "UMask": "0x01",
    "EventName": "BR_MISP_RETIRED.CONDITIONAL",
    "BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "400009",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC5",
    "UMask": "0x04",
    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
    "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "400009",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC5",
    "UMask": "0x08",
    "EventName": "BR_MISP_RETIRED.RET",
    "BriefDescription": "This event counts the number of mispredicted ret instructions retired.(Precise Event)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts mispredicted return instructions retired.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC5",
    "UMask": "0x20",
    "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
    "BriefDescription": "number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).",
    "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "400009",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC7",
    "UMask": "0x01",
    "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
    "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
    "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC7",
    "UMask": "0x02",
    "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
    "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
    "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC7",
    "UMask": "0x03",
    "EventName": "FP_ARITH_INST_RETIRED.SCALAR",
    "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
    "PublicDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC7",
    "UMask": "0x04",
    "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
    "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
    "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired.  Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC7",
    "UMask": "0x08",
    "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
    "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
    "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC7",
    "UMask": "0x10",
    "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
    "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
    "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired.  Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC7",
    "UMask": "0x15",
    "EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
    "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ?.",
    "PublicDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.  ?.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000006",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc7",
    "UMask": "0x20",
    "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
    "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
    "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired.  Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC7",
    "UMask": "0x2A",
    "EventName": "FP_ARITH_INST_RETIRED.SINGLE",
    "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
    "PublicDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000005",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC7",
    "UMask": "0x3C",
    "EventName": "FP_ARITH_INST_RETIRED.PACKED",
    "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
    "PublicDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000004",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc8",
    "UMask": "0x01",
    "EventName": "HLE_RETIRED.START",
    "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
    "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc8",
    "UMask": "0x02",
    "EventName": "HLE_RETIRED.COMMIT",
    "BriefDescription": "Number of times HLE commit succeeded",
    "PublicDescription": "Number of times HLE commit succeeded.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc8",
    "UMask": "0x04",
    "EventName": "HLE_RETIRED.ABORTED",
    "BriefDescription": "Number of times HLE abort was triggered (PEBS)",
    "PublicDescription": "Number of times HLE abort was triggered (PEBS).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc8",
    "UMask": "0x08",
    "EventName": "HLE_RETIRED.ABORTED_MISC1",
    "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
    "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc8",
    "UMask": "0x10",
    "EventName": "HLE_RETIRED.ABORTED_MISC2",
    "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
    "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc8",
    "UMask": "0x20",
    "EventName": "HLE_RETIRED.ABORTED_MISC3",
    "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
    "PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc8",
    "UMask": "0x40",
    "EventName": "HLE_RETIRED.ABORTED_MISC4",
    "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
    "PublicDescription": "Number of times HLE caused a fault.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc8",
    "UMask": "0x80",
    "EventName": "HLE_RETIRED.ABORTED_MISC5",
    "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
    "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc9",
    "UMask": "0x01",
    "EventName": "RTM_RETIRED.START",
    "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
    "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc9",
    "UMask": "0x02",
    "EventName": "RTM_RETIRED.COMMIT",
    "BriefDescription": "Number of times RTM commit succeeded",
    "PublicDescription": "Number of times RTM commit succeeded.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc9",
    "UMask": "0x04",
    "EventName": "RTM_RETIRED.ABORTED",
    "BriefDescription": "Number of times RTM abort was triggered (PEBS)",
    "PublicDescription": "Number of times RTM abort was triggered (PEBS).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc9",
    "UMask": "0x08",
    "EventName": "RTM_RETIRED.ABORTED_MISC1",
    "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
    "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc9",
    "UMask": "0x10",
    "EventName": "RTM_RETIRED.ABORTED_MISC2",
    "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
    "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc9",
    "UMask": "0x20",
    "EventName": "RTM_RETIRED.ABORTED_MISC3",
    "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
    "PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc9",
    "UMask": "0x40",
    "EventName": "RTM_RETIRED.ABORTED_MISC4",
    "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
    "PublicDescription": "Number of times a RTM caused a fault.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc9",
    "UMask": "0x80",
    "EventName": "RTM_RETIRED.ABORTED_MISC5",
    "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
    "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCA",
    "UMask": "0x02",
    "EventName": "FP_ASSIST.X87_OUTPUT",
    "BriefDescription": "Number of X87 assists due to output value.",
    "PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCA",
    "UMask": "0x04",
    "EventName": "FP_ASSIST.X87_INPUT",
    "BriefDescription": "Number of X87 assists due to input value.",
    "PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCA",
    "UMask": "0x08",
    "EventName": "FP_ASSIST.SIMD_OUTPUT",
    "BriefDescription": "Number of SIMD FP assists due to Output values",
    "PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCA",
    "UMask": "0x10",
    "EventName": "FP_ASSIST.SIMD_INPUT",
    "BriefDescription": "Number of SIMD FP assists due to input values",
    "PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCA",
    "UMask": "0x1E",
    "EventName": "FP_ASSIST.ANY",
    "BriefDescription": "Cycles with any input/output SSE or FP assist",
    "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCC",
    "UMask": "0x20",
    "EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
    "BriefDescription": "Count cases of saving new LBR",
    "PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCD",
    "UMask": "0x01",
    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
    "BriefDescription": "Loads with latency value being above 4",
    "PublicDescription": "This event counts loads with latency value being above four.",
    "Counter": "3",
    "CounterHTOff": "3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x4",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM100, BDM35",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCD",
    "UMask": "0x01",
    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
    "BriefDescription": "Loads with latency value being above 8",
    "PublicDescription": "This event counts loads with latency value being above eight.",
    "Counter": "3",
    "CounterHTOff": "3",
    "SampleAfterValue": "50021",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x8",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM100, BDM35",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCD",
    "UMask": "0x01",
    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
    "BriefDescription": "Loads with latency value being above 16",
    "PublicDescription": "This event counts loads with latency value being above 16.",
    "Counter": "3",
    "CounterHTOff": "3",
    "SampleAfterValue": "20011",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x10",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM100, BDM35",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCD",
    "UMask": "0x01",
    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
    "BriefDescription": "Loads with latency value being above 32",
    "PublicDescription": "This event counts loads with latency value being above 32.",
    "Counter": "3",
    "CounterHTOff": "3",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x20",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM100, BDM35",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCD",
    "UMask": "0x01",
    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
    "BriefDescription": "Loads with latency value being above 64",
    "PublicDescription": "This event counts loads with latency value being above 64.",
    "Counter": "3",
    "CounterHTOff": "3",
    "SampleAfterValue": "2003",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x40",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM100, BDM35",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCD",
    "UMask": "0x01",
    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
    "BriefDescription": "Loads with latency value being above 128",
    "PublicDescription": "This event counts loads with latency value being above 128.",
    "Counter": "3",
    "CounterHTOff": "3",
    "SampleAfterValue": "1009",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x80",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM100, BDM35",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCD",
    "UMask": "0x01",
    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
    "BriefDescription": "Loads with latency value being above 256",
    "PublicDescription": "This event counts loads with latency value being above 256.",
    "Counter": "3",
    "CounterHTOff": "3",
    "SampleAfterValue": "503",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x100",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM100, BDM35",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xCD",
    "UMask": "0x01",
    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
    "BriefDescription": "Loads with latency value being above 512",
    "PublicDescription": "This event counts loads with latency value being above 512.",
    "Counter": "3",
    "CounterHTOff": "3",
    "SampleAfterValue": "101",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x200",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "BDM100, BDM35",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD0",
    "UMask": "0x11",
    "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
    "BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD0",
    "UMask": "0x12",
    "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
    "BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "1",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD0",
    "UMask": "0x21",
    "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
    "BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "100007",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "BDM35",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD0",
    "UMask": "0x41",
    "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
    "BriefDescription": "Retired load uops that split across a cacheline boundary.(Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD0",
    "UMask": "0x42",
    "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
    "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "1",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD0",
    "UMask": "0x81",
    "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
    "BriefDescription": "All retired load uops. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD0",
    "UMask": "0x82",
    "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
    "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "1",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD1",
    "UMask": "0x01",
    "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
    "BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data source were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD1",
    "UMask": "0x02",
    "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
    "BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "BDM35",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD1",
    "UMask": "0x04",
    "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
    "BriefDescription": "Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "50021",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "BDM100",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD1",
    "UMask": "0x08",
    "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
    "BriefDescription": "Retired load uops misses in L1 cache as data sources. Uses PEBS.",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD1",
    "UMask": "0x10",
    "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
    "BriefDescription": "Retired load uops with L2 cache misses as data sources. Uses PEBS.",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "50021",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD1",
    "UMask": "0x20",
    "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",
    "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS).",
    "PublicDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "100007",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "BDM100, BDE70",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD1",
    "UMask": "0x40",
    "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
    "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit  even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD2",
    "UMask": "0x01",
    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS",
    "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "20011",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "BDM100",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD2",
    "UMask": "0x02",
    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",
    "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "20011",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "BDM100",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD2",
    "UMask": "0x04",
    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",
    "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "20011",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "BDM100",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD2",
    "UMask": "0x08",
    "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE",
    "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS)",
    "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "BDM100",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD3",
    "UMask": "0x01",
    "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",
    "BriefDescription": "tbd",
    "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "100007",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "BDE70, BDM100",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD3",
    "UMask": "0x04",
    "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM",
    "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)",
    "PublicDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "100007",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "BDE70",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD3",
    "UMask": "0x10",
    "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM",
    "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM (Precise Event)",
    "PublicDescription": "Retired load uop whose Data Source was: Remote cache HITM (Precise Event)",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "100007",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "BDE70",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xD3",
    "UMask": "0x20",
    "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD",
    "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache (Precise Event)",
    "PublicDescription": "Retired load uop whose Data Source was: forwarded from remote cache (Precise Event)",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3",
    "SampleAfterValue": "100007",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "BDE70",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xe6",
    "UMask": "0x1f",
    "EventName": "BACLEARS.ANY",
    "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
    "PublicDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF0",
    "UMask": "0x01",
    "EventName": "L2_TRANS.DEMAND_DATA_RD",
    "BriefDescription": "Demand Data Read requests that access L2 cache",
    "PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF0",
    "UMask": "0x02",
    "EventName": "L2_TRANS.RFO",
    "BriefDescription": "RFO requests that access L2 cache",
    "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF0",
    "UMask": "0x04",
    "EventName": "L2_TRANS.CODE_RD",
    "BriefDescription": "L2 cache accesses when fetching instructions",
    "PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF0",
    "UMask": "0x08",
    "EventName": "L2_TRANS.ALL_PF",
    "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
    "PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF0",
    "UMask": "0x10",
    "EventName": "L2_TRANS.L1D_WB",
    "BriefDescription": "L1D writebacks that access L2 cache",
    "PublicDescription": "This event counts L1D writebacks that access L2 cache.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF0",
    "UMask": "0x20",
    "EventName": "L2_TRANS.L2_FILL",
    "BriefDescription": "L2 fill requests that access L2 cache",
    "PublicDescription": "This event counts L2 fill requests that access L2 cache.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF0",
    "UMask": "0x40",
    "EventName": "L2_TRANS.L2_WB",
    "BriefDescription": "L2 writebacks that access L2 cache",
    "PublicDescription": "This event counts L2 writebacks that access L2 cache.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF0",
    "UMask": "0x80",
    "EventName": "L2_TRANS.ALL_REQUESTS",
    "BriefDescription": "Transactions accessing L2 pipe",
    "PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "200003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF1",
    "UMask": "0x01",
    "EventName": "L2_LINES_IN.I",
    "BriefDescription": "L2 cache lines in I state filling L2",
    "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF1",
    "UMask": "0x02",
    "EventName": "L2_LINES_IN.S",
    "BriefDescription": "L2 cache lines in S state filling L2",
    "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF1",
    "UMask": "0x04",
    "EventName": "L2_LINES_IN.E",
    "BriefDescription": "L2 cache lines in E state filling L2",
    "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF1",
    "UMask": "0x07",
    "EventName": "L2_LINES_IN.ALL",
    "BriefDescription": "L2 cache lines filling L2",
    "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF2",
    "UMask": "0x05",
    "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
    "BriefDescription": "Clean L2 cache lines evicted by demand.",
    "PublicDescription": "Clean L2 cache lines evicted by demand.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xf4",
    "UMask": "0x10",
    "EventName": "SQ_MISC.SPLIT_LOCK",
    "BriefDescription": "Split locks in SQ",
    "PublicDescription": "This event counts the number of split locks in the super queue.",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0",
    "MSRValue": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "AnyThread": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "null",
    "ELLC": "0",
    "Offcore": "0"
  }
]