1*281939dfSRobert Mustacchi[
2*281939dfSRobert Mustacchi{
3*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::FpRetSseAvxOps",
4*281939dfSRobert Mustacchi	"name": "FpRetSseAvxOps",
5*281939dfSRobert Mustacchi	"code": "0x003",
6*281939dfSRobert Mustacchi	"summary": "Retired SSE/AVX FLOPs",
7*281939dfSRobert Mustacchi	"description": "This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count above 15 events per cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It does not provide a useful count without the use of the MergeEvent.",
8*281939dfSRobert Mustacchi	"units": [ {
9*281939dfSRobert Mustacchi		"name": "MacFLOPs",
10*281939dfSRobert Mustacchi		"bit": 3,
11*281939dfSRobert Mustacchi		"rw": "Read-write",
12*281939dfSRobert Mustacchi		"description": "Multiply-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS."
13*281939dfSRobert Mustacchi	}, {
14*281939dfSRobert Mustacchi		"name": "DivFLOPs",
15*281939dfSRobert Mustacchi		"bit": 2,
16*281939dfSRobert Mustacchi		"rw": "Read-write",
17*281939dfSRobert Mustacchi		"description": "Divide/square root FLOPs."
18*281939dfSRobert Mustacchi	}, {
19*281939dfSRobert Mustacchi		"name": "MultFLOPs",
20*281939dfSRobert Mustacchi		"bit": 1,
21*281939dfSRobert Mustacchi		"rw": "Read-write",
22*281939dfSRobert Mustacchi		"description": "Multiply FLOPs."
23*281939dfSRobert Mustacchi	}, {
24*281939dfSRobert Mustacchi		"name": "AddSubFLOPs",
25*281939dfSRobert Mustacchi		"bit": 0,
26*281939dfSRobert Mustacchi		"rw": "Read-write",
27*281939dfSRobert Mustacchi		"description": "Add/subtract FLOPs."
28*281939dfSRobert Mustacchi	} ]
29*281939dfSRobert Mustacchi},
30*281939dfSRobert Mustacchi{
31*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::FpRetiredSerOps",
32*281939dfSRobert Mustacchi	"name": "FpRetiredSerOps",
33*281939dfSRobert Mustacchi	"code": "0x005",
34*281939dfSRobert Mustacchi	"summary": "Retired Serializing Ops",
35*281939dfSRobert Mustacchi	"description": "The number of serializing Ops retired.",
36*281939dfSRobert Mustacchi	"units": [ {
37*281939dfSRobert Mustacchi		"name": "SseBotRet",
38*281939dfSRobert Mustacchi		"bit": 3,
39*281939dfSRobert Mustacchi		"rw": "Read-write",
40*281939dfSRobert Mustacchi		"description": "SSE/AVX bottom-executing ops retired."
41*281939dfSRobert Mustacchi	}, {
42*281939dfSRobert Mustacchi		"name": "SseCtrlRet",
43*281939dfSRobert Mustacchi		"bit": 2,
44*281939dfSRobert Mustacchi		"rw": "Read-write",
45*281939dfSRobert Mustacchi		"description": "SSE/AVX control word mispredict traps."
46*281939dfSRobert Mustacchi	}, {
47*281939dfSRobert Mustacchi		"name": "X87BotRet",
48*281939dfSRobert Mustacchi		"bit": 1,
49*281939dfSRobert Mustacchi		"rw": "Read-write",
50*281939dfSRobert Mustacchi		"description": "x87 bottom-executing ops retired."
51*281939dfSRobert Mustacchi	}, {
52*281939dfSRobert Mustacchi		"name": "X87CtrlRet",
53*281939dfSRobert Mustacchi		"bit": 0,
54*281939dfSRobert Mustacchi		"rw": "Read-write",
55*281939dfSRobert Mustacchi		"description": "x87 control word mispredict traps due to mispredictions in RC or PC, or changes in Exception Mask bits."
56*281939dfSRobert Mustacchi	} ]
57*281939dfSRobert Mustacchi},
58*281939dfSRobert Mustacchi{
59*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::FpDispFaults",
60*281939dfSRobert Mustacchi	"name": "FpDispFaults",
61*281939dfSRobert Mustacchi	"code": "0x00E",
62*281939dfSRobert Mustacchi	"summary": "FP Dispatch Faults",
63*281939dfSRobert Mustacchi	"description": "Floating Point Dispatch Faults.",
64*281939dfSRobert Mustacchi	"units": [ {
65*281939dfSRobert Mustacchi		"name": "YmmSpillFault",
66*281939dfSRobert Mustacchi		"bit": 3,
67*281939dfSRobert Mustacchi		"rw": "Read-write",
68*281939dfSRobert Mustacchi		"description": "YMM Spill fault."
69*281939dfSRobert Mustacchi	}, {
70*281939dfSRobert Mustacchi		"name": "YmmFillFault",
71*281939dfSRobert Mustacchi		"bit": 2,
72*281939dfSRobert Mustacchi		"rw": "Read-write",
73*281939dfSRobert Mustacchi		"description": "YMM Fill fault."
74*281939dfSRobert Mustacchi	}, {
75*281939dfSRobert Mustacchi		"name": "XmmFillFault",
76*281939dfSRobert Mustacchi		"bit": 1,
77*281939dfSRobert Mustacchi		"rw": "Read-write",
78*281939dfSRobert Mustacchi		"description": "XMM Fill fault."
79*281939dfSRobert Mustacchi	}, {
80*281939dfSRobert Mustacchi		"name": "x87FillFault",
81*281939dfSRobert Mustacchi		"bit": 0,
82*281939dfSRobert Mustacchi		"rw": "Read-write",
83*281939dfSRobert Mustacchi		"description": "x87 Fill fault."
84*281939dfSRobert Mustacchi	} ]
85*281939dfSRobert Mustacchi},
86*281939dfSRobert Mustacchi{
87*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsBadStatus2",
88*281939dfSRobert Mustacchi	"name": "LsBadStatus2",
89*281939dfSRobert Mustacchi	"code": "0x024",
90*281939dfSRobert Mustacchi	"summary": "Bad Status 2",
91*281939dfSRobert Mustacchi	"units": [ {
92*281939dfSRobert Mustacchi		"name": "StliOther",
93*281939dfSRobert Mustacchi		"bit": 1,
94*281939dfSRobert Mustacchi		"rw": "Read-write",
95*281939dfSRobert Mustacchi		"description": "Store-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element stores."
96*281939dfSRobert Mustacchi	} ]
97*281939dfSRobert Mustacchi},
98*281939dfSRobert Mustacchi{
99*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsLocks",
100*281939dfSRobert Mustacchi	"name": "LsLocks",
101*281939dfSRobert Mustacchi	"code": "0x025",
102*281939dfSRobert Mustacchi	"summary": "Retired Lock Instructions",
103*281939dfSRobert Mustacchi	"units": [ {
104*281939dfSRobert Mustacchi		"name": "BusLock",
105*281939dfSRobert Mustacchi		"bit": 0,
106*281939dfSRobert Mustacchi		"rw": "Read-write",
107*281939dfSRobert Mustacchi		"description": "Read-write. Reset: 0. Comparable to legacy bus lock."
108*281939dfSRobert Mustacchi	} ]
109*281939dfSRobert Mustacchi},
110*281939dfSRobert Mustacchi{
111*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsRetClClush",
112*281939dfSRobert Mustacchi	"name": "LsRetClClush",
113*281939dfSRobert Mustacchi	"code": "0x026",
114*281939dfSRobert Mustacchi	"summary": "Retired CLFLUSH Instructions",
115*281939dfSRobert Mustacchi	"description": "The number of retired CLFLUSH instructions. This is a non-speculative event."
116*281939dfSRobert Mustacchi},
117*281939dfSRobert Mustacchi{
118*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsRetCpuid",
119*281939dfSRobert Mustacchi	"name": "LsRetCpuid",
120*281939dfSRobert Mustacchi	"code": "0x027",
121*281939dfSRobert Mustacchi	"summary": "Retired CPUID Instructions",
122*281939dfSRobert Mustacchi	"description": "The number of CPUID instructions retired."
123*281939dfSRobert Mustacchi},
124*281939dfSRobert Mustacchi{
125*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsDispatch",
126*281939dfSRobert Mustacchi	"name": "LsDispatch",
127*281939dfSRobert Mustacchi	"code": "0x029",
128*281939dfSRobert Mustacchi	"summary": "LS Dispatch",
129*281939dfSRobert Mustacchi	"description": "Counts the number of operations dispatched to the LS unit.",
130*281939dfSRobert Mustacchi	"unit_mode": "add",
131*281939dfSRobert Mustacchi	"units": [ {
132*281939dfSRobert Mustacchi		"name": "LdStDispatch",
133*281939dfSRobert Mustacchi		"bit": 2,
134*281939dfSRobert Mustacchi		"rw": "Read-write",
135*281939dfSRobert Mustacchi		"description": "Load-op-Store Dispatch. Dispatch of a single op that performs a load from and store to the same memory address."
136*281939dfSRobert Mustacchi	}, {
137*281939dfSRobert Mustacchi		"name": "StoreDispatch",
138*281939dfSRobert Mustacchi		"bit": 1,
139*281939dfSRobert Mustacchi		"rw": "Read-write",
140*281939dfSRobert Mustacchi		"description": "Dispatch of a single op that performs a memory store."
141*281939dfSRobert Mustacchi	}, {
142*281939dfSRobert Mustacchi		"name": "LdDispatch",
143*281939dfSRobert Mustacchi		"bit": 0,
144*281939dfSRobert Mustacchi		"rw": "Read-write",
145*281939dfSRobert Mustacchi		"description": "Dispatch of a single op that performs a memory load."
146*281939dfSRobert Mustacchi	} ]
147*281939dfSRobert Mustacchi},
148*281939dfSRobert Mustacchi{
149*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsSmiRx",
150*281939dfSRobert Mustacchi	"name": "LsSmiRx",
151*281939dfSRobert Mustacchi	"code": "0x02B",
152*281939dfSRobert Mustacchi	"summary": "SMIs Received",
153*281939dfSRobert Mustacchi	"description": "Counts the number of SMIs received."
154*281939dfSRobert Mustacchi},
155*281939dfSRobert Mustacchi{
156*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsIntTaken",
157*281939dfSRobert Mustacchi	"name": "LsIntTaken",
158*281939dfSRobert Mustacchi	"code": "0x02C",
159*281939dfSRobert Mustacchi	"summary": "Interrupts Taken",
160*281939dfSRobert Mustacchi	"description": "Counts the number of interrupts taken."
161*281939dfSRobert Mustacchi},
162*281939dfSRobert Mustacchi{
163*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsSTLF",
164*281939dfSRobert Mustacchi	"name": "LsSTLF",
165*281939dfSRobert Mustacchi	"code": "0x035",
166*281939dfSRobert Mustacchi	"summary": "Store to Load Forward",
167*281939dfSRobert Mustacchi	"description": "Number of STLF hits."
168*281939dfSRobert Mustacchi},
169*281939dfSRobert Mustacchi{
170*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsStCommitCancel2",
171*281939dfSRobert Mustacchi	"name": "LsStCommitCancel2",
172*281939dfSRobert Mustacchi	"code": "0x037",
173*281939dfSRobert Mustacchi	"summary": "Store Commit Cancels 2",
174*281939dfSRobert Mustacchi	"units": [ {
175*281939dfSRobert Mustacchi		"name": "StCommitCancelWcbFull",
176*281939dfSRobert Mustacchi		"bit": 0,
177*281939dfSRobert Mustacchi		"rw": "Read-write",
178*281939dfSRobert Mustacchi		"description": "A non-cacheable store and the non-cacheable commit buffer is full."
179*281939dfSRobert Mustacchi	} ]
180*281939dfSRobert Mustacchi},
181*281939dfSRobert Mustacchi{
182*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsMabAlloc",
183*281939dfSRobert Mustacchi	"name": "LsMabAlloc",
184*281939dfSRobert Mustacchi	"code": "0x041",
185*281939dfSRobert Mustacchi	"summary": "LS MAB Allocates by Type",
186*281939dfSRobert Mustacchi	"description": "Counts when a LS pipe allocates a MAB entry.",
187*281939dfSRobert Mustacchi	"unit_mode": "value",
188*281939dfSRobert Mustacchi	"units": [ {
189*281939dfSRobert Mustacchi		"name": "LsMabAllocation",
190*281939dfSRobert Mustacchi		"bit-range": "6:0",
191*281939dfSRobert Mustacchi		"rw": "Read-write",
192*281939dfSRobert Mustacchi		"values": [
193*281939dfSRobert Mustacchi			{ "value": "0x3f", "description": "Load Store Allocations." },
194*281939dfSRobert Mustacchi			{ "value": "0x40", "description": "Hardware Prefetecher Allocations." },
195*281939dfSRobert Mustacchi			{ "value": "0x7f", "description": "All Allocations." }
196*281939dfSRobert Mustacchi		]
197*281939dfSRobert Mustacchi	} ]
198*281939dfSRobert Mustacchi},
199*281939dfSRobert Mustacchi{
200*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsDmndFillsFromSys",
201*281939dfSRobert Mustacchi	"name": "LsDmndFillsFromSys",
202*281939dfSRobert Mustacchi	"code": "0x043",
203*281939dfSRobert Mustacchi	"summary": "Demand Data Cache Fills by Data Source",
204*281939dfSRobert Mustacchi	"description": "Demand Data Cache Fills by Data Source.",
205*281939dfSRobert Mustacchi	"units": [ {
206*281939dfSRobert Mustacchi		"name": "MemIoRemote",
207*281939dfSRobert Mustacchi		"bit": 6,
208*281939dfSRobert Mustacchi		"rw": "Read-write",
209*281939dfSRobert Mustacchi		"description": "From DRAM or IO connected in different Node."
210*281939dfSRobert Mustacchi	}, {
211*281939dfSRobert Mustacchi		"name": "ExtCacheRemote",
212*281939dfSRobert Mustacchi		"bit": 4,
213*281939dfSRobert Mustacchi		"rw": "Read-write",
214*281939dfSRobert Mustacchi		"description": "From CCX Cache in different Node."
215*281939dfSRobert Mustacchi	}, {
216*281939dfSRobert Mustacchi		"name": "MemIoLocal",
217*281939dfSRobert Mustacchi		"bit": 3,
218*281939dfSRobert Mustacchi		"rw": "Read-write",
219*281939dfSRobert Mustacchi		"description": "From DRAM or IO connected in same node."
220*281939dfSRobert Mustacchi	}, {
221*281939dfSRobert Mustacchi		"name": "ExtCacheLocal",
222*281939dfSRobert Mustacchi		"bit": 2,
223*281939dfSRobert Mustacchi		"rw": "Read-write",
224*281939dfSRobert Mustacchi		"description": "From cache of different CCX in same node."
225*281939dfSRobert Mustacchi	}, {
226*281939dfSRobert Mustacchi		"name": "IntCache",
227*281939dfSRobert Mustacchi		"bit": 1,
228*281939dfSRobert Mustacchi		"rw": "Read-write",
229*281939dfSRobert Mustacchi		"description": "From L3 or different L2 in same CCX."
230*281939dfSRobert Mustacchi	}, {
231*281939dfSRobert Mustacchi		"name": "LclL2",
232*281939dfSRobert Mustacchi		"bit": 0,
233*281939dfSRobert Mustacchi		"rw": "Read-write",
234*281939dfSRobert Mustacchi		"description": "From Local L2 to the core."
235*281939dfSRobert Mustacchi	} ]
236*281939dfSRobert Mustacchi},
237*281939dfSRobert Mustacchi{
238*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsAnyFillsFromSys",
239*281939dfSRobert Mustacchi	"name": "LsAnyFillsFromSys",
240*281939dfSRobert Mustacchi	"code": "0x044",
241*281939dfSRobert Mustacchi	"summary": "Any Data Cache Fills by Data Source",
242*281939dfSRobert Mustacchi	"description": "Any Data Cache Fills by Data Source.",
243*281939dfSRobert Mustacchi	"units": [ {
244*281939dfSRobert Mustacchi		"name": "MemIoRemote",
245*281939dfSRobert Mustacchi		"bit": 6,
246*281939dfSRobert Mustacchi		"rw": "Read-write",
247*281939dfSRobert Mustacchi		"description": "From DRAM or IO connected in different Node."
248*281939dfSRobert Mustacchi	}, {
249*281939dfSRobert Mustacchi		"name": "ExtCacheRemote",
250*281939dfSRobert Mustacchi		"bit": 4,
251*281939dfSRobert Mustacchi		"rw": "Read-write",
252*281939dfSRobert Mustacchi		"description": "From CCX Cache in different Node."
253*281939dfSRobert Mustacchi	}, {
254*281939dfSRobert Mustacchi		"name": "MemIoLocal",
255*281939dfSRobert Mustacchi		"bit": 3,
256*281939dfSRobert Mustacchi		"rw": "Read-write",
257*281939dfSRobert Mustacchi		"description": "From DRAM or IO connected in same node."
258*281939dfSRobert Mustacchi	}, {
259*281939dfSRobert Mustacchi		"name": "ExtCacheLocal",
260*281939dfSRobert Mustacchi		"bit": 2,
261*281939dfSRobert Mustacchi		"rw": "Read-write",
262*281939dfSRobert Mustacchi		"description": "From cache of different CCX in same node."
263*281939dfSRobert Mustacchi	}, {
264*281939dfSRobert Mustacchi		"name": "IntCache",
265*281939dfSRobert Mustacchi		"bit": 1,
266*281939dfSRobert Mustacchi		"rw": "Read-write",
267*281939dfSRobert Mustacchi		"description": "From L3 or different L2 in same CCX."
268*281939dfSRobert Mustacchi	}, {
269*281939dfSRobert Mustacchi		"name": "LclL2",
270*281939dfSRobert Mustacchi		"bit": 0,
271*281939dfSRobert Mustacchi		"rw": "Read-write",
272*281939dfSRobert Mustacchi		"description": "From Local L2 to the core."
273*281939dfSRobert Mustacchi	} ]
274*281939dfSRobert Mustacchi},
275*281939dfSRobert Mustacchi{
276*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsL1DTlbMiss",
277*281939dfSRobert Mustacchi	"name": "LsL1DTlbMiss",
278*281939dfSRobert Mustacchi	"code": "0x045",
279*281939dfSRobert Mustacchi	"summary": "L1 DTLB Misses",
280*281939dfSRobert Mustacchi	"units": [ {
281*281939dfSRobert Mustacchi		"name": "TlbReload1GL2Miss",
282*281939dfSRobert Mustacchi		"bit": 7,
283*281939dfSRobert Mustacchi		"rw": "Read-write",
284*281939dfSRobert Mustacchi		"description": "DTLB reload to a 1G page that also missed in the L2 TLB."
285*281939dfSRobert Mustacchi	}, {
286*281939dfSRobert Mustacchi		"name": "TlbReload2ML2Miss",
287*281939dfSRobert Mustacchi		"bit": 6,
288*281939dfSRobert Mustacchi		"rw": "Read-write",
289*281939dfSRobert Mustacchi		"description": "DTLB reload to a 2M page that also missed in the L2 TLB."
290*281939dfSRobert Mustacchi	}, {
291*281939dfSRobert Mustacchi		"name": "TlbReloadCoalescedPageMiss",
292*281939dfSRobert Mustacchi		"bit": 5,
293*281939dfSRobert Mustacchi		"rw": "Read-write",
294*281939dfSRobert Mustacchi		"description": "DTLB reload to a coalesced page that also missed in the L2 TLB."
295*281939dfSRobert Mustacchi	}, {
296*281939dfSRobert Mustacchi		"name": "TlbReload4KL2Miss",
297*281939dfSRobert Mustacchi		"bit": 4,
298*281939dfSRobert Mustacchi		"rw": "Read-write",
299*281939dfSRobert Mustacchi		"description": "DTLB reload to a 4 K page that missed the L2 TLB"
300*281939dfSRobert Mustacchi	}, {
301*281939dfSRobert Mustacchi		"name": "TlbReload1GL2Hit",
302*281939dfSRobert Mustacchi		"bit": 3,
303*281939dfSRobert Mustacchi		"rw": "Read-write",
304*281939dfSRobert Mustacchi		"description": "DTLB reload to a 1G page that hit in the L2 TLB."
305*281939dfSRobert Mustacchi	}, {
306*281939dfSRobert Mustacchi		"name": "TlbReload2ML2Hit",
307*281939dfSRobert Mustacchi		"bit": 2,
308*281939dfSRobert Mustacchi		"rw": "Read-write",
309*281939dfSRobert Mustacchi		"description": "DTLB reload to a 2M page that hit in the L2 TLB.1TlbReloadCoalescedPageHit. Read-write. Reset: 0. DTLB reload to a coalesced page that hit in the L2 TLB."
310*281939dfSRobert Mustacchi	}, {
311*281939dfSRobert Mustacchi		"name": "TlbReload4KL2Hit",
312*281939dfSRobert Mustacchi		"bit": 0,
313*281939dfSRobert Mustacchi		"rw": "Read-write",
314*281939dfSRobert Mustacchi		"description": "DTLB reload to a 4K page that hit in the L2 TLB."
315*281939dfSRobert Mustacchi	} ]
316*281939dfSRobert Mustacchi},
317*281939dfSRobert Mustacchi{
318*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsMisalLoads",
319*281939dfSRobert Mustacchi	"name": "LsMisalLoads",
320*281939dfSRobert Mustacchi	"code": "0x047",
321*281939dfSRobert Mustacchi	"summary": "Misaligned loads",
322*281939dfSRobert Mustacchi	"units": [ {
323*281939dfSRobert Mustacchi		"name": "MA4K",
324*281939dfSRobert Mustacchi		"bit": 1,
325*281939dfSRobert Mustacchi		"rw": "Read-write",
326*281939dfSRobert Mustacchi		"description": "The number of 4KB misaligned (i.e., page crossing) loads."
327*281939dfSRobert Mustacchi	}, {
328*281939dfSRobert Mustacchi		"name": "MA64",
329*281939dfSRobert Mustacchi		"bit": 0,
330*281939dfSRobert Mustacchi		"rw": "Read-write",
331*281939dfSRobert Mustacchi		"description": "The number of 64B misaligned (i.e., cacheline crossing) loads."
332*281939dfSRobert Mustacchi	} ]
333*281939dfSRobert Mustacchi},
334*281939dfSRobert Mustacchi{
335*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsPrefInstrDisp",
336*281939dfSRobert Mustacchi	"name": "LsPrefInstrDisp",
337*281939dfSRobert Mustacchi	"code": "0x04B",
338*281939dfSRobert Mustacchi	"summary": "Prefetch Instructions Dispatched",
339*281939dfSRobert Mustacchi	"description": "Software Prefetch Instructions Dispatched (Speculative).",
340*281939dfSRobert Mustacchi	"units": [ {
341*281939dfSRobert Mustacchi		"name": "PREFETCHNTA",
342*281939dfSRobert Mustacchi		"bit": 2,
343*281939dfSRobert Mustacchi		"rw": "Read-write",
344*281939dfSRobert Mustacchi		"description": "PrefetchNTA instruction. See docAPM3 PREFETCHlevel."
345*281939dfSRobert Mustacchi	}, {
346*281939dfSRobert Mustacchi		"name": "PREFETCHW",
347*281939dfSRobert Mustacchi		"bit": 1,
348*281939dfSRobert Mustacchi		"rw": "Read-write",
349*281939dfSRobert Mustacchi		"description": "PrefetchW instruction. See docAPM3 PREFETCHW."
350*281939dfSRobert Mustacchi	}, {
351*281939dfSRobert Mustacchi		"name": "PREFETCH",
352*281939dfSRobert Mustacchi		"bit": 0,
353*281939dfSRobert Mustacchi		"rw": "Read-write",
354*281939dfSRobert Mustacchi		"description": "PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel."
355*281939dfSRobert Mustacchi	} ]
356*281939dfSRobert Mustacchi},
357*281939dfSRobert Mustacchi{
358*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsInefSwPref",
359*281939dfSRobert Mustacchi	"name": "LsInefSwPref",
360*281939dfSRobert Mustacchi	"code": "0x052",
361*281939dfSRobert Mustacchi	"summary": "Ineffective Software Prefetches",
362*281939dfSRobert Mustacchi	"description": "The number of software prefetches that did not fetch data outside of the processor core.",
363*281939dfSRobert Mustacchi	"units": [ {
364*281939dfSRobert Mustacchi		"name": "MabMchCnt",
365*281939dfSRobert Mustacchi		"bit": 1,
366*281939dfSRobert Mustacchi		"rw": "Read-write",
367*281939dfSRobert Mustacchi		"description": "Software PREFETCH instruction saw a match on an already-allocated miss request buffer."
368*281939dfSRobert Mustacchi	}, {
369*281939dfSRobert Mustacchi		"name": "DataPipeSwPfDcHit",
370*281939dfSRobert Mustacchi		"bit": 0,
371*281939dfSRobert Mustacchi		"rw": "Read-write",
372*281939dfSRobert Mustacchi		"description": "Software PREFETCH instruction saw a DC hit."
373*281939dfSRobert Mustacchi	} ]
374*281939dfSRobert Mustacchi},
375*281939dfSRobert Mustacchi{
376*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsSwPfDcFills",
377*281939dfSRobert Mustacchi	"name": "LsSwPfDcFills",
378*281939dfSRobert Mustacchi	"code": "0x059",
379*281939dfSRobert Mustacchi	"summary": "Software Prefetch Data Cache Fills",
380*281939dfSRobert Mustacchi	"description": "Software Prefetch Data Cache Fills by Data Source.",
381*281939dfSRobert Mustacchi	"units": [ {
382*281939dfSRobert Mustacchi		"name": "MemIoRemote",
383*281939dfSRobert Mustacchi		"bit": 6,
384*281939dfSRobert Mustacchi		"rw": "Read-write",
385*281939dfSRobert Mustacchi		"description": "From DRAM or IO connected in different Node."
386*281939dfSRobert Mustacchi	}, {
387*281939dfSRobert Mustacchi		"name": "ExtCacheRemote",
388*281939dfSRobert Mustacchi		"bit": 4,
389*281939dfSRobert Mustacchi		"rw": "Read-write",
390*281939dfSRobert Mustacchi		"description": "From CCX Cache in different Node."
391*281939dfSRobert Mustacchi	}, {
392*281939dfSRobert Mustacchi		"name": "MemIoLocal",
393*281939dfSRobert Mustacchi		"bit": 3,
394*281939dfSRobert Mustacchi		"rw": "Read-write",
395*281939dfSRobert Mustacchi		"description": "From DRAM or IO connected in same node."
396*281939dfSRobert Mustacchi	}, {
397*281939dfSRobert Mustacchi		"name": "ExtCacheLocal",
398*281939dfSRobert Mustacchi		"bit": 2,
399*281939dfSRobert Mustacchi		"rw": "Read-write",
400*281939dfSRobert Mustacchi		"description": "From cache of different CCX in same node."
401*281939dfSRobert Mustacchi	}, {
402*281939dfSRobert Mustacchi		"name": "IntCache",
403*281939dfSRobert Mustacchi		"bit": 1,
404*281939dfSRobert Mustacchi		"rw": "Read-write",
405*281939dfSRobert Mustacchi		"description": "From L3 or different L2 in same CCX."
406*281939dfSRobert Mustacchi	}, {
407*281939dfSRobert Mustacchi		"name": "LclL2",
408*281939dfSRobert Mustacchi		"bit": 0,
409*281939dfSRobert Mustacchi		"rw": "Read-write",
410*281939dfSRobert Mustacchi		"description": "From Local L2 to the core."
411*281939dfSRobert Mustacchi	} ]
412*281939dfSRobert Mustacchi},
413*281939dfSRobert Mustacchi{
414*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsHwPfDcFills",
415*281939dfSRobert Mustacchi	"name": "LsHwPfDcFills",
416*281939dfSRobert Mustacchi	"code": "0x05A",
417*281939dfSRobert Mustacchi	"summary": "Hardware Prefetch Data Cache Fills",
418*281939dfSRobert Mustacchi	"description": "Hardware Prefetch Data Cache Fills by Data Source.",
419*281939dfSRobert Mustacchi	"units": [ {
420*281939dfSRobert Mustacchi		"name": "MemIoRemote",
421*281939dfSRobert Mustacchi		"bit": 6,
422*281939dfSRobert Mustacchi		"rw": "Read-write",
423*281939dfSRobert Mustacchi		"description": "From DRAM or IO connected in different Node."
424*281939dfSRobert Mustacchi	}, {
425*281939dfSRobert Mustacchi		"name": "ExtCacheRemote",
426*281939dfSRobert Mustacchi		"bit": 4,
427*281939dfSRobert Mustacchi		"rw": "Read-write",
428*281939dfSRobert Mustacchi		"description": "From CCX Cache in different Node."
429*281939dfSRobert Mustacchi	}, {
430*281939dfSRobert Mustacchi		"name": "MemIoLocal",
431*281939dfSRobert Mustacchi		"bit": 3,
432*281939dfSRobert Mustacchi		"rw": "Read-write",
433*281939dfSRobert Mustacchi		"description": "From DRAM or IO connected in same node."
434*281939dfSRobert Mustacchi	}, {
435*281939dfSRobert Mustacchi		"name": "ExtCacheLocal",
436*281939dfSRobert Mustacchi		"bit": 2,
437*281939dfSRobert Mustacchi		"rw": "Read-write",
438*281939dfSRobert Mustacchi		"description": "From cache of different CCX in same node."
439*281939dfSRobert Mustacchi	}, {
440*281939dfSRobert Mustacchi		"name": "IntCache",
441*281939dfSRobert Mustacchi		"bit": 1,
442*281939dfSRobert Mustacchi		"rw": "Read-write",
443*281939dfSRobert Mustacchi		"description": "From L3 or different L2 in same CCX."
444*281939dfSRobert Mustacchi	}, {
445*281939dfSRobert Mustacchi		"name": "LclL2",
446*281939dfSRobert Mustacchi		"bit": 0,
447*281939dfSRobert Mustacchi		"rw": "Read-write",
448*281939dfSRobert Mustacchi		"description": "From Local L2 to the core."
449*281939dfSRobert Mustacchi	} ]
450*281939dfSRobert Mustacchi},
451*281939dfSRobert Mustacchi{
452*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsAllocMabCount",
453*281939dfSRobert Mustacchi	"name": "LsAllocMabCount",
454*281939dfSRobert Mustacchi	"code": "0x05F",
455*281939dfSRobert Mustacchi	"summary": "Count of Allocated Mabs",
456*281939dfSRobert Mustacchi	"description": "This event counts the in-flight L1 data cache misses (allocated Miss Address Buffers) divided by 4 and rounded down each cycle unless used with the MergeEvent functionality. If the MergeEvent is used, it counts the exact number of outstanding L1 data cache misses. See 2.1.17.3 [Large Increment per Cycle Events]."
457*281939dfSRobert Mustacchi},
458*281939dfSRobert Mustacchi{
459*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsNotHaltedCyc",
460*281939dfSRobert Mustacchi	"name": "LsNotHaltedCyc",
461*281939dfSRobert Mustacchi	"code": "0x076",
462*281939dfSRobert Mustacchi	"summary": "Cycles not in Halt"
463*281939dfSRobert Mustacchi},
464*281939dfSRobert Mustacchi{
465*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsTlbFlush",
466*281939dfSRobert Mustacchi	"name": "LsTlbFlush",
467*281939dfSRobert Mustacchi	"code": "0x078",
468*281939dfSRobert Mustacchi	"summary": "All TLB Flushes",
469*281939dfSRobert Mustacchi	"description": "Requires unit mask 0xFF to engage event for counting.",
470*281939dfSRobert Mustacchi	"unit_mode": "value",
471*281939dfSRobert Mustacchi	"units": [ {
472*281939dfSRobert Mustacchi		"name": "All",
473*281939dfSRobert Mustacchi		"bit-range": "7:0",
474*281939dfSRobert Mustacchi		"rw": "Read-write",
475*281939dfSRobert Mustacchi		"values": [
476*281939dfSRobert Mustacchi			{ "value": "0xff", "description": "All TLB Flushes." }
477*281939dfSRobert Mustacchi		]
478*281939dfSRobert Mustacchi	} ]
479*281939dfSRobert Mustacchi},
480*281939dfSRobert Mustacchi{
481*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::IcCacheFillL2",
482*281939dfSRobert Mustacchi	"name": "IcCacheFillL2",
483*281939dfSRobert Mustacchi	"code": "0x082",
484*281939dfSRobert Mustacchi	"summary": "Instruction Cache Refills from L2",
485*281939dfSRobert Mustacchi	"description": "The number of 64-byte instruction cache line was fulfilled from the L2 cache."
486*281939dfSRobert Mustacchi},
487*281939dfSRobert Mustacchi{
488*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::IcCacheFillSys",
489*281939dfSRobert Mustacchi	"name": "IcCacheFillSys",
490*281939dfSRobert Mustacchi	"code": "0x083",
491*281939dfSRobert Mustacchi	"summary": "Instruction Cache Refills from System",
492*281939dfSRobert Mustacchi	"description": "The number of 64-byte instruction cache line fulfilled from system memory or another cache."
493*281939dfSRobert Mustacchi},
494*281939dfSRobert Mustacchi{
495*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::BpL1TlbMissL2TlbHit",
496*281939dfSRobert Mustacchi	"name": "BpL1TlbMissL2TlbHit",
497*281939dfSRobert Mustacchi	"code": "0x084",
498*281939dfSRobert Mustacchi	"summary": "L1 ITLB Miss, L2 ITLB Hit",
499*281939dfSRobert Mustacchi	"description": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
500*281939dfSRobert Mustacchi},
501*281939dfSRobert Mustacchi{
502*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::BpL1TlbMissL2TlbMiss",
503*281939dfSRobert Mustacchi	"name": "BpL1TlbMissL2TlbMiss",
504*281939dfSRobert Mustacchi	"code": "0x085",
505*281939dfSRobert Mustacchi	"summary": "ITLB Reload from Page-Table walk",
506*281939dfSRobert Mustacchi	"description": "The number of valid fills into the ITLB originating from the LS Page-Table Walker. Tablewalk requests are issued for L1-ITLB and L2-ITLB misses.",
507*281939dfSRobert Mustacchi	"units": [ {
508*281939dfSRobert Mustacchi		"name": "Coalesced4K",
509*281939dfSRobert Mustacchi		"bit": 3,
510*281939dfSRobert Mustacchi		"rw": "Read-write",
511*281939dfSRobert Mustacchi		"description": " Walk for >4K Coalesced page."
512*281939dfSRobert Mustacchi	}, {
513*281939dfSRobert Mustacchi		"name": "IF1G",
514*281939dfSRobert Mustacchi		"bit": 2,
515*281939dfSRobert Mustacchi		"rw": "Read-write",
516*281939dfSRobert Mustacchi		"description": " Walk for 1G page."
517*281939dfSRobert Mustacchi	}, {
518*281939dfSRobert Mustacchi		"name": "IF2M",
519*281939dfSRobert Mustacchi		"bit": 1,
520*281939dfSRobert Mustacchi		"rw": "Read-write",
521*281939dfSRobert Mustacchi		"description": " Walk for 2M page."
522*281939dfSRobert Mustacchi	}, {
523*281939dfSRobert Mustacchi		"name": "IF4K",
524*281939dfSRobert Mustacchi		"bit": 0,
525*281939dfSRobert Mustacchi		"rw": "Read-write",
526*281939dfSRobert Mustacchi		"description": " Walk to 4K page."
527*281939dfSRobert Mustacchi	} ]
528*281939dfSRobert Mustacchi},
529*281939dfSRobert Mustacchi{
530*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::BpL2BTBCorrect",
531*281939dfSRobert Mustacchi	"name": "BpL2BTBCorrect",
532*281939dfSRobert Mustacchi	"code": "0x08B",
533*281939dfSRobert Mustacchi	"summary": "L2 Branch Prediction Overrides Existing Prediction (speculative)"
534*281939dfSRobert Mustacchi},
535*281939dfSRobert Mustacchi{
536*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::BpDynIndPred",
537*281939dfSRobert Mustacchi	"name": "BpDynIndPred",
538*281939dfSRobert Mustacchi	"code": "0x08E",
539*281939dfSRobert Mustacchi	"summary": "Dynamic Indirect Predictions",
540*281939dfSRobert Mustacchi	"description": "The number of times a branch used the indirect predictor to make a prediction."
541*281939dfSRobert Mustacchi},
542*281939dfSRobert Mustacchi{
543*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::BpDeReDirect",
544*281939dfSRobert Mustacchi	"name": "BpDeReDirect",
545*281939dfSRobert Mustacchi	"code": "0x091",
546*281939dfSRobert Mustacchi	"summary": "Decode Redirects",
547*281939dfSRobert Mustacchi	"description": "The number of times the instruction decoder overrides the predicted target."
548*281939dfSRobert Mustacchi},
549*281939dfSRobert Mustacchi{
550*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::BpL1TlbFetchHit",
551*281939dfSRobert Mustacchi	"name": "BpL1TlbFetchHit",
552*281939dfSRobert Mustacchi	"code": "0x094",
553*281939dfSRobert Mustacchi	"summary": "L1 TLB Hits for Instruction Fetch",
554*281939dfSRobert Mustacchi	"description": "The number of instruction fetches that hit in the L1 ITLB.",
555*281939dfSRobert Mustacchi	"units": [ {
556*281939dfSRobert Mustacchi		"name": "IF1G",
557*281939dfSRobert Mustacchi		"bit": 2,
558*281939dfSRobert Mustacchi		"rw": "Read-write",
559*281939dfSRobert Mustacchi		"description": "L1 Instruction TLB hit (1G page size)."
560*281939dfSRobert Mustacchi	}, {
561*281939dfSRobert Mustacchi		"name": "IF2M",
562*281939dfSRobert Mustacchi		"bit": 1,
563*281939dfSRobert Mustacchi		"rw": "Read-write",
564*281939dfSRobert Mustacchi		"description": "L1 Instruction TLB hit (2M page size)."
565*281939dfSRobert Mustacchi	}, {
566*281939dfSRobert Mustacchi		"name": "IF4K",
567*281939dfSRobert Mustacchi		"bit": 0,
568*281939dfSRobert Mustacchi		"rw": "Read-write",
569*281939dfSRobert Mustacchi		"description": "L1 Instruction TLB hit (4K or 16K page size)."
570*281939dfSRobert Mustacchi	} ]
571*281939dfSRobert Mustacchi},
572*281939dfSRobert Mustacchi{
573*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::IcTagHitMiss",
574*281939dfSRobert Mustacchi	"name": "IcTagHitMiss",
575*281939dfSRobert Mustacchi	"code": "0x18E",
576*281939dfSRobert Mustacchi	"summary": "IC Tag Hit/Miss Events",
577*281939dfSRobert Mustacchi	"description": "Counts various IC tag related hit and miss events.",
578*281939dfSRobert Mustacchi	"unit_mode": "value",
579*281939dfSRobert Mustacchi	"units": [ {
580*281939dfSRobert Mustacchi		"name": "IcAccessTypes",
581*281939dfSRobert Mustacchi		"bit-range": "4:0",
582*281939dfSRobert Mustacchi		"rw": "Read-write",
583*281939dfSRobert Mustacchi		"description": "Instruction Cache accesses.",
584*281939dfSRobert Mustacchi		"values": [
585*281939dfSRobert Mustacchi			{ "value": "0x07", "description": "Instruction Cache Hit." },
586*281939dfSRobert Mustacchi			{ "value": "0x18", "description": "Instruction Cache Miss." },
587*281939dfSRobert Mustacchi			{ "value": "0x1f", "description": "All Instruction Cache Accesses." }
588*281939dfSRobert Mustacchi		]
589*281939dfSRobert Mustacchi	} ]
590*281939dfSRobert Mustacchi},
591*281939dfSRobert Mustacchi{
592*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::OpCacheHitMiss",
593*281939dfSRobert Mustacchi	"name": "OpCacheHitMiss",
594*281939dfSRobert Mustacchi	"code": "0x28F",
595*281939dfSRobert Mustacchi	"summary": "Op Cache Hit/Miss",
596*281939dfSRobert Mustacchi	"description": "Counts Op Cache micro-tag hit/miss events.",
597*281939dfSRobert Mustacchi	"unit_mode": "value",
598*281939dfSRobert Mustacchi	"units": [ {
599*281939dfSRobert Mustacchi		"name": "OpCacheAccesses",
600*281939dfSRobert Mustacchi		"bit-range": "2:0",
601*281939dfSRobert Mustacchi		"rw": "Read-write",
602*281939dfSRobert Mustacchi		"values": [
603*281939dfSRobert Mustacchi			{ "value": "0x03", "description": "Op Cache Hit." },
604*281939dfSRobert Mustacchi			{ "value": "0x04", "description": "Op Cache Miss." },
605*281939dfSRobert Mustacchi			{ "value": "0x07", "description": "All Op Cache accesses." }
606*281939dfSRobert Mustacchi		]
607*281939dfSRobert Mustacchi	} ]
608*281939dfSRobert Mustacchi},
609*281939dfSRobert Mustacchi{
610*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::DeSrcOpDisp",
611*281939dfSRobert Mustacchi	"name": "DeSrcOpDisp",
612*281939dfSRobert Mustacchi	"code": "0x0AA",
613*281939dfSRobert Mustacchi	"summary": "Source of Op Dispatched From Decoder",
614*281939dfSRobert Mustacchi	"description": "Counts the number of ops dispatched from the decoder classified by op source. See docRevG erratum #1287.",
615*281939dfSRobert Mustacchi	"units": [ {
616*281939dfSRobert Mustacchi		"name": "OpCache",
617*281939dfSRobert Mustacchi		"bit": 1,
618*281939dfSRobert Mustacchi		"rw": "Read-write",
619*281939dfSRobert Mustacchi		"description": "Count of ops fetched from Op Cache and dispatched."
620*281939dfSRobert Mustacchi	}, {
621*281939dfSRobert Mustacchi		"name": "x86Decoder",
622*281939dfSRobert Mustacchi		"bit": 0,
623*281939dfSRobert Mustacchi		"rw": "Read-write",
624*281939dfSRobert Mustacchi		"description": "Count of ops fetched from Instruction Cache and dispatched."
625*281939dfSRobert Mustacchi	} ]
626*281939dfSRobert Mustacchi},
627*281939dfSRobert Mustacchi{
628*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::DeDisCopsFromDecoder",
629*281939dfSRobert Mustacchi	"name": "DeDisCopsFromDecoder",
630*281939dfSRobert Mustacchi	"code": "0x0AB",
631*281939dfSRobert Mustacchi	"summary": "Types of Oops Dispatched From Decoder",
632*281939dfSRobert Mustacchi	"description": "Counts the number of ops dispatched from the decoder classified by op type. The UnitMask value encodes which types of ops are counted.",
633*281939dfSRobert Mustacchi	"unit_mode": "or-value",
634*281939dfSRobert Mustacchi	"units": [ {
635*281939dfSRobert Mustacchi		"name": "OpCountingMode",
636*281939dfSRobert Mustacchi		"bit": 7,
637*281939dfSRobert Mustacchi		"rw": "Read-write",
638*281939dfSRobert Mustacchi		"description": "0= count aligns with IBS count; 1= count aligns with retire count (PMCx0C1)."
639*281939dfSRobert Mustacchi	}, {
640*281939dfSRobert Mustacchi		"name": "DispOpType",
641*281939dfSRobert Mustacchi		"bit-range": "4:0",
642*281939dfSRobert Mustacchi		"rw": "Read-write",
643*281939dfSRobert Mustacchi		"values": [
644*281939dfSRobert Mustacchi			{ "value": "0x04", "description": "FP Dispatch." },
645*281939dfSRobert Mustacchi			{ "value": "0x08", "description": "Integer Dispatch." }
646*281939dfSRobert Mustacchi		]
647*281939dfSRobert Mustacchi	} ]
648*281939dfSRobert Mustacchi},
649*281939dfSRobert Mustacchi{
650*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::DeDisDispatchTokenStalls1",
651*281939dfSRobert Mustacchi	"name": "DeDisDispatchTokenStalls1",
652*281939dfSRobert Mustacchi	"code": "0x0AE",
653*281939dfSRobert Mustacchi	"summary": "Dispatch Resource Stall Cycles 1",
654*281939dfSRobert Mustacchi	"description": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to dispatch but would have been stalled due to a Token Stall.",
655*281939dfSRobert Mustacchi	"units": [ {
656*281939dfSRobert Mustacchi		"name": "FpFlushRecoveryStall",
657*281939dfSRobert Mustacchi		"bit": 7,
658*281939dfSRobert Mustacchi		"rw": "Read-write",
659*281939dfSRobert Mustacchi		"description": "FP Flush recovery stall."
660*281939dfSRobert Mustacchi	}, {
661*281939dfSRobert Mustacchi		"name": "FPSchRsrcStall",
662*281939dfSRobert Mustacchi		"bit": 6,
663*281939dfSRobert Mustacchi		"rw": "Read-write",
664*281939dfSRobert Mustacchi		"description": "FP scheduler resource stall.  Applies to ops that use the FP scheduler."
665*281939dfSRobert Mustacchi	}, {
666*281939dfSRobert Mustacchi		"name": "FpRegFileRsrcStall",
667*281939dfSRobert Mustacchi		"bit": 5,
668*281939dfSRobert Mustacchi		"rw": "Read-write",
669*281939dfSRobert Mustacchi		"description": "floating point register file resource stall.  Applies to all FP ops that have a destination register."
670*281939dfSRobert Mustacchi	}, {
671*281939dfSRobert Mustacchi		"name": "TakenBrnchBufferRsrc",
672*281939dfSRobert Mustacchi		"bit": 4,
673*281939dfSRobert Mustacchi		"rw": "Read-write",
674*281939dfSRobert Mustacchi		"description": "taken branch buffer resource stall. "
675*281939dfSRobert Mustacchi	}, {
676*281939dfSRobert Mustacchi		"name": "StoreQueueRsrcStall",
677*281939dfSRobert Mustacchi		"bit": 2,
678*281939dfSRobert Mustacchi		"rw": "Read-write",
679*281939dfSRobert Mustacchi		"description": "Store Queue resource stall.  Applies to all ops with store semantics."
680*281939dfSRobert Mustacchi	}, {
681*281939dfSRobert Mustacchi		"name": "LoadQueueRsrcStall",
682*281939dfSRobert Mustacchi		"bit": 1,
683*281939dfSRobert Mustacchi		"rw": "Read-write",
684*281939dfSRobert Mustacchi		"description": "Load Queue resource stall.  Applies to all ops with load semantics."
685*281939dfSRobert Mustacchi	}, {
686*281939dfSRobert Mustacchi		"name": "IntPhyRegFileRsrcStall",
687*281939dfSRobert Mustacchi		"bit": 0,
688*281939dfSRobert Mustacchi		"rw": "Read-write",
689*281939dfSRobert Mustacchi		"description": "Integer Physical Register File resource stall.  Integer Physical Register File, applies to all ops that have an integer destination register."
690*281939dfSRobert Mustacchi	} ]
691*281939dfSRobert Mustacchi},
692*281939dfSRobert Mustacchi{
693*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::DeDisDispatchTokenStalls2",
694*281939dfSRobert Mustacchi	"name": "DeDisDispatchTokenStalls2",
695*281939dfSRobert Mustacchi	"code": "0x0AF",
696*281939dfSRobert Mustacchi	"summary": "Dynamic Tokens Dispatch Stall Cycles 2",
697*281939dfSRobert Mustacchi	"description": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall.",
698*281939dfSRobert Mustacchi	"units": [ {
699*281939dfSRobert Mustacchi		"name": "RetireTokenStall",
700*281939dfSRobert Mustacchi		"bit": 5,
701*281939dfSRobert Mustacchi		"rw": "Read-write",
702*281939dfSRobert Mustacchi		"description": "Insufficient Retire Queue tokens available."
703*281939dfSRobert Mustacchi	}, {
704*281939dfSRobert Mustacchi		"name": "IntSch3TokenStall",
705*281939dfSRobert Mustacchi		"bit": 3,
706*281939dfSRobert Mustacchi		"rw": "Read-write",
707*281939dfSRobert Mustacchi		"description": "No tokens for Integer Scheduler Queue 3 available."
708*281939dfSRobert Mustacchi	}, {
709*281939dfSRobert Mustacchi		"name": "IntSch2TokenStall",
710*281939dfSRobert Mustacchi		"bit": 2,
711*281939dfSRobert Mustacchi		"rw": "Read-write",
712*281939dfSRobert Mustacchi		"description": "No tokens for Integer Scheduler Queue 2 available."
713*281939dfSRobert Mustacchi	}, {
714*281939dfSRobert Mustacchi		"name": "IntSch1TokenStall",
715*281939dfSRobert Mustacchi		"bit": 1,
716*281939dfSRobert Mustacchi		"rw": "Read-write",
717*281939dfSRobert Mustacchi		"description": "No tokens for Integer Scheduler Queue 1 available."
718*281939dfSRobert Mustacchi	}, {
719*281939dfSRobert Mustacchi		"name": "IntSch0TokenStall",
720*281939dfSRobert Mustacchi		"bit": 0,
721*281939dfSRobert Mustacchi		"rw": "Read-write",
722*281939dfSRobert Mustacchi		"description": "No tokens for Integer Scheduler Queue 0 available."
723*281939dfSRobert Mustacchi	} ]
724*281939dfSRobert Mustacchi},
725*281939dfSRobert Mustacchi{
726*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetInstr",
727*281939dfSRobert Mustacchi	"name": "ExRetInstr",
728*281939dfSRobert Mustacchi	"code": "0x0C0",
729*281939dfSRobert Mustacchi	"summary": "Retired Instructions",
730*281939dfSRobert Mustacchi	"description": "The number of instructions retired."
731*281939dfSRobert Mustacchi},
732*281939dfSRobert Mustacchi{
733*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetOps",
734*281939dfSRobert Mustacchi	"name": "ExRetOps",
735*281939dfSRobert Mustacchi	"code": "0x0C1",
736*281939dfSRobert Mustacchi	"summary": "Retired Ops",
737*281939dfSRobert Mustacchi	"description": "The number of macro-ops retired."
738*281939dfSRobert Mustacchi},
739*281939dfSRobert Mustacchi{
740*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrn",
741*281939dfSRobert Mustacchi	"name": "ExRetBrn",
742*281939dfSRobert Mustacchi	"code": "0x0C2",
743*281939dfSRobert Mustacchi	"summary": "Retired Branch Instructions",
744*281939dfSRobert Mustacchi	"description": "The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
745*281939dfSRobert Mustacchi},
746*281939dfSRobert Mustacchi{
747*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrnMisp",
748*281939dfSRobert Mustacchi	"name": "ExRetBrnMisp",
749*281939dfSRobert Mustacchi	"code": "0x0C3",
750*281939dfSRobert Mustacchi	"summary": "Retired Branch Instructions Mispredicted",
751*281939dfSRobert Mustacchi	"description": "The number of retired branch instructions, that were mispredicted."
752*281939dfSRobert Mustacchi},
753*281939dfSRobert Mustacchi{
754*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrnTkn",
755*281939dfSRobert Mustacchi	"name": "ExRetBrnTkn",
756*281939dfSRobert Mustacchi	"code": "0x0C4",
757*281939dfSRobert Mustacchi	"summary": "Retired Taken Branch Instructions",
758*281939dfSRobert Mustacchi	"description": "The number of taken branches that were retired.  This includes all types of architectural control flow changes, including exceptions and interrupts."
759*281939dfSRobert Mustacchi},
760*281939dfSRobert Mustacchi{
761*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrnTknMisp",
762*281939dfSRobert Mustacchi	"name": "ExRetBrnTknMisp",
763*281939dfSRobert Mustacchi	"code": "0x0C5",
764*281939dfSRobert Mustacchi	"summary": "Retired Taken Branch Instructions Mispredicted",
765*281939dfSRobert Mustacchi	"description": "The number of retired taken branch instructions that were mispredicted."
766*281939dfSRobert Mustacchi},
767*281939dfSRobert Mustacchi{
768*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrnFar",
769*281939dfSRobert Mustacchi	"name": "ExRetBrnFar",
770*281939dfSRobert Mustacchi	"code": "0x0C6",
771*281939dfSRobert Mustacchi	"summary": "Retired Far Control Transfers",
772*281939dfSRobert Mustacchi	"description": "The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction."
773*281939dfSRobert Mustacchi},
774*281939dfSRobert Mustacchi{
775*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetNearRet",
776*281939dfSRobert Mustacchi	"name": "ExRetNearRet",
777*281939dfSRobert Mustacchi	"code": "0x0C8",
778*281939dfSRobert Mustacchi	"summary": "Retired Near Returns",
779*281939dfSRobert Mustacchi	"description": "The number of near return instructions (RET or RET Iw) retired."
780*281939dfSRobert Mustacchi},
781*281939dfSRobert Mustacchi{
782*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetNearRetMispred",
783*281939dfSRobert Mustacchi	"name": "ExRetNearRetMispred",
784*281939dfSRobert Mustacchi	"code": "0x0C9",
785*281939dfSRobert Mustacchi	"summary": "Retired Near Returns Mispredicted",
786*281939dfSRobert Mustacchi	"description": "The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredictincurs the same penalty as a mispredicted conditional branch instruction."
787*281939dfSRobert Mustacchi},
788*281939dfSRobert Mustacchi{
789*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrnIndMisp",
790*281939dfSRobert Mustacchi	"name": "ExRetBrnIndMisp",
791*281939dfSRobert Mustacchi	"code": "0x0CA",
792*281939dfSRobert Mustacchi	"summary": "Retired Indirect Branch Instructions Mispredicted",
793*281939dfSRobert Mustacchi	"description": "The number of indirect branches retired that were not correctly predicted. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction. Note that only EX mispredicts are counted."
794*281939dfSRobert Mustacchi},
795*281939dfSRobert Mustacchi{
796*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetMmxFpInstr",
797*281939dfSRobert Mustacchi	"name": "ExRetMmxFpInstr",
798*281939dfSRobert Mustacchi	"code": "0x0CB",
799*281939dfSRobert Mustacchi	"summary": "Retired MMX/FP Instructions",
800*281939dfSRobert Mustacchi	"description": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPs.",
801*281939dfSRobert Mustacchi	"units": [ {
802*281939dfSRobert Mustacchi		"name": "SseInstr",
803*281939dfSRobert Mustacchi		"bit": 2,
804*281939dfSRobert Mustacchi		"rw": "Read-write",
805*281939dfSRobert Mustacchi		"description": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX)."
806*281939dfSRobert Mustacchi	}, {
807*281939dfSRobert Mustacchi		"name": "MmxInstr",
808*281939dfSRobert Mustacchi		"bit": 1,
809*281939dfSRobert Mustacchi		"rw": "Read-write",
810*281939dfSRobert Mustacchi		"description": "MMX instructions."
811*281939dfSRobert Mustacchi	}, {
812*281939dfSRobert Mustacchi		"name": "X87Instr",
813*281939dfSRobert Mustacchi		"bit": 0,
814*281939dfSRobert Mustacchi		"rw": "Read-write",
815*281939dfSRobert Mustacchi		"description": "x87 instructions. "
816*281939dfSRobert Mustacchi	} ]
817*281939dfSRobert Mustacchi},
818*281939dfSRobert Mustacchi{
819*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetIndBrchInstr",
820*281939dfSRobert Mustacchi	"name": "ExRetIndBrchInstr",
821*281939dfSRobert Mustacchi	"code": "0x0CC",
822*281939dfSRobert Mustacchi	"summary": "Retired Indirect Branch Instructions",
823*281939dfSRobert Mustacchi	"description": "The number of indirect branches retired."
824*281939dfSRobert Mustacchi},
825*281939dfSRobert Mustacchi{
826*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetCond",
827*281939dfSRobert Mustacchi	"name": "ExRetCond",
828*281939dfSRobert Mustacchi	"code": "0x0D1",
829*281939dfSRobert Mustacchi	"summary": "Retired Conditional Branch Instructions"
830*281939dfSRobert Mustacchi},
831*281939dfSRobert Mustacchi{
832*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExDivBusy",
833*281939dfSRobert Mustacchi	"name": "ExDivBusy",
834*281939dfSRobert Mustacchi	"code": "0x0D3",
835*281939dfSRobert Mustacchi	"summary": "Div Cycles Busy count"
836*281939dfSRobert Mustacchi},
837*281939dfSRobert Mustacchi{
838*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExDivCount",
839*281939dfSRobert Mustacchi	"name": "ExDivCount",
840*281939dfSRobert Mustacchi	"code": "0x0D4",
841*281939dfSRobert Mustacchi	"summary": "Div Op Count"
842*281939dfSRobert Mustacchi},
843*281939dfSRobert Mustacchi{
844*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetMsprdBrnchInstrDirMsmtch",
845*281939dfSRobert Mustacchi	"name": "ExRetMsprdBrnchInstrDirMsmtch",
846*281939dfSRobert Mustacchi	"code": "0x1C7",
847*281939dfSRobert Mustacchi	"summary": "Retired Mispredicted Branch Instructions due to Direction Mismatch",
848*281939dfSRobert Mustacchi	"description": "The number of retired conditional branch instructions that were not correctly predicted because of a branch direction mismatch."
849*281939dfSRobert Mustacchi},
850*281939dfSRobert Mustacchi{
851*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExTaggedIbsOps",
852*281939dfSRobert Mustacchi	"name": "ExTaggedIbsOps",
853*281939dfSRobert Mustacchi	"code": "0x1CF",
854*281939dfSRobert Mustacchi	"summary": "Tagged IBS Ops",
855*281939dfSRobert Mustacchi	"description": "Counts Op IBS related events.",
856*281939dfSRobert Mustacchi	"units": [ {
857*281939dfSRobert Mustacchi		"name": "IbsCountRollover",
858*281939dfSRobert Mustacchi		"bit": 2,
859*281939dfSRobert Mustacchi		"rw": "Read-write",
860*281939dfSRobert Mustacchi		"description": "Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired."
861*281939dfSRobert Mustacchi	}, {
862*281939dfSRobert Mustacchi		"name": "IbsTaggedOpsRet",
863*281939dfSRobert Mustacchi		"bit": 1,
864*281939dfSRobert Mustacchi		"rw": "Read-write",
865*281939dfSRobert Mustacchi		"description": "Number of Ops tagged by IBS that retired."
866*281939dfSRobert Mustacchi	}, {
867*281939dfSRobert Mustacchi		"name": "IbsTaggedOps",
868*281939dfSRobert Mustacchi		"bit": 0,
869*281939dfSRobert Mustacchi		"rw": "Read-write",
870*281939dfSRobert Mustacchi		"description": "Number of Ops tagged by IBS. "
871*281939dfSRobert Mustacchi	} ]
872*281939dfSRobert Mustacchi},
873*281939dfSRobert Mustacchi{
874*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetFusedInstr",
875*281939dfSRobert Mustacchi	"name": "ExRetFusedInstr",
876*281939dfSRobert Mustacchi	"code": "0x1D0",
877*281939dfSRobert Mustacchi	"summary": "Retired Fused Instructions",
878*281939dfSRobert Mustacchi	"description": "Counts retired fused instructions."
879*281939dfSRobert Mustacchi},
880*281939dfSRobert Mustacchi{
881*281939dfSRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::L2RequestG1",
882*281939dfSRobert Mustacchi	"name": "L2RequestG1",
883*281939dfSRobert Mustacchi	"code": "0x060",
884