1d0e58ef5SRobert Mustacchi[
2d0e58ef5SRobert Mustacchi{
3d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::FpRetSseAvxOps",
4d0e58ef5SRobert Mustacchi	"name": "FpRetSseAvxOps",
5d0e58ef5SRobert Mustacchi	"code": "0x003",
6*31aa6202SRobert Mustacchi	"summary": "Retired SSE/AVX FLOPs",
7*31aa6202SRobert Mustacchi	"description": "This is a retire-based event. The number of retired SSE/AVX FLOPs. The number of events logged per cycle can vary from 0 to 64. This event is a MergeEvent since it can count above 15.",
8*31aa6202SRobert Mustacchi	"units": [ {
9*31aa6202SRobert Mustacchi		"name": "MacFLOPs",
10d0e58ef5SRobert Mustacchi		"bit": 3,
11d0e58ef5SRobert Mustacchi		"rw": "Read-write",
12*31aa6202SRobert Mustacchi		"description": "MacFLOPs count as 2 FLOPs. Does not provide a useful count without use of the MergeEvent feature."
13d0e58ef5SRobert Mustacchi	}, {
14*31aa6202SRobert Mustacchi		"name": "DivFLOPs",
15d0e58ef5SRobert Mustacchi		"bit": 2,
16d0e58ef5SRobert Mustacchi		"rw": "Read-write",
17*31aa6202SRobert Mustacchi		"description": "Divide/square root FLOPs. Does not provide a useful count without use of the MergeEvent feature."
18d0e58ef5SRobert Mustacchi	}, {
19*31aa6202SRobert Mustacchi		"name": "MultFLOPs",
20d0e58ef5SRobert Mustacchi		"bit": 1,
21d0e58ef5SRobert Mustacchi		"rw": "Read-write",
22*31aa6202SRobert Mustacchi		"description": "Multiply FLOPs. Does not provide a useful count without use of the MergeEvent feature."
23d0e58ef5SRobert Mustacchi	}, {
24*31aa6202SRobert Mustacchi		"name": "AddSubFLOPs",
25d0e58ef5SRobert Mustacchi		"bit": 0,
26d0e58ef5SRobert Mustacchi		"rw": "Read-write",
27*31aa6202SRobert Mustacchi		"description": "Add/subtract FLOPs. Does not provide a useful count without use of the MergeEvent feature."
28d0e58ef5SRobert Mustacchi	} ]
29d0e58ef5SRobert Mustacchi},
30d0e58ef5SRobert Mustacchi{
31*31aa6202SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::FpRetiredSerOps",
32*31aa6202SRobert Mustacchi	"name": "FpRetiredSerOps",
33*31aa6202SRobert Mustacchi	"code": "0x005",
34*31aa6202SRobert Mustacchi	"summary": "Retired Serializing Ops",
35*31aa6202SRobert Mustacchi	"description": "The number of serializing Ops retired.",
36d0e58ef5SRobert Mustacchi	"units": [ {
37*31aa6202SRobert Mustacchi		"name": "SseBotRet",
38d0e58ef5SRobert Mustacchi		"bit": 3,
39d0e58ef5SRobert Mustacchi		"rw": "Read-write",
40*31aa6202SRobert Mustacchi		"description": "SSE bottom-executing uOps retired."
41d0e58ef5SRobert Mustacchi	}, {
42*31aa6202SRobert Mustacchi		"name": "SseCtrlRet",
43d0e58ef5SRobert Mustacchi		"bit": 2,
44d0e58ef5SRobert Mustacchi		"rw": "Read-write",
45*31aa6202SRobert Mustacchi		"description": "SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits."
46d0e58ef5SRobert Mustacchi	}, {
47*31aa6202SRobert Mustacchi		"name": "X87BotRet",
48d0e58ef5SRobert Mustacchi		"bit": 1,
49d0e58ef5SRobert Mustacchi		"rw": "Read-write",
50*31aa6202SRobert Mustacchi		"description": "x87 bottom-executing uOps retired."
51d0e58ef5SRobert Mustacchi	}, {
52*31aa6202SRobert Mustacchi		"name": "X87CtrlRet",
53d0e58ef5SRobert Mustacchi		"bit": 0,
54d0e58ef5SRobert Mustacchi		"rw": "Read-write",
55*31aa6202SRobert Mustacchi		"description": "x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits."
56d0e58ef5SRobert Mustacchi	} ]
57d0e58ef5SRobert Mustacchi},
58d0e58ef5SRobert Mustacchi{
59*31aa6202SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::FpDispFaults",
60*31aa6202SRobert Mustacchi	"name": "FpDispFaults",
61*31aa6202SRobert Mustacchi	"code": "0x00E",
62*31aa6202SRobert Mustacchi	"summary": "FP Dispatch Faults",
63*31aa6202SRobert Mustacchi	"description": "Floating Point Dispatch Faults.",
64d0e58ef5SRobert Mustacchi	"units": [ {
65*31aa6202SRobert Mustacchi		"name": "YmmSpillFault",
66d0e58ef5SRobert Mustacchi		"bit": 3,
67d0e58ef5SRobert Mustacchi		"rw": "Read-write",
68*31aa6202SRobert Mustacchi		"description": "YMM Spill fault."
69d0e58ef5SRobert Mustacchi	}, {
70*31aa6202SRobert Mustacchi		"name": "YmmFillFault",
71d0e58ef5SRobert Mustacchi		"bit": 2,
72d0e58ef5SRobert Mustacchi		"rw": "Read-write",
73*31aa6202SRobert Mustacchi		"description": "YMM Fill fault."
74d0e58ef5SRobert Mustacchi	}, {
75*31aa6202SRobert Mustacchi		"name": "XmmFillFault",
76d0e58ef5SRobert Mustacchi		"bit": 1,
77d0e58ef5SRobert Mustacchi		"rw": "Read-write",
78*31aa6202SRobert Mustacchi		"description": "XMM Fill fault."
79d0e58ef5SRobert Mustacchi	}, {
80*31aa6202SRobert Mustacchi		"name": "x87FillFault",
81d0e58ef5SRobert Mustacchi		"bit": 0,
82d0e58ef5SRobert Mustacchi		"rw": "Read-write",
83*31aa6202SRobert Mustacchi		"description": "x87 Fill fault."
84d0e58ef5SRobert Mustacchi	} ]
85d0e58ef5SRobert Mustacchi},
86d0e58ef5SRobert Mustacchi{
87d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsBadStatus2",
88d0e58ef5SRobert Mustacchi	"name": "LsBadStatus2",
89d0e58ef5SRobert Mustacchi	"code": "0x024",
90d0e58ef5SRobert Mustacchi	"summary": "Bad Status 2",
91d0e58ef5SRobert Mustacchi	"description": "Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason. There are a number of reasons why this occurs, and this perfmon organizes them into three major groups.",
92d0e58ef5SRobert Mustacchi	"units": [ {
93d0e58ef5SRobert Mustacchi		"name": "StliOther",
94d0e58ef5SRobert Mustacchi		"bit": 1,
95d0e58ef5SRobert Mustacchi		"rw": "Read-write",
96*31aa6202SRobert Mustacchi		"description": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. The most common among these is that there is only a partial overlap between the store and the load, for example there's an 8B store to address A and a 16B load starting at address A. STLF can't be performed in this case because only some of the load's data is coming from the store, so the load gets StliOther. Another StliOther case is if the load hits a non-cacheable store that's sitting in the non-cacheable buffers (WCBs)."
97d0e58ef5SRobert Mustacchi	} ]
98d0e58ef5SRobert Mustacchi},
99d0e58ef5SRobert Mustacchi{
100d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsLocks",
101d0e58ef5SRobert Mustacchi	"name": "LsLocks",
102d0e58ef5SRobert Mustacchi	"code": "0x025",
103*31aa6202SRobert Mustacchi	"summary": "Retired Lock Instructions",
104d0e58ef5SRobert Mustacchi	"unit_mode": "or",
105d0e58ef5SRobert Mustacchi	"units": [ {
106*31aa6202SRobert Mustacchi		"name": "SpecLockHiSpec",
107d0e58ef5SRobert Mustacchi		"bit": 3,
108*31aa6202SRobert Mustacchi		"rw": "Read-write",
109*31aa6202SRobert Mustacchi		"description": "High speculative cacheable lock speculation succeeded."
110d0e58ef5SRobert Mustacchi	}, {
111*31aa6202SRobert Mustacchi		"name": "SpecLockLoSpec",
112d0e58ef5SRobert Mustacchi		"bit": 2,
113*31aa6202SRobert Mustacchi		"rw": "Read-write",
114*31aa6202SRobert Mustacchi		"description": "Low speculative cacheable lock speculation succeeded."
115d0e58ef5SRobert Mustacchi	}, {
116d0e58ef5SRobert Mustacchi		"name": "NonSpecLock",
117d0e58ef5SRobert Mustacchi		"bit": 1,
118d0e58ef5SRobert Mustacchi		"rw": "Read-write"
119d0e58ef5SRobert Mustacchi	}, {
120d0e58ef5SRobert Mustacchi		"name": "BusLock",
121d0e58ef5SRobert Mustacchi		"bit": 0,
122*31aa6202SRobert Mustacchi		"rw": "Read-write",
123*31aa6202SRobert Mustacchi		"description": "Comparable to legacy bus lock."
124d0e58ef5SRobert Mustacchi	} ]
125d0e58ef5SRobert Mustacchi},
126d0e58ef5SRobert Mustacchi{
127d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsRetClClush",
128d0e58ef5SRobert Mustacchi	"name": "LsRetClClush",
129d0e58ef5SRobert Mustacchi	"code": "0x026",
130d0e58ef5SRobert Mustacchi	"summary": "Retired CLFLUSH Instructions",
131d0e58ef5SRobert Mustacchi	"description": "The number of retired CLFLUSH instructions. This is a non-speculative event."
132d0e58ef5SRobert Mustacchi},
133d0e58ef5SRobert Mustacchi{
134d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsRetCpuid",
135d0e58ef5SRobert Mustacchi	"name": "LsRetCpuid",
136d0e58ef5SRobert Mustacchi	"code": "0x027",
137d0e58ef5SRobert Mustacchi	"summary": "Retired CPUID Instructions",
138d0e58ef5SRobert Mustacchi	"description": "The number of CPUID instructions retired."
139d0e58ef5SRobert Mustacchi},
140d0e58ef5SRobert Mustacchi{
141d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsDispatch",
142d0e58ef5SRobert Mustacchi	"name": "LsDispatch",
143d0e58ef5SRobert Mustacchi	"code": "0x029",
144d0e58ef5SRobert Mustacchi	"summary": "LS Dispatch",
145d0e58ef5SRobert Mustacchi	"description": "Counts the number of operations dispatched to the LS unit.",
146d0e58ef5SRobert Mustacchi	"unit_mode": "add",
147d0e58ef5SRobert Mustacchi	"units": [ {
148d0e58ef5SRobert Mustacchi		"name": "LdStDispatch",
149d0e58ef5SRobert Mustacchi		"bit": 2,
150d0e58ef5SRobert Mustacchi		"rw": "Read-write",
151*31aa6202SRobert Mustacchi		"description": "Load-op-Store Dispatch. Dispatch of a single op that performs a load from and store to the same memory address."
152d0e58ef5SRobert Mustacchi	}, {
153d0e58ef5SRobert Mustacchi		"name": "StoreDispatch",
154d0e58ef5SRobert Mustacchi		"bit": 1,
155d0e58ef5SRobert Mustacchi		"rw": "Read-write"
156d0e58ef5SRobert Mustacchi	}, {
157d0e58ef5SRobert Mustacchi		"name": "LdDispatch",
158d0e58ef5SRobert Mustacchi		"bit": 0,
159d0e58ef5SRobert Mustacchi		"rw": "Read-write"
160d0e58ef5SRobert Mustacchi	} ]
161d0e58ef5SRobert Mustacchi},
162d0e58ef5SRobert Mustacchi{
163d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsSmiRx",
164d0e58ef5SRobert Mustacchi	"name": "LsSmiRx",
165d0e58ef5SRobert Mustacchi	"code": "0x02B",
166d0e58ef5SRobert Mustacchi	"summary": "SMIs Received",
167d0e58ef5SRobert Mustacchi	"description": "Counts the number of SMIs received."
168d0e58ef5SRobert Mustacchi},
169*31aa6202SRobert Mustacchi{
170*31aa6202SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsIntTaken",
171*31aa6202SRobert Mustacchi	"name": "LsIntTaken",
172*31aa6202SRobert Mustacchi	"code": "0x02C",
173*31aa6202SRobert Mustacchi	"summary": "Interrupts Taken",
174*31aa6202SRobert Mustacchi	"description": "Counts the number of interrupts taken."
175*31aa6202SRobert Mustacchi},
176*31aa6202SRobert Mustacchi{
177*31aa6202SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsRdTsc",
178*31aa6202SRobert Mustacchi	"name": "LsRdTsc",
179*31aa6202SRobert Mustacchi	"code": "0x02D",
180*31aa6202SRobert Mustacchi	"summary": "Time Stamp Counter Reads",
181*31aa6202SRobert Mustacchi	"description": "Counts the number of reads of the TSC (RDTSC instructions). The count is speculative."
182*31aa6202SRobert Mustacchi},
183d0e58ef5SRobert Mustacchi{
184d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsSTLF",
185d0e58ef5SRobert Mustacchi	"name": "LsSTLF",
186d0e58ef5SRobert Mustacchi	"code": "0x035",
187d0e58ef5SRobert Mustacchi	"summary": "Store to Load Forward",
188d0e58ef5SRobert Mustacchi	"description": "Number of STLF hits."
189d0e58ef5SRobert Mustacchi},
190d0e58ef5SRobert Mustacchi{
191d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsStCommitCancel2",
192d0e58ef5SRobert Mustacchi	"name": "LsStCommitCancel2",
193d0e58ef5SRobert Mustacchi	"code": "0x037",
194d0e58ef5SRobert Mustacchi	"summary": "Store Commit Cancels 2",
195d0e58ef5SRobert Mustacchi	"units": [ {
196d0e58ef5SRobert Mustacchi		"name": "StCommitCancelWcbFull",
197d0e58ef5SRobert Mustacchi		"bit": 0,
198d0e58ef5SRobert Mustacchi		"rw": "Read-write",
199d0e58ef5SRobert Mustacchi		"description": "A non-cacheable store and the non-cacheable commit buffer is full."
200d0e58ef5SRobert Mustacchi	} ]
201d0e58ef5SRobert Mustacchi},
202d0e58ef5SRobert Mustacchi{
203d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsDcAccesses",
204d0e58ef5SRobert Mustacchi	"name": "LsDcAccesses",
205d0e58ef5SRobert Mustacchi	"code": "0x040",
206d0e58ef5SRobert Mustacchi	"summary": "Data Cache Accesses",
207d0e58ef5SRobert Mustacchi	"description": "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event."
208d0e58ef5SRobert Mustacchi},
209*31aa6202SRobert Mustacchi{
210*31aa6202SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsMabAlloc",
211*31aa6202SRobert Mustacchi	"name": "LsMabAlloc",
212*31aa6202SRobert Mustacchi	"code": "0x041",
213*31aa6202SRobert Mustacchi	"summary": "DC Miss By Type",
214*31aa6202SRobert Mustacchi	"units": [ {
215*31aa6202SRobert Mustacchi		"name": "DcPrefetcher",
216*31aa6202SRobert Mustacchi		"bit": 3,
217*31aa6202SRobert Mustacchi		"rw": "Read-write"
218*31aa6202SRobert Mustacchi	}, {
219*31aa6202SRobert Mustacchi		"name": "Stores",
220*31aa6202SRobert Mustacchi		"bit": 1,
221*31aa6202SRobert Mustacchi		"rw": "Read-write"
222*31aa6202SRobert Mustacchi	}, {
223*31aa6202SRobert Mustacchi		"name": "Loads",
224*31aa6202SRobert Mustacchi		"bit": 0,
225*31aa6202SRobert Mustacchi		"rw": "Read-write"
226*31aa6202SRobert Mustacchi	} ]
227*31aa6202SRobert Mustacchi},
228d0e58ef5SRobert Mustacchi{
229d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsRefillsFromSys",
230d0e58ef5SRobert Mustacchi	"name": "LsRefillsFromSys",
231d0e58ef5SRobert Mustacchi	"code": "0x043",
232d0e58ef5SRobert Mustacchi	"summary": "Data Cache Refills from System",
233d0e58ef5SRobert Mustacchi	"description": "Demand Data Cache Fills by Data Source.",
234d0e58ef5SRobert Mustacchi	"units": [ {
235d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_RMT_DRAM",
236d0e58ef5SRobert Mustacchi		"bit": 6,
237d0e58ef5SRobert Mustacchi		"rw": "Read-write",
238d0e58ef5SRobert Mustacchi		"description": "DRAM or IO from different die."
239d0e58ef5SRobert Mustacchi	}, {
240d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_RMT_CACHE",
241d0e58ef5SRobert Mustacchi		"bit": 4,
242d0e58ef5SRobert Mustacchi		"rw": "Read-write",
243d0e58ef5SRobert Mustacchi		"description": "Hit in cache; Remote CCX and the address's Home Node is on a different die."
244d0e58ef5SRobert Mustacchi	}, {
245d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_LCL_DRAM",
246d0e58ef5SRobert Mustacchi		"bit": 3,
247d0e58ef5SRobert Mustacchi		"rw": "Read-write",
248d0e58ef5SRobert Mustacchi		"description": "DRAM or IO from this thread's die."
249d0e58ef5SRobert Mustacchi	}, {
250d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_LCL_CACHE",
251d0e58ef5SRobert Mustacchi		"bit": 1,
252d0e58ef5SRobert Mustacchi		"rw": "Read-write",
253*31aa6202SRobert Mustacchi		"description": "Hit in cache; local CCX (not Local L2), or Remote CCXand the address's Home Node is on this thread's die."
254d0e58ef5SRobert Mustacchi	}, {
255d0e58ef5SRobert Mustacchi		"name": "MABRESP_LCL_L2",
256d0e58ef5SRobert Mustacchi		"bit": 0,
257d0e58ef5SRobert Mustacchi		"rw": "Read-write",
258d0e58ef5SRobert Mustacchi		"description": "Local L2 hit."
259d0e58ef5SRobert Mustacchi	} ]
260d0e58ef5SRobert Mustacchi},
261d0e58ef5SRobert Mustacchi{
262d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsL1DTlbMiss",
263d0e58ef5SRobert Mustacchi	"name": "LsL1DTlbMiss",
264d0e58ef5SRobert Mustacchi	"code": "0x045",
265d0e58ef5SRobert Mustacchi	"summary": "L1 DTLB Miss",
266d0e58ef5SRobert Mustacchi	"units": [ {
267d0e58ef5SRobert Mustacchi		"name": "TlbReload1GL2Miss",
268d0e58ef5SRobert Mustacchi		"bit": 7,
269*31aa6202SRobert Mustacchi		"rw": "Read-write",
270*31aa6202SRobert Mustacchi		"description": "DTLB reload to a 1G page that miss in the L2 TLB."
271d0e58ef5SRobert Mustacchi	}, {
272d0e58ef5SRobert Mustacchi		"name": "TlbReload2ML2Miss",
273d0e58ef5SRobert Mustacchi		"bit": 6,
274*31aa6202SRobert Mustacchi		"rw": "Read-write",
275*31aa6202SRobert Mustacchi		"description": "DTLB reload to a 2M page that miss in the L2 TLB."
276d0e58ef5SRobert Mustacchi	}, {
277*31aa6202SRobert Mustacchi		"name": "TlbReloadCoalescedPageMiss",
278d0e58ef5SRobert Mustacchi		"bit": 5,
279d0e58ef5SRobert Mustacchi		"rw": "Read-write"
280d0e58ef5SRobert Mustacchi	}, {
281d0e58ef5SRobert Mustacchi		"name": "TlbReload4KL2Miss",
282d0e58ef5SRobert Mustacchi		"bit": 4,
283*31aa6202SRobert Mustacchi		"rw": "Read-write",
284*31aa6202SRobert Mustacchi		"description": "DTLB reload to a 4K page that miss the L2 TLB."
285d0e58ef5SRobert Mustacchi	}, {
286d0e58ef5SRobert Mustacchi		"name": "TlbReload1GL2Hit",
287d0e58ef5SRobert Mustacchi		"bit": 3,
288*31aa6202SRobert Mustacchi		"rw": "Read-write",
289*31aa6202SRobert Mustacchi		"description": "DTLB reload to a 1G page that hit in the L2 TLB."
290d0e58ef5SRobert Mustacchi	}, {
291d0e58ef5SRobert Mustacchi		"name": "TlbReload2ML2Hit",
292d0e58ef5SRobert Mustacchi		"bit": 2,
293*31aa6202SRobert Mustacchi		"rw": "Read-write",
294*31aa6202SRobert Mustacchi		"description": "DTLB reload to a 2M page that hit in the L2 TLB."
295d0e58ef5SRobert Mustacchi	}, {
296*31aa6202SRobert Mustacchi		"name": "TlbReloadCoalescedPageHit",
297d0e58ef5SRobert Mustacchi		"bit": 1,
298d0e58ef5SRobert Mustacchi		"rw": "Read-write"
299d0e58ef5SRobert Mustacchi	}, {
300d0e58ef5SRobert Mustacchi		"name": "TlbReload4KL2Hit",
301d0e58ef5SRobert Mustacchi		"bit": 0,
302*31aa6202SRobert Mustacchi		"rw": "Read-write",
303*31aa6202SRobert Mustacchi		"description": "DTLB reload to a 4K page that hit in the L2 TLB."
304d0e58ef5SRobert Mustacchi	} ]
305d0e58ef5SRobert Mustacchi},
306d0e58ef5SRobert Mustacchi{
307d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsMisalAccesses",
308d0e58ef5SRobert Mustacchi	"name": "LsMisalAccesses",
309d0e58ef5SRobert Mustacchi	"code": "0x047",
310d0e58ef5SRobert Mustacchi	"summary": "Misaligned loads"
311d0e58ef5SRobert Mustacchi},
312d0e58ef5SRobert Mustacchi{
313d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsPrefInstrDisp",
314d0e58ef5SRobert Mustacchi	"name": "LsPrefInstrDisp",
315d0e58ef5SRobert Mustacchi	"code": "0x04B",
316d0e58ef5SRobert Mustacchi	"summary": "Prefetch Instructions Dispatched",
317*31aa6202SRobert Mustacchi	"description": "Software Prefetch Instructions Dispatched (Speculative).",
318d0e58ef5SRobert Mustacchi	"units": [ {
319d0e58ef5SRobert Mustacchi		"name": "PrefetchNTA",
320d0e58ef5SRobert Mustacchi		"bit": 2,
321*31aa6202SRobert Mustacchi		"rw": "Read-write",
322*31aa6202SRobert Mustacchi		"description": "PrefetchNTA instruction. See AMD64 Architecture Programmer's Manual Volume 3: Instruction-Set Reference, order# 24594 PREFETCHlevel."
323d0e58ef5SRobert Mustacchi	}, {
324*31aa6202SRobert Mustacchi		"name": "PrefetchW",
325d0e58ef5SRobert Mustacchi		"bit": 1,
326*31aa6202SRobert Mustacchi		"rw": "Read-write",
327*31aa6202SRobert Mustacchi		"description": "PrefetchW instruction. See AMD64 Architecture Programmer's Manual Volume 3: Instruction-Set Reference, order# 24594 PREFETCHlevel."
328d0e58ef5SRobert Mustacchi	}, {
329*31aa6202SRobert Mustacchi		"name": "Prefetch",
330d0e58ef5SRobert Mustacchi		"bit": 0,
331d0e58ef5SRobert Mustacchi		"rw": "Read-write",
332*31aa6202SRobert Mustacchi		"description": "PrefetchT0, T1 and T2 instructions. See AMD64 Architecture Programmer's Manual Volume 3: Instruction-Set Reference, order# 24594 PREFETCHlevel."
333d0e58ef5SRobert Mustacchi	} ]
334d0e58ef5SRobert Mustacchi},
335d0e58ef5SRobert Mustacchi{
336d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsInefSwPref",
337d0e58ef5SRobert Mustacchi	"name": "LsInefSwPref",
338d0e58ef5SRobert Mustacchi	"code": "0x052",
339*31aa6202SRobert Mustacchi	"summary": "Ineffective Software Prefetches",
340d0e58ef5SRobert Mustacchi	"description": "The number of software prefetches that did not fetch data outside of the processor core.",
341d0e58ef5SRobert Mustacchi	"units": [ {
342d0e58ef5SRobert Mustacchi		"name": "MabMchCnt",
343d0e58ef5SRobert Mustacchi		"bit": 1,
344d0e58ef5SRobert Mustacchi		"rw": "Read-write",
345d0e58ef5SRobert Mustacchi		"description": "Software PREFETCH instruction saw a match on an already-allocated miss request buffer."
346d0e58ef5SRobert Mustacchi	}, {
347d0e58ef5SRobert Mustacchi		"name": "DataPipeSwPfDcHit",
348d0e58ef5SRobert Mustacchi		"bit": 0,
349d0e58ef5SRobert Mustacchi		"rw": "Read-write",
350d0e58ef5SRobert Mustacchi		"description": "Software PREFETCH instruction saw a DC hit."
351d0e58ef5SRobert Mustacchi	} ]
352d0e58ef5SRobert Mustacchi},
353d0e58ef5SRobert Mustacchi{
354d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsSwPfDcFills",
355d0e58ef5SRobert Mustacchi	"name": "LsSwPfDcFills",
356d0e58ef5SRobert Mustacchi	"code": "0x059",
357d0e58ef5SRobert Mustacchi	"summary": "Software Prefetch Data Cache Fills",
358*31aa6202SRobert Mustacchi	"description": "Software Prefetch Data Cache Fills by Data Source.",
359d0e58ef5SRobert Mustacchi	"units": [ {
360d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_RMT_DRAM",
361d0e58ef5SRobert Mustacchi		"bit": 6,
362d0e58ef5SRobert Mustacchi		"rw": "Read-write",
363d0e58ef5SRobert Mustacchi		"description": "DRAM or IO from different die."
364d0e58ef5SRobert Mustacchi	}, {
365d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_RMT_CACHE",
366d0e58ef5SRobert Mustacchi		"bit": 4,
367d0e58ef5SRobert Mustacchi		"rw": "Read-write",
368d0e58ef5SRobert Mustacchi		"description": "Hit in cache; Remote CCX and the address's Home Node is on a different die."
369d0e58ef5SRobert Mustacchi	}, {
370d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_LCL_DRAM",
371d0e58ef5SRobert Mustacchi		"bit": 3,
372d0e58ef5SRobert Mustacchi		"rw": "Read-write",
373d0e58ef5SRobert Mustacchi		"description": "DRAM or IO from this thread's die."
374d0e58ef5SRobert Mustacchi	}, {
375d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_LCL_CACHE",
376d0e58ef5SRobert Mustacchi		"bit": 1,
377d0e58ef5SRobert Mustacchi		"rw": "Read-write",
378d0e58ef5SRobert Mustacchi		"description": "Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's die."
379d0e58ef5SRobert Mustacchi	}, {
380d0e58ef5SRobert Mustacchi		"name": "MABRESP_LCL_L2",
381d0e58ef5SRobert Mustacchi		"bit": 0,
382d0e58ef5SRobert Mustacchi		"rw": "Read-write",
383d0e58ef5SRobert Mustacchi		"description": "Local L2 hit."
384d0e58ef5SRobert Mustacchi	} ]
385d0e58ef5SRobert Mustacchi},
386d0e58ef5SRobert Mustacchi{
387d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsHwPfDcFills",
388d0e58ef5SRobert Mustacchi	"name": "LsHwPfDcFills",
389d0e58ef5SRobert Mustacchi	"code": "0x05A",
390d0e58ef5SRobert Mustacchi	"summary": "Hardware Prefetch Data Cache Fills",
391*31aa6202SRobert Mustacchi	"description": "Hardware Prefetch Data Cache Fills by Data Source.",
392d0e58ef5SRobert Mustacchi	"units": [ {
393d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_RMT_DRAM",
394d0e58ef5SRobert Mustacchi		"bit": 6,
395d0e58ef5SRobert Mustacchi		"rw": "Read-write",
396d0e58ef5SRobert Mustacchi		"description": "DRAM or IO from different die."
397d0e58ef5SRobert Mustacchi	}, {
398d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_RMT_CACHE",
399d0e58ef5SRobert Mustacchi		"bit": 4,
400d0e58ef5SRobert Mustacchi		"rw": "Read-write",
401*31aa6202SRobert Mustacchi		"description": "Hit in cache; Remote CCX and the address's Home Nodeis on a different die."
402d0e58ef5SRobert Mustacchi	}, {
403d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_LCL_DRAM",
404d0e58ef5SRobert Mustacchi		"bit": 3,
405d0e58ef5SRobert Mustacchi		"rw": "Read-write",
406d0e58ef5SRobert Mustacchi		"description": "DRAM or IO from this thread's die."
407d0e58ef5SRobert Mustacchi	}, {
408d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_LCL_CACHE",
409d0e58ef5SRobert Mustacchi		"bit": 1,
410d0e58ef5SRobert Mustacchi		"rw": "Read-write",
411*31aa6202SRobert Mustacchi		"description": "Hit in cache; local CCX (not Local L2), or Remote CCXand the address's Home Node is on this thread's die."
412d0e58ef5SRobert Mustacchi	}, {
413d0e58ef5SRobert Mustacchi		"name": "MABRESP_LCL_L2",
414d0e58ef5SRobert Mustacchi		"bit": 0,
415d0e58ef5SRobert Mustacchi		"rw": "Read-write",
416d0e58ef5SRobert Mustacchi		"description": "Local L2 hit."
417d0e58ef5SRobert Mustacchi	} ]
418d0e58ef5SRobert Mustacchi},
419d0e58ef5SRobert Mustacchi{
420d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsNotHaltedCyc",
421d0e58ef5SRobert Mustacchi	"name": "LsNotHaltedCyc",
422d0e58ef5SRobert Mustacchi	"code": "0x076",
423d0e58ef5SRobert Mustacchi	"summary": "Cycles not in Halt"
424d0e58ef5SRobert Mustacchi},
425d0e58ef5SRobert Mustacchi{
426*31aa6202SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsTlbFlush",
427*31aa6202SRobert Mustacchi	"name": "LsTlbFlush",
428*31aa6202SRobert Mustacchi	"code": "0x078",
429*31aa6202SRobert Mustacchi	"summary": "All TLB Flushes"
430d0e58ef5SRobert Mustacchi},
431d0e58ef5SRobert Mustacchi{
432d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::IcCacheFillL2",
433d0e58ef5SRobert Mustacchi	"name": "IcCacheFillL2",
434d0e58ef5SRobert Mustacchi	"code": "0x082",
435d0e58ef5SRobert Mustacchi	"summary": "Instruction Cache Refills from L2",
436d0e58ef5SRobert Mustacchi	"description": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
437d0e58ef5SRobert Mustacchi},
438d0e58ef5SRobert Mustacchi{
439d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::IcCacheFillSys",
440d0e58ef5SRobert Mustacchi	"name": "IcCacheFillSys",
441d0e58ef5SRobert Mustacchi	"code": "0x083",
442d0e58ef5SRobert Mustacchi	"summary": "Instruction Cache Refills from System",
443d0e58ef5SRobert Mustacchi	"description": "The number of 64 byte instruction cache line fulfilled from system memory or another cache."
444d0e58ef5SRobert Mustacchi},
445d0e58ef5SRobert Mustacchi{
446*31aa6202SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::BpL1TlbMissL2TlbHit",
447*31aa6202SRobert Mustacchi	"name": "BpL1TlbMissL2TlbHit",
448d0e58ef5SRobert Mustacchi	"code": "0x084",
449d0e58ef5SRobert Mustacchi	"summary": "L1 ITLB Miss, L2 ITLB Hit",
450d0e58ef5SRobert Mustacchi	"description": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
451d0e58ef5SRobert Mustacchi},
452d0e58ef5SRobert Mustacchi{
453*31aa6202SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::BpL1TlbMissL2TlbMiss",
454*31aa6202SRobert Mustacchi	"name": "BpL1TlbMissL2TlbMiss",
455d0e58ef5SRobert Mustacchi	"code": "0x085",
456d0e58ef5SRobert Mustacchi	"summary": "L1 ITLB Miss, L2 ITLB Miss",
457*31aa6202SRobert Mustacchi	"description": "The number of instruction fetches that miss in both the L1 and L2 TLBs.",
458d0e58ef5SRobert Mustacchi	"units": [ {
459*31aa6202SRobert Mustacchi		"name": "IF1G",
460d0e58ef5SRobert Mustacchi		"bit": 2,
461*31aa6202SRobert Mustacchi		"rw": "Read-write",
462*31aa6202SRobert Mustacchi		"description": "Instruction fetches to a 1 GB page."
463d0e58ef5SRobert Mustacchi	}, {
464*31aa6202SRobert Mustacchi		"name": "IF2M",
465d0e58ef5SRobert Mustacchi		"bit": 1,
466d0e58ef5SRobert Mustacchi		"rw": "Read-write",
467*31aa6202SRobert Mustacchi		"description": "Instruction fetches to a 2 MB page."
468d0e58ef5SRobert Mustacchi	}, {
469*31aa6202SRobert Mustacchi		"name": "IF4K",
470d0e58ef5SRobert Mustacchi		"bit": 0,
471d0e58ef5SRobert Mustacchi		"rw": "Read-write",
472*31aa6202SRobert Mustacchi		"description": "Instruction fetches to a 4 KB page."
473d0e58ef5SRobert Mustacchi	} ]
474d0e58ef5SRobert Mustacchi},
475d0e58ef5SRobert Mustacchi{
476d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::BpL1BTBCorrect",
477d0e58ef5SRobert Mustacchi	"name": "BpL1BTBCorrect",
478d0e58ef5SRobert Mustacchi	"code": "0x08A",
479*31aa6202SRobert Mustacchi	"summary": "L1 Branch Prediction Overrides Existing Prediction (speculative)"
480d0e58ef5SRobert Mustacchi},
481d0e58ef5SRobert Mustacchi{
482d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::BpL2BTBCorrect",
483d0e58ef5SRobert Mustacchi	"name": "BpL2BTBCorrect",
484d0e58ef5SRobert Mustacchi	"code": "0x08B",
485*31aa6202SRobert Mustacchi	"summary": "L2 Branch Prediction Overrides Existing Prediction (speculative)"
486*31aa6202SRobert Mustacchi},
487*31aa6202SRobert Mustacchi{
488*31aa6202SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::BpDynIndPred",
489*31aa6202SRobert Mustacchi	"name": "BpDynIndPred",
490*31aa6202SRobert Mustacchi	"code": "0x08E",
491*31aa6202SRobert Mustacchi	"summary": "Dynamic Indirect Predictions",
492*31aa6202SRobert Mustacchi	"description": "Indirect Branch Prediction for potential multi-target branch (speculative)"
493d0e58ef5SRobert Mustacchi},
494d0e58ef5SRobert Mustacchi{
495*31aa6202SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::BpDeReDirect",
496*31aa6202SRobert Mustacchi	"name": "BpDeReDirect",
497*31aa6202SRobert Mustacchi	"code": "0x091",
498*31aa6202SRobert Mustacchi	"summary": "Decoder Overrides Existing Branch Prediction (speculative)"
499*31aa6202SRobert Mustacchi},
500*31aa6202SRobert Mustacchi{
501*31aa6202SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::BpL1TlbFetchHit",
502*31aa6202SRobert Mustacchi	"name": "BpL1TlbFetchHit",
503*31aa6202SRobert Mustacchi	"code": "0x094",
504*31aa6202SRobert Mustacchi	"summary": "ITLB Instruction Fetch Hits",
505*31aa6202SRobert Mustacchi	"description": "The number of instruction fetches that hit in the L1 ITLB.",
506d0e58ef5SRobert Mustacchi	"units": [ {
507*31aa6202SRobert Mustacchi		"name": "IF1G",
508*31aa6202SRobert Mustacchi		"bit": 2,
509*31aa6202SRobert Mustacchi		"rw": "Read-write",
510*31aa6202SRobert Mustacchi		"description": "Instruction fetches to a 1 GB page."
511*31aa6202SRobert Mustacchi	}, {
512*31aa6202SRobert Mustacchi		"name": "IF2M",
513d0e58ef5SRobert Mustacchi		"bit": 1,
514d0e58ef5SRobert Mustacchi		"rw": "Read-write",
515*31aa6202SRobert Mustacchi		"description": "Instruction fetches to a 2 MB page."
516d0e58ef5SRobert Mustacchi	}, {
517*31aa6202SRobert Mustacchi		"name": "IF4K",
518d0e58ef5SRobert Mustacchi		"bit": 0,
519d0e58ef5SRobert Mustacchi		"rw": "Read-write",
520*31aa6202SRobert Mustacchi		"description": "Instruction fetches to a 4 KB page."
521d0e58ef5SRobert Mustacchi	} ]
522d0e58ef5SRobert Mustacchi},
523d0e58ef5SRobert Mustacchi{
524*31aa6202SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::DeDisUopQueueEmptyDi0",
525*31aa6202SRobert Mustacchi	"name": "DeDisUopQueueEmptyDi0",
526*31aa6202SRobert Mustacchi	"code": "0x0A9",
527*31aa6202SRobert Mustacchi	"summary": "Micro-Op Queue Empty",
528*31aa6202SRobert Mustacchi	"description": "Cycles where the Micro-Op Queue is empty."
529d0e58ef5SRobert Mustacchi},
530d0e58ef5SRobert Mustacchi{
531*31aa6202SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::DeDisUopsFromDecoder",
532*31aa6202SRobert Mustacchi	"name": "DeDisUopsFromDecoder",
533*31aa6202SRobert Mustacchi	"code": "0x0AA",
534*31aa6202SRobert Mustacchi	"summary": "UOps Dispatched From Decoder",
535*31aa6202SRobert Mustacchi	"description": "Ops dispatched from either the decoders, OpCache or both.",
536d0e58ef5SRobert Mustacchi	"units": [ {
537*31aa6202SRobert Mustacchi		"name": "OpCacheDispatched",
538d0e58ef5SRobert Mustacchi		"bit": 1,
539d0e58ef5SRobert Mustacchi		"rw": "Read-write",
540*31aa6202SRobert Mustacchi		"description": "Count of dispatched Ops from OpCache."
541d0e58ef5SRobert Mustacchi	}, {
542*31aa6202SRobert Mustacchi		"name": "DecoderDispatched",
543d0e58ef5SRobert Mustacchi		"bit": 0,
544d0e58ef5SRobert Mustacchi		"rw": "Read-write",
545*31aa6202SRobert Mustacchi		"description": "Count of dispatched Ops from Decoder."
546*31aa6202SRobert Mustacchi	} ]
547*31aa6202SRobert Mustacchi},
548*31aa6202SRobert Mustacchi{
549*31aa6202SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::DeDisDispatchTokenStalls1",
550*31aa6202SRobert Mustacchi	"name": "DeDisDispatchTokenStalls1",
551*31aa6202SRobert Mustacchi	"code": "0x0AE",
552*31aa6202SRobert Mustacchi	"summary": "Dispatch Resource Stall Cycles 1",
553*31aa6202SRobert Mustacchi	"description": "Cycles where a dispatch group is valid but does not get dispatched due to a Token Stall.",
554*31aa6202SRobert Mustacchi	"units": [ {
555*31aa6202SRobert Mustacchi		"name": "FPMiscRsrcStall",
556*31aa6202SRobert Mustacchi		"bit": 7,
557*31aa6202SRobert Mustacchi		"rw": "Read-write",
558*31aa6202SRobert Mustacchi		"description": "FP Miscellaneous resource unavailable. Applies to the recovery of mispredicts with FP ops."
559*31aa6202SRobert Mustacchi	}, {
560*31aa6202SRobert Mustacchi		"name": "FPSchRsrcStall",
561*31aa6202SRobert Mustacchi		"bit": 6,
562*31aa6202SRobert Mustacchi		"rw": "Read-write",
563*31aa6202SRobert Mustacchi		"description": "FP scheduler resource stall. Applies to ops that use the FP scheduler."
564*31aa6202SRobert Mustacchi	}, {
565*31aa6202SRobert Mustacchi		"name": "FpRegFileRsrcStall",
566*31aa6202SRobert Mustacchi		"bit": 5,
567*31aa6202SRobert Mustacchi		"rw": "Read-write",
568*31aa6202SRobert Mustacchi		"description": "floating point register file resource stall. Applies to all FP ops that have a destination register."
569*31aa6202SRobert Mustacchi	}, {
570*31aa6202SRobert Mustacchi		"name": "TakenBrnchBufferRsrc",
571*31aa6202SRobert Mustacchi		"bit": 4,
572*31aa6202SRobert Mustacchi		"rw": "Read-write",
573*31aa6202SRobert Mustacchi		"description": "taken branch buffer resource stall."
574*31aa6202SRobert Mustacchi	}, {
575*31aa6202SRobert Mustacchi		"name": "IntSchedulerMiscRsrcStall",
576*31aa6202SRobert Mustacchi		"bit": 3,
577*31aa6202SRobert Mustacchi		"rw": "Read-write",
578*31aa6202SRobert Mustacchi		"description": "Integer Scheduler miscellaneous resource stall."
579*31aa6202SRobert Mustacchi	}, {
580*31aa6202SRobert Mustacchi		"name": "StoreQueueRsrcStall",
581*31aa6202SRobert Mustacchi		"bit": 2,
582*31aa6202SRobert Mustacchi		"rw": "Read-write",
583*31aa6202SRobert Mustacchi		"description": "Store Queue resource stall. Applies to all ops with store semantics."
584*31aa6202SRobert Mustacchi	}, {
585*31aa6202SRobert Mustacchi		"name": "LoadQueueRsrcStall",
586*31aa6202SRobert Mustacchi		"bit": 1,
587*31aa6202SRobert Mustacchi		"rw": "Read-write",
588*31aa6202SRobert Mustacchi		"description": "Load Queue resource stall. Applies to all ops with load semantics."
589*31aa6202SRobert Mustacchi	}, {
590*31aa6202SRobert Mustacchi		"name": "IntPhyRegFileRsrcStall",
591*31aa6202SRobert Mustacchi		"bit": 0,
592*31aa6202SRobert Mustacchi		"rw": "Read-write",
593*31aa6202SRobert Mustacchi		"description": "Integer Physical Register File resource stall. Integer Physical Register File, applies to all ops that have an integer destination register."
594d0e58ef5SRobert Mustacchi	} ]
595d0e58ef5SRobert Mustacchi},
596d0e58ef5SRobert Mustacchi{
597d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::DeDisDispatchTokenStalls0",
598d0e58ef5SRobert Mustacchi	"name": "DeDisDispatchTokenStalls0",
599d0e58ef5SRobert Mustacchi	"code": "0x0AF",
600*31aa6202SRobert Mustacchi	"summary": "Dispatch Resource Stall Cycles 0",
601d0e58ef5SRobert Mustacchi	"description": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall.",
602d0e58ef5SRobert Mustacchi	"units": [ {
603*31aa6202SRobert Mustacchi		"name": "ScAguDispatchStall",
604d0e58ef5SRobert Mustacchi		"bit": 6,
605d0e58ef5SRobert Mustacchi		"rw": "Read-write",
606*31aa6202SRobert Mustacchi		"description": "SC AGU dispatch stall."
607d0e58ef5SRobert Mustacchi	}, {
608*31aa6202SRobert Mustacchi		"name": "RetireTokenStall",
609d0e58ef5SRobert Mustacchi		"bit": 5,
610d0e58ef5SRobert Mustacchi		"rw": "Read-write",
611*31aa6202SRobert Mustacchi		"description": "RETIRE Tokens unavailable."
612d0e58ef5SRobert Mustacchi	}, {
613*31aa6202SRobert Mustacchi		"name": "AGSQTokenStall",
614d0e58ef5SRobert Mustacchi		"bit": 4,
615d0e58ef5SRobert Mustacchi		"rw": "Read-write",
616*31aa6202SRobert Mustacchi		"description": "AGSQ Tokens unavailable."
617d0e58ef5SRobert Mustacchi	}, {
618*31aa6202SRobert Mustacchi		"name": "ALUTokenStall",
619d0e58ef5SRobert Mustacchi		"bit": 3,
620*31aa6202SRobert Mustacchi		"rw": "Read-write",
621*31aa6202SRobert Mustacchi		"description": "ALU tokens total unavailable."
622d0e58ef5SRobert Mustacchi	}, {
623*31aa6202SRobert Mustacchi		"name": "ALSQ3_0_TokenStall",
624d0e58ef5SRobert Mustacchi		"bit": 2,
625*31aa6202SRobert Mustacchi		"rw": "Read-write"
626d0e58ef5SRobert Mustacchi	}, {
627*31aa6202SRobert Mustacchi		"name": "ALSQ2RsrcStall",
628d0e58ef5SRobert Mustacchi		"bit": 1,
629d0e58ef5SRobert Mustacchi		"rw": "Read-write",
630*31aa6202SRobert Mustacchi		"description": "ALSQ 2 Resources unavailable."
631d0e58ef5SRobert Mustacchi	}, {
632*31aa6202SRobert Mustacchi		"name": "ALSQ1RsrcStall",
633d0e58ef5SRobert Mustacchi		"bit": 0,
634d0e58ef5SRobert Mustacchi		"rw": "Read-write",
635*31aa6202SRobert Mustacchi		"description": "ALSQ 1 Resources unavailable."
636d0e58ef5SRobert Mustacchi	} ]
637d0e58ef5SRobert Mustacchi},
638d0e58ef5SRobert Mustacchi{
639d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetInstr",
640d0e58ef5SRobert Mustacchi	"name": "ExRetInstr",
641d0e58ef5SRobert Mustacchi	"code": "0x0C0",
642d0e58ef5SRobert Mustacchi	"summary": "Retired Instructions"
643d0e58ef5SRobert Mustacchi},
644d0e58ef5SRobert Mustacchi{
645d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetCops",
646d0e58ef5SRobert Mustacchi	"name": "ExRetCops",
647d0e58ef5SRobert Mustacchi	"code": "0x0C1",
648d0e58ef5SRobert Mustacchi	"summary": "Retired Uops",
649*31aa6202SRobert Mustacchi	"description": "The number of micro-ops retired. This count includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 8."
650d0e58ef5SRobert Mustacchi},
651d0e58ef5SRobert Mustacchi{
652d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrn",
653d0e58ef5SRobert Mustacchi	"name": "ExRetBrn",
654d0e58ef5SRobert Mustacchi	"code": "0x0C2",
655d0e58ef5SRobert Mustacchi	"summary": "Retired Branch Instructions",
656d0e58ef5SRobert Mustacchi	"description": "The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
657d0e58ef5SRobert Mustacchi},
658d0e58ef5SRobert Mustacchi{
659d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrnMisp",
660d0e58ef5SRobert Mustacchi	"name": "ExRetBrnMisp",
661d0e58ef5SRobert Mustacchi	"code": "0x0C3",
662d0e58ef5SRobert Mustacchi	"summary": "Retired Branch Instructions Mispredicted",
663d0e58ef5SRobert Mustacchi	"description": "The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts)."
664d0e58ef5SRobert Mustacchi},
665d0e58ef5SRobert Mustacchi{
666d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrnTkn",
667d0e58ef5SRobert Mustacchi	"name": "ExRetBrnTkn",
668d0e58ef5SRobert Mustacchi	"code": "0x0C4",
669d0e58ef5SRobert Mustacchi	"summary": "Retired Taken Branch Instructions",
670d0e58ef5SRobert Mustacchi	"description": "The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
671d0e58ef5SRobert Mustacchi},
672d0e58ef5SRobert Mustacchi{
673d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrnTknMisp",
674d0e58ef5SRobert Mustacchi	"name": "ExRetBrnTknMisp",
675d0e58ef5SRobert Mustacchi	"code": "0x0C5",
676d0e58ef5SRobert Mustacchi	"summary": "Retired Taken Branch Instructions Mispredicted",
677d0e58ef5SRobert Mustacchi	"description": "The number of retired taken branch instructions that were mispredicted."
678d0e58ef5SRobert Mustacchi},
679d0e58ef5SRobert Mustacchi{
680d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrnFar",
681d0e58ef5SRobert Mustacchi	"name": "ExRetBrnFar",
682d0e58ef5SRobert Mustacchi	"code": "0x0C6",
683d0e58ef5SRobert Mustacchi	"summary": "Retired Far Control Transfers",
684d0e58ef5SRobert Mustacchi	"description": "The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction."
685d0e58ef5SRobert Mustacchi},
686d0e58ef5SRobert Mustacchi{
687d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetNearRet",
688d0e58ef5SRobert Mustacchi	"name": "ExRetNearRet",
689d0e58ef5SRobert Mustacchi	"code": "0x0C8",
690d0e58ef5SRobert Mustacchi	"summary": "Retired Near Returns",
691d0e58ef5SRobert Mustacchi	"description": "The number of near return instructions (RET or RET Iw) retired."
692d0e58ef5SRobert Mustacchi},
693d0e58ef5SRobert Mustacchi{
694d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetNearRetMispred",
695d0e58ef5SRobert Mustacchi	"name": "ExRetNearRetMispred",
696d0e58ef5SRobert Mustacchi	"code": "0x0C9",
697d0e58ef5SRobert Mustacchi	"summary": "Retired Near Returns Mispredicted",
698*31aa6202SRobert Mustacchi	"description": "The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredictincurs the same penalty as a mispredicted conditional branch instruction."
699d0e58ef5SRobert Mustacchi},
700d0e58ef5SRobert Mustacchi{
701d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrnIndMisp",
702d0e58ef5SRobert Mustacchi	"name": "ExRetBrnIndMisp",
703d0e58ef5SRobert Mustacchi	"code": "0x0CA",
704*31aa6202SRobert Mustacchi	"summary": "Retired Indirect Branch Instructions Mispredicted",
705*31aa6202SRobert Mustacchi	"description": "The number of indirect branches retired that were not correctly predicted. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction. Note that only EX mispredicts are counted."
706d0e58ef5SRobert Mustacchi},
707d0e58ef5SRobert Mustacchi{
708d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetMmxFpInstr",
709d0e58ef5SRobert Mustacchi	"name": "ExRetMmxFpInstr",
710d0e58ef5SRobert Mustacchi	"code": "0x0CB",
711*31aa6202SRobert Mustacchi	"summary": "Retired MMX/FP Instructions",
712*31aa6202SRobert Mustacchi	"description": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPs.",
713d0e58ef5SRobert Mustacchi	"units": [ {
714d0e58ef5SRobert Mustacchi		"name": "SseInstr",
715d0e58ef5SRobert Mustacchi		"bit": 2,
716d0e58ef5SRobert Mustacchi		"rw": "Read-write",
717d0e58ef5SRobert Mustacchi		"description": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX)."
718d0e58ef5SRobert Mustacchi	}, {
719d0e58ef5SRobert Mustacchi		"name": "MmxInstr",
720d0e58ef5SRobert Mustacchi		"bit": 1,
721d0e58ef5SRobert Mustacchi		"rw": "Read-write",
722d0e58ef5SRobert Mustacchi		"description": "MMX instructions."
723d0e58ef5SRobert Mustacchi	}, {
724d0e58ef5SRobert Mustacchi		"name": "X87Instr",
725d0e58ef5SRobert Mustacchi		"bit": 0,
726d0e58ef5SRobert Mustacchi		"rw": "Read-write",
727*31aa6202SRobert Mustacchi		"description": "x87 instructions."
728d0e58ef5SRobert Mustacchi	} ]
729d0e58ef5SRobert Mustacchi},
730d0e58ef5SRobert Mustacchi{
731d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetCond",
732d0e58ef5SRobert Mustacchi	"name": "ExRetCond",
733d0e58ef5SRobert Mustacchi	"code": "0x0D1",
734d0e58ef5SRobert Mustacchi	"summary": "Retired Conditional Branch Instructions"
735d0e58ef5SRobert Mustacchi},
736d0e58ef5SRobert Mustacchi{
737d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExDivBusy",
738d0e58ef5SRobert Mustacchi	"name": "ExDivBusy",
739d0e58ef5SRobert Mustacchi	"code": "0x0D3",
740d0e58ef5SRobert Mustacchi	"summary": "Div Cycles Busy count"
741d0e58ef5SRobert Mustacchi},
742d0e58ef5SRobert Mustacchi{
743d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExDivCount",
744d0e58ef5SRobert Mustacchi	"name": "ExDivCount",
745d0e58ef5SRobert Mustacchi	"code": "0x0D4",
746d0e58ef5SRobert Mustacchi	"summary": "Div Op Count"
747d0e58ef5SRobert Mustacchi},
748d0e58ef5SRobert Mustacchi{
749d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExTaggedIbsOps",
750d0e58ef5SRobert Mustacchi	"name": "ExTaggedIbsOps",
751d0e58ef5SRobert Mustacchi	"code": "0x1CF",
752d0e58ef5SRobert Mustacchi	"summary": "Tagged IBS Ops",
753d0e58ef5SRobert Mustacchi	"units": [ {
754d0e58ef5SRobert Mustacchi		"name": "IbsCountRollover",
755d0e58ef5SRobert Mustacchi		"bit": 2,
756d0e58ef5SRobert Mustacchi		"rw": "Read-write",
757d0e58ef5SRobert Mustacchi		"description": "Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired."
758d0e58ef5SRobert Mustacchi	}, {
759d0e58ef5SRobert Mustacchi		"name": "IbsTaggedOpsRet",
760d0e58ef5SRobert Mustacchi		"bit": 1,
761d0e58ef5SRobert Mustacchi		"rw": "Read-write",
762*31aa6202SRobert Mustacchi		"description": "Number of Ops tagged by IBS that retired."
763d0e58ef5SRobert Mustacchi	}, {
764d0e58ef5SRobert Mustacchi		"name": "IbsTaggedOps",
765d0e58ef5SRobert Mustacchi		"bit": 0,
766d0e58ef5SRobert Mustacchi		"rw": "Read-write",
767*31aa6202SRobert Mustacchi		"description": "Number of Ops tagged by IBS."
768d0e58ef5SRobert Mustacchi	} ]
769*31aa6202SRobert Mustacchi},
770*31aa6202SRobert Mustacchi{
771d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetFusBrnchInst",
772d0e58ef5SRobert Mustacchi	"name": "ExRetFusBrnchInst",
773d0e58ef5SRobert Mustacchi	"code": "0x1D0",
774d0e58ef5SRobert Mustacchi	"summary": "Retired Fused Branch Instructions",
775*31aa6202SRobert Mustacchi	"description": "The number of fuse-branch instructions retired per cycle. The number of events logged per cycle can vary from 0-8."
776d0e58ef5SRobert Mustacchi},
777d0e58ef5SRobert Mustacchi{
778d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::L2RequestG1",
779d0e58ef5SRobert Mustacchi	"name": "L2RequestG1",
780d0e58ef5SRobert Mustacchi	"code": "0x060",
781d0e58ef5SRobert Mustacchi	"summary": "Requests to L2 Group1",
782*31aa6202SRobert Mustacchi	"description": "All L2 Cache Requests (Breakdown 1 - Common).",
783d0e58ef5SRobert Mustacchi	"units": [ {
784d0e58ef5SRobert Mustacchi		"name": "RdBlkL",
785d0e58ef5SRobert Mustacchi		"bit": 7,
786*31aa6202SRobert Mustacchi		"rw": "Read-write",
787*31aa6202SRobert Mustacchi		"description": "Data Cache Reads (including hardware and software prefetch)."
788d0e58ef5SRobert Mustacchi	}, {
789d0e58ef5SRobert Mustacchi		"name": "RdBlkX",
790d0e58ef5SRobert Mustacchi		"bit": 6,
791*31aa6202SRobert Mustacchi		"rw": "Read-write",
792*31aa6202SRobert Mustacchi		"description": "Data Cache Stores."
793d0e58ef5SRobert Mustacchi	}, {
794d0e58ef5SRobert Mustacchi		"name": "LsRdBlkC_S",
795d0e58ef5SRobert Mustacchi		"bit": 5,
796*31aa6202SRobert Mustacchi		"rw": "Read-write",
797*31aa6202SRobert Mustacchi		"description": "Data Cache Shared Reads."
798d0e58ef5SRobert Mustacchi	}, {
799d0e58ef5SRobert Mustacchi		"name": "CacheableIcRead",
800d0e58ef5SRobert Mustacchi		"bit": 4,
801*31aa6202SRobert Mustacchi		"rw": "Read-write",
802*31aa6202SRobert Mustacchi		"description": "Instruction Cache Reads."
803d0e58ef5SRobert Mustacchi	}, {
804d0e58ef5SRobert Mustacchi		"name": "ChangeToX",
805d0e58ef5SRobert Mustacchi		"bit": 3,
806*31aa6202SRobert Mustacchi		"rw": "Read-write",
807*31aa6202SRobert Mustacchi		"description": "Data Cache State Change Requests. Request change to writable, check L2 for current state."
808d0e58ef5SRobert Mustacchi	}, {
809*31aa6202SRobert Mustacchi		"name": "PrefetchL2Cmd",
810d0e58ef5SRobert Mustacchi		"bit": 2,
811*31aa6202SRobert Mustacchi		"rw": "Read-write"
812d0e58ef5SRobert Mustacchi	}, {
813d0e58ef5SRobert Mustacchi		"name": "L2HwPf",
814d0e58ef5SRobert Mustacchi		"bit": 1,
815*31aa6202SRobert Mustacchi		"rw": "Read-write",
816*31aa6202SRobert Mustacchi		"description": "L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/miss broken out in a separate perfmon event."
817d0e58ef5SRobert Mustacchi	}, {
818*31aa6202SRobert Mustacchi		"name": "Group2",
819d0e58ef5SRobert Mustacchi		"bit": 0,
820d0e58ef5SRobert Mustacchi		"rw": "Read-write",
821*31aa6202SRobert Mustacchi		"description": "Miscellaneous events covered in more detail by Core::X86::Pmc::Core::L2RequestG2 (PMCx061)."
822d0e58ef5SRobert Mustacchi	} ]
823*31aa6202SRobert Mustacchi},
824*31aa6202SRobert Mustacchi{
825d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::L2RequestG2",
826d0e58ef5SRobert Mustacchi	"name": "L2RequestG2",
827d0e58ef5SRobert Mustacchi	"code": "0x061",
828d0e58ef5SRobert Mustacchi	"summary": "Requests to L2 Group2",
829*31aa6202SRobert Mustacchi	"description": "All L2 Cache Requests (Breakdown 2 - Rare). ",
830d0e58ef5SRobert Mustacchi	"units": [ {
831d0e58ef5SRobert Mustacchi		"name": "Group1",
832d0e58ef5SRobert Mustacchi		"bit": 7,
833d0e58ef5SRobert Mustacchi		"rw": "Read-write",
834*31aa6202SRobert Mustacchi		"description": "Miscellaneous events covered in more detail by Core::X86::Pmc::Core::L2RequestG1 (PMCx060)."
835d0e58ef5SRobert Mustacchi	}, {
836d0e58ef5SRobert Mustacchi		"name": "LsRdSized",
837d0e58ef5SRobert Mustacchi		"bit": 6,
838d0e58ef5SRobert Mustacchi		"rw": "Read-write",
839*31aa6202SRobert Mustacchi		"description": "Data cache read sized."
840d0e58ef5SRobert Mustacchi	}, {
841d0e58ef5SRobert Mustacchi		"name": "LsRdSizedNC",
842d0e58ef5SRobert Mustacchi		"bit": 5,
843d0e58ef5SRobert Mustacchi		"rw": "Read-write",
844*31aa6202SRobert Mustacchi		"description": "Data cache read sized non-cacheable."
845d0e58ef5SRobert Mustacchi	}, {
846d0e58ef5SRobert Mustacchi		"name": "IcRdSized",
847d0e58ef5SRobert Mustacchi		"bit": 4,
848*31aa6202SRobert Mustacchi		"rw": "Read-write",
849*31aa6202SRobert Mustacchi		"description": "Instruction cache read sized."
850d0e58ef5SRobert Mustacchi	}, {
851d0e58ef5SRobert Mustacchi		"name": "IcRdSizedNC",
852d0e58ef5SRobert Mustacchi		"bit": 3,
853*31aa6202SRobert Mustacchi		"rw": "Read-write",
854*31aa6202SRobert Mustacchi		"description": "Instruction cache read sized non-cacheable."
855d0e58ef5SRobert Mustacchi	}, {
856d0e58ef5SRobert Mustacchi		"name": "SmcInval",
857d0e58ef5SRobert Mustacchi		"bit": 2,
858d0e58ef5SRobert Mustacchi		"rw": "Read-write",
859*31aa6202SRobert Mustacchi		"description": "Self-modifying code invalidates."
860d0e58ef5SRobert Mustacchi	}, {
861*31aa6202SRobert Mustacchi		"name": "BusLocksOriginator",
862d0e58ef5SRobert Mustacchi		"bit": 1,
863d0e58ef5SRobert Mustacchi		"rw": "Read-write",
864*31aa6202SRobert Mustacchi		"description": "Bus locks."
865d0e58ef5SRobert Mustacchi	}, {
866*31aa6202SRobert Mustacchi		"name": "BusLocksResponses",
867d0e58ef5SRobert Mustacchi		"bit": 0,
868d0e58ef5SRobert Mustacchi		"rw": "Read-write",
869*31aa6202SRobert Mustacchi		"description": "Bus Lock Response."
870d0e58ef5SRobert Mustacchi	} ]
871d0e58ef5SRobert Mustacchi},
872d0e58ef5SRobert Mustacchi{
873d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::L2CacheReqStat",
874d0e58ef5SRobert Mustacchi	"name": "L2CacheReqStat",
875d0e58ef5SRobert Mustacchi	"code": "0x064",
876d0e58ef5SRobert Mustacchi	"summary": "Core to L2 Cacheable Request Access Status",
877*31aa6202SRobert Mustacchi	"description": "L2 Cache Request Outcomes (not including L2 Prefetch).",
878d0e58ef5SRobert Mustacchi	"units": [ {
879d0e58ef5SRobert Mustacchi		"name": "LsRdBlkCS",
880d0e58ef5SRobert Mustacchi		"bit": 7,
881d0e58ef5SRobert Mustacchi		"rw": "Read-write",
882*31aa6202SRobert Mustacchi		"description": "Data Cache Shared Read Hit in L2."
883d0e58ef5SRobert Mustacchi	}, {
884d0e58ef5SRobert Mustacchi		"name": "LsRdBlkLHitX",
885d0e58ef5SRobert Mustacchi		"bit": 6,
886d0e58ef5SRobert Mustacchi		"rw": "Read-write",
887*31aa6202SRobert Mustacchi		"description": "Data Cache Read Hit in L2."
888d0e58ef5SRobert Mustacchi	}, {
889d0e58ef5SRobert Mustacchi		"name": "LsRdBlkLHitS",
890d0e58ef5SRobert Mustacchi		"bit": 5,
891d0e58ef5SRobert Mustacchi		"rw": "Read-write",
892*31aa6202SRobert Mustacchi		"description": "Data Cache Read Hit on Shared Line in L2."
893d0e58ef5SRobert Mustacchi	}, {
894d0e58ef5SRobert Mustacchi		"name": "LsRdBlkX",
895d0e58ef5SRobert Mustacchi		"bit": 4,
896d0e58ef5SRobert Mustacchi		"rw": "Read-write",
897*31aa6202SRobert Mustacchi		"description": "Data Cache Store or State Change Hit in L2."
898d0e58ef5SRobert Mustacchi	}, {
899d0e58ef5SRobert Mustacchi		"name": "LsRdBlkC",
900d0e58ef5SRobert Mustacchi		"bit": 3,
901d0e58ef5SRobert Mustacchi		"rw": "Read-write",
902*31aa6202SRobert Mustacchi		"description": "Data Cache Req Miss in L2 (all types)."
903d0e58ef5SRobert Mustacchi	}, {
904d0e58ef5SRobert Mustacchi		"name": "IcFillHitX",
905d0e58ef5SRobert Mustacchi		"bit": 2,
906d0e58ef5SRobert Mustacchi		"rw": "Read-write",
907*31aa6202SRobert Mustacchi		"description": "Instruction Cache Hit Modifiable Line in L2."
908d0e58ef5SRobert Mustacchi	}, {
909d0e58ef5SRobert Mustacchi		"name": "IcFillHitS",
910d0e58ef5SRobert Mustacchi		"bit": 1,
911d0e58ef5SRobert Mustacchi		"rw": "Read-write",
912*31aa6202SRobert Mustacchi		"description": "Instruction Cache Hit Clean Line in L2."
913d0e58ef5SRobert Mustacchi	}, {
914d0e58ef5SRobert Mustacchi		"name": "IcFillMiss",
915d0e58ef5SRobert Mustacchi		"bit": 0,
916d0e58ef5SRobert Mustacchi		"rw": "Read-write",
917*31aa6202SRobert Mustacchi		"description": "Instruction Cache Req Miss in L2."
918d0e58ef5SRobert Mustacchi	} ]
919d0e58ef5SRobert Mustacchi},
920d0e58ef5SRobert Mustacchi{
921*31aa6202SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::L2PfHitL2",
922*31aa6202SRobert Mustacchi	"name": "L2PfHitL2",
923*31aa6202SRobert Mustacchi	"code": "0x070",
924*31aa6202SRobert Mustacchi	"summary": "L2 Prefetch Hit in L2"
925*31aa6202SRobert Mustacchi},
926*31aa6202SRobert Mustacchi{
927*31aa6202SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::L2PfMissL2HitL2",
928*31aa6202SRobert Mustacchi	"name": "L2PfMissL2HitL2",
929*31aa6202SRobert Mustacchi	"code": "0x071",
930*31aa6202SRobert Mustacchi	"summary": "L2 Prefetcher Hits in L3",
931*31aa6202SRobert Mustacchi	"description": "Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3."
932*31aa6202SRobert Mustacchi},
933*31aa6202SRobert Mustacchi{
934*31aa6202SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::L2PfMissL2L3",
935*31aa6202SRobert Mustacchi	"name": "L2PfMissL2L3",
936*31aa6202SRobert Mustacchi	"code": "0x072",
937*31aa6202SRobert Mustacchi	"summary": "L2 Prefetcher Misses in L3",
938*31aa6202SRobert Mustacchi	"description": "Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches."
939d0e58ef5SRobert Mustacchi}
940d0e58ef5SRobert Mustacchi]