1d0e58ef5SRobert Mustacchi[
2d0e58ef5SRobert Mustacchi{
3d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::FpuPipeAssignment",
4d0e58ef5SRobert Mustacchi	"name": "FpuPipeAssignment",
5d0e58ef5SRobert Mustacchi	"code": "0x000",
6d0e58ef5SRobert Mustacchi	"summary": "FPU Pipe Assignment",
7d0e58ef5SRobert Mustacchi	"description": "The number of operations (uOps) and dual-pipeuOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMXTM, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. (See Core::X86::Pmc::Core::ExRetMmxFpInstr). Since this event includes non- numeric operations it is not suitable for measuring MFLOPS.",
8d0e58ef5SRobert Mustacchi	"units": [ {
9d0e58ef5SRobert Mustacchi		"name": "Dual3",
10d0e58ef5SRobert Mustacchi		"bit": 7,
11d0e58ef5SRobert Mustacchi		"rw": "Read-only",
12d0e58ef5SRobert Mustacchi		"description": "Total number multi-pipe uOps assigned to Pipe 3"
13d0e58ef5SRobert Mustacchi	}, {
14d0e58ef5SRobert Mustacchi		"name": "Dual2",
15d0e58ef5SRobert Mustacchi		"bit": 6,
16d0e58ef5SRobert Mustacchi		"rw": "Read-only",
17d0e58ef5SRobert Mustacchi		"description": "Total number multi-pipe uOps assigned to Pipe 2"
18d0e58ef5SRobert Mustacchi	}, {
19d0e58ef5SRobert Mustacchi		"name": "Dual1",
20d0e58ef5SRobert Mustacchi		"bit": 5,
21d0e58ef5SRobert Mustacchi		"rw": "Read-only",
22d0e58ef5SRobert Mustacchi		"description": "Total number multi-pipe uOps assigned to Pipe 1"
23d0e58ef5SRobert Mustacchi	}, {
24d0e58ef5SRobert Mustacchi		"name": "Dual0",
25d0e58ef5SRobert Mustacchi		"bit": 4,
26d0e58ef5SRobert Mustacchi		"rw": "Read-only",
27d0e58ef5SRobert Mustacchi		"description": "Total number multi-pipe uOps assigned to Pipe 0"
28d0e58ef5SRobert Mustacchi	}, {
29d0e58ef5SRobert Mustacchi		"name": "Total3",
30d0e58ef5SRobert Mustacchi		"bit": 3,
31d0e58ef5SRobert Mustacchi		"rw": "Read-only",
32d0e58ef5SRobert Mustacchi		"description": "Total number uOps assigned to Pipe 3"
33d0e58ef5SRobert Mustacchi	}, {
34d0e58ef5SRobert Mustacchi		"name": "Total2",
35d0e58ef5SRobert Mustacchi		"bit": 2,
36d0e58ef5SRobert Mustacchi		"rw": "Read-only",
37d0e58ef5SRobert Mustacchi		"description": "Total number uOps assigned to Pipe 2"
38d0e58ef5SRobert Mustacchi	}, {
39d0e58ef5SRobert Mustacchi		"name": "Total1",
40d0e58ef5SRobert Mustacchi		"bit": 1,
41d0e58ef5SRobert Mustacchi		"rw": "Read-only",
42d0e58ef5SRobert Mustacchi		"description": "Total number uOps assigned to Pipe 1"
43d0e58ef5SRobert Mustacchi	}, {
44d0e58ef5SRobert Mustacchi		"name": "Total0",
45d0e58ef5SRobert Mustacchi		"bit": 0,
46d0e58ef5SRobert Mustacchi		"rw": "Read-only",
47d0e58ef5SRobert Mustacchi		"description": "Total number uOps assigned to Pipe 0"
48d0e58ef5SRobert Mustacchi	} ]
49d0e58ef5SRobert Mustacchi},
50d0e58ef5SRobert Mustacchi{
51d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::FpSchedEmpty",
52d0e58ef5SRobert Mustacchi	"name": "FpSchedEmpty",
53d0e58ef5SRobert Mustacchi	"code": "0x001",
54d0e58ef5SRobert Mustacchi	"summary": "FP Scheduler Empty",
55d0e58ef5SRobert Mustacchi	"description": "This is a speculative event. The number of cycles in which the FPU scheduler is empty. Note that some Ops like FP loads bypass the scheduler. Invert this (Core::X86::Msr::PERF_CTL[Inv] == 1) to count cycles in which at least one FPU operation is present in the FPU."
56d0e58ef5SRobert Mustacchi},
57d0e58ef5SRobert Mustacchi{
58d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::FpRetx87FpOps",
59d0e58ef5SRobert Mustacchi	"name": "FpRetx87FpOps",
60d0e58ef5SRobert Mustacchi	"code": "0x002",
61d0e58ef5SRobert Mustacchi	"summary": "Retired x87 Floating Point Operations",
62d0e58ef5SRobert Mustacchi	"description": "The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8.",
63d0e58ef5SRobert Mustacchi	"units": [
64d0e58ef5SRobert Mustacchi		{
65d0e58ef5SRobert Mustacchi		"name": "DivSqrROps",
66d0e58ef5SRobert Mustacchi		"bit": 2,
67d0e58ef5SRobert Mustacchi		"rw": "Read-write",
68d0e58ef5SRobert Mustacchi		"description": "Divide and square root Ops"
69d0e58ef5SRobert Mustacchi	}, {
70d0e58ef5SRobert Mustacchi		"name": "MulOps",
71d0e58ef5SRobert Mustacchi		"bit": 1,
72d0e58ef5SRobert Mustacchi		"rw": "Read-write",
73d0e58ef5SRobert Mustacchi		"description": "Multiply Ops"
74d0e58ef5SRobert Mustacchi	}, {
75d0e58ef5SRobert Mustacchi		"name": "AddSubOps",
76d0e58ef5SRobert Mustacchi		"bit": 0,
77d0e58ef5SRobert Mustacchi		"rw": "Read-write",
78d0e58ef5SRobert Mustacchi		"description": " Add/subtract Ops"
79d0e58ef5SRobert Mustacchi	} ]
80d0e58ef5SRobert Mustacchi},
81d0e58ef5SRobert Mustacchi{
82d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::FpRetSseAvxOps",
83d0e58ef5SRobert Mustacchi	"name": "FpRetSseAvxOps",
84d0e58ef5SRobert Mustacchi	"code": "0x003",
85d0e58ef5SRobert Mustacchi	"summary": "Retired SSE/AVX Operations",
86d0e58ef5SRobert Mustacchi	"description": "This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. See 2.1.11.2 [Large Increment per Cycle Events]",
87d0e58ef5SRobert Mustacchi	"units": [
88d0e58ef5SRobert Mustacchi		{
89d0e58ef5SRobert Mustacchi		"name": "DpMultAddFlops",
90d0e58ef5SRobert Mustacchi		"bit": 7,
91d0e58ef5SRobert Mustacchi		"rw": "Read-write",
92d0e58ef5SRobert Mustacchi		"description": "Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS."
93d0e58ef5SRobert Mustacchi	}, {
94d0e58ef5SRobert Mustacchi		"name": "DpDivFlops",
95d0e58ef5SRobert Mustacchi		"bit": 6,
96d0e58ef5SRobert Mustacchi		"rw": "Read-write",
97d0e58ef5SRobert Mustacchi		"description": "Double precision divide/square root FLOPS."
98d0e58ef5SRobert Mustacchi	}, {
99d0e58ef5SRobert Mustacchi		"name": "DpMultFlops",
100d0e58ef5SRobert Mustacchi		"bit": 5,
101d0e58ef5SRobert Mustacchi		"rw": "Read-write",
102d0e58ef5SRobert Mustacchi		"description": "Double precision multiply FLOPS."
103d0e58ef5SRobert Mustacchi	}, {
104d0e58ef5SRobert Mustacchi		"name": "DpAddSubFlops",
105d0e58ef5SRobert Mustacchi		"bit": 4,
106d0e58ef5SRobert Mustacchi		"rw": "Read-write",
107d0e58ef5SRobert Mustacchi		"description": "Double precision add/subtract FLOPS."
108d0e58ef5SRobert Mustacchi	}, {
109d0e58ef5SRobert Mustacchi		"name": "SpMultAddFlops",
110d0e58ef5SRobert Mustacchi		"bit": 3,
111d0e58ef5SRobert Mustacchi		"rw": "Read-write",
112d0e58ef5SRobert Mustacchi		"description": "Single precision multiply-add FLOP. Multiply-add counts as 2 FLOPS."
113d0e58ef5SRobert Mustacchi	}, {
114d0e58ef5SRobert Mustacchi		"name": "SpDivFlops",
115d0e58ef5SRobert Mustacchi		"bit": 2,
116d0e58ef5SRobert Mustacchi		"rw": "Read-write",
117d0e58ef5SRobert Mustacchi		"description": "Single-precision divide/square root FLOPS"
118d0e58ef5SRobert Mustacchi	}, {
119d0e58ef5SRobert Mustacchi		"name": "SpMultFlops",
120d0e58ef5SRobert Mustacchi		"bit": 1,
121d0e58ef5SRobert Mustacchi		"rw": "Read-write",
122d0e58ef5SRobert Mustacchi		"description": "Single-precision multiply FLOPS"
123d0e58ef5SRobert Mustacchi	}, {
124d0e58ef5SRobert Mustacchi		"name": "SpAddSubFlops",
125d0e58ef5SRobert Mustacchi		"bit": 0,
126d0e58ef5SRobert Mustacchi		"rw": "Read-write",
127d0e58ef5SRobert Mustacchi		"description": "Single-precision add/subtract FLOPS"
128d0e58ef5SRobert Mustacchi	} ]
129d0e58ef5SRobert Mustacchi},
130d0e58ef5SRobert Mustacchi{
131d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::FpNumMovElimScalOp",
132d0e58ef5SRobert Mustacchi	"name": "FpNumMovElimScalOp",
133d0e58ef5SRobert Mustacchi	"code": "0x004",
134d0e58ef5SRobert Mustacchi	"summary": "Number of Move Elimination and Scalar Op Optimization",
135d0e58ef5SRobert Mustacchi	"description": "This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes.",
136d0e58ef5SRobert Mustacchi	"units": [ {
137d0e58ef5SRobert Mustacchi		"name": "Optimized",
138d0e58ef5SRobert Mustacchi		"bit": 3,
139d0e58ef5SRobert Mustacchi		"rw": "Read-write",
140d0e58ef5SRobert Mustacchi		"description": "Number of Scalar Ops optimized"
141d0e58ef5SRobert Mustacchi	}, {
142d0e58ef5SRobert Mustacchi		"name": "OptPotential",
143d0e58ef5SRobert Mustacchi		"bit": 2,
144d0e58ef5SRobert Mustacchi		"rw": "Read-write",
145d0e58ef5SRobert Mustacchi		"description": "Number of Ops that are candidates for optimization (have Z-bit either set or pass)."
146d0e58ef5SRobert Mustacchi	}, {
147d0e58ef5SRobert Mustacchi		"name": "SseMovOpsElim",
148d0e58ef5SRobert Mustacchi		"bit": 1,
149d0e58ef5SRobert Mustacchi		"rw": "Read-write",
150d0e58ef5SRobert Mustacchi		"description": "Number of SSE Move Ops eliminated"
151d0e58ef5SRobert Mustacchi	}, {
152d0e58ef5SRobert Mustacchi		"name": "SseMovOps",
153d0e58ef5SRobert Mustacchi		"bit": 0,
154d0e58ef5SRobert Mustacchi		"rw": "Read-write",
155d0e58ef5SRobert Mustacchi		"description": "Number of SSE Move Ops"
156d0e58ef5SRobert Mustacchi	} ]
157d0e58ef5SRobert Mustacchi},
158d0e58ef5SRobert Mustacchi{
159d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::FpRetiredSerOps",
160d0e58ef5SRobert Mustacchi	"name": "FpRetiredSerOps",
161d0e58ef5SRobert Mustacchi	"code": "0x005",
162d0e58ef5SRobert Mustacchi	"summary": "Retired Serializing Ops",
163d0e58ef5SRobert Mustacchi	"description": "The number of serializing Ops retired.",
164d0e58ef5SRobert Mustacchi	"units": [ {
165d0e58ef5SRobert Mustacchi		"name": "X87CtrlRet",
166d0e58ef5SRobert Mustacchi		"bit": 3,
167d0e58ef5SRobert Mustacchi		"rw": "Read-write",
168d0e58ef5SRobert Mustacchi		"description": "x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits"
169d0e58ef5SRobert Mustacchi	}, {
170d0e58ef5SRobert Mustacchi		"name": "X87BotRet",
171d0e58ef5SRobert Mustacchi		"bit": 2,
172d0e58ef5SRobert Mustacchi		"rw": "Read-write",
173d0e58ef5SRobert Mustacchi		"description": "x87 bottom-executing uOps retired"
174d0e58ef5SRobert Mustacchi	}, {
175d0e58ef5SRobert Mustacchi		"name": "SseCtrlRet",
176d0e58ef5SRobert Mustacchi		"bit": 1,
177d0e58ef5SRobert Mustacchi		"rw": "Read-write",
178d0e58ef5SRobert Mustacchi		"description": "SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits"
179d0e58ef5SRobert Mustacchi	}, {
180d0e58ef5SRobert Mustacchi		"name": "SseBotRet",
181d0e58ef5SRobert Mustacchi		"bit": 0,
182d0e58ef5SRobert Mustacchi		"rw": "Read-write",
183d0e58ef5SRobert Mustacchi		"description": "SSE bottom-executing uOps retired"
184d0e58ef5SRobert Mustacchi	} ]
185d0e58ef5SRobert Mustacchi},
186d0e58ef5SRobert Mustacchi{
187d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsBadStatus2",
188d0e58ef5SRobert Mustacchi	"name": "LsBadStatus2",
189d0e58ef5SRobert Mustacchi	"code": "0x024",
190d0e58ef5SRobert Mustacchi	"summary": "Bad Status 2",
191d0e58ef5SRobert Mustacchi	"description": "Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason. There are a number of reasons why this occurs, and this perfmon organizes them into three major groups.",
192d0e58ef5SRobert Mustacchi	"units": [ {
193d0e58ef5SRobert Mustacchi		"name": "StlfNoData",
194d0e58ef5SRobert Mustacchi		"bit": 2,
195d0e58ef5SRobert Mustacchi		"rw": "Read-write",
196d0e58ef5SRobert Mustacchi		"description": "The load is capable of forwarding from an older store (i.e. the address match/overlap between the load and the older store) was good and everything works from an address perspective, but the store's data has not been produced by EX or FP yet so it can't be forwarded."
197d0e58ef5SRobert Mustacchi	}, {
198d0e58ef5SRobert Mustacchi		"name": "StliOther",
199d0e58ef5SRobert Mustacchi		"bit": 1,
200d0e58ef5SRobert Mustacchi		"rw": "Read-write",
201d0e58ef5SRobert Mustacchi		"description": "All the other reasons. The most common among these is that there is only a partial overlap between the store and the load, for example there's an 8B store to address A and a 16B load starting at address A. STLF can't be performed in this case because only some of the load's data is coming fromthe store, so the load gets StliOther. Another StliOther case is if the load hits a non-cacheable store that's sitting in the non-cacheable buffers (WCBs)."
202d0e58ef5SRobert Mustacchi	}, {
203d0e58ef5SRobert Mustacchi		"name": "StliNoState",
204d0e58ef5SRobert Mustacchi		"bit": 0,
205d0e58ef5SRobert Mustacchi		"rw": "Rewad-write",
206d0e58ef5SRobert Mustacchi		"description": "The STLF is validated using DC way instead of an address compare. The store that wants to STLF is required to be a DC hit and have a valid DC way. The STLF candidate store is chosen based on address bits 11:0 overlap, and the DC way of that store is compared to the way of the load. If the store is in a DC miss state, then it doesn't have a valid DC way and so cannot validate STLF. The load gets StliNoState and can't complete.  Read-write"
207d0e58ef5SRobert Mustacchi	} ]
208d0e58ef5SRobert Mustacchi},
209d0e58ef5SRobert Mustacchi{
210d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsLocks",
211d0e58ef5SRobert Mustacchi	"name": "LsLocks",
212d0e58ef5SRobert Mustacchi	"code": "0x025",
213d0e58ef5SRobert Mustacchi	"summary": "Locks",
214d0e58ef5SRobert Mustacchi	"unit_mode": "or",
215d0e58ef5SRobert Mustacchi	"units": [ {
216d0e58ef5SRobert Mustacchi		"name": "SpecLockMapCommit",
217d0e58ef5SRobert Mustacchi		"bit": 3,
218d0e58ef5SRobert Mustacchi		"rw": "Read-write"
219d0e58ef5SRobert Mustacchi	}, {
220d0e58ef5SRobert Mustacchi		"name": "SpecLock",
221d0e58ef5SRobert Mustacchi		"bit": 2,
222d0e58ef5SRobert Mustacchi		"rw": "Read-write"
223d0e58ef5SRobert Mustacchi	}, {
224d0e58ef5SRobert Mustacchi		"name": "NonSpecLock",
225d0e58ef5SRobert Mustacchi		"bit": 1,
226d0e58ef5SRobert Mustacchi		"rw": "Read-write"
227d0e58ef5SRobert Mustacchi	}, {
228d0e58ef5SRobert Mustacchi		"name": "BusLock",
229d0e58ef5SRobert Mustacchi		"bit": 0,
230d0e58ef5SRobert Mustacchi		"rw": "Read-write"
231d0e58ef5SRobert Mustacchi	} ]
232d0e58ef5SRobert Mustacchi},
233d0e58ef5SRobert Mustacchi{
234d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsRetClClush",
235d0e58ef5SRobert Mustacchi	"name": "LsRetClClush",
236d0e58ef5SRobert Mustacchi	"code": "0x026",
237d0e58ef5SRobert Mustacchi	"summary": "Retired CLFLUSH Instructions",
238d0e58ef5SRobert Mustacchi	"description": "The number of retired CLFLUSH instructions. This is a non-speculative event."
239d0e58ef5SRobert Mustacchi},
240d0e58ef5SRobert Mustacchi{
241d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsRetCpuid",
242d0e58ef5SRobert Mustacchi	"name": "LsRetCpuid",
243d0e58ef5SRobert Mustacchi	"code": "0x027",
244d0e58ef5SRobert Mustacchi	"summary": "Retired CPUID Instructions",
245d0e58ef5SRobert Mustacchi	"description": "The number of CPUID instructions retired."
246d0e58ef5SRobert Mustacchi},
247d0e58ef5SRobert Mustacchi{
248d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsDispatch",
249d0e58ef5SRobert Mustacchi	"name": "LsDispatch",
250d0e58ef5SRobert Mustacchi	"code": "0x029",
251d0e58ef5SRobert Mustacchi	"summary": "LS Dispatch",
252d0e58ef5SRobert Mustacchi	"description": "Counts the number of operations dispatched to the LS unit.",
253d0e58ef5SRobert Mustacchi	"unit_mode": "add",
254d0e58ef5SRobert Mustacchi	"units": [ {
255d0e58ef5SRobert Mustacchi		"name": "LdStDispatch",
256d0e58ef5SRobert Mustacchi		"bit": 2,
257d0e58ef5SRobert Mustacchi		"rw": "Read-write",
258d0e58ef5SRobert Mustacchi		"description": "Load-op-Stores"
259d0e58ef5SRobert Mustacchi	}, {
260d0e58ef5SRobert Mustacchi		"name": "StoreDispatch",
261d0e58ef5SRobert Mustacchi		"bit": 1,
262d0e58ef5SRobert Mustacchi		"rw": "Read-write"
263d0e58ef5SRobert Mustacchi	}, {
264d0e58ef5SRobert Mustacchi		"name": "LdDispatch",
265d0e58ef5SRobert Mustacchi		"bit": 0,
266d0e58ef5SRobert Mustacchi		"rw": "Read-write"
267d0e58ef5SRobert Mustacchi	} ]
268d0e58ef5SRobert Mustacchi},
269d0e58ef5SRobert Mustacchi{
270d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsSmiRx",
271d0e58ef5SRobert Mustacchi	"name": "LsSmiRx",
272d0e58ef5SRobert Mustacchi	"code": "0x02B",
273d0e58ef5SRobert Mustacchi	"summary": "SMIs Received",
274d0e58ef5SRobert Mustacchi	"description": "Counts the number of SMIs received."
275d0e58ef5SRobert Mustacchi},
276d0e58ef5SRobert Mustacchi{
277d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsSTLF",
278d0e58ef5SRobert Mustacchi	"name": "LsSTLF",
279d0e58ef5SRobert Mustacchi	"code": "0x035",
280d0e58ef5SRobert Mustacchi	"summary": "Store to Load Forward",
281d0e58ef5SRobert Mustacchi	"description": "Number of STLF hits."
282d0e58ef5SRobert Mustacchi},
283d0e58ef5SRobert Mustacchi{
284d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsStCommitCancel2",
285d0e58ef5SRobert Mustacchi	"name": "LsStCommitCancel2",
286d0e58ef5SRobert Mustacchi	"code": "0x037",
287d0e58ef5SRobert Mustacchi	"summary": "Store Commit Cancels 2",
288d0e58ef5SRobert Mustacchi	"units": [ {
289d0e58ef5SRobert Mustacchi		"name": "StCommitCancelWcbFull",
290d0e58ef5SRobert Mustacchi		"bit": 0,
291d0e58ef5SRobert Mustacchi		"rw": "Read-write",
292d0e58ef5SRobert Mustacchi		"description": "A non-cacheable store and the non-cacheable commit buffer is full."
293d0e58ef5SRobert Mustacchi	} ]
294d0e58ef5SRobert Mustacchi},
295d0e58ef5SRobert Mustacchi{
296d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsDcAccesses",
297d0e58ef5SRobert Mustacchi	"name": "LsDcAccesses",
298d0e58ef5SRobert Mustacchi	"code": "0x040",
299d0e58ef5SRobert Mustacchi	"summary": "Data Cache Accesses",
300d0e58ef5SRobert Mustacchi	"description": "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event."
301d0e58ef5SRobert Mustacchi},
302d0e58ef5SRobert Mustacchi{
303d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsRefillsFromSys",
304d0e58ef5SRobert Mustacchi	"name": "LsRefillsFromSys",
305d0e58ef5SRobert Mustacchi	"code": "0x043",
306d0e58ef5SRobert Mustacchi	"summary": "Data Cache Refills from System",
307d0e58ef5SRobert Mustacchi	"description": "Demand Data Cache Fills by Data Source.",
308d0e58ef5SRobert Mustacchi	"units": [ {
309d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_RMT_DRAM",
310d0e58ef5SRobert Mustacchi		"bit": 6,
311d0e58ef5SRobert Mustacchi		"rw": "Read-write",
312d0e58ef5SRobert Mustacchi		"description": "DRAM or IO from different die."
313d0e58ef5SRobert Mustacchi	}, {
314d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_RMT_CACHE",
315d0e58ef5SRobert Mustacchi		"bit": 4,
316d0e58ef5SRobert Mustacchi		"rw": "Read-write",
317d0e58ef5SRobert Mustacchi		"description": "Hit in cache; Remote CCX and the address's Home Node is on a different die."
318d0e58ef5SRobert Mustacchi	}, {
319d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_LCL_DRAM",
320d0e58ef5SRobert Mustacchi		"bit": 3,
321d0e58ef5SRobert Mustacchi		"rw": "Read-write",
322d0e58ef5SRobert Mustacchi		"description": "DRAM or IO from this thread's die."
323d0e58ef5SRobert Mustacchi	}, {
324d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_LCL_CACHE",
325d0e58ef5SRobert Mustacchi		"bit": 1,
326d0e58ef5SRobert Mustacchi		"rw": "Read-write",
327d0e58ef5SRobert Mustacchi		"description": "Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's die."
328d0e58ef5SRobert Mustacchi	}, {
329d0e58ef5SRobert Mustacchi		"name": "MABRESP_LCL_L2",
330d0e58ef5SRobert Mustacchi		"bit": 0,
331d0e58ef5SRobert Mustacchi		"rw": "Read-write",
332d0e58ef5SRobert Mustacchi		"description": "Local L2 hit."
333d0e58ef5SRobert Mustacchi	} ]
334d0e58ef5SRobert Mustacchi},
335d0e58ef5SRobert Mustacchi{
336d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsL1DTlbMiss",
337d0e58ef5SRobert Mustacchi	"name": "LsL1DTlbMiss",
338d0e58ef5SRobert Mustacchi	"code": "0x045",
339d0e58ef5SRobert Mustacchi	"summary": "L1 DTLB Miss",
340d0e58ef5SRobert Mustacchi	"units": [ {
341d0e58ef5SRobert Mustacchi		"name": "TlbReload1GL2Miss",
342d0e58ef5SRobert Mustacchi		"bit": 7,
343d0e58ef5SRobert Mustacchi		"rw": "Read-write"
344d0e58ef5SRobert Mustacchi	}, {
345d0e58ef5SRobert Mustacchi		"name": "TlbReload2ML2Miss",
346d0e58ef5SRobert Mustacchi		"bit": 6,
347d0e58ef5SRobert Mustacchi		"rw": "Read-write"
348d0e58ef5SRobert Mustacchi	}, {
349d0e58ef5SRobert Mustacchi		"name": "TlbReload32KL2Miss",
350d0e58ef5SRobert Mustacchi		"bit": 5,
351d0e58ef5SRobert Mustacchi		"rw": "Read-write"
352d0e58ef5SRobert Mustacchi	}, {
353d0e58ef5SRobert Mustacchi		"name": "TlbReload4KL2Miss",
354d0e58ef5SRobert Mustacchi		"bit": 4,
355d0e58ef5SRobert Mustacchi		"rw": "Read-write"
356d0e58ef5SRobert Mustacchi	}, {
357d0e58ef5SRobert Mustacchi		"name": "TlbReload1GL2Hit",
358d0e58ef5SRobert Mustacchi		"bit": 3,
359d0e58ef5SRobert Mustacchi		"rw": "Read-write"
360d0e58ef5SRobert Mustacchi	}, {
361d0e58ef5SRobert Mustacchi		"name": "TlbReload2ML2Hit",
362d0e58ef5SRobert Mustacchi		"bit": 2,
363d0e58ef5SRobert Mustacchi		"rw": "Read-write"
364d0e58ef5SRobert Mustacchi	}, {
365d0e58ef5SRobert Mustacchi		"name": "TlbReload32KL2Hit",
366d0e58ef5SRobert Mustacchi		"bit": 1,
367d0e58ef5SRobert Mustacchi		"rw": "Read-write"
368d0e58ef5SRobert Mustacchi	}, {
369d0e58ef5SRobert Mustacchi		"name": "TlbReload4KL2Hit",
370d0e58ef5SRobert Mustacchi		"bit": 0,
371d0e58ef5SRobert Mustacchi		"rw": "Read-write"
372d0e58ef5SRobert Mustacchi	} ]
373d0e58ef5SRobert Mustacchi},
374d0e58ef5SRobert Mustacchi{
375d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsTablewalker",
376d0e58ef5SRobert Mustacchi	"name": "LsTablewalker",
377d0e58ef5SRobert Mustacchi	"code": "0x046",
378d0e58ef5SRobert Mustacchi	"summary": "Tablewalker allocation",
379d0e58ef5SRobert Mustacchi	"units": [ {
380d0e58ef5SRobert Mustacchi		"name": "PerfMonTablewalkAllocIside1",
381d0e58ef5SRobert Mustacchi		"bit": 3,
382d0e58ef5SRobert Mustacchi		"rw": "Read-write"
383d0e58ef5SRobert Mustacchi	}, {
384d0e58ef5SRobert Mustacchi		"name": "PerfMonTablewalkAllocIside0",
385d0e58ef5SRobert Mustacchi		"bit": 2,
386d0e58ef5SRobert Mustacchi		"rw": "Read-write"
387d0e58ef5SRobert Mustacchi	}, {
388d0e58ef5SRobert Mustacchi		"name": "PerfMonTablewalkAllocDside1",
389d0e58ef5SRobert Mustacchi		"bit": 1,
390d0e58ef5SRobert Mustacchi		"rw": "Read-write"
391d0e58ef5SRobert Mustacchi	}, {
392d0e58ef5SRobert Mustacchi		"name": "PerfMonTablewalkAllocDside0",
393d0e58ef5SRobert Mustacchi		"bit": 0,
394d0e58ef5SRobert Mustacchi		"rw": "Read-write"
395d0e58ef5SRobert Mustacchi	} ]
396d0e58ef5SRobert Mustacchi},
397d0e58ef5SRobert Mustacchi{
398d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsMisalAccesses",
399d0e58ef5SRobert Mustacchi	"name": "LsMisalAccesses",
400d0e58ef5SRobert Mustacchi	"code": "0x047",
401d0e58ef5SRobert Mustacchi	"summary": "Misaligned loads"
402d0e58ef5SRobert Mustacchi},
403d0e58ef5SRobert Mustacchi{
404d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsPrefInstrDisp",
405d0e58ef5SRobert Mustacchi	"name": "LsPrefInstrDisp",
406d0e58ef5SRobert Mustacchi	"code": "0x04B",
407d0e58ef5SRobert Mustacchi	"summary": "Prefetch Instructions Dispatched",
408d0e58ef5SRobert Mustacchi	"description": "Software Prefetch Instructions Dispatched.",
409d0e58ef5SRobert Mustacchi	"units": [ {
410d0e58ef5SRobert Mustacchi		"name": "PrefetchNTA",
411d0e58ef5SRobert Mustacchi		"bit": 2,
412d0e58ef5SRobert Mustacchi		"rw": "Read-write"
413d0e58ef5SRobert Mustacchi	}, {
414d0e58ef5SRobert Mustacchi		"name": "StorePrefetchW",
415d0e58ef5SRobert Mustacchi		"bit": 1,
416d0e58ef5SRobert Mustacchi		"rw": "Read-write"
417d0e58ef5SRobert Mustacchi	}, {
418d0e58ef5SRobert Mustacchi		"name": "LoadPrefetchW",
419d0e58ef5SRobert Mustacchi		"bit": 0,
420d0e58ef5SRobert Mustacchi		"rw": "Read-write",
421d0e58ef5SRobert Mustacchi		"description": "Prefetch, Prefetch_T0_T1_T2"
422d0e58ef5SRobert Mustacchi	} ]
423d0e58ef5SRobert Mustacchi},
424d0e58ef5SRobert Mustacchi{
425d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsInefSwPref",
426d0e58ef5SRobert Mustacchi	"name": "LsInefSwPref",
427d0e58ef5SRobert Mustacchi	"code": "0x052",
428d0e58ef5SRobert Mustacchi	"summary": "Ineffective Software Prefetchs",
429d0e58ef5SRobert Mustacchi	"description": "The number of software prefetches that did not fetch data outside of the processor core.",
430d0e58ef5SRobert Mustacchi	"units": [ {
431d0e58ef5SRobert Mustacchi		"name": "MabMchCnt",
432d0e58ef5SRobert Mustacchi		"bit": 1,
433d0e58ef5SRobert Mustacchi		"rw": "Read-write",
434d0e58ef5SRobert Mustacchi		"description": "Software PREFETCH instruction saw a match on an already-allocated miss request buffer."
435d0e58ef5SRobert Mustacchi	}, {
436d0e58ef5SRobert Mustacchi		"name": "DataPipeSwPfDcHit",
437d0e58ef5SRobert Mustacchi		"bit": 0,
438d0e58ef5SRobert Mustacchi		"rw": "Read-write",
439d0e58ef5SRobert Mustacchi		"description": "Software PREFETCH instruction saw a DC hit."
440d0e58ef5SRobert Mustacchi	} ]
441d0e58ef5SRobert Mustacchi},
442d0e58ef5SRobert Mustacchi{
443d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsSwPfDcFills",
444d0e58ef5SRobert Mustacchi	"name": "LsSwPfDcFills",
445d0e58ef5SRobert Mustacchi	"code": "0x059",
446d0e58ef5SRobert Mustacchi	"summary": "Software Prefetch Data Cache Fills",
447d0e58ef5SRobert Mustacchi	"description": "Software Prefetch Data Cache Fills by Data Source",
448d0e58ef5SRobert Mustacchi	"units": [ {
449d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_RMT_DRAM",
450d0e58ef5SRobert Mustacchi		"bit": 6,
451d0e58ef5SRobert Mustacchi		"rw": "Read-write",
452d0e58ef5SRobert Mustacchi		"description": "DRAM or IO from different die."
453d0e58ef5SRobert Mustacchi	}, {
454d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_RMT_CACHE",
455d0e58ef5SRobert Mustacchi		"bit": 4,
456d0e58ef5SRobert Mustacchi		"rw": "Read-write",
457d0e58ef5SRobert Mustacchi		"description": "Hit in cache; Remote CCX and the address's Home Node is on a different die."
458d0e58ef5SRobert Mustacchi	}, {
459d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_LCL_DRAM",
460d0e58ef5SRobert Mustacchi		"bit": 3,
461d0e58ef5SRobert Mustacchi		"rw": "Read-write",
462d0e58ef5SRobert Mustacchi		"description": "DRAM or IO from this thread's die."
463d0e58ef5SRobert Mustacchi	}, {
464d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_LCL_CACHE",
465d0e58ef5SRobert Mustacchi		"bit": 1,
466d0e58ef5SRobert Mustacchi		"rw": "Read-write",
467d0e58ef5SRobert Mustacchi		"description": "Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's die."
468d0e58ef5SRobert Mustacchi	}, {
469d0e58ef5SRobert Mustacchi		"name": "MABRESP_LCL_L2",
470d0e58ef5SRobert Mustacchi		"bit": 0,
471d0e58ef5SRobert Mustacchi		"rw": "Read-write",
472d0e58ef5SRobert Mustacchi		"description": "Local L2 hit."
473d0e58ef5SRobert Mustacchi	} ]
474d0e58ef5SRobert Mustacchi},
475d0e58ef5SRobert Mustacchi{
476d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsHwPfDcFills",
477d0e58ef5SRobert Mustacchi	"name": "LsHwPfDcFills",
478d0e58ef5SRobert Mustacchi	"code": "0x05A",
479d0e58ef5SRobert Mustacchi	"summary": "Hardware Prefetch Data Cache Fills",
480d0e58ef5SRobert Mustacchi	"description": "Hardware Prefetch Data Cache Fills by Data Source",
481d0e58ef5SRobert Mustacchi	"units": [ {
482d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_RMT_DRAM",
483d0e58ef5SRobert Mustacchi		"bit": 6,
484d0e58ef5SRobert Mustacchi		"rw": "Read-write",
485d0e58ef5SRobert Mustacchi		"description": "DRAM or IO from different die."
486d0e58ef5SRobert Mustacchi	}, {
487d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_RMT_CACHE",
488d0e58ef5SRobert Mustacchi		"bit": 4,
489d0e58ef5SRobert Mustacchi		"rw": "Read-write",
490d0e58ef5SRobert Mustacchi		"description": "Hit in cache; Remote CCX and the address's Home Node is on a different die."
491d0e58ef5SRobert Mustacchi	}, {
492d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_LCL_DRAM",
493d0e58ef5SRobert Mustacchi		"bit": 3,
494d0e58ef5SRobert Mustacchi		"rw": "Read-write",
495d0e58ef5SRobert Mustacchi		"description": "DRAM or IO from this thread's die."
496d0e58ef5SRobert Mustacchi	}, {
497d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_LCL_CACHE",
498d0e58ef5SRobert Mustacchi		"bit": 1,
499d0e58ef5SRobert Mustacchi		"rw": "Read-write",
500d0e58ef5SRobert Mustacchi		"description": "Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's die."
501d0e58ef5SRobert Mustacchi	}, {
502d0e58ef5SRobert Mustacchi		"name": "MABRESP_LCL_L2",
503d0e58ef5SRobert Mustacchi		"bit": 0,
504d0e58ef5SRobert Mustacchi		"rw": "Read-write",
505d0e58ef5SRobert Mustacchi		"description": "Local L2 hit."
506d0e58ef5SRobert Mustacchi	} ]
507d0e58ef5SRobert Mustacchi},
508d0e58ef5SRobert Mustacchi{
509d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsTwDcFills",
510d0e58ef5SRobert Mustacchi	"name": "LsTwDcFills",
511d0e58ef5SRobert Mustacchi	"code": "0x05B",
512d0e58ef5SRobert Mustacchi	"summary": "Table Walker Data Cache Fills by Data Source",
513d0e58ef5SRobert Mustacchi	"units": [ {
514d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_RMT_DRAM",
515d0e58ef5SRobert Mustacchi		"bit": 6,
516d0e58ef5SRobert Mustacchi		"rw": "Read-write",
517d0e58ef5SRobert Mustacchi		"description": "DRAM or IO from different die."
518d0e58ef5SRobert Mustacchi	}, {
519d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_RMT_CACHE",
520d0e58ef5SRobert Mustacchi		"bit": 4,
521d0e58ef5SRobert Mustacchi		"rw": "Read-write",
522d0e58ef5SRobert Mustacchi		"description": "Hit in cache; Remote CCX and the address's Home Node is on a different die."
523d0e58ef5SRobert Mustacchi	}, {
524d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_LCL_DRAM",
525d0e58ef5SRobert Mustacchi		"bit": 3,
526d0e58ef5SRobert Mustacchi		"rw": "Read-write",
527d0e58ef5SRobert Mustacchi		"description": "DRAM or IO from this thread's die."
528d0e58ef5SRobert Mustacchi	}, {
529d0e58ef5SRobert Mustacchi		"name": "LS_MABRESP_LCL_CACHE",
530d0e58ef5SRobert Mustacchi		"bit": 1,
531d0e58ef5SRobert Mustacchi		"rw": "Read-write",
532d0e58ef5SRobert Mustacchi		"description": "Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's die."
533d0e58ef5SRobert Mustacchi	}, {
534d0e58ef5SRobert Mustacchi		"name": "MABRESP_LCL_L2",
535d0e58ef5SRobert Mustacchi		"bit": 0,
536d0e58ef5SRobert Mustacchi		"rw": "Read-write",
537d0e58ef5SRobert Mustacchi		"description": "Local L2 hit."
538d0e58ef5SRobert Mustacchi	} ]
539d0e58ef5SRobert Mustacchi},
540d0e58ef5SRobert Mustacchi{
541d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::LsNotHaltedCyc",
542d0e58ef5SRobert Mustacchi	"name": "LsNotHaltedCyc",
543d0e58ef5SRobert Mustacchi	"code": "0x076",
544d0e58ef5SRobert Mustacchi	"summary": "Cycles not in Halt"
545d0e58ef5SRobert Mustacchi},
546d0e58ef5SRobert Mustacchi{
547d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::IcFw32",
548d0e58ef5SRobert Mustacchi	"name": "IcFw32",
549d0e58ef5SRobert Mustacchi	"code": "0x080",
550d0e58ef5SRobert Mustacchi	"summary": "32 Byte Instruction Cache Fetch",
551d0e58ef5SRobert Mustacchi	"description": "The number of 32B fetch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill responses)."
552d0e58ef5SRobert Mustacchi},
553d0e58ef5SRobert Mustacchi{
554d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::IcFw32Miss",
555d0e58ef5SRobert Mustacchi	"name": "IcFw32Miss",
556d0e58ef5SRobert Mustacchi	"code": "0x081",
557d0e58ef5SRobert Mustacchi	"summary": "32 Byte Instruction Cache Misses",
558d0e58ef5SRobert Mustacchi	"description": "The number of 32B fetch windows tried to read the L1 IC and missed in the full tag."
559d0e58ef5SRobert Mustacchi},
560d0e58ef5SRobert Mustacchi{
561d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::IcCacheFillL2",
562d0e58ef5SRobert Mustacchi	"name": "IcCacheFillL2",
563d0e58ef5SRobert Mustacchi	"code": "0x082",
564d0e58ef5SRobert Mustacchi	"summary": "Instruction Cache Refills from L2",
565d0e58ef5SRobert Mustacchi	"description": "The number of 64 byte instruction cache line was fulfilled from the L2 cache."
566d0e58ef5SRobert Mustacchi},
567d0e58ef5SRobert Mustacchi{
568d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::IcCacheFillSys",
569d0e58ef5SRobert Mustacchi	"name": "IcCacheFillSys",
570d0e58ef5SRobert Mustacchi	"code": "0x083",
571d0e58ef5SRobert Mustacchi	"summary": "Instruction Cache Refills from System",
572d0e58ef5SRobert Mustacchi	"description": "The number of 64 byte instruction cache line fulfilled from system memory or another cache."
573d0e58ef5SRobert Mustacchi},
574d0e58ef5SRobert Mustacchi{
575d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::BpL1TlbMissL2Hit",
576d0e58ef5SRobert Mustacchi	"name": "BpL1TlbMissL2Hit",
577d0e58ef5SRobert Mustacchi	"code": "0x084",
578d0e58ef5SRobert Mustacchi	"summary": "L1 ITLB Miss, L2 ITLB Hit",
579d0e58ef5SRobert Mustacchi	"description": "The number of instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
580d0e58ef5SRobert Mustacchi},
581d0e58ef5SRobert Mustacchi{
582d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::BpL1TlbMissL2Miss",
583d0e58ef5SRobert Mustacchi	"name": "BpL1TlbMissL2Miss",
584d0e58ef5SRobert Mustacchi	"code": "0x085",
585d0e58ef5SRobert Mustacchi	"summary": "L1 ITLB Miss, L2 ITLB Miss",
586d0e58ef5SRobert Mustacchi	"description": "The number of instruction fetches that miss in both the L1 and L2 TLBs"
587d0e58ef5SRobert Mustacchi},
588d0e58ef5SRobert Mustacchi{
589d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::IcFetchStall",
590d0e58ef5SRobert Mustacchi	"name": "IcFetchStall",
591d0e58ef5SRobert Mustacchi	"code": "0x087",
592d0e58ef5SRobert Mustacchi	"summary": "Instruction Pipe Stall",
593d0e58ef5SRobert Mustacchi	"units": [ {
594d0e58ef5SRobert Mustacchi		"name": "IcStallAny",
595d0e58ef5SRobert Mustacchi		"bit": 2,
596d0e58ef5SRobert Mustacchi		"rw": "Read-write ",
597d0e58ef5SRobert Mustacchi		"description": "Instruction Cache pipeline was stalled during this clock cycle for any reason."
598d0e58ef5SRobert Mustacchi	}, {
599d0e58ef5SRobert Mustacchi		"name": "IcStallDqEmpty",
600d0e58ef5SRobert Mustacchi		"bit": 1,
601d0e58ef5SRobert Mustacchi		"rw": "Read-write",
602d0e58ef5SRobert Mustacchi		"description": "Instruction Cache pipeline was stalled during this clock cycle due to upstream not providing fetch addresses quickly."
603d0e58ef5SRobert Mustacchi	}, {
604d0e58ef5SRobert Mustacchi		"name": "IcStallBackPressure",
605d0e58ef5SRobert Mustacchi		"bit": 0,
606d0e58ef5SRobert Mustacchi		"rw": "Read-write",
607d0e58ef5SRobert Mustacchi		"description": "Instruction Cache pipeline was stalled during this clock cycle due to downstream queues being full."
608d0e58ef5SRobert Mustacchi	} ]
609d0e58ef5SRobert Mustacchi},
610d0e58ef5SRobert Mustacchi{
611d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::BpL1BTBCorrect",
612d0e58ef5SRobert Mustacchi	"name": "BpL1BTBCorrect",
613d0e58ef5SRobert Mustacchi	"code": "0x08A",
614d0e58ef5SRobert Mustacchi	"summary": "L1 BTB Correction"
615d0e58ef5SRobert Mustacchi},
616d0e58ef5SRobert Mustacchi{
617d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::BpL2BTBCorrect",
618d0e58ef5SRobert Mustacchi	"name": "BpL2BTBCorrect",
619d0e58ef5SRobert Mustacchi	"code": "0x08B",
620d0e58ef5SRobert Mustacchi	"summary": "L2 BTB Correction"
621d0e58ef5SRobert Mustacchi},
622d0e58ef5SRobert Mustacchi{
623d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::IcCacheInval",
624d0e58ef5SRobert Mustacchi	"name": "IcCacheInval",
625d0e58ef5SRobert Mustacchi	"code": "0x08C",
626d0e58ef5SRobert Mustacchi	"summary": "Instruction Cache Lines Invalidated",
627d0e58ef5SRobert Mustacchi	"description": "The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core.",
628d0e58ef5SRobert Mustacchi	"units": [ {
629d0e58ef5SRobert Mustacchi		"name": "L2InvalidatingProbe",
630d0e58ef5SRobert Mustacchi		"bit": 1,
631d0e58ef5SRobert Mustacchi		"rw": "Read-write",
632d0e58ef5SRobert Mustacchi		"description": "IC line invalidated due to L2 invalidating probe (external or LS)."
633d0e58ef5SRobert Mustacchi	}, {
634d0e58ef5SRobert Mustacchi		"name": "FillInvalidated",
635d0e58ef5SRobert Mustacchi		"bit": 0,
636d0e58ef5SRobert Mustacchi		"rw": "Read-write",
637d0e58ef5SRobert Mustacchi		"description": "IC line invalidated due to overwriting fill response."
638d0e58ef5SRobert Mustacchi	} ]
639d0e58ef5SRobert Mustacchi},
640d0e58ef5SRobert Mustacchi{
641d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::BpTlbRel",
642d0e58ef5SRobert Mustacchi	"name": "BpTlbRel",
643d0e58ef5SRobert Mustacchi	"code": "0x099",
644d0e58ef5SRobert Mustacchi	"summary": "ITLB Reloads",
645d0e58ef5SRobert Mustacchi	"description": "The number of ITLB reload requests."
646d0e58ef5SRobert Mustacchi},
647d0e58ef5SRobert Mustacchi{
648d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::IcOcModeSwitch",
649d0e58ef5SRobert Mustacchi	"name": "IcOcModeSwitch",
650d0e58ef5SRobert Mustacchi	"code": "0x28A",
651d0e58ef5SRobert Mustacchi	"summary": "OC Mode Switch",
652d0e58ef5SRobert Mustacchi	"units": [ {
653d0e58ef5SRobert Mustacchi		"name": "OcIcModeSwitch",
654d0e58ef5SRobert Mustacchi		"bit": 1,
655d0e58ef5SRobert Mustacchi		"rw": "Read-write",
656d0e58ef5SRobert Mustacchi		"description": "OC to IC mode switch"
657d0e58ef5SRobert Mustacchi	}, {
658d0e58ef5SRobert Mustacchi		"name": "IcOcModeSwitch",
659d0e58ef5SRobert Mustacchi		"bit": 0,
660d0e58ef5SRobert Mustacchi		"rw": "Read-write",
661d0e58ef5SRobert Mustacchi		"description": "IC to OC mode switch"
662d0e58ef5SRobert Mustacchi	} ]
663d0e58ef5SRobert Mustacchi},
664d0e58ef5SRobert Mustacchi{
665d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::DeDisDispatchTokenStalls0",
666d0e58ef5SRobert Mustacchi	"name": "DeDisDispatchTokenStalls0",
667d0e58ef5SRobert Mustacchi	"code": "0x0AF",
668d0e58ef5SRobert Mustacchi	"summary": "Dynamic Tokens Dispatch Stall Cycles 0",
669d0e58ef5SRobert Mustacchi	"description": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall.",
670d0e58ef5SRobert Mustacchi	"units": [ {
671d0e58ef5SRobert Mustacchi		"name": "RetireTokenStall",
672d0e58ef5SRobert Mustacchi		"bit": 6,
673d0e58ef5SRobert Mustacchi		"rw": "Read-write",
674d0e58ef5SRobert Mustacchi		"description": "RETIRE Tokens unavailable"
675d0e58ef5SRobert Mustacchi	}, {
676d0e58ef5SRobert Mustacchi		"name": "AGSQTokenStall",
677d0e58ef5SRobert Mustacchi		"bit": 5,
678d0e58ef5SRobert Mustacchi		"rw": "Read-write",
679d0e58ef5SRobert Mustacchi		"description": "AGSQ Tokens unavailable"
680d0e58ef5SRobert Mustacchi	}, {
681d0e58ef5SRobert Mustacchi		"name": "ALUTokenStall",
682d0e58ef5SRobert Mustacchi		"bit": 4,
683d0e58ef5SRobert Mustacchi		"rw": "Read-write",
684d0e58ef5SRobert Mustacchi		"description": "ALU tokens total unavailable"
685d0e58ef5SRobert Mustacchi	}, {
686d0e58ef5SRobert Mustacchi		"name": "ALSQ3_0_TokenStall",
687d0e58ef5SRobert Mustacchi		"bit": 3,
688d0e58ef5SRobert Mustacchi		"rw": "Read-write"
689d0e58ef5SRobert Mustacchi	}, {
690d0e58ef5SRobert Mustacchi		"name": "ALSQ3TokenStall",
691d0e58ef5SRobert Mustacchi		"bit": 2,
692d0e58ef5SRobert Mustacchi		"rw": "Read-write",
693d0e58ef5SRobert Mustacchi		"description": "ALSQ 3 Tokens unavailable"
694d0e58ef5SRobert Mustacchi	}, {
695d0e58ef5SRobert Mustacchi		"name": "ALSQ2TokenStall",
696d0e58ef5SRobert Mustacchi		"bit": 1,
697d0e58ef5SRobert Mustacchi		"rw": "Read-write",
698d0e58ef5SRobert Mustacchi		"description": "ALSQ 2 Tokens unavailable"
699d0e58ef5SRobert Mustacchi	}, {
700d0e58ef5SRobert Mustacchi		"name": "ALSQ1TokenStall",
701d0e58ef5SRobert Mustacchi		"bit": 0,
702d0e58ef5SRobert Mustacchi		"rw": "Read-write",
703d0e58ef5SRobert Mustacchi		"description": "ALSQ 1 Tokens unavailable"
704d0e58ef5SRobert Mustacchi	} ]
705d0e58ef5SRobert Mustacchi},
706d0e58ef5SRobert Mustacchi{
707d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetInstr",
708d0e58ef5SRobert Mustacchi	"name": "ExRetInstr",
709d0e58ef5SRobert Mustacchi	"code": "0x0C0",
710d0e58ef5SRobert Mustacchi	"summary": "Retired Instructions"
711d0e58ef5SRobert Mustacchi},
712d0e58ef5SRobert Mustacchi{
713d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetCops",
714d0e58ef5SRobert Mustacchi	"name": "ExRetCops",
715d0e58ef5SRobert Mustacchi	"code": "0x0C1",
716d0e58ef5SRobert Mustacchi	"summary": "Retired Uops",
717d0e58ef5SRobert Mustacchi	"description": "The number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4."
718d0e58ef5SRobert Mustacchi},
719d0e58ef5SRobert Mustacchi{
720d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrn",
721d0e58ef5SRobert Mustacchi	"name": "ExRetBrn",
722d0e58ef5SRobert Mustacchi	"code": "0x0C2",
723d0e58ef5SRobert Mustacchi	"summary": "Retired Branch Instructions",
724d0e58ef5SRobert Mustacchi	"description": "The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
725d0e58ef5SRobert Mustacchi},
726d0e58ef5SRobert Mustacchi{
727d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrnMisp",
728d0e58ef5SRobert Mustacchi	"name": "ExRetBrnMisp",
729d0e58ef5SRobert Mustacchi	"code": "0x0C3",
730d0e58ef5SRobert Mustacchi	"summary": "Retired Branch Instructions Mispredicted",
731d0e58ef5SRobert Mustacchi	"description": "The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts)."
732d0e58ef5SRobert Mustacchi},
733d0e58ef5SRobert Mustacchi{
734d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrnTkn",
735d0e58ef5SRobert Mustacchi	"name": "ExRetBrnTkn",
736d0e58ef5SRobert Mustacchi	"code": "0x0C4",
737d0e58ef5SRobert Mustacchi	"summary": "Retired Taken Branch Instructions",
738d0e58ef5SRobert Mustacchi	"description": "The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
739d0e58ef5SRobert Mustacchi},
740d0e58ef5SRobert Mustacchi{
741d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrnTknMisp",
742d0e58ef5SRobert Mustacchi	"name": "ExRetBrnTknMisp",
743d0e58ef5SRobert Mustacchi	"code": "0x0C5",
744d0e58ef5SRobert Mustacchi	"summary": "Retired Taken Branch Instructions Mispredicted",
745d0e58ef5SRobert Mustacchi	"description": "The number of retired taken branch instructions that were mispredicted."
746d0e58ef5SRobert Mustacchi},
747d0e58ef5SRobert Mustacchi{
748d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrnFar",
749d0e58ef5SRobert Mustacchi	"name": "ExRetBrnFar",
750d0e58ef5SRobert Mustacchi	"code": "0x0C6",
751d0e58ef5SRobert Mustacchi	"summary": "Retired Far Control Transfers",
752d0e58ef5SRobert Mustacchi	"description": "The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction."
753d0e58ef5SRobert Mustacchi},
754d0e58ef5SRobert Mustacchi{
755d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrnResync",
756d0e58ef5SRobert Mustacchi	"name": "ExRetBrnResync",
757d0e58ef5SRobert Mustacchi	"code": "0x0C7",
758d0e58ef5SRobert Mustacchi	"summary": "Retired Branch Resyncs",
759d0e58ef5SRobert Mustacchi	"description": "The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare."
760d0e58ef5SRobert Mustacchi},
761d0e58ef5SRobert Mustacchi{
762d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetNearRet",
763d0e58ef5SRobert Mustacchi	"name": "ExRetNearRet",
764d0e58ef5SRobert Mustacchi	"code": "0x0C8",
765d0e58ef5SRobert Mustacchi	"summary": "Retired Near Returns",
766d0e58ef5SRobert Mustacchi	"description": "The number of near return instructions (RET or RET Iw) retired."
767d0e58ef5SRobert Mustacchi},
768d0e58ef5SRobert Mustacchi{
769d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetNearRetMispred",
770d0e58ef5SRobert Mustacchi	"name": "ExRetNearRetMispred",
771d0e58ef5SRobert Mustacchi	"code": "0x0C9",
772d0e58ef5SRobert Mustacchi	"summary": "Retired Near Returns Mispredicted",
773d0e58ef5SRobert Mustacchi	"description": "The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction."
774d0e58ef5SRobert Mustacchi},
775d0e58ef5SRobert Mustacchi{
776d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetBrnIndMisp",
777d0e58ef5SRobert Mustacchi	"name": "ExRetBrnIndMisp",
778d0e58ef5SRobert Mustacchi	"code": "0x0CA",
779d0e58ef5SRobert Mustacchi	"summary": "Retired Indirect Branch Instructions Mispredicted"
780d0e58ef5SRobert Mustacchi},
781d0e58ef5SRobert Mustacchi{
782d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetMmxFpInstr",
783d0e58ef5SRobert Mustacchi	"name": "ExRetMmxFpInstr",
784d0e58ef5SRobert Mustacchi	"code": "0x0CB",
785d0e58ef5SRobert Mustacchi	"summary": "Retired MMXTM/FP Instructions",
786d0e58ef5SRobert Mustacchi	"description": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non- numeric instructions it is not suitable for measuring MFLOPS.",
787d0e58ef5SRobert Mustacchi	"units": [ {
788d0e58ef5SRobert Mustacchi		"name": "SseInstr",
789d0e58ef5SRobert Mustacchi		"bit": 2,
790d0e58ef5SRobert Mustacchi		"rw": "Read-write",
791d0e58ef5SRobert Mustacchi		"description": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX)."
792d0e58ef5SRobert Mustacchi	}, {
793d0e58ef5SRobert Mustacchi		"name": "MmxInstr",
794d0e58ef5SRobert Mustacchi		"bit": 1,
795d0e58ef5SRobert Mustacchi		"rw": "Read-write",
796d0e58ef5SRobert Mustacchi		"description": "MMX instructions."
797d0e58ef5SRobert Mustacchi	}, {
798d0e58ef5SRobert Mustacchi		"name": "X87Instr",
799d0e58ef5SRobert Mustacchi		"bit": 0,
800d0e58ef5SRobert Mustacchi		"rw": "Read-write",
801d0e58ef5SRobert Mustacchi		"description": "x87 instructions"
802d0e58ef5SRobert Mustacchi	} ]
803d0e58ef5SRobert Mustacchi},
804d0e58ef5SRobert Mustacchi{
805d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetCond",
806d0e58ef5SRobert Mustacchi	"name": "ExRetCond",
807d0e58ef5SRobert Mustacchi	"code": "0x0D1",
808d0e58ef5SRobert Mustacchi	"summary": "Retired Conditional Branch Instructions"
809d0e58ef5SRobert Mustacchi},
810d0e58ef5SRobert Mustacchi{
811d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExDivBusy",
812d0e58ef5SRobert Mustacchi	"name": "ExDivBusy",
813d0e58ef5SRobert Mustacchi	"code": "0x0D3",
814d0e58ef5SRobert Mustacchi	"summary": "Div Cycles Busy count"
815d0e58ef5SRobert Mustacchi},
816d0e58ef5SRobert Mustacchi{
817d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExDivCount",
818d0e58ef5SRobert Mustacchi	"name": "ExDivCount",
819d0e58ef5SRobert Mustacchi	"code": "0x0D4",
820d0e58ef5SRobert Mustacchi	"summary": "Div Op Count"
821d0e58ef5SRobert Mustacchi},
822d0e58ef5SRobert Mustacchi{
823d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExTaggedIbsOps",
824d0e58ef5SRobert Mustacchi	"name": "ExTaggedIbsOps",
825d0e58ef5SRobert Mustacchi	"code": "0x1CF",
826d0e58ef5SRobert Mustacchi	"summary": "Tagged IBS Ops",
827d0e58ef5SRobert Mustacchi	"units": [ {
828d0e58ef5SRobert Mustacchi		"name": "IbsCountRollover",
829d0e58ef5SRobert Mustacchi		"bit": 2,
830d0e58ef5SRobert Mustacchi		"rw": "Read-write",
831d0e58ef5SRobert Mustacchi		"description": "Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired."
832d0e58ef5SRobert Mustacchi	}, {
833d0e58ef5SRobert Mustacchi		"name": "IbsTaggedOpsRet",
834d0e58ef5SRobert Mustacchi		"bit": 1,
835d0e58ef5SRobert Mustacchi		"rw": "Read-write",
836d0e58ef5SRobert Mustacchi		"description": "Number of Ops tagged by IBS that retired"
837d0e58ef5SRobert Mustacchi	}, {
838d0e58ef5SRobert Mustacchi		"name": "IbsTaggedOps",
839d0e58ef5SRobert Mustacchi		"bit": 0,
840d0e58ef5SRobert Mustacchi		"rw": "Read-write",
841d0e58ef5SRobert Mustacchi		"description": "Number of Ops tagged by IBS"
842d0e58ef5SRobert Mustacchi	} ]
843d0e58ef5SRobert Mustacchi}, {
844d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::ExRetFusBrnchInst",
845d0e58ef5SRobert Mustacchi	"name": "ExRetFusBrnchInst",
846d0e58ef5SRobert Mustacchi	"code": "0x1D0",
847d0e58ef5SRobert Mustacchi	"summary": "Retired Fused Branch Instructions",
848d0e58ef5SRobert Mustacchi	"description": "The number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3."
849d0e58ef5SRobert Mustacchi},
850d0e58ef5SRobert Mustacchi{
851d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::L2RequestG1",
852d0e58ef5SRobert Mustacchi	"name": "L2RequestG1",
853d0e58ef5SRobert Mustacchi	"code": "0x060",
854d0e58ef5SRobert Mustacchi	"summary": "Requests to L2 Group1",
855d0e58ef5SRobert Mustacchi	"units": [ {
856d0e58ef5SRobert Mustacchi		"name": "RdBlkL",
857d0e58ef5SRobert Mustacchi		"bit": 7,
858d0e58ef5SRobert Mustacchi		"rw": "Read-write"
859d0e58ef5SRobert Mustacchi	}, {
860d0e58ef5SRobert Mustacchi		"name": "RdBlkX",
861d0e58ef5SRobert Mustacchi		"bit": 6,
862d0e58ef5SRobert Mustacchi		"rw": "Read-write"
863d0e58ef5SRobert Mustacchi	}, {
864d0e58ef5SRobert Mustacchi		"name": "LsRdBlkC_S",
865d0e58ef5SRobert Mustacchi		"bit": 5,
866d0e58ef5SRobert Mustacchi		"rw": "Read-write"
867d0e58ef5SRobert Mustacchi	}, {
868d0e58ef5SRobert Mustacchi		"name": "CacheableIcRead",
869d0e58ef5SRobert Mustacchi		"bit": 4,
870d0e58ef5SRobert Mustacchi		"rw": "Read-write"
871d0e58ef5SRobert Mustacchi	}, {
872d0e58ef5SRobert Mustacchi		"name": "ChangeToX",
873d0e58ef5SRobert Mustacchi		"bit": 3,
874d0e58ef5SRobert Mustacchi		"rw": "Read-write"
875d0e58ef5SRobert Mustacchi	}, {
876d0e58ef5SRobert Mustacchi		"name": "PrefetchL2",
877d0e58ef5SRobert Mustacchi		"bit": 2,
878d0e58ef5SRobert Mustacchi		"rw": "Read-write",
879d0e58ef5SRobert Mustacchi		"description": "Assume core should also count these and allow the breakdown between H/W vs. S/W and LS vs. IC."
880d0e58ef5SRobert Mustacchi	}, {
881d0e58ef5SRobert Mustacchi		"name": "L2HwPf",
882d0e58ef5SRobert Mustacchi		"bit": 1,
883d0e58ef5SRobert Mustacchi		"rw": "Read-write"
884d0e58ef5SRobert Mustacchi	}, {
885d0e58ef5SRobert Mustacchi		"name": "OtherRequests",
886d0e58ef5SRobert Mustacchi		"bit": 0,
887d0e58ef5SRobert Mustacchi		"rw": "Read-write",
888d0e58ef5SRobert Mustacchi		"description": "Events covered by Core::X86::Pmc::Core::L2RequestG2."
889d0e58ef5SRobert Mustacchi	} ]
890d0e58ef5SRobert Mustacchi}, {
891d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::L2RequestG2",
892d0e58ef5SRobert Mustacchi	"name": "L2RequestG2",
893d0e58ef5SRobert Mustacchi	"code": "0x061",
894d0e58ef5SRobert Mustacchi	"summary": "Requests to L2 Group2",
895d0e58ef5SRobert Mustacchi	"description": "Multi-events in that LS and IF requests can be received simultaneous.",
896d0e58ef5SRobert Mustacchi	"units": [ {
897d0e58ef5SRobert Mustacchi		"name": "Group1",
898d0e58ef5SRobert Mustacchi		"bit": 7,
899d0e58ef5SRobert Mustacchi		"rw": "Read-write",
900d0e58ef5SRobert Mustacchi		"description": "All Group 1 commands not in unit0."
901d0e58ef5SRobert Mustacchi	}, {
902d0e58ef5SRobert Mustacchi		"name": "LsRdSized",
903d0e58ef5SRobert Mustacchi		"bit": 6,
904d0e58ef5SRobert Mustacchi		"rw": "Read-write",
905d0e58ef5SRobert Mustacchi		"description": "RdSized, RdSized32, RdSized64."
906d0e58ef5SRobert Mustacchi	}, {
907d0e58ef5SRobert Mustacchi		"name": "LsRdSizedNC",
908d0e58ef5SRobert Mustacchi		"bit": 5,
909d0e58ef5SRobert Mustacchi		"rw": "Read-write",
910d0e58ef5SRobert Mustacchi		"description": "RdSizedNC, RdSized32NC, RdSized64NC."
911d0e58ef5SRobert Mustacchi	}, {
912d0e58ef5SRobert Mustacchi		"name": "IcRdSized",
913d0e58ef5SRobert Mustacchi		"bit": 4,
914d0e58ef5SRobert Mustacchi		"rw": "Read-write"
915d0e58ef5SRobert Mustacchi	}, {
916d0e58ef5SRobert Mustacchi		"name": "IcRdSizedNC",
917d0e58ef5SRobert Mustacchi		"bit": 3,
918d0e58ef5SRobert Mustacchi		"rw": "Read-write"
919d0e58ef5SRobert Mustacchi	}, {
920d0e58ef5SRobert Mustacchi		"name": "SmcInval",
921d0e58ef5SRobert Mustacchi		"bit": 2,
922d0e58ef5SRobert Mustacchi		"rw": "Read-write"
923d0e58ef5SRobert Mustacchi	}, {
924d0e58ef5SRobert Mustacchi		"name": "BusLocksOriginator",
925d0e58ef5SRobert Mustacchi		"bit": 1,
926d0e58ef5SRobert Mustacchi		"rw": "Read-write"
927d0e58ef5SRobert Mustacchi	}, {
928d0e58ef5SRobert Mustacchi		"name": "BusLocksResponses",
929d0e58ef5SRobert Mustacchi		"bit": 0,
930d0e58ef5SRobert Mustacchi		"rw": "Read-write"
931d0e58ef5SRobert Mustacchi	} ]
932d0e58ef5SRobert Mustacchi},
933d0e58ef5SRobert Mustacchi{
934d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::L2Latancy",
935d0e58ef5SRobert Mustacchi	"name": "L2Latancy",
936d0e58ef5SRobert Mustacchi	"code": "0x062",
937d0e58ef5SRobert Mustacchi	"summary": "L2 Latency",
938d0e58ef5SRobert Mustacchi	"description": "Total cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. This may be used to calculate average latency by multiplying this count by four and then dividing by the total number of L2 fills (unit mask Core::X86::Pmc::Core::L2RequestG1 == FEh). Event counts are for both threads. To calculate average latency, the number of fills from both threads must be used.",
939d0e58ef5SRobert Mustacchi	"units": [ {
940d0e58ef5SRobert Mustacchi		"name": "L2CyclesWaitingOnFills",
941d0e58ef5SRobert Mustacchi		"bit": 0,
942d0e58ef5SRobert Mustacchi		"rw": "Read-write"
943d0e58ef5SRobert Mustacchi	} ]
944d0e58ef5SRobert Mustacchi},
945d0e58ef5SRobert Mustacchi{
946d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::L2WbcReq",
947d0e58ef5SRobert Mustacchi	"name": "L2WbcReq",
948d0e58ef5SRobert Mustacchi	"code": "0x063",
949d0e58ef5SRobert Mustacchi	"summary": "LS to L2 WBC requests",
950d0e58ef5SRobert Mustacchi	"units": [ {
951d0e58ef5SRobert Mustacchi		"name": "WcbWrite",
952d0e58ef5SRobert Mustacchi		"bit": 6,
953d0e58ef5SRobert Mustacchi		"rw": "Read-write"
954d0e58ef5SRobert Mustacchi	}, {
955d0e58ef5SRobert Mustacchi		"name": "WcbClose",
956d0e58ef5SRobert Mustacchi		"bit": 5,
957d0e58ef5SRobert Mustacchi		"rw": "Read-write"
958d0e58ef5SRobert Mustacchi	}, {
959d0e58ef5SRobert Mustacchi		"name": "CacheLineFlush",
960d0e58ef5SRobert Mustacchi		"bit": 4,
961d0e58ef5SRobert Mustacchi		"rw": "Read-write"
962d0e58ef5SRobert Mustacchi	}, {
963d0e58ef5SRobert Mustacchi		"name": "I_LineFlush",
964d0e58ef5SRobert Mustacchi		"bit": 3,
965d0e58ef5SRobert Mustacchi		"rw": "Read-write"
966d0e58ef5SRobert Mustacchi	}, {
967d0e58ef5SRobert Mustacchi		"name": "ZeroByteStore",
968d0e58ef5SRobert Mustacchi		"bit": 2,
969d0e58ef5SRobert Mustacchi		"rw": "Read-write",
970d0e58ef5SRobert Mustacchi		"description": "This becomes WriteNoData at SDP; this count does not include DVM Sync Ops and bus locks which are counted in Core::X86::Pmc::Core::L2RequestG2."
971d0e58ef5SRobert Mustacchi	}, {
972d0e58ef5SRobert Mustacchi		"name": "LocalIcClr",
973d0e58ef5SRobert Mustacchi		"bit": 1,
974d0e58ef5SRobert Mustacchi		"rw": "Read-write",
975d0e58ef5SRobert Mustacchi		"description": "Local IC Clear"
976d0e58ef5SRobert Mustacchi	}, {
977d0e58ef5SRobert Mustacchi		"name": "CLZero",
978d0e58ef5SRobert Mustacchi		"bit": 0,
979d0e58ef5SRobert Mustacchi		"rw": "Read-write",
980d0e58ef5SRobert Mustacchi		"description": "Cache Line Zero"
981d0e58ef5SRobert Mustacchi	} ]
982d0e58ef5SRobert Mustacchi},
983d0e58ef5SRobert Mustacchi{
984d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::L2CacheReqStat",
985d0e58ef5SRobert Mustacchi	"name": "L2CacheReqStat",
986d0e58ef5SRobert Mustacchi	"code": "0x064",
987d0e58ef5SRobert Mustacchi	"summary": "Core to L2 Cacheable Request Access Status",
988d0e58ef5SRobert Mustacchi	"description": "This event does not count accesses to the L2 cache by the L2 prefetcher, but it does count accesses by the L1 prefetcher.",
989d0e58ef5SRobert Mustacchi	"units": [ {
990d0e58ef5SRobert Mustacchi		"name": "LsRdBlkCS",
991d0e58ef5SRobert Mustacchi		"bit": 7,
992d0e58ef5SRobert Mustacchi		"rw": "Read-write",
993d0e58ef5SRobert Mustacchi		"description": "LS ReadBlock C/S Hit"
994d0e58ef5SRobert Mustacchi	}, {
995d0e58ef5SRobert Mustacchi		"name": "LsRdBlkLHitX",
996d0e58ef5SRobert Mustacchi		"bit": 6,
997d0e58ef5SRobert Mustacchi		"rw": "Read-write",
998d0e58ef5SRobert Mustacchi		"description": "LS Read Block L Hit X"
999d0e58ef5SRobert Mustacchi	}, {
1000d0e58ef5SRobert Mustacchi		"name": "LsRdBlkLHitS",
1001d0e58ef5SRobert Mustacchi		"bit": 5,
1002d0e58ef5SRobert Mustacchi		"rw": "Read-write",
1003d0e58ef5SRobert Mustacchi		"description": "LsRdBlkL Hit Shared"
1004d0e58ef5SRobert Mustacchi	}, {
1005d0e58ef5SRobert Mustacchi		"name": "LsRdBlkX",
1006d0e58ef5SRobert Mustacchi		"bit": 4,
1007d0e58ef5SRobert Mustacchi		"rw": "Read-write",
1008d0e58ef5SRobert Mustacchi		"description": "LsRdBlkX/ChgToX Hit X. Count RdBlkX finding Shared as a Miss."
1009d0e58ef5SRobert Mustacchi	}, {
1010d0e58ef5SRobert Mustacchi		"name": "LsRdBlkC",
1011d0e58ef5SRobert Mustacchi		"bit": 3,
1012d0e58ef5SRobert Mustacchi		"rw": "Read-write",
1013d0e58ef5SRobert Mustacchi		"description": "LS Read Block C S L X Change to X Miss"
1014d0e58ef5SRobert Mustacchi	}, {
1015d0e58ef5SRobert Mustacchi		"name": "IcFillHitX",
1016d0e58ef5SRobert Mustacchi		"bit": 2,
1017d0e58ef5SRobert Mustacchi		"rw": "Read-write",
1018d0e58ef5SRobert Mustacchi		"description": "IC Fill Hit Exclusive Stale"
1019d0e58ef5SRobert Mustacchi	}, {
1020d0e58ef5SRobert Mustacchi		"name": "IcFillHitS",
1021d0e58ef5SRobert Mustacchi		"bit": 1,
1022d0e58ef5SRobert Mustacchi		"rw": "Read-write",
1023d0e58ef5SRobert Mustacchi		"description": "IC Fill Hit Shared"
1024d0e58ef5SRobert Mustacchi	}, {
1025d0e58ef5SRobert Mustacchi		"name": "IcFillMiss",
1026d0e58ef5SRobert Mustacchi		"bit": 0,
1027d0e58ef5SRobert Mustacchi		"rw": "Read-write",
1028d0e58ef5SRobert Mustacchi		"description": "IC Fill Miss"
1029d0e58ef5SRobert Mustacchi	} ]
1030d0e58ef5SRobert Mustacchi},
1031d0e58ef5SRobert Mustacchi{
1032d0e58ef5SRobert Mustacchi	"mnemonic": "Core::X86::Pmc::Core::L2FillPending",
1033d0e58ef5SRobert Mustacchi	"name": "L2FillPending",
1034d0e58ef5SRobert Mustacchi	"code": "0x06D",
1035d0e58ef5SRobert Mustacchi	"summary": "Cycles with fill pending from L2",
1036d0e58ef5SRobert Mustacchi	"description": "Total cycles spent with one or more fill requests in flight from L2.",
1037d0e58ef5SRobert Mustacchi	"units": [ {
1038d0e58ef5SRobert Mustacchi		"name": "L2FillBusy.",
1039d0e58ef5SRobert Mustacchi		"bit": 0,
1040d0e58ef5SRobert Mustacchi		"rw": "Read-write."
1041d0e58ef5SRobert Mustacchi	} ]
1042d0e58ef5SRobert Mustacchi}
1043d0e58ef5SRobert Mustacchi]
1044