14c87aefeSPatrick Mooney /* $FreeBSD$ */ 24c87aefeSPatrick Mooney 34c87aefeSPatrick Mooney /*- 44c87aefeSPatrick Mooney * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 54c87aefeSPatrick Mooney * 64c87aefeSPatrick Mooney * Redistribution and use in source and binary forms, with or without 74c87aefeSPatrick Mooney * modification, are permitted provided that the following conditions 84c87aefeSPatrick Mooney * are met: 94c87aefeSPatrick Mooney * 1. Redistributions of source code must retain the above copyright 104c87aefeSPatrick Mooney * notice, this list of conditions and the following disclaimer. 114c87aefeSPatrick Mooney * 2. Redistributions in binary form must reproduce the above copyright 124c87aefeSPatrick Mooney * notice, this list of conditions and the following disclaimer in the 134c87aefeSPatrick Mooney * documentation and/or other materials provided with the distribution. 144c87aefeSPatrick Mooney * 154c87aefeSPatrick Mooney * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 164c87aefeSPatrick Mooney * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 174c87aefeSPatrick Mooney * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 184c87aefeSPatrick Mooney * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 194c87aefeSPatrick Mooney * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 204c87aefeSPatrick Mooney * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 214c87aefeSPatrick Mooney * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 224c87aefeSPatrick Mooney * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 234c87aefeSPatrick Mooney * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 244c87aefeSPatrick Mooney * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 254c87aefeSPatrick Mooney * SUCH DAMAGE. 264c87aefeSPatrick Mooney */ 274c87aefeSPatrick Mooney 284c87aefeSPatrick Mooney #ifndef _XHCIREG_H_ 294c87aefeSPatrick Mooney #define _XHCIREG_H_ 304c87aefeSPatrick Mooney 314c87aefeSPatrick Mooney /* XHCI PCI config registers */ 324c87aefeSPatrick Mooney #define PCI_XHCI_CBMEM 0x10 /* configuration base MEM */ 334c87aefeSPatrick Mooney #define PCI_XHCI_USBREV 0x60 /* RO USB protocol revision */ 344c87aefeSPatrick Mooney #define PCI_USB_REV_3_0 0x30 /* USB 3.0 */ 354c87aefeSPatrick Mooney #define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */ 364c87aefeSPatrick Mooney 374c87aefeSPatrick Mooney #define PCI_XHCI_INTEL_XUSB2PR 0xD0 /* Intel USB2 Port Routing */ 384c87aefeSPatrick Mooney #define PCI_XHCI_INTEL_USB2PRM 0xD4 /* Intel USB2 Port Routing Mask */ 394c87aefeSPatrick Mooney #define PCI_XHCI_INTEL_USB3_PSSEN 0xD8 /* Intel USB3 Port SuperSpeed Enable */ 404c87aefeSPatrick Mooney #define PCI_XHCI_INTEL_USB3PRM 0xDC /* Intel USB3 Port Routing Mask */ 414c87aefeSPatrick Mooney 424c87aefeSPatrick Mooney /* XHCI capability registers */ 434c87aefeSPatrick Mooney #define XHCI_CAPLENGTH 0x00 /* RO capability */ 444c87aefeSPatrick Mooney #define XHCI_RESERVED 0x01 /* Reserved */ 454c87aefeSPatrick Mooney #define XHCI_HCIVERSION 0x02 /* RO Interface version number */ 464c87aefeSPatrick Mooney #define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */ 474c87aefeSPatrick Mooney #define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */ 484c87aefeSPatrick Mooney #define XHCI_HCSPARAMS1 0x04 /* RO structural parameters 1 */ 494c87aefeSPatrick Mooney #define XHCI_HCS1_DEVSLOT_MAX(x)((x) & 0xFF) 504c87aefeSPatrick Mooney #define XHCI_HCS1_IRQ_MAX(x) (((x) >> 8) & 0x3FF) 514c87aefeSPatrick Mooney #define XHCI_HCS1_N_PORTS(x) (((x) >> 24) & 0xFF) 524c87aefeSPatrick Mooney #define XHCI_HCSPARAMS2 0x08 /* RO structural parameters 2 */ 534c87aefeSPatrick Mooney #define XHCI_HCS2_IST(x) ((x) & 0xF) 544c87aefeSPatrick Mooney #define XHCI_HCS2_ERST_MAX(x) (((x) >> 4) & 0xF) 554c87aefeSPatrick Mooney #define XHCI_HCS2_SPR(x) (((x) >> 26) & 0x1) 564c87aefeSPatrick Mooney #define XHCI_HCS2_SPB_MAX(x) ((((x) >> 16) & 0x3E0) | (((x) >> 27) & 0x1F)) 574c87aefeSPatrick Mooney #define XHCI_HCSPARAMS3 0x0C /* RO structural parameters 3 */ 584c87aefeSPatrick Mooney #define XHCI_HCS3_U1_DEL(x) ((x) & 0xFF) 594c87aefeSPatrick Mooney #define XHCI_HCS3_U2_DEL(x) (((x) >> 16) & 0xFFFF) 604c87aefeSPatrick Mooney #define XHCI_HCSPARAMS0 0x10 /* RO capability parameters */ 614c87aefeSPatrick Mooney #define XHCI_HCS0_AC64(x) ((x) & 0x1) /* 64-bit capable */ 624c87aefeSPatrick Mooney #define XHCI_HCS0_BNC(x) (((x) >> 1) & 0x1) /* BW negotiation */ 634c87aefeSPatrick Mooney #define XHCI_HCS0_CSZ(x) (((x) >> 2) & 0x1) /* context size */ 644c87aefeSPatrick Mooney #define XHCI_HCS0_PPC(x) (((x) >> 3) & 0x1) /* port power control */ 654c87aefeSPatrick Mooney #define XHCI_HCS0_PIND(x) (((x) >> 4) & 0x1) /* port indicators */ 664c87aefeSPatrick Mooney #define XHCI_HCS0_LHRC(x) (((x) >> 5) & 0x1) /* light HC reset */ 674c87aefeSPatrick Mooney #define XHCI_HCS0_LTC(x) (((x) >> 6) & 0x1) /* latency tolerance msg */ 684c87aefeSPatrick Mooney #define XHCI_HCS0_NSS(x) (((x) >> 7) & 0x1) /* no secondary sid */ 694c87aefeSPatrick Mooney #define XHCI_HCS0_PSA_SZ_MAX(x) (((x) >> 12) & 0xF) /* max pri. stream array size */ 704c87aefeSPatrick Mooney #define XHCI_HCS0_XECP(x) (((x) >> 16) & 0xFFFF) /* extended capabilities pointer */ 714c87aefeSPatrick Mooney #define XHCI_DBOFF 0x14 /* RO doorbell offset */ 724c87aefeSPatrick Mooney #define XHCI_RTSOFF 0x18 /* RO runtime register space offset */ 734c87aefeSPatrick Mooney 744c87aefeSPatrick Mooney /* XHCI operational registers. Offset given by XHCI_CAPLENGTH register */ 754c87aefeSPatrick Mooney #define XHCI_USBCMD 0x00 /* XHCI command */ 764c87aefeSPatrick Mooney #define XHCI_CMD_RS 0x00000001 /* RW Run/Stop */ 774c87aefeSPatrick Mooney #define XHCI_CMD_HCRST 0x00000002 /* RW Host Controller Reset */ 784c87aefeSPatrick Mooney #define XHCI_CMD_INTE 0x00000004 /* RW Interrupter Enable */ 794c87aefeSPatrick Mooney #define XHCI_CMD_HSEE 0x00000008 /* RW Host System Error Enable */ 804c87aefeSPatrick Mooney #define XHCI_CMD_LHCRST 0x00000080 /* RO/RW Light Host Controller Reset */ 814c87aefeSPatrick Mooney #define XHCI_CMD_CSS 0x00000100 /* RW Controller Save State */ 824c87aefeSPatrick Mooney #define XHCI_CMD_CRS 0x00000200 /* RW Controller Restore State */ 834c87aefeSPatrick Mooney #define XHCI_CMD_EWE 0x00000400 /* RW Enable Wrap Event */ 844c87aefeSPatrick Mooney #define XHCI_CMD_EU3S 0x00000800 /* RW Enable U3 MFINDEX Stop */ 854c87aefeSPatrick Mooney #define XHCI_USBSTS 0x04 /* XHCI status */ 864c87aefeSPatrick Mooney #define XHCI_STS_HCH 0x00000001 /* RO - Host Controller Halted */ 874c87aefeSPatrick Mooney #define XHCI_STS_HSE 0x00000004 /* RW - Host System Error */ 884c87aefeSPatrick Mooney #define XHCI_STS_EINT 0x00000008 /* RW - Event Interrupt */ 894c87aefeSPatrick Mooney #define XHCI_STS_PCD 0x00000010 /* RW - Port Change Detect */ 904c87aefeSPatrick Mooney #define XHCI_STS_SSS 0x00000100 /* RO - Save State Status */ 914c87aefeSPatrick Mooney #define XHCI_STS_RSS 0x00000200 /* RO - Restore State Status */ 924c87aefeSPatrick Mooney #define XHCI_STS_SRE 0x00000400 /* RW - Save/Restore Error */ 934c87aefeSPatrick Mooney #define XHCI_STS_CNR 0x00000800 /* RO - Controller Not Ready */ 944c87aefeSPatrick Mooney #define XHCI_STS_HCE 0x00001000 /* RO - Host Controller Error */ 954c87aefeSPatrick Mooney #define XHCI_PAGESIZE 0x08 /* XHCI page size mask */ 964c87aefeSPatrick Mooney #define XHCI_PAGESIZE_4K 0x00000001 /* 4K Page Size */ 974c87aefeSPatrick Mooney #define XHCI_PAGESIZE_8K 0x00000002 /* 8K Page Size */ 984c87aefeSPatrick Mooney #define XHCI_PAGESIZE_16K 0x00000004 /* 16K Page Size */ 994c87aefeSPatrick Mooney #define XHCI_PAGESIZE_32K 0x00000008 /* 32K Page Size */ 1004c87aefeSPatrick Mooney #define XHCI_PAGESIZE_64K 0x00000010 /* 64K Page Size */ 1014c87aefeSPatrick Mooney #define XHCI_DNCTRL 0x14 /* XHCI device notification control */ 1024c87aefeSPatrick Mooney #define XHCI_DNCTRL_MASK(n) (1U << (n)) 1034c87aefeSPatrick Mooney #define XHCI_CRCR_LO 0x18 /* XHCI command ring control */ 1044c87aefeSPatrick Mooney #define XHCI_CRCR_LO_RCS 0x00000001 /* RW - consumer cycle state */ 1054c87aefeSPatrick Mooney #define XHCI_CRCR_LO_CS 0x00000002 /* RW - command stop */ 1064c87aefeSPatrick Mooney #define XHCI_CRCR_LO_CA 0x00000004 /* RW - command abort */ 1074c87aefeSPatrick Mooney #define XHCI_CRCR_LO_CRR 0x00000008 /* RW - command ring running */ 1084c87aefeSPatrick Mooney #define XHCI_CRCR_LO_MASK 0x0000000F 1094c87aefeSPatrick Mooney #define XHCI_CRCR_HI 0x1C /* XHCI command ring control */ 1104c87aefeSPatrick Mooney #define XHCI_DCBAAP_LO 0x30 /* XHCI dev context BA pointer */ 1114c87aefeSPatrick Mooney #define XHCI_DCBAAP_HI 0x34 /* XHCI dev context BA pointer */ 1124c87aefeSPatrick Mooney #define XHCI_CONFIG 0x38 1134c87aefeSPatrick Mooney #define XHCI_CONFIG_SLOTS_MASK 0x000000FF /* RW - number of device slots enabled */ 1144c87aefeSPatrick Mooney 1154c87aefeSPatrick Mooney /* XHCI port status registers */ 1164c87aefeSPatrick Mooney #define XHCI_PORTSC(n) (0x3F0 + (0x10 * (n))) /* XHCI port status */ 1174c87aefeSPatrick Mooney #define XHCI_PS_CCS 0x00000001 /* RO - current connect status */ 1184c87aefeSPatrick Mooney #define XHCI_PS_PED 0x00000002 /* RW - port enabled / disabled */ 1194c87aefeSPatrick Mooney #define XHCI_PS_OCA 0x00000008 /* RO - over current active */ 1204c87aefeSPatrick Mooney #define XHCI_PS_PR 0x00000010 /* RW - port reset */ 1214c87aefeSPatrick Mooney #define XHCI_PS_PLS_GET(x) (((x) >> 5) & 0xF) /* RW - port link state */ 1224c87aefeSPatrick Mooney #define XHCI_PS_PLS_SET(x) (((x) & 0xF) << 5) /* RW - port link state */ 1234c87aefeSPatrick Mooney #define XHCI_PS_PP 0x00000200 /* RW - port power */ 1244c87aefeSPatrick Mooney #define XHCI_PS_SPEED_GET(x) (((x) >> 10) & 0xF) /* RO - port speed */ 1254c87aefeSPatrick Mooney #define XHCI_PS_PIC_GET(x) (((x) >> 14) & 0x3) /* RW - port indicator */ 1264c87aefeSPatrick Mooney #define XHCI_PS_PIC_SET(x) (((x) & 0x3) << 14) /* RW - port indicator */ 1274c87aefeSPatrick Mooney #define XHCI_PS_LWS 0x00010000 /* RW - port link state write strobe */ 1284c87aefeSPatrick Mooney #define XHCI_PS_CSC 0x00020000 /* RW - connect status change */ 1294c87aefeSPatrick Mooney #define XHCI_PS_PEC 0x00040000 /* RW - port enable/disable change */ 1304c87aefeSPatrick Mooney #define XHCI_PS_WRC 0x00080000 /* RW - warm port reset change */ 1314c87aefeSPatrick Mooney #define XHCI_PS_OCC 0x00100000 /* RW - over-current change */ 1324c87aefeSPatrick Mooney #define XHCI_PS_PRC 0x00200000 /* RW - port reset change */ 1334c87aefeSPatrick Mooney #define XHCI_PS_PLC 0x00400000 /* RW - port link state change */ 1344c87aefeSPatrick Mooney #define XHCI_PS_CEC 0x00800000 /* RW - config error change */ 1354c87aefeSPatrick Mooney #define XHCI_PS_CAS 0x01000000 /* RO - cold attach status */ 1364c87aefeSPatrick Mooney #define XHCI_PS_WCE 0x02000000 /* RW - wake on connect enable */ 1374c87aefeSPatrick Mooney #define XHCI_PS_WDE 0x04000000 /* RW - wake on disconnect enable */ 1384c87aefeSPatrick Mooney #define XHCI_PS_WOE 0x08000000 /* RW - wake on over-current enable */ 1394c87aefeSPatrick Mooney #define XHCI_PS_DR 0x40000000 /* RO - device removable */ 1404c87aefeSPatrick Mooney #define XHCI_PS_WPR 0x80000000U /* RW - warm port reset */ 1414c87aefeSPatrick Mooney #define XHCI_PS_CLEAR 0x80FF01FFU /* command bits */ 1424c87aefeSPatrick Mooney 1434c87aefeSPatrick Mooney #define XHCI_PORTPMSC(n) (0x3F4 + (0x10 * (n))) /* XHCI status and control */ 1444c87aefeSPatrick Mooney #define XHCI_PM3_U1TO_GET(x) (((x) >> 0) & 0xFF) /* RW - U1 timeout */ 1454c87aefeSPatrick Mooney #define XHCI_PM3_U1TO_SET(x) (((x) & 0xFF) << 0) /* RW - U1 timeout */ 1464c87aefeSPatrick Mooney #define XHCI_PM3_U2TO_GET(x) (((x) >> 8) & 0xFF) /* RW - U2 timeout */ 1474c87aefeSPatrick Mooney #define XHCI_PM3_U2TO_SET(x) (((x) & 0xFF) << 8) /* RW - U2 timeout */ 1484c87aefeSPatrick Mooney #define XHCI_PM3_FLA 0x00010000 /* RW - Force Link PM Accept */ 1494c87aefeSPatrick Mooney #define XHCI_PM2_L1S_GET(x) (((x) >> 0) & 0x7) /* RO - L1 status */ 1504c87aefeSPatrick Mooney #define XHCI_PM2_RWE 0x00000008 /* RW - remote wakup enable */ 1514c87aefeSPatrick Mooney #define XHCI_PM2_HIRD_GET(x) (((x) >> 4) & 0xF) /* RW - host initiated resume duration */ 1524c87aefeSPatrick Mooney #define XHCI_PM2_HIRD_SET(x) (((x) & 0xF) << 4) /* RW - host initiated resume duration */ 1534c87aefeSPatrick Mooney #define XHCI_PM2_L1SLOT_GET(x) (((x) >> 8) & 0xFF) /* RW - L1 device slot */ 1544c87aefeSPatrick Mooney #define XHCI_PM2_L1SLOT_SET(x) (((x) & 0xFF) << 8) /* RW - L1 device slot */ 1554c87aefeSPatrick Mooney #define XHCI_PM2_HLE 0x00010000 /* RW - hardware LPM enable */ 1564c87aefeSPatrick Mooney #define XHCI_PORTLI(n) (0x3F8 + (0x10 * (n))) /* XHCI port link info */ 1574c87aefeSPatrick Mooney #define XHCI_PLI3_ERR_GET(x) (((x) >> 0) & 0xFFFF) /* RO - port link errors */ 1584c87aefeSPatrick Mooney #define XHCI_PORTRSV(n) (0x3FC + (0x10 * (n))) /* XHCI port reserved */ 1594c87aefeSPatrick Mooney 1604c87aefeSPatrick Mooney /* XHCI runtime registers. Offset given by XHCI_CAPLENGTH + XHCI_RTSOFF registers */ 1614c87aefeSPatrick Mooney #define XHCI_MFINDEX 0x0000 /* RO - microframe index */ 1624c87aefeSPatrick Mooney #define XHCI_MFINDEX_GET(x) ((x) & 0x3FFF) 1634c87aefeSPatrick Mooney #define XHCI_IMAN(n) (0x0020 + (0x20 * (n))) /* XHCI interrupt management */ 1644c87aefeSPatrick Mooney #define XHCI_IMAN_INTR_PEND 0x00000001 /* RW - interrupt pending */ 1654c87aefeSPatrick Mooney #define XHCI_IMAN_INTR_ENA 0x00000002 /* RW - interrupt enable */ 1664c87aefeSPatrick Mooney #define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) /* XHCI interrupt moderation */ 1674c87aefeSPatrick Mooney #define XHCI_IMOD_IVAL_GET(x) (((x) >> 0) & 0xFFFF) /* 250ns unit */ 1684c87aefeSPatrick Mooney #define XHCI_IMOD_IVAL_SET(x) (((x) & 0xFFFF) << 0) /* 250ns unit */ 1694c87aefeSPatrick Mooney #define XHCI_IMOD_ICNT_GET(x) (((x) >> 16) & 0xFFFF) /* 250ns unit */ 1704c87aefeSPatrick Mooney #define XHCI_IMOD_ICNT_SET(x) (((x) & 0xFFFF) << 16) /* 250ns unit */ 1714c87aefeSPatrick Mooney #define XHCI_IMOD_DEFAULT 0x000001F4U /* 8000 IRQs/second */ 1724c87aefeSPatrick Mooney #define XHCI_IMOD_DEFAULT_LP 0x000003F8U /* 4000 IRQs/second - LynxPoint */ 1734c87aefeSPatrick Mooney #define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n))) /* XHCI event ring segment table size */ 1744c87aefeSPatrick Mooney #define XHCI_ERSTS_GET(x) ((x) & 0xFFFF) 1754c87aefeSPatrick Mooney #define XHCI_ERSTS_SET(x) ((x) & 0xFFFF) 1764c87aefeSPatrick Mooney #define XHCI_ERSTBA_LO(n) (0x0030 + (0x20 * (n))) /* XHCI event ring segment table BA */ 1774c87aefeSPatrick Mooney #define XHCI_ERSTBA_HI(n) (0x0034 + (0x20 * (n))) /* XHCI event ring segment table BA */ 1784c87aefeSPatrick Mooney #define XHCI_ERDP_LO(n) (0x0038 + (0x20 * (n))) /* XHCI event ring dequeue pointer */ 1794c87aefeSPatrick Mooney #define XHCI_ERDP_LO_SINDEX(x) ((x) & 0x7) /* RO - dequeue segment index */ 1804c87aefeSPatrick Mooney #define XHCI_ERDP_LO_BUSY 0x00000008 /* RW - event handler busy */ 1814c87aefeSPatrick Mooney #define XHCI_ERDP_HI(n) (0x003C + (0x20 * (n))) /* XHCI event ring dequeue pointer */ 1824c87aefeSPatrick Mooney 1834c87aefeSPatrick Mooney /* XHCI doorbell registers. Offset given by XHCI_CAPLENGTH + XHCI_DBOFF registers */ 1844c87aefeSPatrick Mooney #define XHCI_DOORBELL(n) (0x0000 + (4 * (n))) 1854c87aefeSPatrick Mooney #define XHCI_DB_TARGET_GET(x) ((x) & 0xFF) /* RW - doorbell target */ 1864c87aefeSPatrick Mooney #define XHCI_DB_TARGET_SET(x) ((x) & 0xFF) /* RW - doorbell target */ 1874c87aefeSPatrick Mooney #define XHCI_DB_SID_GET(x) (((x) >> 16) & 0xFFFF) /* RW - doorbell stream ID */ 1884c87aefeSPatrick Mooney #define XHCI_DB_SID_SET(x) (((x) & 0xFFFF) << 16) /* RW - doorbell stream ID */ 1894c87aefeSPatrick Mooney 1904c87aefeSPatrick Mooney /* XHCI legacy support */ 1914c87aefeSPatrick Mooney #define XHCI_XECP_ID(x) ((x) & 0xFF) 1924c87aefeSPatrick Mooney #define XHCI_XECP_NEXT(x) (((x) >> 8) & 0xFF) 1934c87aefeSPatrick Mooney #define XHCI_XECP_BIOS_SEM 0x0002 1944c87aefeSPatrick Mooney #define XHCI_XECP_OS_SEM 0x0003 1954c87aefeSPatrick Mooney 1964c87aefeSPatrick Mooney /* XHCI capability ID's */ 1974c87aefeSPatrick Mooney #define XHCI_ID_USB_LEGACY 0x0001 1984c87aefeSPatrick Mooney #define XHCI_ID_PROTOCOLS 0x0002 1994c87aefeSPatrick Mooney #define XHCI_ID_POWER_MGMT 0x0003 2004c87aefeSPatrick Mooney #define XHCI_ID_VIRTUALIZATION 0x0004 2014c87aefeSPatrick Mooney #define XHCI_ID_MSG_IRQ 0x0005 2024c87aefeSPatrick Mooney #define XHCI_ID_USB_LOCAL_MEM 0x0006 2034c87aefeSPatrick Mooney 2044c87aefeSPatrick Mooney /* XHCI register R/W wrappers */ 2054c87aefeSPatrick Mooney #define XREAD1(sc, what, a) \ 2064c87aefeSPatrick Mooney bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 2074c87aefeSPatrick Mooney (a) + (sc)->sc_##what##_off) 2084c87aefeSPatrick Mooney #define XREAD2(sc, what, a) \ 2094c87aefeSPatrick Mooney bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 2104c87aefeSPatrick Mooney (a) + (sc)->sc_##what##_off) 2114c87aefeSPatrick Mooney #define XREAD4(sc, what, a) \ 2124c87aefeSPatrick Mooney bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 2134c87aefeSPatrick Mooney (a) + (sc)->sc_##what##_off) 2144c87aefeSPatrick Mooney #define XWRITE1(sc, what, a, x) \ 2154c87aefeSPatrick Mooney bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 2164c87aefeSPatrick Mooney (a) + (sc)->sc_##what##_off, (x)) 2174c87aefeSPatrick Mooney #define XWRITE2(sc, what, a, x) \ 2184c87aefeSPatrick Mooney bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 2194c87aefeSPatrick Mooney (a) + (sc)->sc_##what##_off, (x)) 2204c87aefeSPatrick Mooney #define XWRITE4(sc, what, a, x) \ 2214c87aefeSPatrick Mooney bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, \ 2224c87aefeSPatrick Mooney (a) + (sc)->sc_##what##_off, (x)) 2234c87aefeSPatrick Mooney 2244c87aefeSPatrick Mooney #endif /* _XHCIREG_H_ */ 225