1bf21cd93STycho Nightingale /*- 2bf21cd93STycho Nightingale * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3bf21cd93STycho Nightingale * All rights reserved. 4bf21cd93STycho Nightingale * 5bf21cd93STycho Nightingale * Redistribution and use in source and binary forms, with or without 6bf21cd93STycho Nightingale * modification, are permitted provided that the following conditions 7bf21cd93STycho Nightingale * are met: 8bf21cd93STycho Nightingale * 1. Redistributions of source code must retain the above copyright 9bf21cd93STycho Nightingale * notice unmodified, this list of conditions, and the following 10bf21cd93STycho Nightingale * disclaimer. 11bf21cd93STycho Nightingale * 2. Redistributions in binary form must reproduce the above copyright 12bf21cd93STycho Nightingale * notice, this list of conditions and the following disclaimer in the 13bf21cd93STycho Nightingale * documentation and/or other materials provided with the distribution. 14bf21cd93STycho Nightingale * 15bf21cd93STycho Nightingale * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16bf21cd93STycho Nightingale * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17bf21cd93STycho Nightingale * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18bf21cd93STycho Nightingale * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19bf21cd93STycho Nightingale * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20bf21cd93STycho Nightingale * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21bf21cd93STycho Nightingale * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22bf21cd93STycho Nightingale * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23bf21cd93STycho Nightingale * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24bf21cd93STycho Nightingale * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25bf21cd93STycho Nightingale * 26bf21cd93STycho Nightingale * $FreeBSD: head/sys/dev/pci/pcireg.h 266468 2014-05-20 14:39:22Z mav $ 27bf21cd93STycho Nightingale * 28bf21cd93STycho Nightingale */ 29bf21cd93STycho Nightingale 30bf21cd93STycho Nightingale /* 31bf21cd93STycho Nightingale * PCIM_xxx: mask to locate subfield in register 32bf21cd93STycho Nightingale * PCIR_xxx: config register offset 33bf21cd93STycho Nightingale * PCIC_xxx: device class 34bf21cd93STycho Nightingale * PCIS_xxx: device subclass 35bf21cd93STycho Nightingale * PCIP_xxx: device programming interface 36bf21cd93STycho Nightingale * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 37bf21cd93STycho Nightingale * PCID_xxx: device ID 38bf21cd93STycho Nightingale * PCIY_xxx: capability identification number 39bf21cd93STycho Nightingale * PCIZ_xxx: extended capability identification number 40bf21cd93STycho Nightingale */ 41bf21cd93STycho Nightingale 42bf21cd93STycho Nightingale /* some PCI bus constants */ 43bf21cd93STycho Nightingale #define PCI_DOMAINMAX 65535 /* highest supported domain number */ 44bf21cd93STycho Nightingale #define PCI_BUSMAX 255 /* highest supported bus number */ 45bf21cd93STycho Nightingale #define PCI_SLOTMAX 31 /* highest supported slot number */ 46bf21cd93STycho Nightingale #define PCI_FUNCMAX 7 /* highest supported function number */ 47bf21cd93STycho Nightingale #define PCI_REGMAX 255 /* highest supported config register addr. */ 48bf21cd93STycho Nightingale #define PCIE_REGMAX 4095 /* highest supported config register addr. */ 49bf21cd93STycho Nightingale #define PCI_MAXHDRTYPE 2 50bf21cd93STycho Nightingale 51bf21cd93STycho Nightingale #define PCIE_ARI_SLOTMAX 0 52bf21cd93STycho Nightingale #define PCIE_ARI_FUNCMAX 255 53bf21cd93STycho Nightingale 54bf21cd93STycho Nightingale #define PCI_RID_BUS_SHIFT 8 55bf21cd93STycho Nightingale #define PCI_RID_SLOT_SHIFT 3 56bf21cd93STycho Nightingale #define PCI_RID_FUNC_SHIFT 0 57bf21cd93STycho Nightingale 58bf21cd93STycho Nightingale #define PCI_RID(bus, slot, func) \ 59bf21cd93STycho Nightingale ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \ 60bf21cd93STycho Nightingale (((slot) & PCI_SLOTMAX) << PCI_RID_SLOT_SHIFT) | \ 61bf21cd93STycho Nightingale (((func) & PCI_FUNCMAX) << PCI_RID_FUNC_SHIFT)) 62bf21cd93STycho Nightingale 63bf21cd93STycho Nightingale #define PCI_ARI_RID(bus, func) \ 64bf21cd93STycho Nightingale ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \ 65bf21cd93STycho Nightingale (((func) & PCIE_ARI_FUNCMAX) << PCI_RID_FUNC_SHIFT)) 66bf21cd93STycho Nightingale 67bf21cd93STycho Nightingale #define PCI_RID2BUS(rid) (((rid) >> PCI_RID_BUS_SHIFT) & PCI_BUSMAX) 68bf21cd93STycho Nightingale #define PCI_RID2SLOT(rid) (((rid) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX) 69bf21cd93STycho Nightingale #define PCI_RID2FUNC(rid) (((rid) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX) 70bf21cd93STycho Nightingale 71bf21cd93STycho Nightingale #define PCIE_ARI_SLOT(func) (((func) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX) 72bf21cd93STycho Nightingale #define PCIE_ARI_FUNC(func) (((func) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX) 73bf21cd93STycho Nightingale 74bf21cd93STycho Nightingale /* PCI config header registers for all devices */ 75bf21cd93STycho Nightingale 76bf21cd93STycho Nightingale #define PCIR_DEVVENDOR 0x00 77bf21cd93STycho Nightingale #define PCIR_VENDOR 0x00 78bf21cd93STycho Nightingale #define PCIR_DEVICE 0x02 79bf21cd93STycho Nightingale #define PCIR_COMMAND 0x04 80bf21cd93STycho Nightingale #define PCIM_CMD_PORTEN 0x0001 81bf21cd93STycho Nightingale #define PCIM_CMD_MEMEN 0x0002 82bf21cd93STycho Nightingale #define PCIM_CMD_BUSMASTEREN 0x0004 83bf21cd93STycho Nightingale #define PCIM_CMD_SPECIALEN 0x0008 84bf21cd93STycho Nightingale #define PCIM_CMD_MWRICEN 0x0010 85bf21cd93STycho Nightingale #define PCIM_CMD_PERRESPEN 0x0040 86bf21cd93STycho Nightingale #define PCIM_CMD_SERRESPEN 0x0100 87bf21cd93STycho Nightingale #define PCIM_CMD_BACKTOBACK 0x0200 88bf21cd93STycho Nightingale #define PCIM_CMD_INTxDIS 0x0400 89bf21cd93STycho Nightingale #define PCIR_STATUS 0x06 90bf21cd93STycho Nightingale #define PCIM_STATUS_INTxSTATE 0x0008 91bf21cd93STycho Nightingale #define PCIM_STATUS_CAPPRESENT 0x0010 92bf21cd93STycho Nightingale #define PCIM_STATUS_66CAPABLE 0x0020 93bf21cd93STycho Nightingale #define PCIM_STATUS_BACKTOBACK 0x0080 94bf21cd93STycho Nightingale #define PCIM_STATUS_MDPERR 0x0100 95bf21cd93STycho Nightingale #define PCIM_STATUS_SEL_FAST 0x0000 96bf21cd93STycho Nightingale #define PCIM_STATUS_SEL_MEDIMUM 0x0200 97bf21cd93STycho Nightingale #define PCIM_STATUS_SEL_SLOW 0x0400 98bf21cd93STycho Nightingale #define PCIM_STATUS_SEL_MASK 0x0600 99bf21cd93STycho Nightingale #define PCIM_STATUS_STABORT 0x0800 100bf21cd93STycho Nightingale #define PCIM_STATUS_RTABORT 0x1000 101bf21cd93STycho Nightingale #define PCIM_STATUS_RMABORT 0x2000 102bf21cd93STycho Nightingale #define PCIM_STATUS_SERR 0x4000 103bf21cd93STycho Nightingale #define PCIM_STATUS_PERR 0x8000 104bf21cd93STycho Nightingale #define PCIR_REVID 0x08 105bf21cd93STycho Nightingale #define PCIR_PROGIF 0x09 106bf21cd93STycho Nightingale #define PCIR_SUBCLASS 0x0a 107bf21cd93STycho Nightingale #define PCIR_CLASS 0x0b 108bf21cd93STycho Nightingale #define PCIR_CACHELNSZ 0x0c 109bf21cd93STycho Nightingale #define PCIR_LATTIMER 0x0d 110bf21cd93STycho Nightingale #define PCIR_HDRTYPE 0x0e 111bf21cd93STycho Nightingale #define PCIM_HDRTYPE 0x7f 112bf21cd93STycho Nightingale #define PCIM_HDRTYPE_NORMAL 0x00 113bf21cd93STycho Nightingale #define PCIM_HDRTYPE_BRIDGE 0x01 114bf21cd93STycho Nightingale #define PCIM_HDRTYPE_CARDBUS 0x02 115bf21cd93STycho Nightingale #define PCIM_MFDEV 0x80 116bf21cd93STycho Nightingale #define PCIR_BIST 0x0f 117bf21cd93STycho Nightingale 118bf21cd93STycho Nightingale /* Capability Register Offsets */ 119bf21cd93STycho Nightingale 120bf21cd93STycho Nightingale #define PCICAP_ID 0x0 121bf21cd93STycho Nightingale #define PCICAP_NEXTPTR 0x1 122bf21cd93STycho Nightingale 123bf21cd93STycho Nightingale /* Capability Identification Numbers */ 124bf21cd93STycho Nightingale 125bf21cd93STycho Nightingale #define PCIY_PMG 0x01 /* PCI Power Management */ 126bf21cd93STycho Nightingale #define PCIY_AGP 0x02 /* AGP */ 127bf21cd93STycho Nightingale #define PCIY_VPD 0x03 /* Vital Product Data */ 128bf21cd93STycho Nightingale #define PCIY_SLOTID 0x04 /* Slot Identification */ 129bf21cd93STycho Nightingale #define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 130bf21cd93STycho Nightingale #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 131bf21cd93STycho Nightingale #define PCIY_PCIX 0x07 /* PCI-X */ 132bf21cd93STycho Nightingale #define PCIY_HT 0x08 /* HyperTransport */ 133bf21cd93STycho Nightingale #define PCIY_VENDOR 0x09 /* Vendor Unique */ 134bf21cd93STycho Nightingale #define PCIY_DEBUG 0x0a /* Debug port */ 135bf21cd93STycho Nightingale #define PCIY_CRES 0x0b /* CompactPCI central resource control */ 136bf21cd93STycho Nightingale #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 137bf21cd93STycho Nightingale #define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */ 138bf21cd93STycho Nightingale #define PCIY_AGP8X 0x0e /* AGP 8x */ 139bf21cd93STycho Nightingale #define PCIY_SECDEV 0x0f /* Secure Device */ 140bf21cd93STycho Nightingale #define PCIY_EXPRESS 0x10 /* PCI Express */ 141bf21cd93STycho Nightingale #define PCIY_MSIX 0x11 /* MSI-X */ 142bf21cd93STycho Nightingale #define PCIY_SATA 0x12 /* SATA */ 143bf21cd93STycho Nightingale #define PCIY_PCIAF 0x13 /* PCI Advanced Features */ 144bf21cd93STycho Nightingale 145bf21cd93STycho Nightingale /* Extended Capability Register Fields */ 146bf21cd93STycho Nightingale 147bf21cd93STycho Nightingale #define PCIR_EXTCAP 0x100 148bf21cd93STycho Nightingale #define PCIM_EXTCAP_ID 0x0000ffff 149bf21cd93STycho Nightingale #define PCIM_EXTCAP_VER 0x000f0000 150bf21cd93STycho Nightingale #define PCIM_EXTCAP_NEXTPTR 0xfff00000 151bf21cd93STycho Nightingale #define PCI_EXTCAP_ID(ecap) ((ecap) & PCIM_EXTCAP_ID) 152bf21cd93STycho Nightingale #define PCI_EXTCAP_VER(ecap) (((ecap) & PCIM_EXTCAP_VER) >> 16) 153bf21cd93STycho Nightingale #define PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20) 154bf21cd93STycho Nightingale 155bf21cd93STycho Nightingale /* Extended Capability Identification Numbers */ 156bf21cd93STycho Nightingale 157bf21cd93STycho Nightingale #define PCIZ_AER 0x0001 /* Advanced Error Reporting */ 158bf21cd93STycho Nightingale #define PCIZ_VC 0x0002 /* Virtual Channel if MFVC Ext Cap not set */ 159bf21cd93STycho Nightingale #define PCIZ_SERNUM 0x0003 /* Device Serial Number */ 160bf21cd93STycho Nightingale #define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */ 161bf21cd93STycho Nightingale #define PCIZ_RCLINK_DCL 0x0005 /* Root Complex Link Declaration */ 162bf21cd93STycho Nightingale #define PCIZ_RCLINK_CTL 0x0006 /* Root Complex Internal Link Control */ 163bf21cd93STycho Nightingale #define PCIZ_RCEC_ASSOC 0x0007 /* Root Complex Event Collector Association */ 164bf21cd93STycho Nightingale #define PCIZ_MFVC 0x0008 /* Multi-Function Virtual Channel */ 165bf21cd93STycho Nightingale #define PCIZ_VC2 0x0009 /* Virtual Channel if MFVC Ext Cap set */ 166bf21cd93STycho Nightingale #define PCIZ_RCRB 0x000a /* RCRB Header */ 167bf21cd93STycho Nightingale #define PCIZ_VENDOR 0x000b /* Vendor Unique */ 168bf21cd93STycho Nightingale #define PCIZ_CAC 0x000c /* Configuration Access Correction -- obsolete */ 169bf21cd93STycho Nightingale #define PCIZ_ACS 0x000d /* Access Control Services */ 170bf21cd93STycho Nightingale #define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */ 171bf21cd93STycho Nightingale #define PCIZ_ATS 0x000f /* Address Translation Services */ 172bf21cd93STycho Nightingale #define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */ 173bf21cd93STycho Nightingale #define PCIZ_MRIOV 0x0011 /* Multiple Root IO Virtualization */ 174bf21cd93STycho Nightingale #define PCIZ_MULTICAST 0x0012 /* Multicast */ 175bf21cd93STycho Nightingale #define PCIZ_PAGE_REQ 0x0013 /* Page Request */ 176bf21cd93STycho Nightingale #define PCIZ_AMD 0x0014 /* Reserved for AMD */ 177bf21cd93STycho Nightingale #define PCIZ_RESIZE_BAR 0x0015 /* Resizable BAR */ 178bf21cd93STycho Nightingale #define PCIZ_DPA 0x0016 /* Dynamic Power Allocation */ 179bf21cd93STycho Nightingale #define PCIZ_TPH_REQ 0x0017 /* TPH Requester */ 180bf21cd93STycho Nightingale #define PCIZ_LTR 0x0018 /* Latency Tolerance Reporting */ 181bf21cd93STycho Nightingale #define PCIZ_SEC_PCIE 0x0019 /* Secondary PCI Express */ 182bf21cd93STycho Nightingale #define PCIZ_PMUX 0x001a /* Protocol Multiplexing */ 183bf21cd93STycho Nightingale #define PCIZ_PASID 0x001b /* Process Address Space ID */ 184bf21cd93STycho Nightingale #define PCIZ_LN_REQ 0x001c /* LN Requester */ 185bf21cd93STycho Nightingale #define PCIZ_DPC 0x001d /* Downstream Porto Containment */ 186bf21cd93STycho Nightingale #define PCIZ_L1PM 0x001e /* L1 PM Substates */ 187bf21cd93STycho Nightingale 188bf21cd93STycho Nightingale /* config registers for header type 0 devices */ 189bf21cd93STycho Nightingale 190bf21cd93STycho Nightingale #define PCIR_BARS 0x10 191bf21cd93STycho Nightingale #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 192bf21cd93STycho Nightingale #define PCIR_MAX_BAR_0 5 193bf21cd93STycho Nightingale #define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4) 194bf21cd93STycho Nightingale #define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) 195bf21cd93STycho Nightingale #define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE) 196bf21cd93STycho Nightingale #define PCIM_BAR_SPACE 0x00000001 197bf21cd93STycho Nightingale #define PCIM_BAR_MEM_SPACE 0 198bf21cd93STycho Nightingale #define PCIM_BAR_IO_SPACE 1 199bf21cd93STycho Nightingale #define PCIM_BAR_MEM_TYPE 0x00000006 200bf21cd93STycho Nightingale #define PCIM_BAR_MEM_32 0 201bf21cd93STycho Nightingale #define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */ 202bf21cd93STycho Nightingale #define PCIM_BAR_MEM_64 4 203bf21cd93STycho Nightingale #define PCIM_BAR_MEM_PREFETCH 0x00000008 204bf21cd93STycho Nightingale #define PCIM_BAR_MEM_BASE 0xfffffffffffffff0ULL 205bf21cd93STycho Nightingale #define PCIM_BAR_IO_RESERVED 0x00000002 206bf21cd93STycho Nightingale #define PCIM_BAR_IO_BASE 0xfffffffc 207bf21cd93STycho Nightingale #define PCIR_CIS 0x28 208bf21cd93STycho Nightingale #define PCIM_CIS_ASI_MASK 0x00000007 209bf21cd93STycho Nightingale #define PCIM_CIS_ASI_CONFIG 0 210bf21cd93STycho Nightingale #define PCIM_CIS_ASI_BAR0 1 211bf21cd93STycho Nightingale #define PCIM_CIS_ASI_BAR1 2 212bf21cd93STycho Nightingale #define PCIM_CIS_ASI_BAR2 3 213bf21cd93STycho Nightingale #define PCIM_CIS_ASI_BAR3 4 214bf21cd93STycho Nightingale #define PCIM_CIS_ASI_BAR4 5 215bf21cd93STycho Nightingale #define PCIM_CIS_ASI_BAR5 6 216bf21cd93STycho Nightingale #define PCIM_CIS_ASI_ROM 7 217bf21cd93STycho Nightingale #define PCIM_CIS_ADDR_MASK 0x0ffffff8 218bf21cd93STycho Nightingale #define PCIM_CIS_ROM_MASK 0xf0000000 219bf21cd93STycho Nightingale #define PCIM_CIS_CONFIG_MASK 0xff 220bf21cd93STycho Nightingale #define PCIR_SUBVEND_0 0x2c 221bf21cd93STycho Nightingale #define PCIR_SUBDEV_0 0x2e 222bf21cd93STycho Nightingale #define PCIR_BIOS 0x30 223bf21cd93STycho Nightingale #define PCIM_BIOS_ENABLE 0x01 224bf21cd93STycho Nightingale #define PCIM_BIOS_ADDR_MASK 0xfffff800 225bf21cd93STycho Nightingale #define PCIR_CAP_PTR 0x34 226bf21cd93STycho Nightingale #define PCIR_INTLINE 0x3c 227bf21cd93STycho Nightingale #define PCIR_INTPIN 0x3d 228bf21cd93STycho Nightingale #define PCIR_MINGNT 0x3e 229bf21cd93STycho Nightingale #define PCIR_MAXLAT 0x3f 230bf21cd93STycho Nightingale 231bf21cd93STycho Nightingale /* config registers for header type 1 (PCI-to-PCI bridge) devices */ 232bf21cd93STycho Nightingale 233bf21cd93STycho Nightingale #define PCIR_MAX_BAR_1 1 234bf21cd93STycho Nightingale #define PCIR_SECSTAT_1 0x1e 235bf21cd93STycho Nightingale 236bf21cd93STycho Nightingale #define PCIR_PRIBUS_1 0x18 237bf21cd93STycho Nightingale #define PCIR_SECBUS_1 0x19 238bf21cd93STycho Nightingale #define PCIR_SUBBUS_1 0x1a 239bf21cd93STycho Nightingale #define PCIR_SECLAT_1 0x1b 240bf21cd93STycho Nightingale 241bf21cd93STycho Nightingale #define PCIR_IOBASEL_1 0x1c 242bf21cd93STycho Nightingale #define PCIR_IOLIMITL_1 0x1d 243bf21cd93STycho Nightingale #define PCIR_IOBASEH_1 0x30 244bf21cd93STycho Nightingale #define PCIR_IOLIMITH_1 0x32 245bf21cd93STycho Nightingale #define PCIM_BRIO_16 0x0 246bf21cd93STycho Nightingale #define PCIM_BRIO_32 0x1 247bf21cd93STycho Nightingale #define PCIM_BRIO_MASK 0xf 248bf21cd93STycho Nightingale 249bf21cd93STycho Nightingale #define PCIR_MEMBASE_1 0x20 250bf21cd93STycho Nightingale #define PCIR_MEMLIMIT_1 0x22 251bf21cd93STycho Nightingale 252bf21cd93STycho Nightingale #define PCIR_PMBASEL_1 0x24 253bf21cd93STycho Nightingale #define PCIR_PMLIMITL_1 0x26 254bf21cd93STycho Nightingale #define PCIR_PMBASEH_1 0x28 255bf21cd93STycho Nightingale #define PCIR_PMLIMITH_1 0x2c 256bf21cd93STycho Nightingale #define PCIM_BRPM_32 0x0 257bf21cd93STycho Nightingale #define PCIM_BRPM_64 0x1 258bf21cd93STycho Nightingale #define PCIM_BRPM_MASK 0xf 259bf21cd93STycho Nightingale 260bf21cd93STycho Nightingale #define PCIR_BIOS_1 0x38 261bf21cd93STycho Nightingale #define PCIR_BRIDGECTL_1 0x3e 262bf21cd93STycho Nightingale 263bf21cd93STycho Nightingale /* config registers for header type 2 (CardBus) devices */ 264bf21cd93STycho Nightingale 265bf21cd93STycho Nightingale #define PCIR_MAX_BAR_2 0 266bf21cd93STycho Nightingale #define PCIR_CAP_PTR_2 0x14 267bf21cd93STycho Nightingale #define PCIR_SECSTAT_2 0x16 268bf21cd93STycho Nightingale 269bf21cd93STycho Nightingale #define PCIR_PRIBUS_2 0x18 270bf21cd93STycho Nightingale #define PCIR_SECBUS_2 0x19 271bf21cd93STycho Nightingale #define PCIR_SUBBUS_2 0x1a 272bf21cd93STycho Nightingale #define PCIR_SECLAT_2 0x1b 273bf21cd93STycho Nightingale 274bf21cd93STycho Nightingale #define PCIR_MEMBASE0_2 0x1c 275bf21cd93STycho Nightingale #define PCIR_MEMLIMIT0_2 0x20 276bf21cd93STycho Nightingale #define PCIR_MEMBASE1_2 0x24 277bf21cd93STycho Nightingale #define PCIR_MEMLIMIT1_2 0x28 278bf21cd93STycho Nightingale #define PCIR_IOBASE0_2 0x2c 279bf21cd93STycho Nightingale #define PCIR_IOLIMIT0_2 0x30 280bf21cd93STycho Nightingale #define PCIR_IOBASE1_2 0x34 281bf21cd93STycho Nightingale #define PCIR_IOLIMIT1_2 0x38 282bf21cd93STycho Nightingale 283bf21cd93STycho Nightingale #define PCIR_BRIDGECTL_2 0x3e 284bf21cd93STycho Nightingale 285bf21cd93STycho Nightingale #define PCIR_SUBVEND_2 0x40 286bf21cd93STycho Nightingale #define PCIR_SUBDEV_2 0x42 287bf21cd93STycho Nightingale 288bf21cd93STycho Nightingale #define PCIR_PCCARDIF_2 0x44 289bf21cd93STycho Nightingale 290bf21cd93STycho Nightingale /* PCI device class, subclass and programming interface definitions */ 291bf21cd93STycho Nightingale 292bf21cd93STycho Nightingale #define PCIC_OLD 0x00 293bf21cd93STycho Nightingale #define PCIS_OLD_NONVGA 0x00 294bf21cd93STycho Nightingale #define PCIS_OLD_VGA 0x01 295bf21cd93STycho Nightingale 296bf21cd93STycho Nightingale #define PCIC_STORAGE 0x01 297bf21cd93STycho Nightingale #define PCIS_STORAGE_SCSI 0x00 298bf21cd93STycho Nightingale #define PCIS_STORAGE_IDE 0x01 299bf21cd93STycho Nightingale #define PCIP_STORAGE_IDE_MODEPRIM 0x01 300bf21cd93STycho Nightingale #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 301bf21cd93STycho Nightingale #define PCIP_STORAGE_IDE_MODESEC 0x04 302bf21cd93STycho Nightingale #define PCIP_STORAGE_IDE_PROGINDSEC 0x08 303bf21cd93STycho Nightingale #define PCIP_STORAGE_IDE_MASTERDEV 0x80 304bf21cd93STycho Nightingale #define PCIS_STORAGE_FLOPPY 0x02 305bf21cd93STycho Nightingale #define PCIS_STORAGE_IPI 0x03 306bf21cd93STycho Nightingale #define PCIS_STORAGE_RAID 0x04 307bf21cd93STycho Nightingale #define PCIS_STORAGE_ATA_ADMA 0x05 308bf21cd93STycho Nightingale #define PCIS_STORAGE_SATA 0x06 309bf21cd93STycho Nightingale #define PCIP_STORAGE_SATA_AHCI_1_0 0x01 310bf21cd93STycho Nightingale #define PCIS_STORAGE_SAS 0x07 311bf21cd93STycho Nightingale #define PCIS_STORAGE_NVM 0x08 312bf21cd93STycho Nightingale #define PCIP_STORAGE_NVM_NVMHCI_1_0 0x01 313bf21cd93STycho Nightingale #define PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0 0x02 314bf21cd93STycho Nightingale #define PCIS_STORAGE_OTHER 0x80 315bf21cd93STycho Nightingale 316bf21cd93STycho Nightingale #define PCIC_NETWORK 0x02 317bf21cd93STycho Nightingale #define PCIS_NETWORK_ETHERNET 0x00 318bf21cd93STycho Nightingale #define PCIS_NETWORK_TOKENRING 0x01 319bf21cd93STycho Nightingale #define PCIS_NETWORK_FDDI 0x02 320bf21cd93STycho Nightingale #define PCIS_NETWORK_ATM 0x03 321bf21cd93STycho Nightingale #define PCIS_NETWORK_ISDN 0x04 322bf21cd93STycho Nightingale #define PCIS_NETWORK_WORLDFIP 0x05 323bf21cd93STycho Nightingale #define PCIS_NETWORK_PICMG 0x06 324bf21cd93STycho Nightingale #define PCIS_NETWORK_OTHER 0x80 325bf21cd93STycho Nightingale 326bf21cd93STycho Nightingale #define PCIC_DISPLAY 0x03 327bf21cd93STycho Nightingale #define PCIS_DISPLAY_VGA 0x00 328bf21cd93STycho Nightingale #define PCIS_DISPLAY_XGA 0x01 329bf21cd93STycho Nightingale #define PCIS_DISPLAY_3D 0x02 330bf21cd93STycho Nightingale #define PCIS_DISPLAY_OTHER 0x80 331bf21cd93STycho Nightingale 332bf21cd93STycho Nightingale #define PCIC_MULTIMEDIA 0x04 333bf21cd93STycho Nightingale #define PCIS_MULTIMEDIA_VIDEO 0x00 334bf21cd93STycho Nightingale #define PCIS_MULTIMEDIA_AUDIO 0x01 335bf21cd93STycho Nightingale #define PCIS_MULTIMEDIA_TELE 0x02 336bf21cd93STycho Nightingale #define PCIS_MULTIMEDIA_HDA 0x03 337bf21cd93STycho Nightingale #define PCIS_MULTIMEDIA_OTHER 0x80 338bf21cd93STycho Nightingale 339bf21cd93STycho Nightingale #define PCIC_MEMORY 0x05 340bf21cd93STycho Nightingale #define PCIS_MEMORY_RAM 0x00 341bf21cd93STycho Nightingale #define PCIS_MEMORY_FLASH 0x01 342bf21cd93STycho Nightingale #define PCIS_MEMORY_OTHER 0x80 343bf21cd93STycho Nightingale 344bf21cd93STycho Nightingale #define PCIC_BRIDGE 0x06 345bf21cd93STycho Nightingale #define PCIS_BRIDGE_HOST 0x00 346bf21cd93STycho Nightingale #define PCIS_BRIDGE_ISA 0x01 347bf21cd93STycho Nightingale #define PCIS_BRIDGE_EISA 0x02 348bf21cd93STycho Nightingale #define PCIS_BRIDGE_MCA 0x03 349bf21cd93STycho Nightingale #define PCIS_BRIDGE_PCI 0x04 350bf21cd93STycho Nightingale #define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01 351bf21cd93STycho Nightingale #define PCIS_BRIDGE_PCMCIA 0x05 352bf21cd93STycho Nightingale #define PCIS_BRIDGE_NUBUS 0x06 353bf21cd93STycho Nightingale #define PCIS_BRIDGE_CARDBUS 0x07 354bf21cd93STycho Nightingale #define PCIS_BRIDGE_RACEWAY 0x08 355bf21cd93STycho Nightingale #define PCIS_BRIDGE_PCI_TRANSPARENT 0x09 356bf21cd93STycho Nightingale #define PCIS_BRIDGE_INFINIBAND 0x0a 357bf21cd93STycho Nightingale #define PCIS_BRIDGE_OTHER 0x80 358bf21cd93STycho Nightingale 359bf21cd93STycho Nightingale #define PCIC_SIMPLECOMM 0x07 360bf21cd93STycho Nightingale #define PCIS_SIMPLECOMM_UART 0x00 361bf21cd93STycho Nightingale #define PCIP_SIMPLECOMM_UART_8250 0x00 362bf21cd93STycho Nightingale #define PCIP_SIMPLECOMM_UART_16450A 0x01 363bf21cd93STycho Nightingale #define PCIP_SIMPLECOMM_UART_16550A 0x02 364bf21cd93STycho Nightingale #define PCIP_SIMPLECOMM_UART_16650A 0x03 365bf21cd93STycho Nightingale #define PCIP_SIMPLECOMM_UART_16750A 0x04 366bf21cd93STycho Nightingale #define PCIP_SIMPLECOMM_UART_16850A 0x05 367bf21cd93STycho Nightingale #define PCIP_SIMPLECOMM_UART_16950A 0x06 368bf21cd93STycho Nightingale #define PCIS_SIMPLECOMM_PAR 0x01 369bf21cd93STycho Nightingale #define PCIS_SIMPLECOMM_MULSER 0x02 370bf21cd93STycho Nightingale #define PCIS_SIMPLECOMM_MODEM 0x03 371bf21cd93STycho Nightingale #define PCIS_SIMPLECOMM_GPIB 0x04 372bf21cd93STycho Nightingale #define PCIS_SIMPLECOMM_SMART_CARD 0x05 373bf21cd93STycho Nightingale #define PCIS_SIMPLECOMM_OTHER 0x80 374bf21cd93STycho Nightingale 375bf21cd93STycho Nightingale #define PCIC_BASEPERIPH 0x08 376bf21cd93STycho Nightingale #define PCIS_BASEPERIPH_PIC 0x00 377bf21cd93STycho Nightingale #define PCIP_BASEPERIPH_PIC_8259A 0x00 378bf21cd93STycho Nightingale #define PCIP_BASEPERIPH_PIC_ISA 0x01 379bf21cd93STycho Nightingale #define PCIP_BASEPERIPH_PIC_EISA 0x02 380bf21cd93STycho Nightingale #define PCIP_BASEPERIPH_PIC_IO_APIC 0x10 381bf21cd93STycho Nightingale #define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20 382bf21cd93STycho Nightingale #define PCIS_BASEPERIPH_DMA 0x01 383bf21cd93STycho Nightingale #define PCIS_BASEPERIPH_TIMER 0x02 384bf21cd93STycho Nightingale #define PCIS_BASEPERIPH_RTC 0x03 385bf21cd93STycho Nightingale #define PCIS_BASEPERIPH_PCIHOT 0x04 386bf21cd93STycho Nightingale #define PCIS_BASEPERIPH_SDHC 0x05 387bf21cd93STycho Nightingale #define PCIS_BASEPERIPH_IOMMU 0x06 388bf21cd93STycho Nightingale #define PCIS_BASEPERIPH_OTHER 0x80 389bf21cd93STycho Nightingale 390bf21cd93STycho Nightingale #define PCIC_INPUTDEV 0x09 391bf21cd93STycho Nightingale #define PCIS_INPUTDEV_KEYBOARD 0x00 392bf21cd93STycho Nightingale #define PCIS_INPUTDEV_DIGITIZER 0x01 393bf21cd93STycho Nightingale #define PCIS_INPUTDEV_MOUSE 0x02 394bf21cd93STycho Nightingale #define PCIS_INPUTDEV_SCANNER 0x03 395bf21cd93STycho Nightingale #define PCIS_INPUTDEV_GAMEPORT 0x04 396bf21cd93STycho Nightingale #define PCIS_INPUTDEV_OTHER 0x80 397bf21cd93STycho Nightingale 398bf21cd93STycho Nightingale #define PCIC_DOCKING 0x0a 399bf21cd93STycho Nightingale #define PCIS_DOCKING_GENERIC 0x00 400bf21cd93STycho Nightingale #define PCIS_DOCKING_OTHER 0x80 401bf21cd93STycho Nightingale 402bf21cd93STycho Nightingale #define PCIC_PROCESSOR 0x0b 403bf21cd93STycho Nightingale #define PCIS_PROCESSOR_386 0x00 404bf21cd93STycho Nightingale #define PCIS_PROCESSOR_486 0x01 405bf21cd93STycho Nightingale #define PCIS_PROCESSOR_PENTIUM 0x02 406bf21cd93STycho Nightingale #define PCIS_PROCESSOR_ALPHA 0x10 407bf21cd93STycho Nightingale #define PCIS_PROCESSOR_POWERPC 0x20 408bf21cd93STycho Nightingale #define PCIS_PROCESSOR_MIPS 0x30 409bf21cd93STycho Nightingale #define PCIS_PROCESSOR_COPROC 0x40 410bf21cd93STycho Nightingale 411bf21cd93STycho Nightingale #define PCIC_SERIALBUS 0x0c 412bf21cd93STycho Nightingale #define PCIS_SERIALBUS_FW 0x00 413bf21cd93STycho Nightingale #define PCIS_SERIALBUS_ACCESS 0x01 414bf21cd93STycho Nightingale #define PCIS_SERIALBUS_SSA 0x02 415bf21cd93STycho Nightingale #define PCIS_SERIALBUS_USB 0x03 416bf21cd93STycho Nightingale #define PCIP_SERIALBUS_USB_UHCI 0x00 417bf21cd93STycho Nightingale #define PCIP_SERIALBUS_USB_OHCI 0x10 418bf21cd93STycho Nightingale #define PCIP_SERIALBUS_USB_EHCI 0x20 419bf21cd93STycho Nightingale #define PCIP_SERIALBUS_USB_XHCI 0x30 420bf21cd93STycho Nightingale #define PCIP_SERIALBUS_USB_DEVICE 0xfe 421bf21cd93STycho Nightingale #define PCIS_SERIALBUS_FC 0x04 422bf21cd93STycho Nightingale #define PCIS_SERIALBUS_SMBUS 0x05 423bf21cd93STycho Nightingale #define PCIS_SERIALBUS_INFINIBAND 0x06 424bf21cd93STycho Nightingale #define PCIS_SERIALBUS_IPMI 0x07 425bf21cd93STycho Nightingale #define PCIP_SERIALBUS_IPMI_SMIC 0x00 426bf21cd93STycho Nightingale #define PCIP_SERIALBUS_IPMI_KCS 0x01 427bf21cd93STycho Nightingale #define PCIP_SERIALBUS_IPMI_BT 0x02 428bf21cd93STycho Nightingale #define PCIS_SERIALBUS_SERCOS 0x08 429bf21cd93STycho Nightingale #define PCIS_SERIALBUS_CANBUS 0x09 430bf21cd93STycho Nightingale 431bf21cd93STycho Nightingale #define PCIC_WIRELESS 0x0d 432bf21cd93STycho Nightingale #define PCIS_WIRELESS_IRDA 0x00 433bf21cd93STycho Nightingale #define PCIS_WIRELESS_IR 0x01 434bf21cd93STycho Nightingale #define PCIS_WIRELESS_RF 0x10 435bf21cd93STycho Nightingale #define PCIS_WIRELESS_BLUETOOTH 0x11 436bf21cd93STycho Nightingale #define PCIS_WIRELESS_BROADBAND 0x12 437bf21cd93STycho Nightingale #define PCIS_WIRELESS_80211A 0x20 438bf21cd93STycho Nightingale #define PCIS_WIRELESS_80211B 0x21 439bf21cd93STycho Nightingale #define PCIS_WIRELESS_OTHER 0x80 440bf21cd93STycho Nightingale 441bf21cd93STycho Nightingale #define PCIC_INTELLIIO 0x0e 442bf21cd93STycho Nightingale #define PCIS_INTELLIIO_I2O 0x00 443bf21cd93STycho Nightingale 444bf21cd93STycho Nightingale #define PCIC_SATCOM 0x0f 445bf21cd93STycho Nightingale #define PCIS_SATCOM_TV 0x01 446bf21cd93STycho Nightingale #define PCIS_SATCOM_AUDIO 0x02 447bf21cd93STycho Nightingale #define PCIS_SATCOM_VOICE 0x03 448bf21cd93STycho Nightingale #define PCIS_SATCOM_DATA 0x04 449bf21cd93STycho Nightingale 450bf21cd93STycho Nightingale #define PCIC_CRYPTO 0x10 451bf21cd93STycho Nightingale #define PCIS_CRYPTO_NETCOMP 0x00 452bf21cd93STycho Nightingale #define PCIS_CRYPTO_ENTERTAIN 0x10 453bf21cd93STycho Nightingale #define PCIS_CRYPTO_OTHER 0x80 454bf21cd93STycho Nightingale 455bf21cd93STycho Nightingale #define PCIC_DASP 0x11 456bf21cd93STycho Nightingale #define PCIS_DASP_DPIO 0x00 457bf21cd93STycho Nightingale #define PCIS_DASP_PERFCNTRS 0x01 458bf21cd93STycho Nightingale #define PCIS_DASP_COMM_SYNC 0x10 459bf21cd93STycho Nightingale #define PCIS_DASP_MGMT_CARD 0x20 460bf21cd93STycho Nightingale #define PCIS_DASP_OTHER 0x80 461bf21cd93STycho Nightingale 462bf21cd93STycho Nightingale #define PCIC_OTHER 0xff 463bf21cd93STycho Nightingale 464bf21cd93STycho Nightingale /* Bridge Control Values. */ 465bf21cd93STycho Nightingale #define PCIB_BCR_PERR_ENABLE 0x0001 466bf21cd93STycho Nightingale #define PCIB_BCR_SERR_ENABLE 0x0002 467bf21cd93STycho Nightingale #define PCIB_BCR_ISA_ENABLE 0x0004 468bf21cd93STycho Nightingale #define PCIB_BCR_VGA_ENABLE 0x0008 469bf21cd93STycho Nightingale #define PCIB_BCR_MASTER_ABORT_MODE 0x0020 470bf21cd93STycho Nightingale #define PCIB_BCR_SECBUS_RESET 0x0040 471bf21cd93STycho Nightingale #define PCIB_BCR_SECBUS_BACKTOBACK 0x0080 472bf21cd93STycho Nightingale #define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100 473bf21cd93STycho Nightingale #define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200 474bf21cd93STycho Nightingale #define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400 475bf21cd93STycho Nightingale #define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800 476bf21cd93STycho Nightingale 477bf21cd93STycho Nightingale /* PCI power manangement */ 478bf21cd93STycho Nightingale #define PCIR_POWER_CAP 0x2 479bf21cd93STycho Nightingale #define PCIM_PCAP_SPEC 0x0007 480bf21cd93STycho Nightingale #define PCIM_PCAP_PMEREQCLK 0x0008 481bf21cd93STycho Nightingale #define PCIM_PCAP_DEVSPECINIT 0x0020 482bf21cd93STycho Nightingale #define PCIM_PCAP_AUXPWR_0 0x0000 483bf21cd93STycho Nightingale #define PCIM_PCAP_AUXPWR_55 0x0040 484bf21cd93STycho Nightingale #define PCIM_PCAP_AUXPWR_100 0x0080 485bf21cd93STycho Nightingale #define PCIM_PCAP_AUXPWR_160 0x00c0 486bf21cd93STycho Nightingale #define PCIM_PCAP_AUXPWR_220 0x0100 487bf21cd93STycho Nightingale #define PCIM_PCAP_AUXPWR_270 0x0140 488bf21cd93STycho Nightingale #define PCIM_PCAP_AUXPWR_320 0x0180 489bf21cd93STycho Nightingale #define PCIM_PCAP_AUXPWR_375 0x01c0 490bf21cd93STycho Nightingale #define PCIM_PCAP_AUXPWRMASK 0x01c0 491bf21cd93STycho Nightingale #define PCIM_PCAP_D1SUPP 0x0200 492bf21cd93STycho Nightingale #define PCIM_PCAP_D2SUPP 0x0400 493bf21cd93STycho Nightingale #define PCIM_PCAP_D0PME 0x0800 494bf21cd93STycho Nightingale #define PCIM_PCAP_D1PME 0x1000 495bf21cd93STycho Nightingale #define PCIM_PCAP_D2PME 0x2000 496bf21cd93STycho Nightingale #define PCIM_PCAP_D3PME_HOT 0x4000 497bf21cd93STycho Nightingale #define PCIM_PCAP_D3PME_COLD 0x8000 498bf21cd93STycho Nightingale 499bf21cd93STycho Nightingale #define PCIR_POWER_STATUS 0x4 500bf21cd93STycho Nightingale #define PCIM_PSTAT_D0 0x0000 501bf21cd93STycho Nightingale #define PCIM_PSTAT_D1 0x0001 502bf21cd93STycho Nightingale #define PCIM_PSTAT_D2 0x0002 503bf21cd93STycho Nightingale #define PCIM_PSTAT_D3 0x0003 504bf21cd93STycho Nightingale #define PCIM_PSTAT_DMASK 0x0003 505bf21cd93STycho Nightingale #define PCIM_PSTAT_NOSOFTRESET 0x0008 506bf21cd93STycho Nightingale #define PCIM_PSTAT_PMEENABLE 0x0100 507bf21cd93STycho Nightingale #define PCIM_PSTAT_D0POWER 0x0000 508bf21cd93STycho Nightingale #define PCIM_PSTAT_D1POWER 0x0200 509bf21cd93STycho Nightingale #define PCIM_PSTAT_D2POWER 0x0400 510bf21cd93STycho Nightingale #define PCIM_PSTAT_D3POWER 0x0600 511bf21cd93STycho Nightingale #define PCIM_PSTAT_D0HEAT 0x0800 512bf21cd93STycho Nightingale #define PCIM_PSTAT_D1HEAT 0x0a00 513bf21cd93STycho Nightingale #define PCIM_PSTAT_D2HEAT 0x0c00 514bf21cd93STycho Nightingale #define PCIM_PSTAT_D3HEAT 0x0e00 515bf21cd93STycho Nightingale #define PCIM_PSTAT_DATASELMASK 0x1e00 516bf21cd93STycho Nightingale #define PCIM_PSTAT_DATAUNKN 0x0000 517bf21cd93STycho Nightingale #define PCIM_PSTAT_DATADIV10 0x2000 518bf21cd93STycho Nightingale #define PCIM_PSTAT_DATADIV100 0x4000 519bf21cd93STycho Nightingale #define PCIM_PSTAT_DATADIV1000 0x6000 520bf21cd93STycho Nightingale #define PCIM_PSTAT_DATADIVMASK 0x6000 521bf21cd93STycho Nightingale #define PCIM_PSTAT_PME 0x8000 522bf21cd93STycho Nightingale 523bf21cd93STycho Nightingale #define PCIR_POWER_BSE 0x6 524bf21cd93STycho Nightingale #define PCIM_PMCSR_BSE_D3B3 0x00 525bf21cd93STycho Nightingale #define PCIM_PMCSR_BSE_D3B2 0x40 526bf21cd93STycho Nightingale #define PCIM_PMCSR_BSE_BPCCE 0x80 527bf21cd93STycho Nightingale 528bf21cd93STycho Nightingale #define PCIR_POWER_DATA 0x7 529bf21cd93STycho Nightingale 530bf21cd93STycho Nightingale /* VPD capability registers */ 531bf21cd93STycho Nightingale #define PCIR_VPD_ADDR 0x2 532bf21cd93STycho Nightingale #define PCIR_VPD_DATA 0x4 533bf21cd93STycho Nightingale 534bf21cd93STycho Nightingale /* PCI Message Signalled Interrupts (MSI) */ 535bf21cd93STycho Nightingale #define PCIR_MSI_CTRL 0x2 536bf21cd93STycho Nightingale #define PCIM_MSICTRL_VECTOR 0x0100 537bf21cd93STycho Nightingale #define PCIM_MSICTRL_64BIT 0x0080 538bf21cd93STycho Nightingale #define PCIM_MSICTRL_MME_MASK 0x0070 539bf21cd93STycho Nightingale #define PCIM_MSICTRL_MME_1 0x0000 540bf21cd93STycho Nightingale #define PCIM_MSICTRL_MME_2 0x0010 541bf21cd93STycho Nightingale #define PCIM_MSICTRL_MME_4 0x0020 542bf21cd93STycho Nightingale #define PCIM_MSICTRL_MME_8 0x0030 543bf21cd93STycho Nightingale #define PCIM_MSICTRL_MME_16 0x0040 544bf21cd93STycho Nightingale #define PCIM_MSICTRL_MME_32 0x0050 545bf21cd93STycho Nightingale #define PCIM_MSICTRL_MMC_MASK 0x000E 546bf21cd93STycho Nightingale #define PCIM_MSICTRL_MMC_1 0x0000 547bf21cd93STycho Nightingale #define PCIM_MSICTRL_MMC_2 0x0002 548bf21cd93STycho Nightingale #define PCIM_MSICTRL_MMC_4 0x0004 549bf21cd93STycho Nightingale #define PCIM_MSICTRL_MMC_8 0x0006 550bf21cd93STycho Nightingale #define PCIM_MSICTRL_MMC_16 0x0008 551bf21cd93STycho Nightingale #define PCIM_MSICTRL_MMC_32 0x000A 552bf21cd93STycho Nightingale #define PCIM_MSICTRL_MSI_ENABLE 0x0001 553bf21cd93STycho Nightingale #define PCIR_MSI_ADDR 0x4 554bf21cd93STycho Nightingale #define PCIR_MSI_ADDR_HIGH 0x8 555bf21cd93STycho Nightingale #define PCIR_MSI_DATA 0x8 556bf21cd93STycho Nightingale #define PCIR_MSI_DATA_64BIT 0xc 557bf21cd93STycho Nightingale #define PCIR_MSI_MASK 0x10 558bf21cd93STycho Nightingale #define PCIR_MSI_PENDING 0x14 559bf21cd93STycho Nightingale 560bf21cd93STycho Nightingale /* PCI-X definitions */ 561bf21cd93STycho Nightingale 562bf21cd93STycho Nightingale /* For header type 0 devices */ 563bf21cd93STycho Nightingale #define PCIXR_COMMAND 0x2 564bf21cd93STycho Nightingale #define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */ 565bf21cd93STycho Nightingale #define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ 566bf21cd93STycho Nightingale #define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */ 567bf21cd93STycho Nightingale #define PCIXM_COMMAND_MAX_READ_512 0x0000 568bf21cd93STycho Nightingale #define PCIXM_COMMAND_MAX_READ_1024 0x0004 569bf21cd93STycho Nightingale #define PCIXM_COMMAND_MAX_READ_2048 0x0008 570bf21cd93STycho Nightingale #define PCIXM_COMMAND_MAX_READ_4096 0x000c 571bf21cd93STycho Nightingale #define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */ 572bf21cd93STycho Nightingale #define PCIXM_COMMAND_MAX_SPLITS_1 0x0000 573bf21cd93STycho Nightingale #define PCIXM_COMMAND_MAX_SPLITS_2 0x0010 574bf21cd93STycho Nightingale #define PCIXM_COMMAND_MAX_SPLITS_3 0x0020 575bf21cd93STycho Nightingale #define PCIXM_COMMAND_MAX_SPLITS_4 0x0030 576bf21cd93STycho Nightingale #define PCIXM_COMMAND_MAX_SPLITS_8 0x0040 577bf21cd93STycho Nightingale #define PCIXM_COMMAND_MAX_SPLITS_12 0x0050 578bf21cd93STycho Nightingale #define PCIXM_COMMAND_MAX_SPLITS_16 0x0060 579bf21cd93STycho Nightingale #define PCIXM_COMMAND_MAX_SPLITS_32 0x0070 580bf21cd93STycho Nightingale #define PCIXM_COMMAND_VERSION 0x3000 581bf21cd93STycho Nightingale #define PCIXR_STATUS 0x4 582bf21cd93STycho Nightingale #define PCIXM_STATUS_DEVFN 0x000000FF 583bf21cd93STycho Nightingale #define PCIXM_STATUS_BUS 0x0000FF00 584bf21cd93STycho Nightingale #define PCIXM_STATUS_64BIT 0x00010000 585bf21cd93STycho Nightingale #define PCIXM_STATUS_133CAP 0x00020000 586bf21cd93STycho Nightingale #define PCIXM_STATUS_SC_DISCARDED 0x00040000 587bf21cd93STycho Nightingale #define PCIXM_STATUS_UNEXP_SC 0x00080000 588bf21cd93STycho Nightingale #define PCIXM_STATUS_COMPLEX_DEV 0x00100000 589bf21cd93STycho Nightingale #define PCIXM_STATUS_MAX_READ 0x00600000 590bf21cd93STycho Nightingale #define PCIXM_STATUS_MAX_READ_512 0x00000000 591bf21cd93STycho Nightingale #define PCIXM_STATUS_MAX_READ_1024 0x00200000 592bf21cd93STycho Nightingale #define PCIXM_STATUS_MAX_READ_2048 0x00400000 593bf21cd93STycho Nightingale #define PCIXM_STATUS_MAX_READ_4096 0x00600000 594bf21cd93STycho Nightingale #define PCIXM_STATUS_MAX_SPLITS 0x03800000 595bf21cd93STycho Nightingale #define PCIXM_STATUS_MAX_SPLITS_1 0x00000000 596bf21cd93STycho Nightingale #define PCIXM_STATUS_MAX_SPLITS_2 0x00800000 597bf21cd93STycho Nightingale #define PCIXM_STATUS_MAX_SPLITS_3 0x01000000 598bf21cd93STycho Nightingale #define PCIXM_STATUS_MAX_SPLITS_4 0x01800000 599bf21cd93STycho Nightingale #define PCIXM_STATUS_MAX_SPLITS_8 0x02000000 600bf21cd93STycho Nightingale #define PCIXM_STATUS_MAX_SPLITS_12 0x02800000 601bf21cd93STycho Nightingale #define PCIXM_STATUS_MAX_SPLITS_16 0x03000000 602bf21cd93STycho Nightingale #define PCIXM_STATUS_MAX_SPLITS_32 0x03800000 603bf21cd93STycho Nightingale #define PCIXM_STATUS_MAX_CUM_READ 0x1C000000 604bf21cd93STycho Nightingale #define PCIXM_STATUS_RCVD_SC_ERR 0x20000000 605bf21cd93STycho Nightingale #define PCIXM_STATUS_266CAP 0x40000000 606bf21cd93STycho Nightingale #define PCIXM_STATUS_533CAP 0x80000000 607bf21cd93STycho Nightingale 608bf21cd93STycho Nightingale /* For header type 1 devices (PCI-X bridges) */ 609bf21cd93STycho Nightingale #define PCIXR_SEC_STATUS 0x2 610bf21cd93STycho Nightingale #define PCIXM_SEC_STATUS_64BIT 0x0001 611bf21cd93STycho Nightingale #define PCIXM_SEC_STATUS_133CAP 0x0002 612bf21cd93STycho Nightingale #define PCIXM_SEC_STATUS_SC_DISC 0x0004 613bf21cd93STycho Nightingale #define PCIXM_SEC_STATUS_UNEXP_SC 0x0008 614bf21cd93STycho Nightingale #define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010 615bf21cd93STycho Nightingale #define PCIXM_SEC_STATUS_SR_DELAYED 0x0020 616bf21cd93STycho Nightingale #define PCIXM_SEC_STATUS_BUS_MODE 0x03c0 617bf21cd93STycho Nightingale #define PCIXM_SEC_STATUS_VERSION 0x3000 618bf21cd93STycho Nightingale #define PCIXM_SEC_STATUS_266CAP 0x4000 619bf21cd93STycho Nightingale #define PCIXM_SEC_STATUS_533CAP 0x8000 620bf21cd93STycho Nightingale #define PCIXR_BRIDGE_STATUS 0x4 621bf21cd93STycho Nightingale #define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF 622bf21cd93STycho Nightingale #define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00 623bf21cd93STycho Nightingale #define PCIXM_BRIDGE_STATUS_64BIT 0x00010000 624bf21cd93STycho Nightingale #define PCIXM_BRIDGE_STATUS_133CAP 0x00020000 625bf21cd93STycho Nightingale #define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000 626bf21cd93STycho Nightingale #define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000 627bf21cd93STycho Nightingale #define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000 628bf21cd93STycho Nightingale #define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000 629bf21cd93STycho Nightingale #define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000 630bf21cd93STycho Nightingale #define PCIXM_BRIDGE_STATUS_266CAP 0x40000000 631bf21cd93STycho Nightingale #define PCIXM_BRIDGE_STATUS_533CAP 0x80000000 632bf21cd93STycho Nightingale 633bf21cd93STycho Nightingale /* HT (HyperTransport) Capability definitions */ 634bf21cd93STycho Nightingale #define PCIR_HT_COMMAND 0x2 635bf21cd93STycho Nightingale #define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ 636bf21cd93STycho Nightingale #define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ 637bf21cd93STycho Nightingale #define PCIM_HTCAP_HOST 0x2000 /* 001xx */ 638bf21cd93STycho Nightingale #define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ 639bf21cd93STycho Nightingale #define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ 640bf21cd93STycho Nightingale #define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ 641bf21cd93STycho Nightingale #define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */ 642bf21cd93STycho Nightingale #define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */ 643bf21cd93STycho Nightingale #define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */ 644bf21cd93STycho Nightingale #define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */ 645bf21cd93STycho Nightingale #define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */ 646bf21cd93STycho Nightingale #define PCIM_HTCAP_VCSET 0xb800 /* 10111 */ 647bf21cd93STycho Nightingale #define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */ 648bf21cd93STycho Nightingale #define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */ 649bf21cd93STycho Nightingale #define PCIM_HTCAP_GEN3 0xd000 /* 11010 */ 650bf21cd93STycho Nightingale #define PCIM_HTCAP_FLE 0xd800 /* 11011 */ 651bf21cd93STycho Nightingale #define PCIM_HTCAP_PM 0xe000 /* 11100 */ 652bf21cd93STycho Nightingale #define PCIM_HTCAP_HIGH_NODE_COUNT 0xe800 /* 11101 */ 653bf21cd93STycho Nightingale 654bf21cd93STycho Nightingale /* HT MSI Mapping Capability definitions. */ 655bf21cd93STycho Nightingale #define PCIM_HTCMD_MSI_ENABLE 0x0001 656bf21cd93STycho Nightingale #define PCIM_HTCMD_MSI_FIXED 0x0002 657bf21cd93STycho Nightingale #define PCIR_HTMSI_ADDRESS_LO 0x4 658bf21cd93STycho Nightingale #define PCIR_HTMSI_ADDRESS_HI 0x8 659bf21cd93STycho Nightingale 660bf21cd93STycho Nightingale /* PCI Vendor capability definitions */ 661bf21cd93STycho Nightingale #define PCIR_VENDOR_LENGTH 0x2 662bf21cd93STycho Nightingale #define PCIR_VENDOR_DATA 0x3 663bf21cd93STycho Nightingale 664bf21cd93STycho Nightingale /* PCI EHCI Debug Port definitions */ 665bf21cd93STycho Nightingale #define PCIR_DEBUG_PORT 0x2 666bf21cd93STycho Nightingale #define PCIM_DEBUG_PORT_OFFSET 0x1FFF 667bf21cd93STycho Nightingale #define PCIM_DEBUG_PORT_BAR 0xe000 668bf21cd93STycho Nightingale 669bf21cd93STycho Nightingale /* PCI-PCI Bridge Subvendor definitions */ 670bf21cd93STycho Nightingale #define PCIR_SUBVENDCAP_ID 0x4 671bf21cd93STycho Nightingale 672bf21cd93STycho Nightingale /* PCI Express definitions */ 673bf21cd93STycho Nightingale #define PCIER_FLAGS 0x2 674bf21cd93STycho Nightingale #define PCIEM_FLAGS_VERSION 0x000F 675bf21cd93STycho Nightingale #define PCIEM_FLAGS_TYPE 0x00F0 676bf21cd93STycho Nightingale #define PCIEM_TYPE_ENDPOINT 0x0000 677bf21cd93STycho Nightingale #define PCIEM_TYPE_LEGACY_ENDPOINT 0x0010 678bf21cd93STycho Nightingale #define PCIEM_TYPE_ROOT_PORT 0x0040 679bf21cd93STycho Nightingale #define PCIEM_TYPE_UPSTREAM_PORT 0x0050 680bf21cd93STycho Nightingale #define PCIEM_TYPE_DOWNSTREAM_PORT 0x0060 681bf21cd93STycho Nightingale #define PCIEM_TYPE_PCI_BRIDGE 0x0070 682bf21cd93STycho Nightingale #define PCIEM_TYPE_PCIE_BRIDGE 0x0080 683bf21cd93STycho Nightingale #define PCIEM_TYPE_ROOT_INT_EP 0x0090 684bf21cd93STycho Nightingale #define PCIEM_TYPE_ROOT_EC 0x00a0 685bf21cd93STycho Nightingale #define PCIEM_FLAGS_SLOT 0x0100 686bf21cd93STycho Nightingale #define PCIEM_FLAGS_IRQ 0x3e00 687bf21cd93STycho Nightingale #define PCIER_DEVICE_CAP 0x4 688bf21cd93STycho Nightingale #define PCIEM_CAP_MAX_PAYLOAD 0x00000007 689bf21cd93STycho Nightingale #define PCIEM_CAP_PHANTHOM_FUNCS 0x00000018 690bf21cd93STycho Nightingale #define PCIEM_CAP_EXT_TAG_FIELD 0x00000020 691bf21cd93STycho Nightingale #define PCIEM_CAP_L0S_LATENCY 0x000001c0 692bf21cd93STycho Nightingale #define PCIEM_CAP_L1_LATENCY 0x00000e00 693bf21cd93STycho Nightingale #define PCIEM_CAP_ROLE_ERR_RPT 0x00008000 694bf21cd93STycho Nightingale #define PCIEM_CAP_SLOT_PWR_LIM_VAL 0x03fc0000 695bf21cd93STycho Nightingale #define PCIEM_CAP_SLOT_PWR_LIM_SCALE 0x0c000000 696bf21cd93STycho Nightingale #define PCIEM_CAP_FLR 0x10000000 697bf21cd93STycho Nightingale #define PCIER_DEVICE_CTL 0x8 698bf21cd93STycho Nightingale #define PCIEM_CTL_COR_ENABLE 0x0001 699bf21cd93STycho Nightingale #define PCIEM_CTL_NFER_ENABLE 0x0002 700bf21cd93STycho Nightingale #define PCIEM_CTL_FER_ENABLE 0x0004 701bf21cd93STycho Nightingale #define PCIEM_CTL_URR_ENABLE 0x0008 702bf21cd93STycho Nightingale #define PCIEM_CTL_RELAXED_ORD_ENABLE 0x0010 703bf21cd93STycho Nightingale #define PCIEM_CTL_MAX_PAYLOAD 0x00e0 704bf21cd93STycho Nightingale #define PCIEM_CTL_EXT_TAG_FIELD 0x0100 705bf21cd93STycho Nightingale #define PCIEM_CTL_PHANTHOM_FUNCS 0x0200 706bf21cd93STycho Nightingale #define PCIEM_CTL_AUX_POWER_PM 0x0400 707bf21cd93STycho Nightingale #define PCIEM_CTL_NOSNOOP_ENABLE 0x0800 708bf21cd93STycho Nightingale #define PCIEM_CTL_MAX_READ_REQUEST 0x7000 709bf21cd93STycho Nightingale #define PCIEM_CTL_BRDG_CFG_RETRY 0x8000 /* PCI-E - PCI/PCI-X bridges */ 710bf21cd93STycho Nightingale #define PCIEM_CTL_INITIATE_FLR 0x8000 /* FLR capable endpoints */ 711bf21cd93STycho Nightingale #define PCIER_DEVICE_STA 0xa 712bf21cd93STycho Nightingale #define PCIEM_STA_CORRECTABLE_ERROR 0x0001 713bf21cd93STycho Nightingale #define PCIEM_STA_NON_FATAL_ERROR 0x0002 714bf21cd93STycho Nightingale #define PCIEM_STA_FATAL_ERROR 0x0004 715bf21cd93STycho Nightingale #define PCIEM_STA_UNSUPPORTED_REQ 0x0008 716bf21cd93STycho Nightingale #define PCIEM_STA_AUX_POWER 0x0010 717bf21cd93STycho Nightingale #define PCIEM_STA_TRANSACTION_PND 0x0020 718bf21cd93STycho Nightingale #define PCIER_LINK_CAP 0xc 719bf21cd93STycho Nightingale #define PCIEM_LINK_CAP_MAX_SPEED 0x0000000f 720bf21cd93STycho Nightingale #define PCIEM_LINK_CAP_MAX_WIDTH 0x000003f0 721bf21cd93STycho Nightingale #define PCIEM_LINK_CAP_ASPM 0x00000c00 722bf21cd93STycho Nightingale #define PCIEM_LINK_CAP_L0S_EXIT 0x00007000 723bf21cd93STycho Nightingale #define PCIEM_LINK_CAP_L1_EXIT 0x00038000 724bf21cd93STycho Nightingale #define PCIEM_LINK_CAP_CLOCK_PM 0x00040000 725bf21cd93STycho Nightingale #define PCIEM_LINK_CAP_SURPRISE_DOWN 0x00080000 726bf21cd93STycho Nightingale #define PCIEM_LINK_CAP_DL_ACTIVE 0x00100000 727bf21cd93STycho Nightingale #define PCIEM_LINK_CAP_LINK_BW_NOTIFY 0x00200000 728bf21cd93STycho Nightingale #define PCIEM_LINK_CAP_ASPM_COMPLIANCE 0x00400000 729bf21cd93STycho Nightingale #define PCIEM_LINK_CAP_PORT 0xff000000 730bf21cd93STycho Nightingale #define PCIER_LINK_CTL 0x10 731bf21cd93STycho Nightingale #define PCIEM_LINK_CTL_ASPMC_DIS 0x0000 732bf21cd93STycho Nightingale #define PCIEM_LINK_CTL_ASPMC_L0S 0x0001 733bf21cd93STycho Nightingale #define PCIEM_LINK_CTL_ASPMC_L1 0x0002 734bf21cd93STycho Nightingale #define PCIEM_LINK_CTL_ASPMC 0x0003 735bf21cd93STycho Nightingale #define PCIEM_LINK_CTL_RCB 0x0008 736bf21cd93STycho Nightingale #define PCIEM_LINK_CTL_LINK_DIS 0x0010 737bf21cd93STycho Nightingale #define PCIEM_LINK_CTL_RETRAIN_LINK 0x0020 738bf21cd93STycho Nightingale #define PCIEM_LINK_CTL_COMMON_CLOCK 0x0040 739bf21cd93STycho Nightingale #define PCIEM_LINK_CTL_EXTENDED_SYNC 0x0080 740bf21cd93STycho Nightingale #define PCIEM_LINK_CTL_ECPM 0x0100 741bf21cd93STycho Nightingale #define PCIEM_LINK_CTL_HAWD 0x0200 742bf21cd93STycho Nightingale #define PCIEM_LINK_CTL_LBMIE 0x0400 743bf21cd93STycho Nightingale #define PCIEM_LINK_CTL_LABIE 0x0800 744bf21cd93STycho Nightingale #define PCIER_LINK_STA 0x12 745bf21cd93STycho Nightingale #define PCIEM_LINK_STA_SPEED 0x000f 746bf21cd93STycho Nightingale #define PCIEM_LINK_STA_WIDTH 0x03f0 747bf21cd93STycho Nightingale #define PCIEM_LINK_STA_TRAINING_ERROR 0x0400 748bf21cd93STycho Nightingale #define PCIEM_LINK_STA_TRAINING 0x0800 749bf21cd93STycho Nightingale #define PCIEM_LINK_STA_SLOT_CLOCK 0x1000 750bf21cd93STycho Nightingale #define PCIEM_LINK_STA_DL_ACTIVE 0x2000 751bf21cd93STycho Nightingale #define PCIEM_LINK_STA_LINK_BW_MGMT 0x4000 752bf21cd93STycho Nightingale #define PCIEM_LINK_STA_LINK_AUTO_BW 0x8000 753bf21cd93STycho Nightingale #define PCIER_SLOT_CAP 0x14 754bf21cd93STycho Nightingale #define PCIEM_SLOT_CAP_APB 0x00000001 755bf21cd93STycho Nightingale #define PCIEM_SLOT_CAP_PCP 0x00000002 756bf21cd93STycho Nightingale #define PCIEM_SLOT_CAP_MRLSP 0x00000004 757bf21cd93STycho Nightingale #define PCIEM_SLOT_CAP_AIP 0x00000008 758bf21cd93STycho Nightingale #define PCIEM_SLOT_CAP_PIP 0x00000010 759bf21cd93STycho Nightingale #define PCIEM_SLOT_CAP_HPS 0x00000020 760bf21cd93STycho Nightingale #define PCIEM_SLOT_CAP_HPC 0x00000040 761bf21cd93STycho Nightingale #define PCIEM_SLOT_CAP_SPLV 0x00007f80 762bf21cd93STycho Nightingale #define PCIEM_SLOT_CAP_SPLS 0x00018000 763bf21cd93STycho Nightingale #define PCIEM_SLOT_CAP_EIP 0x00020000 764bf21cd93STycho Nightingale #define PCIEM_SLOT_CAP_NCCS 0x00040000 765bf21cd93STycho Nightingale #define PCIEM_SLOT_CAP_PSN 0xfff80000 766bf21cd93STycho Nightingale #define PCIER_SLOT_CTL 0x18 767bf21cd93STycho Nightingale #define PCIEM_SLOT_CTL_ABPE 0x0001 768bf21cd93STycho Nightingale #define PCIEM_SLOT_CTL_PFDE 0x0002 769bf21cd93STycho Nightingale #define PCIEM_SLOT_CTL_MRLSCE 0x0004 770bf21cd93STycho Nightingale #define PCIEM_SLOT_CTL_PDCE 0x0008 771bf21cd93STycho Nightingale #define PCIEM_SLOT_CTL_CCIE 0x0010 772bf21cd93STycho Nightingale #define PCIEM_SLOT_CTL_HPIE 0x0020 773bf21cd93STycho Nightingale #define PCIEM_SLOT_CTL_AIC 0x00c0 774bf21cd93STycho Nightingale #define PCIEM_SLOT_CTL_PIC 0x0300 775bf21cd93STycho Nightingale #define PCIEM_SLOT_CTL_PCC 0x0400 776bf21cd93STycho Nightingale #define PCIEM_SLOT_CTL_EIC 0x0800 777bf21cd93STycho Nightingale #define PCIEM_SLOT_CTL_DLLSCE 0x1000 778bf21cd93STycho Nightingale #define PCIER_SLOT_STA 0x1a 779bf21cd93STycho Nightingale #define PCIEM_SLOT_STA_ABP 0x0001 780bf21cd93STycho Nightingale #define PCIEM_SLOT_STA_PFD 0x0002 781bf21cd93STycho Nightingale #define PCIEM_SLOT_STA_MRLSC 0x0004 782bf21cd93STycho Nightingale #define PCIEM_SLOT_STA_PDC 0x0008 783bf21cd93STycho Nightingale #define PCIEM_SLOT_STA_CC 0x0010 784bf21cd93STycho Nightingale #define PCIEM_SLOT_STA_MRLSS 0x0020 785bf21cd93STycho Nightingale #define PCIEM_SLOT_STA_PDS 0x0040 786bf21cd93STycho Nightingale #define PCIEM_SLOT_STA_EIS 0x0080 787bf21cd93STycho Nightingale #define PCIEM_SLOT_STA_DLLSC 0x0100 788bf21cd93STycho Nightingale #define PCIER_ROOT_CTL 0x1c 789bf21cd93STycho Nightingale #define PCIEM_ROOT_CTL_SERR_CORR 0x0001 790bf21cd93STycho Nightingale #define PCIEM_ROOT_CTL_SERR_NONFATAL 0x0002 791bf21cd93STycho Nightingale #define PCIEM_ROOT_CTL_SERR_FATAL 0x0004 792bf21cd93STycho Nightingale #define PCIEM_ROOT_CTL_PME 0x0008 793bf21cd93STycho Nightingale #define PCIEM_ROOT_CTL_CRS_VIS 0x0010 794bf21cd93STycho Nightingale #define PCIER_ROOT_CAP 0x1e 795bf21cd93STycho Nightingale #define PCIEM_ROOT_CAP_CRS_VIS 0x0001 796bf21cd93STycho Nightingale #define PCIER_ROOT_STA 0x20 797bf21cd93STycho Nightingale #define PCIEM_ROOT_STA_PME_REQID_MASK 0x0000ffff 798bf21cd93STycho Nightingale #define PCIEM_ROOT_STA_PME_STATUS 0x00010000 799bf21cd93STycho Nightingale #define PCIEM_ROOT_STA_PME_PEND 0x00020000 800bf21cd93STycho Nightingale #define PCIER_DEVICE_CAP2 0x24 801bf21cd93STycho Nightingale #define PCIEM_CAP2_ARI 0x20 802bf21cd93STycho Nightingale #define PCIER_DEVICE_CTL2 0x28 803bf21cd93STycho Nightingale #define PCIEM_CTL2_COMP_TIMEOUT_VAL 0x000f 804bf21cd93STycho Nightingale #define PCIEM_CTL2_COMP_TIMEOUT_DIS 0x0010 805bf21cd93STycho Nightingale #define PCIEM_CTL2_ARI 0x0020 806bf21cd93STycho Nightingale #define PCIEM_CTL2_ATOMIC_REQ_ENABLE 0x0040 807bf21cd93STycho Nightingale #define PCIEM_CTL2_ATOMIC_EGR_BLOCK 0x0080 808bf21cd93STycho Nightingale #define PCIEM_CTL2_ID_ORDERED_REQ_EN 0x0100 809bf21cd93STycho Nightingale #define PCIEM_CTL2_ID_ORDERED_CMP_EN 0x0200 810bf21cd93STycho Nightingale #define PCIEM_CTL2_LTR_ENABLE 0x0400 811bf21cd93STycho Nightingale #define PCIEM_CTL2_OBFF 0x6000 812bf21cd93STycho Nightingale #define PCIEM_OBFF_DISABLE 0x0000 813bf21cd93STycho Nightingale #define PCIEM_OBFF_MSGA_ENABLE 0x2000 814bf21cd93STycho Nightingale #define PCIEM_OBFF_MSGB_ENABLE 0x4000 815bf21cd93STycho Nightingale #define PCIEM_OBFF_WAKE_ENABLE 0x6000 816bf21cd93STycho Nightingale #define PCIEM_CTL2_END2END_TLP 0x8000 817bf21cd93STycho Nightingale #define PCIER_DEVICE_STA2 0x2a 818bf21cd93STycho Nightingale #define PCIER_LINK_CAP2 0x2c 819bf21cd93STycho Nightingale #define PCIER_LINK_CTL2 0x30 820bf21cd93STycho Nightingale #define PCIER_LINK_STA2 0x32 821bf21cd93STycho Nightingale #define PCIER_SLOT_CAP2 0x34 822bf21cd93STycho Nightingale #define PCIER_SLOT_CTL2 0x38 823bf21cd93STycho Nightingale #define PCIER_SLOT_STA2 0x3a 824bf21cd93STycho Nightingale 825bf21cd93STycho Nightingale /* MSI-X definitions */ 826bf21cd93STycho Nightingale #define PCIR_MSIX_CTRL 0x2 827bf21cd93STycho Nightingale #define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000 828bf21cd93STycho Nightingale #define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000 829bf21cd93STycho Nightingale #define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF 830bf21cd93STycho Nightingale #define PCIR_MSIX_TABLE 0x4 831bf21cd93STycho Nightingale #define PCIR_MSIX_PBA 0x8 832bf21cd93STycho Nightingale #define PCIM_MSIX_BIR_MASK 0x7 833bf21cd93STycho Nightingale #define PCIM_MSIX_BIR_BAR_10 0 834bf21cd93STycho Nightingale #define PCIM_MSIX_BIR_BAR_14 1 835bf21cd93STycho Nightingale #define PCIM_MSIX_BIR_BAR_18 2 836bf21cd93STycho Nightingale #define PCIM_MSIX_BIR_BAR_1C 3 837bf21cd93STycho Nightingale #define PCIM_MSIX_BIR_BAR_20 4 838bf21cd93STycho Nightingale #define PCIM_MSIX_BIR_BAR_24 5 839bf21cd93STycho Nightingale #define PCIM_MSIX_VCTRL_MASK 0x1 840bf21cd93STycho Nightingale 841bf21cd93STycho Nightingale /* PCI Advanced Features definitions */ 842bf21cd93STycho Nightingale #define PCIR_PCIAF_CAP 0x3 843bf21cd93STycho Nightingale #define PCIM_PCIAFCAP_TP 0x01 844bf21cd93STycho Nightingale #define PCIM_PCIAFCAP_FLR 0x02 845bf21cd93STycho Nightingale #define PCIR_PCIAF_CTRL 0x4 846bf21cd93STycho Nightingale #define PCIR_PCIAFCTRL_FLR 0x01 847bf21cd93STycho Nightingale #define PCIR_PCIAF_STATUS 0x5 848bf21cd93STycho Nightingale #define PCIR_PCIAFSTATUS_TP 0x01 849bf21cd93STycho Nightingale 850bf21cd93STycho Nightingale /* Advanced Error Reporting */ 851bf21cd93STycho Nightingale #define PCIR_AER_UC_STATUS 0x04 852bf21cd93STycho Nightingale #define PCIM_AER_UC_TRAINING_ERROR 0x00000001 853bf21cd93STycho Nightingale #define PCIM_AER_UC_DL_PROTOCOL_ERROR 0x00000010 854bf21cd93STycho Nightingale #define PCIM_AER_UC_SURPRISE_LINK_DOWN 0x00000020 855bf21cd93STycho Nightingale #define PCIM_AER_UC_POISONED_TLP 0x00001000 856bf21cd93STycho Nightingale #define PCIM_AER_UC_FC_PROTOCOL_ERROR 0x00002000 857bf21cd93STycho Nightingale #define PCIM_AER_UC_COMPLETION_TIMEOUT 0x00004000 858bf21cd93STycho Nightingale #define PCIM_AER_UC_COMPLETER_ABORT 0x00008000 859bf21cd93STycho Nightingale #define PCIM_AER_UC_UNEXPECTED_COMPLETION 0x00010000 860bf21cd93STycho Nightingale #define PCIM_AER_UC_RECEIVER_OVERFLOW 0x00020000 861bf21cd93STycho Nightingale #define PCIM_AER_UC_MALFORMED_TLP 0x00040000 862bf21cd93STycho Nightingale #define PCIM_AER_UC_ECRC_ERROR 0x00080000 863bf21cd93STycho Nightingale #define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000 864bf21cd93STycho Nightingale #define PCIM_AER_UC_ACS_VIOLATION 0x00200000 865bf21cd93STycho Nightingale #define PCIM_AER_UC_INTERNAL_ERROR 0x00400000 866bf21cd93STycho Nightingale #define PCIM_AER_UC_MC_BLOCKED_TLP 0x00800000 867bf21cd93STycho Nightingale #define PCIM_AER_UC_ATOMIC_EGRESS_BLK 0x01000000 868bf21cd93STycho Nightingale #define PCIM_AER_UC_TLP_PREFIX_BLOCKED 0x02000000 869bf21cd93STycho Nightingale #define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */ 870bf21cd93STycho Nightingale #define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */ 871bf21cd93STycho Nightingale #define PCIR_AER_COR_STATUS 0x10 872bf21cd93STycho Nightingale #define PCIM_AER_COR_RECEIVER_ERROR 0x00000001 873bf21cd93STycho Nightingale #define PCIM_AER_COR_BAD_TLP 0x00000040 874bf21cd93STycho Nightingale #define PCIM_AER_COR_BAD_DLLP 0x00000080 875bf21cd93STycho Nightingale #define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100 876bf21cd93STycho Nightingale #define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000 877bf21cd93STycho Nightingale #define PCIM_AER_COR_ADVISORY_NF_ERROR 0x00002000 878bf21cd93STycho Nightingale #define PCIM_AER_COR_INTERNAL_ERROR 0x00004000 879bf21cd93STycho Nightingale #define PCIM_AER_COR_HEADER_LOG_OVFLOW 0x00008000 880bf21cd93STycho Nightingale #define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */ 881bf21cd93STycho Nightingale #define PCIR_AER_CAP_CONTROL 0x18 882bf21cd93STycho Nightingale #define PCIM_AER_FIRST_ERROR_PTR 0x0000001f 883bf21cd93STycho Nightingale #define PCIM_AER_ECRC_GEN_CAPABLE 0x00000020 884bf21cd93STycho Nightingale #define PCIM_AER_ECRC_GEN_ENABLE 0x00000040 885bf21cd93STycho Nightingale #define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080 886bf21cd93STycho Nightingale #define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100 887bf21cd93STycho Nightingale #define PCIM_AER_MULT_HDR_CAPABLE 0x00000200 888bf21cd93STycho Nightingale #define PCIM_AER_MULT_HDR_ENABLE 0x00000400 889bf21cd93STycho Nightingale #define PCIM_AER_TLP_PREFIX_LOG_PRESENT 0x00000800 890bf21cd93STycho Nightingale #define PCIR_AER_HEADER_LOG 0x1c 891bf21cd93STycho Nightingale #define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */ 892bf21cd93STycho Nightingale #define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001 893bf21cd93STycho Nightingale #define PCIM_AER_ROOTERR_NF_ENABLE 0x00000002 894bf21cd93STycho Nightingale #define PCIM_AER_ROOTERR_F_ENABLE 0x00000004 895bf21cd93STycho Nightingale #define PCIR_AER_ROOTERR_STATUS 0x30 /* Only for root complex ports */ 896bf21cd93STycho Nightingale #define PCIM_AER_ROOTERR_COR_ERR 0x00000001 897bf21cd93STycho Nightingale #define PCIM_AER_ROOTERR_MULTI_COR_ERR 0x00000002 898bf21cd93STycho Nightingale #define PCIM_AER_ROOTERR_UC_ERR 0x00000004 899bf21cd93STycho Nightingale #define PCIM_AER_ROOTERR_MULTI_UC_ERR 0x00000008 900bf21cd93STycho Nightingale #define PCIM_AER_ROOTERR_FIRST_UC_FATAL 0x00000010 901bf21cd93STycho Nightingale #define PCIM_AER_ROOTERR_NF_ERR 0x00000020 902bf21cd93STycho Nightingale #define PCIM_AER_ROOTERR_F_ERR 0x00000040 903bf21cd93STycho Nightingale #define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000 904bf21cd93STycho Nightingale #define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */ 905bf21cd93STycho Nightingale #define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */ 906bf21cd93STycho Nightingale #define PCIR_AER_TLP_PREFIX_LOG 0x38 /* Only for TLP prefix functions */ 907bf21cd93STycho Nightingale 908bf21cd93STycho Nightingale /* Virtual Channel definitions */ 909bf21cd93STycho Nightingale #define PCIR_VC_CAP1 0x04 910bf21cd93STycho Nightingale #define PCIM_VC_CAP1_EXT_COUNT 0x00000007 911bf21cd93STycho Nightingale #define PCIM_VC_CAP1_LOWPRI_EXT_COUNT 0x00000070 912bf21cd93STycho Nightingale #define PCIR_VC_CAP2 0x08 913bf21cd93STycho Nightingale #define PCIR_VC_CONTROL 0x0C 914bf21cd93STycho Nightingale #define PCIR_VC_STATUS 0x0E 915bf21cd93STycho Nightingale #define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0C) 916bf21cd93STycho Nightingale #define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0C) 917bf21cd93STycho Nightingale #define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0C) 918bf21cd93STycho Nightingale 919bf21cd93STycho Nightingale /* Serial Number definitions */ 920bf21cd93STycho Nightingale #define PCIR_SERIAL_LOW 0x04 921bf21cd93STycho Nightingale #define PCIR_SERIAL_HIGH 0x08 922bf21cd93STycho Nightingale 923