1 /* 2 * 3 * CDDL HEADER START 4 * 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2018 Joyent, Inc. 25 */ 26 27 /* 28 * Copyright (c) 2010, Intel Corporation. 29 * All rights reserved. 30 */ 31 32 /* Copyright (c) 1988 AT&T */ 33 /* All Rights Reserved */ 34 35 #include "dis_tables.h" 36 37 /* BEGIN CSTYLED */ 38 39 /* 40 * Disassembly begins in dis_distable, which is equivalent to the One-byte 41 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The 42 * decoding loops then traverse out through the other tables as necessary to 43 * decode a given instruction. 44 * 45 * The behavior of this file can be controlled by one of the following flags: 46 * 47 * DIS_TEXT Include text for disassembly 48 * DIS_MEM Include memory-size calculations 49 * 50 * Either or both of these can be defined. 51 * 52 * This file is not, and will never be, cstyled. If anything, the tables should 53 * be taken out another tab stop or two so nothing overlaps. 54 */ 55 56 /* 57 * These functions must be provided for the consumer to do disassembly. 58 */ 59 #ifdef DIS_TEXT 60 extern char *strncpy(char *, const char *, size_t); 61 extern size_t strlen(const char *); 62 extern int strcmp(const char *, const char *); 63 extern int strncmp(const char *, const char *, size_t); 64 extern size_t strlcat(char *, const char *, size_t); 65 #endif 66 67 68 #define TERM 0 /* used to indicate that the 'indirect' */ 69 /* field terminates - no pointer. */ 70 71 /* Used to decode instructions. */ 72 typedef struct instable { 73 struct instable *it_indirect; /* for decode op codes */ 74 uchar_t it_adrmode; 75 #ifdef DIS_TEXT 76 char it_name[NCPS]; 77 uint_t it_suffix:1; /* mnem + "w", "l", or "d" */ 78 #endif 79 #ifdef DIS_MEM 80 uint_t it_size:16; 81 #endif 82 uint_t it_invalid64:1; /* opcode invalid in amd64 */ 83 uint_t it_always64:1; /* 64 bit when in 64 bit mode */ 84 uint_t it_invalid32:1; /* invalid in IA32 */ 85 uint_t it_stackop:1; /* push/pop stack operation */ 86 uint_t it_vexwoxmm:1; /* VEX instructions that don't use XMM/YMM */ 87 uint_t it_avxsuf:2; /* AVX2/AVX512 suffix rqd. */ 88 uint_t it_vexopmask:1; /* VEX inst. that use opmask */ 89 } instable_t; 90 91 /* 92 * Instruction formats. 93 */ 94 enum { 95 UNKNOWN, 96 MRw, 97 IMlw, 98 IMw, 99 IR, 100 OA, 101 AO, 102 MS, 103 SM, 104 Mv, 105 Mw, 106 M, /* register or memory */ 107 MG9, /* register or memory in group 9 (prefix optional) */ 108 Mb, /* register or memory, always byte sized */ 109 MO, /* memory only (no registers) */ 110 PREF, 111 SWAPGS_RDTSCP, 112 MONITOR_MWAIT, 113 R, 114 RA, 115 SEG, 116 MR, 117 RM, 118 RM_66r, /* RM, but with a required 0x66 prefix */ 119 IA, 120 MA, 121 SD, 122 AD, 123 SA, 124 D, 125 INM, 126 SO, 127 BD, 128 I, 129 P, 130 V, 131 DSHIFT, /* for double shift that has an 8-bit immediate */ 132 U, 133 OVERRIDE, 134 NORM, /* instructions w/o ModR/M byte, no memory access */ 135 IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */ 136 O, /* for call */ 137 JTAB, /* jump table */ 138 IMUL, /* for 186 iimul instr */ 139 CBW, /* so data16 can be evaluated for cbw and variants */ 140 MvI, /* for 186 logicals */ 141 ENTER, /* for 186 enter instr */ 142 RMw, /* for 286 arpl instr */ 143 Ib, /* for push immediate byte */ 144 F, /* for 287 instructions */ 145 FF, /* for 287 instructions */ 146 FFC, /* for 287 instructions */ 147 DM, /* 16-bit data */ 148 AM, /* 16-bit addr */ 149 LSEG, /* for 3-bit seg reg encoding */ 150 MIb, /* for 386 logicals */ 151 SREG, /* for 386 special registers */ 152 PREFIX, /* a REP instruction prefix */ 153 LOCK, /* a LOCK instruction prefix */ 154 INT3, /* The int 3 instruction, which has a fake operand */ 155 INTx, /* The normal int instruction, with explicit int num */ 156 DSHIFTcl, /* for double shift that implicitly uses %cl */ 157 CWD, /* so data16 can be evaluated for cwd and variants */ 158 RET, /* single immediate 16-bit operand */ 159 MOVZ, /* for movs and movz, with different size operands */ 160 CRC32, /* for crc32, with different size operands */ 161 XADDB, /* for xaddb */ 162 MOVSXZ, /* AMD64 mov sign extend 32 to 64 bit instruction */ 163 MOVBE, /* movbe instruction */ 164 165 /* 166 * MMX/SIMD addressing modes. 167 */ 168 169 MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */ 170 MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */ 171 MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */ 172 MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */ 173 MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */ 174 MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */ 175 MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */ 176 MMOPM_66o, /* MMX/SIMD-Int 0x66 optional mm/mem -> mm,imm8 */ 177 MMOPRM, /* Prefixable MMX/SIMD-Int r32/mem -> mm,imm8 */ 178 MMOSH, /* Prefixable MMX mm,imm8 */ 179 MM, /* MMX/SIMD-Int mm/mem -> mm */ 180 MMS, /* MMX/SIMD-Int mm -> mm/mem */ 181 MMSH, /* MMX mm,imm8 */ 182 XMMO, /* Prefixable SIMD xmm/mem -> xmm */ 183 XMMOS, /* Prefixable SIMD xmm -> xmm/mem */ 184 XMMOPM, /* Prefixable SIMD xmm/mem w/to xmm,imm8 */ 185 XMMOMX, /* Prefixable SIMD mm/mem -> xmm */ 186 XMMOX3, /* Prefixable SIMD xmm -> r32 */ 187 XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */ 188 XMMOM, /* Prefixable SIMD xmm -> mem */ 189 XMMOMS, /* Prefixable SIMD mem -> xmm */ 190 XMM, /* SIMD xmm/mem -> xmm */ 191 XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */ 192 XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */ 193 XMMXIMPL, /* SIMD xmm -> xmm (mem) */ 194 XMM3P, /* SIMD xmm -> r32,imm8 */ 195 XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8 */ 196 XMMP, /* SIMD xmm/mem w/to xmm,imm8 */ 197 XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */ 198 XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */ 199 XMMPRM, /* SIMD r32/mem -> xmm,imm8 */ 200 XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */ 201 XMMS, /* SIMD xmm -> xmm/mem */ 202 XMMM, /* SIMD mem -> xmm */ 203 XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */ 204 XMMMS, /* SIMD xmm -> mem */ 205 XMM3MX, /* SIMD r32/mem -> xmm */ 206 XMM3MXS, /* SIMD xmm -> r32/mem */ 207 XMMSH, /* SIMD xmm,imm8 */ 208 XMMXM3, /* SIMD xmm/mem -> r32 */ 209 XMMX3, /* SIMD xmm -> r32 */ 210 XMMXMM, /* SIMD xmm/mem -> mm */ 211 XMMMX, /* SIMD mm -> xmm */ 212 XMMXM, /* SIMD xmm -> mm */ 213 XMMX2I, /* SIMD xmm -> xmm, imm, imm */ 214 XMM2I, /* SIMD xmm, imm, imm */ 215 XMMFENCE, /* SIMD lfence or mfence */ 216 XMMSFNC, /* SIMD sfence (none or mem) */ 217 FSGS, /* FSGSBASE if reg */ 218 XGETBV_XSETBV, 219 VEX_NONE, /* VEX no operand */ 220 VEX_MO, /* VEX mod_rm -> implicit reg */ 221 VEX_RMrX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 222 VEX_VRMrX, /* VEX mod_rm, VEX.vvvv -> mod_rm */ 223 VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 224 VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */ 225 VEX_MX, /* VEX mod_rm -> mod_reg */ 226 VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */ 227 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */ 228 VEX_MR, /* VEX mod_rm -> mod_reg */ 229 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */ 230 VEX_RX, /* VEX mod_reg -> mod_rm */ 231 VEX_KRR, /* VEX mod_rm -> mod_reg */ 232 VEX_KMR, /* VEX mod_reg -> mod_rm */ 233 VEX_KRM, /* VEX mod_rm -> mod_reg */ 234 VEX_RR, /* VEX mod_rm -> mod_reg */ 235 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */ 236 VEX_RM, /* VEX mod_reg -> mod_rm */ 237 VEX_RIM, /* VEX mod_reg, imm8 -> mod_rm */ 238 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 239 VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 240 VEX_SbVM, /* VEX SIB, VEX.vvvv -> mod_rm */ 241 VMx, /* vmcall/vmlaunch/vmresume/vmxoff */ 242 VMxo, /* VMx instruction with optional prefix */ 243 SVM, /* AMD SVM instructions */ 244 BLS, /* BLSR, BLSMSK, BLSI */ 245 FMA, /* FMA instructions, all VEX_RMrX */ 246 ADX, /* ADX instructions, support REX.w, mod_rm->mod_reg */ 247 EVEX_RX, /* EVEX mod_reg -> mod_rm */ 248 EVEX_MX, /* EVEX mod_rm -> mod_reg */ 249 EVEX_RMrX /* EVEX EVEX.vvvv, mod_rm -> mod_reg */ 250 }; 251 252 /* 253 * VEX prefixes 254 */ 255 #define VEX_2bytes 0xC5 /* the first byte of two-byte form */ 256 #define VEX_3bytes 0xC4 /* the first byte of three-byte form */ 257 258 #define FILL 0x90 /* Fill byte used for alignment (nop) */ 259 260 /* 261 ** Register numbers for the i386 262 */ 263 #define EAX_REGNO 0 264 #define ECX_REGNO 1 265 #define EDX_REGNO 2 266 #define EBX_REGNO 3 267 #define ESP_REGNO 4 268 #define EBP_REGNO 5 269 #define ESI_REGNO 6 270 #define EDI_REGNO 7 271 272 /* 273 * modes for immediate values 274 */ 275 #define MODE_NONE 0 276 #define MODE_IPREL 1 /* signed IP relative value */ 277 #define MODE_SIGNED 2 /* sign extended immediate */ 278 #define MODE_IMPLIED 3 /* constant value implied from opcode */ 279 #define MODE_OFFSET 4 /* offset part of an address */ 280 #define MODE_RIPREL 5 /* like IPREL, but from %rip (amd64) */ 281 282 /* 283 * The letters used in these macros are: 284 * IND - indirect to another to another table 285 * "T" - means to Terminate indirections (this is the final opcode) 286 * "S" - means "operand length suffix required" 287 * "Sa" - means AVX2 suffix (q/d) required 288 * "Sq" - means AVX512 suffix (q/d) required 289 * "Sd" - means AVX512 suffix (d/s) required 290 * "NS" - means "no suffix" which is the operand length suffix of the opcode 291 * "Z" - means instruction size arg required 292 * "u" - means the opcode is invalid in IA32 but valid in amd64 293 * "x" - means the opcode is invalid in amd64, but not IA32 294 * "y" - means the operand size is always 64 bits in 64 bit mode 295 * "p" - means push/pop stack operation 296 * "vr" - means VEX instruction that operates on normal registers, not fpu 297 * "vo" - means VEX instruction that operates on opmask registers, not fpu 298 */ 299 300 #define AVS2 (uint_t)1 /* it_avxsuf: AVX2 q/d suffix handling */ 301 #define AVS5Q (uint_t)2 /* it_avxsuf: AVX512 q/d suffix handling */ 302 #define AVS5D (uint_t)3 /* it_avxsuf: AVX512 d/s suffix handling */ 303 304 #if defined(DIS_TEXT) && defined(DIS_MEM) 305 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0} 306 #define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0} 307 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0} 308 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0} 309 #define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0} 310 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0} 311 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1} 312 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0} 313 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0} 314 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 1} 315 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 0, 1} 316 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0} 317 #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0} 318 #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0} 319 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1} 320 #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0} 321 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, AVS2} 322 #define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5Q} 323 #define TSd(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5D} 324 #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0} 325 #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0} 326 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 327 #elif defined(DIS_TEXT) 328 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0} 329 #define INDx(table) {(instable_t *)table, 0, "", 0, 1, 0, 0, 0} 330 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0} 331 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0} 332 #define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0} 333 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0} 334 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1} 335 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0} 336 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0} 337 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0, 1} 338 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 1} 339 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0} 340 #define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0} 341 #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0} 342 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1} 343 #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0} 344 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0, AVS2} 345 #define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5Q} 346 #define TSd(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5D} 347 #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0} 348 #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0} 349 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 350 #elif defined(DIS_MEM) 351 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0} 352 #define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0} 353 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 354 #define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0} 355 #define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 356 #define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1} 357 #define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 358 #define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 359 #define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 360 #define TNSZvr(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 1} 361 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 0, 1} 362 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 363 #define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 364 #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 365 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1} 366 #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 367 #define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, AVS2} 368 #define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5Q} 369 #define TSd(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5D} 370 #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0} 371 #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 372 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0} 373 #else 374 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0} 375 #define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0} 376 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0} 377 #define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0} 378 #define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0} 379 #define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1} 380 #define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0} 381 #define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 382 #define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 383 #define TNSZvr(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 1} 384 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 1} 385 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0} 386 #define TSx(name, amode) {TERM, amode, 1, 0, 0, 0} 387 #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0} 388 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1} 389 #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 390 #define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, AVS2} 391 #define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5Q} 392 #define TSd(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5D} 393 #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0} 394 #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 395 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0} 396 #endif 397 398 #ifdef DIS_TEXT 399 /* 400 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode 401 */ 402 const char *const dis_addr16[3][8] = { 403 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "", 404 "(%bx)", 405 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)", 406 "(%bx)", 407 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)", 408 "(%bx)", 409 }; 410 411 412 /* 413 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2 414 */ 415 const char *const dis_addr32_mode0[16] = { 416 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)", 417 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)" 418 }; 419 420 const char *const dis_addr32_mode12[16] = { 421 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)", 422 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)" 423 }; 424 425 /* 426 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2 427 */ 428 const char *const dis_addr64_mode0[16] = { 429 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)", "(%rdi)", 430 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)" 431 }; 432 const char *const dis_addr64_mode12[16] = { 433 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)", "(%rdi)", 434 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)" 435 }; 436 437 /* 438 * decode for scale from SIB byte 439 */ 440 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" }; 441 442 /* 443 * decode for scale from VSIB byte, note that we always include the scale factor 444 * to match gas. 445 */ 446 const char *const dis_vscale_factor[4] = { ",1)", ",2)", ",4)", ",8)" }; 447 448 /* 449 * register decoding for normal references to registers (ie. not addressing) 450 */ 451 const char *const dis_REG8[16] = { 452 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", 453 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 454 }; 455 456 const char *const dis_REG8_REX[16] = { 457 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", 458 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 459 }; 460 461 const char *const dis_REG16[16] = { 462 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", 463 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" 464 }; 465 466 const char *const dis_REG32[16] = { 467 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 468 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" 469 }; 470 471 const char *const dis_REG64[16] = { 472 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 473 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" 474 }; 475 476 const char *const dis_DEBUGREG[16] = { 477 "%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7", 478 "%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15" 479 }; 480 481 const char *const dis_CONTROLREG[16] = { 482 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?", 483 "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?" 484 }; 485 486 const char *const dis_TESTREG[16] = { 487 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7", 488 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7" 489 }; 490 491 const char *const dis_MMREG[16] = { 492 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7", 493 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7" 494 }; 495 496 const char *const dis_XMMREG[32] = { 497 "%xmm0", "%xmm1", "%xmm2", "%xmm3", 498 "%xmm4", "%xmm5", "%xmm6", "%xmm7", 499 "%xmm8", "%xmm9", "%xmm10", "%xmm11", 500 "%xmm12", "%xmm13", "%xmm14", "%xmm15", 501 "%xmm16", "%xmm17", "%xmm18", "%xmm19", 502 "%xmm20", "%xmm21", "%xmm22", "%xmm23", 503 "%xmm24", "%xmm25", "%xmm26", "%xmm27", 504 "%xmm28", "%xmm29", "%xmm30", "%xmm31", 505 }; 506 507 const char *const dis_YMMREG[32] = { 508 "%ymm0", "%ymm1", "%ymm2", "%ymm3", 509 "%ymm4", "%ymm5", "%ymm6", "%ymm7", 510 "%ymm8", "%ymm9", "%ymm10", "%ymm11", 511 "%ymm12", "%ymm13", "%ymm14", "%ymm15", 512 "%ymm16", "%ymm17", "%ymm18", "%ymm19", 513 "%ymm20", "%ymm21", "%ymm22", "%ymm23", 514 "%ymm24", "%ymm25", "%ymm26", "%ymm27", 515 "%ymm28", "%ymm29", "%ymm30", "%ymm31", 516 }; 517 518 const char *const dis_ZMMREG[32] = { 519 "%zmm0", "%zmm1", "%zmm2", "%zmm3", 520 "%zmm4", "%zmm5", "%zmm6", "%zmm7", 521 "%zmm8", "%zmm9", "%zmm10", "%zmm11", 522 "%zmm12", "%zmm13", "%zmm14", "%zmm15", 523 "%zmm16", "%zmm17", "%zmm18", "%zmm19", 524 "%zmm20", "%zmm21", "%zmm22", "%zmm23", 525 "%zmm24", "%zmm25", "%zmm26", "%zmm27", 526 "%zmm28", "%zmm29", "%zmm30", "%zmm31", 527 }; 528 529 const char *const dis_KOPMASKREG[8] = { 530 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" 531 }; 532 533 const char *const dis_SEGREG[16] = { 534 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>", 535 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>" 536 }; 537 538 /* 539 * SIMD predicate suffixes 540 */ 541 const char *const dis_PREDSUFFIX[8] = { 542 "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord" 543 }; 544 545 const char *const dis_AVXvgrp7[3][8] = { 546 /*0 1 2 3 4 5 6 7*/ 547 /*71*/ {"", "", "vpsrlw", "", "vpsraw", "", "vpsllw", ""}, 548 /*72*/ {"", "", "vpsrld", "", "vpsrad", "", "vpslld", ""}, 549 /*73*/ {"", "", "vpsrlq", "vpsrldq", "", "", "vpsllq", "vpslldq"} 550 }; 551 552 #endif /* DIS_TEXT */ 553 554 /* 555 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63) 556 */ 557 const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ); 558 559 /* 560 * "decode table" for pause and clflush instructions 561 */ 562 const instable_t dis_opPause = TNS("pause", NORM); 563 564 /* 565 * Decode table for 0x0F00 opcodes 566 */ 567 const instable_t dis_op0F00[8] = { 568 569 /* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M), TNSy("ltr",M), 570 /* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID, INVALID, 571 }; 572 573 574 /* 575 * Decode table for 0x0F01 opcodes 576 */ 577 const instable_t dis_op0F01[8] = { 578 579 /* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6), 580 /* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP), 581 }; 582 583 /* 584 * Decode table for 0x0F18 opcodes -- SIMD prefetch 585 */ 586 const instable_t dis_op0F18[8] = { 587 588 /* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF), 589 /* [4] */ INVALID, INVALID, INVALID, INVALID, 590 }; 591 592 /* 593 * Decode table for 0x0FAE opcodes -- SIMD state save/restore 594 */ 595 const instable_t dis_op0FAE[8] = { 596 /* [0] */ TNSZ("fxsave",FSGS,512),TNSZ("fxrstor",FSGS,512),TNS("ldmxcsr",FSGS), TNS("stmxcsr",FSGS), 597 /* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC), 598 }; 599 600 /* 601 * Decode table for 0xF30FAE opcodes -- FSGSBASE 602 */ 603 const instable_t dis_opF30FAE[8] = { 604 /* [0] */ TNSx("rdfsbase",FSGS), TNSx("rdgsbase",FSGS), TNSx("wrfsbase",FSGS), TNSx("wrgsbase",FSGS), 605 /* [4] */ INVALID, INVALID, INVALID, INVALID, 606 }; 607 608 /* 609 * Decode table for 0x0FBA opcodes 610 */ 611 612 const instable_t dis_op0FBA[8] = { 613 614 /* [0] */ INVALID, INVALID, INVALID, INVALID, 615 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb), 616 }; 617 618 /* 619 * Decode table for 0x0FC7 opcode (group 9) 620 */ 621 622 const instable_t dis_op0FC7[8] = { 623 624 /* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, TNS("xrstors",MG9), 625 /* [4] */ TNS("xsavec",MG9), TNS("xsaves",MG9), TNS("vmptrld",MG9), TNS("vmptrst",MG9), 626 }; 627 628 /* 629 * Decode table for 0x0FC7 opcode (group 9) mode 3 630 */ 631 632 const instable_t dis_op0FC7m3[8] = { 633 634 /* [0] */ INVALID, INVALID, INVALID, INVALID, 635 /* [4] */ INVALID, INVALID, TNS("rdrand",MG9), TNS("rdseed", MG9), 636 }; 637 638 /* 639 * Decode table for 0x0FC7 opcode with 0x66 prefix 640 */ 641 642 const instable_t dis_op660FC7[8] = { 643 644 /* [0] */ INVALID, INVALID, INVALID, INVALID, 645 /* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID, 646 }; 647 648 /* 649 * Decode table for 0x0FC7 opcode with 0xF3 prefix 650 */ 651 652 const instable_t dis_opF30FC7[8] = { 653 654 /* [0] */ INVALID, INVALID, INVALID, INVALID, 655 /* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID, 656 }; 657 658 /* 659 * Decode table for 0x0FC8 opcode -- 486 bswap instruction 660 * 661 *bit pattern: 0000 1111 1100 1reg 662 */ 663 const instable_t dis_op0FC8[4] = { 664 /* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID, 665 }; 666 667 /* 668 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions 669 */ 670 const instable_t dis_op0F7123[4][8] = { 671 { 672 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 673 /* .4 */ INVALID, INVALID, INVALID, INVALID, 674 }, { 675 /* [71].0 */ INVALID, INVALID, TNS("psrlw",MMOSH), INVALID, 676 /* .4 */ TNS("psraw",MMOSH), INVALID, TNS("psllw",MMOSH), INVALID, 677 }, { 678 /* [72].0 */ INVALID, INVALID, TNS("psrld",MMOSH), INVALID, 679 /* .4 */ TNS("psrad",MMOSH), INVALID, TNS("pslld",MMOSH), INVALID, 680 }, { 681 /* [73].0 */ INVALID, INVALID, TNS("psrlq",MMOSH), TNS("INVALID",MMOSH), 682 /* .4 */ INVALID, INVALID, TNS("psllq",MMOSH), TNS("INVALID",MMOSH), 683 } }; 684 685 /* 686 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes. 687 */ 688 const instable_t dis_opSIMD7123[32] = { 689 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 690 /* .4 */ INVALID, INVALID, INVALID, INVALID, 691 692 /* [71].0 */ INVALID, INVALID, TNS("psrlw",XMMSH), INVALID, 693 /* .4 */ TNS("psraw",XMMSH), INVALID, TNS("psllw",XMMSH), INVALID, 694 695 /* [72].0 */ INVALID, INVALID, TNS("psrld",XMMSH), INVALID, 696 /* .4 */ TNS("psrad",XMMSH), INVALID, TNS("pslld",XMMSH), INVALID, 697 698 /* [73].0 */ INVALID, INVALID, TNS("psrlq",XMMSH), TNS("psrldq",XMMSH), 699 /* .4 */ INVALID, INVALID, TNS("psllq",XMMSH), TNS("pslldq",XMMSH), 700 }; 701 702 /* 703 * SIMD instructions have been wedged into the existing IA32 instruction 704 * set through the use of prefixes. That is, while 0xf0 0x58 may be 705 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different 706 * instruction - addss. At present, three prefixes have been coopted in 707 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The 708 * following tables are used to provide the prefixed instruction names. 709 * The arrays are sparse, but they're fast. 710 */ 711 712 /* 713 * Decode table for SIMD instructions with the address size (0x66) prefix. 714 */ 715 const instable_t dis_opSIMDdata16[256] = { 716 /* [00] */ INVALID, INVALID, INVALID, INVALID, 717 /* [04] */ INVALID, INVALID, INVALID, INVALID, 718 /* [08] */ INVALID, INVALID, INVALID, INVALID, 719 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 720 721 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8), 722 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8), 723 /* [18] */ INVALID, INVALID, INVALID, INVALID, 724 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 725 726 /* [20] */ INVALID, INVALID, INVALID, INVALID, 727 /* [24] */ INVALID, INVALID, INVALID, INVALID, 728 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16), 729 /* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8), 730 731 /* [30] */ INVALID, INVALID, INVALID, INVALID, 732 /* [34] */ INVALID, INVALID, INVALID, INVALID, 733 /* [38] */ INVALID, INVALID, INVALID, INVALID, 734 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 735 736 /* [40] */ INVALID, INVALID, INVALID, INVALID, 737 /* [44] */ INVALID, INVALID, INVALID, INVALID, 738 /* [48] */ INVALID, INVALID, INVALID, INVALID, 739 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 740 741 /* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID, INVALID, 742 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16), 743 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16), 744 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16), 745 746 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16), 747 /* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16), 748 /* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16), 749 /* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16), 750 751 /* [70] */ TNSZ("pshufd",XMMP,16), INVALID, INVALID, INVALID, 752 /* [74] */ TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID, 753 /* [78] */ TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID, INVALID, 754 /* [7C] */ TNSZ("haddpd",XMM,16), TNSZ("hsubpd",XMM,16), TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16), 755 756 /* [80] */ INVALID, INVALID, INVALID, INVALID, 757 /* [84] */ INVALID, INVALID, INVALID, INVALID, 758 /* [88] */ INVALID, INVALID, INVALID, INVALID, 759 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 760 761 /* [90] */ INVALID, INVALID, INVALID, INVALID, 762 /* [94] */ INVALID, INVALID, INVALID, INVALID, 763 /* [98] */ INVALID, INVALID, INVALID, INVALID, 764 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 765 766 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 767 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 768 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 769 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 770 771 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 772 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 773 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 774 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 775 776 /* [C0] */ INVALID, INVALID, TNSZ("cmppd",XMMP,16), INVALID, 777 /* [C4] */ TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P), TNSZ("shufpd",XMMP,16), INVALID, 778 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 779 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 780 781 /* [D0] */ TNSZ("addsubpd",XMM,16),TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16), 782 /* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3), 783 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16), 784 /* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16), 785 786 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16), 787 /* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16), 788 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16), 789 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16), 790 791 /* [F0] */ INVALID, TNSZ("psllw",XMM,16), TNSZ("pslld",XMM,16), TNSZ("psllq",XMM,16), 792 /* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16), 793 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16), 794 /* [FC] */ TNSZ("paddb",XMM,16), TNSZ("paddw",XMM,16), TNSZ("paddd",XMM,16), INVALID, 795 }; 796 797 const instable_t dis_opAVX660F[256] = { 798 /* [00] */ INVALID, INVALID, INVALID, INVALID, 799 /* [04] */ INVALID, INVALID, INVALID, INVALID, 800 /* [08] */ INVALID, INVALID, INVALID, INVALID, 801 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 802 803 /* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8), 804 /* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8), 805 /* [18] */ INVALID, INVALID, INVALID, INVALID, 806 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 807 808 /* [20] */ INVALID, INVALID, INVALID, INVALID, 809 /* [24] */ INVALID, INVALID, INVALID, INVALID, 810 /* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16), 811 /* [2C] */ INVALID, INVALID, TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8), 812 813 /* [30] */ INVALID, INVALID, INVALID, INVALID, 814 /* [34] */ INVALID, INVALID, INVALID, INVALID, 815 /* [38] */ INVALID, INVALID, INVALID, INVALID, 816 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 817 818 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID, 819 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX), 820 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX), 821 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 822 823 /* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16), INVALID, INVALID, 824 /* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16), 825 /* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16), 826 /* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16), 827 828 /* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16), 829 /* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16), 830 /* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16), 831 /* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16), 832 833 /* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16), 834 /* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID, 835 /* [78] */ INVALID, INVALID, INVALID, INVALID, 836 /* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16), 837 838 /* [80] */ INVALID, INVALID, INVALID, INVALID, 839 /* [84] */ INVALID, INVALID, INVALID, INVALID, 840 /* [88] */ INVALID, INVALID, INVALID, INVALID, 841 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 842 843 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 844 /* [94] */ INVALID, INVALID, INVALID, INVALID, 845 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID, 846 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 847 848 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 849 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 850 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 851 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 852 853 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 854 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 855 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 856 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 857 858 /* [C0] */ INVALID, INVALID, TNSZ("vcmppd",VEX_RMRX,16), INVALID, 859 /* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID, 860 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 861 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 862 863 /* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16), 864 /* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR), 865 /* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16), 866 /* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16), 867 868 /* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16), 869 /* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16), 870 /* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16), 871 /* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16), 872 873 /* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16), 874 /* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX), 875 /* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16), 876 /* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID, 877 }; 878 879 /* 880 * Decode table for SIMD instructions with the repnz (0xf2) prefix. 881 */ 882 const instable_t dis_opSIMDrepnz[256] = { 883 /* [00] */ INVALID, INVALID, INVALID, INVALID, 884 /* [04] */ INVALID, INVALID, INVALID, INVALID, 885 /* [08] */ INVALID, INVALID, INVALID, INVALID, 886 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 887 888 /* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8), TNSZ("movddup",XMM,8), INVALID, 889 /* [14] */ INVALID, INVALID, INVALID, INVALID, 890 /* [18] */ INVALID, INVALID, INVALID, INVALID, 891 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 892 893 /* [20] */ INVALID, INVALID, INVALID, INVALID, 894 /* [24] */ INVALID, INVALID, INVALID, INVALID, 895 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8), 896 /* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID, INVALID, 897 898 /* [30] */ INVALID, INVALID, INVALID, INVALID, 899 /* [34] */ INVALID, INVALID, INVALID, INVALID, 900 /* [38] */ INVALID, INVALID, INVALID, INVALID, 901 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 902 903 /* [40] */ INVALID, INVALID, INVALID, INVALID, 904 /* [44] */ INVALID, INVALID, INVALID, INVALID, 905 /* [48] */ INVALID, INVALID, INVALID, INVALID, 906 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 907 908 /* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID, INVALID, 909 /* [54] */ INVALID, INVALID, INVALID, INVALID, 910 /* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8), TNSZ("cvtsd2ss",XMM,8), INVALID, 911 /* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8), TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8), 912 913 /* [60] */ INVALID, INVALID, INVALID, INVALID, 914 /* [64] */ INVALID, INVALID, INVALID, INVALID, 915 /* [68] */ INVALID, INVALID, INVALID, INVALID, 916 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 917 918 /* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID, INVALID, 919 /* [74] */ INVALID, INVALID, INVALID, INVALID, 920 /* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID, INVALID, 921 /* [7C] */ TNSZ("haddps",XMM,16), TNSZ("hsubps",XMM,16), INVALID, INVALID, 922 923 /* [80] */ INVALID, INVALID, INVALID, INVALID, 924 /* [84] */ INVALID, INVALID, INVALID, INVALID, 925 /* [88] */ INVALID, INVALID, INVALID, INVALID, 926 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 927 928 /* [90] */ INVALID, INVALID, INVALID, INVALID, 929 /* [94] */ INVALID, INVALID, INVALID, INVALID, 930 /* [98] */ INVALID, INVALID, INVALID, INVALID, 931 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 932 933 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 934 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 935 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 936 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 937 938 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 939 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 940 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 941 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 942 943 /* [C0] */ INVALID, INVALID, TNSZ("cmpsd",XMMP,8), INVALID, 944 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 945 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 946 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 947 948 /* [D0] */ TNSZ("addsubps",XMM,16),INVALID, INVALID, INVALID, 949 /* [D4] */ INVALID, INVALID, TNS("movdq2q",XMMXM), INVALID, 950 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 951 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 952 953 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 954 /* [E4] */ INVALID, INVALID, TNSZ("cvtpd2dq",XMM,16),INVALID, 955 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 956 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 957 958 /* [F0] */ TNS("lddqu",XMMM), INVALID, INVALID, INVALID, 959 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 960 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 961 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 962 }; 963 964 const instable_t dis_opAVXF20F[256] = { 965 /* [00] */ INVALID, INVALID, INVALID, INVALID, 966 /* [04] */ INVALID, INVALID, INVALID, INVALID, 967 /* [08] */ INVALID, INVALID, INVALID, INVALID, 968 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 969 970 /* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID, 971 /* [14] */ INVALID, INVALID, INVALID, INVALID, 972 /* [18] */ INVALID, INVALID, INVALID, INVALID, 973 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 974 975 /* [20] */ INVALID, INVALID, INVALID, INVALID, 976 /* [24] */ INVALID, INVALID, INVALID, INVALID, 977 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID, 978 /* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID, INVALID, 979 980 /* [30] */ INVALID, INVALID, INVALID, INVALID, 981 /* [34] */ INVALID, INVALID, INVALID, INVALID, 982 /* [38] */ INVALID, INVALID, INVALID, INVALID, 983 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 984 985 /* [40] */ INVALID, INVALID, INVALID, INVALID, 986 /* [44] */ INVALID, INVALID, INVALID, INVALID, 987 /* [48] */ INVALID, INVALID, INVALID, INVALID, 988 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 989 990 /* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8), INVALID, INVALID, 991 /* [54] */ INVALID, INVALID, INVALID, INVALID, 992 /* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID, 993 /* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8), 994 995 /* [60] */ INVALID, INVALID, INVALID, INVALID, 996 /* [64] */ INVALID, INVALID, INVALID, INVALID, 997 /* [68] */ INVALID, INVALID, INVALID, INVALID, 998 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 999 1000 /* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID, INVALID, 1001 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1002 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1003 /* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8), INVALID, INVALID, 1004 1005 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1006 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1007 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1008 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1009 1010 /* [90] */ INVALID, INVALID, TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 1011 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1012 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1013 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1014 1015 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1016 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1017 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1018 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1019 1020 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1021 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1022 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1023 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1024 1025 /* [C0] */ INVALID, INVALID, TNSZ("vcmpsd",VEX_RMRX,8), INVALID, 1026 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1027 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1028 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1029 1030 /* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID, INVALID, INVALID, 1031 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1032 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1033 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1034 1035 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1036 /* [E4] */ INVALID, INVALID, TNSZ("vcvtpd2dq",VEX_MX,16),INVALID, 1037 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1038 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1039 1040 /* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID, INVALID, INVALID, 1041 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1042 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1043 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1044 }; 1045 1046 const instable_t dis_opAVXF20F3A[256] = { 1047 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1048 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1049 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1050 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1051 1052 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1053 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1054 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1055 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1056 1057 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1058 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1059 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1060 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1061 1062 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1063 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1064 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1065 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1066 1067 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1068 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1069 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1070 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1071 1072 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1073 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1074 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1075 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1076 1077 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1078 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1079 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1080 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1081 1082 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1083 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1084 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1085 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1086 1087 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1088 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1089 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1090 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1091 1092 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1093 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1094 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1095 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1096 1097 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1098 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1099 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1100 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1101 1102 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1103 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1104 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1105 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1106 1107 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1108 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1109 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1110 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1111 1112 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1113 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1114 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1115 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1116 1117 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1118 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1119 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1120 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1121 1122 /* [F0] */ TNSZvr("rorx",VEX_MXI,6),INVALID, INVALID, INVALID, 1123 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1124 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1125 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1126 }; 1127 1128 const instable_t dis_opAVXF20F38[256] = { 1129 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1130 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1131 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1132 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1133 1134 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1135 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1136 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1137 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1138 1139 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1140 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1141 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1142 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1143 1144 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1145 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1146 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1147 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1148 1149 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1150 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1151 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1152 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1153 1154 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1155 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1156 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1157 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1158 1159 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1160 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1161 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1162 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1163 1164 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1165 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1166 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1167 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1168 1169 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1170 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1171 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1172 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1173 1174 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1175 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1176 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1177 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1178 1179 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1180 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1181 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1182 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1183 1184 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1185 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1186 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1187 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1188 1189 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1190 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1191 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1192 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1193 1194 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1195 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1196 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1197 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1198 1199 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1200 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1201 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1202 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1203 1204 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1205 /* [F4] */ INVALID, TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5), 1206 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1207 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1208 }; 1209 1210 const instable_t dis_opAVXF30F38[256] = { 1211 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1212 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1213 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1214 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1215 1216 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1217 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1218 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1219 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1220 1221 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1222 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1223 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1224 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1225 1226 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1227 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1228 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1229 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1230 1231 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1232 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1233 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1234 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1235 1236 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1237 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1238 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1239 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1240 1241 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1242 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1243 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1244 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1245 1246 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1247 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1248 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1249 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1250 1251 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1252 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1253 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1254 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1255 1256 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1257 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1258 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1259 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1260 1261 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1262 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1263 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1264 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1265 1266 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1267 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1268 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1269 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1270 1271 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1272 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1273 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1274 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1275 1276 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1277 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1278 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1279 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1280 1281 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1282 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1283 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1284 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1285 1286 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1287 /* [F4] */ INVALID, TNSZvr("pext",VEX_RMrX,5),INVALID, TNSZvr("sarx",VEX_VRMrX,5), 1288 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1289 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1290 }; 1291 /* 1292 * Decode table for SIMD instructions with the repz (0xf3) prefix. 1293 */ 1294 const instable_t dis_opSIMDrepz[256] = { 1295 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1296 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1297 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1298 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1299 1300 /* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4), TNSZ("movsldup",XMM,16),INVALID, 1301 /* [14] */ INVALID, INVALID, TNSZ("movshdup",XMM,16),INVALID, 1302 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1303 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1304 1305 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1306 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1307 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4), 1308 /* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID, INVALID, 1309 1310 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1311 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1312 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1313 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1314 1315 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1316 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1317 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1318 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1319 1320 /* [50] */ INVALID, TNSZ("sqrtss",XMM,4), TNSZ("rsqrtss",XMM,4), TNSZ("rcpss",XMM,4), 1321 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1322 /* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16), 1323 /* [5C] */ TNSZ("subss",XMM,4), TNSZ("minss",XMM,4), TNSZ("divss",XMM,4), TNSZ("maxss",XMM,4), 1324 1325 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1326 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1327 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1328 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("movdqu",XMM,16), 1329 1330 /* [70] */ TNSZ("pshufhw",XMMP,16),INVALID, INVALID, INVALID, 1331 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1332 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1333 /* [7C] */ INVALID, INVALID, TNSZ("movq",XMM,8), TNSZ("movdqu",XMMS,16), 1334 1335 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1336 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1337 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1338 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1339 1340 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1341 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1342 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1343 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1344 1345 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1346 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1347 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1348 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1349 1350 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1351 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1352 /* [B8] */ TS("popcnt",MRw), INVALID, INVALID, INVALID, 1353 /* [BC] */ TNSZ("tzcnt",MRw,5), TS("lzcnt",MRw), INVALID, INVALID, 1354 1355 /* [C0] */ INVALID, INVALID, TNSZ("cmpss",XMMP,4), INVALID, 1356 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1357 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1358 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1359 1360 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1361 /* [D4] */ INVALID, INVALID, TNS("movq2dq",XMMMX), INVALID, 1362 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1363 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1364 1365 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1366 /* [E4] */ INVALID, INVALID, TNSZ("cvtdq2pd",XMM,8), INVALID, 1367 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1368 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1369 1370 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1371 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1372 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1373 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1374 }; 1375 1376 const instable_t dis_opAVXF30F[256] = { 1377 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1378 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1379 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1380 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1381 1382 /* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID, 1383 /* [14] */ INVALID, INVALID, TNSZ("vmovshdup",VEX_MX,4), INVALID, 1384 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1385 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1386 1387 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1388 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1389 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID, 1390 /* [2C] */ TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID, INVALID, 1391 1392 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1393 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1394 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1395 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1396 1397 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1398 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1399 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1400 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1401 1402 /* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4), 1403 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1404 /* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16), 1405 /* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4), 1406 1407 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1408 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1409 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1410 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("vmovdqu",VEX_MX,16), 1411 1412 /* [70] */ TNSZ("vpshufhw",VEX_MXI,16),INVALID, INVALID, INVALID, 1413 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1414 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1415 /* [7C] */ INVALID, INVALID, TNSZ("vmovq",VEX_MX,8), TNSZ("vmovdqu",VEX_RX,16), 1416 1417 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1418 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1419 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1420 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1421 1422 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1423 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1424 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1425 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1426 1427 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1428 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1429 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1430 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1431 1432 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1433 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1434 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1435 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1436 1437 /* [C0] */ INVALID, INVALID, TNSZ("vcmpss",VEX_RMRX,4), INVALID, 1438 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1439 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1440 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1441 1442 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1443 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1444 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1445 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1446 1447 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1448 /* [E4] */ INVALID, INVALID, TNSZ("vcvtdq2pd",VEX_MX,8), INVALID, 1449 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1450 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1451 1452 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1453 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1454 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1455 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1456 }; 1457 1458 /* 1459 * Table for instructions with an EVEX prefix. 1460 */ 1461 const instable_t dis_opAVX62[256] = { 1462 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1463 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1464 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1465 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1466 1467 /* [10] */ TSd("vmovup",EVEX_MX), TSd("vmovup",EVEX_RX), INVALID, INVALID, 1468 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1469 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1470 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1471 1472 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1473 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1474 /* [28] */ TSd("vmovap",EVEX_MX), TSd("vmovap",EVEX_RX), INVALID, INVALID, 1475 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1476 1477 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1478 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1479 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1480 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1481 1482 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1483 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1484 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1485 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1486 1487 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1488 /* [54] */ TSd("vandp",EVEX_RMrX), TSd("vandnp",EVEX_RMrX), TSd("vorp",EVEX_RMrX), TSd("vxorp",EVEX_RMrX), 1489 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1490 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1491 1492 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1493 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1494 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1495 /* [6C] */ INVALID, INVALID, INVALID, TNS("vmovdq",EVEX_MX), 1496 1497 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1498 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1499 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1500 /* [7C] */ INVALID, INVALID, INVALID, TNS("vmovdq",EVEX_RX), 1501 1502 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1503 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1504 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1505 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1506 1507 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1508 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1509 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1510 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1511 1512 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1513 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1514 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1515 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1516 1517 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1518 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1519 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1520 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1521 1522 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1523 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1524 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1525 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1526 1527 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1528 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1529 /* [D8] */ INVALID, INVALID, INVALID, TSq("vpand",EVEX_RMrX), 1530 /* [DC] */ INVALID, INVALID, INVALID, TSq("vpandn",EVEX_RMrX), 1531 1532 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1533 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1534 /* [E8] */ INVALID, INVALID, INVALID, TSq("vpor",EVEX_RMrX), 1535 /* [EC] */ INVALID, INVALID, INVALID, TSq("vpxor",EVEX_RMrX), 1536 1537 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1538 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1539 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1540 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1541 }; 1542 1543 /* 1544 * The following two tables are used to encode crc32 and movbe 1545 * since they share the same opcodes. 1546 */ 1547 const instable_t dis_op0F38F0[2] = { 1548 /* [00] */ TNS("crc32b",CRC32), 1549 TS("movbe",MOVBE), 1550 }; 1551 1552 const instable_t dis_op0F38F1[2] = { 1553 /* [00] */ TS("crc32",CRC32), 1554 TS("movbe",MOVBE), 1555 }; 1556 1557 /* 1558 * The following table is used to distinguish between adox and adcx which share 1559 * the same opcodes. 1560 */ 1561 const instable_t dis_op0F38F6[2] = { 1562 /* [00] */ TNS("adcx",ADX), 1563 TNS("adox",ADX), 1564 }; 1565 1566 const instable_t dis_op0F38[256] = { 1567 /* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16), 1568 /* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16), 1569 /* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16), 1570 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1571 1572 /* [10] */ TNSZ("pblendvb",XMM_66r,16),INVALID, INVALID, INVALID, 1573 /* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16), 1574 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1575 /* [1C] */ TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID, 1576 1577 /* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16), 1578 /* [24] */ TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID, INVALID, 1579 /* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16), 1580 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1581 1582 /* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16), 1583 /* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16), 1584 /* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16), 1585 /* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16), 1586 1587 /* [40] */ TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID, INVALID, 1588 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1589 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1590 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1591 1592 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1593 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1594 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1595 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1596 1597 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1598 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1599 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1600 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1601 1602 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1603 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1604 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1605 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1606 1607 /* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),TNSy("invpcid", RM_66r),INVALID, 1608 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1609 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1610 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1611 1612 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1613 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1614 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1615 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1616 1617 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1618 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1619 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1620 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1621 1622 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1623 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1624 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1625 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1626 1627 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1628 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1629 /* [C8] */ TNSZ("sha1nexte",XMM,16),TNSZ("sha1msg1",XMM,16),TNSZ("sha1msg2",XMM,16),TNSZ("sha256rnds2",XMM,16), 1630 /* [CC] */ TNSZ("sha256msg1",XMM,16),TNSZ("sha256msg2",XMM,16),INVALID, INVALID, 1631 1632 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1633 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1634 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("aesimc",XMM_66r,16), 1635 /* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16), 1636 1637 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1638 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1639 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1640 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1641 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 1642 /* [F4] */ INVALID, INVALID, IND(dis_op0F38F6), INVALID, 1643 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1644 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1645 }; 1646 1647 const instable_t dis_opAVX660F38[256] = { 1648 /* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16), 1649 /* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16), 1650 /* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16), 1651 /* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16), 1652 1653 /* [10] */ INVALID, INVALID, INVALID, TNSZ("vcvtph2ps",VEX_MX,16), 1654 /* [14] */ INVALID, INVALID, TNSZ("vpermps",VEX_RMrX,16),TNSZ("vptest",VEX_RRI,16), 1655 /* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID, 1656 /* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID, 1657 1658 /* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16), 1659 /* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID, 1660 /* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16), 1661 /* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16), 1662 1663 /* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16), 1664 /* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16), 1665 /* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16), 1666 /* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16), 1667 1668 /* [40] */ TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID, INVALID, 1669 /* [44] */ INVALID, TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16), 1670 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1671 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1672 1673 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1674 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1675 /* [58] */ TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID, 1676 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1677 1678 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1679 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1680 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1681 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1682 1683 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1684 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1685 /* [78] */ TNSZ("vpbroadcastb",VEX_MX,16),TNSZ("vpbroadcastw",VEX_MX,16),INVALID, INVALID, 1686 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1687 1688 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1689 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1690 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1691 /* [8C] */ TSaZ("vpmaskmov",VEX_RMrX,16),INVALID, TSaZ("vpmaskmov",VEX_RRM,16),INVALID, 1692 1693 /* [90] */ TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16), 1694 /* [94] */ INVALID, INVALID, TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16), 1695 /* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16), 1696 /* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16), 1697 1698 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1699 /* [A4] */ INVALID, INVALID, TNSZ("vfmaddsub213p",FMA,16),TNSZ("vfmsubadd213p",FMA,16), 1700 /* [A8] */ TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16), 1701 /* [AC] */ TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16), 1702 1703 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1704 /* [B4] */ INVALID, INVALID, TNSZ("vfmaddsub231p",FMA,16),TNSZ("vfmsubadd231p",FMA,16), 1705 /* [B8] */ TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16), 1706 /* [BC] */ TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16), 1707 1708 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1709 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1710 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1711 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1712 1713 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1714 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1715 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("vaesimc",VEX_MX,16), 1716 /* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16), 1717 1718 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1719 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1720 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1721 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1722 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 1723 /* [F4] */ INVALID, INVALID, INVALID, TNSZvr("shlx",VEX_VRMrX,5), 1724 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1725 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1726 }; 1727 1728 const instable_t dis_op0F3A[256] = { 1729 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1730 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1731 /* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16), 1732 /* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16), 1733 1734 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1735 /* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16), 1736 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1737 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1738 1739 /* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID, 1740 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1741 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1742 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1743 1744 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1745 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1746 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1747 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1748 1749 /* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID, 1750 /* [44] */ TNSZ("pclmulqdq",XMMP_66r,16),INVALID, INVALID, INVALID, 1751 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1752 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1753 1754 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1755 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1756 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1757 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1758 1759 /* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16), 1760 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1761 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1762 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1763 1764 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1765 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1766 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1767 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1768 1769 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1770 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1771 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1772 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1773 1774 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1775 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1776 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1777 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1778 1779 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1780 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1781 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1782 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1783 1784 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1785 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1786 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1787 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1788 1789 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1790 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1791 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1792 /* [CC] */ TNSZ("sha1rnds4",XMMP,16),INVALID, INVALID, INVALID, 1793 1794 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1795 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1796 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1797 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("aeskeygenassist",XMMP_66r,16), 1798 1799 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1800 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1801 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1802 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1803 1804 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1805 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1806 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1807 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1808 }; 1809 1810 const instable_t dis_opAVX660F3A[256] = { 1811 /* [00] */ TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID, 1812 /* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID, 1813 /* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16), 1814 /* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16), 1815 1816 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1817 /* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16), 1818 /* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID, 1819 /* [1C] */ INVALID, TNSZ("vcvtps2ph",VEX_RX,16), INVALID, INVALID, 1820 1821 /* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID, 1822 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1823 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1824 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1825 1826 /* [30] */ TSvo("kshiftr",VEX_MXI), TSvo("kshiftr",VEX_MXI), TSvo("kshiftl",VEX_MXI), TSvo("kshiftl",VEX_MXI), 1827 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1828 /* [38] */ TNSZ("vinserti128",VEX_RMRX,16),TNSZ("vextracti128",VEX_RIM,16),INVALID, INVALID, 1829 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1830 1831 /* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID, 1832 /* [44] */ TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID, TNSZ("vperm2i128",VEX_RMRX,16),INVALID, 1833 /* [48] */ INVALID, INVALID, TNSZ("vblendvps",VEX_RMRX,8), TNSZ("vblendvpd",VEX_RMRX,16), 1834 /* [4C] */ TNSZ("vpblendvb",VEX_RMRX,16),INVALID, INVALID, INVALID, 1835 1836 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1837 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1838 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1839 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1840 1841 /* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16), 1842 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1843 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1844 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1845 1846 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1847 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1848 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1849 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1850 1851 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1852 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1853 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1854 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1855 1856 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1857 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1858 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1859 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1860 1861 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1862 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1863 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1864 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1865 1866 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1867 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1868 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1869 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1870 1871 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1872 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1873 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1874 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1875 1876 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1877 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1878 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1879 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("vaeskeygenassist",VEX_MXI,16), 1880 1881 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1882 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1883 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1884 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1885 1886 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1887 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1888 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1889 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1890 }; 1891 1892 /* 1893 * Decode table for 0x0F0D which uses the first byte of the mod_rm to 1894 * indicate a sub-code. 1895 */ 1896 const instable_t dis_op0F0D[8] = { 1897 /* [00] */ INVALID, TNS("prefetchw",PREF), TNS("prefetchwt1",PREF),INVALID, 1898 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1899 }; 1900 1901 /* 1902 * Decode table for 0x0F opcodes 1903 */ 1904 1905 const instable_t dis_op0F[16][16] = { 1906 { 1907 /* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR), 1908 /* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM), 1909 /* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM), 1910 /* [0C] */ INVALID, IND(dis_op0F0D), INVALID, INVALID, 1911 }, { 1912 /* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8), 1913 /* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8), 1914 /* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID, 1915 /* [1C] */ INVALID, INVALID, INVALID, TS("nop",Mw), 1916 }, { 1917 /* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), 1918 /* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID, 1919 /* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16), 1920 /* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4), 1921 }, { 1922 /* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM), 1923 /* [34] */ TNS("sysenter",NORM), TNS("sysexit",NORM), INVALID, INVALID, 1924 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1925 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1926 }, { 1927 /* [40] */ TS("cmovx.o",MR), TS("cmovx.no",MR), TS("cmovx.b",MR), TS("cmovx.ae",MR), 1928 /* [44] */ TS("cmovx.e",MR), TS("cmovx.ne",MR), TS("cmovx.be",MR), TS("cmovx.a",MR), 1929 /* [48] */ TS("cmovx.s",MR), TS("cmovx.ns",MR), TS("cmovx.pe",MR), TS("cmovx.po",MR), 1930 /* [4C] */ TS("cmovx.l",MR), TS("cmovx.ge",MR), TS("cmovx.le",MR), TS("cmovx.g",MR), 1931 }, { 1932 /* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16), 1933 /* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16), 1934 /* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16), 1935 /* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16), 1936 }, { 1937 /* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8), 1938 /* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8), 1939 /* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8), 1940 /* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8), 1941 }, { 1942 /* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR), 1943 /* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM), 1944 /* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID, 1945 /* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8), 1946 }, { 1947 /* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D), 1948 /* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D), 1949 /* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D), 1950 /* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D), 1951 }, { 1952 /* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb), 1953 /* [94] */ TNS("sete",Mb), TNS("setne",Mb), TNS("setbe",Mb), TNS("seta",Mb), 1954 /* [98] */ TNS("sets",Mb), TNS("setns",Mb), TNS("setp",Mb), TNS("setnp",Mb), 1955 /* [9C] */ TNS("setl",Mb), TNS("setge",Mb), TNS("setle",Mb), TNS("setg",Mb), 1956 }, { 1957 /* [A0] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("cpuid",NORM), TS("bt",RMw), 1958 /* [A4] */ TS("shld",DSHIFT), TS("shld",DSHIFTcl), INVALID, INVALID, 1959 /* [A8] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("rsm",NORM), TS("bts",RMw), 1960 /* [AC] */ TS("shrd",DSHIFT), TS("shrd",DSHIFTcl), IND(dis_op0FAE), TS("imul",MRw), 1961 }, { 1962 /* [B0] */ TNS("cmpxchgb",RMw), TS("cmpxchg",RMw), TS("lss",MR), TS("btr",RMw), 1963 /* [B4] */ TS("lfs",MR), TS("lgs",MR), TS("movzb",MOVZ), TNS("movzwl",MOVZ), 1964 /* [B8] */ TNS("INVALID",MRw), INVALID, IND(dis_op0FBA), TS("btc",RMw), 1965 /* [BC] */ TS("bsf",MRw), TS("bsr",MRw), TS("movsb",MOVZ), TNS("movswl",MOVZ), 1966 }, { 1967 /* [C0] */ TNS("xaddb",XADDB), TS("xadd",RMw), TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM), 1968 /* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7), 1969 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1970 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1971 }, { 1972 /* [D0] */ INVALID, TNSZ("psrlw",MMO,8), TNSZ("psrld",MMO,8), TNSZ("psrlq",MMO,8), 1973 /* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3), 1974 /* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8), 1975 /* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8), 1976 }, { 1977 /* [E0] */ TNSZ("pavgb",MMO,8), TNSZ("psraw",MMO,8), TNSZ("psrad",MMO,8), TNSZ("pavgw",MMO,8), 1978 /* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8), 1979 /* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8), 1980 /* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8), 1981 }, { 1982 /* [F0] */ INVALID, TNSZ("psllw",MMO,8), TNSZ("pslld",MMO,8), TNSZ("psllq",MMO,8), 1983 /* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8), 1984 /* [F8] */ TNSZ("psubb",MMO,8), TNSZ("psubw",MMO,8), TNSZ("psubd",MMO,8), TNSZ("psubq",MMO,8), 1985 /* [FC] */ TNSZ("paddb",MMO,8), TNSZ("paddw",MMO,8), TNSZ("paddd",MMO,8), INVALID, 1986 } }; 1987 1988 const instable_t dis_opAVX0F[16][16] = { 1989 { 1990 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1991 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1992 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1993 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1994 }, { 1995 /* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8), 1996 /* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8), 1997 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1998 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1999 }, { 2000 /* [20] */ INVALID, INVALID, INVALID, INVALID, 2001 /* [24] */ INVALID, INVALID, INVALID, INVALID, 2002 /* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16), 2003 /* [2C] */ INVALID, INVALID, TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4), 2004 }, { 2005 /* [30] */ INVALID, INVALID, INVALID, INVALID, 2006 /* [34] */ INVALID, INVALID, INVALID, INVALID, 2007 /* [38] */ INVALID, INVALID, INVALID, INVALID, 2008 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 2009 }, { 2010 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID, 2011 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX), 2012 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX), 2013 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 2014 }, { 2015 /* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16), 2016 /* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16), 2017 /* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16), 2018 /* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16), 2019 }, { 2020 /* [60] */ INVALID, INVALID, INVALID, INVALID, 2021 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2022 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2023 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2024 }, { 2025 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2026 /* [74] */ INVALID, INVALID, INVALID, TNS("vzeroupper", VEX_NONE), 2027 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2028 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2029 }, { 2030 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2031 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2032 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2033 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 2034 }, { 2035 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 2036 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2037 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID, 2038 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2039 }, { 2040 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2041 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2042 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2043 /* [AC] */ INVALID, INVALID, TNSZ("vldmxcsr",VEX_MO,2), INVALID, 2044 }, { 2045 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2046 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2047 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2048 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2049 }, { 2050 /* [C0] */ INVALID, INVALID, TNSZ("vcmpps",VEX_RMRX,16),INVALID, 2051 /* [C4] */ INVALID, INVALID, TNSZ("vshufps",VEX_RMRX,16),INVALID, 2052 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2053 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 2054 }, { 2055 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2056 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2057 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 2058 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 2059 }, { 2060 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2061 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2062 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2063 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2064 }, { 2065 /* [F0] */ INVALID, INVALID, TNSZvr("andn",VEX_RMrX,5),TNSZvr("bls",BLS,5), 2066 /* [F4] */ INVALID, TNSZvr("bzhi",VEX_VRMrX,5),INVALID, TNSZvr("bextr",VEX_VRMrX,5), 2067 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2068 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2069 } }; 2070 2071 /* 2072 * Decode table for 0x80 opcodes 2073 */ 2074 2075 const instable_t dis_op80[8] = { 2076 2077 /* [0] */ TNS("addb",IMlw), TNS("orb",IMw), TNS("adcb",IMlw), TNS("sbbb",IMlw), 2078 /* [4] */ TNS("andb",IMw), TNS("subb",IMlw), TNS("xorb",IMw), TNS("cmpb",IMlw), 2079 }; 2080 2081 2082 /* 2083 * Decode table for 0x81 opcodes. 2084 */ 2085 2086 const instable_t dis_op81[8] = { 2087 2088 /* [0] */ TS("add",IMlw), TS("or",IMw), TS("adc",IMlw), TS("sbb",IMlw), 2089 /* [4] */ TS("and",IMw), TS("sub",IMlw), TS("xor",IMw), TS("cmp",IMlw), 2090 }; 2091 2092 2093 /* 2094 * Decode table for 0x82 opcodes. 2095 */ 2096 2097 const instable_t dis_op82[8] = { 2098 2099 /* [0] */ TNSx("addb",IMlw), TNSx("orb",IMlw), TNSx("adcb",IMlw), TNSx("sbbb",IMlw), 2100 /* [4] */ TNSx("andb",IMlw), TNSx("subb",IMlw), TNSx("xorb",IMlw), TNSx("cmpb",IMlw), 2101 }; 2102 /* 2103 * Decode table for 0x83 opcodes. 2104 */ 2105 2106 const instable_t dis_op83[8] = { 2107 2108 /* [0] */ TS("add",IMlw), TS("or",IMlw), TS("adc",IMlw), TS("sbb",IMlw), 2109 /* [4] */ TS("and",IMlw), TS("sub",IMlw), TS("xor",IMlw), TS("cmp",IMlw), 2110 }; 2111 2112 /* 2113 * Decode table for 0xC0 opcodes. 2114 */ 2115 2116 const instable_t dis_opC0[8] = { 2117 2118 /* [0] */ TNS("rolb",MvI), TNS("rorb",MvI), TNS("rclb",MvI), TNS("rcrb",MvI), 2119 /* [4] */ TNS("shlb",MvI), TNS("shrb",MvI), INVALID, TNS("sarb",MvI), 2120 }; 2121 2122 /* 2123 * Decode table for 0xD0 opcodes. 2124 */ 2125 2126 const instable_t dis_opD0[8] = { 2127 2128 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 2129 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 2130 }; 2131 2132 /* 2133 * Decode table for 0xC1 opcodes. 2134 * 186 instruction set 2135 */ 2136 2137 const instable_t dis_opC1[8] = { 2138 2139 /* [0] */ TS("rol",MvI), TS("ror",MvI), TS("rcl",MvI), TS("rcr",MvI), 2140 /* [4] */ TS("shl",MvI), TS("shr",MvI), TS("sal",MvI), TS("sar",MvI), 2141 }; 2142 2143 /* 2144 * Decode table for 0xD1 opcodes. 2145 */ 2146 2147 const instable_t dis_opD1[8] = { 2148 2149 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 2150 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("sal",Mv), TS("sar",Mv), 2151 }; 2152 2153 2154 /* 2155 * Decode table for 0xD2 opcodes. 2156 */ 2157 2158 const instable_t dis_opD2[8] = { 2159 2160 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 2161 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 2162 }; 2163 /* 2164 * Decode table for 0xD3 opcodes. 2165 */ 2166 2167 const instable_t dis_opD3[8] = { 2168 2169 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 2170 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("salb",Mv), TS("sar",Mv), 2171 }; 2172 2173 2174 /* 2175 * Decode table for 0xF6 opcodes. 2176 */ 2177 2178 const instable_t dis_opF6[8] = { 2179 2180 /* [0] */ TNS("testb",IMw), TNS("testb",IMw), TNS("notb",Mw), TNS("negb",Mw), 2181 /* [4] */ TNS("mulb",MA), TNS("imulb",MA), TNS("divb",MA), TNS("idivb",MA), 2182 }; 2183 2184 2185 /* 2186 * Decode table for 0xF7 opcodes. 2187 */ 2188 2189 const instable_t dis_opF7[8] = { 2190 2191 /* [0] */ TS("test",IMw), TS("test",IMw), TS("not",Mw), TS("neg",Mw), 2192 /* [4] */ TS("mul",MA), TS("imul",MA), TS("div",MA), TS("idiv",MA), 2193 }; 2194 2195 2196 /* 2197 * Decode table for 0xFE opcodes. 2198 */ 2199 2200 const instable_t dis_opFE[8] = { 2201 2202 /* [0] */ TNS("incb",Mw), TNS("decb",Mw), INVALID, INVALID, 2203 /* [4] */ INVALID, INVALID, INVALID, INVALID, 2204 }; 2205 /* 2206 * Decode table for 0xFF opcodes. 2207 */ 2208 2209 const instable_t dis_opFF[8] = { 2210 2211 /* [0] */ TS("inc",Mw), TS("dec",Mw), TNSyp("call",INM), TNS("lcall",INM), 2212 /* [4] */ TNSy("jmp",INM), TNS("ljmp",INM), TSp("push",M), INVALID, 2213 }; 2214 2215 /* for 287 instructions, which are a mess to decode */ 2216 2217 const instable_t dis_opFP1n2[8][8] = { 2218 { 2219 /* bit pattern: 1101 1xxx MODxx xR/M */ 2220 /* [0,0] */ TNS("fadds",M), TNS("fmuls",M), TNS("fcoms",M), TNS("fcomps",M), 2221 /* [0,4] */ TNS("fsubs",M), TNS("fsubrs",M), TNS("fdivs",M), TNS("fdivrs",M), 2222 }, { 2223 /* [1,0] */ TNS("flds",M), INVALID, TNS("fsts",M), TNS("fstps",M), 2224 /* [1,4] */ TNSZ("fldenv",M,28), TNSZ("fldcw",M,2), TNSZ("fnstenv",M,28), TNSZ("fnstcw",M,2), 2225 }, { 2226 /* [2,0] */ TNS("fiaddl",M), TNS("fimull",M), TNS("ficoml",M), TNS("ficompl",M), 2227 /* [2,4] */ TNS("fisubl",M), TNS("fisubrl",M), TNS("fidivl",M), TNS("fidivrl",M), 2228 }, { 2229 /* [3,0] */ TNS("fildl",M), TNSZ("tisttpl",M,4), TNS("fistl",M), TNS("fistpl",M), 2230 /* [3,4] */ INVALID, TNSZ("fldt",M,10), INVALID, TNSZ("fstpt",M,10), 2231 }, { 2232 /* [4,0] */ TNSZ("faddl",M,8), TNSZ("fmull",M,8), TNSZ("fcoml",M,8), TNSZ("fcompl",M,8), 2233 /* [4,1] */ TNSZ("fsubl",M,8), TNSZ("fsubrl",M,8), TNSZ("fdivl",M,8), TNSZ("fdivrl",M,8), 2234 }, { 2235 /* [5,0] */ TNSZ("fldl",M,8), TNSZ("fisttpll",M,8), TNSZ("fstl",M,8), TNSZ("fstpl",M,8), 2236 /* [5,4] */ TNSZ("frstor",M,108), INVALID, TNSZ("fnsave",M,108), TNSZ("fnstsw",M,2), 2237 }, { 2238 /* [6,0] */ TNSZ("fiadd",M,2), TNSZ("fimul",M,2), TNSZ("ficom",M,2), TNSZ("ficomp",M,2), 2239 /* [6,4] */ TNSZ("fisub",M,2), TNSZ("fisubr",M,2), TNSZ("fidiv",M,2), TNSZ("fidivr",M,2), 2240 }, { 2241 /* [7,0] */ TNSZ("fild",M,2), TNSZ("fisttp",M,2), TNSZ("fist",M,2), TNSZ("fistp",M,2), 2242 /* [7,4] */ TNSZ("fbld",M,10), TNSZ("fildll",M,8), TNSZ("fbstp",M,10), TNSZ("fistpll",M,8), 2243 } }; 2244 2245 const instable_t dis_opFP3[8][8] = { 2246 { 2247 /* bit pattern: 1101 1xxx 11xx xREG */ 2248 /* [0,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 2249 /* [0,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 2250 }, { 2251 /* [1,0] */ TNS("fld",F), TNS("fxch",F), TNS("fnop",NORM), TNS("fstp",F), 2252 /* [1,4] */ INVALID, INVALID, INVALID, INVALID, 2253 }, { 2254 /* [2,0] */ INVALID, INVALID, INVALID, INVALID, 2255 /* [2,4] */ INVALID, TNS("fucompp",NORM), INVALID, INVALID, 2256 }, { 2257 /* [3,0] */ INVALID, INVALID, INVALID, INVALID, 2258 /* [3,4] */ INVALID, INVALID, INVALID, INVALID, 2259 }, { 2260 /* [4,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 2261 /* [4,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 2262 }, { 2263 /* [5,0] */ TNS("ffree",F), TNS("fxch",F), TNS("fst",F), TNS("fstp",F), 2264 /* [5,4] */ TNS("fucom",F), TNS("fucomp",F), INVALID, INVALID, 2265 }, { 2266 /* [6,0] */ TNS("faddp",FF), TNS("fmulp",FF), TNS("fcomp",F), TNS("fcompp",NORM), 2267 /* [6,4] */ TNS("fsubp",FF), TNS("fsubrp",FF), TNS("fdivp",FF), TNS("fdivrp",FF), 2268 }, { 2269 /* [7,0] */ TNS("ffreep",F), TNS("fxch",F), TNS("fstp",F), TNS("fstp",F), 2270 /* [7,4] */ TNS("fnstsw",M), TNS("fucomip",FFC), TNS("fcomip",FFC), INVALID, 2271 } }; 2272 2273 const instable_t dis_opFP4[4][8] = { 2274 { 2275 /* bit pattern: 1101 1001 111x xxxx */ 2276 /* [0,0] */ TNS("fchs",NORM), TNS("fabs",NORM), INVALID, INVALID, 2277 /* [0,4] */ TNS("ftst",NORM), TNS("fxam",NORM), TNS("ftstp",NORM), INVALID, 2278 }, { 2279 /* [1,0] */ TNS("fld1",NORM), TNS("fldl2t",NORM), TNS("fldl2e",NORM), TNS("fldpi",NORM), 2280 /* [1,4] */ TNS("fldlg2",NORM), TNS("fldln2",NORM), TNS("fldz",NORM), INVALID, 2281 }, { 2282 /* [2,0] */ TNS("f2xm1",NORM), TNS("fyl2x",NORM), TNS("fptan",NORM), TNS("fpatan",NORM), 2283 /* [2,4] */ TNS("fxtract",NORM), TNS("fprem1",NORM), TNS("fdecstp",NORM), TNS("fincstp",NORM), 2284 }, { 2285 /* [3,0] */ TNS("fprem",NORM), TNS("fyl2xp1",NORM), TNS("fsqrt",NORM), TNS("fsincos",NORM), 2286 /* [3,4] */ TNS("frndint",NORM), TNS("fscale",NORM), TNS("fsin",NORM), TNS("fcos",NORM), 2287 } }; 2288 2289 const instable_t dis_opFP5[8] = { 2290 /* bit pattern: 1101 1011 111x xxxx */ 2291 /* [0] */ TNS("feni",NORM), TNS("fdisi",NORM), TNS("fnclex",NORM), TNS("fninit",NORM), 2292 /* [4] */ TNS("fsetpm",NORM), TNS("frstpm",NORM), INVALID, INVALID, 2293 }; 2294 2295 const instable_t dis_opFP6[8] = { 2296 /* bit pattern: 1101 1011 11yy yxxx */ 2297 /* [00] */ TNS("fcmov.nb",FF), TNS("fcmov.ne",FF), TNS("fcmov.nbe",FF), TNS("fcmov.nu",FF), 2298 /* [04] */ INVALID, TNS("fucomi",F), TNS("fcomi",F), INVALID, 2299 }; 2300 2301 const instable_t dis_opFP7[8] = { 2302 /* bit pattern: 1101 1010 11yy yxxx */ 2303 /* [00] */ TNS("fcmov.b",FF), TNS("fcmov.e",FF), TNS("fcmov.be",FF), TNS("fcmov.u",FF), 2304 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2305 }; 2306 2307 /* 2308 * Main decode table for the op codes. The first two nibbles 2309 * will be used as an index into the table. If there is a 2310 * a need to further decode an instruction, the array to be 2311 * referenced is indicated with the other two entries being 2312 * empty. 2313 */ 2314 2315 const instable_t dis_distable[16][16] = { 2316 { 2317 /* [0,0] */ TNS("addb",RMw), TS("add",RMw), TNS("addb",MRw), TS("add",MRw), 2318 /* [0,4] */ TNS("addb",IA), TS("add",IA), TSx("push",SEG), TSx("pop",SEG), 2319 /* [0,8] */ TNS("orb",RMw), TS("or",RMw), TNS("orb",MRw), TS("or",MRw), 2320 /* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F), 2321 }, { 2322 /* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw), 2323 /* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG), 2324 /* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw), 2325 /* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG), 2326 }, { 2327 /* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw), 2328 /* [2,4] */ TNS("andb",IA), TS("and",IA), TNSx("%es:",OVERRIDE), TNSx("daa",NORM), 2329 /* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw), 2330 /* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM), 2331 }, { 2332 /* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw), 2333 /* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNSx("%ss:",OVERRIDE), TNSx("aaa",NORM), 2334 /* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw), 2335 /* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNSx("%ds:",OVERRIDE), TNSx("aas",NORM), 2336 }, { 2337 /* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 2338 /* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 2339 /* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 2340 /* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 2341 }, { 2342 /* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 2343 /* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 2344 /* [5,8] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 2345 /* [5,C] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 2346 }, { 2347 /* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",RM), TNS("arpl",RMw), 2348 /* [6,4] */ TNS("%fs:",OVERRIDE), TNS("%gs:",OVERRIDE), TNS("data16",DM), TNS("addr16",AM), 2349 /* [6,8] */ TSp("push",I), TS("imul",IMUL), TSp("push",Ib), TS("imul",IMUL), 2350 /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4), 2351 }, { 2352 /* [7,0] */ TNSy("jo",BD), TNSy("jno",BD), TNSy("jb",BD), TNSy("jae",BD), 2353 /* [7,4] */ TNSy("je",BD), TNSy("jne",BD), TNSy("jbe",BD), TNSy("ja",BD), 2354 /* [7,8] */ TNSy("js",BD), TNSy("jns",BD), TNSy("jp",BD), TNSy("jnp",BD), 2355 /* [7,C] */ TNSy("jl",BD), TNSy("jge",BD), TNSy("jle",BD), TNSy("jg",BD), 2356 }, { 2357 /* [8,0] */ IND(dis_op80), IND(dis_op81), INDx(dis_op82), IND(dis_op83), 2358 /* [8,4] */ TNS("testb",RMw), TS("test",RMw), TNS("xchgb",RMw), TS("xchg",RMw), 2359 /* [8,8] */ TNS("movb",RMw), TS("mov",RMw), TNS("movb",MRw), TS("mov",MRw), 2360 /* [8,C] */ TNS("movw",SM), TS("lea",MR), TNS("movw",MS), TSp("pop",M), 2361 }, { 2362 /* [9,0] */ TNS("nop",NORM), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 2363 /* [9,4] */ TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 2364 /* [9,8] */ TNS("cXtX",CBW), TNS("cXtX",CWD), TNSx("lcall",SO), TNS("fwait",NORM), 2365 /* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNS("sahf",NORM), TNS("lahf",NORM), 2366 }, { 2367 /* [A,0] */ TNS("movb",OA), TS("mov",OA), TNS("movb",AO), TS("mov",AO), 2368 /* [A,4] */ TNSZ("movsb",SD,1), TS("movs",SD), TNSZ("cmpsb",SD,1), TS("cmps",SD), 2369 /* [A,8] */ TNS("testb",IA), TS("test",IA), TNS("stosb",AD), TS("stos",AD), 2370 /* [A,C] */ TNS("lodsb",SA), TS("lods",SA), TNS("scasb",AD), TS("scas",AD), 2371 }, { 2372 /* [B,0] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 2373 /* [B,4] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 2374 /* [B,8] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 2375 /* [B,C] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 2376 }, { 2377 /* [C,0] */ IND(dis_opC0), IND(dis_opC1), TNSyp("ret",RET), TNSyp("ret",NORM), 2378 /* [C,4] */ TNSx("les",MR), TNSx("lds",MR), TNS("movb",IMw), TS("mov",IMw), 2379 /* [C,8] */ TNSyp("enter",ENTER), TNSyp("leave",NORM), TNS("lret",RET), TNS("lret",NORM), 2380 /* [C,C] */ TNS("int",INT3), TNS("int",INTx), TNSx("into",NORM), TNS("iret",NORM), 2381 }, { 2382 /* [D,0] */ IND(dis_opD0), IND(dis_opD1), IND(dis_opD2), IND(dis_opD3), 2383 /* [D,4] */ TNSx("aam",U), TNSx("aad",U), TNSx("falc",NORM), TNSZ("xlat",IMPLMEM,1), 2384 2385 /* 287 instructions. Note that although the indirect field */ 2386 /* indicates opFP1n2 for further decoding, this is not necessarily */ 2387 /* the case since the opFP arrays are not partitioned according to key1 */ 2388 /* and key2. opFP1n2 is given only to indicate that we haven't */ 2389 /* finished decoding the instruction. */ 2390 /* [D,8] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 2391 /* [D,C] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 2392 }, { 2393 /* [E,0] */ TNSy("loopnz",BD), TNSy("loopz",BD), TNSy("loop",BD), TNSy("jcxz",BD), 2394 /* [E,4] */ TNS("inb",P), TS("in",P), TNS("outb",P), TS("out",P), 2395 /* [E,8] */ TNSyp("call",D), TNSy("jmp",D), TNSx("ljmp",SO), TNSy("jmp",BD), 2396 /* [E,C] */ TNS("inb",V), TS("in",V), TNS("outb",V), TS("out",V), 2397 }, { 2398 /* [F,0] */ TNS("lock",LOCK), TNS("icebp", NORM), TNS("repnz",PREFIX), TNS("repz",PREFIX), 2399 /* [F,4] */ TNS("hlt",NORM), TNS("cmc",NORM), IND(dis_opF6), IND(dis_opF7), 2400 /* [F,8] */ TNS("clc",NORM), TNS("stc",NORM), TNS("cli",NORM), TNS("sti",NORM), 2401 /* [F,C] */ TNS("cld",NORM), TNS("std",NORM), IND(dis_opFE), IND(dis_opFF), 2402 } }; 2403 2404 /* END CSTYLED */ 2405 2406 /* 2407 * common functions to decode and disassemble an x86 or amd64 instruction 2408 */ 2409 2410 /* 2411 * These are the individual fields of a REX prefix. Note that a REX 2412 * prefix with none of these set is still needed to: 2413 * - use the MOVSXD (sign extend 32 to 64 bits) instruction 2414 * - access the %sil, %dil, %bpl, %spl registers 2415 */ 2416 #define REX_W 0x08 /* 64 bit operand size when set */ 2417 #define REX_R 0x04 /* high order bit extension of ModRM reg field */ 2418 #define REX_X 0x02 /* high order bit extension of SIB index field */ 2419 #define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */ 2420 2421 /* 2422 * These are the individual fields of a VEX/EVEX prefix. 2423 */ 2424 #define VEX_R 0x08 /* REX.R in 1's complement form */ 2425 #define VEX_X 0x04 /* REX.X in 1's complement form */ 2426 #define VEX_B 0x02 /* REX.B in 1's complement form */ 2427 2428 /* Additional EVEX prefix definitions */ 2429 #define EVEX_R 0x01 /* REX.R' in 1's complement form */ 2430 #define EVEX_OPREG_MASK 0x7 /* bit mask for selecting opmask register number */ 2431 #define EVEX_ZERO_MASK 0x80 /* bit mask for selecting zeroing */ 2432 2433 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */ 2434 #define VEX_L 0x04 2435 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector, 2: 512-bit */ 2436 #define EVEX_L 0x06 /* bit mask for EVEX.L'L vector length/RC */ 2437 #define VEX_W 0x08 /* opcode specific, use like REX.W */ 2438 #define VEX_m 0x1F /* VEX m-mmmm field */ 2439 #define EVEX_m 0x3 /* EVEX mm field */ 2440 #define VEX_v 0x78 /* VEX/EVEX register specifier */ 2441 #define VEX_p 0x03 /* VEX pp field, opcode extension */ 2442 2443 /* VEX m-mmmm field, only used by three bytes prefix */ 2444 #define VEX_m_0F 0x01 /* implied 0F leading opcode byte */ 2445 #define VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */ 2446 #define VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */ 2447 2448 /* VEX pp field, providing equivalent functionality of a SIMD prefix */ 2449 #define VEX_p_66 0x01 2450 #define VEX_p_F3 0x02 2451 #define VEX_p_F2 0x03 2452 2453 /* 2454 * Even in 64 bit mode, usually only 4 byte immediate operands are supported. 2455 */ 2456 static int isize[] = {1, 2, 4, 4}; 2457 static int isize64[] = {1, 2, 4, 8}; 2458 2459 /* 2460 * Just a bunch of useful macros. 2461 */ 2462 #define WBIT(x) (x & 0x1) /* to get w bit */ 2463 #define REGNO(x) (x & 0x7) /* to get 3 bit register */ 2464 #define VBIT(x) ((x)>>1 & 0x1) /* to get 'v' bit */ 2465 #define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1) 2466 #define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1) 2467 2468 #define REG_ONLY 3 /* mode to indicate a register operand (not memory) */ 2469 2470 #define BYTE_OPND 0 /* w-bit value indicating byte register */ 2471 #define LONG_OPND 1 /* w-bit value indicating opnd_size register */ 2472 #define MM_OPND 2 /* "value" used to indicate a mmx reg */ 2473 #define XMM_OPND 3 /* "value" used to indicate a xmm reg */ 2474 #define SEG_OPND 4 /* "value" used to indicate a segment reg */ 2475 #define CONTROL_OPND 5 /* "value" used to indicate a control reg */ 2476 #define DEBUG_OPND 6 /* "value" used to indicate a debug reg */ 2477 #define TEST_OPND 7 /* "value" used to indicate a test reg */ 2478 #define WORD_OPND 8 /* w-bit value indicating word size reg */ 2479 #define YMM_OPND 9 /* "value" used to indicate a ymm reg */ 2480 #define KOPMASK_OPND 10 /* "value" used to indicate an opmask reg */ 2481 #define ZMM_OPND 11 /* "value" used to indicate a zmm reg */ 2482 2483 /* 2484 * The AVX2 gather instructions are a bit of a mess. While there's a pattern, 2485 * there's not really a consistent scheme that we can use to know what the mode 2486 * is supposed to be for a given type. Various instructions, like VPGATHERDD, 2487 * always match the value of VEX_L. Other instructions like VPGATHERDQ, have 2488 * some registers match VEX_L, but the VSIB is always XMM. 2489 * 2490 * The simplest way to deal with this is to just define a table based on the 2491 * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into 2492 * them. 2493 * 2494 * We further have to subdivide this based on the value of VEX_W and the value 2495 * of VEX_L. The array is constructed to be indexed as: 2496 * [opcode - 0x90][VEX_W][VEX_L]. 2497 */ 2498 /* w = 0, 0x90 */ 2499 typedef struct dis_gather_regs { 2500 uint_t dgr_arg0; /* src reg */ 2501 uint_t dgr_arg1; /* vsib reg */ 2502 uint_t dgr_arg2; /* dst reg */ 2503 char *dgr_suffix; /* suffix to append */ 2504 } dis_gather_regs_t; 2505 2506 static dis_gather_regs_t dis_vgather[4][2][2] = { 2507 { 2508 /* op 0x90, W.0 */ 2509 { 2510 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2511 { YMM_OPND, YMM_OPND, YMM_OPND, "d" } 2512 }, 2513 /* op 0x90, W.1 */ 2514 { 2515 { XMM_OPND, XMM_OPND, XMM_OPND, "q" }, 2516 { YMM_OPND, XMM_OPND, YMM_OPND, "q" } 2517 } 2518 }, 2519 { 2520 /* op 0x91, W.0 */ 2521 { 2522 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2523 { XMM_OPND, YMM_OPND, XMM_OPND, "d" }, 2524 }, 2525 /* op 0x91, W.1 */ 2526 { 2527 { XMM_OPND, XMM_OPND, XMM_OPND, "q" }, 2528 { YMM_OPND, YMM_OPND, YMM_OPND, "q" }, 2529 } 2530 }, 2531 { 2532 /* op 0x92, W.0 */ 2533 { 2534 { XMM_OPND, XMM_OPND, XMM_OPND, "s" }, 2535 { YMM_OPND, YMM_OPND, YMM_OPND, "s" } 2536 }, 2537 /* op 0x92, W.1 */ 2538 { 2539 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2540 { YMM_OPND, XMM_OPND, YMM_OPND, "d" } 2541 } 2542 }, 2543 { 2544 /* op 0x93, W.0 */ 2545 { 2546 { XMM_OPND, XMM_OPND, XMM_OPND, "s" }, 2547 { XMM_OPND, YMM_OPND, XMM_OPND, "s" } 2548 }, 2549 /* op 0x93, W.1 */ 2550 { 2551 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2552 { YMM_OPND, YMM_OPND, YMM_OPND, "d" } 2553 } 2554 } 2555 }; 2556 2557 /* 2558 * Get the next byte and separate the op code into the high and low nibbles. 2559 */ 2560 static int 2561 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low) 2562 { 2563 int byte; 2564 2565 /* 2566 * x86 instructions have a maximum length of 15 bytes. Bail out if 2567 * we try to read more. 2568 */ 2569 if (x->d86_len >= 15) 2570 return (x->d86_error = 1); 2571 2572 if (x->d86_error) 2573 return (1); 2574 byte = x->d86_get_byte(x->d86_data); 2575 if (byte < 0) 2576 return (x->d86_error = 1); 2577 x->d86_bytes[x->d86_len++] = byte; 2578 *low = byte & 0xf; /* ----xxxx low 4 bits */ 2579 *high = byte >> 4 & 0xf; /* xxxx---- bits 7 to 4 */ 2580 return (0); 2581 } 2582 2583 /* 2584 * Get and decode an SIB (scaled index base) byte 2585 */ 2586 static void 2587 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base) 2588 { 2589 int byte; 2590 2591 if (x->d86_error) 2592 return; 2593 2594 byte = x->d86_get_byte(x->d86_data); 2595 if (byte < 0) { 2596 x->d86_error = 1; 2597 return; 2598 } 2599 x->d86_bytes[x->d86_len++] = byte; 2600 2601 *base = byte & 0x7; 2602 *index = (byte >> 3) & 0x7; 2603 *ss = (byte >> 6) & 0x3; 2604 } 2605 2606 /* 2607 * Get the byte following the op code and separate it into the 2608 * mode, register, and r/m fields. 2609 */ 2610 static void 2611 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m) 2612 { 2613 if (x->d86_got_modrm == 0) { 2614 if (x->d86_rmindex == -1) 2615 x->d86_rmindex = x->d86_len; 2616 dtrace_get_SIB(x, mode, reg, r_m); 2617 x->d86_got_modrm = 1; 2618 } 2619 } 2620 2621 /* 2622 * Adjust register selection based on any REX prefix bits present. 2623 */ 2624 /*ARGSUSED*/ 2625 static void 2626 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m) 2627 { 2628 if (reg != NULL && r_m == NULL) { 2629 if (rex_prefix & REX_B) 2630 *reg += 8; 2631 } else { 2632 if (reg != NULL && (REX_R & rex_prefix) != 0) 2633 *reg += 8; 2634 if (r_m != NULL && (REX_B & rex_prefix) != 0) 2635 *r_m += 8; 2636 } 2637 } 2638 2639 /* 2640 * Adjust register selection based on any VEX prefix bits present. 2641 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix 2642 */ 2643 /*ARGSUSED*/ 2644 static void 2645 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m) 2646 { 2647 if (reg != NULL && r_m == NULL) { 2648 if (!(vex_byte1 & VEX_B)) 2649 *reg += 8; 2650 } else { 2651 if (reg != NULL && ((VEX_R & vex_byte1) == 0)) 2652 *reg += 8; 2653 if (r_m != NULL && ((VEX_B & vex_byte1) == 0)) 2654 *r_m += 8; 2655 } 2656 } 2657 2658 /* 2659 * Adjust the instruction mnemonic with the appropriate suffix. 2660 */ 2661 /* ARGSUSED */ 2662 static void 2663 dtrace_evex_mnem_adjust(dis86_t *x, instable_t *dp, uint_t vex_W, 2664 uint_t evex_byte2) 2665 { 2666 #ifdef DIS_TEXT 2667 if (dp == &dis_opAVX62[0x7f] || /* vmovdq */ 2668 dp == &dis_opAVX62[0x6f]) { 2669 /* Aligned or Unaligned? */ 2670 if ((evex_byte2 & 0x3) == 0x01) { 2671 (void) strlcat(x->d86_mnem, "a", OPLEN); 2672 (void) strlcat(x->d86_mnem, vex_W != 0 ? "64" : "32", 2673 OPLEN); 2674 } else { 2675 (void) strlcat(x->d86_mnem, "u", OPLEN); 2676 switch (evex_byte2 & 0x81) { 2677 case 0x0: 2678 (void) strlcat(x->d86_mnem, "32", OPLEN); 2679 break; 2680 case 0x1: 2681 (void) strlcat(x->d86_mnem, "8", OPLEN); 2682 break; 2683 case 0x80: 2684 (void) strlcat(x->d86_mnem, "64", OPLEN); 2685 break; 2686 case 0x81: 2687 (void) strlcat(x->d86_mnem, "16", OPLEN); 2688 break; 2689 } 2690 } 2691 2692 } else { 2693 if (dp->it_avxsuf == AVS5Q) { 2694 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d", 2695 OPLEN); 2696 } else { 2697 (void) strlcat(x->d86_mnem, vex_W != 0 ? "d" : "s", 2698 OPLEN); 2699 } 2700 } 2701 #endif 2702 } 2703 2704 /* 2705 * The following three functions adjust the register selection based on any 2706 * EVEX prefix bits present. See Intel 64 and IA-32 Architectures Software 2707 * Developer’s Manual Volume 2 (IASDv2), section 2.6.1 Table 2-30 and 2708 * section 2.6.2 Table 2-31. 2709 */ 2710 static void 2711 dtrace_evex_adjust_reg(uint_t evex_byte1, uint_t *reg) 2712 { 2713 if (reg != NULL) { 2714 if ((VEX_R & evex_byte1) == 0) { 2715 *reg += 8; 2716 } 2717 if ((EVEX_R & evex_byte1) == 0) { 2718 *reg += 16; 2719 } 2720 } 2721 } 2722 2723 static void 2724 dtrace_evex_adjust_rm(uint_t evex_byte1, uint_t *r_m) 2725 { 2726 if (r_m != NULL) { 2727 if ((VEX_B & evex_byte1) == 0) { 2728 *r_m += 8; 2729 } 2730 if ((VEX_X & evex_byte1) == 0) { 2731 *r_m += 16; 2732 } 2733 } 2734 } 2735 2736 /* 2737 * Use evex_L to set wbit. See IASDv2 Section 2.6.10 and Table 2-36. 2738 */ 2739 static void 2740 dtrace_evex_adjust_reg_name(uint_t evex_L, uint_t *wbitp) 2741 { 2742 switch (evex_L) { 2743 case 0x0: 2744 *wbitp = XMM_OPND; 2745 break; 2746 case 0x1: 2747 *wbitp = YMM_OPND; 2748 break; 2749 case 0x2: 2750 *wbitp = ZMM_OPND; 2751 break; 2752 } 2753 } 2754 2755 /* 2756 * Adjust operand value for disp8*N immediate. See IASDv2 Section 2.6.5. 2757 * This currently only handles a subset of the possibilities. 2758 */ 2759 static void 2760 dtrace_evex_adjust_disp8_n(dis86_t *x, int opindex, uint_t L, uint_t modrm) 2761 { 2762 d86opnd_t *opnd = &x->d86_opnd[opindex]; 2763 2764 if (x->d86_error) 2765 return; 2766 2767 /* Check disp8 bit in the ModR/M byte */ 2768 if ((modrm & 0x80) == 0x80) 2769 return; 2770 2771 /* use evex_L to adjust the value */ 2772 switch (L) { 2773 case 0x0: 2774 opnd->d86_value *= 16; 2775 break; 2776 case 0x1: 2777 opnd->d86_value *= 32; 2778 break; 2779 case 0x2: 2780 opnd->d86_value *= 64; 2781 break; 2782 } 2783 } 2784 2785 /* 2786 * Adjust target for opmask and zeroing. See IASDv2 Section 2.6.1 Table 2-30. 2787 */ 2788 /* ARGSUSED */ 2789 static void 2790 dtrace_evex_adjust_z_opmask(dis86_t *x, uint_t tgtop, uint_t evex_byte3) 2791 { 2792 #ifdef DIS_TEXT 2793 char *opnd = x->d86_opnd[tgtop].d86_opnd; 2794 int opmask_reg = evex_byte3 & EVEX_OPREG_MASK; 2795 #endif 2796 if (x->d86_error) 2797 return; 2798 2799 #ifdef DIS_TEXT 2800 if (opmask_reg != 0) { 2801 /* Append the opmask register to operand 1 */ 2802 (void) strlcat(opnd, "{", OPLEN); 2803 (void) strlcat(opnd, dis_KOPMASKREG[opmask_reg], OPLEN); 2804 (void) strlcat(opnd, "}", OPLEN); 2805 } 2806 if ((evex_byte3 & EVEX_ZERO_MASK) != 0) { 2807 /* Append the 'zeroing' modifier to operand 1 */ 2808 (void) strlcat(opnd, "{z}", OPLEN); 2809 } 2810 #endif /* DIS_TEXT */ 2811 } 2812 2813 /* 2814 * Get an immediate operand of the given size, with sign extension. 2815 */ 2816 static void 2817 dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex) 2818 { 2819 int i; 2820 int byte; 2821 int valsize; 2822 2823 if (x->d86_numopnds < opindex + 1) 2824 x->d86_numopnds = opindex + 1; 2825 2826 switch (wbit) { 2827 case BYTE_OPND: 2828 valsize = 1; 2829 break; 2830 case LONG_OPND: 2831 if (x->d86_opnd_size == SIZE16) 2832 valsize = 2; 2833 else if (x->d86_opnd_size == SIZE32) 2834 valsize = 4; 2835 else 2836 valsize = 8; 2837 break; 2838 case MM_OPND: 2839 case XMM_OPND: 2840 case YMM_OPND: 2841 case ZMM_OPND: 2842 case SEG_OPND: 2843 case CONTROL_OPND: 2844 case DEBUG_OPND: 2845 case TEST_OPND: 2846 valsize = size; 2847 break; 2848 case WORD_OPND: 2849 valsize = 2; 2850 break; 2851 } 2852 if (valsize < size) 2853 valsize = size; 2854 2855 if (x->d86_error) 2856 return; 2857 x->d86_opnd[opindex].d86_value = 0; 2858 for (i = 0; i < size; ++i) { 2859 byte = x->d86_get_byte(x->d86_data); 2860 if (byte < 0) { 2861 x->d86_error = 1; 2862 return; 2863 } 2864 x->d86_bytes[x->d86_len++] = byte; 2865 x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8); 2866 } 2867 /* Do sign extension */ 2868 if (x->d86_bytes[x->d86_len - 1] & 0x80) { 2869 for (; i < sizeof (uint64_t); i++) 2870 x->d86_opnd[opindex].d86_value |= 2871 (uint64_t)0xff << (i * 8); 2872 } 2873 #ifdef DIS_TEXT 2874 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 2875 x->d86_opnd[opindex].d86_value_size = valsize; 2876 x->d86_imm_bytes += size; 2877 #endif 2878 } 2879 2880 /* 2881 * Get an ip relative operand of the given size, with sign extension. 2882 */ 2883 static void 2884 dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex) 2885 { 2886 dtrace_imm_opnd(x, wbit, size, opindex); 2887 #ifdef DIS_TEXT 2888 x->d86_opnd[opindex].d86_mode = MODE_IPREL; 2889 #endif 2890 } 2891 2892 /* 2893 * Check to see if there is a segment override prefix pending. 2894 * If so, print it in the current 'operand' location and set 2895 * the override flag back to false. 2896 */ 2897 /*ARGSUSED*/ 2898 static void 2899 dtrace_check_override(dis86_t *x, int opindex) 2900 { 2901 #ifdef DIS_TEXT 2902 if (x->d86_seg_prefix) { 2903 (void) strlcat(x->d86_opnd[opindex].d86_prefix, 2904 x->d86_seg_prefix, PFIXLEN); 2905 } 2906 #endif 2907 x->d86_seg_prefix = NULL; 2908 } 2909 2910 2911 /* 2912 * Process a single instruction Register or Memory operand. 2913 * 2914 * mode = addressing mode from ModRM byte 2915 * r_m = r_m (or reg if mode == 3) field from ModRM byte 2916 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use. 2917 * o = index of operand that we are processing (0, 1 or 2) 2918 * 2919 * the value of reg or r_m must have already been adjusted for any REX prefix. 2920 */ 2921 /*ARGSUSED*/ 2922 static void 2923 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex) 2924 { 2925 int have_SIB = 0; /* flag presence of scale-index-byte */ 2926 uint_t ss; /* scale-factor from opcode */ 2927 uint_t index; /* index register number */ 2928 uint_t base; /* base register number */ 2929 int dispsize; /* size of displacement in bytes */ 2930 #ifdef DIS_TEXT 2931 char *opnd = x->d86_opnd[opindex].d86_opnd; 2932 #endif 2933 2934 if (x->d86_numopnds < opindex + 1) 2935 x->d86_numopnds = opindex + 1; 2936 2937 if (x->d86_error) 2938 return; 2939 2940 /* 2941 * first handle a simple register 2942 */ 2943 if (mode == REG_ONLY) { 2944 #ifdef DIS_TEXT 2945 switch (wbit) { 2946 case MM_OPND: 2947 (void) strlcat(opnd, dis_MMREG[r_m], OPLEN); 2948 break; 2949 case XMM_OPND: 2950 (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN); 2951 break; 2952 case YMM_OPND: 2953 (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN); 2954 break; 2955 case ZMM_OPND: 2956 (void) strlcat(opnd, dis_ZMMREG[r_m], OPLEN); 2957 break; 2958 case KOPMASK_OPND: 2959 (void) strlcat(opnd, dis_KOPMASKREG[r_m], OPLEN); 2960 break; 2961 case SEG_OPND: 2962 (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN); 2963 break; 2964 case CONTROL_OPND: 2965 (void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN); 2966 break; 2967 case DEBUG_OPND: 2968 (void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN); 2969 break; 2970 case TEST_OPND: 2971 (void) strlcat(opnd, dis_TESTREG[r_m], OPLEN); 2972 break; 2973 case BYTE_OPND: 2974 if (x->d86_rex_prefix == 0) 2975 (void) strlcat(opnd, dis_REG8[r_m], OPLEN); 2976 else 2977 (void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN); 2978 break; 2979 case WORD_OPND: 2980 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 2981 break; 2982 case LONG_OPND: 2983 if (x->d86_opnd_size == SIZE16) 2984 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 2985 else if (x->d86_opnd_size == SIZE32) 2986 (void) strlcat(opnd, dis_REG32[r_m], OPLEN); 2987 else 2988 (void) strlcat(opnd, dis_REG64[r_m], OPLEN); 2989 break; 2990 } 2991 #endif /* DIS_TEXT */ 2992 return; 2993 } 2994 2995 /* 2996 * if symbolic representation, skip override prefix, if any 2997 */ 2998 dtrace_check_override(x, opindex); 2999 3000 /* 3001 * Handle 16 bit memory references first, since they decode 3002 * the mode values more simply. 3003 * mode 1 is r_m + 8 bit displacement 3004 * mode 2 is r_m + 16 bit displacement 3005 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp 3006 */ 3007 if (x->d86_addr_size == SIZE16) { 3008 if ((mode == 0 && r_m == 6) || mode == 2) 3009 dtrace_imm_opnd(x, WORD_OPND, 2, opindex); 3010 else if (mode == 1) 3011 dtrace_imm_opnd(x, BYTE_OPND, 1, opindex); 3012 #ifdef DIS_TEXT 3013 if (mode == 0 && r_m == 6) 3014 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 3015 else if (mode == 0) 3016 x->d86_opnd[opindex].d86_mode = MODE_NONE; 3017 else 3018 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 3019 (void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN); 3020 #endif 3021 return; 3022 } 3023 3024 /* 3025 * 32 and 64 bit addressing modes are more complex since they 3026 * can involve an SIB (scaled index and base) byte to decode. 3027 */ 3028 if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8) { 3029 have_SIB = 1; 3030 dtrace_get_SIB(x, &ss, &index, &base); 3031 if (x->d86_error) 3032 return; 3033 if (base != 5 || mode != 0) 3034 if (x->d86_rex_prefix & REX_B) 3035 base += 8; 3036 if (x->d86_rex_prefix & REX_X) 3037 index += 8; 3038 } else { 3039 base = r_m; 3040 } 3041 3042 /* 3043 * Compute the displacement size and get its bytes 3044 */ 3045 dispsize = 0; 3046 3047 if (mode == 1) 3048 dispsize = 1; 3049 else if (mode == 2) 3050 dispsize = 4; 3051 else if ((r_m & 7) == EBP_REGNO || 3052 (have_SIB && (base & 7) == EBP_REGNO)) 3053 dispsize = 4; 3054 3055 if (dispsize > 0) { 3056 dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND, 3057 dispsize, opindex); 3058 if (x->d86_error) 3059 return; 3060 } 3061 3062 #ifdef DIS_TEXT 3063 if (dispsize > 0) 3064 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 3065 3066 if (have_SIB == 0) { 3067 if (x->d86_mode == SIZE32) { 3068 if (mode == 0) 3069 (void) strlcat(opnd, dis_addr32_mode0[r_m], 3070 OPLEN); 3071 else 3072 (void) strlcat(opnd, dis_addr32_mode12[r_m], 3073 OPLEN); 3074 } else { 3075 if (mode == 0) { 3076 (void) strlcat(opnd, dis_addr64_mode0[r_m], 3077 OPLEN); 3078 if (r_m == 5) { 3079 x->d86_opnd[opindex].d86_mode = 3080 MODE_RIPREL; 3081 } 3082 } else { 3083 (void) strlcat(opnd, dis_addr64_mode12[r_m], 3084 OPLEN); 3085 } 3086 } 3087 } else { 3088 uint_t need_paren = 0; 3089 char **regs; 3090 char **bregs; 3091 const char *const *sf; 3092 if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */ 3093 regs = (char **)dis_REG32; 3094 else 3095 regs = (char **)dis_REG64; 3096 3097 if (x->d86_vsib != 0) { 3098 if (wbit == YMM_OPND) { /* NOTE this is not addr_size */ 3099 bregs = (char **)dis_YMMREG; 3100 } else if (wbit == XMM_OPND) { 3101 bregs = (char **)dis_XMMREG; 3102 } else { 3103 bregs = (char **)dis_ZMMREG; 3104 } 3105 sf = dis_vscale_factor; 3106 } else { 3107 bregs = regs; 3108 sf = dis_scale_factor; 3109 } 3110 3111 /* 3112 * print the base (if any) 3113 */ 3114 if (base == EBP_REGNO && mode == 0) { 3115 if (index != ESP_REGNO || x->d86_vsib != 0) { 3116 (void) strlcat(opnd, "(", OPLEN); 3117 need_paren = 1; 3118 } 3119 } else { 3120 (void) strlcat(opnd, "(", OPLEN); 3121 (void) strlcat(opnd, regs[base], OPLEN); 3122 need_paren = 1; 3123 } 3124 3125 /* 3126 * print the index (if any) 3127 */ 3128 if (index != ESP_REGNO || x->d86_vsib) { 3129 (void) strlcat(opnd, ",", OPLEN); 3130 (void) strlcat(opnd, bregs[index], OPLEN); 3131 (void) strlcat(opnd, sf[ss], OPLEN); 3132 } else 3133 if (need_paren) 3134 (void) strlcat(opnd, ")", OPLEN); 3135 } 3136 #endif 3137 } 3138 3139 /* 3140 * Operand sequence for standard instruction involving one register 3141 * and one register/memory operand. 3142 * wbit indicates a byte(0) or opnd_size(1) operation 3143 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r") 3144 */ 3145 #define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \ 3146 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3147 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3148 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 3149 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \ 3150 } 3151 3152 /* 3153 * Similar to above, but allows for the two operands to be of different 3154 * classes (ie. wbit). 3155 * wbit is for the r_m operand 3156 * w2 is for the reg operand 3157 */ 3158 #define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \ 3159 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3160 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3161 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 3162 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \ 3163 } 3164 3165 /* 3166 * Similar, but for 2 operands plus an immediate. 3167 * vbit indicates direction 3168 * 0 for "opcode imm, r, r_m" or 3169 * 1 for "opcode imm, r_m, r" 3170 */ 3171 #define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \ 3172 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3173 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3174 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \ 3175 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \ 3176 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3177 } 3178 3179 /* 3180 * Similar, but for 2 operands plus two immediates. 3181 */ 3182 #define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \ 3183 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3184 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3185 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 3186 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \ 3187 dtrace_imm_opnd(x, wbit, immsize, 1); \ 3188 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3189 } 3190 3191 /* 3192 * 1 operands plus two immediates. 3193 */ 3194 #define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \ 3195 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3196 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3197 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 3198 dtrace_imm_opnd(x, wbit, immsize, 1); \ 3199 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3200 } 3201 3202 /* 3203 * Dissassemble a single x86 or amd64 instruction. 3204 * 3205 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64) 3206 * for interpreting instructions. 3207 * 3208 * returns non-zero for bad opcode 3209 */ 3210 int 3211 dtrace_disx86(dis86_t *x, uint_t cpu_mode) 3212 { 3213 instable_t *dp; /* decode table being used */ 3214 #ifdef DIS_TEXT 3215 uint_t i; 3216 #endif 3217 #ifdef DIS_MEM 3218 uint_t nomem = 0; 3219 #define NOMEM (nomem = 1) 3220 #else 3221 #define NOMEM /* nothing */ 3222 #endif 3223 uint_t opnd_size; /* SIZE16, SIZE32 or SIZE64 */ 3224 uint_t addr_size; /* SIZE16, SIZE32 or SIZE64 */ 3225 uint_t wbit; /* opcode wbit, 0 is 8 bit, !0 for opnd_size */ 3226 uint_t w2; /* wbit value for second operand */ 3227 uint_t vbit; 3228 uint_t mode = 0; /* mode value from ModRM byte */ 3229 uint_t reg; /* reg value from ModRM byte */ 3230 uint_t r_m; /* r_m value from ModRM byte */ 3231 3232 uint_t opcode1; /* high nibble of 1st byte */ 3233 uint_t opcode2; /* low nibble of 1st byte */ 3234 uint_t opcode3; /* extra opcode bits usually from ModRM byte */ 3235 uint_t opcode4; /* high nibble of 2nd byte */ 3236 uint_t opcode5; /* low nibble of 2nd byte */ 3237 uint_t opcode6; /* high nibble of 3rd byte */ 3238 uint_t opcode7; /* low nibble of 3rd byte */ 3239 uint_t opcode8; /* high nibble of 4th byte */ 3240 uint_t opcode9; /* low nibble of 4th byte */ 3241 uint_t opcode_bytes = 1; 3242 3243 /* 3244 * legacy prefixes come in 5 flavors, you should have only one of each 3245 */ 3246 uint_t opnd_size_prefix = 0; 3247 uint_t addr_size_prefix = 0; 3248 uint_t segment_prefix = 0; 3249 uint_t lock_prefix = 0; 3250 uint_t rep_prefix = 0; 3251 uint_t rex_prefix = 0; /* amd64 register extension prefix */ 3252 3253 /* 3254 * Intel VEX instruction encoding prefix and fields 3255 */ 3256 3257 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */ 3258 uint_t vex_prefix = 0; 3259 3260 /* 3261 * VEX prefix byte 1, includes vex.r, vex.x and vex.b 3262 * (for 3 bytes prefix) 3263 */ 3264 uint_t vex_byte1 = 0; 3265 3266 /* 3267 * EVEX prefix byte 1 includes vex.r, vex.x, vex.b and evex.r. 3268 */ 3269 uint_t evex_byte1 = 0; 3270 uint_t evex_byte2 = 0; 3271 uint_t evex_byte3 = 0; 3272 3273 /* 3274 * For 32-bit mode, it should prefetch the next byte to 3275 * distinguish between AVX and les/lds 3276 */ 3277 uint_t vex_prefetch = 0; 3278 3279 uint_t vex_m = 0; 3280 uint_t vex_v = 0; 3281 uint_t vex_p = 0; 3282 uint_t vex_R = 1; 3283 uint_t vex_X = 1; 3284 uint_t vex_B = 1; 3285 uint_t vex_W = 0; 3286 uint_t vex_L = 0; 3287 uint_t evex_L = 0; 3288 uint_t evex_modrm = 0; 3289 dis_gather_regs_t *vreg; 3290 3291 #ifdef DIS_TEXT 3292 /* Instruction name for BLS* family of instructions */ 3293 char *blsinstr; 3294 #endif 3295 3296 size_t off; 3297 3298 instable_t dp_mmx; 3299 3300 x->d86_len = 0; 3301 x->d86_rmindex = -1; 3302 x->d86_error = 0; 3303 #ifdef DIS_TEXT 3304 x->d86_numopnds = 0; 3305 x->d86_seg_prefix = NULL; 3306 x->d86_mnem[0] = 0; 3307 for (i = 0; i < 4; ++i) { 3308 x->d86_opnd[i].d86_opnd[0] = 0; 3309 x->d86_opnd[i].d86_prefix[0] = 0; 3310 x->d86_opnd[i].d86_value_size = 0; 3311 x->d86_opnd[i].d86_value = 0; 3312 x->d86_opnd[i].d86_mode = MODE_NONE; 3313 } 3314 #endif 3315 x->d86_rex_prefix = 0; 3316 x->d86_got_modrm = 0; 3317 x->d86_memsize = 0; 3318 x->d86_vsib = 0; 3319 3320 if (cpu_mode == SIZE16) { 3321 opnd_size = SIZE16; 3322 addr_size = SIZE16; 3323 } else if (cpu_mode == SIZE32) { 3324 opnd_size = SIZE32; 3325 addr_size = SIZE32; 3326 } else { 3327 opnd_size = SIZE32; 3328 addr_size = SIZE64; 3329 } 3330 3331 /* 3332 * Get one opcode byte and check for zero padding that follows 3333 * jump tables. 3334 */ 3335 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3336 goto error; 3337 3338 if (opcode1 == 0 && opcode2 == 0 && 3339 x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) { 3340 #ifdef DIS_TEXT 3341 (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN); 3342 #endif 3343 goto done; 3344 } 3345 3346 /* 3347 * Gather up legacy x86 prefix bytes. 3348 */ 3349 for (;;) { 3350 uint_t *which_prefix = NULL; 3351 3352 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 3353 3354 switch (dp->it_adrmode) { 3355 case PREFIX: 3356 which_prefix = &rep_prefix; 3357 break; 3358 case LOCK: 3359 which_prefix = &lock_prefix; 3360 break; 3361 case OVERRIDE: 3362 which_prefix = &segment_prefix; 3363 #ifdef DIS_TEXT 3364 x->d86_seg_prefix = (char *)dp->it_name; 3365 #endif 3366 if (dp->it_invalid64 && cpu_mode == SIZE64) 3367 goto error; 3368 break; 3369 case AM: 3370 which_prefix = &addr_size_prefix; 3371 break; 3372 case DM: 3373 which_prefix = &opnd_size_prefix; 3374 break; 3375 } 3376 if (which_prefix == NULL) 3377 break; 3378 *which_prefix = (opcode1 << 4) | opcode2; 3379 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3380 goto error; 3381 } 3382 3383 /* 3384 * Handle amd64 mode PREFIX values. 3385 * Some of the segment prefixes are no-ops. (only FS/GS actually work) 3386 * We might have a REX prefix (opcodes 0x40-0x4f) 3387 */ 3388 if (cpu_mode == SIZE64) { 3389 if (segment_prefix != 0x64 && segment_prefix != 0x65) 3390 segment_prefix = 0; 3391 3392 if (opcode1 == 0x4) { 3393 rex_prefix = (opcode1 << 4) | opcode2; 3394 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3395 goto error; 3396 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 3397 } else if (opcode1 == 0xC && 3398 (opcode2 == 0x4 || opcode2 == 0x5)) { 3399 /* AVX instructions */ 3400 vex_prefix = (opcode1 << 4) | opcode2; 3401 x->d86_rex_prefix = 0x40; 3402 } 3403 } else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) { 3404 /* LDS, LES or AVX */ 3405 dtrace_get_modrm(x, &mode, ®, &r_m); 3406 vex_prefetch = 1; 3407 3408 if (mode == REG_ONLY) { 3409 /* AVX */ 3410 vex_prefix = (opcode1 << 4) | opcode2; 3411 x->d86_rex_prefix = 0x40; 3412 opcode3 = (((mode << 3) | reg)>>1) & 0x0F; 3413 opcode4 = ((reg << 3) | r_m) & 0x0F; 3414 } 3415 } 3416 3417 /* 3418 * The EVEX prefix and "bound" instruction share the same first byte. 3419 * "bound" is only valid for 32-bit. For 64-bit this byte begins the 3420 * EVEX prefix and the 2nd byte must have bits 2 & 3 set to 0. 3421 */ 3422 if (opcode1 == 0x6 && opcode2 == 0x2) { 3423 /* 3424 * An EVEX prefix is 4 bytes long, get the next 3 bytes. 3425 */ 3426 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 3427 goto error; 3428 3429 if (addr_size == SIZE32 && (opcode4 & 0xf) == 0) { 3430 /* 3431 * Upper bits in 2nd byte == 0 is 'bound' instn. 3432 * 3433 * We've already read the byte so perform the 3434 * equivalent of dtrace_get_modrm on the byte and set 3435 * the flag to indicate we've already read it. 3436 */ 3437 char b = (opcode4 << 4) | opcode5; 3438 3439 r_m = b & 0x7; 3440 reg = (b >> 3) & 0x7; 3441 mode = (b >> 6) & 0x3; 3442 vex_prefetch = 1; 3443 goto not_avx512; 3444 } 3445 3446 /* check for correct bits being 0 in 2nd byte */ 3447 if ((opcode5 & 0xc) != 0) 3448 goto error; 3449 3450 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3451 goto error; 3452 /* check for correct bit being 1 in 3rd byte */ 3453 if ((opcode7 & 0x4) == 0) 3454 goto error; 3455 3456 if (dtrace_get_opcode(x, &opcode8, &opcode9) != 0) 3457 goto error; 3458 3459 /* Reuse opcode1 & opcode2 to get the real opcode now */ 3460 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3461 goto error; 3462 3463 /* 3464 * We only use the high nibble from the 2nd byte of the prefix 3465 * and save it in the low bits of evex_byte1. This is because 3466 * two of the bits in opcode5 are constant 0 (checked above), 3467 * and the other two bits are captured in vex_m. Also, the VEX 3468 * constants we check in evex_byte1 are against the low bits. 3469 */ 3470 evex_byte1 = opcode4; 3471 evex_byte2 = (opcode6 << 4) | opcode7; 3472 evex_byte3 = (opcode8 << 4) | opcode9; 3473 3474 vex_m = opcode5 & EVEX_m; 3475 vex_v = (((opcode6 << 4) | opcode7) & VEX_v) >> 3; 3476 vex_W = (opcode6 & VEX_W) >> 3; 3477 vex_p = opcode7 & VEX_p; 3478 3479 /* Currently only 3 valid values for evex L'L: 00, 01, 10 */ 3480 evex_L = (opcode8 & EVEX_L) >> 1; 3481 3482 dp = (instable_t *)&dis_opAVX62[(opcode1 << 4) | opcode2]; 3483 } 3484 not_avx512: 3485 3486 if (vex_prefix == VEX_2bytes) { 3487 if (!vex_prefetch) { 3488 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 3489 goto error; 3490 } 3491 vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3; 3492 vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2; 3493 vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3; 3494 vex_p = opcode4 & VEX_p; 3495 /* 3496 * The vex.x and vex.b bits are not defined in two bytes 3497 * mode vex prefix, their default values are 1 3498 */ 3499 vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B; 3500 3501 if (vex_R == 0) 3502 x->d86_rex_prefix |= REX_R; 3503 3504 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3505 goto error; 3506 3507 switch (vex_p) { 3508 case VEX_p_66: 3509 dp = (instable_t *) 3510 &dis_opAVX660F[(opcode1 << 4) | opcode2]; 3511 break; 3512 case VEX_p_F3: 3513 dp = (instable_t *) 3514 &dis_opAVXF30F[(opcode1 << 4) | opcode2]; 3515 break; 3516 case VEX_p_F2: 3517 dp = (instable_t *) 3518 &dis_opAVXF20F [(opcode1 << 4) | opcode2]; 3519 break; 3520 default: 3521 dp = (instable_t *) 3522 &dis_opAVX0F[opcode1][opcode2]; 3523 3524 } 3525 3526 } else if (vex_prefix == VEX_3bytes) { 3527 if (!vex_prefetch) { 3528 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 3529 goto error; 3530 } 3531 vex_R = (opcode3 & VEX_R) >> 3; 3532 vex_X = (opcode3 & VEX_X) >> 2; 3533 vex_B = (opcode3 & VEX_B) >> 1; 3534 vex_m = (((opcode3 << 4) | opcode4) & VEX_m); 3535 vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B); 3536 3537 if (vex_R == 0) 3538 x->d86_rex_prefix |= REX_R; 3539 if (vex_X == 0) 3540 x->d86_rex_prefix |= REX_X; 3541 if (vex_B == 0) 3542 x->d86_rex_prefix |= REX_B; 3543 3544 if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0) 3545 goto error; 3546 vex_W = (opcode5 & VEX_W) >> 3; 3547 vex_L = (opcode6 & VEX_L) >> 2; 3548 vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3; 3549 vex_p = opcode6 & VEX_p; 3550 3551 if (vex_W) 3552 x->d86_rex_prefix |= REX_W; 3553 3554 /* Only these three vex_m values valid; others are reserved */ 3555 if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) && 3556 (vex_m != VEX_m_0F3A)) 3557 goto error; 3558 3559 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3560 goto error; 3561 3562 switch (vex_p) { 3563 case VEX_p_66: 3564 if (vex_m == VEX_m_0F) { 3565 dp = (instable_t *) 3566 &dis_opAVX660F 3567 [(opcode1 << 4) | opcode2]; 3568 } else if (vex_m == VEX_m_0F38) { 3569 dp = (instable_t *) 3570 &dis_opAVX660F38 3571 [(opcode1 << 4) | opcode2]; 3572 } else if (vex_m == VEX_m_0F3A) { 3573 dp = (instable_t *) 3574 &dis_opAVX660F3A 3575 [(opcode1 << 4) | opcode2]; 3576 } else { 3577 goto error; 3578 } 3579 break; 3580 case VEX_p_F3: 3581 if (vex_m == VEX_m_0F) { 3582 dp = (instable_t *) 3583 &dis_opAVXF30F 3584 [(opcode1 << 4) | opcode2]; 3585 } else if (vex_m == VEX_m_0F38) { 3586 dp = (instable_t *) 3587 &dis_opAVXF30F38 3588 [(opcode1 << 4) | opcode2]; 3589 } else { 3590 goto error; 3591 } 3592 break; 3593 case VEX_p_F2: 3594 if (vex_m == VEX_m_0F) { 3595 dp = (instable_t *) 3596 &dis_opAVXF20F 3597 [(opcode1 << 4) | opcode2]; 3598 } else if (vex_m == VEX_m_0F3A) { 3599 dp = (instable_t *) 3600 &dis_opAVXF20F3A 3601 [(opcode1 << 4) | opcode2]; 3602 } else if (vex_m == VEX_m_0F38) { 3603 dp = (instable_t *) 3604 &dis_opAVXF20F38 3605 [(opcode1 << 4) | opcode2]; 3606 } else { 3607 goto error; 3608 } 3609 break; 3610 default: 3611 dp = (instable_t *) 3612 &dis_opAVX0F[opcode1][opcode2]; 3613 3614 } 3615 } 3616 if (vex_prefix) { 3617 if (dp->it_vexwoxmm) { 3618 wbit = LONG_OPND; 3619 } else if (dp->it_vexopmask) { 3620 wbit = KOPMASK_OPND; 3621 } else { 3622 if (vex_L) { 3623 wbit = YMM_OPND; 3624 } else { 3625 wbit = XMM_OPND; 3626 } 3627 } 3628 } 3629 3630 /* 3631 * Deal with selection of operand and address size now. 3632 * Note that the REX.W bit being set causes opnd_size_prefix to be 3633 * ignored. 3634 */ 3635 if (cpu_mode == SIZE64) { 3636 if ((rex_prefix & REX_W) || vex_W) 3637 opnd_size = SIZE64; 3638 else if (opnd_size_prefix) 3639 opnd_size = SIZE16; 3640 3641 if (addr_size_prefix) 3642 addr_size = SIZE32; 3643 } else if (cpu_mode == SIZE32) { 3644 if (opnd_size_prefix) 3645 opnd_size = SIZE16; 3646 if (addr_size_prefix) 3647 addr_size = SIZE16; 3648 } else { 3649 if (opnd_size_prefix) 3650 opnd_size = SIZE32; 3651 if (addr_size_prefix) 3652 addr_size = SIZE32; 3653 } 3654 /* 3655 * The pause instruction - a repz'd nop. This doesn't fit 3656 * with any of the other prefix goop added for SSE, so we'll 3657 * special-case it here. 3658 */ 3659 if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) { 3660 rep_prefix = 0; 3661 dp = (instable_t *)&dis_opPause; 3662 } 3663 3664 /* 3665 * Some 386 instructions have 2 bytes of opcode before the mod_r/m 3666 * byte so we may need to perform a table indirection. 3667 */ 3668 if (dp->it_indirect == (instable_t *)dis_op0F) { 3669 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 3670 goto error; 3671 opcode_bytes = 2; 3672 if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) { 3673 uint_t subcode; 3674 3675 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3676 goto error; 3677 opcode_bytes = 3; 3678 subcode = ((opcode6 & 0x3) << 1) | 3679 ((opcode7 & 0x8) >> 3); 3680 dp = (instable_t *)&dis_op0F7123[opcode5][subcode]; 3681 } else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) { 3682 dp = (instable_t *)&dis_op0FC8[0]; 3683 } else if ((opcode4 == 0x3) && (opcode5 == 0xA)) { 3684 opcode_bytes = 3; 3685 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3686 goto error; 3687 if (opnd_size == SIZE16) 3688 opnd_size = SIZE32; 3689 3690 dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7]; 3691 #ifdef DIS_TEXT 3692 if (strcmp(dp->it_name, "INVALID") == 0) 3693 goto error; 3694 #endif 3695 switch (dp->it_adrmode) { 3696 case XMMP: 3697 break; 3698 case XMMP_66r: 3699 case XMMPRM_66r: 3700 case XMM3PM_66r: 3701 if (opnd_size_prefix == 0) { 3702 goto error; 3703 } 3704 3705 break; 3706 case XMMP_66o: 3707 if (opnd_size_prefix == 0) { 3708 /* SSSE3 MMX instructions */ 3709 dp_mmx = *dp; 3710 dp = &dp_mmx; 3711 dp->it_adrmode = MMOPM_66o; 3712 #ifdef DIS_MEM 3713 dp->it_size = 8; 3714 #endif 3715 } 3716 break; 3717 default: 3718 goto error; 3719 } 3720 } else if ((opcode4 == 0x3) && (opcode5 == 0x8)) { 3721 opcode_bytes = 3; 3722 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3723 goto error; 3724 dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7]; 3725 3726 /* 3727 * Both crc32 and movbe have the same 3rd opcode 3728 * byte of either 0xF0 or 0xF1, so we use another 3729 * indirection to distinguish between the two. 3730 */ 3731 if (dp->it_indirect == (instable_t *)dis_op0F38F0 || 3732 dp->it_indirect == (instable_t *)dis_op0F38F1) { 3733 3734 dp = dp->it_indirect; 3735 if (rep_prefix != 0xF2) { 3736 /* It is movbe */ 3737 dp++; 3738 } 3739 } 3740 3741 /* 3742 * The adx family of instructions (adcx and adox) 3743 * continue the classic Intel tradition of abusing 3744 * arbitrary prefixes without actually meaning the 3745 * prefix bit. Therefore, if we find either the 3746 * opnd_size_prefix or rep_prefix we end up zeroing it 3747 * out after making our determination so as to ensure 3748 * that we don't get confused and accidentally print 3749 * repz prefixes and the like on these instructions. 3750 * 3751 * In addition, these instructions are actually much 3752 * closer to AVX instructions in semantics. Importantly, 3753 * they always default to having 32-bit operands. 3754 * However, if the CPU is in 64-bit mode, then and only 3755 * then, does it use REX.w promotes things to 64-bits 3756 * and REX.r allows 64-bit mode to use register r8-r15. 3757 */ 3758 if (dp->it_indirect == (instable_t *)dis_op0F38F6) { 3759 dp = dp->it_indirect; 3760 if (opnd_size_prefix == 0 && 3761 rep_prefix == 0xf3) { 3762 /* It is adox */ 3763 dp++; 3764 } else if (opnd_size_prefix != 0x66 && 3765 rep_prefix != 0) { 3766 /* It isn't adcx */ 3767 goto error; 3768 } 3769 opnd_size_prefix = 0; 3770 rep_prefix = 0; 3771 opnd_size = SIZE32; 3772 if (rex_prefix & REX_W) 3773 opnd_size = SIZE64; 3774 } 3775 3776 #ifdef DIS_TEXT 3777 if (strcmp(dp->it_name, "INVALID") == 0) 3778 goto error; 3779 #endif 3780 switch (dp->it_adrmode) { 3781 case ADX: 3782 case XMM: 3783 break; 3784 case RM_66r: 3785 case XMM_66r: 3786 case XMMM_66r: 3787 if (opnd_size_prefix == 0) { 3788 goto error; 3789 } 3790 break; 3791 case XMM_66o: 3792 if (opnd_size_prefix == 0) { 3793 /* SSSE3 MMX instructions */ 3794 dp_mmx = *dp; 3795 dp = &dp_mmx; 3796 dp->it_adrmode = MM; 3797 #ifdef DIS_MEM 3798 dp->it_size = 8; 3799 #endif 3800 } 3801 break; 3802 case CRC32: 3803 if (rep_prefix != 0xF2) { 3804 goto error; 3805 } 3806 rep_prefix = 0; 3807 break; 3808 case MOVBE: 3809 if (rep_prefix != 0x0) { 3810 goto error; 3811 } 3812 break; 3813 default: 3814 goto error; 3815 } 3816 } else { 3817 dp = (instable_t *)&dis_op0F[opcode4][opcode5]; 3818 } 3819 } 3820 3821 /* 3822 * If still not at a TERM decode entry, then a ModRM byte 3823 * exists and its fields further decode the instruction. 3824 */ 3825 x->d86_got_modrm = 0; 3826 if (dp->it_indirect != TERM) { 3827 dtrace_get_modrm(x, &mode, &opcode3, &r_m); 3828 if (x->d86_error) 3829 goto error; 3830 reg = opcode3; 3831 3832 /* 3833 * decode 287 instructions (D8-DF) from opcodeN 3834 */ 3835 if (opcode1 == 0xD && opcode2 >= 0x8) { 3836 if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4) 3837 dp = (instable_t *)&dis_opFP5[r_m]; 3838 else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4) 3839 dp = (instable_t *)&dis_opFP7[opcode3]; 3840 else if (opcode2 == 0xB && mode == 0x3) 3841 dp = (instable_t *)&dis_opFP6[opcode3]; 3842 else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4) 3843 dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m]; 3844 else if (mode == 0x3) 3845 dp = (instable_t *) 3846 &dis_opFP3[opcode2 - 8][opcode3]; 3847 else 3848 dp = (instable_t *) 3849 &dis_opFP1n2[opcode2 - 8][opcode3]; 3850 } else { 3851 dp = (instable_t *)dp->it_indirect + opcode3; 3852 } 3853 } 3854 3855 /* 3856 * In amd64 bit mode, ARPL opcode is changed to MOVSXD 3857 * (sign extend 32bit to 64 bit) 3858 */ 3859 if ((vex_prefix == 0) && cpu_mode == SIZE64 && 3860 opcode1 == 0x6 && opcode2 == 0x3) 3861 dp = (instable_t *)&dis_opMOVSLD; 3862 3863 /* 3864 * at this point we should have a correct (or invalid) opcode 3865 */ 3866 if (cpu_mode == SIZE64 && dp->it_invalid64 || 3867 cpu_mode != SIZE64 && dp->it_invalid32) 3868 goto error; 3869 if (dp->it_indirect != TERM) 3870 goto error; 3871 3872 /* 3873 * Deal with MMX/SSE opcodes which are changed by prefixes. Note, we do 3874 * need to include UNKNOWN below, as we may have instructions that 3875 * actually have a prefix, but don't exist in any other form. 3876 */ 3877 switch (dp->it_adrmode) { 3878 case UNKNOWN: 3879 case MMO: 3880 case MMOIMPL: 3881 case MMO3P: 3882 case MMOM3: 3883 case MMOMS: 3884 case MMOPM: 3885 case MMOPRM: 3886 case MMOS: 3887 case XMMO: 3888 case XMMOM: 3889 case XMMOMS: 3890 case XMMOPM: 3891 case XMMOS: 3892 case XMMOMX: 3893 case XMMOX3: 3894 case XMMOXMM: 3895 /* 3896 * This is horrible. Some SIMD instructions take the 3897 * form 0x0F 0x?? ..., which is easily decoded using the 3898 * existing tables. Other SIMD instructions use various 3899 * prefix bytes to overload existing instructions. For 3900 * Example, addps is F0, 58, whereas addss is F3 (repz), 3901 * F0, 58. Presumably someone got a raise for this. 3902 * 3903 * If we see one of the instructions which can be 3904 * modified in this way (if we've got one of the SIMDO* 3905 * address modes), we'll check to see if the last prefix 3906 * was a repz. If it was, we strip the prefix from the 3907 * mnemonic, and we indirect using the dis_opSIMDrepz 3908 * table. 3909 */ 3910 3911 /* 3912 * Calculate our offset in dis_op0F 3913 */ 3914 if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F)) 3915 goto error; 3916 3917 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 3918 sizeof (instable_t); 3919 3920 /* 3921 * Rewrite if this instruction used one of the magic prefixes. 3922 */ 3923 if (rep_prefix) { 3924 if (rep_prefix == 0xf2) 3925 dp = (instable_t *)&dis_opSIMDrepnz[off]; 3926 else 3927 dp = (instable_t *)&dis_opSIMDrepz[off]; 3928 rep_prefix = 0; 3929 } else if (opnd_size_prefix) { 3930 dp = (instable_t *)&dis_opSIMDdata16[off]; 3931 opnd_size_prefix = 0; 3932 if (opnd_size == SIZE16) 3933 opnd_size = SIZE32; 3934 } 3935 break; 3936 3937 case MG9: 3938 /* 3939 * More horribleness: the group 9 (0xF0 0xC7) instructions are 3940 * allowed an optional prefix of 0x66 or 0xF3. This is similar 3941 * to the SIMD business described above, but with a different 3942 * addressing mode (and an indirect table), so we deal with it 3943 * separately (if similarly). 3944 * 3945 * Intel further complicated this with the release of Ivy Bridge 3946 * where they overloaded these instructions based on the ModR/M 3947 * bytes. The VMX instructions have a mode of 0 since they are 3948 * memory instructions but rdrand instructions have a mode of 3949 * 0b11 (REG_ONLY) because they only operate on registers. While 3950 * there are different prefix formats, for now it is sufficient 3951 * to use a single different table. 3952 */ 3953 3954 /* 3955 * Calculate our offset in dis_op0FC7 (the group 9 table) 3956 */ 3957 if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7)) 3958 goto error; 3959 3960 off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) / 3961 sizeof (instable_t); 3962 3963 /* 3964 * If we have a mode of 0b11 then we have to rewrite this. 3965 */ 3966 dtrace_get_modrm(x, &mode, ®, &r_m); 3967 if (mode == REG_ONLY) { 3968 dp = (instable_t *)&dis_op0FC7m3[off]; 3969 break; 3970 } 3971 3972 /* 3973 * Rewrite if this instruction used one of the magic prefixes. 3974 */ 3975 if (rep_prefix) { 3976 if (rep_prefix == 0xf3) 3977 dp = (instable_t *)&dis_opF30FC7[off]; 3978 else 3979 goto error; 3980 rep_prefix = 0; 3981 } else if (opnd_size_prefix) { 3982 dp = (instable_t *)&dis_op660FC7[off]; 3983 opnd_size_prefix = 0; 3984 if (opnd_size == SIZE16) 3985 opnd_size = SIZE32; 3986 } else if (reg == 4 || reg == 5) { 3987 /* 3988 * We have xsavec (4) or xsaves (5), so rewrite. 3989 */ 3990 dp = (instable_t *)&dis_op0FC7[reg]; 3991 break; 3992 } 3993 break; 3994 3995 3996 case MMOSH: 3997 /* 3998 * As with the "normal" SIMD instructions, the MMX 3999 * shuffle instructions are overloaded. These 4000 * instructions, however, are special in that they use 4001 * an extra byte, and thus an extra table. As of this 4002 * writing, they only use the opnd_size prefix. 4003 */ 4004 4005 /* 4006 * Calculate our offset in dis_op0F7123 4007 */ 4008 if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 > 4009 sizeof (dis_op0F7123)) 4010 goto error; 4011 4012 if (opnd_size_prefix) { 4013 off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) / 4014 sizeof (instable_t); 4015 dp = (instable_t *)&dis_opSIMD7123[off]; 4016 opnd_size_prefix = 0; 4017 if (opnd_size == SIZE16) 4018 opnd_size = SIZE32; 4019 } 4020 break; 4021 case MRw: 4022 if (rep_prefix) { 4023 if (rep_prefix == 0xf3) { 4024 4025 /* 4026 * Calculate our offset in dis_op0F 4027 */ 4028 if ((uintptr_t)dp - (uintptr_t)dis_op0F > 4029 sizeof (dis_op0F)) 4030 goto error; 4031 4032 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 4033 sizeof (instable_t); 4034 4035 dp = (instable_t *)&dis_opSIMDrepz[off]; 4036 rep_prefix = 0; 4037 } else { 4038 goto error; 4039 } 4040 } 4041 break; 4042 case FSGS: 4043 if (rep_prefix == 0xf3) { 4044 if ((uintptr_t)dp - (uintptr_t)dis_op0FAE > 4045 sizeof (dis_op0FAE)) 4046 goto error; 4047 4048 off = ((uintptr_t)dp - (uintptr_t)dis_op0FAE) / 4049 sizeof (instable_t); 4050 dp = (instable_t *)&dis_opF30FAE[off]; 4051 rep_prefix = 0; 4052 } else if (rep_prefix != 0x00) { 4053 goto error; 4054 } 4055 } 4056 4057 /* 4058 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64. 4059 */ 4060 if (cpu_mode == SIZE64) 4061 if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop)) 4062 opnd_size = SIZE64; 4063 4064 #ifdef DIS_TEXT 4065 /* 4066 * At this point most instructions can format the opcode mnemonic 4067 * including the prefixes. 4068 */ 4069 if (lock_prefix) 4070 (void) strlcat(x->d86_mnem, "lock ", OPLEN); 4071 4072 if (rep_prefix == 0xf2) 4073 (void) strlcat(x->d86_mnem, "repnz ", OPLEN); 4074 else if (rep_prefix == 0xf3) 4075 (void) strlcat(x->d86_mnem, "repz ", OPLEN); 4076 4077 if (cpu_mode == SIZE64 && addr_size_prefix) 4078 (void) strlcat(x->d86_mnem, "addr32 ", OPLEN); 4079 4080 if (dp->it_adrmode != CBW && 4081 dp->it_adrmode != CWD && 4082 dp->it_adrmode != XMMSFNC) { 4083 if (strcmp(dp->it_name, "INVALID") == 0) 4084 goto error; 4085 (void) strlcat(x->d86_mnem, dp->it_name, OPLEN); 4086 if (dp->it_avxsuf == AVS2 && dp->it_suffix) { 4087 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d", 4088 OPLEN); 4089 } else if (dp->it_vexopmask && dp->it_suffix) { 4090 /* opmask instructions */ 4091 4092 if (opcode1 == 4 && opcode2 == 0xb) { 4093 /* It's a kunpck. */ 4094 if (vex_prefix == VEX_2bytes) { 4095 (void) strlcat(x->d86_mnem, 4096 vex_p == 0 ? "wd" : "bw", OPLEN); 4097 } else { 4098 /* vex_prefix == VEX_3bytes */ 4099 (void) strlcat(x->d86_mnem, 4100 "dq", OPLEN); 4101 } 4102 } else if (opcode1 == 3) { 4103 /* It's a kshift[l|r]. */ 4104 if (vex_W == 0) { 4105 (void) strlcat(x->d86_mnem, 4106 opcode2 == 2 || 4107 opcode2 == 0 ? 4108 "b" : "d", OPLEN); 4109 } else { 4110 /* W == 1 */ 4111 (void) strlcat(x->d86_mnem, 4112 opcode2 == 3 || opcode2 == 1 ? 4113 "q" : "w", OPLEN); 4114 } 4115 } else { 4116 /* if (vex_prefix == VEX_2bytes) { */ 4117 if ((cpu_mode == SIZE64 && opnd_size == 2) || 4118 vex_prefix == VEX_2bytes) { 4119 (void) strlcat(x->d86_mnem, 4120 vex_p == 0 ? "w" : 4121 vex_p == 1 ? "b" : "d", 4122 OPLEN); 4123 } else { 4124 /* vex_prefix == VEX_3bytes */ 4125 (void) strlcat(x->d86_mnem, 4126 vex_p == 1 ? "d" : "q", OPLEN); 4127 } 4128 } 4129 } else if (dp->it_suffix) { 4130 char *types[] = {"", "w", "l", "q"}; 4131 if (opcode_bytes == 2 && opcode4 == 4) { 4132 /* It's a cmovx.yy. Replace the suffix x */ 4133 for (i = 5; i < OPLEN; i++) { 4134 if (x->d86_mnem[i] == '.') 4135 break; 4136 } 4137 x->d86_mnem[i - 1] = *types[opnd_size]; 4138 } else if ((opnd_size == 2) && (opcode_bytes == 3) && 4139 ((opcode6 == 1 && opcode7 == 6) || 4140 (opcode6 == 2 && opcode7 == 2))) { 4141 /* 4142 * To handle PINSRD and PEXTRD 4143 */ 4144 (void) strlcat(x->d86_mnem, "d", OPLEN); 4145 } else if (dp != &dis_distable[0x6][0x2]) { 4146 /* bound instructions (0x62) have no suffix */ 4147 (void) strlcat(x->d86_mnem, types[opnd_size], 4148 OPLEN); 4149 } 4150 } 4151 } 4152 #endif 4153 4154 /* 4155 * Process operands based on the addressing modes. 4156 */ 4157 x->d86_mode = cpu_mode; 4158 /* 4159 * In vex mode the rex_prefix has no meaning 4160 */ 4161 if (!vex_prefix) 4162 x->d86_rex_prefix = rex_prefix; 4163 x->d86_opnd_size = opnd_size; 4164 x->d86_addr_size = addr_size; 4165 vbit = 0; /* initialize for mem/reg -> reg */ 4166 switch (dp->it_adrmode) { 4167 /* 4168 * amd64 instruction to sign extend 32 bit reg/mem operands 4169 * into 64 bit register values 4170 */ 4171 case MOVSXZ: 4172 #ifdef DIS_TEXT 4173 if (rex_prefix == 0) 4174 (void) strncpy(x->d86_mnem, "movzld", OPLEN); 4175 #endif 4176 dtrace_get_modrm(x, &mode, ®, &r_m); 4177 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4178 x->d86_opnd_size = SIZE64; 4179 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4180 x->d86_opnd_size = opnd_size = SIZE32; 4181 wbit = LONG_OPND; 4182 dtrace_get_operand(x, mode, r_m, wbit, 0); 4183 break; 4184 4185 /* 4186 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF) 4187 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7) 4188 * wbit lives in 2nd byte, note that operands 4189 * are different sized 4190 */ 4191 case MOVZ: 4192 if (rex_prefix & REX_W) { 4193 /* target register size = 64 bit */ 4194 x->d86_mnem[5] = 'q'; 4195 } 4196 dtrace_get_modrm(x, &mode, ®, &r_m); 4197 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4198 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4199 x->d86_opnd_size = opnd_size = SIZE16; 4200 wbit = WBIT(opcode5); 4201 dtrace_get_operand(x, mode, r_m, wbit, 0); 4202 break; 4203 case CRC32: 4204 opnd_size = SIZE32; 4205 if (rex_prefix & REX_W) 4206 opnd_size = SIZE64; 4207 x->d86_opnd_size = opnd_size; 4208 4209 dtrace_get_modrm(x, &mode, ®, &r_m); 4210 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4211 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4212 wbit = WBIT(opcode7); 4213 if (opnd_size_prefix) 4214 x->d86_opnd_size = opnd_size = SIZE16; 4215 dtrace_get_operand(x, mode, r_m, wbit, 0); 4216 break; 4217 case MOVBE: 4218 opnd_size = SIZE32; 4219 if (rex_prefix & REX_W) 4220 opnd_size = SIZE64; 4221 x->d86_opnd_size = opnd_size; 4222 4223 dtrace_get_modrm(x, &mode, ®, &r_m); 4224 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4225 wbit = WBIT(opcode7); 4226 if (opnd_size_prefix) 4227 x->d86_opnd_size = opnd_size = SIZE16; 4228 if (wbit) { 4229 /* reg -> mem */ 4230 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4231 dtrace_get_operand(x, mode, r_m, wbit, 1); 4232 } else { 4233 /* mem -> reg */ 4234 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4235 dtrace_get_operand(x, mode, r_m, wbit, 0); 4236 } 4237 break; 4238 4239 /* 4240 * imul instruction, with either 8-bit or longer immediate 4241 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s) 4242 */ 4243 case IMUL: 4244 wbit = LONG_OPND; 4245 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 4246 OPSIZE(opnd_size, opcode2 == 0x9), 1); 4247 break; 4248 4249 /* memory or register operand to register, with 'w' bit */ 4250 case MRw: 4251 case ADX: 4252 wbit = WBIT(opcode2); 4253 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4254 break; 4255 4256 /* register to memory or register operand, with 'w' bit */ 4257 /* arpl happens to fit here also because it is odd */ 4258 case RMw: 4259 if (opcode_bytes == 2) 4260 wbit = WBIT(opcode5); 4261 else 4262 wbit = WBIT(opcode2); 4263 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4264 break; 4265 4266 /* xaddb instruction */ 4267 case XADDB: 4268 wbit = 0; 4269 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4270 break; 4271 4272 /* MMX register to memory or register operand */ 4273 case MMS: 4274 case MMOS: 4275 #ifdef DIS_TEXT 4276 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4277 #else 4278 wbit = LONG_OPND; 4279 #endif 4280 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 4281 break; 4282 4283 /* MMX register to memory */ 4284 case MMOMS: 4285 dtrace_get_modrm(x, &mode, ®, &r_m); 4286 if (mode == REG_ONLY) 4287 goto error; 4288 wbit = MM_OPND; 4289 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 4290 break; 4291 4292 /* Double shift. Has immediate operand specifying the shift. */ 4293 case DSHIFT: 4294 wbit = LONG_OPND; 4295 dtrace_get_modrm(x, &mode, ®, &r_m); 4296 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4297 dtrace_get_operand(x, mode, r_m, wbit, 2); 4298 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4299 dtrace_imm_opnd(x, wbit, 1, 0); 4300 break; 4301 4302 /* 4303 * Double shift. With no immediate operand, specifies using %cl. 4304 */ 4305 case DSHIFTcl: 4306 wbit = LONG_OPND; 4307 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4308 break; 4309 4310 /* immediate to memory or register operand */ 4311 case IMlw: 4312 wbit = WBIT(opcode2); 4313 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4314 dtrace_get_operand(x, mode, r_m, wbit, 1); 4315 /* 4316 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83 4317 */ 4318 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0); 4319 break; 4320 4321 /* immediate to memory or register operand with the */ 4322 /* 'w' bit present */ 4323 case IMw: 4324 wbit = WBIT(opcode2); 4325 dtrace_get_modrm(x, &mode, ®, &r_m); 4326 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4327 dtrace_get_operand(x, mode, r_m, wbit, 1); 4328 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 4329 break; 4330 4331 /* immediate to register with register in low 3 bits */ 4332 /* of op code */ 4333 case IR: 4334 /* w-bit here (with regs) is bit 3 */ 4335 wbit = opcode2 >>3 & 0x1; 4336 reg = REGNO(opcode2); 4337 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4338 mode = REG_ONLY; 4339 r_m = reg; 4340 dtrace_get_operand(x, mode, r_m, wbit, 1); 4341 dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0); 4342 break; 4343 4344 /* MMX immediate shift of register */ 4345 case MMSH: 4346 case MMOSH: 4347 wbit = MM_OPND; 4348 goto mm_shift; /* in next case */ 4349 4350 /* SIMD immediate shift of register */ 4351 case XMMSH: 4352 wbit = XMM_OPND; 4353 mm_shift: 4354 reg = REGNO(opcode7); 4355 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4356 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4357 dtrace_imm_opnd(x, wbit, 1, 0); 4358 NOMEM; 4359 break; 4360 4361 /* accumulator to memory operand */ 4362 case AO: 4363 vbit = 1; 4364 /*FALLTHROUGH*/ 4365 4366 /* memory operand to accumulator */ 4367 case OA: 4368 wbit = WBIT(opcode2); 4369 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit); 4370 dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit); 4371 #ifdef DIS_TEXT 4372 x->d86_opnd[vbit].d86_mode = MODE_OFFSET; 4373 #endif 4374 break; 4375 4376 4377 /* segment register to memory or register operand */ 4378 case SM: 4379 vbit = 1; 4380 /*FALLTHROUGH*/ 4381 4382 /* memory or register operand to segment register */ 4383 case MS: 4384 dtrace_get_modrm(x, &mode, ®, &r_m); 4385 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4386 dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit); 4387 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit); 4388 break; 4389 4390 /* 4391 * rotate or shift instructions, which may shift by 1 or 4392 * consult the cl register, depending on the 'v' bit 4393 */ 4394 case Mv: 4395 vbit = VBIT(opcode2); 4396 wbit = WBIT(opcode2); 4397 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4398 dtrace_get_operand(x, mode, r_m, wbit, 1); 4399 #ifdef DIS_TEXT 4400 if (vbit) { 4401 (void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN); 4402 } else { 4403 x->d86_opnd[0].d86_mode = MODE_SIGNED; 4404 x->d86_opnd[0].d86_value_size = 1; 4405 x->d86_opnd[0].d86_value = 1; 4406 } 4407 #endif 4408 break; 4409 /* 4410 * immediate rotate or shift instructions 4411 */ 4412 case MvI: 4413 wbit = WBIT(opcode2); 4414 normal_imm_mem: 4415 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4416 dtrace_get_operand(x, mode, r_m, wbit, 1); 4417 dtrace_imm_opnd(x, wbit, 1, 0); 4418 break; 4419 4420 /* bit test instructions */ 4421 case MIb: 4422 wbit = LONG_OPND; 4423 goto normal_imm_mem; 4424 4425 /* single memory or register operand with 'w' bit present */ 4426 case Mw: 4427 wbit = WBIT(opcode2); 4428 just_mem: 4429 dtrace_get_modrm(x, &mode, ®, &r_m); 4430 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4431 dtrace_get_operand(x, mode, r_m, wbit, 0); 4432 break; 4433 4434 case SWAPGS_RDTSCP: 4435 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) { 4436 #ifdef DIS_TEXT 4437 (void) strncpy(x->d86_mnem, "swapgs", OPLEN); 4438 #endif 4439 NOMEM; 4440 break; 4441 } else if (mode == 3 && r_m == 1) { 4442 #ifdef DIS_TEXT 4443 (void) strncpy(x->d86_mnem, "rdtscp", OPLEN); 4444 #endif 4445 NOMEM; 4446 break; 4447 } else if (mode == 3 && r_m == 2) { 4448 #ifdef DIS_TEXT 4449 (void) strncpy(x->d86_mnem, "monitorx", OPLEN); 4450 #endif 4451 NOMEM; 4452 break; 4453 } else if (mode == 3 && r_m == 3) { 4454 #ifdef DIS_TEXT 4455 (void) strncpy(x->d86_mnem, "mwaitx", OPLEN); 4456 #endif 4457 NOMEM; 4458 break; 4459 } else if (mode == 3 && r_m == 4) { 4460 #ifdef DIS_TEXT 4461 (void) strncpy(x->d86_mnem, "clzero", OPLEN); 4462 #endif 4463 NOMEM; 4464 break; 4465 } 4466 4467 /*FALLTHROUGH*/ 4468 4469 /* prefetch instruction - memory operand, but no memory acess */ 4470 case PREF: 4471 NOMEM; 4472 /*FALLTHROUGH*/ 4473 4474 /* single memory or register operand */ 4475 case M: 4476 case MG9: 4477 wbit = LONG_OPND; 4478 goto just_mem; 4479 4480 /* single memory or register byte operand */ 4481 case Mb: 4482 wbit = BYTE_OPND; 4483 goto just_mem; 4484 4485 case VMx: 4486 if (mode == 3) { 4487 #ifdef DIS_TEXT 4488 char *vminstr; 4489 4490 switch (r_m) { 4491 case 1: 4492 vminstr = "vmcall"; 4493 break; 4494 case 2: 4495 vminstr = "vmlaunch"; 4496 break; 4497 case 3: 4498 vminstr = "vmresume"; 4499 break; 4500 case 4: 4501 vminstr = "vmxoff"; 4502 break; 4503 default: 4504 goto error; 4505 } 4506 4507 (void) strncpy(x->d86_mnem, vminstr, OPLEN); 4508 #else 4509 if (r_m < 1 || r_m > 4) 4510 goto error; 4511 #endif 4512 4513 NOMEM; 4514 break; 4515 } 4516 /*FALLTHROUGH*/ 4517 case SVM: 4518 if (mode == 3) { 4519 #if DIS_TEXT 4520 char *vinstr; 4521 4522 switch (r_m) { 4523 case 0: 4524 vinstr = "vmrun"; 4525 break; 4526 case 1: 4527 vinstr = "vmmcall"; 4528 break; 4529 case 2: 4530 vinstr = "vmload"; 4531 break; 4532 case 3: 4533 vinstr = "vmsave"; 4534 break; 4535 case 4: 4536 vinstr = "stgi"; 4537 break; 4538 case 5: 4539 vinstr = "clgi"; 4540 break; 4541 case 6: 4542 vinstr = "skinit"; 4543 break; 4544 case 7: 4545 vinstr = "invlpga"; 4546 break; 4547 } 4548 4549 (void) strncpy(x->d86_mnem, vinstr, OPLEN); 4550 #endif 4551 NOMEM; 4552 break; 4553 } 4554 /*FALLTHROUGH*/ 4555 case MONITOR_MWAIT: 4556 if (mode == 3) { 4557 if (r_m == 0) { 4558 #ifdef DIS_TEXT 4559 (void) strncpy(x->d86_mnem, "monitor", OPLEN); 4560 #endif 4561 NOMEM; 4562 break; 4563 } else if (r_m == 1) { 4564 #ifdef DIS_TEXT 4565 (void) strncpy(x->d86_mnem, "mwait", OPLEN); 4566 #endif 4567 NOMEM; 4568 break; 4569 } else if (r_m == 2) { 4570 #ifdef DIS_TEXT 4571 (void) strncpy(x->d86_mnem, "clac", OPLEN); 4572 #endif 4573 NOMEM; 4574 break; 4575 } else if (r_m == 3) { 4576 #ifdef DIS_TEXT 4577 (void) strncpy(x->d86_mnem, "stac", OPLEN); 4578 #endif 4579 NOMEM; 4580 break; 4581 } else { 4582 goto error; 4583 } 4584 } 4585 /*FALLTHROUGH*/ 4586 case XGETBV_XSETBV: 4587 if (mode == 3) { 4588 if (r_m == 0) { 4589 #ifdef DIS_TEXT 4590 (void) strncpy(x->d86_mnem, "xgetbv", OPLEN); 4591 #endif 4592 NOMEM; 4593 break; 4594 } else if (r_m == 1) { 4595 #ifdef DIS_TEXT 4596 (void) strncpy(x->d86_mnem, "xsetbv", OPLEN); 4597 #endif 4598 NOMEM; 4599 break; 4600 } else { 4601 goto error; 4602 } 4603 4604 } 4605 /*FALLTHROUGH*/ 4606 case MO: 4607 /* Similar to M, but only memory (no direct registers) */ 4608 wbit = LONG_OPND; 4609 dtrace_get_modrm(x, &mode, ®, &r_m); 4610 if (mode == 3) 4611 goto error; 4612 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4613 dtrace_get_operand(x, mode, r_m, wbit, 0); 4614 break; 4615 4616 /* move special register to register or reverse if vbit */ 4617 case SREG: 4618 switch (opcode5) { 4619 4620 case 2: 4621 vbit = 1; 4622 /*FALLTHROUGH*/ 4623 case 0: 4624 wbit = CONTROL_OPND; 4625 break; 4626 4627 case 3: 4628 vbit = 1; 4629 /*FALLTHROUGH*/ 4630 case 1: 4631 wbit = DEBUG_OPND; 4632 break; 4633 4634 case 6: 4635 vbit = 1; 4636 /*FALLTHROUGH*/ 4637 case 4: 4638 wbit = TEST_OPND; 4639 break; 4640 4641 } 4642 dtrace_get_modrm(x, &mode, ®, &r_m); 4643 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4644 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit); 4645 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit); 4646 NOMEM; 4647 break; 4648 4649 /* 4650 * single register operand with register in the low 3 4651 * bits of op code 4652 */ 4653 case R: 4654 if (opcode_bytes == 2) 4655 reg = REGNO(opcode5); 4656 else 4657 reg = REGNO(opcode2); 4658 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4659 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4660 NOMEM; 4661 break; 4662 4663 /* 4664 * register to accumulator with register in the low 3 4665 * bits of op code, xchg instructions 4666 */ 4667 case RA: 4668 NOMEM; 4669 reg = REGNO(opcode2); 4670 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4671 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4672 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1); 4673 break; 4674 4675 /* 4676 * single segment register operand, with register in 4677 * bits 3-4 of op code byte 4678 */ 4679 case SEG: 4680 NOMEM; 4681 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3; 4682 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 4683 break; 4684 4685 /* 4686 * single segment register operand, with register in 4687 * bits 3-5 of op code 4688 */ 4689 case LSEG: 4690 NOMEM; 4691 /* long seg reg from opcode */ 4692 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7; 4693 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 4694 break; 4695 4696 /* memory or register operand to register */ 4697 case MR: 4698 if (vex_prefetch) 4699 x->d86_got_modrm = 1; 4700 wbit = LONG_OPND; 4701 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4702 break; 4703 4704 case RM: 4705 case RM_66r: 4706 if (vex_prefetch) 4707 x->d86_got_modrm = 1; 4708 wbit = LONG_OPND; 4709 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4710 break; 4711 4712 /* MMX/SIMD-Int memory or mm reg to mm reg */ 4713 case MM: 4714 case MMO: 4715 #ifdef DIS_TEXT 4716 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4717 #else 4718 wbit = LONG_OPND; 4719 #endif 4720 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 4721 break; 4722 4723 case MMOIMPL: 4724 #ifdef DIS_TEXT 4725 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4726 #else 4727 wbit = LONG_OPND; 4728 #endif 4729 dtrace_get_modrm(x, &mode, ®, &r_m); 4730 if (mode != REG_ONLY) 4731 goto error; 4732 4733 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4734 dtrace_get_operand(x, mode, r_m, wbit, 0); 4735 dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1); 4736 mode = 0; /* change for memory access size... */ 4737 break; 4738 4739 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */ 4740 case MMO3P: 4741 wbit = MM_OPND; 4742 goto xmm3p; 4743 case XMM3P: 4744 wbit = XMM_OPND; 4745 xmm3p: 4746 dtrace_get_modrm(x, &mode, ®, &r_m); 4747 if (mode != REG_ONLY) 4748 goto error; 4749 4750 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1, 4751 1); 4752 NOMEM; 4753 break; 4754 4755 case XMM3PM_66r: 4756 THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND, 4757 1, 0); 4758 break; 4759 4760 /* MMX/SIMD-Int predicated r32/mem to mm reg */ 4761 case MMOPRM: 4762 wbit = LONG_OPND; 4763 w2 = MM_OPND; 4764 goto xmmprm; 4765 case XMMPRM: 4766 case XMMPRM_66r: 4767 wbit = LONG_OPND; 4768 w2 = XMM_OPND; 4769 xmmprm: 4770 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1); 4771 break; 4772 4773 /* MMX/SIMD-Int predicated mm/mem to mm reg */ 4774 case MMOPM: 4775 case MMOPM_66o: 4776 wbit = w2 = MM_OPND; 4777 goto xmmprm; 4778 4779 /* MMX/SIMD-Int mm reg to r32 */ 4780 case MMOM3: 4781 NOMEM; 4782 dtrace_get_modrm(x, &mode, ®, &r_m); 4783 if (mode != REG_ONLY) 4784 goto error; 4785 wbit = MM_OPND; 4786 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 4787 break; 4788 4789 /* SIMD memory or xmm reg operand to xmm reg */ 4790 case XMM: 4791 case XMM_66o: 4792 case XMM_66r: 4793 case XMMO: 4794 case XMMXIMPL: 4795 wbit = XMM_OPND; 4796 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4797 4798 if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY) 4799 goto error; 4800 4801 #ifdef DIS_TEXT 4802 /* 4803 * movlps and movhlps share opcodes. They differ in the 4804 * addressing modes allowed for their operands. 4805 * movhps and movlhps behave similarly. 4806 */ 4807 if (mode == REG_ONLY) { 4808 if (strcmp(dp->it_name, "movlps") == 0) 4809 (void) strncpy(x->d86_mnem, "movhlps", OPLEN); 4810 else if (strcmp(dp->it_name, "movhps") == 0) 4811 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 4812 } 4813 #endif 4814 if (dp->it_adrmode == XMMXIMPL) 4815 mode = 0; /* change for memory access size... */ 4816 break; 4817 4818 /* SIMD xmm reg to memory or xmm reg */ 4819 case XMMS: 4820 case XMMOS: 4821 case XMMMS: 4822 case XMMOMS: 4823 dtrace_get_modrm(x, &mode, ®, &r_m); 4824 #ifdef DIS_TEXT 4825 if ((strcmp(dp->it_name, "movlps") == 0 || 4826 strcmp(dp->it_name, "movhps") == 0 || 4827 strcmp(dp->it_name, "movntps") == 0) && 4828 mode == REG_ONLY) 4829 goto error; 4830 #endif 4831 wbit = XMM_OPND; 4832 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 4833 break; 4834 4835 /* SIMD memory to xmm reg */ 4836 case XMMM: 4837 case XMMM_66r: 4838 case XMMOM: 4839 wbit = XMM_OPND; 4840 dtrace_get_modrm(x, &mode, ®, &r_m); 4841 #ifdef DIS_TEXT 4842 if (mode == REG_ONLY) { 4843 if (strcmp(dp->it_name, "movhps") == 0) 4844 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 4845 else 4846 goto error; 4847 } 4848 #endif 4849 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 4850 break; 4851 4852 /* SIMD memory or r32 to xmm reg */ 4853 case XMM3MX: 4854 wbit = LONG_OPND; 4855 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 4856 break; 4857 4858 case XMM3MXS: 4859 wbit = LONG_OPND; 4860 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 4861 break; 4862 4863 /* SIMD memory or mm reg to xmm reg */ 4864 case XMMOMX: 4865 /* SIMD mm to xmm */ 4866 case XMMMX: 4867 wbit = MM_OPND; 4868 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 4869 break; 4870 4871 /* SIMD memory or xmm reg to mm reg */ 4872 case XMMXMM: 4873 case XMMOXMM: 4874 case XMMXM: 4875 wbit = XMM_OPND; 4876 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 4877 break; 4878 4879 4880 /* SIMD memory or xmm reg to r32 */ 4881 case XMMXM3: 4882 wbit = XMM_OPND; 4883 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 4884 break; 4885 4886 /* SIMD xmm to r32 */ 4887 case XMMX3: 4888 case XMMOX3: 4889 dtrace_get_modrm(x, &mode, ®, &r_m); 4890 if (mode != REG_ONLY) 4891 goto error; 4892 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4893 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 4894 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4895 NOMEM; 4896 break; 4897 4898 /* SIMD predicated memory or xmm reg with/to xmm reg */ 4899 case XMMP: 4900 case XMMP_66r: 4901 case XMMP_66o: 4902 case XMMOPM: 4903 wbit = XMM_OPND; 4904 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1, 4905 1); 4906 4907 #ifdef DIS_TEXT 4908 /* 4909 * cmpps and cmpss vary their instruction name based 4910 * on the value of imm8. Other XMMP instructions, 4911 * such as shufps, require explicit specification of 4912 * the predicate. 4913 */ 4914 if (dp->it_name[0] == 'c' && 4915 dp->it_name[1] == 'm' && 4916 dp->it_name[2] == 'p' && 4917 strlen(dp->it_name) == 5) { 4918 uchar_t pred = x->d86_opnd[0].d86_value & 0xff; 4919 4920 if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *))) 4921 goto error; 4922 4923 (void) strncpy(x->d86_mnem, "cmp", OPLEN); 4924 (void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred], 4925 OPLEN); 4926 (void) strlcat(x->d86_mnem, 4927 dp->it_name + strlen(dp->it_name) - 2, 4928 OPLEN); 4929 x->d86_opnd[0] = x->d86_opnd[1]; 4930 x->d86_opnd[1] = x->d86_opnd[2]; 4931 x->d86_numopnds = 2; 4932 } 4933 4934 /* 4935 * The pclmulqdq instruction has a series of alternate names for 4936 * various encodings of the immediate byte. As such, if we 4937 * happen to find it and the immediate value matches, we'll 4938 * rewrite the mnemonic. 4939 */ 4940 if (strcmp(dp->it_name, "pclmulqdq") == 0) { 4941 boolean_t changed = B_TRUE; 4942 switch (x->d86_opnd[0].d86_value) { 4943 case 0x00: 4944 (void) strncpy(x->d86_mnem, "pclmullqlqdq", 4945 OPLEN); 4946 break; 4947 case 0x01: 4948 (void) strncpy(x->d86_mnem, "pclmulhqlqdq", 4949 OPLEN); 4950 break; 4951 case 0x10: 4952 (void) strncpy(x->d86_mnem, "pclmullqhqdq", 4953 OPLEN); 4954 break; 4955 case 0x11: 4956 (void) strncpy(x->d86_mnem, "pclmulhqhqdq", 4957 OPLEN); 4958 break; 4959 default: 4960 changed = B_FALSE; 4961 break; 4962 } 4963 4964 if (changed == B_TRUE) { 4965 x->d86_opnd[0].d86_value_size = 0; 4966 x->d86_opnd[0] = x->d86_opnd[1]; 4967 x->d86_opnd[1] = x->d86_opnd[2]; 4968 x->d86_numopnds = 2; 4969 } 4970 } 4971 #endif 4972 break; 4973 4974 case XMMX2I: 4975 FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND, 4976 1); 4977 NOMEM; 4978 break; 4979 4980 case XMM2I: 4981 ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1); 4982 NOMEM; 4983 break; 4984 4985 /* immediate operand to accumulator */ 4986 case IA: 4987 wbit = WBIT(opcode2); 4988 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 4989 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 4990 NOMEM; 4991 break; 4992 4993 /* memory or register operand to accumulator */ 4994 case MA: 4995 wbit = WBIT(opcode2); 4996 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4997 dtrace_get_operand(x, mode, r_m, wbit, 0); 4998 break; 4999 5000 /* si register to di register used to reference memory */ 5001 case SD: 5002 #ifdef DIS_TEXT 5003 dtrace_check_override(x, 0); 5004 x->d86_numopnds = 2; 5005 if (addr_size == SIZE64) { 5006 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 5007 OPLEN); 5008 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 5009 OPLEN); 5010 } else if (addr_size == SIZE32) { 5011 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 5012 OPLEN); 5013 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 5014 OPLEN); 5015 } else { 5016 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 5017 OPLEN); 5018 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 5019 OPLEN); 5020 } 5021 #endif 5022 wbit = LONG_OPND; 5023 break; 5024 5025 /* accumulator to di register */ 5026 case AD: 5027 wbit = WBIT(opcode2); 5028 #ifdef DIS_TEXT 5029 dtrace_check_override(x, 1); 5030 x->d86_numopnds = 2; 5031 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0); 5032 if (addr_size == SIZE64) 5033 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 5034 OPLEN); 5035 else if (addr_size == SIZE32) 5036 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 5037 OPLEN); 5038 else 5039 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 5040 OPLEN); 5041 #endif 5042 break; 5043 5044 /* si register to accumulator */ 5045 case SA: 5046 wbit = WBIT(opcode2); 5047 #ifdef DIS_TEXT 5048 dtrace_check_override(x, 0); 5049 x->d86_numopnds = 2; 5050 if (addr_size == SIZE64) 5051 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 5052 OPLEN); 5053 else if (addr_size == SIZE32) 5054 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 5055 OPLEN); 5056 else 5057 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 5058 OPLEN); 5059 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 5060 #endif 5061 break; 5062 5063 /* 5064 * single operand, a 16/32 bit displacement 5065 */ 5066 case D: 5067 wbit = LONG_OPND; 5068 dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 5069 NOMEM; 5070 break; 5071 5072 /* jmp/call indirect to memory or register operand */ 5073 case INM: 5074 #ifdef DIS_TEXT 5075 (void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN); 5076 #endif 5077 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5078 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5079 wbit = LONG_OPND; 5080 break; 5081 5082 /* 5083 * for long jumps and long calls -- a new code segment 5084 * register and an offset in IP -- stored in object 5085 * code in reverse order. Note - not valid in amd64 5086 */ 5087 case SO: 5088 dtrace_check_override(x, 1); 5089 wbit = LONG_OPND; 5090 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1); 5091 #ifdef DIS_TEXT 5092 x->d86_opnd[1].d86_mode = MODE_SIGNED; 5093 #endif 5094 /* will now get segment operand */ 5095 dtrace_imm_opnd(x, wbit, 2, 0); 5096 break; 5097 5098 /* 5099 * jmp/call. single operand, 8 bit displacement. 5100 * added to current EIP in 'compofff' 5101 */ 5102 case BD: 5103 dtrace_disp_opnd(x, BYTE_OPND, 1, 0); 5104 NOMEM; 5105 break; 5106 5107 /* single 32/16 bit immediate operand */ 5108 case I: 5109 wbit = LONG_OPND; 5110 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 5111 break; 5112 5113 /* single 8 bit immediate operand */ 5114 case Ib: 5115 wbit = LONG_OPND; 5116 dtrace_imm_opnd(x, wbit, 1, 0); 5117 break; 5118 5119 case ENTER: 5120 wbit = LONG_OPND; 5121 dtrace_imm_opnd(x, wbit, 2, 0); 5122 dtrace_imm_opnd(x, wbit, 1, 1); 5123 switch (opnd_size) { 5124 case SIZE64: 5125 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8; 5126 break; 5127 case SIZE32: 5128 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4; 5129 break; 5130 case SIZE16: 5131 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2; 5132 break; 5133 } 5134 5135 break; 5136 5137 /* 16-bit immediate operand */ 5138 case RET: 5139 wbit = LONG_OPND; 5140 dtrace_imm_opnd(x, wbit, 2, 0); 5141 break; 5142 5143 /* single 8 bit port operand */ 5144 case P: 5145 dtrace_check_override(x, 0); 5146 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 5147 NOMEM; 5148 break; 5149 5150 /* single operand, dx register (variable port instruction) */ 5151 case V: 5152 x->d86_numopnds = 1; 5153 dtrace_check_override(x, 0); 5154 #ifdef DIS_TEXT 5155 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN); 5156 #endif 5157 NOMEM; 5158 break; 5159 5160 /* 5161 * The int instruction, which has two forms: 5162 * int 3 (breakpoint) or 5163 * int n, where n is indicated in the subsequent 5164 * byte (format Ib). The int 3 instruction (opcode 0xCC), 5165 * where, although the 3 looks like an operand, 5166 * it is implied by the opcode. It must be converted 5167 * to the correct base and output. 5168 */ 5169 case INT3: 5170 #ifdef DIS_TEXT 5171 x->d86_numopnds = 1; 5172 x->d86_opnd[0].d86_mode = MODE_SIGNED; 5173 x->d86_opnd[0].d86_value_size = 1; 5174 x->d86_opnd[0].d86_value = 3; 5175 #endif 5176 NOMEM; 5177 break; 5178 5179 /* single 8 bit immediate operand */ 5180 case INTx: 5181 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 5182 NOMEM; 5183 break; 5184 5185 /* an unused byte must be discarded */ 5186 case U: 5187 if (x->d86_get_byte(x->d86_data) < 0) 5188 goto error; 5189 x->d86_len++; 5190 NOMEM; 5191 break; 5192 5193 case CBW: 5194 #ifdef DIS_TEXT 5195 if (opnd_size == SIZE16) 5196 (void) strlcat(x->d86_mnem, "cbtw", OPLEN); 5197 else if (opnd_size == SIZE32) 5198 (void) strlcat(x->d86_mnem, "cwtl", OPLEN); 5199 else 5200 (void) strlcat(x->d86_mnem, "cltq", OPLEN); 5201 #endif 5202 wbit = LONG_OPND; 5203 NOMEM; 5204 break; 5205 5206 case CWD: 5207 #ifdef DIS_TEXT 5208 if (opnd_size == SIZE16) 5209 (void) strlcat(x->d86_mnem, "cwtd", OPLEN); 5210 else if (opnd_size == SIZE32) 5211 (void) strlcat(x->d86_mnem, "cltd", OPLEN); 5212 else 5213 (void) strlcat(x->d86_mnem, "cqtd", OPLEN); 5214 #endif 5215 wbit = LONG_OPND; 5216 NOMEM; 5217 break; 5218 5219 case XMMSFNC: 5220 /* 5221 * sfence is sfence if mode is REG_ONLY. If mode isn't 5222 * REG_ONLY, mnemonic should be 'clflush'. 5223 */ 5224 dtrace_get_modrm(x, &mode, ®, &r_m); 5225 5226 /* sfence doesn't take operands */ 5227 if (mode != REG_ONLY) { 5228 if (opnd_size_prefix == 0x66) { 5229 #ifdef DIS_TEXT 5230 (void) strlcat(x->d86_mnem, "clflushopt", 5231 OPLEN); 5232 #endif 5233 } else if (opnd_size_prefix == 0) { 5234 #ifdef DIS_TEXT 5235 (void) strlcat(x->d86_mnem, "clflush", OPLEN); 5236 #endif 5237 } else { 5238 /* Unknown instruction */ 5239 goto error; 5240 } 5241 5242 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5243 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 5244 NOMEM; 5245 #ifdef DIS_TEXT 5246 } else { 5247 (void) strlcat(x->d86_mnem, "sfence", OPLEN); 5248 #endif 5249 } 5250 break; 5251 5252 case FSGS: 5253 /* 5254 * The FSGSBASE instructions are taken only when the mode is set 5255 * to registers. They share opcodes with instructions like 5256 * fxrstor, stmxcsr, etc. We handle the repz prefix earlier. 5257 */ 5258 wbit = WBIT(opcode2); 5259 dtrace_get_modrm(x, &mode, ®, &r_m); 5260 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5261 dtrace_get_operand(x, mode, r_m, wbit, 0); 5262 if (mode == REG_ONLY) { 5263 NOMEM; 5264 } 5265 break; 5266 5267 /* 5268 * no disassembly, the mnemonic was all there was so go on 5269 */ 5270 case NORM: 5271 if (dp->it_invalid32 && cpu_mode != SIZE64) 5272 goto error; 5273 NOMEM; 5274 /*FALLTHROUGH*/ 5275 case IMPLMEM: 5276 break; 5277 5278 case XMMFENCE: 5279 /* 5280 * XRSTOR, XSAVEOPT and LFENCE share the same opcode but 5281 * differ in mode and reg. 5282 */ 5283 dtrace_get_modrm(x, &mode, ®, &r_m); 5284 5285 if (mode == REG_ONLY) { 5286 /* 5287 * Only the following exact byte sequences are allowed: 5288 * 5289 * 0f ae e8 lfence 5290 * 0f ae f0 mfence 5291 */ 5292 if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 && 5293 (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0) 5294 goto error; 5295 } else { 5296 #ifdef DIS_TEXT 5297 if (reg == 5) { 5298 (void) strncpy(x->d86_mnem, "xrstor", OPLEN); 5299 } else if (reg == 6) { 5300 if (opnd_size_prefix == 0x66) { 5301 (void) strncpy(x->d86_mnem, "clwb", 5302 OPLEN); 5303 } else if (opnd_size_prefix == 0x00) { 5304 (void) strncpy(x->d86_mnem, "xsaveopt", 5305 OPLEN); 5306 } else { 5307 goto error; 5308 } 5309 } else { 5310 goto error; 5311 } 5312 #endif 5313 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5314 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 5315 } 5316 break; 5317 5318 /* float reg */ 5319 case F: 5320 #ifdef DIS_TEXT 5321 x->d86_numopnds = 1; 5322 (void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN); 5323 x->d86_opnd[0].d86_opnd[4] = r_m + '0'; 5324 #endif 5325 NOMEM; 5326 break; 5327 5328 /* float reg to float reg, with ret bit present */ 5329 case FF: 5330 vbit = opcode2 >> 2 & 0x1; /* vbit = 1: st -> st(i) */ 5331 /*FALLTHROUGH*/ 5332 case FFC: /* case for vbit always = 0 */ 5333 #ifdef DIS_TEXT 5334 x->d86_numopnds = 2; 5335 (void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN); 5336 (void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN); 5337 x->d86_opnd[vbit].d86_opnd[4] = r_m + '0'; 5338 #endif 5339 NOMEM; 5340 break; 5341 5342 /* AVX instructions */ 5343 case VEX_MO: 5344 /* op(ModR/M.r/m) */ 5345 x->d86_numopnds = 1; 5346 dtrace_get_modrm(x, &mode, ®, &r_m); 5347 #ifdef DIS_TEXT 5348 if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3)) 5349 (void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN); 5350 #endif 5351 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5352 dtrace_get_operand(x, mode, r_m, wbit, 0); 5353 break; 5354 case VEX_RMrX: 5355 case FMA: 5356 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */ 5357 x->d86_numopnds = 3; 5358 dtrace_get_modrm(x, &mode, ®, &r_m); 5359 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5360 5361 /* 5362 * In classic Intel fashion, the opcodes for all of the FMA 5363 * instructions all have two possible mnemonics which vary by 5364 * one letter, which is selected based on the value of the wbit. 5365 * When wbit is one, they have the 'd' suffix and when 'wbit' is 5366 * 0, they have the 's' suffix. Otherwise, the FMA instructions 5367 * are all a standard VEX_RMrX. 5368 */ 5369 #ifdef DIS_TEXT 5370 if (dp->it_adrmode == FMA) { 5371 size_t len = strlen(dp->it_name); 5372 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN); 5373 if (len + 1 < OPLEN) { 5374 (void) strncpy(x->d86_mnem + len, 5375 vex_W != 0 ? "d" : "s", OPLEN - len); 5376 } 5377 } 5378 #endif 5379 5380 if (mode != REG_ONLY) { 5381 if ((dp == &dis_opAVXF20F[0x10]) || 5382 (dp == &dis_opAVXF30F[0x10])) { 5383 /* vmovsd <m64>, <xmm> */ 5384 /* or vmovss <m64>, <xmm> */ 5385 x->d86_numopnds = 2; 5386 goto L_VEX_MX; 5387 } 5388 } 5389 5390 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5391 /* 5392 * VEX prefix uses the 1's complement form to encode the 5393 * XMM/YMM regs 5394 */ 5395 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5396 5397 if ((dp == &dis_opAVXF20F[0x2A]) || 5398 (dp == &dis_opAVXF30F[0x2A])) { 5399 /* 5400 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>, 5401 * <xmm>, <xmm> 5402 */ 5403 wbit = LONG_OPND; 5404 } 5405 #ifdef DIS_TEXT 5406 else if ((mode == REG_ONLY) && 5407 (dp == &dis_opAVX0F[0x1][0x6])) { /* vmovlhps */ 5408 (void) strncpy(x->d86_mnem, "vmovlhps", OPLEN); 5409 } else if ((mode == REG_ONLY) && 5410 (dp == &dis_opAVX0F[0x1][0x2])) { /* vmovhlps */ 5411 (void) strncpy(x->d86_mnem, "vmovhlps", OPLEN); 5412 } 5413 #endif 5414 dtrace_get_operand(x, mode, r_m, wbit, 0); 5415 5416 break; 5417 5418 case VEX_VRMrX: 5419 /* ModR/M.reg := op(MODR/M.r/m, VEX.vvvv) */ 5420 x->d86_numopnds = 3; 5421 dtrace_get_modrm(x, &mode, ®, &r_m); 5422 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5423 5424 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5425 /* 5426 * VEX prefix uses the 1's complement form to encode the 5427 * XMM/YMM regs 5428 */ 5429 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 0); 5430 5431 dtrace_get_operand(x, mode, r_m, wbit, 1); 5432 break; 5433 5434 case VEX_SbVM: 5435 /* ModR/M.reg := op(MODR/M.r/m, VSIB, VEX.vvvv) */ 5436 x->d86_numopnds = 3; 5437 x->d86_vsib = 1; 5438 5439 /* 5440 * All instructions that use VSIB are currently a mess. See the 5441 * comment around the dis_gather_regs_t structure definition. 5442 */ 5443 5444 vreg = &dis_vgather[opcode2][vex_W][vex_L]; 5445 5446 #ifdef DIS_TEXT 5447 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN); 5448 (void) strlcat(x->d86_mnem + strlen(dp->it_name), 5449 vreg->dgr_suffix, OPLEN - strlen(dp->it_name)); 5450 #endif 5451 5452 dtrace_get_modrm(x, &mode, ®, &r_m); 5453 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5454 5455 dtrace_get_operand(x, REG_ONLY, reg, vreg->dgr_arg2, 2); 5456 /* 5457 * VEX prefix uses the 1's complement form to encode the 5458 * XMM/YMM regs 5459 */ 5460 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), vreg->dgr_arg0, 5461 0); 5462 dtrace_get_operand(x, mode, r_m, vreg->dgr_arg1, 1); 5463 break; 5464 5465 case VEX_RRX: 5466 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 5467 x->d86_numopnds = 3; 5468 5469 dtrace_get_modrm(x, &mode, ®, &r_m); 5470 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5471 5472 if (mode != REG_ONLY) { 5473 if ((dp == &dis_opAVXF20F[0x11]) || 5474 (dp == &dis_opAVXF30F[0x11])) { 5475 /* vmovsd <xmm>, <m64> */ 5476 /* or vmovss <xmm>, <m64> */ 5477 x->d86_numopnds = 2; 5478 goto L_VEX_RM; 5479 } 5480 } 5481 5482 dtrace_get_operand(x, mode, r_m, wbit, 2); 5483 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5484 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5485 break; 5486 5487 case VEX_RMRX: 5488 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */ 5489 x->d86_numopnds = 4; 5490 5491 dtrace_get_modrm(x, &mode, ®, &r_m); 5492 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5493 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3); 5494 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 5495 if (dp == &dis_opAVX660F3A[0x18]) { 5496 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */ 5497 dtrace_get_operand(x, mode, r_m, XMM_OPND, 1); 5498 } else if ((dp == &dis_opAVX660F3A[0x20]) || 5499 (dp == & dis_opAVX660F[0xC4])) { 5500 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */ 5501 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */ 5502 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5503 } else if (dp == &dis_opAVX660F3A[0x22]) { 5504 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */ 5505 #ifdef DIS_TEXT 5506 if (vex_W) 5507 x->d86_mnem[6] = 'q'; 5508 #endif 5509 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5510 } else { 5511 dtrace_get_operand(x, mode, r_m, wbit, 1); 5512 } 5513 5514 /* one byte immediate number */ 5515 dtrace_imm_opnd(x, wbit, 1, 0); 5516 5517 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */ 5518 if ((dp == &dis_opAVX660F3A[0x4A]) || 5519 (dp == &dis_opAVX660F3A[0x4B]) || 5520 (dp == &dis_opAVX660F3A[0x4C])) { 5521 #ifdef DIS_TEXT 5522 int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4; 5523 #endif 5524 x->d86_opnd[0].d86_mode = MODE_NONE; 5525 #ifdef DIS_TEXT 5526 if (vex_L) 5527 (void) strncpy(x->d86_opnd[0].d86_opnd, 5528 dis_YMMREG[regnum], OPLEN); 5529 else 5530 (void) strncpy(x->d86_opnd[0].d86_opnd, 5531 dis_XMMREG[regnum], OPLEN); 5532 #endif 5533 } 5534 break; 5535 5536 case VEX_MX: 5537 /* ModR/M.reg := op(ModR/M.rm) */ 5538 x->d86_numopnds = 2; 5539 5540 dtrace_get_modrm(x, &mode, ®, &r_m); 5541 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5542 L_VEX_MX: 5543 5544 if ((dp == &dis_opAVXF20F[0xE6]) || 5545 (dp == &dis_opAVX660F[0x5A]) || 5546 (dp == &dis_opAVX660F[0xE6])) { 5547 /* vcvtpd2dq <ymm>, <xmm> */ 5548 /* or vcvtpd2ps <ymm>, <xmm> */ 5549 /* or vcvttpd2dq <ymm>, <xmm> */ 5550 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1); 5551 dtrace_get_operand(x, mode, r_m, wbit, 0); 5552 } else if ((dp == &dis_opAVXF30F[0xE6]) || 5553 (dp == &dis_opAVX0F[0x5][0xA]) || 5554 (dp == &dis_opAVX660F38[0x13]) || 5555 (dp == &dis_opAVX660F38[0x18]) || 5556 (dp == &dis_opAVX660F38[0x19]) || 5557 (dp == &dis_opAVX660F38[0x58]) || 5558 (dp == &dis_opAVX660F38[0x78]) || 5559 (dp == &dis_opAVX660F38[0x79]) || 5560 (dp == &dis_opAVX660F38[0x59])) { 5561 /* vcvtdq2pd <xmm>, <ymm> */ 5562 /* or vcvtps2pd <xmm>, <ymm> */ 5563 /* or vcvtph2ps <xmm>, <ymm> */ 5564 /* or vbroadcasts* <xmm>, <ymm> */ 5565 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5566 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 5567 } else if (dp == &dis_opAVX660F[0x6E]) { 5568 /* vmovd/q <reg/mem 32/64>, <xmm> */ 5569 #ifdef DIS_TEXT 5570 if (vex_W) 5571 x->d86_mnem[4] = 'q'; 5572 #endif 5573 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5574 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5575 } else { 5576 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5577 dtrace_get_operand(x, mode, r_m, wbit, 0); 5578 } 5579 5580 break; 5581 5582 case VEX_MXI: 5583 /* ModR/M.reg := op(ModR/M.rm, imm8) */ 5584 x->d86_numopnds = 3; 5585 5586 dtrace_get_modrm(x, &mode, ®, &r_m); 5587 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5588 5589 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5590 dtrace_get_operand(x, mode, r_m, wbit, 1); 5591 5592 /* one byte immediate number */ 5593 dtrace_imm_opnd(x, wbit, 1, 0); 5594 break; 5595 5596 case VEX_XXI: 5597 /* VEX.vvvv := op(ModR/M.rm, imm8) */ 5598 x->d86_numopnds = 3; 5599 5600 dtrace_get_modrm(x, &mode, ®, &r_m); 5601 #ifdef DIS_TEXT 5602 (void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg], 5603 OPLEN); 5604 #endif 5605 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5606 5607 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 5608 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1); 5609 5610 /* one byte immediate number */ 5611 dtrace_imm_opnd(x, wbit, 1, 0); 5612 break; 5613 5614 case VEX_MR: 5615 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */ 5616 if (dp == &dis_opAVX660F[0xC5]) { 5617 /* vpextrw <imm8>, <xmm>, <reg> */ 5618 x->d86_numopnds = 2; 5619 vbit = 2; 5620 } else { 5621 x->d86_numopnds = 2; 5622 vbit = 1; 5623 } 5624 5625 dtrace_get_modrm(x, &mode, ®, &r_m); 5626 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5627 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit); 5628 dtrace_get_operand(x, mode, r_m, wbit, vbit - 1); 5629 5630 if (vbit == 2) 5631 dtrace_imm_opnd(x, wbit, 1, 0); 5632 5633 break; 5634 5635 case VEX_KMR: 5636 /* opmask: mod_rm := %k */ 5637 x->d86_numopnds = 2; 5638 dtrace_get_modrm(x, &mode, ®, &r_m); 5639 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5640 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5641 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5642 break; 5643 5644 case VEX_KRM: 5645 /* opmask: mod_reg := mod_rm */ 5646 x->d86_numopnds = 2; 5647 dtrace_get_modrm(x, &mode, ®, &r_m); 5648 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5649 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5650 if (mode == REG_ONLY) { 5651 dtrace_get_operand(x, mode, r_m, KOPMASK_OPND, 0); 5652 } else { 5653 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5654 } 5655 break; 5656 5657 case VEX_KRR: 5658 /* opmask: mod_reg := mod_rm */ 5659 x->d86_numopnds = 2; 5660 dtrace_get_modrm(x, &mode, ®, &r_m); 5661 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5662 dtrace_get_operand(x, mode, reg, wbit, 1); 5663 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 0); 5664 break; 5665 5666 case VEX_RRI: 5667 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */ 5668 x->d86_numopnds = 2; 5669 5670 dtrace_get_modrm(x, &mode, ®, &r_m); 5671 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5672 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5673 dtrace_get_operand(x, mode, r_m, wbit, 0); 5674 break; 5675 5676 case VEX_RX: 5677 /* ModR/M.rm := op(ModR/M.reg) */ 5678 /* vextractf128 || vcvtps2ph */ 5679 if (dp == &dis_opAVX660F3A[0x19] || 5680 dp == &dis_opAVX660F3A[0x1d]) { 5681 x->d86_numopnds = 3; 5682 5683 dtrace_get_modrm(x, &mode, ®, &r_m); 5684 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5685 5686 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 5687 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5688 5689 /* one byte immediate number */ 5690 dtrace_imm_opnd(x, wbit, 1, 0); 5691 break; 5692 } 5693 5694 x->d86_numopnds = 2; 5695 5696 dtrace_get_modrm(x, &mode, ®, &r_m); 5697 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5698 dtrace_get_operand(x, mode, r_m, wbit, 1); 5699 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5700 break; 5701 5702 case VEX_RR: 5703 /* ModR/M.rm := op(ModR/M.reg) */ 5704 x->d86_numopnds = 2; 5705 5706 dtrace_get_modrm(x, &mode, ®, &r_m); 5707 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5708 5709 if (dp == &dis_opAVX660F[0x7E]) { 5710 /* vmovd/q <reg/mem 32/64>, <xmm> */ 5711 #ifdef DIS_TEXT 5712 if (vex_W) 5713 x->d86_mnem[4] = 'q'; 5714 #endif 5715 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5716 } else 5717 dtrace_get_operand(x, mode, r_m, wbit, 1); 5718 5719 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5720 break; 5721 5722 case VEX_RRi: 5723 /* ModR/M.rm := op(ModR/M.reg, imm) */ 5724 x->d86_numopnds = 3; 5725 5726 dtrace_get_modrm(x, &mode, ®, &r_m); 5727 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5728 5729 #ifdef DIS_TEXT 5730 if (dp == &dis_opAVX660F3A[0x16]) { 5731 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */ 5732 if (vex_W) 5733 x->d86_mnem[6] = 'q'; 5734 } 5735 #endif 5736 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 5737 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5738 5739 /* one byte immediate number */ 5740 dtrace_imm_opnd(x, wbit, 1, 0); 5741 break; 5742 case VEX_RIM: 5743 /* ModR/M.rm := op(ModR/M.reg, imm) */ 5744 x->d86_numopnds = 3; 5745 5746 dtrace_get_modrm(x, &mode, ®, &r_m); 5747 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5748 5749 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 5750 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5751 /* one byte immediate number */ 5752 dtrace_imm_opnd(x, wbit, 1, 0); 5753 break; 5754 5755 case VEX_RM: 5756 /* ModR/M.rm := op(ModR/M.reg) */ 5757 if (dp == &dis_opAVX660F3A[0x17]) { /* vextractps */ 5758 x->d86_numopnds = 3; 5759 5760 dtrace_get_modrm(x, &mode, ®, &r_m); 5761 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5762 5763 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 5764 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5765 /* one byte immediate number */ 5766 dtrace_imm_opnd(x, wbit, 1, 0); 5767 break; 5768 } 5769 x->d86_numopnds = 2; 5770 5771 dtrace_get_modrm(x, &mode, ®, &r_m); 5772 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5773 L_VEX_RM: 5774 vbit = 1; 5775 dtrace_get_operand(x, mode, r_m, wbit, vbit); 5776 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1); 5777 5778 break; 5779 5780 case VEX_RRM: 5781 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 5782 x->d86_numopnds = 3; 5783 5784 dtrace_get_modrm(x, &mode, ®, &r_m); 5785 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5786 dtrace_get_operand(x, mode, r_m, wbit, 2); 5787 /* VEX use the 1's complement form encode the XMM/YMM regs */ 5788 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5789 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5790 break; 5791 5792 case VEX_RMX: 5793 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */ 5794 x->d86_numopnds = 3; 5795 5796 dtrace_get_modrm(x, &mode, ®, &r_m); 5797 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5798 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5799 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5800 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0); 5801 break; 5802 5803 case VEX_NONE: 5804 #ifdef DIS_TEXT 5805 if (vex_L) 5806 (void) strncpy(x->d86_mnem, "vzeroall", OPLEN); 5807 #endif 5808 break; 5809 case BLS: { 5810 5811 /* 5812 * The BLS instructions are VEX instructions that are based on 5813 * VEX.0F38.F3; however, they are considered special group 17 5814 * and like everything else, they use the bits in 3-5 of the 5815 * MOD R/M to determine the sub instruction. Unlike many others 5816 * like the VMX instructions, these are valid both for memory 5817 * and register forms. 5818 */ 5819 5820 dtrace_get_modrm(x, &mode, ®, &r_m); 5821 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5822 5823 switch (reg) { 5824 case 1: 5825 #ifdef DIS_TEXT 5826 blsinstr = "blsr"; 5827 #endif 5828 break; 5829 case 2: 5830 #ifdef DIS_TEXT 5831 blsinstr = "blsmsk"; 5832 #endif 5833 break; 5834 case 3: 5835 #ifdef DIS_TEXT 5836 blsinstr = "blsi"; 5837 #endif 5838 break; 5839 default: 5840 goto error; 5841 } 5842 5843 x->d86_numopnds = 2; 5844 #ifdef DIS_TEXT 5845 (void) strncpy(x->d86_mnem, blsinstr, OPLEN); 5846 #endif 5847 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5848 dtrace_get_operand(x, mode, r_m, wbit, 0); 5849 break; 5850 } 5851 case EVEX_MX: 5852 /* ModR/M.reg := op(ModR/M.rm) */ 5853 x->d86_numopnds = 2; 5854 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 5855 dtrace_get_modrm(x, &mode, ®, &r_m); 5856 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 5857 dtrace_evex_adjust_reg(evex_byte1, ®); 5858 dtrace_evex_adjust_rm(evex_byte1, &r_m); 5859 dtrace_evex_adjust_reg_name(evex_L, &wbit); 5860 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5861 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3); 5862 dtrace_get_operand(x, mode, r_m, wbit, 0); 5863 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 5864 break; 5865 case EVEX_RX: 5866 /* ModR/M.rm := op(ModR/M.reg) */ 5867 x->d86_numopnds = 2; 5868 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 5869 dtrace_get_modrm(x, &mode, ®, &r_m); 5870 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 5871 dtrace_evex_adjust_reg(evex_byte1, ®); 5872 dtrace_evex_adjust_rm(evex_byte1, &r_m); 5873 dtrace_evex_adjust_reg_name(evex_L, &wbit); 5874 dtrace_get_operand(x, mode, r_m, wbit, 1); 5875 dtrace_evex_adjust_disp8_n(x, 1, evex_L, evex_modrm); 5876 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3); 5877 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5878 break; 5879 case EVEX_RMrX: 5880 /* ModR/M.reg := op(EVEX.vvvv, ModR/M.r/m) */ 5881 x->d86_numopnds = 3; 5882 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 5883 dtrace_get_modrm(x, &mode, ®, &r_m); 5884 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 5885 dtrace_evex_adjust_reg(evex_byte1, ®); 5886 dtrace_evex_adjust_rm(evex_byte1, &r_m); 5887 dtrace_evex_adjust_reg_name(evex_L, &wbit); 5888 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5889 /* 5890 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the 5891 * register specifier). The EVEX prefix handling uses the vex_v 5892 * variable for these bits. 5893 */ 5894 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5895 dtrace_get_operand(x, mode, r_m, wbit, 0); 5896 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 5897 dtrace_evex_adjust_z_opmask(x, 2, evex_byte3); 5898 break; 5899 /* an invalid op code */ 5900 case AM: 5901 case DM: 5902 case OVERRIDE: 5903 case PREFIX: 5904 case UNKNOWN: 5905 NOMEM; 5906 default: 5907 goto error; 5908 } /* end switch */ 5909 if (x->d86_error) 5910 goto error; 5911 5912 done: 5913 #ifdef DIS_MEM 5914 /* 5915 * compute the size of any memory accessed by the instruction 5916 */ 5917 if (x->d86_memsize != 0) { 5918 return (0); 5919 } else if (dp->it_stackop) { 5920 switch (opnd_size) { 5921 case SIZE16: 5922 x->d86_memsize = 2; 5923 break; 5924 case SIZE32: 5925 x->d86_memsize = 4; 5926 break; 5927 case SIZE64: 5928 x->d86_memsize = 8; 5929 break; 5930 } 5931 } else if (nomem || mode == REG_ONLY) { 5932 x->d86_memsize = 0; 5933 5934 } else if (dp->it_size != 0) { 5935 /* 5936 * In 64 bit mode descriptor table entries 5937 * go up to 10 bytes and popf/pushf are always 8 bytes 5938 */ 5939 if (x->d86_mode == SIZE64 && dp->it_size == 6) 5940 x->d86_memsize = 10; 5941 else if (x->d86_mode == SIZE64 && opcode1 == 0x9 && 5942 (opcode2 == 0xc || opcode2 == 0xd)) 5943 x->d86_memsize = 8; 5944 else 5945 x->d86_memsize = dp->it_size; 5946 5947 } else if (wbit == 0) { 5948 x->d86_memsize = 1; 5949 5950 } else if (wbit == LONG_OPND) { 5951 if (opnd_size == SIZE64) 5952 x->d86_memsize = 8; 5953 else if (opnd_size == SIZE32) 5954 x->d86_memsize = 4; 5955 else 5956 x->d86_memsize = 2; 5957 5958 } else if (wbit == SEG_OPND) { 5959 x->d86_memsize = 4; 5960 5961 } else { 5962 x->d86_memsize = 8; 5963 } 5964 #endif 5965 return (0); 5966 5967 error: 5968 #ifdef DIS_TEXT 5969 (void) strlcat(x->d86_mnem, "undef", OPLEN); 5970 #endif 5971 return (1); 5972 } 5973 5974 #ifdef DIS_TEXT 5975 5976 /* 5977 * Some instructions should have immediate operands printed 5978 * as unsigned integers. We compare against this table. 5979 */ 5980 static char *unsigned_ops[] = { 5981 "or", "and", "xor", "test", "in", "out", "lcall", "ljmp", 5982 "rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl", 5983 0 5984 }; 5985 5986 5987 static int 5988 isunsigned_op(char *opcode) 5989 { 5990 char *where; 5991 int i; 5992 int is_unsigned = 0; 5993 5994 /* 5995 * Work back to start of last mnemonic, since we may have 5996 * prefixes on some opcodes. 5997 */ 5998 where = opcode + strlen(opcode) - 1; 5999 while (where > opcode && *where != ' ') 6000 --where; 6001 if (*where == ' ') 6002 ++where; 6003 6004 for (i = 0; unsigned_ops[i]; ++i) { 6005 if (strncmp(where, unsigned_ops[i], 6006 strlen(unsigned_ops[i]))) 6007 continue; 6008 is_unsigned = 1; 6009 break; 6010 } 6011 return (is_unsigned); 6012 } 6013 6014 /* 6015 * Print a numeric immediate into end of buf, maximum length buflen. 6016 * The immediate may be an address or a displacement. Mask is set 6017 * for address size. If the immediate is a "small negative", or 6018 * if it's a negative displacement of any magnitude, print as -<absval>. 6019 * Respect the "octal" flag. "Small negative" is defined as "in the 6020 * interval [NEG_LIMIT, 0)". 6021 * 6022 * Also, "isunsigned_op()" instructions never print negatives. 6023 * 6024 * Return whether we decided to print a negative value or not. 6025 */ 6026 6027 #define NEG_LIMIT -255 6028 enum {IMM, DISP}; 6029 enum {POS, TRY_NEG}; 6030 6031 static int 6032 print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf, 6033 size_t buflen, int disp, int try_neg) 6034 { 6035 int curlen; 6036 int64_t sv = (int64_t)usv; 6037 int octal = dis->d86_flags & DIS_F_OCTAL; 6038 6039 curlen = strlen(buf); 6040 6041 if (try_neg == TRY_NEG && sv < 0 && 6042 (disp || sv >= NEG_LIMIT) && 6043 !isunsigned_op(dis->d86_mnem)) { 6044 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 6045 octal ? "-0%llo" : "-0x%llx", (-sv) & mask); 6046 return (1); 6047 } else { 6048 if (disp == DISP) 6049 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 6050 octal ? "+0%llo" : "+0x%llx", usv & mask); 6051 else 6052 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 6053 octal ? "0%llo" : "0x%llx", usv & mask); 6054 return (0); 6055 6056 } 6057 } 6058 6059 6060 static int 6061 log2(int size) 6062 { 6063 switch (size) { 6064 case 1: return (0); 6065 case 2: return (1); 6066 case 4: return (2); 6067 case 8: return (3); 6068 } 6069 return (0); 6070 } 6071 6072 /* ARGSUSED */ 6073 void 6074 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf, 6075 size_t buflen) 6076 { 6077 uint64_t reltgt = 0; 6078 uint64_t tgt = 0; 6079 int curlen; 6080 int (*lookup)(void *, uint64_t, char *, size_t); 6081 int i; 6082 int64_t sv; 6083 uint64_t usv, mask, save_mask, save_usv; 6084 static uint64_t masks[] = 6085 {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL}; 6086 save_usv = 0; 6087 6088 dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem); 6089 6090 /* 6091 * For PC-relative jumps, the pc is really the next pc after executing 6092 * this instruction, so increment it appropriately. 6093 */ 6094 pc += dis->d86_len; 6095 6096 for (i = 0; i < dis->d86_numopnds; i++) { 6097 d86opnd_t *op = &dis->d86_opnd[i]; 6098 6099 if (i != 0) 6100 (void) strlcat(buf, ",", buflen); 6101 6102 (void) strlcat(buf, op->d86_prefix, buflen); 6103 6104 /* 6105 * sv is for the signed, possibly-truncated immediate or 6106 * displacement; usv retains the original size and 6107 * unsignedness for symbol lookup. 6108 */ 6109 6110 sv = usv = op->d86_value; 6111 6112 /* 6113 * About masks: for immediates that represent 6114 * addresses, the appropriate display size is 6115 * the effective address size of the instruction. 6116 * This includes MODE_OFFSET, MODE_IPREL, and 6117 * MODE_RIPREL. Immediates that are simply 6118 * immediate values should display in the operand's 6119 * size, however, since they don't represent addresses. 6120 */ 6121 6122 /* d86_addr_size is SIZEnn, which is log2(real size) */ 6123 mask = masks[dis->d86_addr_size]; 6124 6125 /* d86_value_size and d86_imm_bytes are in bytes */ 6126 if (op->d86_mode == MODE_SIGNED || 6127 op->d86_mode == MODE_IMPLIED) 6128 mask = masks[log2(op->d86_value_size)]; 6129 6130 switch (op->d86_mode) { 6131 6132 case MODE_NONE: 6133 6134 (void) strlcat(buf, op->d86_opnd, buflen); 6135 break; 6136 6137 case MODE_SIGNED: 6138 case MODE_IMPLIED: 6139 case MODE_OFFSET: 6140 6141 tgt = usv; 6142 6143 if (dis->d86_seg_prefix) 6144 (void) strlcat(buf, dis->d86_seg_prefix, 6145 buflen); 6146 6147 if (op->d86_mode == MODE_SIGNED || 6148 op->d86_mode == MODE_IMPLIED) { 6149 (void) strlcat(buf, "$", buflen); 6150 } 6151 6152 if (print_imm(dis, usv, mask, buf, buflen, 6153 IMM, TRY_NEG) && 6154 (op->d86_mode == MODE_SIGNED || 6155 op->d86_mode == MODE_IMPLIED)) { 6156 6157 /* 6158 * We printed a negative value for an 6159 * immediate that wasn't a 6160 * displacement. Note that fact so we can 6161 * print the positive value as an 6162 * annotation. 6163 */ 6164 6165 save_usv = usv; 6166 save_mask = mask; 6167 } 6168 (void) strlcat(buf, op->d86_opnd, buflen); 6169 6170 break; 6171 6172 case MODE_IPREL: 6173 case MODE_RIPREL: 6174 6175 reltgt = pc + sv; 6176 6177 switch (mode) { 6178 case SIZE16: 6179 reltgt = (uint16_t)reltgt; 6180 break; 6181 case SIZE32: 6182 reltgt = (uint32_t)reltgt; 6183 break; 6184 } 6185 6186 (void) print_imm(dis, usv, mask, buf, buflen, 6187 DISP, TRY_NEG); 6188 6189 if (op->d86_mode == MODE_RIPREL) 6190 (void) strlcat(buf, "(%rip)", buflen); 6191 break; 6192 } 6193 } 6194 6195 /* 6196 * The symbol lookups may result in false positives, 6197 * particularly on object files, where small numbers may match 6198 * the 0-relative non-relocated addresses of symbols. 6199 */ 6200 6201 lookup = dis->d86_sym_lookup; 6202 if (tgt != 0) { 6203 if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 && 6204 lookup(dis->d86_data, tgt, NULL, 0) == 0) { 6205 (void) strlcat(buf, "\t<", buflen); 6206 curlen = strlen(buf); 6207 lookup(dis->d86_data, tgt, buf + curlen, 6208 buflen - curlen); 6209 (void) strlcat(buf, ">", buflen); 6210 } 6211 6212 /* 6213 * If we printed a negative immediate above, print the 6214 * positive in case our heuristic was unhelpful 6215 */ 6216 if (save_usv) { 6217 (void) strlcat(buf, "\t<", buflen); 6218 (void) print_imm(dis, save_usv, save_mask, buf, buflen, 6219 IMM, POS); 6220 (void) strlcat(buf, ">", buflen); 6221 } 6222 } 6223 6224 if (reltgt != 0) { 6225 /* Print symbol or effective address for reltgt */ 6226 6227 (void) strlcat(buf, "\t<", buflen); 6228 curlen = strlen(buf); 6229 lookup(dis->d86_data, reltgt, buf + curlen, 6230 buflen - curlen); 6231 (void) strlcat(buf, ">", buflen); 6232 } 6233 } 6234 6235 #endif /* DIS_TEXT */ 6236