1/*
2 *
3 * CDDL HEADER START
4 *
5 * The contents of this file are subject to the terms of the
6 * Common Development and Distribution License (the "License").
7 * You may not use this file except in compliance with the License.
8 *
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22/*
23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright 2019 Joyent, Inc.
25 * Copyright 2020 Robert Mustacchi
26 */
27
28/*
29 * Copyright (c) 2010, Intel Corporation.
30 * All rights reserved.
31 */
32
33/*	Copyright (c) 1988 AT&T	*/
34/*	  All Rights Reserved	*/
35
36#include	"dis_tables.h"
37
38/* BEGIN CSTYLED */
39
40/*
41 * Disassembly begins in dis_distable, which is equivalent to the One-byte
42 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy).  The
43 * decoding loops then traverse out through the other tables as necessary to
44 * decode a given instruction.
45 *
46 * The behavior of this file can be controlled by one of the following flags:
47 *
48 *	DIS_TEXT	Include text for disassembly
49 *	DIS_MEM		Include memory-size calculations
50 *
51 * Either or both of these can be defined.
52 *
53 * This file is not, and will never be, cstyled.  If anything, the tables should
54 * be taken out another tab stop or two so nothing overlaps.
55 */
56
57/*
58 * These functions must be provided for the consumer to do disassembly.
59 */
60#ifdef DIS_TEXT
61extern char *strncpy(char *, const char *, size_t);
62extern size_t strlen(const char *);
63extern int strcmp(const char *, const char *);
64extern int strncmp(const char *, const char *, size_t);
65extern size_t strlcat(char *, const char *, size_t);
66#endif
67
68
69#define		TERM	0	/* used to indicate that the 'indirect' */
70				/* field terminates - no pointer.	*/
71
72/* Used to decode instructions. */
73typedef struct	instable {
74	struct instable	*it_indirect;	/* for decode op codes */
75	uchar_t		it_adrmode;
76#ifdef DIS_TEXT
77	char		it_name[NCPS];
78	uint_t		it_suffix:1;		/* mnem + "w", "l", or "d" */
79#endif
80#ifdef DIS_MEM
81	uint_t		it_size:16;
82#endif
83	uint_t		it_invalid64:1;		/* opcode invalid in amd64 */
84	uint_t		it_always64:1;		/* 64 bit when in 64 bit mode */
85	uint_t		it_invalid32:1;		/* invalid in IA32 */
86	uint_t		it_stackop:1;		/* push/pop stack operation */
87	uint_t		it_vexwoxmm:1;		/* VEX instructions that don't use XMM/YMM */
88	uint_t		it_avxsuf:2;		/* AVX2/AVX512 suffix rqd. */
89	uint_t		it_vexopmask:1;		/* VEX inst. that use opmask */
90} instable_t;
91
92/*
93 * Instruction formats.
94 */
95enum {
96	UNKNOWN,
97	MRw,
98	IMlw,
99	IMw,
100	IR,
101	OA,
102	AO,
103	MS,
104	SM,
105	Mv,
106	Mw,
107	M,		/* register or memory */
108	MG9,		/* register or memory in group 9 (prefix optional) */
109	Mb,		/* register or memory, always byte sized */
110	MO,		/* memory only (no registers) */
111	PREF,
112	SWAPGS_RDTSCP,
113	MONITOR_MWAIT,
114	R,
115	RA,
116	SEG,
117	MR,
118	RM,
119	RM_66r,		/* RM, but with a required 0x66 prefix */
120	IA,
121	MA,
122	SD,
123	AD,
124	SA,
125	D,
126	INM,
127	SO,
128	BD,
129	I,
130	P,
131	V,
132	DSHIFT,		/* for double shift that has an 8-bit immediate */
133	U,
134	OVERRIDE,
135	NORM,		/* instructions w/o ModR/M byte, no memory access */
136	IMPLMEM,	/* instructions w/o ModR/M byte, implicit mem access */
137	O,		/* for call	*/
138	JTAB,		/* jump table	*/
139	IMUL,		/* for 186 iimul instr  */
140	CBW,		/* so data16 can be evaluated for cbw and variants */
141	MvI,		/* for 186 logicals */
142	ENTER,		/* for 186 enter instr  */
143	RMw,		/* for 286 arpl instr */
144	Ib,		/* for push immediate byte */
145	F,		/* for 287 instructions */
146	FF,		/* for 287 instructions */
147	FFC,		/* for 287 instructions */
148	DM,		/* 16-bit data */
149	AM,		/* 16-bit addr */
150	LSEG,		/* for 3-bit seg reg encoding */
151	MIb,		/* for 386 logicals */
152	SREG,		/* for 386 special registers */
153	PREFIX,		/* a REP instruction prefix */
154	LOCK,		/* a LOCK instruction prefix */
155	INT3,		/* The int 3 instruction, which has a fake operand */
156	INTx,		/* The normal int instruction, with explicit int num */
157	DSHIFTcl,	/* for double shift that implicitly uses %cl */
158	CWD,		/* so data16 can be evaluated for cwd and variants */
159	RET,		/* single immediate 16-bit operand */
160	MOVZ,		/* for movs and movz, with different size operands */
161	CRC32,		/* for crc32, with different size operands */
162	XADDB,		/* for xaddb */
163	MOVSXZ,		/* AMD64 mov sign extend 32 to 64 bit instruction */
164	MOVBE,		/* movbe instruction */
165
166/*
167 * MMX/SIMD addressing modes.
168 */
169
170	MMO,		/* Prefixable MMX/SIMD-Int	mm/mem	-> mm */
171	MMOIMPL,	/* Prefixable MMX/SIMD-Int	mm	-> mm (mem) */
172	MMO3P,		/* Prefixable MMX/SIMD-Int	mm	-> r32,imm8 */
173	MMOM3,		/* Prefixable MMX/SIMD-Int	mm	-> r32	*/
174	MMOS,		/* Prefixable MMX/SIMD-Int	mm	-> mm/mem */
175	MMOMS,		/* Prefixable MMX/SIMD-Int	mm	-> mem */
176	MMOPM,		/* MMX/SIMD-Int			mm/mem	-> mm,imm8 */
177	MMOPM_66o,	/* MMX/SIMD-Int 0x66 optional	mm/mem	-> mm,imm8 */
178	MMOPRM,		/* Prefixable MMX/SIMD-Int	r32/mem	-> mm,imm8 */
179	MMOSH,		/* Prefixable MMX		mm,imm8	*/
180	MM,		/* MMX/SIMD-Int			mm/mem	-> mm	*/
181	MMS,		/* MMX/SIMD-Int			mm	-> mm/mem */
182	MMSH,		/* MMX				mm,imm8 */
183	XMMO,		/* Prefixable SIMD		xmm/mem	-> xmm */
184	XMMOS,		/* Prefixable SIMD		xmm	-> xmm/mem */
185	XMMOPM,		/* Prefixable SIMD		xmm/mem	w/to xmm,imm8 */
186	XMMOMX,		/* Prefixable SIMD		mm/mem	-> xmm */
187	XMMOX3,		/* Prefixable SIMD		xmm	-> r32 */
188	XMMOXMM,	/* Prefixable SIMD		xmm/mem	-> mm	*/
189	XMMOM,		/* Prefixable SIMD		xmm	-> mem */
190	XMMOMS,		/* Prefixable SIMD		mem	-> xmm */
191	XMM,		/* SIMD				xmm/mem	-> xmm */
192	XMM_66r,	/* SIMD 0x66 prefix required	xmm/mem	-> xmm */
193	XMM_66o,	/* SIMD 0x66 prefix optional	xmm/mem	-> xmm */
194	XMMXIMPL,	/* SIMD				xmm	-> xmm (mem) */
195	XMM3P,		/* SIMD				xmm	-> r32,imm8 */
196	XMM3PM_66r,	/* SIMD 0x66 prefix required	xmm	-> r32/mem,imm8 */
197	XMMP,		/* SIMD				xmm/mem w/to xmm,imm8 */
198	XMMP_66o,	/* SIMD 0x66 prefix optional	xmm/mem w/to xmm,imm8 */
199	XMMP_66r,	/* SIMD 0x66 prefix required	xmm/mem w/to xmm,imm8 */
200	XMMPRM,		/* SIMD				r32/mem -> xmm,imm8 */
201	XMMPRM_66r,	/* SIMD 0x66 prefix required	r32/mem -> xmm,imm8 */
202	XMMS,		/* SIMD				xmm	-> xmm/mem */
203	XMMM,		/* SIMD				mem	-> xmm */
204	XMMM_66r,	/* SIMD	0x66 prefix required	mem	-> xmm */
205	XMMMS,		/* SIMD				xmm	-> mem */
206	XMM3MX,		/* SIMD				r32/mem -> xmm */
207	XMM3MXS,	/* SIMD				xmm	-> r32/mem */
208	XMMSH,		/* SIMD				xmm,imm8 */
209	XMMXM3,		/* SIMD				xmm/mem -> r32 */
210	XMMX3,		/* SIMD				xmm	-> r32 */
211	XMMXMM,		/* SIMD				xmm/mem	-> mm */
212	XMMMX,		/* SIMD				mm	-> xmm */
213	XMMXM,		/* SIMD				xmm	-> mm */
214	XMMX2I,		/* SIMD				xmm -> xmm, imm, imm */
215	XMM2I,		/* SIMD				xmm, imm, imm */
216	XMMFENCE,	/* SIMD lfence or mfence */
217	XMMSFNC,	/* SIMD sfence (none or mem) */
218	FSGS,		/* FSGSBASE if reg */
219	XGETBV_XSETBV,
220	VEX_NONE,	/* VEX  no operand */
221	VEX_MO,		/* VEX	mod_rm		               -> implicit reg */
222	VEX_RMrX,	/* VEX  VEX.vvvv, mod_rm               -> mod_reg */
223	VEX_VRMrX,	/* VEX  mod_rm, VEX.vvvv               -> mod_rm */
224	VEX_RRX,	/* VEX  VEX.vvvv, mod_reg              -> mod_rm */
225	VEX_RMRX,	/* VEX  VEX.vvvv, mod_rm, imm8[7:4]    -> mod_reg */
226	VEX_MX,		/* VEX  mod_rm                         -> mod_reg */
227	VEX_MXI,	/* VEX  mod_rm, imm8                   -> mod_reg */
228	VEX_XXI,	/* VEX  mod_rm, imm8                   -> VEX.vvvv */
229	VEX_MR,		/* VEX  mod_rm                         -> mod_reg */
230	VEX_RRI,	/* VEX  mod_reg, mod_rm                -> implicit(eflags/r32) */
231	VEX_RX,		/* VEX  mod_reg                        -> mod_rm */
232	VEX_KRR,	/* VEX  mod_rm                         -> mod_reg */
233	VEX_KMR,	/* VEX  mod_reg                        -> mod_rm */
234	VEX_KRM,	/* VEX  mod_rm                         -> mod_reg */
235	VEX_RR,		/* VEX  mod_rm                         -> mod_reg */
236	VEX_RRi,	/* VEX  mod_rm, imm8                   -> mod_reg */
237	VEX_RM,		/* VEX  mod_reg                        -> mod_rm */
238	VEX_RIM,	/* VEX  mod_reg, imm8                  -> mod_rm */
239	VEX_RRM,	/* VEX  VEX.vvvv, mod_reg              -> mod_rm */
240	VEX_RMX,	/* VEX  VEX.vvvv, mod_rm               -> mod_reg */
241	VEX_SbVM,	/* VEX  SIB, VEX.vvvv                  -> mod_rm */
242	VMx,		/* vmcall/vmlaunch/vmresume/vmxoff */
243	VMxo,		/* VMx instruction with optional prefix */
244	SVM,		/* AMD SVM instructions */
245	BLS,		/* BLSR, BLSMSK, BLSI */
246	FMA,		/* FMA instructions, all VEX_RMrX */
247	ADX,		/* ADX instructions, support REX.w, mod_rm->mod_reg */
248	EVEX_RX,	/* EVEX  mod_reg                      -> mod_rm */
249	EVEX_MX,	/* EVEX  mod_rm                       -> mod_reg */
250	EVEX_RMrX,	/* EVEX  EVEX.vvvv, mod_rm            -> mod_reg */
251	EVEX_RMRX	/* EVEX  EVEX.vvvv, mod_rm, imm8      -> mod_reg */
252};
253
254/*
255 * VEX prefixes
256 */
257#define VEX_2bytes	0xC5	/* the first byte of two-byte form */
258#define VEX_3bytes	0xC4	/* the first byte of three-byte form */
259
260#define	FILL	0x90	/* Fill byte used for alignment (nop)	*/
261
262/*
263** Register numbers for the i386
264*/
265#define	EAX_REGNO 0
266#define	ECX_REGNO 1
267#define	EDX_REGNO 2
268#define	EBX_REGNO 3
269#define	ESP_REGNO 4
270#define	EBP_REGNO 5
271#define	ESI_REGNO 6
272#define	EDI_REGNO 7
273
274/*
275 * modes for immediate values
276 */
277#define	MODE_NONE	0
278#define	MODE_IPREL	1	/* signed IP relative value */
279#define	MODE_SIGNED	2	/* sign extended immediate */
280#define	MODE_IMPLIED	3	/* constant value implied from opcode */
281#define	MODE_OFFSET	4	/* offset part of an address */
282#define	MODE_RIPREL	5	/* like IPREL, but from %rip (amd64) */
283
284/*
285 * The letters used in these macros are:
286 *   IND - indirect to another to another table
287 *   "T" - means to Terminate indirections (this is the final opcode)
288 *   "S" - means "operand length suffix required"
289 *   "Sa" - means AVX2 suffix (q/d) required
290 *   "Sq" - means AVX512 suffix (q/d) required
291 *   "Sd" - means AVX512 suffix (d/s) required
292 *   "NS" - means "no suffix" which is the operand length suffix of the opcode
293 *   "Z" - means instruction size arg required
294 *   "u" - means the opcode is invalid in IA32 but valid in amd64
295 *   "x" - means the opcode is invalid in amd64, but not IA32
296 *   "y" - means the operand size is always 64 bits in 64 bit mode
297 *   "p" - means push/pop stack operation
298 *   "vr" - means VEX instruction that operates on normal registers, not fpu
299 *   "vo" - means VEX instruction that operates on opmask registers, not fpu
300 */
301
302#define	AVS2	(uint_t)1	/* it_avxsuf: AVX2 q/d suffix handling */
303#define	AVS5Q	(uint_t)2	/* it_avxsuf: AVX512 q/d suffix handling */
304#define	AVS5D	(uint_t)3	/* it_avxsuf: AVX512 d/s suffix handling */
305
306#if defined(DIS_TEXT) && defined(DIS_MEM)
307#define	IND(table)		{(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0}
308#define	INDx(table)		{(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0}
309#define	TNS(name, amode)	{TERM, amode, name, 0, 0, 0, 0, 0, 0}
310#define	TNSu(name, amode)	{TERM, amode, name, 0, 0, 0, 0, 1, 0}
311#define	TNSx(name, amode)	{TERM, amode, name, 0, 0, 1, 0, 0, 0}
312#define	TNSy(name, amode)	{TERM, amode, name, 0, 0, 0, 1, 0, 0}
313#define	TNSyp(name, amode)	{TERM, amode, name, 0, 0, 0, 1, 0, 1}
314#define	TNSZ(name, amode, sz)	{TERM, amode, name, 0, sz, 0, 0, 0, 0}
315#define	TNSZy(name, amode, sz)	{TERM, amode, name, 0, sz, 0, 1, 0, 0}
316#define	TNSZvr(name, amode, sz)	{TERM, amode, name, 0, sz, 0, 0, 0, 0, 1}
317#define	TSvo(name, amode)	{TERM, amode, name, 1,  0, 0, 0, 0, 0, 0, 0, 1}
318#define	TS(name, amode)		{TERM, amode, name, 1, 0, 0, 0, 0, 0}
319#define	TSx(name, amode)	{TERM, amode, name, 1, 0, 1, 0, 0, 0}
320#define	TSy(name, amode)	{TERM, amode, name, 1, 0, 0, 1, 0, 0}
321#define	TSp(name, amode)	{TERM, amode, name, 1, 0, 0, 0, 0, 1}
322#define	TSZ(name, amode, sz)	{TERM, amode, name, 1, sz, 0, 0, 0, 0}
323#define	TSaZ(name, amode, sz)	{TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, AVS2}
324#define	TSq(name, amode)	{TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5Q}
325#define	TSd(name, amode)	{TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5D}
326#define	TSZx(name, amode, sz)	{TERM, amode, name, 1, sz, 1, 0, 0, 0}
327#define	TSZy(name, amode, sz)	{TERM, amode, name, 1, sz, 0, 1, 0, 0}
328#define	INVALID			{TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
329#elif defined(DIS_TEXT)
330#define	IND(table)		{(instable_t *)table, 0, "", 0, 0, 0, 0, 0}
331#define	INDx(table)		{(instable_t *)table, 0, "", 0, 1, 0, 0, 0}
332#define	TNS(name, amode)	{TERM, amode, name, 0, 0, 0, 0, 0}
333#define	TNSu(name, amode)	{TERM, amode, name, 0, 0, 0, 1, 0}
334#define	TNSx(name, amode)	{TERM, amode, name, 0, 1, 0, 0, 0}
335#define	TNSy(name, amode)	{TERM, amode, name, 0, 0, 1, 0, 0}
336#define	TNSyp(name, amode)	{TERM, amode, name, 0, 0, 1, 0, 1}
337#define	TNSZ(name, amode, sz)	{TERM, amode, name, 0, 0, 0, 0, 0}
338#define	TNSZy(name, amode, sz)	{TERM, amode, name, 0, 0, 1, 0, 0}
339#define	TNSZvr(name, amode, sz)	{TERM, amode, name, 0, 0, 0, 0, 0, 1}
340#define	TSvo(name, amode)	{TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 1}
341#define	TS(name, amode)		{TERM, amode, name, 1, 0, 0, 0, 0}
342#define	TSx(name, amode)	{TERM, amode, name, 1, 1, 0, 0, 0}
343#define	TSy(name, amode)	{TERM, amode, name, 1, 0, 1, 0, 0}
344#define	TSp(name, amode)	{TERM, amode, name, 1, 0, 0, 0, 1}
345#define	TSZ(name, amode, sz)	{TERM, amode, name, 1, 0, 0, 0, 0}
346#define	TSaZ(name, amode, sz)	{TERM, amode, name, 1, 0, 0, 0, 0, 0, AVS2}
347#define	TSq(name, amode)	{TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5Q}
348#define	TSZx(name, amode, sz)	{TERM, amode, name, 1, 1, 0, 0, 0}
349#define	TSZy(name, amode, sz)	{TERM, amode, name, 1, 0, 1, 0, 0}
350#define	INVALID			{TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
351#elif defined(DIS_MEM)
352#define	IND(table)		{(instable_t *)table, 0, 0, 0, 0, 0, 0}
353#define	INDx(table)		{(instable_t *)table, 0, 0, 1, 0, 0, 0}
354#define	TNS(name, amode)	{TERM, amode,  0, 0, 0, 0, 0}
355#define	TNSu(name, amode)	{TERM, amode,  0, 0, 0, 1, 0}
356#define	TNSy(name, amode)	{TERM, amode,  0, 0, 1, 0, 0}
357#define	TNSyp(name, amode)	{TERM, amode,  0, 0, 1, 0, 1}
358#define	TNSx(name, amode)	{TERM, amode,  0, 1, 0, 0, 0}
359#define	TNSZ(name, amode, sz)	{TERM, amode, sz, 0, 0, 0, 0}
360#define	TNSZy(name, amode, sz)	{TERM, amode, sz, 0, 1, 0, 0}
361#define	TNSZvr(name, amode, sz)	{TERM, amode, sz, 0, 0, 0, 0, 1}
362#define	TSvo(name, amode)	{TERM, amode,  0, 0, 0, 0, 0, 0, 0, 1}
363#define	TS(name, amode)		{TERM, amode,  0, 0, 0, 0, 0}
364#define	TSx(name, amode)	{TERM, amode,  0, 1, 0, 0, 0}
365#define	TSy(name, amode)	{TERM, amode,  0, 0, 1, 0, 0}
366#define	TSp(name, amode)	{TERM, amode,  0, 0, 0, 0, 1}
367#define	TSZ(name, amode, sz)	{TERM, amode, sz, 0, 0, 0, 0}
368#define	TSaZ(name, amode, sz)	{TERM, amode, sz, 0, 0, 0, 0, 0, AVS2}
369#define	TSq(name, amode)	{TERM, amode, 0, 0, 0, 0, 0, 0, AVS5Q}
370#define	TSZx(name, amode, sz)	{TERM, amode, sz, 1, 0, 0, 0}
371#define	TSZy(name, amode, sz)	{TERM, amode, sz, 0, 1, 0, 0}
372#define	INVALID			{TERM, UNKNOWN, 0, 0, 0, 0, 0}
373#else
374#define	IND(table)		{(instable_t *)table, 0, 0, 0, 0, 0}
375#define	INDx(table)		{(instable_t *)table, 0, 1, 0, 0, 0}
376#define	TNS(name, amode)	{TERM, amode,  0, 0, 0, 0}
377#define	TNSu(name, amode)	{TERM, amode,  0, 0, 1, 0}
378#define	TNSy(name, amode)	{TERM, amode,  0, 1, 0, 0}
379#define	TNSyp(name, amode)	{TERM, amode,  0, 1, 0, 1}
380#define	TNSx(name, amode)	{TERM, amode,  1, 0, 0, 0}
381#define	TNSZ(name, amode, sz)	{TERM, amode,  0, 0, 0, 0}
382#define	TNSZy(name, amode, sz)	{TERM, amode,  0, 1, 0, 0}
383#define	TNSZvr(name, amode, sz)	{TERM, amode,  0, 0, 0, 0, 1}
384#define	TSvo(name, amode)	{TERM, amode,  0, 0, 0, 0, 0, 0, 1}
385#define	TS(name, amode)		{TERM, amode,  0, 0, 0, 0}
386#define	TSx(name, amode)	{TERM, amode,  1, 0, 0, 0}
387#define	TSy(name, amode)	{TERM, amode,  0, 1, 0, 0}
388#define	TSp(name, amode)	{TERM, amode,  0, 0, 0, 1}
389#define	TSZ(name, amode, sz)	{TERM, amode,  0, 0, 0, 0}
390#define	TSaZ(name, amode, sz)	{TERM, amode,  0, 0, 0, 0, 0, AVS2}
391#define	TSq(name, amode)	{TERM, amode,  0, 0, 0, 0, 0, AVS5Q}
392#define	TSd(name, amode)	{TERM, amode,  0, 0, 0, 0, 0, AVS5D}
393#define	TSZx(name, amode, sz)	{TERM, amode,  1, 0, 0, 0}
394#define	TSZy(name, amode, sz)	{TERM, amode,  0, 1, 0, 0}
395#define	INVALID			{TERM, UNKNOWN, 0, 0, 0, 0}
396#endif
397
398#ifdef DIS_TEXT
399/*
400 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode
401 */
402const char *const dis_addr16[3][8] = {
403"(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "",
404									"(%bx)",
405"(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)",
406									"(%bx)",
407"(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)",
408									"(%bx)",
409};
410
411
412/*
413 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2
414 */
415const char *const dis_addr32_mode0[16] = {
416  "(%eax)", "(%ecx)", "(%edx)",  "(%ebx)",  "", "",        "(%esi)",  "(%edi)",
417  "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "",        "(%r14d)", "(%r15d)"
418};
419
420const char *const dis_addr32_mode12[16] = {
421  "(%eax)", "(%ecx)", "(%edx)",  "(%ebx)",  "", "(%ebp)",  "(%esi)",  "(%edi)",
422  "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)"
423};
424
425/*
426 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2
427 */
428const char *const dis_addr64_mode0[16] = {
429 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "",       "(%rip)", "(%rsi)", "(%rdi)",
430 "(%r8)",  "(%r9)",  "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)"
431};
432const char *const dis_addr64_mode12[16] = {
433 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "",       "(%rbp)", "(%rsi)", "(%rdi)",
434 "(%r8)",  "(%r9)",  "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)"
435};
436
437/*
438 * decode for scale from SIB byte
439 */
440const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" };
441
442/*
443 * decode for scale from VSIB byte, note that we always include the scale factor
444 * to match gas.
445 */
446const char *const dis_vscale_factor[4] = { ",1)", ",2)", ",4)", ",8)" };
447
448/*
449 * register decoding for normal references to registers (ie. not addressing)
450 */
451const char *const dis_REG8[16] = {
452	"%al",  "%cl",  "%dl",   "%bl",   "%ah",   "%ch",   "%dh",   "%bh",
453	"%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
454};
455
456const char *const dis_REG8_REX[16] = {
457	"%al",  "%cl",  "%dl",   "%bl",   "%spl",  "%bpl",  "%sil",  "%dil",
458	"%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
459};
460
461const char *const dis_REG16[16] = {
462	"%ax",  "%cx",  "%dx",   "%bx",   "%sp",   "%bp",   "%si",   "%di",
463	"%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
464};
465
466const char *const dis_REG32[16] = {
467	"%eax", "%ecx", "%edx",  "%ebx",  "%esp",  "%ebp",  "%esi",  "%edi",
468	"%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
469};
470
471const char *const dis_REG64[16] = {
472	"%rax", "%rcx", "%rdx",  "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
473	"%r8",  "%r9",  "%r10",  "%r11", "%r12", "%r13", "%r14", "%r15"
474};
475
476const char *const dis_DEBUGREG[16] = {
477	"%db0", "%db1", "%db2",  "%db3",  "%db4",  "%db5",  "%db6",  "%db7",
478	"%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15"
479};
480
481const char *const dis_CONTROLREG[16] = {
482    "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?",
483    "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?"
484};
485
486const char *const dis_TESTREG[16] = {
487	"%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7",
488	"%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7"
489};
490
491const char *const dis_MMREG[16] = {
492	"%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7",
493	"%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7"
494};
495
496const char *const dis_XMMREG[32] = {
497    "%xmm0", "%xmm1", "%xmm2", "%xmm3",
498    "%xmm4", "%xmm5", "%xmm6", "%xmm7",
499    "%xmm8", "%xmm9", "%xmm10", "%xmm11",
500    "%xmm12", "%xmm13", "%xmm14", "%xmm15",
501    "%xmm16", "%xmm17", "%xmm18", "%xmm19",
502    "%xmm20", "%xmm21", "%xmm22", "%xmm23",
503    "%xmm24", "%xmm25", "%xmm26", "%xmm27",
504    "%xmm28", "%xmm29", "%xmm30", "%xmm31",
505};
506
507const char *const dis_YMMREG[32] = {
508    "%ymm0", "%ymm1", "%ymm2", "%ymm3",
509    "%ymm4", "%ymm5", "%ymm6", "%ymm7",
510    "%ymm8", "%ymm9", "%ymm10", "%ymm11",
511    "%ymm12", "%ymm13", "%ymm14", "%ymm15",
512    "%ymm16", "%ymm17", "%ymm18", "%ymm19",
513    "%ymm20", "%ymm21", "%ymm22", "%ymm23",
514    "%ymm24", "%ymm25", "%ymm26", "%ymm27",
515    "%ymm28", "%ymm29", "%ymm30", "%ymm31",
516};
517
518const char *const dis_ZMMREG[32] = {
519    "%zmm0", "%zmm1", "%zmm2", "%zmm3",
520    "%zmm4", "%zmm5", "%zmm6", "%zmm7",
521    "%zmm8", "%zmm9", "%zmm10", "%zmm11",
522    "%zmm12", "%zmm13", "%zmm14", "%zmm15",
523    "%zmm16", "%zmm17", "%zmm18", "%zmm19",
524    "%zmm20", "%zmm21", "%zmm22", "%zmm23",
525    "%zmm24", "%zmm25", "%zmm26", "%zmm27",
526    "%zmm28", "%zmm29", "%zmm30", "%zmm31",
527};
528
529const char *const dis_KOPMASKREG[8] = {
530    "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
531};
532
533const char *const dis_SEGREG[16] = {
534	"%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>",
535	"%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>"
536};
537
538/*
539 * SIMD predicate suffixes
540 */
541const char *const dis_PREDSUFFIX[8] = {
542	"eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord"
543};
544
545const char *const dis_AVXvgrp7[3][8] = {
546	/*0	1	2		3		4		5	6		7*/
547/*71*/	{"",	"",	"vpsrlw",	"",		"vpsraw",	"",	"vpsllw",	""},
548/*72*/	{"",	"",	"vpsrld",	"",		"vpsrad",	"",	"vpslld",	""},
549/*73*/	{"",	"",	"vpsrlq",	"vpsrldq",	"",		"",	"vpsllq",	"vpslldq"}
550};
551
552#endif	/* DIS_TEXT */
553
554/*
555 *	"decode table" for 64 bit mode MOVSXD instruction (opcode 0x63)
556 */
557const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ);
558
559/*
560 *	"decode table" for pause and clflush instructions
561 */
562const instable_t dis_opPause = TNS("pause", NORM);
563
564/*
565 *	"decode table" for wbnoinvd instruction
566 */
567const instable_t dis_opWbnoinvd = TNS("wbnoinvd", NORM);
568
569/*
570 *	Decode table for 0x0F00 opcodes
571 */
572const instable_t dis_op0F00[8] = {
573
574/*  [0]  */	TNS("sldt",M),		TNS("str",M),		TNSy("lldt",M),		TNSy("ltr",M),
575/*  [4]  */	TNSZ("verr",M,2),	TNSZ("verw",M,2),	INVALID,		INVALID,
576};
577
578
579/*
580 *	Decode table for 0x0F01 opcodes
581 */
582const instable_t dis_op0F01[8] = {
583
584/*  [0]  */	TNSZ("sgdt",VMx,6),	TNSZ("sidt",MONITOR_MWAIT,6),	TNSZ("lgdt",XGETBV_XSETBV,6),	TNSZ("lidt",SVM,6),
585/*  [4]  */	TNSZ("smsw",M,2),	INVALID,		TNSZ("lmsw",M,2),	TNS("invlpg",SWAPGS_RDTSCP),
586};
587
588/*
589 *	Decode table for 0x0F18 opcodes -- SIMD prefetch
590 */
591const instable_t dis_op0F18[8] = {
592
593/*  [0]  */	TNS("prefetchnta",PREF),TNS("prefetcht0",PREF),	TNS("prefetcht1",PREF),	TNS("prefetcht2",PREF),
594/*  [4]  */	INVALID,		INVALID,		INVALID,		INVALID,
595};
596
597/*
598 *	Decode table for 0x0FAE opcodes -- SIMD state save/restore
599 */
600const instable_t dis_op0FAE[8] = {
601/*  [0]  */	TNSZ("fxsave",FSGS,512),TNSZ("fxrstor",FSGS,512),TNS("ldmxcsr",FSGS),	TNS("stmxcsr",FSGS),
602/*  [4]  */	TNSZ("xsave",M,512),	TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE),	TNS("sfence",XMMSFNC),
603};
604
605/*
606 *	Decode table for 0xF30FAE opcodes -- FSGSBASE
607 */
608const instable_t dis_opF30FAE[8] = {
609/*  [0]  */	TNSx("rdfsbase",FSGS),	TNSx("rdgsbase",FSGS),	TNSx("wrfsbase",FSGS),	TNSx("wrgsbase",FSGS),
610/*  [4]  */	INVALID,		INVALID,		INVALID,		INVALID,
611};
612
613/*
614 *	Decode table for 0x0FBA opcodes
615 */
616
617const instable_t dis_op0FBA[8] = {
618
619/*  [0]  */	INVALID,		INVALID,		INVALID,		INVALID,
620/*  [4]  */	TS("bt",MIb),		TS("bts",MIb),		TS("btr",MIb),		TS("btc",MIb),
621};
622
623/*
624 *	Decode table for 0x0FC7 opcode (group 9)
625 */
626
627const instable_t dis_op0FC7[8] = {
628
629/*  [0]  */	INVALID,		TNS("cmpxchg8b",M),	INVALID,		TNS("xrstors",MG9),
630/*  [4]  */	TNS("xsavec",MG9),	TNS("xsaves",MG9),		TNS("vmptrld",MG9),	TNS("vmptrst",MG9),
631};
632
633/*
634 *	Decode table for 0x0FC7 opcode (group 9) mode 3
635 */
636
637const instable_t dis_op0FC7m3[8] = {
638
639/*  [0]  */	INVALID,		INVALID,	INVALID,		INVALID,
640/*  [4]  */	INVALID,		INVALID,	TNS("rdrand",MG9),	TNS("rdseed", MG9),
641};
642
643/*
644 *	Decode table for 0x0FC7 opcode with 0x66 prefix
645 */
646
647const instable_t dis_op660FC7[8] = {
648
649/*  [0]  */	INVALID,		INVALID,		INVALID,		INVALID,
650/*  [4]  */	INVALID,		INVALID,		TNS("vmclear",M),	INVALID,
651};
652
653/*
654 *	Decode table for 0x0FC7 opcode with 0xF3 prefix
655 */
656
657const instable_t dis_opF30FC7[8] = {
658
659/*  [0]  */	INVALID,		INVALID,		INVALID,		INVALID,
660/*  [4]  */	INVALID,		INVALID,		TNS("vmxon",M),		INVALID,
661};
662
663/*
664 *	Decode table for 0x0FC8 opcode -- 486 bswap instruction
665 *
666 *bit pattern: 0000 1111 1100 1reg
667 */
668const instable_t dis_op0FC8[4] = {
669/*  [0]  */	TNS("bswap",R),		INVALID,		INVALID,		INVALID,
670};
671
672/*
673 *	Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions
674 */
675const instable_t dis_op0F7123[4][8] = {
676{
677/*  [70].0 */	INVALID,		INVALID,		INVALID,		INVALID,
678/*      .4 */	INVALID,		INVALID,		INVALID,		INVALID,
679}, {
680/*  [71].0 */	INVALID,		INVALID,		TNS("psrlw",MMOSH),	INVALID,
681/*      .4 */	TNS("psraw",MMOSH),	INVALID,		TNS("psllw",MMOSH),	INVALID,
682}, {
683/*  [72].0 */	INVALID,		INVALID,		TNS("psrld",MMOSH),	INVALID,
684/*      .4 */	TNS("psrad",MMOSH),	INVALID,		TNS("pslld",MMOSH),	INVALID,
685}, {
686/*  [73].0 */	INVALID,		INVALID,		TNS("psrlq",MMOSH),	TNS("INVALID",MMOSH),
687/*      .4 */	INVALID,		INVALID,		TNS("psllq",MMOSH),	TNS("INVALID",MMOSH),
688} };
689
690/*
691 *	Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes.
692 */
693const instable_t dis_opSIMD7123[32] = {
694/* [70].0 */	INVALID,		INVALID,		INVALID,		INVALID,
695/*     .4 */	INVALID,		INVALID,		INVALID,		INVALID,
696
697/* [71].0 */	INVALID,		INVALID,		TNS("psrlw",XMMSH),	INVALID,
698/*     .4 */	TNS("psraw",XMMSH),	INVALID,		TNS("psllw",XMMSH),	INVALID,
699
700/* [72].0 */	INVALID,		INVALID,		TNS("psrld",XMMSH),	INVALID,
701/*     .4 */	TNS("psrad",XMMSH),	INVALID,		TNS("pslld",XMMSH),	INVALID,
702
703/* [73].0 */	INVALID,		INVALID,		TNS("psrlq",XMMSH),	TNS("psrldq",XMMSH),
704/*     .4 */	INVALID,		INVALID,		TNS("psllq",XMMSH),	TNS("pslldq",XMMSH),
705};
706
707/*
708 *	SIMD instructions have been wedged into the existing IA32 instruction
709 *	set through the use of prefixes.  That is, while 0xf0 0x58 may be
710 *	addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different
711 *	instruction - addss.  At present, three prefixes have been coopted in
712 *	this manner - address size (0x66), repnz (0xf2) and repz (0xf3).  The
713 *	following tables are used to provide the prefixed instruction names.
714 *	The arrays are sparse, but they're fast.
715 */
716
717/*
718 *	Decode table for SIMD instructions with the address size (0x66) prefix.
719 */
720const instable_t dis_opSIMDdata16[256] = {
721/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
722/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
723/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
724/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
725
726/*  [10]  */	TNSZ("movupd",XMM,16),	TNSZ("movupd",XMMS,16),	TNSZ("movlpd",XMMM,8),	TNSZ("movlpd",XMMMS,8),
727/*  [14]  */	TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8),	TNSZ("movhpd",XMMMS,8),
728/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
729/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
730
731/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
732/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
733/*  [28]  */	TNSZ("movapd",XMM,16),	TNSZ("movapd",XMMS,16),	TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16),
734/*  [2C]  */	TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8),
735
736/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
737/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
738/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
739/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
740
741/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
742/*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
743/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
744/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
745
746/*  [50]  */	TNS("movmskpd",XMMOX3),	TNSZ("sqrtpd",XMM,16),	INVALID,		INVALID,
747/*  [54]  */	TNSZ("andpd",XMM,16),	TNSZ("andnpd",XMM,16),	TNSZ("orpd",XMM,16),	TNSZ("xorpd",XMM,16),
748/*  [58]  */	TNSZ("addpd",XMM,16),	TNSZ("mulpd",XMM,16),	TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16),
749/*  [5C]  */	TNSZ("subpd",XMM,16),	TNSZ("minpd",XMM,16),	TNSZ("divpd",XMM,16),	TNSZ("maxpd",XMM,16),
750
751/*  [60]  */	TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16),
752/*  [64]  */	TNSZ("pcmpgtb",XMM,16),	TNSZ("pcmpgtw",XMM,16),	TNSZ("pcmpgtd",XMM,16),	TNSZ("packuswb",XMM,16),
753/*  [68]  */	TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16),
754/*  [6C]  */	TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16),
755
756/*  [70]  */	TNSZ("pshufd",XMMP,16),	INVALID,		INVALID,		INVALID,
757/*  [74]  */	TNSZ("pcmpeqb",XMM,16),	TNSZ("pcmpeqw",XMM,16),	TNSZ("pcmpeqd",XMM,16),	INVALID,
758/*  [78]  */	TNSZ("extrq",XMM2I,16),	TNSZ("extrq",XMM,16), INVALID,		INVALID,
759/*  [7C]  */	TNSZ("haddpd",XMM,16),	TNSZ("hsubpd",XMM,16),	TNSZ("movd",XMM3MXS,4),	TNSZ("movdqa",XMMS,16),
760
761/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
762/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
763/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
764/*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
765
766/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
767/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
768/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
769/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
770
771/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
772/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
773/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
774/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
775
776/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
777/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
778/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
779/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
780
781/*  [C0]  */	INVALID,		INVALID,		TNSZ("cmppd",XMMP,16),	INVALID,
782/*  [C4]  */	TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P),	TNSZ("shufpd",XMMP,16),	INVALID,
783/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
784/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
785
786/*  [D0]  */	TNSZ("addsubpd",XMM,16),TNSZ("psrlw",XMM,16),	TNSZ("psrld",XMM,16),	TNSZ("psrlq",XMM,16),
787/*  [D4]  */	TNSZ("paddq",XMM,16),	TNSZ("pmullw",XMM,16),	TNSZ("movq",XMMS,8),	TNS("pmovmskb",XMMX3),
788/*  [D8]  */	TNSZ("psubusb",XMM,16),	TNSZ("psubusw",XMM,16),	TNSZ("pminub",XMM,16),	TNSZ("pand",XMM,16),
789/*  [DC]  */	TNSZ("paddusb",XMM,16),	TNSZ("paddusw",XMM,16),	TNSZ("pmaxub",XMM,16),	TNSZ("pandn",XMM,16),
790
791/*  [E0]  */	TNSZ("pavgb",XMM,16),	TNSZ("psraw",XMM,16),	TNSZ("psrad",XMM,16),	TNSZ("pavgw",XMM,16),
792/*  [E4]  */	TNSZ("pmulhuw",XMM,16),	TNSZ("pmulhw",XMM,16),	TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16),
793/*  [E8]  */	TNSZ("psubsb",XMM,16),	TNSZ("psubsw",XMM,16),	TNSZ("pminsw",XMM,16),	TNSZ("por",XMM,16),
794/*  [EC]  */	TNSZ("paddsb",XMM,16),	TNSZ("paddsw",XMM,16),	TNSZ("pmaxsw",XMM,16),	TNSZ("pxor",XMM,16),
795
796/*  [F0]  */	INVALID,		TNSZ("psllw",XMM,16),	TNSZ("pslld",XMM,16),	TNSZ("psllq",XMM,16),
797/*  [F4]  */	TNSZ("pmuludq",XMM,16),	TNSZ("pmaddwd",XMM,16),	TNSZ("psadbw",XMM,16),	TNSZ("maskmovdqu", XMMXIMPL,16),
798/*  [F8]  */	TNSZ("psubb",XMM,16),	TNSZ("psubw",XMM,16),	TNSZ("psubd",XMM,16),	TNSZ("psubq",XMM,16),
799/*  [FC]  */	TNSZ("paddb",XMM,16),	TNSZ("paddw",XMM,16),	TNSZ("paddd",XMM,16),	INVALID,
800};
801
802const instable_t dis_opAVX660F[256] = {
803/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
804/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
805/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
806/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
807
808/*  [10]  */	TNSZ("vmovupd",VEX_MX,16),	TNSZ("vmovupd",VEX_RX,16),	TNSZ("vmovlpd",VEX_RMrX,8),	TNSZ("vmovlpd",VEX_RM,8),
809/*  [14]  */	TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8),	TNSZ("vmovhpd",VEX_RM,8),
810/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
811/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
812
813/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
814/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
815/*  [28]  */	TNSZ("vmovapd",VEX_MX,16),	TNSZ("vmovapd",VEX_RX,16),	INVALID,		TNSZ("vmovntpd",VEX_RM,16),
816/*  [2C]  */	INVALID,		INVALID,		TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8),
817
818/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
819/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
820/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
821/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
822
823/*  [40]  */	INVALID,		TSvo("kand",VEX_RMX),	TSvo("kandn",VEX_RMX),		INVALID,
824/*  [44]  */	TSvo("knot",VEX_MX),	TSvo("kor",VEX_RMX),	TSvo("kxnor",VEX_RMX),		TSvo("kxor",VEX_RMX),
825/*  [48]  */	INVALID,		INVALID,		TSvo("kadd",VEX_RMX),		TSvo("kunpck",VEX_RMX),
826/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
827
828/*  [50]  */	TNS("vmovmskpd",VEX_MR),	TNSZ("vsqrtpd",VEX_MX,16),	INVALID,		INVALID,
829/*  [54]  */	TNSZ("vandpd",VEX_RMrX,16),	TNSZ("vandnpd",VEX_RMrX,16),	TNSZ("vorpd",VEX_RMrX,16),	TNSZ("vxorpd",VEX_RMrX,16),
830/*  [58]  */	TNSZ("vaddpd",VEX_RMrX,16),	TNSZ("vmulpd",VEX_RMrX,16),	TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16),
831/*  [5C]  */	TNSZ("vsubpd",VEX_RMrX,16),	TNSZ("vminpd",VEX_RMrX,16),	TNSZ("vdivpd",VEX_RMrX,16),	TNSZ("vmaxpd",VEX_RMrX,16),
832
833/*  [60]  */	TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16),
834/*  [64]  */	TNSZ("vpcmpgtb",VEX_RMrX,16),	TNSZ("vpcmpgtw",VEX_RMrX,16),	TNSZ("vpcmpgtd",VEX_RMrX,16),	TNSZ("vpackuswb",VEX_RMrX,16),
835/*  [68]  */	TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16),
836/*  [6C]  */	TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16),
837
838/*  [70]  */	TNSZ("vpshufd",VEX_MXI,16),	TNSZ("vgrp71",VEX_XXI,16),	TNSZ("vgrp72",VEX_XXI,16),		TNSZ("vgrp73",VEX_XXI,16),
839/*  [74]  */	TNSZ("vpcmpeqb",VEX_RMrX,16),	TNSZ("vpcmpeqw",VEX_RMrX,16),	TNSZ("vpcmpeqd",VEX_RMrX,16),	INVALID,
840/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
841/*  [7C]  */	TNSZ("vhaddpd",VEX_RMrX,16),	TNSZ("vhsubpd",VEX_RMrX,16),	TNSZ("vmovd",VEX_RR,4),	TNSZ("vmovdqa",VEX_RX,16),
842
843/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
844/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
845/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
846/*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
847
848/*  [90]  */	TSvo("kmov",VEX_KRM),	TSvo("kmov",VEX_KMR),	TSvo("kmov",VEX_KRR),		TSvo("kmov",VEX_MR),
849/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
850/*  [98]  */	TSvo("kortest",VEX_MX),	TSvo("ktest",VEX_MX),	INVALID,		INVALID,
851/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
852
853/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
854/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
855/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
856/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
857
858/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
859/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
860/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
861/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
862
863/*  [C0]  */	INVALID,		INVALID,		TNSZ("vcmppd",VEX_RMRX,16),	INVALID,
864/*  [C4]  */	TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR),	TNSZ("vshufpd",VEX_RMRX,16),	INVALID,
865/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
866/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
867
868/*  [D0]  */	TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16),	TNSZ("vpsrld",VEX_RMrX,16),	TNSZ("vpsrlq",VEX_RMrX,16),
869/*  [D4]  */	TNSZ("vpaddq",VEX_RMrX,16),	TNSZ("vpmullw",VEX_RMrX,16),	TNSZ("vmovq",VEX_RX,8),	TNS("vpmovmskb",VEX_MR),
870/*  [D8]  */	TNSZ("vpsubusb",VEX_RMrX,16),	TNSZ("vpsubusw",VEX_RMrX,16),	TNSZ("vpminub",VEX_RMrX,16),	TNSZ("vpand",VEX_RMrX,16),
871/*  [DC]  */	TNSZ("vpaddusb",VEX_RMrX,16),	TNSZ("vpaddusw",VEX_RMrX,16),	TNSZ("vpmaxub",VEX_RMrX,16),	TNSZ("vpandn",VEX_RMrX,16),
872
873/*  [E0]  */	TNSZ("vpavgb",VEX_RMrX,16),	TNSZ("vpsraw",VEX_RMrX,16),	TNSZ("vpsrad",VEX_RMrX,16),	TNSZ("vpavgw",VEX_RMrX,16),
874/*  [E4]  */	TNSZ("vpmulhuw",VEX_RMrX,16),	TNSZ("vpmulhw",VEX_RMrX,16),	TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16),
875/*  [E8]  */	TNSZ("vpsubsb",VEX_RMrX,16),	TNSZ("vpsubsw",VEX_RMrX,16),	TNSZ("vpminsw",VEX_RMrX,16),	TNSZ("vpor",VEX_RMrX,16),
876/*  [EC]  */	TNSZ("vpaddsb",VEX_RMrX,16),	TNSZ("vpaddsw",VEX_RMrX,16),	TNSZ("vpmaxsw",VEX_RMrX,16),	TNSZ("vpxor",VEX_RMrX,16),
877
878/*  [F0]  */	INVALID,		TNSZ("vpsllw",VEX_RMrX,16),	TNSZ("vpslld",VEX_RMrX,16),	TNSZ("vpsllq",VEX_RMrX,16),
879/*  [F4]  */	TNSZ("vpmuludq",VEX_RMrX,16),	TNSZ("vpmaddwd",VEX_RMrX,16),	TNSZ("vpsadbw",VEX_RMrX,16),	TNS("vmaskmovdqu",VEX_MX),
880/*  [F8]  */	TNSZ("vpsubb",VEX_RMrX,16),	TNSZ("vpsubw",VEX_RMrX,16),	TNSZ("vpsubd",VEX_RMrX,16),	TNSZ("vpsubq",VEX_RMrX,16),
881/*  [FC]  */	TNSZ("vpaddb",VEX_RMrX,16),	TNSZ("vpaddw",VEX_RMrX,16),	TNSZ("vpaddd",VEX_RMrX,16),	INVALID,
882};
883
884/*
885 *	Decode table for SIMD instructions with the repnz (0xf2) prefix.
886 */
887const instable_t dis_opSIMDrepnz[256] = {
888/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
889/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
890/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
891/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
892
893/*  [10]  */	TNSZ("movsd",XMM,8),	TNSZ("movsd",XMMS,8),	TNSZ("movddup",XMM,8),	INVALID,
894/*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
895/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
896/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
897
898/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
899/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
900/*  [28]  */	INVALID,		INVALID,		TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8),
901/*  [2C]  */	TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID,		INVALID,
902
903/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
904/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
905/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
906/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
907
908/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
909/*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
910/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
911/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
912
913/*  [50]  */	INVALID,		TNSZ("sqrtsd",XMM,8),	INVALID,		INVALID,
914/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
915/*  [58]  */	TNSZ("addsd",XMM,8),	TNSZ("mulsd",XMM,8),	TNSZ("cvtsd2ss",XMM,8),	INVALID,
916/*  [5C]  */	TNSZ("subsd",XMM,8),	TNSZ("minsd",XMM,8),	TNSZ("divsd",XMM,8),	TNSZ("maxsd",XMM,8),
917
918/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
919/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
920/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
921/*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
922
923/*  [70]  */	TNSZ("pshuflw",XMMP,16),INVALID,		INVALID,		INVALID,
924/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
925/*  [78]  */	TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID,		INVALID,
926/*  [7C]  */	TNSZ("haddps",XMM,16),	TNSZ("hsubps",XMM,16),	INVALID,		INVALID,
927
928/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
929/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
930/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
931/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
932
933/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
934/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
935/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
936/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
937
938/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
939/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
940/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
941/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
942
943/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
944/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
945/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
946/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
947
948/*  [C0]  */	INVALID,		INVALID,		TNSZ("cmpsd",XMMP,8),	INVALID,
949/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
950/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
951/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
952
953/*  [D0]  */	TNSZ("addsubps",XMM,16),INVALID,		INVALID,		INVALID,
954/*  [D4]  */	INVALID,		INVALID,		TNS("movdq2q",XMMXM),	INVALID,
955/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
956/*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
957
958/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
959/*  [E4]  */	INVALID,		INVALID,		TNSZ("cvtpd2dq",XMM,16),INVALID,
960/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
961/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
962
963/*  [F0]  */	TNS("lddqu",XMMM),	INVALID,		INVALID,		INVALID,
964/*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
965/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
966/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
967};
968
969const instable_t dis_opAVXF20F[256] = {
970/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
971/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
972/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
973/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
974
975/*  [10]  */	TNSZ("vmovsd",VEX_RMrX,8),	TNSZ("vmovsd",VEX_RRX,8),	TNSZ("vmovddup",VEX_MX,8),	INVALID,
976/*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
977/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
978/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
979
980/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
981/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
982/*  [28]  */	INVALID,		INVALID,		TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID,
983/*  [2C]  */	TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID,		INVALID,
984
985/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
986/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
987/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
988/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
989
990/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
991/*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
992/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
993/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
994
995/*  [50]  */	INVALID,		TNSZ("vsqrtsd",VEX_RMrX,8),	INVALID,		INVALID,
996/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
997/*  [58]  */	TNSZ("vaddsd",VEX_RMrX,8),	TNSZ("vmulsd",VEX_RMrX,8),	TNSZ("vcvtsd2ss",VEX_RMrX,8),	INVALID,
998/*  [5C]  */	TNSZ("vsubsd",VEX_RMrX,8),	TNSZ("vminsd",VEX_RMrX,8),	TNSZ("vdivsd",VEX_RMrX,8),	TNSZ("vmaxsd",VEX_RMrX,8),
999
1000/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1001/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1002/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1003/*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1004
1005/*  [70]  */	TNSZ("vpshuflw",VEX_MXI,16),INVALID,		INVALID,		INVALID,
1006/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1007/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1008/*  [7C]  */	TNSZ("vhaddps",VEX_RMrX,8),	TNSZ("vhsubps",VEX_RMrX,8),	INVALID,		INVALID,
1009
1010/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1011/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1012/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1013/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1014
1015/*  [90]  */	INVALID,		INVALID,		TSvo("kmov",VEX_KRR),		TSvo("kmov",VEX_MR),
1016/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1017/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1018/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1019
1020/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1021/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1022/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1023/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1024
1025/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1026/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1027/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1028/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1029
1030/*  [C0]  */	INVALID,		INVALID,		TNSZ("vcmpsd",VEX_RMRX,8),	INVALID,
1031/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1032/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1033/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1034
1035/*  [D0]  */	TNSZ("vaddsubps",VEX_RMrX,8),	INVALID,		INVALID,		INVALID,
1036/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1037/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1038/*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1039
1040/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1041/*  [E4]  */	INVALID,		INVALID,		TNSZ("vcvtpd2dq",VEX_MX,16),INVALID,
1042/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1043/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1044
1045/*  [F0]  */	TNSZ("vlddqu",VEX_MX,16),	INVALID,		INVALID,		INVALID,
1046/*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1047/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1048/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1049};
1050
1051const instable_t dis_opAVXF20F3A[256] = {
1052/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1053/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1054/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1055/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1056
1057/*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
1058/*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1059/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1060/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1061
1062/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1063/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1064/*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
1065/*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1066
1067/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1068/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1069/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1070/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1071
1072/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1073/*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1074/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1075/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1076
1077/*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1078/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1079/*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1080/*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1081
1082/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1083/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1084/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1085/*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1086
1087/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1088/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1089/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1090/*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1091
1092/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1093/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1094/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1095/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1096
1097/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1098/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1099/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1100/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1101
1102/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1103/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1104/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1105/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1106
1107/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1108/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1109/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1110/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1111
1112/*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1113/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1114/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1115/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1116
1117/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1118/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1119/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1120/*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1121
1122/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1123/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1124/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1125/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1126
1127/*  [F0]  */	TNSZvr("rorx",VEX_MXI,6),INVALID,		INVALID,		INVALID,
1128/*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1129/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1130/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1131};
1132
1133const instable_t dis_opAVXF20F38[256] = {
1134/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1135/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1136/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1137/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1138
1139/*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
1140/*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1141/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1142/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1143
1144/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1145/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1146/*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
1147/*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1148
1149/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1150/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1151/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1152/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1153
1154/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1155/*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1156/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1157/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1158
1159/*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1160/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1161/*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1162/*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1163
1164/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1165/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1166/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1167/*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1168
1169/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1170/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1171/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1172/*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1173
1174/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1175/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1176/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1177/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1178
1179/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1180/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1181/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1182/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1183
1184/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1185/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1186/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1187/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1188
1189/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1190/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1191/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1192/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1193
1194/*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1195/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1196/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1197/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1198
1199/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1200/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1201/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1202/*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1203
1204/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1205/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1206/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1207/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1208
1209/*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1210/*  [F4]  */	INVALID,		TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5),
1211/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1212/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1213};
1214
1215const instable_t dis_opAVXF30F38[256] = {
1216/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1217/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1218/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1219/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1220
1221/*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
1222/*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1223/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1224/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1225
1226/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1227/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1228/*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
1229/*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1230
1231/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1232/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1233/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1234/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1235
1236/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1237/*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1238/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1239/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1240
1241/*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1242/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1243/*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1244/*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1245
1246/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1247/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1248/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1249/*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1250
1251/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1252/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1253/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1254/*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1255
1256/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1257/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1258/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1259/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1260
1261/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1262/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1263/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1264/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1265
1266/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1267/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1268/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1269/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1270
1271/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1272/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1273/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1274/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1275
1276/*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1277/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1278/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1279/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1280
1281/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1282/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1283/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1284/*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1285
1286/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1287/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1288/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1289/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1290
1291/*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1292/*  [F4]  */	INVALID,		TNSZvr("pext",VEX_RMrX,5),INVALID,		TNSZvr("sarx",VEX_VRMrX,5),
1293/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1294/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1295};
1296/*
1297 *	Decode table for SIMD instructions with the repz (0xf3) prefix.
1298 */
1299const instable_t dis_opSIMDrepz[256] = {
1300/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1301/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1302/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1303/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1304
1305/*  [10]  */	TNSZ("movss",XMM,4),	TNSZ("movss",XMMS,4),	TNSZ("movsldup",XMM,16),INVALID,
1306/*  [14]  */	INVALID,		INVALID,		TNSZ("movshdup",XMM,16),INVALID,
1307/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1308/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1309
1310/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1311/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1312/*  [28]  */	INVALID,		INVALID,		TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4),
1313/*  [2C]  */	TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID,		INVALID,
1314
1315/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1316/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1317/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1318/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1319
1320/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1321/*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1322/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1323/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1324
1325/*  [50]  */	INVALID,		TNSZ("sqrtss",XMM,4),	TNSZ("rsqrtss",XMM,4),	TNSZ("rcpss",XMM,4),
1326/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1327/*  [58]  */	TNSZ("addss",XMM,4),	TNSZ("mulss",XMM,4),	TNSZ("cvtss2sd",XMM,4),	TNSZ("cvttps2dq",XMM,16),
1328/*  [5C]  */	TNSZ("subss",XMM,4),	TNSZ("minss",XMM,4),	TNSZ("divss",XMM,4),	TNSZ("maxss",XMM,4),
1329
1330/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1331/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1332/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1333/*  [6C]  */	INVALID,		INVALID,		INVALID,		TNSZ("movdqu",XMM,16),
1334
1335/*  [70]  */	TNSZ("pshufhw",XMMP,16),INVALID,		INVALID,		INVALID,
1336/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1337/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1338/*  [7C]  */	INVALID,		INVALID,		TNSZ("movq",XMM,8),	TNSZ("movdqu",XMMS,16),
1339
1340/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1341/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1342/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1343/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1344
1345/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1346/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1347/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1348/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1349
1350/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1351/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1352/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1353/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1354
1355/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1356/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1357/*  [B8]  */	TS("popcnt",MRw),	INVALID,		INVALID,		INVALID,
1358/*  [BC]  */	TNSZ("tzcnt",MRw,5),	TS("lzcnt",MRw),	INVALID,		INVALID,
1359
1360/*  [C0]  */	INVALID,		INVALID,		TNSZ("cmpss",XMMP,4),	INVALID,
1361/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1362/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1363/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1364
1365/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1366/*  [D4]  */	INVALID,		INVALID,		TNS("movq2dq",XMMMX),	INVALID,
1367/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1368/*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1369
1370/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1371/*  [E4]  */	INVALID,		INVALID,		TNSZ("cvtdq2pd",XMM,8),	INVALID,
1372/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1373/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1374
1375/*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1376/*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1377/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1378/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1379};
1380
1381const instable_t dis_opAVXF30F[256] = {
1382/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1383/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1384/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1385/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1386
1387/*  [10]  */	TNSZ("vmovss",VEX_RMrX,4),	TNSZ("vmovss",VEX_RRX,4),	TNSZ("vmovsldup",VEX_MX,4),	INVALID,
1388/*  [14]  */	INVALID,		INVALID,		TNSZ("vmovshdup",VEX_MX,4),	INVALID,
1389/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1390/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1391
1392/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1393/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1394/*  [28]  */	INVALID,		INVALID,		TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID,
1395/*  [2C]  */	TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID,		INVALID,
1396
1397/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1398/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1399/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1400/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1401
1402/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1403/*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1404/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1405/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1406
1407/*  [50]  */	INVALID,		TNSZ("vsqrtss",VEX_RMrX,4),	TNSZ("vrsqrtss",VEX_RMrX,4),	TNSZ("vrcpss",VEX_RMrX,4),
1408/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1409/*  [58]  */	TNSZ("vaddss",VEX_RMrX,4),	TNSZ("vmulss",VEX_RMrX,4),	TNSZ("vcvtss2sd",VEX_RMrX,4),	TNSZ("vcvttps2dq",VEX_MX,16),
1410/*  [5C]  */	TNSZ("vsubss",VEX_RMrX,4),	TNSZ("vminss",VEX_RMrX,4),	TNSZ("vdivss",VEX_RMrX,4),	TNSZ("vmaxss",VEX_RMrX,4),
1411
1412/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1413/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1414/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1415/*  [6C]  */	INVALID,		INVALID,		INVALID,		TNSZ("vmovdqu",VEX_MX,16),
1416
1417/*  [70]  */	TNSZ("vpshufhw",VEX_MXI,16),INVALID,		INVALID,		INVALID,
1418/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1419/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1420/*  [7C]  */	INVALID,		INVALID,		TNSZ("vmovq",VEX_MX,8),	TNSZ("vmovdqu",VEX_RX,16),
1421
1422/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1423/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1424/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1425/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1426
1427/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1428/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1429/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1430/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1431
1432/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1433/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1434/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1435/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1436
1437/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1438/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1439/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1440/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1441
1442/*  [C0]  */	INVALID,		INVALID,		TNSZ("vcmpss",VEX_RMRX,4),	INVALID,
1443/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1444/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1445/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1446
1447/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1448/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1449/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1450/*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1451
1452/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1453/*  [E4]  */	INVALID,		INVALID,		TNSZ("vcvtdq2pd",VEX_MX,8),	INVALID,
1454/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1455/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1456
1457/*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1458/*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1459/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1460/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1461};
1462
1463/*
1464 * Table for instructions with an EVEX prefix followed by 0F.
1465 */
1466const instable_t dis_opEVEX0F[256] = {
1467/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1468/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1469/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1470/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1471
1472/*  [10]  */	TNS("vmovups",EVEX_MX),	TNS("vmovups",EVEX_RX),	INVALID,		INVALID,
1473/*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1474/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1475/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1476
1477/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1478/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1479/*  [28]  */	TNS("vmovaps",EVEX_MX),	TNS("vmovaps",EVEX_RX),	INVALID,		INVALID,
1480/*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1481
1482/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1483/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1484/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1485/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1486
1487/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1488/*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1489/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1490/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1491
1492/*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1493/*  [54]  */	TNS("vandps",EVEX_RMrX),TNS("vandnps",EVEX_RMrX),TNS("vorps",EVEX_RMrX),TNS("vxorps",EVEX_RMrX),
1494/*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1495/*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1496
1497/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1498/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1499/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1500/*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1501
1502/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1503/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1504/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1505/*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1506
1507/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1508/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1509/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1510/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1511
1512/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1513/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1514/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1515/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1516
1517/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1518/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1519/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1520/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1521
1522/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1523/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1524/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1525/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1526
1527/*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1528/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1529/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1530/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1531
1532/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1533/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1534/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1535/*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1536
1537/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1538/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1539/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1540/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1541
1542/*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1543/*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1544/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1545/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1546};
1547
1548/*
1549 * Decode tables for EVEX 66 0F
1550 */
1551const instable_t dis_opEVEX660F[256] = {
1552/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1553/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1554/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1555/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1556
1557/*  [10]  */	TNS("vmovupd",EVEX_MX),	TNS("vmovupd",EVEX_RX),	INVALID,		INVALID,
1558/*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1559/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1560/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1561
1562/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1563/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1564/*  [28]  */	TNS("vmovapd",EVEX_MX),	TNS("vmovapd",EVEX_RX),	INVALID,		INVALID,
1565/*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1566
1567/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1568/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1569/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1570/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1571
1572/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1573/*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1574/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1575/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1576
1577/*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1578/*  [54]  */	TNS("vandpd",EVEX_RMrX),TNS("vandnpd",EVEX_RMrX),TNS("vorpd",EVEX_RMrX),TNS("vxorpd",EVEX_RMrX),
1579/*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1580/*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1581
1582/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1583/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1584/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1585/*  [6C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdqa",EVEX_MX),
1586
1587/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1588/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1589/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1590/*  [7C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdqa",EVEX_RX),
1591
1592/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1593/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1594/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1595/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1596
1597/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1598/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1599/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1600/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1601
1602/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1603/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1604/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1605/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1606
1607/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1608/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1609/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1610/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1611
1612/*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1613/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1614/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1615/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1616
1617/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1618/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1619/*  [D8]  */	INVALID,		INVALID,		INVALID,		TSq("vpand",EVEX_RMrX),
1620/*  [DC]  */	INVALID,		INVALID,		INVALID,		TSq("vpandn",EVEX_RMrX),
1621
1622/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1623/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1624/*  [E8]  */	INVALID,		INVALID,		INVALID,		TSq("vpor",EVEX_RMrX),
1625/*  [EC]  */	INVALID,		INVALID,		INVALID,		TSq("vpxor",EVEX_RMrX),
1626
1627/*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1628/*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1629/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1630/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1631};
1632
1633const instable_t dis_opEVEX660F38[256] = {
1634/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1635/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1636/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1637/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1638
1639/*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
1640/*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1641/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1642/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1643
1644/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1645/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1646/*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
1647/*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1648
1649/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1650/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1651/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1652/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1653
1654/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1655/*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1656/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1657/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1658
1659/*  [50]  */	TNSZ("vpdpbusd",EVEX_RMrX,16),TNSZ("vpdpbusds",EVEX_RMrX,16),TNSZ("vpdpwssd",EVEX_RMrX,16),TNSZ("vpdpwssds",EVEX_RMrX,16),
1660/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1661/*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1662/*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1663
1664/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1665/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1666/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1667/*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1668
1669/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1670/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1671/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1672/*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1673
1674/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1675/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1676/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1677/*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1678
1679/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1680/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1681/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1682/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1683
1684/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1685/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1686/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1687/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1688
1689/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1690/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1691/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1692/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1693
1694/*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1695/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1696/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1697/*  [CC]  */	INVALID,		INVALID,		INVALID,		TNS("vgf2p8mulb",EVEX_RMrX),
1698
1699/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1700/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1701/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1702/*  [DC]  */	TNSZ("vaesenc",EVEX_RMrX,16),TNSZ("vaesenclast",EVEX_RMrX,16),TNSZ("vaesdec",EVEX_RMrX,16),TNSZ("vaesdeclast",EVEX_RMrX,16),
1703
1704/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1705/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1706/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1707/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1708
1709/*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1710/*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1711/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1712/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1713};
1714
1715const instable_t dis_opEVEX660F3A[256] = {
1716/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1717/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1718/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1719/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1720
1721/*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
1722/*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1723/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1724/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1725
1726/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1727/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1728/*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
1729/*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1730
1731/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1732/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1733/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1734/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1735
1736/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1737/*  [44]  */	TNSZ("vpclmulqdq",EVEX_RMRX,16),INVALID,		INVALID,		INVALID,
1738/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1739/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1740
1741/*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1742/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1743/*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1744/*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1745
1746/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1747/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1748/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1749/*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1750
1751/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1752/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1753/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1754/*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1755
1756/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1757/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1758/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1759/*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1760
1761/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1762/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1763/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1764/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1765
1766/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1767/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1768/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1769/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1770
1771/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1772/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1773/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1774/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1775
1776/*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1777/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1778/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1779/*  [CC]  */	INVALID,		INVALID,		TNS("vgf2p8affineqb",EVEX_RMRX),TNS("vgf2p8affineinvqb",EVEX_RMRX),
1780
1781/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1782/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1783/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1784/*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1785
1786/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1787/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1788/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1789/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1790
1791/*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1792/*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1793/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1794/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1795};
1796
1797
1798const instable_t dis_opEVEXF20F[256] = {
1799/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1800/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1801/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1802/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1803
1804/*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
1805/*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1806/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1807/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1808
1809/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1810/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1811/*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
1812/*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1813
1814/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1815/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1816/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1817/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1818
1819/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1820/*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1821/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1822/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1823
1824/*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1825/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1826/*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1827/*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1828
1829/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1830/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1831/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1832/*  [6C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdqu",EVEX_MX),
1833
1834/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1835/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1836/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1837/*  [7C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdqu",EVEX_RX),
1838
1839/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1840/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1841/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1842/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1843
1844/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1845/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1846/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1847/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1848
1849/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1850/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1851/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1852/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1853
1854/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1855/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1856/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1857/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1858
1859/*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1860/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1861/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1862/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1863
1864/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1865/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1866/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1867/*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1868
1869/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1870/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1871/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1872/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1873
1874/*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1875/*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1876/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1877/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1878};
1879
1880const instable_t dis_opEVEXF30F[256] = {
1881/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
1882/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
1883/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
1884/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1885
1886/*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
1887/*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
1888/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1889/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1890
1891/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
1892/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
1893/*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
1894/*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1895
1896/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
1897/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
1898/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
1899/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1900
1901/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
1902/*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
1903/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
1904/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1905
1906/*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
1907/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
1908/*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
1909/*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1910
1911/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
1912/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
1913/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
1914/*  [6C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdqu",EVEX_MX),
1915
1916/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
1917/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
1918/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
1919/*  [7C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdqu",EVEX_RX),
1920
1921/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
1922/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
1923/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
1924/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1925
1926/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
1927/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
1928/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
1929/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1930
1931/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1932/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1933/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1934/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1935
1936/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1937/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1938/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1939/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1940
1941/*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1942/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1943/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1944/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1945
1946/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1947/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1948/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1949/*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1950
1951/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1952/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1953/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1954/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1955
1956/*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
1957/*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
1958/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
1959/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
1960};
1961/*
1962 * The following two tables are used to encode crc32 and movbe
1963 * since they share the same opcodes.
1964 */
1965const instable_t dis_op0F38F0[2] = {
1966/*  [00]  */	TNS("crc32b",CRC32),
1967		TS("movbe",MOVBE),
1968};
1969
1970const instable_t dis_op0F38F1[2] = {
1971/*  [00]  */	TS("crc32",CRC32),
1972		TS("movbe",MOVBE),
1973};
1974
1975/*
1976 * The following table is used to distinguish between adox and adcx which share
1977 * the same opcodes.
1978 */
1979const instable_t dis_op0F38F6[2] = {
1980/*  [00]  */	TNS("adcx",ADX),
1981		TNS("adox",ADX),
1982};
1983
1984const instable_t dis_op0F38[256] = {
1985/*  [00]  */	TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16),
1986/*  [04]  */	TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16),	TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16),
1987/*  [08]  */	TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16),
1988/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1989
1990/*  [10]  */	TNSZ("pblendvb",XMM_66r,16),INVALID,		INVALID,		INVALID,
1991/*  [14]  */	TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID,	TNSZ("ptest",XMM_66r,16),
1992/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
1993/*  [1C]  */	TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID,
1994
1995/*  [20]  */	TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16),
1996/*  [24]  */	TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID,	INVALID,
1997/*  [28]  */	TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16),
1998/*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
1999
2000/*  [30]  */	TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16),
2001/*  [34]  */	TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID,	TNSZ("pcmpgtq",XMM_66r,16),
2002/*  [38]  */	TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16),
2003/*  [3C]  */	TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16),
2004
2005/*  [40]  */	TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID,	INVALID,
2006/*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
2007/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
2008/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2009
2010/*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
2011/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
2012/*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
2013/*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2014
2015/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
2016/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
2017/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
2018/*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2019
2020/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
2021/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
2022/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
2023/*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2024
2025/*  [80]  */	TNSy("invept", RM_66r),	TNSy("invvpid", RM_66r),TNSy("invpcid", RM_66r),INVALID,
2026/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
2027/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
2028/*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2029
2030/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
2031/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
2032/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
2033/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2034
2035/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2036/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2037/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2038/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2039
2040/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2041/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2042/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2043/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2044
2045/*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2046/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2047/*  [C8]  */	TNSZ("sha1nexte",XMM,16),TNSZ("sha1msg1",XMM,16),TNSZ("sha1msg2",XMM,16),TNSZ("sha256rnds2",XMM,16),
2048/*  [CC]  */	TNSZ("sha256msg1",XMM,16),TNSZ("sha256msg2",XMM,16),INVALID,		TNS("gf2p8mulb",XMM_66r),
2049
2050/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2051/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2052/*  [D8]  */	INVALID,		INVALID,		INVALID,		TNSZ("aesimc",XMM_66r,16),
2053/*  [DC]  */	TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16),
2054
2055/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2056/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2057/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2058/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2059/*  [F0]  */	IND(dis_op0F38F0),	IND(dis_op0F38F1),	INVALID,		INVALID,
2060/*  [F4]  */	INVALID,		INVALID,		IND(dis_op0F38F6),	INVALID,
2061/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2062/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2063};
2064
2065const instable_t dis_opAVX660F38[256] = {
2066/*  [00]  */	TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16),
2067/*  [04]  */	TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16),	TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16),
2068/*  [08]  */	TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16),
2069/*  [0C]  */	TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8),	TNSZ("vtestpd",VEX_RRI,16),
2070
2071/*  [10]  */	INVALID,		INVALID,		INVALID,		TNSZ("vcvtph2ps",VEX_MX,16),
2072/*  [14]  */	INVALID,		INVALID,		TNSZ("vpermps",VEX_RMrX,16),TNSZ("vptest",VEX_RRI,16),
2073/*  [18]  */	TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID,
2074/*  [1C]  */	TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID,
2075
2076/*  [20]  */	TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16),
2077/*  [24]  */	TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID,	INVALID,
2078/*  [28]  */	TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16),
2079/*  [2C]  */	TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16),
2080
2081/*  [30]  */	TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16),
2082/*  [34]  */	TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16),
2083/*  [38]  */	TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16),
2084/*  [3C]  */	TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16),
2085
2086/*  [40]  */	TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID,	INVALID,
2087/*  [44]  */	INVALID,		TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16),
2088/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
2089/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2090
2091/*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
2092/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
2093/*  [58]  */	TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID,
2094/*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2095
2096/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
2097/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
2098/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
2099/*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2100
2101/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
2102/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
2103/*  [78]  */	TNSZ("vpbroadcastb",VEX_MX,16),TNSZ("vpbroadcastw",VEX_MX,16),INVALID,	INVALID,
2104/*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2105
2106/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
2107/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
2108/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
2109/*  [8C]  */	TSaZ("vpmaskmov",VEX_RMrX,16),INVALID,		TSaZ("vpmaskmov",VEX_RRM,16),INVALID,
2110
2111/*  [90]  */	TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16),
2112/*  [94]  */	INVALID,		INVALID,		TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16),
2113/*  [98]  */	TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16),
2114/*  [9C]  */	TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16),
2115
2116/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2117/*  [A4]  */	INVALID,		INVALID,		TNSZ("vfmaddsub213p",FMA,16),TNSZ("vfmsubadd213p",FMA,16),
2118/*  [A8]  */	TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16),
2119/*  [AC]  */	TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16),
2120
2121/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2122/*  [B4]  */	INVALID,		INVALID,		TNSZ("vfmaddsub231p",FMA,16),TNSZ("vfmsubadd231p",FMA,16),
2123/*  [B8]  */	TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16),
2124/*  [BC]  */	TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16),
2125
2126/*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2127/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2128/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2129/*  [CC]  */	INVALID,		INVALID,		INVALID,		TNS("vgf2p8mulb",VEX_RMrX),
2130
2131/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2132/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2133/*  [D8]  */	INVALID,		INVALID,		INVALID,		TNSZ("vaesimc",VEX_MX,16),
2134/*  [DC]  */	TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16),
2135
2136/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2137/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2138/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2139/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2140/*  [F0]  */	IND(dis_op0F38F0),	IND(dis_op0F38F1),	INVALID,		INVALID,
2141/*  [F4]  */	INVALID,		INVALID,		INVALID,		TNSZvr("shlx",VEX_VRMrX,5),
2142/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2143/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2144};
2145
2146const instable_t dis_op0F3A[256] = {
2147/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
2148/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
2149/*  [08]  */	TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16),
2150/*  [0C]  */	TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16),
2151
2152/*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
2153/*  [14]  */	TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16),
2154/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
2155/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2156
2157/*  [20]  */	TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID,
2158/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
2159/*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
2160/*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2161
2162/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
2163/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
2164/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
2165/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2166
2167/*  [40]  */	TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID,
2168/*  [44]  */	TNSZ("pclmulqdq",XMMP_66r,16),INVALID,		INVALID,		INVALID,
2169/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
2170/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2171
2172/*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
2173/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
2174/*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
2175/*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2176
2177/*  [60]  */	TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16),
2178/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
2179/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
2180/*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2181
2182/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
2183/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
2184/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
2185/*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2186
2187/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
2188/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
2189/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
2190/*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2191
2192/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
2193/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
2194/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
2195/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2196
2197/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2198/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2199/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2200/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2201
2202/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2203/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2204/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2205/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2206
2207/*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2208/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2209/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2210/*  [CC]  */	TNSZ("sha1rnds4",XMMP,16),INVALID,		TNS("gf2p8affineqb",XMMP_66r),TNS("gf2p8affineinvqb",XMMP_66r),
2211
2212/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2213/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2214/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2215/*  [DC]  */	INVALID,		INVALID,		INVALID,		TNSZ("aeskeygenassist",XMMP_66r,16),
2216
2217/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2218/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2219/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2220/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2221
2222/*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2223/*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2224/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2225/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2226};
2227
2228const instable_t dis_opAVX660F3A[256] = {
2229/*  [00]  */	TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID,
2230/*  [04]  */	TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID,
2231/*  [08]  */	TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16),
2232/*  [0C]  */	TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16),
2233
2234/*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
2235/*  [14]  */	TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16),
2236/*  [18]  */	TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID,		INVALID,
2237/*  [1C]  */	INVALID,		TNSZ("vcvtps2ph",VEX_RX,16),		INVALID,		INVALID,
2238
2239/*  [20]  */	TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID,
2240/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
2241/*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
2242/*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2243
2244/*  [30]  */	TSvo("kshiftr",VEX_MXI),	TSvo("kshiftr",VEX_MXI),	TSvo("kshiftl",VEX_MXI),	TSvo("kshiftl",VEX_MXI),
2245/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
2246/*  [38]  */	TNSZ("vinserti128",VEX_RMRX,16),TNSZ("vextracti128",VEX_RIM,16),INVALID,		INVALID,
2247/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2248
2249/*  [40]  */	TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID,
2250/*  [44]  */	TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID,		TNSZ("vperm2i128",VEX_RMRX,16),INVALID,
2251/*  [48]  */	INVALID,		INVALID,		TNSZ("vblendvps",VEX_RMRX,8),	TNSZ("vblendvpd",VEX_RMRX,16),
2252/*  [4C]  */	TNSZ("vpblendvb",VEX_RMRX,16),INVALID,		INVALID,		INVALID,
2253
2254/*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
2255/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
2256/*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
2257/*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2258
2259/*  [60]  */	TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16),
2260/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
2261/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
2262/*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2263
2264/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
2265/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
2266/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
2267/*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2268
2269/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
2270/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
2271/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
2272/*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2273
2274/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
2275/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
2276/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
2277/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2278
2279/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2280/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2281/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2282/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2283
2284/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2285/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2286/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2287/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2288
2289/*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2290/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2291/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2292/*  [CC]  */	INVALID,		INVALID,		TNS("vgf2p8affineqb",VEX_RMRX),TNS("vgf2p8affineinvqb",VEX_RMRX),
2293
2294/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2295/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2296/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2297/*  [DC]  */	INVALID,		INVALID,		INVALID,		TNSZ("vaeskeygenassist",VEX_MXI,16),
2298
2299/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2300/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2301/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2302/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2303
2304/*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2305/*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2306/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2307/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2308};
2309
2310/*
2311 *	Decode table for 0x0F0D which uses the first byte of the mod_rm to
2312 *	indicate a sub-code.
2313 */
2314const instable_t dis_op0F0D[8] = {
2315/*  [00]  */	INVALID,		TNS("prefetchw",PREF),	TNS("prefetchwt1",PREF),INVALID,
2316/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
2317};
2318
2319/*
2320 *	Decode table for 0x0F opcodes
2321 */
2322
2323const instable_t dis_op0F[16][16] = {
2324{
2325/*  [00]  */	IND(dis_op0F00),	IND(dis_op0F01),	TNS("lar",MR),		TNS("lsl",MR),
2326/*  [04]  */	INVALID,		TNS("syscall",NORM),	TNS("clts",NORM),	TNS("sysret",NORM),
2327/*  [08]  */	TNS("invd",NORM),	TNS("wbinvd",NORM),	INVALID,		TNS("ud2",NORM),
2328/*  [0C]  */	INVALID,		IND(dis_op0F0D),	INVALID,		INVALID,
2329}, {
2330/*  [10]  */	TNSZ("movups",XMMO,16),	TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8),	TNSZ("movlps",XMMOS,8),
2331/*  [14]  */	TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
2332/*  [18]  */	IND(dis_op0F18),	INVALID,		INVALID,		INVALID,
2333/*  [1C]  */	INVALID,		INVALID,		INVALID,		TS("nop",Mw),
2334}, {
2335/*  [20]  */	TSy("mov",SREG),	TSy("mov",SREG),	TSy("mov",SREG),	TSy("mov",SREG),
2336/*  [24]  */	TSx("mov",SREG),	INVALID,		TSx("mov",SREG),	INVALID,
2337/*  [28]  */	TNSZ("movaps",XMMO,16),	TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16),
2338/*  [2C]  */	TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4),
2339}, {
2340/*  [30]  */	TNS("wrmsr",NORM),	TNS("rdtsc",NORM),	TNS("rdmsr",NORM),	TNS("rdpmc",NORM),
2341/*  [34]  */	TNS("sysenter",NORM),	TNS("sysexit",NORM),	INVALID,		INVALID,
2342/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
2343/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2344}, {
2345/*  [40]  */	TS("cmovx.o",MR),	TS("cmovx.no",MR),	TS("cmovx.b",MR),	TS("cmovx.ae",MR),
2346/*  [44]  */	TS("cmovx.e",MR),	TS("cmovx.ne",MR),	TS("cmovx.be",MR),	TS("cmovx.a",MR),
2347/*  [48]  */	TS("cmovx.s",MR),	TS("cmovx.ns",MR),	TS("cmovx.pe",MR),	TS("cmovx.po",MR),
2348/*  [4C]  */	TS("cmovx.l",MR),	TS("cmovx.ge",MR),	TS("cmovx.le",MR),	TS("cmovx.g",MR),
2349}, {
2350/*  [50]  */	TNS("movmskps",XMMOX3),	TNSZ("sqrtps",XMMO,16),	TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16),
2351/*  [54]  */	TNSZ("andps",XMMO,16),	TNSZ("andnps",XMMO,16),	TNSZ("orps",XMMO,16),	TNSZ("xorps",XMMO,16),
2352/*  [58]  */	TNSZ("addps",XMMO,16),	TNSZ("mulps",XMMO,16),	TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16),
2353/*  [5C]  */	TNSZ("subps",XMMO,16),	TNSZ("minps",XMMO,16),	TNSZ("divps",XMMO,16),	TNSZ("maxps",XMMO,16),
2354}, {
2355/*  [60]  */	TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8),
2356/*  [64]  */	TNSZ("pcmpgtb",MMO,8),	TNSZ("pcmpgtw",MMO,8),	TNSZ("pcmpgtd",MMO,8),	TNSZ("packuswb",MMO,8),
2357/*  [68]  */	TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8),
2358/*  [6C]  */	TNSZ("INVALID",MMO,0),	TNSZ("INVALID",MMO,0),	TNSZ("movd",MMO,4),	TNSZ("movq",MMO,8),
2359}, {
2360/*  [70]  */	TNSZ("pshufw",MMOPM,8),	TNS("psrXXX",MR),	TNS("psrXXX",MR),	TNS("psrXXX",MR),
2361/*  [74]  */	TNSZ("pcmpeqb",MMO,8),	TNSZ("pcmpeqw",MMO,8),	TNSZ("pcmpeqd",MMO,8),	TNS("emms",NORM),
2362/*  [78]  */	TNSy("vmread",RM),	TNSy("vmwrite",MR),	INVALID,		INVALID,
2363/*  [7C]  */	INVALID,		INVALID,		TNSZ("movd",MMOS,4),	TNSZ("movq",MMOS,8),
2364}, {
2365/*  [80]  */	TNS("jo",D),		TNS("jno",D),		TNS("jb",D),		TNS("jae",D),
2366/*  [84]  */	TNS("je",D),		TNS("jne",D),		TNS("jbe",D),		TNS("ja",D),
2367/*  [88]  */	TNS("js",D),		TNS("jns",D),		TNS("jp",D),		TNS("jnp",D),
2368/*  [8C]  */	TNS("jl",D),		TNS("jge",D),		TNS("jle",D),		TNS("jg",D),
2369}, {
2370/*  [90]  */	TNS("seto",Mb),		TNS("setno",Mb),	TNS("setb",Mb),		TNS("setae",Mb),
2371/*  [94]  */	TNS("sete",Mb),		TNS("setne",Mb),	TNS("setbe",Mb),	TNS("seta",Mb),
2372/*  [98]  */	TNS("sets",Mb),		TNS("setns",Mb),	TNS("setp",Mb),		TNS("setnp",Mb),
2373/*  [9C]  */	TNS("setl",Mb),		TNS("setge",Mb),	TNS("setle",Mb),	TNS("setg",Mb),
2374}, {
2375/*  [A0]  */	TSp("push",LSEG),	TSp("pop",LSEG),	TNS("cpuid",NORM),	TS("bt",RMw),
2376/*  [A4]  */	TS("shld",DSHIFT),	TS("shld",DSHIFTcl),	INVALID,		INVALID,
2377/*  [A8]  */	TSp("push",LSEG),	TSp("pop",LSEG),	TNS("rsm",NORM),	TS("bts",RMw),
2378/*  [AC]  */	TS("shrd",DSHIFT),	TS("shrd",DSHIFTcl),	IND(dis_op0FAE),	TS("imul",MRw),
2379}, {
2380/*  [B0]  */	TNS("cmpxchgb",RMw),	TS("cmpxchg",RMw),	TS("lss",MR),		TS("btr",RMw),
2381/*  [B4]  */	TS("lfs",MR),		TS("lgs",MR),		TS("movzb",MOVZ),	TNS("movzwl",MOVZ),
2382/*  [B8]  */	TNS("INVALID",MRw),	INVALID,		IND(dis_op0FBA),	TS("btc",RMw),
2383/*  [BC]  */	TS("bsf",MRw),		TS("bsr",MRw),		TS("movsb",MOVZ),	TNS("movswl",MOVZ),
2384}, {
2385/*  [C0]  */	TNS("xaddb",XADDB),	TS("xadd",RMw),		TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM),
2386/*  [C4]  */	TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P),	TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7),
2387/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2388/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2389}, {
2390/*  [D0]  */	INVALID,		TNSZ("psrlw",MMO,8),	TNSZ("psrld",MMO,8),	TNSZ("psrlq",MMO,8),
2391/*  [D4]  */	TNSZ("paddq",MMO,8),	TNSZ("pmullw",MMO,8),	TNSZ("INVALID",MMO,0),	TNS("pmovmskb",MMOM3),
2392/*  [D8]  */	TNSZ("psubusb",MMO,8),	TNSZ("psubusw",MMO,8),	TNSZ("pminub",MMO,8),	TNSZ("pand",MMO,8),
2393/*  [DC]  */	TNSZ("paddusb",MMO,8),	TNSZ("paddusw",MMO,8),	TNSZ("pmaxub",MMO,8),	TNSZ("pandn",MMO,8),
2394}, {
2395/*  [E0]  */	TNSZ("pavgb",MMO,8),	TNSZ("psraw",MMO,8),	TNSZ("psrad",MMO,8),	TNSZ("pavgw",MMO,8),
2396/*  [E4]  */	TNSZ("pmulhuw",MMO,8),	TNSZ("pmulhw",MMO,8),	TNS("INVALID",XMMO),	TNSZ("movntq",MMOMS,8),
2397/*  [E8]  */	TNSZ("psubsb",MMO,8),	TNSZ("psubsw",MMO,8),	TNSZ("pminsw",MMO,8),	TNSZ("por",MMO,8),
2398/*  [EC]  */	TNSZ("paddsb",MMO,8),	TNSZ("paddsw",MMO,8),	TNSZ("pmaxsw",MMO,8),	TNSZ("pxor",MMO,8),
2399}, {
2400/*  [F0]  */	INVALID,		TNSZ("psllw",MMO,8),	TNSZ("pslld",MMO,8),	TNSZ("psllq",MMO,8),
2401/*  [F4]  */	TNSZ("pmuludq",MMO,8),	TNSZ("pmaddwd",MMO,8),	TNSZ("psadbw",MMO,8),	TNSZ("maskmovq",MMOIMPL,8),
2402/*  [F8]  */	TNSZ("psubb",MMO,8),	TNSZ("psubw",MMO,8),	TNSZ("psubd",MMO,8),	TNSZ("psubq",MMO,8),
2403/*  [FC]  */	TNSZ("paddb",MMO,8),	TNSZ("paddw",MMO,8),	TNSZ("paddd",MMO,8),	INVALID,
2404} };
2405
2406const instable_t dis_opAVX0F[16][16] = {
2407{
2408/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
2409/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
2410/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
2411/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2412}, {
2413/*  [10]  */	TNSZ("vmovups",VEX_MX,16),	TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8),	TNSZ("vmovlps",VEX_RM,8),
2414/*  [14]  */	TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8),
2415/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
2416/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2417}, {
2418/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
2419/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
2420/*  [28]  */	TNSZ("vmovaps",VEX_MX,16),	TNSZ("vmovaps",VEX_RX,16),INVALID,		TNSZ("vmovntps",VEX_RM,16),
2421/*  [2C]  */	INVALID,		INVALID,		TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4),
2422}, {
2423/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
2424/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
2425/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
2426/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2427}, {
2428/*  [40]  */	INVALID,		TSvo("kand",VEX_RMX),	TSvo("kandn",VEX_RMX),		INVALID,
2429/*  [44]  */	TSvo("knot",VEX_MX),	TSvo("kor",VEX_RMX),	TSvo("kxnor",VEX_RMX),		TSvo("kxor",VEX_RMX),
2430/*  [48]  */	INVALID,		INVALID,		TSvo("kadd",VEX_RMX),		TSvo("kunpck",VEX_RMX),
2431/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2432}, {
2433/*  [50]  */	TNS("vmovmskps",VEX_MR),	TNSZ("vsqrtps",VEX_MX,16),	TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16),
2434/*  [54]  */	TNSZ("vandps",VEX_RMrX,16),	TNSZ("vandnps",VEX_RMrX,16),	TNSZ("vorps",VEX_RMrX,16),	TNSZ("vxorps",VEX_RMrX,16),
2435/*  [58]  */	TNSZ("vaddps",VEX_RMrX,16),	TNSZ("vmulps",VEX_RMrX,16),	TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16),
2436/*  [5C]  */	TNSZ("vsubps",VEX_RMrX,16),	TNSZ("vminps",VEX_RMrX,16),	TNSZ("vdivps",VEX_RMrX,16),	TNSZ("vmaxps",VEX_RMrX,16),
2437}, {
2438/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
2439/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
2440/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
2441/*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2442}, {
2443/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
2444/*  [74]  */	INVALID,		INVALID,		INVALID,		TNS("vzeroupper", VEX_NONE),
2445/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
2446/*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2447}, {
2448/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
2449/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
2450/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
2451/*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2452}, {
2453/*  [90]  */	TSvo("kmov",VEX_KRM),	TSvo("kmov",VEX_KMR),	TSvo("kmov",VEX_KRR),		TSvo("kmov",VEX_MR),
2454/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
2455/*  [98]  */	TSvo("kortest",VEX_MX),	TSvo("ktest",VEX_MX),	INVALID,		INVALID,
2456/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
2457}, {
2458/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2459/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2460/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2461/*  [AC]  */	INVALID,		INVALID,		TNSZ("vldmxcsr",VEX_MO,2),		INVALID,
2462}, {
2463/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2464/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2465/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2466/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2467}, {
2468/*  [C0]  */	INVALID,		INVALID,		TNSZ("vcmpps",VEX_RMRX,16),INVALID,
2469/*  [C4]  */	INVALID,		INVALID,		TNSZ("vshufps",VEX_RMRX,16),INVALID,
2470/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2471/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2472}, {
2473/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2474/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2475/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2476/*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2477}, {
2478/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2479/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2480/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2481/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2482}, {
2483/*  [F0]  */	INVALID,		INVALID,		TNSZvr("andn",VEX_RMrX,5),TNSZvr("bls",BLS,5),
2484/*  [F4]  */	INVALID,		TNSZvr("bzhi",VEX_VRMrX,5),INVALID,		TNSZvr("bextr",VEX_VRMrX,5),
2485/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
2486/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
2487} };
2488
2489/*
2490 *	Decode table for 0x80 opcodes
2491 */
2492
2493const instable_t dis_op80[8] = {
2494
2495/*  [0]  */	TNS("addb",IMlw),	TNS("orb",IMw),		TNS("adcb",IMlw),	TNS("sbbb",IMlw),
2496/*  [4]  */	TNS("andb",IMw),	TNS("subb",IMlw),	TNS("xorb",IMw),	TNS("cmpb",IMlw),
2497};
2498
2499
2500/*
2501 *	Decode table for 0x81 opcodes.
2502 */
2503
2504const instable_t dis_op81[8] = {
2505
2506/*  [0]  */	TS("add",IMlw),		TS("or",IMw),		TS("adc",IMlw),		TS("sbb",IMlw),
2507/*  [4]  */	TS("and",IMw),		TS("sub",IMlw),		TS("xor",IMw),		TS("cmp",IMlw),
2508};
2509
2510
2511/*
2512 *	Decode table for 0x82 opcodes.
2513 */
2514
2515const instable_t dis_op82[8] = {
2516
2517/*  [0]  */	TNSx("addb",IMlw),	TNSx("orb",IMlw),	TNSx("adcb",IMlw),	TNSx("sbbb",IMlw),
2518/*  [4]  */	TNSx("andb",IMlw),	TNSx("subb",IMlw),	TNSx("xorb",IMlw),	TNSx("cmpb",IMlw),
2519};
2520/*
2521 *	Decode table for 0x83 opcodes.
2522 */
2523
2524const instable_t dis_op83[8] = {
2525
2526/*  [0]  */	TS("add",IMlw),		TS("or",IMlw),		TS("adc",IMlw),		TS("sbb",IMlw),
2527/*  [4]  */	TS("and",IMlw),		TS("sub",IMlw),		TS("xor",IMlw),		TS("cmp",IMlw),
2528};
2529
2530/*
2531 *	Decode table for 0xC0 opcodes.
2532 */
2533
2534const instable_t dis_opC0[8] = {
2535
2536/*  [0]  */	TNS("rolb",MvI),	TNS("rorb",MvI),	TNS("rclb",MvI),	TNS("rcrb",MvI),
2537/*  [4]  */	TNS("shlb",MvI),	TNS("shrb",MvI),	INVALID,		TNS("sarb",MvI),
2538};
2539
2540/*
2541 *	Decode table for 0xD0 opcodes.
2542 */
2543
2544const instable_t dis_opD0[8] = {
2545
2546/*  [0]  */	TNS("rolb",Mv),		TNS("rorb",Mv),		TNS("rclb",Mv),		TNS("rcrb",Mv),
2547/*  [4]  */	TNS("shlb",Mv),		TNS("shrb",Mv),		TNS("salb",Mv),		TNS("sarb",Mv),
2548};
2549
2550/*
2551 *	Decode table for 0xC1 opcodes.
2552 *	186 instruction set
2553 */
2554
2555const instable_t dis_opC1[8] = {
2556
2557/*  [0]  */	TS("rol",MvI),		TS("ror",MvI),		TS("rcl",MvI),		TS("rcr",MvI),
2558/*  [4]  */	TS("shl",MvI),		TS("shr",MvI),		TS("sal",MvI),		TS("sar",MvI),
2559};
2560
2561/*
2562 *	Decode table for 0xD1 opcodes.
2563 */
2564
2565const instable_t dis_opD1[8] = {
2566
2567/*  [0]  */	TS("rol",Mv),		TS("ror",Mv),		TS("rcl",Mv),		TS("rcr",Mv),
2568/*  [4]  */	TS("shl",Mv),		TS("shr",Mv),		TS("sal",Mv),		TS("sar",Mv),
2569};
2570
2571
2572/*
2573 *	Decode table for 0xD2 opcodes.
2574 */
2575
2576const instable_t dis_opD2[8] = {
2577
2578/*  [0]  */	TNS("rolb",Mv),		TNS("rorb",Mv),		TNS("rclb",Mv),		TNS("rcrb",Mv),
2579/*  [4]  */	TNS("shlb",Mv),		TNS("shrb",Mv),		TNS("salb",Mv),		TNS("sarb",Mv),
2580};
2581/*
2582 *	Decode table for 0xD3 opcodes.
2583 */
2584
2585const instable_t dis_opD3[8] = {
2586
2587/*  [0]  */	TS("rol",Mv),		TS("ror",Mv),		TS("rcl",Mv),		TS("rcr",Mv),
2588/*  [4]  */	TS("shl",Mv),		TS("shr",Mv),		TS("salb",Mv),		TS("sar",Mv),
2589};
2590
2591
2592/*
2593 *	Decode table for 0xF6 opcodes.
2594 */
2595
2596const instable_t dis_opF6[8] = {
2597
2598/*  [0]  */	TNS("testb",IMw),	TNS("testb",IMw),	TNS("notb",Mw),		TNS("negb",Mw),
2599/*  [4]  */	TNS("mulb",MA),		TNS("imulb",MA),	TNS("divb",MA),		TNS("idivb",MA),
2600};
2601
2602
2603/*
2604 *	Decode table for 0xF7 opcodes.
2605 */
2606
2607const instable_t dis_opF7[8] = {
2608
2609/*  [0]  */	TS("test",IMw),		TS("test",IMw),		TS("not",Mw),		TS("neg",Mw),
2610/*  [4]  */	TS("mul",MA),		TS("imul",MA),		TS("div",MA),		TS("idiv",MA),
2611};
2612
2613
2614/*
2615 *	Decode table for 0xFE opcodes.
2616 */
2617
2618const instable_t dis_opFE[8] = {
2619
2620/*  [0]  */	TNS("incb",Mw),		TNS("decb",Mw),		INVALID,		INVALID,
2621/*  [4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2622};
2623/*
2624 *	Decode table for 0xFF opcodes.
2625 */
2626
2627const instable_t dis_opFF[8] = {
2628
2629/*  [0]  */	TS("inc",Mw),		TS("dec",Mw),		TNSyp("call",INM),	TNS("lcall",INM),
2630/*  [4]  */	TNSy("jmp",INM),	TNS("ljmp",INM),	TSp("push",M),		INVALID,
2631};
2632
2633/* for 287 instructions, which are a mess to decode */
2634
2635const instable_t dis_opFP1n2[8][8] = {
2636{
2637/* bit pattern:	1101 1xxx MODxx xR/M */
2638/*  [0,0] */	TNS("fadds",M),		TNS("fmuls",M),		TNS("fcoms",M),		TNS("fcomps",M),
2639/*  [0,4] */	TNS("fsubs",M),		TNS("fsubrs",M),	TNS("fdivs",M),		TNS("fdivrs",M),
2640}, {
2641/*  [1,0]  */	TNS("flds",M),		INVALID,		TNS("fsts",M),		TNS("fstps",M),
2642/*  [1,4]  */	TNSZ("fldenv",M,28),	TNSZ("fldcw",M,2),	TNSZ("fnstenv",M,28),	TNSZ("fnstcw",M,2),
2643}, {
2644/*  [2,0]  */	TNS("fiaddl",M),	TNS("fimull",M),	TNS("ficoml",M),	TNS("ficompl",M),
2645/*  [2,4]  */	TNS("fisubl",M),	TNS("fisubrl",M),	TNS("fidivl",M),	TNS("fidivrl",M),
2646}, {
2647/*  [3,0]  */	TNS("fildl",M),		TNSZ("tisttpl",M,4),	TNS("fistl",M),		TNS("fistpl",M),
2648/*  [3,4]  */	INVALID,		TNSZ("fldt",M,10),	INVALID,		TNSZ("fstpt",M,10),
2649}, {
2650/*  [4,0]  */	TNSZ("faddl",M,8),	TNSZ("fmull",M,8),	TNSZ("fcoml",M,8),	TNSZ("fcompl",M,8),
2651/*  [4,1]  */	TNSZ("fsubl",M,8),	TNSZ("fsubrl",M,8),	TNSZ("fdivl",M,8),	TNSZ("fdivrl",M,8),
2652}, {
2653/*  [5,0]  */	TNSZ("fldl",M,8),	TNSZ("fisttpll",M,8),	TNSZ("fstl",M,8),	TNSZ("fstpl",M,8),
2654/*  [5,4]  */	TNSZ("frstor",M,108),	INVALID,		TNSZ("fnsave",M,108),	TNSZ("fnstsw",M,2),
2655}, {
2656/*  [6,0]  */	TNSZ("fiadd",M,2),	TNSZ("fimul",M,2),	TNSZ("ficom",M,2),	TNSZ("ficomp",M,2),
2657/*  [6,4]  */	TNSZ("fisub",M,2),	TNSZ("fisubr",M,2),	TNSZ("fidiv",M,2),	TNSZ("fidivr",M,2),
2658}, {
2659/*  [7,0]  */	TNSZ("fild",M,2),	TNSZ("fisttp",M,2),	TNSZ("fist",M,2),	TNSZ("fistp",M,2),
2660/*  [7,4]  */	TNSZ("fbld",M,10),	TNSZ("fildll",M,8),	TNSZ("fbstp",M,10),	TNSZ("fistpll",M,8),
2661} };
2662
2663const instable_t dis_opFP3[8][8] = {
2664{
2665/* bit  pattern:	1101 1xxx 11xx xREG */
2666/*  [0,0]  */	TNS("fadd",FF),		TNS("fmul",FF),		TNS("fcom",F),		TNS("fcomp",F),
2667/*  [0,4]  */	TNS("fsub",FF),		TNS("fsubr",FF),	TNS("fdiv",FF),		TNS("fdivr",FF),
2668}, {
2669/*  [1,0]  */	TNS("fld",F),		TNS("fxch",F),		TNS("fnop",NORM),	TNS("fstp",F),
2670/*  [1,4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2671}, {
2672/*  [2,0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2673/*  [2,4]  */	INVALID,		TNS("fucompp",NORM),	INVALID,		INVALID,
2674}, {
2675/*  [3,0]  */	INVALID,		INVALID,		INVALID,		INVALID,
2676/*  [3,4]  */	INVALID,		INVALID,		INVALID,		INVALID,
2677}, {
2678/*  [4,0]  */	TNS("fadd",FF),		TNS("fmul",FF),		TNS("fcom",F),		TNS("fcomp",F),
2679/*  [4,4]  */	TNS("fsub",FF),		TNS("fsubr",FF),	TNS("fdiv",FF),		TNS("fdivr",FF),
2680}, {
2681/*  [5,0]  */	TNS("ffree",F),		TNS("fxch",F),		TNS("fst",F),		TNS("fstp",F),
2682/*  [5,4]  */	TNS("fucom",F),		TNS("fucomp",F),	INVALID,		INVALID,
2683}, {
2684/*  [6,0]  */	TNS("faddp",FF),	TNS("fmulp",FF),	TNS("fcomp",F),		TNS("fcompp",NORM),
2685/*  [6,4]  */	TNS("fsubp",FF),	TNS("fsubrp",FF),	TNS("fdivp",FF),	TNS("fdivrp",FF),
2686}, {
2687/*  [7,0]  */	TNS("ffreep",F),		TNS("fxch",F),		TNS("fstp",F),		TNS("fstp",F),
2688/*  [7,4]  */	TNS("fnstsw",M),	TNS("fucomip",FFC),	TNS("fcomip",FFC),	INVALID,
2689} };
2690
2691const instable_t dis_opFP4[4][8] = {
2692{
2693/* bit pattern:	1101 1001 111x xxxx */
2694/*  [0,0]  */	TNS("fchs",NORM),	TNS("fabs",NORM),	INVALID,		INVALID,
2695/*  [0,4]  */	TNS("ftst",NORM),	TNS("fxam",NORM),	TNS("ftstp",NORM),	INVALID,
2696}, {
2697/*  [1,0]  */	TNS("fld1",NORM),	TNS("fldl2t",NORM),	TNS("fldl2e",NORM),	TNS("fldpi",NORM),
2698/*  [1,4]  */	TNS("fldlg2",NORM),	TNS("fldln2",NORM),	TNS("fldz",NORM),	INVALID,
2699}, {
2700/*  [2,0]  */	TNS("f2xm1",NORM),	TNS("fyl2x",NORM),	TNS("fptan",NORM),	TNS("fpatan",NORM),
2701/*  [2,4]  */	TNS("fxtract",NORM),	TNS("fprem1",NORM),	TNS("fdecstp",NORM),	TNS("fincstp",NORM),
2702}, {
2703/*  [3,0]  */	TNS("fprem",NORM),	TNS("fyl2xp1",NORM),	TNS("fsqrt",NORM),	TNS("fsincos",NORM),
2704/*  [3,4]  */	TNS("frndint",NORM),	TNS("fscale",NORM),	TNS("fsin",NORM),	TNS("fcos",NORM),
2705} };
2706
2707const instable_t dis_opFP5[8] = {
2708/* bit pattern:	1101 1011 111x xxxx */
2709/*  [0]  */	TNS("feni",NORM),	TNS("fdisi",NORM),	TNS("fnclex",NORM),	TNS("fninit",NORM),
2710/*  [4]  */	TNS("fsetpm",NORM),	TNS("frstpm",NORM),	INVALID,		INVALID,
2711};
2712
2713const instable_t dis_opFP6[8] = {
2714/* bit pattern:	1101 1011 11yy yxxx */
2715/*  [00]  */	TNS("fcmov.nb",FF),	TNS("fcmov.ne",FF),	TNS("fcmov.nbe",FF),	TNS("fcmov.nu",FF),
2716/*  [04]  */	INVALID,		TNS("fucomi",F),	TNS("fcomi",F),		INVALID,
2717};
2718
2719const instable_t dis_opFP7[8] = {
2720/* bit pattern:	1101 1010 11yy yxxx */
2721/*  [00]  */	TNS("fcmov.b",FF),	TNS("fcmov.e",FF),	TNS("fcmov.be",FF),	TNS("fcmov.u",FF),
2722/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
2723};
2724
2725/*
2726 *	Main decode table for the op codes.  The first two nibbles
2727 *	will be used as an index into the table.  If there is a
2728 *	a need to further decode an instruction, the array to be
2729 *	referenced is indicated with the other two entries being
2730 *	empty.
2731 */
2732
2733const instable_t dis_distable[16][16] = {
2734{
2735/* [0,0] */	TNS("addb",RMw),	TS("add",RMw),		TNS("addb",MRw),	TS("add",MRw),
2736/* [0,4] */	TNS("addb",IA),		TS("add",IA),		TSx("push",SEG),	TSx("pop",SEG),
2737/* [0,8] */	TNS("orb",RMw),		TS("or",RMw),		TNS("orb",MRw),		TS("or",MRw),
2738/* [0,C] */	TNS("orb",IA),		TS("or",IA),		TSx("push",SEG),	IND(dis_op0F),
2739}, {
2740/* [1,0] */	TNS("adcb",RMw),	TS("adc",RMw),		TNS("adcb",MRw),	TS("adc",MRw),
2741/* [1,4] */	TNS("adcb",IA),		TS("adc",IA),		TSx("push",SEG),	TSx("pop",SEG),
2742/* [1,8] */	TNS("sbbb",RMw),	TS("sbb",RMw),		TNS("sbbb",MRw),	TS("sbb",MRw),
2743/* [1,C] */	TNS("sbbb",IA),		TS("sbb",IA),		TSx("push",SEG),	TSx("pop",SEG),
2744}, {
2745/* [2,0] */	TNS("andb",RMw),	TS("and",RMw),		TNS("andb",MRw),	TS("and",MRw),
2746/* [2,4] */	TNS("andb",IA),		TS("and",IA),		TNSx("%es:",OVERRIDE),	TNSx("daa",NORM),
2747/* [2,8] */	TNS("subb",RMw),	TS("sub",RMw),		TNS("subb",MRw),	TS("sub",MRw),
2748/* [2,C] */	TNS("subb",IA),		TS("sub",IA),		TNS("%cs:",OVERRIDE),	TNSx("das",NORM),
2749}, {
2750/* [3,0] */	TNS("xorb",RMw),	TS("xor",RMw),		TNS("xorb",MRw),	TS("xor",MRw),
2751/* [3,4] */	TNS("xorb",IA),		TS("xor",IA),		TNSx("%ss:",OVERRIDE),	TNSx("aaa",NORM),
2752/* [3,8] */	TNS("cmpb",RMw),	TS("cmp",RMw),		TNS("cmpb",MRw),	TS("cmp",MRw),
2753/* [3,C] */	TNS("cmpb",IA),		TS("cmp",IA),		TNSx("%ds:",OVERRIDE),	TNSx("aas",NORM),
2754}, {
2755/* [4,0] */	TSx("inc",R),		TSx("inc",R),		TSx("inc",R),		TSx("inc",R),
2756/* [4,4] */	TSx("inc",R),		TSx("inc",R),		TSx("inc",R),		TSx("inc",R),
2757/* [4,8] */	TSx("dec",R),		TSx("dec",R),		TSx("dec",R),		TSx("dec",R),
2758/* [4,C] */	TSx("dec",R),		TSx("dec",R),		TSx("dec",R),		TSx("dec",R),
2759}, {
2760/* [5,0] */	TSp("push",R),		TSp("push",R),		TSp("push",R),		TSp("push",R),
2761/* [5,4] */	TSp("push",R),		TSp("push",R),		TSp("push",R),		TSp("push",R),
2762/* [5,8] */	TSp("pop",R),		TSp("pop",R),		TSp("pop",R),		TSp("pop",R),
2763/* [5,C] */	TSp("pop",R),		TSp("pop",R),		TSp("pop",R),		TSp("pop",R),
2764}, {
2765/* [6,0] */	TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",RM),	TNS("arpl",RMw),
2766/* [6,4] */	TNS("%fs:",OVERRIDE),	TNS("%gs:",OVERRIDE),	TNS("data16",DM),	TNS("addr16",AM),
2767/* [6,8] */	TSp("push",I),		TS("imul",IMUL),	TSp("push",Ib),	TS("imul",IMUL),
2768/* [6,C] */	TNSZ("insb",IMPLMEM,1),	TSZ("ins",IMPLMEM,4),	TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4),
2769}, {
2770/* [7,0] */	TNSy("jo",BD),		TNSy("jno",BD),		TNSy("jb",BD),		TNSy("jae",BD),
2771/* [7,4] */	TNSy("je",BD),		TNSy("jne",BD),		TNSy("jbe",BD),		TNSy("ja",BD),
2772/* [7,8] */	TNSy("js",BD),		TNSy("jns",BD),		TNSy("jp",BD),		TNSy("jnp",BD),
2773/* [7,C] */	TNSy("jl",BD),		TNSy("jge",BD),		TNSy("jle",BD),		TNSy("jg",BD),
2774}, {
2775/* [8,0] */	IND(dis_op80),		IND(dis_op81),		INDx(dis_op82),		IND(dis_op83),
2776/* [8,4] */	TNS("testb",RMw),	TS("test",RMw),		TNS("xchgb",RMw),	TS("xchg",RMw),
2777/* [8,8] */	TNS("movb",RMw),	TS("mov",RMw),		TNS("movb",MRw),	TS("mov",MRw),
2778/* [8,C] */	TNS("movw",SM),		TS("lea",MR),		TNS("movw",MS),		TSp("pop",M),
2779}, {
2780/* [9,0] */	TNS("nop",NORM),	TS("xchg",RA),		TS("xchg",RA),		TS("xchg",RA),
2781/* [9,4] */	TS("xchg",RA),		TS("xchg",RA),		TS("xchg",RA),		TS("xchg",RA),
2782/* [9,8] */	TNS("cXtX",CBW),	TNS("cXtX",CWD),	TNSx("lcall",SO),	TNS("fwait",NORM),
2783/* [9,C] */	TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4),	TNS("sahf",NORM),	TNS("lahf",NORM),
2784}, {
2785/* [A,0] */	TNS("movb",OA),		TS("mov",OA),		TNS("movb",AO),		TS("mov",AO),
2786/* [A,4] */	TNSZ("movsb",SD,1),	TS("movs",SD),		TNSZ("cmpsb",SD,1),	TS("cmps",SD),
2787/* [A,8] */	TNS("testb",IA),	TS("test",IA),		TNS("stosb",AD),	TS("stos",AD),
2788/* [A,C] */	TNS("lodsb",SA),	TS("lods",SA),		TNS("scasb",AD),	TS("scas",AD),
2789}, {
2790/* [B,0] */	TNS("movb",IR),		TNS("movb",IR),		TNS("movb",IR),		TNS("movb",IR),
2791/* [B,4] */	TNS("movb",IR),		TNS("movb",IR),		TNS("movb",IR),		TNS("movb",IR),
2792/* [B,8] */	TS("mov",IR),		TS("mov",IR),		TS("mov",IR),		TS("mov",IR),
2793/* [B,C] */	TS("mov",IR),		TS("mov",IR),		TS("mov",IR),		TS("mov",IR),
2794}, {
2795/* [C,0] */	IND(dis_opC0),		IND(dis_opC1),		TNSyp("ret",RET),	TNSyp("ret",NORM),
2796/* [C,4] */	TNSx("les",MR),		TNSx("lds",MR),		TNS("movb",IMw),	TS("mov",IMw),
2797/* [C,8] */	TNSyp("enter",ENTER),	TNSyp("leave",NORM),	TNS("lret",RET),	TNS("lret",NORM),
2798/* [C,C] */	TNS("int",INT3),	TNS("int",INTx),	TNSx("into",NORM),	TNS("iret",NORM),
2799}, {
2800/* [D,0] */	IND(dis_opD0),		IND(dis_opD1),		IND(dis_opD2),		IND(dis_opD3),
2801/* [D,4] */	TNSx("aam",U),		TNSx("aad",U),		TNSx("falc",NORM),	TNSZ("xlat",IMPLMEM,1),
2802
2803/* 287 instructions.  Note that although the indirect field		*/
2804/* indicates opFP1n2 for further decoding, this is not necessarily	*/
2805/* the case since the opFP arrays are not partitioned according to key1	*/
2806/* and key2.  opFP1n2 is given only to indicate that we haven't		*/
2807/* finished decoding the instruction.					*/
2808/* [D,8] */	IND(dis_opFP1n2),	IND(dis_opFP1n2),	IND(dis_opFP1n2),	IND(dis_opFP1n2),
2809/* [D,C] */	IND(dis_opFP1n2),	IND(dis_opFP1n2),	IND(dis_opFP1n2),	IND(dis_opFP1n2),
2810}, {
2811/* [E,0] */	TNSy("loopnz",BD),	TNSy("loopz",BD),	TNSy("loop",BD),	TNSy("jcxz",BD),
2812/* [E,4] */	TNS("inb",P),		TS("in",P),		TNS("outb",P),		TS("out",P),
2813/* [E,8] */	TNSyp("call",D),	TNSy("jmp",D),		TNSx("ljmp",SO),		TNSy("jmp",BD),
2814/* [E,C] */	TNS("inb",V),		TS("in",V),		TNS("outb",V),		TS("out",V),
2815}, {
2816/* [F,0] */	TNS("lock",LOCK),	TNS("icebp", NORM),	TNS("repnz",PREFIX),	TNS("repz",PREFIX),
2817/* [F,4] */	TNS("hlt",NORM),	TNS("cmc",NORM),	IND(dis_opF6),		IND(dis_opF7),
2818/* [F,8] */	TNS("clc",NORM),	TNS("stc",NORM),	TNS("cli",NORM),	TNS("sti",NORM),
2819/* [F,C] */	TNS("cld",NORM),	TNS("std",NORM),	IND(dis_opFE),		IND(dis_opFF),
2820} };
2821
2822/* END CSTYLED */
2823
2824/*
2825 * common functions to decode and disassemble an x86 or amd64 instruction
2826 */
2827
2828/*
2829 * These are the individual fields of a REX prefix. Note that a REX
2830 * prefix with none of these set is still needed to:
2831 *	- use the MOVSXD (sign extend 32 to 64 bits) instruction
2832 *	- access the %sil, %dil, %bpl, %spl registers
2833 */
2834#define	REX_W 0x08	/* 64 bit operand size when set */
2835#define	REX_R 0x04	/* high order bit extension of ModRM reg field */
2836#define	REX_X 0x02	/* high order bit extension of SIB index field */
2837#define	REX_B 0x01	/* extends ModRM r_m, SIB base, or opcode reg */
2838
2839/*
2840 * These are the individual fields of a VEX/EVEX prefix.
2841 */
2842#define	VEX_R 0x08	/* REX.R in 1's complement form */
2843#define	VEX_X 0x04	/* REX.X in 1's complement form */
2844#define	VEX_B 0x02	/* REX.B in 1's complement form */
2845
2846/* Additional EVEX prefix definitions */
2847#define	EVEX_R 0x01	/* REX.R' in 1's complement form */
2848#define	EVEX_OPREG_MASK 0x7 /* bit mask for selecting opmask register number */
2849#define	EVEX_ZERO_MASK 0x80 /* bit mask for selecting zeroing */
2850
2851/* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */
2852#define	VEX_L 0x04
2853/* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector, 2: 512-bit */
2854#define	EVEX_L 0x06	/* bit mask for EVEX.L'L vector length/RC */
2855#define	VEX_W 0x08	/* opcode specific, use like REX.W */
2856#define	VEX_m 0x1F	/* VEX m-mmmm field */
2857#define	EVEX_m 0x3	/* EVEX mm field */
2858#define	VEX_v 0x78	/* VEX/EVEX register specifier */
2859#define	VEX_p 0x03	/* VEX pp field, opcode extension */
2860
2861/* VEX m-mmmm field, only used by three bytes prefix */
2862#define	VEX_m_0F 0x01   /* implied 0F leading opcode byte */
2863#define	VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */
2864#define	VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */
2865
2866/* VEX pp field, providing equivalent functionality of a SIMD prefix */
2867#define	VEX_p_66 0x01
2868#define	VEX_p_F3 0x02
2869#define	VEX_p_F2 0x03
2870
2871/*
2872 * Even in 64 bit mode, usually only 4 byte immediate operands are supported.
2873 */
2874static int isize[] = {1, 2, 4, 4};
2875static int isize64[] = {1, 2, 4, 8};
2876
2877/*
2878 * Just a bunch of useful macros.
2879 */
2880#define	WBIT(x)	(x & 0x1)		/* to get w bit	*/
2881#define	REGNO(x) (x & 0x7)		/* to get 3 bit register */
2882#define	VBIT(x)	((x)>>1 & 0x1)		/* to get 'v' bit */
2883#define	OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1)
2884#define	OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1)
2885
2886#define	REG_ONLY 3	/* mode to indicate a register operand (not memory) */
2887
2888#define	BYTE_OPND	0	/* w-bit value indicating byte register */
2889#define	LONG_OPND	1	/* w-bit value indicating opnd_size register */
2890#define	MM_OPND		2	/* "value" used to indicate a mmx reg */
2891#define	XMM_OPND	3	/* "value" used to indicate a xmm reg */
2892#define	SEG_OPND	4	/* "value" used to indicate a segment reg */
2893#define	CONTROL_OPND	5	/* "value" used to indicate a control reg */
2894#define	DEBUG_OPND	6	/* "value" used to indicate a debug reg */
2895#define	TEST_OPND	7	/* "value" used to indicate a test reg */
2896#define	WORD_OPND	8	/* w-bit value indicating word size reg */
2897#define	YMM_OPND	9	/* "value" used to indicate a ymm reg */
2898#define	KOPMASK_OPND	10	/* "value" used to indicate an opmask reg */
2899#define	ZMM_OPND	11	/* "value" used to indicate a zmm reg */
2900
2901/*
2902 * The AVX2 gather instructions are a bit of a mess. While there's a pattern,
2903 * there's not really a consistent scheme that we can use to know what the mode
2904 * is supposed to be for a given type. Various instructions, like VPGATHERDD,
2905 * always match the value of VEX_L. Other instructions like VPGATHERDQ, have
2906 * some registers match VEX_L, but the VSIB is always XMM.
2907 *
2908 * The simplest way to deal with this is to just define a table based on the
2909 * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into
2910 * them.
2911 *
2912 * We further have to subdivide this based on the value of VEX_W and the value
2913 * of VEX_L. The array is constructed to be indexed as:
2914 *	[opcode - 0x90][VEX_W][VEX_L].
2915 */
2916/* w = 0, 0x90 */
2917typedef struct dis_gather_regs {
2918	uint_t dgr_arg0;	/* src reg */
2919	uint_t dgr_arg1;	/* vsib reg */
2920	uint_t dgr_arg2;	/* dst reg */
2921	char   *dgr_suffix;	/* suffix to append */
2922} dis_gather_regs_t;
2923
2924static dis_gather_regs_t dis_vgather[4][2][2] = {
2925	{
2926		/* op 0x90, W.0 */
2927		{
2928			{ XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2929			{ YMM_OPND, YMM_OPND, YMM_OPND, "d" }
2930		},
2931		/* op 0x90, W.1 */
2932		{
2933			{ XMM_OPND, XMM_OPND, XMM_OPND, "q" },
2934			{ YMM_OPND, XMM_OPND, YMM_OPND, "q" }
2935		}
2936	},
2937	{
2938		/* op 0x91, W.0 */
2939		{
2940			{ XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2941			{ XMM_OPND, YMM_OPND, XMM_OPND, "d" },
2942		},
2943		/* op 0x91, W.1 */
2944		{
2945			{ XMM_OPND, XMM_OPND, XMM_OPND, "q" },
2946			{ YMM_OPND, YMM_OPND, YMM_OPND, "q" },
2947		}
2948	},
2949	{
2950		/* op 0x92, W.0 */
2951		{
2952			{ XMM_OPND, XMM_OPND, XMM_OPND, "s" },
2953			{ YMM_OPND, YMM_OPND, YMM_OPND, "s" }
2954		},
2955		/* op 0x92, W.1 */
2956		{
2957			{ XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2958			{ YMM_OPND, XMM_OPND, YMM_OPND, "d" }
2959		}
2960	},
2961	{
2962		/* op 0x93, W.0 */
2963		{
2964			{ XMM_OPND, XMM_OPND, XMM_OPND, "s" },
2965			{ XMM_OPND, YMM_OPND, XMM_OPND, "s" }
2966		},
2967		/* op 0x93, W.1 */
2968		{
2969			{ XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2970			{ YMM_OPND, YMM_OPND, YMM_OPND, "d" }
2971		}
2972	}
2973};
2974
2975/*
2976 * Get the next byte and separate the op code into the high and low nibbles.
2977 */
2978static int
2979dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low)
2980{
2981	int byte;
2982
2983	/*
2984	 * x86 instructions have a maximum length of 15 bytes.  Bail out if
2985	 * we try to read more.
2986	 */
2987	if (x->d86_len >= 15)
2988		return (x->d86_error = 1);
2989
2990	if (x->d86_error)
2991		return (1);
2992	byte = x->d86_get_byte(x->d86_data);
2993	if (byte < 0)
2994		return (x->d86_error = 1);
2995	x->d86_bytes[x->d86_len++] = byte;
2996	*low = byte & 0xf;		/* ----xxxx low 4 bits */
2997	*high = byte >> 4 & 0xf;	/* xxxx---- bits 7 to 4 */
2998	return (0);
2999}
3000
3001/*
3002 * Get and decode an SIB (scaled index base) byte
3003 */
3004static void
3005dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base)
3006{
3007	int byte;
3008
3009	if (x->d86_error)
3010		return;
3011
3012	byte = x->d86_get_byte(x->d86_data);
3013	if (byte < 0) {
3014		x->d86_error = 1;
3015		return;
3016	}
3017	x->d86_bytes[x->d86_len++] = byte;
3018
3019	*base = byte & 0x7;
3020	*index = (byte >> 3) & 0x7;
3021	*ss = (byte >> 6) & 0x3;
3022}
3023
3024/*
3025 * Get the byte following the op code and separate it into the
3026 * mode, register, and r/m fields.
3027 */
3028static void
3029dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m)
3030{
3031	if (x->d86_got_modrm == 0) {
3032		if (x->d86_rmindex == -1)
3033			x->d86_rmindex = x->d86_len;
3034		dtrace_get_SIB(x, mode, reg, r_m);
3035		x->d86_got_modrm = 1;
3036	}
3037}
3038
3039/*
3040 * Adjust register selection based on any REX prefix bits present.
3041 */
3042/*ARGSUSED*/
3043static void
3044dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m)
3045{
3046	if (reg != NULL && r_m == NULL) {
3047		if (rex_prefix & REX_B)
3048			*reg += 8;
3049	} else {
3050		if (reg != NULL && (REX_R & rex_prefix) != 0)
3051			*reg += 8;
3052		if (r_m != NULL && (REX_B & rex_prefix) != 0)
3053			*r_m += 8;
3054	}
3055}
3056
3057/*
3058 * Adjust register selection based on any VEX prefix bits present.
3059 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix
3060 */
3061/*ARGSUSED*/
3062static void
3063dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m)
3064{
3065	if (reg != NULL && r_m == NULL) {
3066		if (!(vex_byte1 & VEX_B))
3067			*reg += 8;
3068	} else {
3069		if (reg != NULL && ((VEX_R & vex_byte1) == 0))
3070			*reg += 8;
3071		if (r_m != NULL && ((VEX_B & vex_byte1) == 0))
3072			*r_m += 8;
3073	}
3074}
3075
3076/*
3077 * Adjust the instruction mnemonic with the appropriate suffix.
3078 */
3079/* ARGSUSED */
3080static void
3081dtrace_evex_mnem_adjust(dis86_t *x, const instable_t *dp, uint_t vex_W,
3082    uint_t evex_byte2)
3083{
3084#ifdef DIS_TEXT
3085	if (dp == &dis_opEVEX660F[0x7f] ||		/* vmovdqa */
3086	    dp == &dis_opEVEX660F[0x6f]) {
3087		(void) strlcat(x->d86_mnem, vex_W != 0 ? "64" : "32",
3088		    OPLEN);
3089	}
3090
3091	if (dp == &dis_opEVEXF20F[0x7f] ||		/* vmovdqu */
3092	    dp == &dis_opEVEXF20F[0x6f] ||
3093	    dp == &dis_opEVEXF30F[0x7f] ||
3094	    dp == &dis_opEVEXF30F[0x6f]) {
3095		switch (evex_byte2 & 0x81) {
3096		case 0x0:
3097			(void) strlcat(x->d86_mnem, "32", OPLEN);
3098			break;
3099		case 0x1:
3100			(void) strlcat(x->d86_mnem, "8", OPLEN);
3101			break;
3102		case 0x80:
3103			(void) strlcat(x->d86_mnem, "64", OPLEN);
3104			break;
3105		case 0x81:
3106			(void) strlcat(x->d86_mnem, "16", OPLEN);
3107			break;
3108		}
3109	}
3110
3111	if (dp->it_avxsuf == AVS5Q) {
3112		(void) strlcat(x->d86_mnem, vex_W != 0 ?  "q" : "d",
3113		    OPLEN);
3114	}
3115#endif
3116}
3117
3118/*
3119 * The following three functions adjust the register selection based on any
3120 * EVEX prefix bits present. See Intel 64 and IA-32 Architectures Software
3121 * Developer���s Manual Volume 2 (IASDv2), section 2.6.1 Table 2-30 and
3122 * section 2.6.2 Table 2-31.
3123 */
3124static void
3125dtrace_evex_adjust_reg(uint_t evex_byte1, uint_t *reg)
3126{
3127	if (reg != NULL) {
3128		if ((VEX_R & evex_byte1) == 0) {
3129			*reg += 8;
3130		}
3131		if ((EVEX_R & evex_byte1) == 0) {
3132			*reg += 16;
3133		}
3134	}
3135}
3136
3137static void
3138dtrace_evex_adjust_rm(uint_t evex_byte1, uint_t *r_m)
3139{
3140	if (r_m != NULL) {
3141		if ((VEX_B & evex_byte1) == 0) {
3142			*r_m += 8;
3143		}
3144		if ((VEX_X & evex_byte1) == 0) {
3145			*r_m += 16;
3146		}
3147	}
3148}
3149
3150/*
3151 * Use evex_L to set wbit. See IASDv2 Section 2.6.10 and Table 2-36.
3152 */
3153static void
3154dtrace_evex_adjust_reg_name(uint_t evex_L, uint_t *wbitp)
3155{
3156	switch (evex_L) {
3157	case 0x0:
3158		*wbitp = XMM_OPND;
3159		break;
3160	case 0x1:
3161		*wbitp = YMM_OPND;
3162		break;
3163	case 0x2:
3164		*wbitp = ZMM_OPND;
3165		break;
3166	}
3167}
3168
3169/*
3170 * Adjust operand value for disp8*N immediate. See IASDv2 Section 2.6.5.
3171 * This currently only handles a subset of the possibilities.
3172 */
3173static void
3174dtrace_evex_adjust_disp8_n(dis86_t *x, int opindex, uint_t L, uint_t modrm)
3175{
3176	d86opnd_t *opnd = &x->d86_opnd[opindex];
3177
3178	if (x->d86_error)
3179		return;
3180
3181	/* Check disp8 bit in the ModR/M byte */
3182	if ((modrm & 0x80) == 0x80)
3183		return;
3184
3185	/* use evex_L to adjust the value */
3186	switch (L) {
3187	case 0x0:
3188		opnd->d86_value *= 16;
3189		break;
3190	case 0x1:
3191		opnd->d86_value *= 32;
3192		break;
3193	case 0x2:
3194		opnd->d86_value *= 64;
3195		break;
3196	}
3197}
3198
3199/*
3200 * Adjust target for opmask and zeroing. See IASDv2 Section 2.6.1 Table 2-30.
3201 */
3202/* ARGSUSED */
3203static void
3204dtrace_evex_adjust_z_opmask(dis86_t *x, uint_t tgtop, uint_t evex_byte3)
3205{
3206#ifdef DIS_TEXT
3207	char *opnd = x->d86_opnd[tgtop].d86_opnd;
3208	int opmask_reg = evex_byte3 & EVEX_OPREG_MASK;
3209#endif
3210	if (x->d86_error)
3211		return;
3212
3213#ifdef DIS_TEXT
3214	if (opmask_reg != 0) {
3215		/* Append the opmask register to operand 1 */
3216		(void) strlcat(opnd, "{", OPLEN);
3217		(void) strlcat(opnd, dis_KOPMASKREG[opmask_reg], OPLEN);
3218		(void) strlcat(opnd, "}", OPLEN);
3219	}
3220	if ((evex_byte3 & EVEX_ZERO_MASK) != 0) {
3221		/* Append the 'zeroing' modifier to operand 1 */
3222		(void) strlcat(opnd, "{z}", OPLEN);
3223	}
3224#endif /* DIS_TEXT */
3225}
3226
3227/*
3228 * Get an immediate operand of the given size, with sign extension.
3229 */
3230static void
3231dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex)
3232{
3233	int i;
3234	int byte;
3235	int valsize;
3236
3237	if (x->d86_numopnds < opindex + 1)
3238		x->d86_numopnds = opindex + 1;
3239
3240	switch (wbit) {
3241	case BYTE_OPND:
3242		valsize = 1;
3243		break;
3244	case LONG_OPND:
3245		if (x->d86_opnd_size == SIZE16)
3246			valsize = 2;
3247		else if (x->d86_opnd_size == SIZE32)
3248			valsize = 4;
3249		else
3250			valsize = 8;
3251		break;
3252	case MM_OPND:
3253	case XMM_OPND:
3254	case YMM_OPND:
3255	case ZMM_OPND:
3256	case SEG_OPND:
3257	case CONTROL_OPND:
3258	case DEBUG_OPND:
3259	case TEST_OPND:
3260		valsize = size;
3261		break;
3262	case WORD_OPND:
3263		valsize = 2;
3264		break;
3265	}
3266	if (valsize < size)
3267		valsize = size;
3268
3269	if (x->d86_error)
3270		return;
3271	x->d86_opnd[opindex].d86_value = 0;
3272	for (i = 0; i < size; ++i) {
3273		byte = x->d86_get_byte(x->d86_data);
3274		if (byte < 0) {
3275			x->d86_error = 1;
3276			return;
3277		}
3278		x->d86_bytes[x->d86_len++] = byte;
3279		x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8);
3280	}
3281	/* Do sign extension */
3282	if (x->d86_bytes[x->d86_len - 1] & 0x80) {
3283		for (; i < sizeof (uint64_t); i++)
3284			x->d86_opnd[opindex].d86_value |=
3285			    (uint64_t)0xff << (i * 8);
3286	}
3287#ifdef DIS_TEXT
3288	x->d86_opnd[opindex].d86_mode = MODE_SIGNED;
3289	x->d86_opnd[opindex].d86_value_size = valsize;
3290	x->d86_imm_bytes += size;
3291#endif
3292}
3293
3294/*
3295 * Get an ip relative operand of the given size, with sign extension.
3296 */
3297static void
3298dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex)
3299{
3300	dtrace_imm_opnd(x, wbit, size, opindex);
3301#ifdef DIS_TEXT
3302	x->d86_opnd[opindex].d86_mode = MODE_IPREL;
3303#endif
3304}
3305
3306/*
3307 * Check to see if there is a segment override prefix pending.
3308 * If so, print it in the current 'operand' location and set
3309 * the override flag back to false.
3310 */
3311/*ARGSUSED*/
3312static void
3313dtrace_check_override(dis86_t *x, int opindex)
3314{
3315#ifdef DIS_TEXT
3316	if (x->d86_seg_prefix) {
3317		(void) strlcat(x->d86_opnd[opindex].d86_prefix,
3318		    x->d86_seg_prefix, PFIXLEN);
3319	}
3320#endif
3321	x->d86_seg_prefix = NULL;
3322}
3323
3324
3325/*
3326 * Process a single instruction Register or Memory operand.
3327 *
3328 * mode = addressing mode from ModRM byte
3329 * r_m = r_m (or reg if mode == 3) field from ModRM byte
3330 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use.
3331 * o = index of operand that we are processing (0, 1 or 2)
3332 *
3333 * the value of reg or r_m must have already been adjusted for any REX prefix.
3334 */
3335/*ARGSUSED*/
3336static void
3337dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex)
3338{
3339	int have_SIB = 0;	/* flag presence of scale-index-byte */
3340	uint_t ss;		/* scale-factor from opcode */
3341	uint_t index;		/* index register number */
3342	uint_t base;		/* base register number */
3343	int dispsize;		/* size of displacement in bytes */
3344#ifdef DIS_TEXT
3345	char *opnd = x->d86_opnd[opindex].d86_opnd;
3346#endif
3347
3348	if (x->d86_numopnds < opindex + 1)
3349		x->d86_numopnds = opindex + 1;
3350
3351	if (x->d86_error)
3352		return;
3353
3354	/*
3355	 * first handle a simple register
3356	 */
3357	if (mode == REG_ONLY) {
3358#ifdef DIS_TEXT
3359		switch (wbit) {
3360		case MM_OPND:
3361			(void) strlcat(opnd, dis_MMREG[r_m], OPLEN);
3362			break;
3363		case XMM_OPND:
3364			(void) strlcat(opnd, dis_XMMREG[r_m], OPLEN);
3365			break;
3366		case YMM_OPND:
3367			(void) strlcat(opnd, dis_YMMREG[r_m], OPLEN);
3368			break;
3369		case ZMM_OPND:
3370			(void) strlcat(opnd, dis_ZMMREG[r_m], OPLEN);
3371			break;
3372		case KOPMASK_OPND:
3373			(void) strlcat(opnd, dis_KOPMASKREG[r_m], OPLEN);
3374			break;
3375		case SEG_OPND:
3376			(void) strlcat(opnd, dis_SEGREG[r_m], OPLEN);
3377			break;
3378		case CONTROL_OPND:
3379			(void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN);
3380			break;
3381		case DEBUG_OPND:
3382			(void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN);
3383			break;
3384		case TEST_OPND:
3385			(void) strlcat(opnd, dis_TESTREG[r_m], OPLEN);
3386			break;
3387		case BYTE_OPND:
3388			if (x->d86_rex_prefix == 0)
3389				(void) strlcat(opnd, dis_REG8[r_m], OPLEN);
3390			else
3391				(void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN);
3392			break;
3393		case WORD_OPND:
3394			(void) strlcat(opnd, dis_REG16[r_m], OPLEN);
3395			break;
3396		case LONG_OPND:
3397			if (x->d86_opnd_size == SIZE16)
3398				(void) strlcat(opnd, dis_REG16[r_m], OPLEN);
3399			else if (x->d86_opnd_size == SIZE32)
3400				(void) strlcat(opnd, dis_REG32[r_m], OPLEN);
3401			else
3402				(void) strlcat(opnd, dis_REG64[r_m], OPLEN);
3403			break;
3404		}
3405#endif /* DIS_TEXT */
3406		return;
3407	}
3408
3409	/*
3410	 * if symbolic representation, skip override prefix, if any
3411	 */
3412	dtrace_check_override(x, opindex);
3413
3414	/*
3415	 * Handle 16 bit memory references first, since they decode
3416	 * the mode values more simply.
3417	 * mode 1 is r_m + 8 bit displacement
3418	 * mode 2 is r_m + 16 bit displacement
3419	 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp
3420	 */
3421	if (x->d86_addr_size == SIZE16) {
3422		if ((mode == 0 && r_m == 6) || mode == 2)
3423			dtrace_imm_opnd(x, WORD_OPND, 2, opindex);
3424		else if (mode == 1)
3425			dtrace_imm_opnd(x, BYTE_OPND, 1, opindex);
3426#ifdef DIS_TEXT
3427		if (mode == 0 && r_m == 6)
3428			x->d86_opnd[opindex].d86_mode = MODE_SIGNED;
3429		else if (mode == 0)
3430			x->d86_opnd[opindex].d86_mode = MODE_NONE;
3431		else
3432			x->d86_opnd[opindex].d86_mode = MODE_OFFSET;
3433		(void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN);
3434#endif
3435		return;
3436	}
3437
3438	/*
3439	 * 32 and 64 bit addressing modes are more complex since they can
3440	 * involve an SIB (scaled index and base) byte to decode. When using VEX
3441	 * and EVEX encodings, the r_m indicator for a SIB may be offset by 8
3442	 * and 24 (8 + 16) respectively.
3443	 */
3444	if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8 || r_m == ESP_REGNO + 24) {
3445		have_SIB = 1;
3446		dtrace_get_SIB(x, &ss, &index, &base);
3447		if (x->d86_error)
3448			return;
3449		if (base != 5 || mode != 0)
3450			if (x->d86_rex_prefix & REX_B)
3451				base += 8;
3452		if (x->d86_rex_prefix & REX_X)
3453			index += 8;
3454	} else {
3455		base = r_m;
3456	}
3457
3458	/*
3459	 * Compute the displacement size and get its bytes
3460	 */
3461	dispsize = 0;
3462
3463	if (mode == 1)
3464		dispsize = 1;
3465	else if (mode == 2)
3466		dispsize = 4;
3467	else if ((r_m & 7) == EBP_REGNO ||
3468	    (have_SIB && (base & 7) == EBP_REGNO))
3469		dispsize = 4;
3470
3471	if (dispsize > 0) {
3472		dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND,
3473		    dispsize, opindex);
3474		if (x->d86_error)
3475			return;
3476	}
3477
3478#ifdef DIS_TEXT
3479	if (dispsize > 0)
3480		x->d86_opnd[opindex].d86_mode = MODE_OFFSET;
3481
3482	if (have_SIB == 0) {
3483		if (x->d86_mode == SIZE32) {
3484			if (mode == 0)
3485				(void) strlcat(opnd, dis_addr32_mode0[r_m],
3486				    OPLEN);
3487			else
3488				(void) strlcat(opnd, dis_addr32_mode12[r_m],
3489				    OPLEN);
3490		} else {
3491			if (mode == 0) {
3492				(void) strlcat(opnd, dis_addr64_mode0[r_m],
3493				    OPLEN);
3494				if (r_m == 5) {
3495					x->d86_opnd[opindex].d86_mode =
3496					    MODE_RIPREL;
3497				}
3498			} else {
3499				(void) strlcat(opnd, dis_addr64_mode12[r_m],
3500				    OPLEN);
3501			}
3502		}
3503	} else {
3504		uint_t need_paren = 0;
3505		char **regs;
3506		char **bregs;
3507		const char *const *sf;
3508		if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */
3509			regs = (char **)dis_REG32;
3510		else
3511			regs = (char **)dis_REG64;
3512
3513		if (x->d86_vsib != 0) {
3514			if (wbit == YMM_OPND) { /* NOTE this is not addr_size */
3515				bregs = (char **)dis_YMMREG;
3516			} else if (wbit == XMM_OPND) {
3517				bregs = (char **)dis_XMMREG;
3518			} else {
3519				bregs = (char **)dis_ZMMREG;
3520			}
3521			sf = dis_vscale_factor;
3522		} else {
3523			bregs = regs;
3524			sf = dis_scale_factor;
3525		}
3526
3527		/*
3528		 * print the base (if any)
3529		 */
3530		if (base == EBP_REGNO && mode == 0) {
3531			if (index != ESP_REGNO || x->d86_vsib != 0) {
3532				(void) strlcat(opnd, "(", OPLEN);
3533				need_paren = 1;
3534			}
3535		} else {
3536			(void) strlcat(opnd, "(", OPLEN);
3537			(void) strlcat(opnd, regs[base], OPLEN);
3538			need_paren = 1;
3539		}
3540
3541		/*
3542		 * print the index (if any)
3543		 */
3544		if (index != ESP_REGNO || x->d86_vsib) {
3545			(void) strlcat(opnd, ",", OPLEN);
3546			(void) strlcat(opnd, bregs[index], OPLEN);
3547			(void) strlcat(opnd, sf[ss], OPLEN);
3548		} else
3549			if (need_paren)
3550				(void) strlcat(opnd, ")", OPLEN);
3551	}
3552#endif
3553}
3554
3555/*
3556 * Operand sequence for standard instruction involving one register
3557 * and one register/memory operand.
3558 * wbit indicates a byte(0) or opnd_size(1) operation
3559 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r")
3560 */
3561#define	STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit)  {	\
3562		dtrace_get_modrm(x, &mode, &reg, &r_m);			\
3563		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);	\
3564		dtrace_get_operand(x, mode, r_m, wbit, vbit);		\
3565		dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit);	\
3566}
3567
3568/*
3569 * Similar to above, but allows for the two operands to be of different
3570 * classes (ie. wbit).
3571 *	wbit is for the r_m operand
3572 *	w2 is for the reg operand
3573 */
3574#define	MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit)	{	\
3575		dtrace_get_modrm(x, &mode, &reg, &r_m);			\
3576		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);	\
3577		dtrace_get_operand(x, mode, r_m, wbit, vbit);		\
3578		dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit);	\
3579}
3580
3581/*
3582 * Similar, but for 2 operands plus an immediate.
3583 * vbit indicates direction
3584 *	0 for "opcode imm, r, r_m" or
3585 *	1 for "opcode imm, r_m, r"
3586 */
3587#define	THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \
3588		dtrace_get_modrm(x, &mode, &reg, &r_m);			\
3589		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);	\
3590		dtrace_get_operand(x, mode, r_m, wbit, 2-vbit);		\
3591		dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit);	\
3592		dtrace_imm_opnd(x, wbit, immsize, 0);			\
3593}
3594
3595/*
3596 * Similar, but for 2 operands plus two immediates.
3597 */
3598#define	FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \
3599		dtrace_get_modrm(x, &mode, &reg, &r_m);			\
3600		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);	\
3601		dtrace_get_operand(x, mode, r_m, wbit, 2);		\
3602		dtrace_get_operand(x, REG_ONLY, reg, w2, 3);		\
3603		dtrace_imm_opnd(x, wbit, immsize, 1);			\
3604		dtrace_imm_opnd(x, wbit, immsize, 0);			\
3605}
3606
3607/*
3608 * 1 operands plus two immediates.
3609 */
3610#define	ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \
3611		dtrace_get_modrm(x, &mode, &reg, &r_m);			\
3612		dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);	\
3613		dtrace_get_operand(x, mode, r_m, wbit, 2);		\
3614		dtrace_imm_opnd(x, wbit, immsize, 1);			\
3615		dtrace_imm_opnd(x, wbit, immsize, 0);			\
3616}
3617
3618/*
3619 * Dissassemble a single x86 or amd64 instruction.
3620 *
3621 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64)
3622 * for interpreting instructions.
3623 *
3624 * returns non-zero for bad opcode
3625 */
3626int
3627dtrace_disx86(dis86_t *x, uint_t cpu_mode)
3628{
3629	const instable_t *dp = NULL;	/* decode table being used */
3630#ifdef DIS_TEXT
3631	uint_t i;
3632#endif
3633#ifdef DIS_MEM
3634	uint_t nomem = 0;
3635#define	NOMEM	(nomem = 1)
3636#else
3637#define	NOMEM	/* nothing */
3638#endif
3639	uint_t opnd_size;	/* SIZE16, SIZE32 or SIZE64 */
3640	uint_t addr_size;	/* SIZE16, SIZE32 or SIZE64 */
3641	uint_t wbit;		/* opcode wbit, 0 is 8 bit, !0 for opnd_size */
3642	uint_t w2;		/* wbit value for second operand */
3643	uint_t vbit;
3644	uint_t mode = 0;	/* mode value from ModRM byte */
3645	uint_t reg;		/* reg value from ModRM byte */
3646	uint_t r_m;		/* r_m value from ModRM byte */
3647
3648	uint_t opcode1;		/* high nibble of 1st byte */
3649	uint_t opcode2;		/* low nibble of 1st byte */
3650	uint_t opcode3;		/* extra opcode bits usually from ModRM byte */
3651	uint_t opcode4;		/* high nibble of 2nd byte */
3652	uint_t opcode5;		/* low nibble of 2nd byte */
3653	uint_t opcode6;		/* high nibble of 3rd byte */
3654	uint_t opcode7;		/* low nibble of 3rd byte */
3655	uint_t opcode8;		/* high nibble of 4th byte */
3656	uint_t opcode9;		/* low nibble of 4th byte */
3657	uint_t opcode_bytes = 1;
3658
3659	/*
3660	 * legacy prefixes come in 5 flavors, you should have only one of each
3661	 */
3662	uint_t	opnd_size_prefix = 0;
3663	uint_t	addr_size_prefix = 0;
3664	uint_t	segment_prefix = 0;
3665	uint_t	lock_prefix = 0;
3666	uint_t	rep_prefix = 0;
3667	uint_t	rex_prefix = 0;	/* amd64 register extension prefix */
3668
3669	/*
3670	 * Intel VEX instruction encoding prefix and fields
3671	 */
3672
3673	/* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */
3674	uint_t vex_prefix = 0;
3675
3676	/*
3677	 * VEX prefix byte 1, includes vex.r, vex.x and vex.b
3678	 * (for 3 bytes prefix)
3679	 */
3680	uint_t vex_byte1 = 0;
3681
3682	/*
3683	 * EVEX prefix byte 1 includes vex.r, vex.x, vex.b and evex.r.
3684	 */
3685	uint_t evex_byte1 = 0;
3686	uint_t evex_byte2 = 0;
3687	uint_t evex_byte3 = 0;
3688
3689	/*
3690	 * For 32-bit mode, it should prefetch the next byte to
3691	 * distinguish between AVX and les/lds
3692	 */
3693	uint_t vex_prefetch = 0;
3694
3695	uint_t vex_m = 0;
3696	uint_t vex_v = 0;
3697	uint_t vex_p = 0;
3698	uint_t vex_R = 1;
3699	uint_t vex_X = 1;
3700	uint_t vex_B = 1;
3701	uint_t vex_W = 0;
3702	uint_t vex_L = 0;
3703	uint_t evex_L = 0;
3704	uint_t evex_modrm = 0;
3705	uint_t evex_prefix = 0;
3706	dis_gather_regs_t *vreg;
3707
3708#ifdef	DIS_TEXT
3709	/* Instruction name for BLS* family of instructions */
3710	char *blsinstr;
3711#endif
3712
3713	size_t	off;
3714
3715	instable_t dp_mmx;
3716
3717	x->d86_len = 0;
3718	x->d86_rmindex = -1;
3719	x->d86_error = 0;
3720#ifdef DIS_TEXT
3721	x->d86_numopnds = 0;
3722	x->d86_seg_prefix = NULL;
3723	x->d86_mnem[0] = 0;
3724	for (i = 0; i < 4; ++i) {
3725		x->d86_opnd[i].d86_opnd[0] = 0;
3726		x->d86_opnd[i].d86_prefix[0] = 0;
3727		x->d86_opnd[i].d86_value_size = 0;
3728		x->d86_opnd[i].d86_value = 0;
3729		x->d86_opnd[i].d86_mode = MODE_NONE;
3730	}
3731#endif
3732	x->d86_rex_prefix = 0;
3733	x->d86_got_modrm = 0;
3734	x->d86_memsize = 0;
3735	x->d86_vsib = 0;
3736
3737	if (cpu_mode == SIZE16) {
3738		opnd_size = SIZE16;
3739		addr_size = SIZE16;
3740	} else if (cpu_mode == SIZE32) {
3741		opnd_size = SIZE32;
3742		addr_size = SIZE32;
3743	} else {
3744		opnd_size = SIZE32;
3745		addr_size = SIZE64;
3746	}
3747
3748	/*
3749	 * Get one opcode byte and check for zero padding that follows
3750	 * jump tables.
3751	 */
3752	if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3753		goto error;
3754
3755	if (opcode1 == 0 && opcode2 == 0 &&
3756	    x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) {
3757#ifdef DIS_TEXT
3758		(void) strncpy(x->d86_mnem, ".byte\t0", OPLEN);
3759#endif
3760		goto done;
3761	}
3762
3763	/*
3764	 * Gather up legacy x86 prefix bytes.
3765	 */
3766	for (;;) {
3767		uint_t *which_prefix = NULL;
3768
3769		dp = (instable_t *)&dis_distable[opcode1][opcode2];
3770
3771		switch (dp->it_adrmode) {
3772		case PREFIX:
3773			which_prefix = &rep_prefix;
3774			break;
3775		case LOCK:
3776			which_prefix = &lock_prefix;
3777			break;
3778		case OVERRIDE:
3779			which_prefix = &segment_prefix;
3780#ifdef DIS_TEXT
3781			x->d86_seg_prefix = (char *)dp->it_name;
3782#endif
3783			if (dp->it_invalid64 && cpu_mode == SIZE64)
3784				goto error;
3785			break;
3786		case AM:
3787			which_prefix = &addr_size_prefix;
3788			break;
3789		case DM:
3790			which_prefix = &opnd_size_prefix;
3791			break;
3792		}
3793		if (which_prefix == NULL)
3794			break;
3795		*which_prefix = (opcode1 << 4) | opcode2;
3796		if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3797			goto error;
3798	}
3799
3800	/*
3801	 * Handle amd64 mode PREFIX values.
3802	 * Some of the segment prefixes are no-ops. (only FS/GS actually work)
3803	 * We might have a REX prefix (opcodes 0x40-0x4f)
3804	 */
3805	if (cpu_mode == SIZE64) {
3806		if (segment_prefix != 0x64 && segment_prefix != 0x65)
3807			segment_prefix = 0;
3808
3809		if (opcode1 == 0x4) {
3810			rex_prefix = (opcode1 << 4) | opcode2;
3811			if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3812				goto error;
3813			dp = (instable_t *)&dis_distable[opcode1][opcode2];
3814		} else if (opcode1 == 0xC &&
3815		    (opcode2 == 0x4 || opcode2 == 0x5)) {
3816			/* AVX instructions */
3817			vex_prefix = (opcode1 << 4) | opcode2;
3818			x->d86_rex_prefix = 0x40;
3819		}
3820	} else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) {
3821		/* LDS, LES or AVX */
3822		dtrace_get_modrm(x, &mode, &reg, &r_m);
3823		vex_prefetch = 1;
3824
3825		if (mode == REG_ONLY) {
3826			/* AVX */
3827			vex_prefix = (opcode1 << 4) | opcode2;
3828			x->d86_rex_prefix = 0x40;
3829			opcode3 = (((mode << 3) | reg)>>1) & 0x0F;
3830			opcode4 = ((reg << 3) | r_m) & 0x0F;
3831		}
3832	}
3833
3834	/*
3835	 * The EVEX prefix and "bound" instruction share the same first byte.
3836	 * "bound" is only valid for 32-bit. For 64-bit this byte begins the
3837	 * EVEX prefix and the 2nd byte must have bits 2 & 3 set to 0.
3838	 */
3839	if (opcode1 == 0x6 && opcode2 == 0x2) {
3840		evex_prefix = 0x62;
3841
3842		/*
3843		 * An EVEX prefix is 4 bytes long, get the next 3 bytes.
3844		 */
3845		if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0)
3846			goto error;
3847
3848		if (addr_size == SIZE32 && (opcode4 & 0xf) == 0) {
3849			/*
3850			 * Upper bits in 2nd byte == 0 is 'bound' instn.
3851			 *
3852			 * We've already read the byte so perform the
3853			 * equivalent of dtrace_get_modrm on the byte and set
3854			 * the flag to indicate we've already read it.
3855			 */
3856			char b = (opcode4 << 4) | opcode5;
3857
3858			r_m = b & 0x7;
3859			reg = (b >> 3) & 0x7;
3860			mode = (b >> 6) & 0x3;
3861			vex_prefetch = 1;
3862			goto not_avx512;
3863		}
3864
3865		/* check for correct bits being 0 in 2nd byte */
3866		if ((opcode5 & 0xc) != 0)
3867			goto error;
3868
3869		if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
3870			goto error;
3871		/* check for correct bit being 1 in 3rd byte */
3872		if ((opcode7 & 0x4) == 0)
3873			goto error;
3874
3875		if (dtrace_get_opcode(x, &opcode8, &opcode9) != 0)
3876			goto error;
3877
3878		/* Reuse opcode1 & opcode2 to get the real opcode now */
3879		if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3880			goto error;
3881
3882		/*
3883		 * We only use the high nibble from the 2nd byte of the prefix
3884		 * and save it in the low bits of evex_byte1. This is because
3885		 * two of the bits in opcode5 are constant 0 (checked above),
3886		 * and the other two bits are captured in vex_m. Also, the VEX
3887		 * constants we check in evex_byte1 are against the low bits.
3888		 */
3889		evex_byte1 = opcode4;
3890		evex_byte2 = (opcode6 << 4) | opcode7;
3891		evex_byte3 = (opcode8 << 4) | opcode9;
3892
3893		vex_m = opcode5 & EVEX_m;
3894		vex_v = (((opcode6 << 4) | opcode7) & VEX_v) >> 3;
3895		vex_W = (opcode6 & VEX_W) >> 3;
3896		vex_p = opcode7 & VEX_p;
3897
3898		/*
3899		 * Store the corresponding prefix information for later use when
3900		 * calculating the SIB.
3901		 */
3902		if ((evex_byte1 & VEX_R) == 0)
3903			x->d86_rex_prefix |= REX_R;
3904		if ((evex_byte1 & VEX_X) == 0)
3905			x->d86_rex_prefix |= REX_X;
3906		if ((evex_byte1 & VEX_B) == 0)
3907			x->d86_rex_prefix |= REX_B;
3908
3909		/* Currently only 3 valid values for evex L'L: 00, 01, 10 */
3910		evex_L = (opcode8 & EVEX_L) >> 1;
3911
3912		switch (vex_p) {
3913		case VEX_p_66:
3914			switch (vex_m) {
3915			case VEX_m_0F:
3916				dp = &dis_opEVEX660F[(opcode1 << 4) | opcode2];
3917				break;
3918			case VEX_m_0F38:
3919				dp = &dis_opEVEX660F38[(opcode1 << 4) |
3920				    opcode2];
3921				break;
3922			case VEX_m_0F3A:
3923				dp = &dis_opEVEX660F3A[(opcode1 << 4) |
3924				    opcode2];
3925				break;
3926			default:
3927				goto error;
3928			}
3929			break;
3930		case VEX_p_F3:
3931			switch (vex_m) {
3932			case VEX_m_0F:
3933				dp = &dis_opEVEXF30F[(opcode1 << 4) | opcode2];
3934				break;
3935			default:
3936				goto error;
3937			}
3938			break;
3939		case VEX_p_F2:
3940			switch (vex_m) {
3941			case VEX_m_0F:
3942				dp = &dis_opEVEXF20F[(opcode1 << 4) | opcode2];
3943				break;
3944			default:
3945				goto error;
3946			}
3947			break;
3948		default:
3949			dp = &dis_opEVEX0F[(opcode1 << 4) | opcode2];
3950			break;
3951		}
3952	}
3953not_avx512:
3954
3955	if (vex_prefix == VEX_2bytes) {
3956		if (!vex_prefetch) {
3957			if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0)
3958				goto error;
3959		}
3960		vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3;
3961		vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2;
3962		vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3;
3963		vex_p = opcode4 & VEX_p;
3964		/*
3965		 * The vex.x and vex.b bits are not defined in two bytes
3966		 * mode vex prefix, their default values are 1
3967		 */
3968		vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B;
3969
3970		if (vex_R == 0)
3971			x->d86_rex_prefix |= REX_R;
3972
3973		if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3974			goto error;
3975
3976		switch (vex_p) {
3977			case VEX_p_66:
3978				dp = (instable_t *)
3979				    &dis_opAVX660F[(opcode1 << 4) | opcode2];
3980				break;
3981			case VEX_p_F3:
3982				dp = (instable_t *)
3983				    &dis_opAVXF30F[(opcode1 << 4) | opcode2];
3984				break;
3985			case VEX_p_F2:
3986				dp = (instable_t *)
3987				    &dis_opAVXF20F [(opcode1 << 4) | opcode2];
3988				break;
3989			default:
3990				dp = (instable_t *)
3991				    &dis_opAVX0F[opcode1][opcode2];
3992
3993		}
3994
3995	} else if (vex_prefix == VEX_3bytes) {
3996		if (!vex_prefetch) {
3997			if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0)
3998				goto error;
3999		}
4000		vex_R = (opcode3 & VEX_R) >> 3;
4001		vex_X = (opcode3 & VEX_X) >> 2;
4002		vex_B = (opcode3 & VEX_B) >> 1;
4003		vex_m = (((opcode3 << 4) | opcode4) & VEX_m);
4004		vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B);
4005
4006		if (vex_R == 0)
4007			x->d86_rex_prefix |= REX_R;
4008		if (vex_X == 0)
4009			x->d86_rex_prefix |= REX_X;
4010		if (vex_B == 0)
4011			x->d86_rex_prefix |= REX_B;
4012
4013		if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0)
4014			goto error;
4015		vex_W = (opcode5 & VEX_W) >> 3;
4016		vex_L = (opcode6 & VEX_L) >> 2;
4017		vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3;
4018		vex_p = opcode6 & VEX_p;
4019
4020		if (vex_W)
4021			x->d86_rex_prefix |= REX_W;
4022
4023		/* Only these three vex_m values valid; others are reserved */
4024		if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) &&
4025		    (vex_m != VEX_m_0F3A))
4026			goto error;
4027
4028		if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
4029			goto error;
4030
4031		switch (vex_p) {
4032			case VEX_p_66:
4033				if (vex_m == VEX_m_0F) {
4034					dp = (instable_t *)
4035					    &dis_opAVX660F
4036					    [(opcode1 << 4) | opcode2];
4037				} else if (vex_m == VEX_m_0F38) {
4038					dp = (instable_t *)
4039					    &dis_opAVX660F38
4040					    [(opcode1 << 4) | opcode2];
4041				} else if (vex_m == VEX_m_0F3A) {
4042					dp = (instable_t *)
4043					    &dis_opAVX660F3A
4044					    [(opcode1 << 4) | opcode2];
4045				} else {
4046					goto error;
4047				}
4048				break;
4049			case VEX_p_F3:
4050				if (vex_m == VEX_m_0F) {
4051					dp = (instable_t *)
4052					    &dis_opAVXF30F
4053					    [(opcode1 << 4) | opcode2];
4054				} else if (vex_m == VEX_m_0F38) {
4055					dp = (instable_t *)
4056					    &dis_opAVXF30F38
4057					    [(opcode1 << 4) | opcode2];
4058				} else {
4059					goto error;
4060				}
4061				break;
4062			case VEX_p_F2:
4063				if (vex_m == VEX_m_0F) {
4064					dp = (instable_t *)
4065					    &dis_opAVXF20F
4066					    [(opcode1 << 4) | opcode2];
4067				} else if (vex_m == VEX_m_0F3A) {
4068					dp = (instable_t *)
4069					    &dis_opAVXF20F3A
4070					    [(opcode1 << 4) | opcode2];
4071				} else if (vex_m == VEX_m_0F38) {
4072					dp = (instable_t *)
4073					    &dis_opAVXF20F38
4074					    [(opcode1 << 4) | opcode2];
4075				} else {
4076					goto error;
4077				}
4078				break;
4079			default:
4080				dp = (instable_t *)
4081				    &dis_opAVX0F[opcode1][opcode2];
4082
4083		}
4084	}
4085	if (vex_prefix) {
4086		if (dp->it_vexwoxmm) {
4087			wbit = LONG_OPND;
4088		} else if (dp->it_vexopmask) {
4089			wbit = KOPMASK_OPND;
4090		} else {
4091			if (vex_L) {
4092				wbit = YMM_OPND;
4093			} else {
4094				wbit = XMM_OPND;
4095			}
4096		}
4097	}
4098
4099	/*
4100	 * Deal with selection of operand and address size now.
4101	 * Note that the REX.W bit being set causes opnd_size_prefix to be
4102	 * ignored.
4103	 */
4104	if (cpu_mode == SIZE64) {
4105		if ((rex_prefix & REX_W) || vex_W)
4106			opnd_size = SIZE64;
4107		else if (opnd_size_prefix)
4108			opnd_size = SIZE16;
4109
4110		if (addr_size_prefix)
4111			addr_size = SIZE32;
4112	} else if (cpu_mode == SIZE32) {
4113		if (opnd_size_prefix)
4114			opnd_size = SIZE16;
4115		if (addr_size_prefix)
4116			addr_size = SIZE16;
4117	} else {
4118		if (opnd_size_prefix)
4119			opnd_size = SIZE32;
4120		if (addr_size_prefix)
4121			addr_size = SIZE32;
4122	}
4123	/*
4124	 * The pause instruction - a repz'd nop.  This doesn't fit
4125	 * with any of the other prefix goop added for SSE, so we'll
4126	 * special-case it here.
4127	 */
4128	if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) {
4129		rep_prefix = 0;
4130		dp = (instable_t *)&dis_opPause;
4131	}
4132
4133	/*
4134	 * Some 386 instructions have 2 bytes of opcode before the mod_r/m
4135	 * byte so we may need to perform a table indirection.
4136	 */
4137	if (dp->it_indirect == (instable_t *)dis_op0F) {
4138		if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0)
4139			goto error;
4140		opcode_bytes = 2;
4141		if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) {
4142			uint_t	subcode;
4143
4144			if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
4145				goto error;
4146			opcode_bytes = 3;
4147			subcode = ((opcode6 & 0x3) << 1) |
4148			    ((opcode7 & 0x8) >> 3);
4149			dp = (instable_t *)&dis_op0F7123[opcode5][subcode];
4150		} else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) {
4151			dp = (instable_t *)&dis_op0FC8[0];
4152		} else if ((opcode4 == 0x3) && (opcode5 == 0xA)) {
4153			opcode_bytes = 3;
4154			if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
4155				goto error;
4156			if (opnd_size == SIZE16)
4157				opnd_size = SIZE32;
4158
4159			dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7];
4160#ifdef DIS_TEXT
4161			if (strcmp(dp->it_name, "INVALID") == 0)
4162				goto error;
4163#endif
4164			switch (dp->it_adrmode) {
4165				case XMMP:
4166					break;
4167				case XMMP_66r:
4168				case XMMPRM_66r:
4169				case XMM3PM_66r:
4170					if (opnd_size_prefix == 0) {
4171						goto error;
4172					}
4173
4174					break;
4175				case XMMP_66o:
4176					if (opnd_size_prefix == 0) {
4177						/* SSSE3 MMX instructions */
4178						dp_mmx = *dp;
4179						dp_mmx.it_adrmode = MMOPM_66o;
4180#ifdef	DIS_MEM
4181						dp_mmx.it_size = 8;
4182#endif
4183						dp = &dp_mmx;
4184					}
4185					break;
4186				default:
4187					goto error;
4188			}
4189		} else if ((opcode4 == 0x3) && (opcode5 == 0x8)) {
4190			opcode_bytes = 3;
4191			if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
4192				goto error;
4193			dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7];
4194
4195			/*
4196			 * Both crc32 and movbe have the same 3rd opcode
4197			 * byte of either 0xF0 or 0xF1, so we use another
4198			 * indirection to distinguish between the two.
4199			 */
4200			if (dp->it_indirect == (instable_t *)dis_op0F38F0 ||
4201			    dp->it_indirect == (instable_t *)dis_op0F38F1) {
4202
4203				dp = dp->it_indirect;