1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 /* 27 * Copyright (c) 2018, Joyent, Inc. 28 * Copyright 2019 Doma Gergő Mihály <doma.gergo.mihaly@gmail.com> 29 */ 30 31 /* 32 * User Process Target Intel 32-bit component 33 * 34 * This file provides the ISA-dependent portion of the user process target. 35 * For more details on the implementation refer to mdb_proc.c. 36 */ 37 38 #include <mdb/mdb_proc.h> 39 #include <mdb/mdb_kreg.h> 40 #include <mdb/mdb_err.h> 41 #include <mdb/mdb_amd64util.h> 42 #include <mdb/mdb.h> 43 44 #include <sys/ucontext.h> 45 #include <sys/frame.h> 46 #include <libproc.h> 47 #include <sys/fp.h> 48 #include <ieeefp.h> 49 50 #include <stddef.h> 51 52 const mdb_tgt_regdesc_t pt_regdesc[] = { 53 { "r15", REG_R15, MDB_TGT_R_EXPORT }, 54 { "r15d", REG_R15, MDB_TGT_R_EXPORT | MDB_TGT_R_32 }, 55 { "r15w", REG_R15, MDB_TGT_R_EXPORT | MDB_TGT_R_16 }, 56 { "r15l", REG_R15, MDB_TGT_R_EXPORT | MDB_TGT_R_8L }, 57 { "r14", REG_R14, MDB_TGT_R_EXPORT }, 58 { "r14d", REG_R14, MDB_TGT_R_EXPORT | MDB_TGT_R_32 }, 59 { "r14w", REG_R14, MDB_TGT_R_EXPORT | MDB_TGT_R_16 }, 60 { "r14l", REG_R14, MDB_TGT_R_EXPORT | MDB_TGT_R_8L }, 61 { "r13", REG_R13, MDB_TGT_R_EXPORT }, 62 { "r13d", REG_R13, MDB_TGT_R_EXPORT | MDB_TGT_R_32 }, 63 { "r13w", REG_R13, MDB_TGT_R_EXPORT | MDB_TGT_R_16 }, 64 { "r13l", REG_R13, MDB_TGT_R_EXPORT | MDB_TGT_R_8L }, 65 { "r12", REG_R12, MDB_TGT_R_EXPORT }, 66 { "r12d", REG_R12, MDB_TGT_R_EXPORT | MDB_TGT_R_32 }, 67 { "r12w", REG_R12, MDB_TGT_R_EXPORT | MDB_TGT_R_16 }, 68 { "r12l", REG_R12, MDB_TGT_R_EXPORT | MDB_TGT_R_8L }, 69 { "r11", REG_R11, MDB_TGT_R_EXPORT }, 70 { "r11d", REG_R11, MDB_TGT_R_EXPORT | MDB_TGT_R_32 }, 71 { "r11w", REG_R11, MDB_TGT_R_EXPORT | MDB_TGT_R_16 }, 72 { "r11l", REG_R11, MDB_TGT_R_EXPORT | MDB_TGT_R_8L }, 73 { "r10", REG_R10, MDB_TGT_R_EXPORT }, 74 { "r10d", REG_R10, MDB_TGT_R_EXPORT | MDB_TGT_R_32 }, 75 { "r10w", REG_R10, MDB_TGT_R_EXPORT | MDB_TGT_R_16 }, 76 { "r10l", REG_R10, MDB_TGT_R_EXPORT | MDB_TGT_R_8L }, 77 { "r9", REG_R9, MDB_TGT_R_EXPORT }, 78 { "r9d", REG_R9, MDB_TGT_R_EXPORT | MDB_TGT_R_32 }, 79 { "r9w", REG_R9, MDB_TGT_R_EXPORT | MDB_TGT_R_16 }, 80 { "r9l", REG_R9, MDB_TGT_R_EXPORT | MDB_TGT_R_8L }, 81 { "r8", REG_R8, MDB_TGT_R_EXPORT }, 82 { "r8d", REG_R8, MDB_TGT_R_EXPORT | MDB_TGT_R_32 }, 83 { "r8w", REG_R8, MDB_TGT_R_EXPORT | MDB_TGT_R_16 }, 84 { "r8l", REG_R8, MDB_TGT_R_EXPORT | MDB_TGT_R_8L }, 85 { "rdi", REG_RDI, MDB_TGT_R_EXPORT }, 86 { "edi", REG_RDI, MDB_TGT_R_EXPORT | MDB_TGT_R_32 }, 87 { "di", REG_RDI, MDB_TGT_R_EXPORT | MDB_TGT_R_16 }, 88 { "dil", REG_RDI, MDB_TGT_R_EXPORT | MDB_TGT_R_8L }, 89 { "rsi", REG_RSI, MDB_TGT_R_EXPORT }, 90 { "esi", REG_RSI, MDB_TGT_R_EXPORT | MDB_TGT_R_32 }, 91 { "si", REG_RSI, MDB_TGT_R_EXPORT | MDB_TGT_R_16 }, 92 { "sil", REG_RSI, MDB_TGT_R_EXPORT | MDB_TGT_R_8L }, 93 { "rbp", REG_RBP, MDB_TGT_R_EXPORT }, 94 { "ebp", REG_RBP, MDB_TGT_R_EXPORT | MDB_TGT_R_32 }, 95 { "bp", REG_RBP, MDB_TGT_R_EXPORT | MDB_TGT_R_16 }, 96 { "bpl", REG_RBP, MDB_TGT_R_EXPORT | MDB_TGT_R_8L }, 97 { "rbx", REG_RBX, MDB_TGT_R_EXPORT }, 98 { "ebx", REG_RBX, MDB_TGT_R_EXPORT | MDB_TGT_R_32 }, 99 { "bx", REG_RBX, MDB_TGT_R_EXPORT | MDB_TGT_R_16 }, 100 { "bh", REG_RBX, MDB_TGT_R_EXPORT | MDB_TGT_R_8H }, 101 { "bl", REG_RBX, MDB_TGT_R_EXPORT | MDB_TGT_R_8L }, 102 { "rdx", REG_RDX, MDB_TGT_R_EXPORT }, 103 { "edx", REG_RDX, MDB_TGT_R_EXPORT | MDB_TGT_R_32 }, 104 { "dx", REG_RDX, MDB_TGT_R_EXPORT | MDB_TGT_R_16 }, 105 { "dh", REG_RDX, MDB_TGT_R_EXPORT | MDB_TGT_R_8H }, 106 { "dl", REG_RDX, MDB_TGT_R_EXPORT | MDB_TGT_R_8L }, 107 { "rcx", REG_RCX, MDB_TGT_R_EXPORT }, 108 { "ecx", REG_RCX, MDB_TGT_R_EXPORT | MDB_TGT_R_32 }, 109 { "cx", REG_RCX, MDB_TGT_R_EXPORT | MDB_TGT_R_16 }, 110 { "ch", REG_RCX, MDB_TGT_R_EXPORT | MDB_TGT_R_8H }, 111 { "cl", REG_RCX, MDB_TGT_R_EXPORT | MDB_TGT_R_8L }, 112 { "rax", REG_RAX, MDB_TGT_R_EXPORT }, 113 { "eax", REG_RAX, MDB_TGT_R_EXPORT | MDB_TGT_R_32 }, 114 { "ax", REG_RAX, MDB_TGT_R_EXPORT | MDB_TGT_R_16 }, 115 { "ah", REG_RAX, MDB_TGT_R_EXPORT | MDB_TGT_R_8H }, 116 { "al", REG_RAX, MDB_TGT_R_EXPORT | MDB_TGT_R_8L }, 117 { "trapno", REG_TRAPNO, MDB_TGT_R_EXPORT }, 118 { "err", REG_ERR, MDB_TGT_R_EXPORT }, 119 { "rip", REG_RIP, MDB_TGT_R_EXPORT }, 120 { "cs", REG_CS, MDB_TGT_R_EXPORT }, 121 { "rflags", REG_RFL, MDB_TGT_R_EXPORT }, 122 { "eflags", REG_RFL, MDB_TGT_R_EXPORT | MDB_TGT_R_32 }, 123 { "rsp", REG_RSP, MDB_TGT_R_EXPORT }, 124 { "esp", REG_RSP, MDB_TGT_R_EXPORT | MDB_TGT_R_32 }, 125 { "sp", REG_RSP, MDB_TGT_R_EXPORT | MDB_TGT_R_16 }, 126 { "spl", REG_RSP, MDB_TGT_R_EXPORT | MDB_TGT_R_8L }, 127 { "ss", REG_SS, MDB_TGT_R_EXPORT }, 128 { "fs", REG_FS, MDB_TGT_R_EXPORT }, 129 { "gs", REG_GS, MDB_TGT_R_EXPORT }, 130 { "es", REG_ES, MDB_TGT_R_EXPORT }, 131 { "ds", REG_DS, MDB_TGT_R_EXPORT }, 132 { "fsbase", REG_FSBASE, MDB_TGT_R_EXPORT }, 133 { "gsbase", REG_GSBASE, MDB_TGT_R_EXPORT }, 134 { NULL, 0, 0 } 135 }; 136 137 /* 138 * We cannot rely on pr_instr, because if we hit a breakpoint or the user has 139 * artifically modified memory, it will no longer be correct. 140 */ 141 static uint8_t 142 pt_read_instr(mdb_tgt_t *t) 143 { 144 const lwpstatus_t *psp = &Pstatus(t->t_pshandle)->pr_lwp; 145 uint8_t ret = 0; 146 147 (void) mdb_tgt_vread(t, &ret, sizeof (ret), psp->pr_reg[REG_RIP]); 148 149 return (ret); 150 } 151 152 /*ARGSUSED*/ 153 int 154 pt_regs(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv) 155 { 156 mdb_tgt_t *t = mdb.m_target; 157 mdb_tgt_tid_t tid; 158 prgregset_t grs; 159 prgreg_t rflags; 160 boolean_t from_ucontext = B_FALSE; 161 162 if (mdb_getopts(argc, argv, 163 'u', MDB_OPT_SETBITS, B_TRUE, &from_ucontext, NULL) != argc) { 164 return (DCMD_USAGE); 165 } 166 167 if (from_ucontext) { 168 int off; 169 int o0, o1; 170 171 if (!(flags & DCMD_ADDRSPEC)) { 172 mdb_warn("-u requires a ucontext_t address\n"); 173 return (DCMD_ERR); 174 } 175 176 o0 = mdb_ctf_offsetof_by_name("ucontext_t", "uc_mcontext"); 177 o1 = mdb_ctf_offsetof_by_name("mcontext_t", "gregs"); 178 if (o0 == -1 || o1 == -1) { 179 off = offsetof(ucontext_t, uc_mcontext) + 180 offsetof(mcontext_t, gregs); 181 } else { 182 off = o0 + o1; 183 } 184 185 if (mdb_vread(&grs, sizeof (grs), addr + off) != sizeof (grs)) { 186 mdb_warn("failed to read from ucontext_t %p", addr); 187 return (DCMD_ERR); 188 } 189 goto print_regs; 190 } 191 192 if (t->t_pshandle == NULL || Pstate(t->t_pshandle) == PS_UNDEAD) { 193 mdb_warn("no process active\n"); 194 return (DCMD_ERR); 195 } 196 197 if (Pstate(t->t_pshandle) == PS_LOST) { 198 mdb_warn("debugger has lost control of process\n"); 199 return (DCMD_ERR); 200 } 201 202 if (flags & DCMD_ADDRSPEC) 203 tid = (mdb_tgt_tid_t)addr; 204 else 205 tid = PTL_TID(t); 206 207 if (PTL_GETREGS(t, tid, grs) != 0) { 208 mdb_warn("failed to get current register set"); 209 return (DCMD_ERR); 210 } 211 212 print_regs: 213 rflags = grs[REG_RFL]; 214 215 mdb_printf("%%rax = 0x%0?p\t%%r8 = 0x%0?p\n", 216 grs[REG_RAX], grs[REG_R8]); 217 mdb_printf("%%rbx = 0x%0?p\t%%r9 = 0x%0?p\n", 218 grs[REG_RBX], grs[REG_R9]); 219 mdb_printf("%%rcx = 0x%0?p\t%%r10 = 0x%0?p\n", 220 grs[REG_RCX], grs[REG_R10]); 221 mdb_printf("%%rdx = 0x%0?p\t%%r11 = 0x%0?p\n", 222 grs[REG_RDX], grs[REG_R11]); 223 mdb_printf("%%rsi = 0x%0?p\t%%r12 = 0x%0?p\n", 224 grs[REG_RSI], grs[REG_R12]); 225 mdb_printf("%%rdi = 0x%0?p\t%%r13 = 0x%0?p\n", 226 grs[REG_RDI], grs[REG_R13]); 227 mdb_printf(" %?s\t%%r14 = 0x%0?p\n", 228 "", grs[REG_R14]); 229 mdb_printf(" %?s\t%%r15 = 0x%0?p\n", 230 "", grs[REG_R15]); 231 232 mdb_printf("\n"); 233 234 mdb_printf("%%cs = 0x%04x\t%%fs = 0x%04x\t%%gs = 0x%04x\n", 235 grs[REG_CS], grs[REG_FS], grs[REG_GS]); 236 mdb_printf("%%ds = 0x%04x\t%%es = 0x%04x\t%%ss = 0x%04x\n", 237 grs[REG_DS], grs[REG_ES], grs[REG_SS]); 238 239 mdb_printf("\n"); 240 241 mdb_printf("%%rip = 0x%0?p %A\n", grs[REG_RIP], grs[REG_RIP]); 242 mdb_printf("%%rbp = 0x%0?p\n", grs[REG_RBP], grs[REG_RBP]); 243 mdb_printf("%%rsp = 0x%0?p\n", grs[REG_RSP], grs[REG_RSP]); 244 245 mdb_printf("\n"); 246 247 mdb_printf("%%rflags = 0x%08x\n", rflags); 248 249 mdb_printf(" id=%u vip=%u vif=%u ac=%u vm=%u rf=%u nt=%u iopl=0x%x\n", 250 (rflags & KREG_EFLAGS_ID_MASK) >> KREG_EFLAGS_ID_SHIFT, 251 (rflags & KREG_EFLAGS_VIP_MASK) >> KREG_EFLAGS_VIP_SHIFT, 252 (rflags & KREG_EFLAGS_VIF_MASK) >> KREG_EFLAGS_VIF_SHIFT, 253 (rflags & KREG_EFLAGS_AC_MASK) >> KREG_EFLAGS_AC_SHIFT, 254 (rflags & KREG_EFLAGS_VM_MASK) >> KREG_EFLAGS_VM_SHIFT, 255 (rflags & KREG_EFLAGS_RF_MASK) >> KREG_EFLAGS_RF_SHIFT, 256 (rflags & KREG_EFLAGS_NT_MASK) >> KREG_EFLAGS_NT_SHIFT, 257 (rflags & KREG_EFLAGS_IOPL_MASK) >> KREG_EFLAGS_IOPL_SHIFT); 258 259 mdb_printf(" status=<%s,%s,%s,%s,%s,%s,%s,%s,%s>\n", 260 (rflags & KREG_EFLAGS_OF_MASK) ? "OF" : "of", 261 (rflags & KREG_EFLAGS_DF_MASK) ? "DF" : "df", 262 (rflags & KREG_EFLAGS_IF_MASK) ? "IF" : "if", 263 (rflags & KREG_EFLAGS_TF_MASK) ? "TF" : "tf", 264 (rflags & KREG_EFLAGS_SF_MASK) ? "SF" : "sf", 265 (rflags & KREG_EFLAGS_ZF_MASK) ? "ZF" : "zf", 266 (rflags & KREG_EFLAGS_AF_MASK) ? "AF" : "af", 267 (rflags & KREG_EFLAGS_PF_MASK) ? "PF" : "pf", 268 (rflags & KREG_EFLAGS_CF_MASK) ? "CF" : "cf"); 269 270 mdb_printf("\n"); 271 272 mdb_printf("%%gsbase = 0x%0?p\n", grs[REG_GSBASE]); 273 mdb_printf("%%fsbase = 0x%0?p\n", grs[REG_FSBASE]); 274 mdb_printf("%%trapno = 0x%x\n", grs[REG_TRAPNO]); 275 mdb_printf(" %%err = 0x%x\n", grs[REG_ERR]); 276 277 return (set_errno(ENOTSUP)); 278 } 279 280 static const char * 281 fpcw2str(uint32_t cw, char *buf, size_t nbytes) 282 { 283 char *end = buf + nbytes; 284 char *p = buf; 285 286 buf[0] = '\0'; 287 288 /* 289 * Decode all exception masks in the x87 FPU Control Word. 290 * 291 * See here: 292 * Intel® 64 and IA-32 Architectures Software Developer’s Manual, 293 * Volume 1: Basic Architecture, 8.1.5 x87 FPU Control Word 294 */ 295 if (cw & FPIM) /* Invalid operation mask. */ 296 p += mdb_snprintf(p, (size_t)(end - p), "|IM"); 297 if (cw & FPDM) /* Denormalized operand mask. */ 298 p += mdb_snprintf(p, (size_t)(end - p), "|DM"); 299 if (cw & FPZM) /* Zero divide mask. */ 300 p += mdb_snprintf(p, (size_t)(end - p), "|ZM"); 301 if (cw & FPOM) /* Overflow mask. */ 302 p += mdb_snprintf(p, (size_t)(end - p), "|OM"); 303 if (cw & FPUM) /* Underflow mask. */ 304 p += mdb_snprintf(p, (size_t)(end - p), "|UM"); 305 if (cw & FPPM) /* Precision mask. */ 306 p += mdb_snprintf(p, (size_t)(end - p), "|PM"); 307 308 /* 309 * Decode precision control options. 310 */ 311 switch (cw & FPPC) { 312 case FPSIG24: 313 /* 24-bit significand, single precision. */ 314 p += mdb_snprintf(p, (size_t)(end - p), "|SIG24"); 315 break; 316 case FPSIG53: 317 /* 53-bit significand, double precision. */ 318 p += mdb_snprintf(p, (size_t)(end - p), "|SIG53"); 319 break; 320 case FPSIG64: 321 /* 64-bit significand, double extended precision. */ 322 p += mdb_snprintf(p, (size_t)(end - p), "|SIG64"); 323 break; 324 default: 325 /* 326 * Should never happen. 327 * Value 0x00000100 is 'Reserved'. 328 */ 329 break; 330 } 331 332 /* 333 * Decode rounding control options. 334 */ 335 switch (cw & FPRC) { 336 case FPRTN: 337 /* Round to nearest, or to even if equidistant. */ 338 p += mdb_snprintf(p, (size_t)(end - p), "|RTN"); 339 break; 340 case FPRD: 341 /* Round down. */ 342 p += mdb_snprintf(p, (size_t)(end - p), "|RD"); 343 break; 344 case FPRU: 345 /* Round up. */ 346 p += mdb_snprintf(p, (size_t)(end - p), "|RU"); 347 break; 348 case FPCHOP: 349 /* Truncate. */ 350 p += mdb_snprintf(p, (size_t)(end - p), "|RTZ"); 351 break; 352 default: 353 /* 354 * This is a two-bit field. 355 * No other options left. 356 */ 357 break; 358 } 359 360 /* 361 * Decode infinity control options. 362 * 363 * This field has been retained for compatibility with 364 * the 287 and earlier co-processors. 365 * In the more modern FPUs, this bit is disregarded and 366 * both -infinity and +infinity are respected. 367 * Comment source: SIMPLY FPU by Raymond Filiatreault 368 */ 369 switch (cw & FPIC) { 370 case FPP: 371 /* 372 * Projective infinity. 373 * Both -infinity and +infinity are treated as 374 * unsigned infinity. 375 */ 376 p += mdb_snprintf(p, (size_t)(end - p), "|P"); 377 break; 378 case FPA: 379 /* 380 * Affine infinity. 381 * Respects both -infinity and +infinity. 382 */ 383 p += mdb_snprintf(p, (size_t)(end - p), "|A"); 384 break; 385 default: 386 /* 387 * This is a one-bit field. 388 * No other options left. 389 */ 390 break; 391 } 392 393 if (cw & WFPB17) 394 p += mdb_snprintf(p, (size_t)(end - p), "|WFPB17"); 395 if (cw & WFPB24) 396 p += mdb_snprintf(p, (size_t)(end - p), "|WFPB24"); 397 398 if (buf[0] == '|') 399 return (buf + 1); 400 401 return ("0"); 402 } 403 404 static const char * 405 fpsw2str(uint32_t cw, char *buf, size_t nbytes) 406 { 407 char *end = buf + nbytes; 408 char *p = buf; 409 410 buf[0] = '\0'; 411 412 /* 413 * Decode all masks in the 80387 status word. 414 */ 415 if (cw & FPS_IE) 416 p += mdb_snprintf(p, (size_t)(end - p), "|IE"); 417 if (cw & FPS_DE) 418 p += mdb_snprintf(p, (size_t)(end - p), "|DE"); 419 if (cw & FPS_ZE) 420 p += mdb_snprintf(p, (size_t)(end - p), "|ZE"); 421 if (cw & FPS_OE) 422 p += mdb_snprintf(p, (size_t)(end - p), "|OE"); 423 if (cw & FPS_UE) 424 p += mdb_snprintf(p, (size_t)(end - p), "|UE"); 425 if (cw & FPS_PE) 426 p += mdb_snprintf(p, (size_t)(end - p), "|PE"); 427 if (cw & FPS_SF) 428 p += mdb_snprintf(p, (size_t)(end - p), "|SF"); 429 if (cw & FPS_ES) 430 p += mdb_snprintf(p, (size_t)(end - p), "|ES"); 431 if (cw & FPS_C0) 432 p += mdb_snprintf(p, (size_t)(end - p), "|C0"); 433 if (cw & FPS_C1) 434 p += mdb_snprintf(p, (size_t)(end - p), "|C1"); 435 if (cw & FPS_C2) 436 p += mdb_snprintf(p, (size_t)(end - p), "|C2"); 437 if (cw & FPS_C3) 438 p += mdb_snprintf(p, (size_t)(end - p), "|C3"); 439 if (cw & FPS_B) 440 p += mdb_snprintf(p, (size_t)(end - p), "|B"); 441 442 if (buf[0] == '|') 443 return (buf + 1); 444 445 return ("0"); 446 } 447 448 static const char * 449 fpmxcsr2str(uint32_t mxcsr, char *buf, size_t nbytes) 450 { 451 char *end = buf + nbytes; 452 char *p = buf; 453 454 buf[0] = '\0'; 455 456 /* 457 * Decode the MXCSR word 458 */ 459 if (mxcsr & SSE_IE) 460 p += mdb_snprintf(p, (size_t)(end - p), "|IE"); 461 if (mxcsr & SSE_DE) 462 p += mdb_snprintf(p, (size_t)(end - p), "|DE"); 463 if (mxcsr & SSE_ZE) 464 p += mdb_snprintf(p, (size_t)(end - p), "|ZE"); 465 if (mxcsr & SSE_OE) 466 p += mdb_snprintf(p, (size_t)(end - p), "|OE"); 467 if (mxcsr & SSE_UE) 468 p += mdb_snprintf(p, (size_t)(end - p), "|UE"); 469 if (mxcsr & SSE_PE) 470 p += mdb_snprintf(p, (size_t)(end - p), "|PE"); 471 472 if (mxcsr & SSE_DAZ) 473 p += mdb_snprintf(p, (size_t)(end - p), "|DAZ"); 474 475 if (mxcsr & SSE_IM) 476 p += mdb_snprintf(p, (size_t)(end - p), "|IM"); 477 if (mxcsr & SSE_DM) 478 p += mdb_snprintf(p, (size_t)(end - p), "|DM"); 479 if (mxcsr & SSE_ZM) 480 p += mdb_snprintf(p, (size_t)(end - p), "|ZM"); 481 if (mxcsr & SSE_OM) 482 p += mdb_snprintf(p, (size_t)(end - p), "|OM"); 483 if (mxcsr & SSE_UM) 484 p += mdb_snprintf(p, (size_t)(end - p), "|UM"); 485 if (mxcsr & SSE_PM) 486 p += mdb_snprintf(p, (size_t)(end - p), "|PM"); 487 488 if ((mxcsr & SSE_RC) == (SSE_RD|SSE_RU)) 489 p += mdb_snprintf(p, (size_t)(end - p), "|RTZ"); 490 else if (mxcsr & SSE_RD) 491 p += mdb_snprintf(p, (size_t)(end - p), "|RD"); 492 else if (mxcsr & SSE_RU) 493 p += mdb_snprintf(p, (size_t)(end - p), "|RU"); 494 else 495 p += mdb_snprintf(p, (size_t)(end - p), "|RTN"); 496 497 if (mxcsr & SSE_FZ) 498 p += mdb_snprintf(p, (size_t)(end - p), "|FZ"); 499 500 if (buf[0] == '|') 501 return (buf + 1); 502 return ("0"); 503 } 504 505 /*ARGSUSED*/ 506 int 507 pt_fpregs(uintptr_t addr, uint_t flags, int argc, const mdb_arg_t *argv) 508 { 509 mdb_tgt_t *t = mdb.m_target; 510 mdb_tgt_tid_t tid; 511 prfpregset_t fprs; 512 struct _fpchip_state fps; 513 char buf[256]; 514 uint_t top; 515 int i; 516 517 /* 518 * Union for overlaying _fpreg structure on to quad-precision 519 * floating-point value (long double). 520 */ 521 union { 522 struct _fpreg reg; 523 long double ld; 524 } fpru; 525 526 /* 527 * Array of strings corresponding to FPU tag word values (see 528 * section 7.3.6 of the Intel Programmer's Reference Manual). 529 */ 530 const char *tag_strings[] = { "valid", "zero", "special", "empty" }; 531 532 if (argc != 0) 533 return (DCMD_USAGE); 534 535 if (t->t_pshandle == NULL || Pstate(t->t_pshandle) == PS_UNDEAD) { 536 mdb_warn("no process active\n"); 537 return (DCMD_ERR); 538 } 539 540 if (Pstate(t->t_pshandle) == PS_LOST) { 541 mdb_warn("debugger has lost control of process\n"); 542 return (DCMD_ERR); 543 } 544 545 if (flags & DCMD_ADDRSPEC) 546 tid = (mdb_tgt_tid_t)addr; 547 else 548 tid = PTL_TID(t); 549 550 mdb_printf("AMD64 (80486 chip with SSE)\n"); 551 552 if (PTL_GETFPREGS(t, tid, &fprs) != 0) { 553 mdb_warn("failed to get floating point registers"); 554 return (DCMD_ERR); 555 } 556 557 bcopy(&fprs.fp_reg_set.fpchip_state, &fps, sizeof (fps)); 558 559 fps.status &= 0xffff; /* saved status word is really 16 bits */ 560 561 mdb_printf("cw 0x%04x (%s)\n", fps.cw, 562 fpcw2str(fps.cw, buf, sizeof (buf))); 563 564 top = (fps.sw & FPS_TOP) >> 11; 565 mdb_printf("sw 0x%04x (TOP=0t%u) (%s)\n", fps.sw, 566 top, fpsw2str(fps.sw, buf, sizeof (buf))); 567 568 mdb_printf("xcp sw 0x%04x (%s)\n\n", fps.status, 569 fpsw2str(fps.status, buf, sizeof (buf))); 570 571 mdb_printf("fop 0x%x\n", fps.fop); 572 mdb_printf("rip 0x%x\n", fps.rip); 573 mdb_printf("rdp 0x%x\n\n", fps.rdp); 574 575 for (i = 0; i < 8; i++) { 576 /* 577 * Recall that we need to use the current TOP-of-stack value to 578 * associate the _st[] index back to a physical register number, 579 * since tag word indices are physical register numbers. Then 580 * to get the tag value, we shift over two bits for each tag 581 * index, and then grab the bottom two bits. 582 */ 583 uint_t tag_index = (i + top) & 7; 584 uint_t tag_fctw = (fps.fctw >> tag_index) & 1; 585 uint_t tag_value; 586 uint_t exp; 587 588 /* 589 * AMD64 stores the tag in a compressed form. It is 590 * necessary to extract the original 2-bit tag value. 591 * See AMD64 Architecture Programmer's Manual Volume 2: 592 * System Programming, Chapter 11. 593 */ 594 595 fpru.ld = fps.st[i].__fpr_pad._q; 596 exp = fpru.reg.exponent & 0x7fff; 597 598 if (tag_fctw == 0) { 599 tag_value = 3; /* empty */ 600 } else if (exp == 0) { 601 if (fpru.reg.significand[0] == 0 && 602 fpru.reg.significand[1] == 0 && 603 fpru.reg.significand[2] == 0 && 604 fpru.reg.significand[3] == 0) 605 tag_value = 1; /* zero */ 606 else 607 tag_value = 2; /* special: denormal */ 608 } else if (exp == 0x7fff) { 609 tag_value = 2; /* special: infinity or NaN */ 610 } else if (fpru.reg.significand[3] & 0x8000) { 611 tag_value = 0; /* valid */ 612 } else { 613 tag_value = 2; /* special: unnormal */ 614 } 615 616 mdb_printf("%%st%d 0x%04x.%04x%04x%04x%04x = %lg %s\n", 617 i, fpru.reg.exponent, 618 fpru.reg.significand[3], fpru.reg.significand[2], 619 fpru.reg.significand[1], fpru.reg.significand[0], 620 fpru.ld, tag_strings[tag_value]); 621 } 622 623 mdb_printf("\nmxcsr 0x%04x (%s)\n", fps.mxcsr, 624 fpmxcsr2str(fps.mxcsr, buf, sizeof (buf))); 625 mdb_printf("xcp 0x%04x (%s)\n\n", fps.xstatus, 626 fpmxcsr2str(fps.xstatus, buf, sizeof (buf))); 627 628 for (i = 0; i < 8; i++) 629 mdb_printf("%%xmm%d 0x%08x%08x%08x%08x\n", i, 630 fps.xmm[i]._l[3], fps.xmm[i]._l[2], 631 fps.xmm[i]._l[1], fps.xmm[i]._l[0]); 632 633 return (DCMD_OK); 634 } 635 636 /*ARGSUSED*/ 637 int 638 pt_getfpreg(mdb_tgt_t *t, mdb_tgt_tid_t tid, ushort_t rd_num, 639 ushort_t rd_flags, mdb_tgt_reg_t *rp) 640 { 641 return (set_errno(ENOTSUP)); 642 } 643 644 /*ARGSUSED*/ 645 int 646 pt_putfpreg(mdb_tgt_t *t, mdb_tgt_tid_t tid, ushort_t rd_num, 647 ushort_t rd_flags, mdb_tgt_reg_t rval) 648 { 649 return (set_errno(ENOTSUP)); 650 } 651 652 /*ARGSUSED*/ 653 void 654 pt_addfpregs(mdb_tgt_t *t) 655 { 656 /* not implemented */ 657 } 658 659 /*ARGSUSED*/ 660 int 661 pt_frameregs(void *arglim, uintptr_t pc, uint_t argc, const long *argv, 662 const mdb_tgt_gregset_t *gregs, boolean_t pc_faked) 663 { 664 return (set_errno(ENOTSUP)); 665 } 666 667 /*ARGSUSED*/ 668 const char * 669 pt_disasm(const GElf_Ehdr *ehp) 670 { 671 return ("amd64"); 672 } 673 674 /* 675 * Determine the return address for the current frame. 676 */ 677 int 678 pt_step_out(mdb_tgt_t *t, uintptr_t *p) 679 { 680 const lwpstatus_t *psp = &Pstatus(t->t_pshandle)->pr_lwp; 681 682 if (Pstate(t->t_pshandle) != PS_STOP) 683 return (set_errno(EMDB_TGTBUSY)); 684 685 return (mdb_amd64_step_out(t, p, psp->pr_reg[EIP], psp->pr_reg[EBP], 686 psp->pr_reg[UESP], psp->pr_instr)); 687 } 688 689 /* 690 * Return the address of the next instruction following a call, or return -1 691 * and set errno to EAGAIN if the target should just single-step. 692 */ 693 int 694 pt_next(mdb_tgt_t *t, uintptr_t *p) 695 { 696 const lwpstatus_t *psp = &Pstatus(t->t_pshandle)->pr_lwp; 697 698 if (Pstate(t->t_pshandle) != PS_STOP) 699 return (set_errno(EMDB_TGTBUSY)); 700 701 return (mdb_amd64_next(t, p, psp->pr_reg[REG_RIP], pt_read_instr(t))); 702 } 703