1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23 * Use is subject to license terms.
24 */
25
26#pragma ident	"%Z%%M%	%I%	%E% SMI"
27
28#pragma dictionary "SUN4U"
29
30#define	AGENT_ID_MASK	0x1f
31#define	AGENT_ID_SHIFT	24
32
33#define	HB_FIT		1000
34#define HBUS_FIT	1000
35#define PCI_BUS_FIT	500
36#define PCI_DEV_FIT	1000
37#define	CPU_FIT		500
38
39#define	PCI_HB_DEV_PATH hostbridge/pcibus/pcidev[32]/pcifn[0]
40
41fru hostbridge;
42asru hostbridge;
43
44event fault.io.psycho@hostbridge,
45    FITrate=HB_FIT, FRU=hostbridge, ASRU=hostbridge;
46
47event error.io.psy.ecc.thresh@hostbridge;
48event ereport.io.psy.ecc.pue@hostbridge{within(5s)};
49event ereport.io.psy.ecc.s-pue@hostbridge{within(5s)};
50event ereport.io.psy.ecc.thresh@hostbridge;
51
52/*
53 * A faulty Psycho hostbridge may cause:
54 *
55 *  - pue:	the psycho to detect a PIO uncorrectable error, bad reader.
56 *  - s-pue:	the psycho to detect a secondary PIO UE, bad reader.
57 *  - ecc:	the SERD engine to gather enough PIO CEs to generate an ereport.
58 */
59prop fault.io.psycho@hostbridge (0)->
60    ereport.io.psy.ecc.pue@hostbridge,
61    ereport.io.psy.ecc.s-pue@hostbridge,
62    error.io.psy.ecc.thresh@hostbridge;
63
64engine serd.io.psycho.ecc@hostbridge,
65    N=3, T=1day, method=persistent,
66    trip=ereport.io.psy.ecc.thresh@hostbridge;
67
68event upset.io.psycho@hostbridge,
69    engine=serd.io.psycho.ecc@hostbridge;
70
71event ereport.io.psy.ecc.pce@hostbridge{within(5s)};
72event ereport.io.psy.ecc.s-pce@hostbridge{within(5s)};
73
74prop error.io.psy.ecc.thresh@hostbridge (2)->
75    ereport.io.psy.ecc.thresh@hostbridge,
76    ereport.io.psy.ecc.pce@hostbridge;
77
78/*
79 * An upset Psycho may cause:
80 *
81 *  - pce:	the psycho to detect a PIO correctable error, bad reader.
82 */
83prop upset.io.psycho@hostbridge (0)->
84    ereport.io.psy.ecc.pce@hostbridge;
85
86event fault.io.hbus@hostbridge,
87    FITrate=HBUS_FIT, FRU=hostbridge, ASRU=hostbridge;
88
89/*
90 * A faulty host bus may cause:
91 *
92 *  - pue:	a PIO uncorrectable error.
93 *  - s-pue:	a secondary PIO UE.
94 *  - ecc:	the SERD engine to gather enough PIO CEs to generate an ereport.
95 */
96prop fault.io.hbus@hostbridge (0)->
97    ereport.io.psy.ecc.pue@hostbridge,
98    ereport.io.psy.ecc.s-pue@hostbridge,
99    error.io.psy.ecc.thresh@hostbridge;
100
101fru cpu;
102
103event fault.io.datapath@cpu, retire=0,
104    FITrate=CPU_FIT, FRU=cpu;
105
106event error.io.cpu.ecc.thresh@cpu;
107
108/*
109 * A faulty CPU may cause:
110 *
111 *  - pue:	a PIO uncorrectable error, where the captured Agentid matches
112 *		the cpuid.
113 *  - ecc:	the SERD engine for the CPU to fire due to PIO CEs from this
114 *		CPU
115 */
116prop fault.io.datapath@cpu[cpuid] (0)->
117    ereport.io.psy.ecc.pue@hostbridge
118    {((payloadprop("ecc-afsr") >> AGENT_ID_SHIFT) & AGENT_ID_MASK) == cpuid};
119
120prop fault.io.datapath@cpu (0)->
121    error.io.cpu.ecc.thresh@cpu;
122
123prop error.io.cpu.ecc.thresh@cpu (1)->
124    ereport.io.psy.ecc.thresh@hostbridge<>;
125
126prop error.io.cpu.ecc.thresh@cpu[cpuid] (1)->
127    ereport.io.psy.ecc.pce@hostbridge<>
128    {((payloadprop("ecc-afsr") >> AGENT_ID_SHIFT) & AGENT_ID_MASK) == cpuid};
129
130asru pcibus/pcidev/pcifn;
131fru pcibus/pcidev;
132
133event fault.io.pci.device-interr@hostbridge/pcibus/pcidev/pcifn,
134    FITrate=PCI_DEV_FIT, FRU=pcibus/pcidev, ASRU=pcibus/pcidev/pcifn;
135
136event fault.io.pci.device-interr@pcibus/pcidev/pcifn,
137    FITrate=PCI_DEV_FIT, FRU=pcibus/pcidev, ASRU=pcibus/pcidev/pcifn;
138
139event error.io.psy.pbm.rl@hostbridge/pcibus/pcidev/pcifn;
140event error.io.psy.pbm.rl@pcibus/pcidev/pcifn;
141event error.io.psy.pbm.rl@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn;
142event error.io.psy.pbm.target-rl@pcibus/pcidev/pcifn;
143event error.io.psy.pbm.target-rl@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn;
144event error.io.pci.ma-u@hostbridge/pcibus/pcidev/pcifn;
145event error.io.pci.perr-pw-u@hostbridge/pcibus/pcidev/pcifn;
146event error.io.pci.perr-dw-u@hostbridge/pcibus/pcidev/pcifn;
147event error.io.pci.dpdata-dr-u@hostbridge/pcibus/pcidev/pcifn;
148event error.io.pci.ta-u@hostbridge/pcibus/pcidev/pcifn;
149event error.io.pci.serr-u@hostbridge/pcibus/pcidev/pcifn;
150event error.io.pci.retry-to-d@hostbridge/pcibus/pcidev/pcifn;
151event error.psy.cpu.berr@cpu;
152
153event ereport.io.psy.sbh@hostbridge/pcibus/pcidev/pcifn{within(5s)};
154event ereport.io.psy.pbm.rl@hostbridge/pcibus/pcidev/pcifn{within(5s)};
155event ereport.io.psy.pbm.s-rl@hostbridge/pcibus/pcidev/pcifn{within(5s)};
156event ereport.io.psy.pbm.s-ma@hostbridge/pcibus/pcidev/pcifn{within(5s)};
157event ereport.io.psy.pbm.s-rta@hostbridge/pcibus/pcidev/pcifn{within(5s)};
158event ereport.io.psy.pbm.s-mdpe@hostbridge/pcibus/pcidev/pcifn{within(5s)};
159event ereport.io.psy.pbm.target-rl@pcibus/pcidev/pcifn{within(5s)};
160event ereport.io.pci.rserr@hostbridge/pcibus/pcidev/pcifn{within(5s)};
161event ereport.cpu.ultraSPARC-II.berr@cpu{within(5s)};
162
163/*
164 * A faulty PCI device may cause:
165 *
166 *  - rl:	it to retry a transaction beyond the specified limit.
167 *  - sbh:	it to generate a streaming byte hole.
168 *
169 * For rl, there may be a target-rl ereport on a child device. There may also be
170 * an associated dto - the retry-to-d error propagates into the pci.esc rules
171 * to handle this.
172 */
173
174prop fault.io.pci.device-interr@pcibus/pcidev[fromdev]/pcifn (0)->
175    error.io.psy.pbm.rl@pcibus/pcidev<todev>/pcifn {
176	fromdev == todev && fromdev != 32 },
177    error.io.psy.pbm.target-rl@pcibus/pcidev<todev>/pcifn {
178	fromdev == todev && fromdev != 32 };
179
180prop error.io.psy.pbm.rl@pcibus/pcidev/pcifn/pcibus/pcidev/pcifn (1)->
181    error.io.psy.pbm.rl@pcibus/pcidev/pcifn;
182
183prop error.io.psy.pbm.rl@hostbridge/pcibus/pcidev/pcifn (1)->
184    ereport.io.psy.pbm.rl@PCI_HB_DEV_PATH,
185    ereport.io.psy.pbm.s-rl@PCI_HB_DEV_PATH;
186
187prop error.io.psy.pbm.target-rl@pcibus/pcidev/pcifn (1)->
188    error.io.psy.pbm.target-rl@pcibus/pcidev/pcifn/pcibus<>/pcidev<>/pcifn<>;
189
190prop error.io.psy.pbm.target-rl@pcibus/pcidev/pcifn (0)->
191    ereport.io.psy.pbm.target-rl@pcibus/pcidev/pcifn;
192
193prop error.io.psy.pbm.rl@hostbridge/pcibus/pcidev/pcifn (0)->
194    error.io.pci.retry-to-d@hostbridge/pcibus/pcidev/pcifn;
195
196prop error.io.psy.pbm.rl@hostbridge/pcibus/pcidev/pcifn (0)->
197    error.psy.cpu.berr@cpu;
198
199prop fault.io.pci.device-interr@hostbridge/pcibus/pcidev/pcifn (0)->
200    ereport.io.psy.sbh@PCI_HB_DEV_PATH;
201
202/*
203 * Need to add the following psycho specific propagations to complete the PCI
204 * fault tree. These are to allow propagations to secondary errors and cpu
205 * bus errors, and to represent the way the chip raises rserr
206 * on detection of SERR#
207 */
208prop error.io.pci.ma-u@hostbridge/pcibus/pcidev/pcifn (0)->
209    ereport.io.psy.pbm.s-ma@PCI_HB_DEV_PATH;
210
211prop error.io.pci.ta-u@hostbridge/pcibus/pcidev/pcifn (0)->
212    ereport.io.psy.pbm.s-rta@PCI_HB_DEV_PATH;
213
214prop error.io.pci.perr-pw-u@hostbridge/pcibus/pcidev/pcifn (0)->
215    ereport.io.psy.pbm.s-mdpe@PCI_HB_DEV_PATH;
216
217prop error.io.pci.perr-dw-u@hostbridge/pcibus/pcidev/pcifn (0)->
218    ereport.io.psy.pbm.s-mdpe@PCI_HB_DEV_PATH;
219
220prop error.io.pci.dpdata-dr-u@hostbridge/pcibus/pcidev/pcifn (0)->
221    ereport.io.psy.pbm.s-mdpe@PCI_HB_DEV_PATH;
222
223prop error.io.pci.ta-u@hostbridge/pcibus/pcidev/pcifn (0)->
224    error.psy.cpu.berr@cpu;
225
226prop error.io.pci.dpdata-dr-u@hostbridge/pcibus/pcidev/pcifn (0)->
227    error.psy.cpu.berr@cpu;
228
229prop error.io.pci.ma-u@hostbridge/pcibus/pcidev/pcifn (0)->
230    error.psy.cpu.berr@cpu;
231
232prop error.psy.cpu.berr@cpu (0)->
233    ereport.cpu.ultraSPARC-II.berr@cpu;
234
235prop error.io.pci.serr-u@hostbridge/pcibus/pcidev/pcifn (1)->
236    ereport.io.pci.rserr@PCI_HB_DEV_PATH;
237
238event ereport.io.psy.nodiag@hostbridge;
239
240/*
241 * Upset used to hide ereports that can not be currently diagnosed.
242 */
243engine serd.io.psy.nodiag@hostbridge,
244    N=1000, T=1hour, method=persistent,
245    trip=ereport.io.psy.nodiag@hostbridge;
246
247event upset.io.psy.nodiag@hostbridge,
248    engine=serd.io.psy.nodiag@hostbridge;
249
250prop upset.io.psy.nodiag@hostbridge (0)->
251    ereport.io.psy.ecc.s-pce@hostbridge,
252    ereport.io.psy.nodiag@hostbridge;
253