1/*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source.  A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12/*
13 * Copyright (c) 2019 by Chelsio Communications, Inc.
14 */
15
16#ifndef __CUDBG_VIEW_ENTITY_H__
17#define __CUDBG_VIEW_ENTITY_H__
18
19#include "cudbg_entity.h"
20
21static const char * const memory[] = { "EDC0:", "EDC1:", "MC:",
22	"MC0:", "MC1:", "HMA:"};
23
24static const char * const lb_stat_name[] = {
25	"OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
26	"UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
27	"Frames128To255:", "Frames256To511:", "Frames512To1023:",
28	"Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
29	"BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
30	"BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
31	"BG2FramesTrunc:", "BG3FramesTrunc:"
32};
33
34
35static struct field_desc tp_la0[] = {
36	{ "RcfOpCodeOut", 60, 4 },
37	{ "State", 56, 4 },
38	{ "WcfState", 52, 4 },
39	{ "RcfOpcSrcOut", 50, 2 },
40	{ "CRxError", 49, 1 },
41	{ "ERxError", 48, 1 },
42	{ "SanityFailed", 47, 1 },
43	{ "SpuriousMsg", 46, 1 },
44	{ "FlushInputMsg", 45, 1 },
45	{ "FlushInputCpl", 44, 1 },
46	{ "RssUpBit", 43, 1 },
47	{ "RssFilterHit", 42, 1 },
48	{ "Tid", 32, 10 },
49	{ "InitTcb", 31, 1 },
50	{ "LineNumber", 24, 7 },
51	{ "Emsg", 23, 1 },
52	{ "EdataOut", 22, 1 },
53	{ "Cmsg", 21, 1 },
54	{ "CdataOut", 20, 1 },
55	{ "EreadPdu", 19, 1 },
56	{ "CreadPdu", 18, 1 },
57	{ "TunnelPkt", 17, 1 },
58	{ "RcfPeerFin", 16, 1 },
59	{ "RcfReasonOut", 12, 4 },
60	{ "TxCchannel", 10, 2 },
61	{ "RcfTxChannel", 8, 2 },
62	{ "RxEchannel", 6, 2 },
63	{ "RcfRxChannel", 5, 1 },
64	{ "RcfDataOutSrdy", 4, 1 },
65	{ "RxDvld", 3, 1 },
66	{ "RxOoDvld", 2, 1 },
67	{ "RxCongestion", 1, 1 },
68	{ "TxCongestion", 0, 1 },
69	{ NULL }
70};
71
72static struct field_desc tp_la1[] = {
73	{ "CplCmdIn", 56, 8 },
74	{ "CplCmdOut", 48, 8 },
75	{ "ESynOut", 47, 1 },
76	{ "EAckOut", 46, 1 },
77	{ "EFinOut", 45, 1 },
78	{ "ERstOut", 44, 1 },
79	{ "SynIn", 43, 1 },
80	{ "AckIn", 42, 1 },
81	{ "FinIn", 41, 1 },
82	{ "RstIn", 40, 1 },
83	{ "DataIn", 39, 1 },
84	{ "DataInVld", 38, 1 },
85	{ "PadIn", 37, 1 },
86	{ "RxBufEmpty", 36, 1 },
87	{ "RxDdp", 35, 1 },
88	{ "RxFbCongestion", 34, 1 },
89	{ "TxFbCongestion", 33, 1 },
90	{ "TxPktSumSrdy", 32, 1 },
91	{ "RcfUlpType", 28, 4 },
92	{ "Eread", 27, 1 },
93	{ "Ebypass", 26, 1 },
94	{ "Esave", 25, 1 },
95	{ "Static0", 24, 1 },
96	{ "Cread", 23, 1 },
97	{ "Cbypass", 22, 1 },
98	{ "Csave", 21, 1 },
99	{ "CPktOut", 20, 1 },
100	{ "RxPagePoolFull", 18, 2 },
101	{ "RxLpbkPkt", 17, 1 },
102	{ "TxLpbkPkt", 16, 1 },
103	{ "RxVfValid", 15, 1 },
104	{ "SynLearned", 14, 1 },
105	{ "SetDelEntry", 13, 1 },
106	{ "SetInvEntry", 12, 1 },
107	{ "CpcmdDvld", 11, 1 },
108	{ "CpcmdSave", 10, 1 },
109	{ "RxPstructsFull", 8, 2 },
110	{ "EpcmdDvld", 7, 1 },
111	{ "EpcmdFlush", 6, 1 },
112	{ "EpcmdTrimPrefix", 5, 1 },
113	{ "EpcmdTrimPostfix", 4, 1 },
114	{ "ERssIp4Pkt", 3, 1 },
115	{ "ERssIp6Pkt", 2, 1 },
116	{ "ERssTcpUdpPkt", 1, 1 },
117	{ "ERssFceFipPkt", 0, 1 },
118	{ NULL }
119};
120
121static struct field_desc tp_la2[] = {
122	{ "CplCmdIn", 56, 8 },
123	{ "MpsVfVld", 55, 1 },
124	{ "MpsPf", 52, 3 },
125	{ "MpsVf", 44, 8 },
126	{ "SynIn", 43, 1 },
127	{ "AckIn", 42, 1 },
128	{ "FinIn", 41, 1 },
129	{ "RstIn", 40, 1 },
130	{ "DataIn", 39, 1 },
131	{ "DataInVld", 38, 1 },
132	{ "PadIn", 37, 1 },
133	{ "RxBufEmpty", 36, 1 },
134	{ "RxDdp", 35, 1 },
135	{ "RxFbCongestion", 34, 1 },
136	{ "TxFbCongestion", 33, 1 },
137	{ "TxPktSumSrdy", 32, 1 },
138	{ "RcfUlpType", 28, 4 },
139	{ "Eread", 27, 1 },
140	{ "Ebypass", 26, 1 },
141	{ "Esave", 25, 1 },
142	{ "Static0", 24, 1 },
143	{ "Cread", 23, 1 },
144	{ "Cbypass", 22, 1 },
145	{ "Csave", 21, 1 },
146	{ "CPktOut", 20, 1 },
147	{ "RxPagePoolFull", 18, 2 },
148	{ "RxLpbkPkt", 17, 1 },
149	{ "TxLpbkPkt", 16, 1 },
150	{ "RxVfValid", 15, 1 },
151	{ "SynLearned", 14, 1 },
152	{ "SetDelEntry", 13, 1 },
153	{ "SetInvEntry", 12, 1 },
154	{ "CpcmdDvld", 11, 1 },
155	{ "CpcmdSave", 10, 1 },
156	{ "RxPstructsFull", 8, 2 },
157	{ "EpcmdDvld", 7, 1 },
158	{ "EpcmdFlush", 6, 1 },
159	{ "EpcmdTrimPrefix", 5, 1 },
160	{ "EpcmdTrimPostfix", 4, 1 },
161	{ "ERssIp4Pkt", 3, 1 },
162	{ "ERssIp6Pkt", 2, 1 },
163	{ "ERssTcpUdpPkt", 1, 1 },
164	{ "ERssFceFipPkt", 0, 1 },
165	{ NULL }
166};
167
168static const char * const devlog_level_strings[] = {
169	/*[FW_DEVLOG_LEVEL_EMERG]	=*/ "EMERG",
170	/*[FW_DEVLOG_LEVEL_CRIT]	=*/ "CRIT",
171	/*[FW_DEVLOG_LEVEL_ERR]		=*/ "ERR",
172	/*[FW_DEVLOG_LEVEL_NOTICE]	=*/ "NOTICE",
173	/*[FW_DEVLOG_LEVEL_INFO]	=*/ "INFO",
174	/*[FW_DEVLOG_LEVEL_DEBUG]	=*/ "DEBUG",
175	/*[FW_DEVLOG_LEVEL_MAX]		=*/ "MAX"
176};
177
178static const char * const devlog_facility_strings[] = {
179	/*[FW_DEVLOG_FACILITY_CORE]   =*/ "CORE",
180	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
181	/*[FW_DEVLOG_FACILITY_SCHED]  =*/ "SCHED",
182	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
183	/*[FW_DEVLOG_FACILITY_TIMER]  =*/ "TIMER",
184	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
185	/*[FW_DEVLOG_FACILITY_RES]    =*/ "RES",
186	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
187	/*[FW_DEVLOG_FACILITY_HW]     =*/ "HW",
188	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
189	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
190	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
191	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
192	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
193	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
194	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
195	/*[FW_DEVLOG_FACILITY_FLR]    =*/ "FLR",
196	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
197	/*[FW_DEVLOG_FACILITY_DMAQ]   =*/ "DMAQ",
198	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
199	/*[FW_DEVLOG_FACILITY_PHY]    =*/ "PHY",
200	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
201	/*[FW_DEVLOG_FACILITY_MAC]    =*/ "MAC",
202	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
203	/*[FW_DEVLOG_FACILITY_PORT]   =*/ "PORT",
204	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
205	/*[FW_DEVLOG_FACILITY_VI]     =*/ "VI",
206	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
207	/*[FW_DEVLOG_FACILITY_FILTER] =*/ "FILTER",
208	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
209	/*[FW_DEVLOG_FACILITY_ACL]    =*/ "ACL",
210	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
211	/*[FW_DEVLOG_FACILITY_TM]     =*/ "TM",
212	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
213	/*[FW_DEVLOG_FACILITY_QFC]    =*/ "QFC",
214	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
215	/*[FW_DEVLOG_FACILITY_DCB]    =*/ "DCB",
216	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
217	/*[FW_DEVLOG_FACILITY_ETH]    =*/ "ETH",
218	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
219	/*[FW_DEVLOG_FACILITY_OFLD]   =*/ "OFLD",
220	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
221	/*[FW_DEVLOG_FACILITY_RI]     =*/ "RI",
222	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
223	/*[FW_DEVLOG_FACILITY_ISCSI]  =*/ "ISCSI",
224	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
225	/*[FW_DEVLOG_FACILITY_FCOE]   =*/ "FCOE",
226	/*[FW_DEVLOG_FACILITY_DUMMY]  =*/ "DUMMY",
227	/*[FW_DEVLOG_FACILITY_FOISCSI]	 =*/ "FOISCSI",
228	/*[FW_DEVLOG_FACILITY_DUMMY]   =*/ "DUMMY",
229	/*[FW_DEVLOG_FACILITY_FOFCOE] =*/ "FOFCOE",
230	/*[FW_DEVLOG_FACILITY_MAX]    =*/ "MAX"
231};
232
233static struct tp1_reg_info t6_tp_mib_index_reg_array[] = {
234	{"0x0", "TP_MIB_MAC_IN_ERR_0"},
235	{"0x1", "TP_MIB_MAC_IN_ERR_1"},
236	{"0x2", "TP_MIB_MAC_IN_ERR_2"},
237	{"0x3", "TP_MIB_MAC_IN_ERR_3"},
238	{"0x4", "TP_MIB_HDR_IN_ERR_0"},
239	{"0x5", "TP_MIB_HDR_IN_ERR_1"},
240	{"0x6", "TP_MIB_HDR_IN_ERR_2"},
241	{"0x7", "TP_MIB_HDR_IN_ERR_3"},
242	{"0x8", "TP_MIB_TCP_IN_ERR_0"},
243	{"0x9", "TP_MIB_TCP_IN_ERR_1"},
244	{"0xA", "TP_MIB_TCP_IN_ERR_2"},
245	{"0xB", "TP_MIB_TCP_IN_ERR_3"},
246	{"0xC", "TP_MIB_TCP_OUT_RST"},
247	{"0x10", "TP_MIB_TCP_IN_SEG_HI"},
248	{"0x11", "TP_MIB_TCP_IN_SEG_LO"},
249	{"0x12", "TP_MIB_TCP_OUT_SEG_HI"},
250	{"0x13", "TP_MIB_TCP_OUT_SEG_LO"},
251	{"0x14", "TP_MIB_TCP_RXT_SEG_HI"},
252	{"0x15", "TP_MIB_TCP_RXT_SEG_LO"},
253	{"0x18", "TP_MIB_TNL_CNG_DROP_0"},
254	{"0x19", "TP_MIB_TNL_CNG_DROP_1"},
255	{"0x1A", "TP_MIB_TNL_CNG_DROP_2"},
256	{"0x1B", "TP_MIB_TNL_CNG_DROP_3"},
257	{"0x1C", "TP_MIB_OFD_CHN_DROP_0"},
258	{"0x1D", "TP_MIB_OFD_CHN_DROP_1"},
259	{"0x1E", "TP_MIB_OFD_CHN_DROP_2"},
260	{"0x1F", "TP_MIB_OFD_CHN_DROP_3"},
261	{"0x20", "TP_MIB_TNL_OUT_PKT_0"},
262	{"0x21", "TP_MIB_TNL_OUT_PKT_1"},
263	{"0x22", "TP_MIB_TNL_OUT_PKT_2"},
264	{"0x23", "TP_MIB_TNL_OUT_PKT_3"},
265	{"0x24", "TP_MIB_TNL_IN_PKT_0"},
266	{"0x25", "TP_MIB_TNL_IN_PKT_1"},
267	{"0x26", "TP_MIB_TNL_IN_PKT_2"},
268	{"0x27", "TP_MIB_TNL_IN_PKT_3"},
269	{"0x28", "TP_MIB_TCP_V6IN_ERR_0"},
270	{"0x29", "TP_MIB_TCP_V6IN_ERR_1"},
271	{"0x2A", "TP_MIB_TCP_V6IN_ERR_2"},
272	{"0x2B", "TP_MIB_TCP_V6IN_ERR_3"},
273	{"0x2C", "TP_MIB_TCP_V6OUT_RST"},
274	{"0x30", "TP_MIB_TCP_V6IN_SEG_HI"},
275	{"0x31", "TP_MIB_TCP_V6IN_SEG_LO"},
276	{"0x32", "TP_MIB_TCP_V6OUT_SEG_HI"},
277	{"0x33", "TP_MIB_TCP_V6OUT_SEG_LO"},
278	{"0x34", "TP_MIB_TCP_V6RXT_SEG_HI"},
279	{"0x35", "TP_MIB_TCP_V6RXT_SEG_LO"},
280	{"0x36", "TP_MIB_OFD_ARP_DROP"},
281	{"0x37", "TP_MIB_OFD_DFR_DROP"},
282	{"0x38", "TP_MIB_CPL_IN_REQ_0"},
283	{"0x39", "TP_MIB_CPL_IN_REQ_1"},
284	{"0x3A", "TP_MIB_CPL_IN_REQ_2"},
285	{"0x3B", "TP_MIB_CPL_IN_REQ_3"},
286	{"0x3C", "TP_MIB_CPL_OUT_RSP_0"},
287	{"0x3D", "TP_MIB_CPL_OUT_RSP_1"},
288	{"0x3E", "TP_MIB_CPL_OUT_RSP_2"},
289	{"0x3F", "TP_MIB_CPL_OUT_RSP_3"},
290	{"0x40", "TP_MIB_TNL_LPBK_0"},
291	{"0x41", "TP_MIB_TNL_LPBK_1"},
292	{"0x42", "TP_MIB_TNL_LPBK_2"},
293	{"0x43", "TP_MIB_TNL_LPBK_3"},
294	{"0x44", "TP_MIB_TNL_DROP_0"},
295	{"0x45", "TP_MIB_TNL_DROP_1"},
296	{"0x46", "TP_MIB_TNL_DROP_2"},
297	{"0x47", "TP_MIB_TNL_DROP_3"},
298	{"0x48", "TP_MIB_FCOE_DDP_0"},
299	{"0x49", "TP_MIB_FCOE_DDP_1"},
300	{"0x4A", "TP_MIB_FCOE_DDP_2"},
301	{"0x4B", "TP_MIB_FCOE_DDP_3"},
302	{"0x4C", "TP_MIB_FCOE_DROP_0"},
303	{"0x4D", "TP_MIB_FCOE_DROP_1"},
304	{"0x4E", "TP_MIB_FCOE_DROP_2"},
305	{"0x4F", "TP_MIB_FCOE_DROP_3"},
306	{"0x50", "TP_MIB_FCOE_BYTE_0_HI"},
307	{"0x51", "TP_MIB_FCOE_BYTE_0_LO"},
308	{"0x52", "TP_MIB_FCOE_BYTE_1_HI"},
309	{"0x53", "TP_MIB_FCOE_BYTE_1_LO"},
310	{"0x54", "TP_MIB_FCOE_BYTE_2_HI"},
311	{"0x55", "TP_MIB_FCOE_BYTE_2_LO"},
312	{"0x56", "TP_MIB_FCOE_BYTE_3_HI"},
313	{"0x57", "TP_MIB_FCOE_BYTE_3_LO"},
314	{"0x58", "TP_MIB_OFD_VLN_DROP_0"},
315	{"0x59", "TP_MIB_OFD_VLN_DROP_1"},
316	{"0x5A", "TP_MIB_OFD_VLN_DROP_2"},
317	{"0x5B", "TP_MIB_OFD_VLN_DROP_3"},
318	{"0x5C", "TP_MIB_USM_PKTS"},
319	{"0x5D", "TP_MIB_USM_DROP"},
320	{"0x5E", "TP_MIB_USM_BYTES_HI"},
321	{"0x5F", "TP_MIB_USM_BYTES_LO"},
322	{"0x60", "TP_MIB_TID_DEL"},
323	{"0x61", "TP_MIB_TID_INV"},
324	{"0x62", "TP_MIB_TID_ACT"},
325	{"0x63", "TP_MIB_TID_PAS"},
326	{"0x64", "TP_MIB_RQE_DFR_PKT"},
327	{"0x65", "TP_MIB_RQE_DFR_MOD"},
328	{"0x68", "TP_MIB_CPL_OUT_ERR_0"},
329	{"0x69", "TP_MIB_CPL_OUT_ERR_1"},
330	{"0x6A", "TP_MIB_CPL_OUT_ERR_2"},
331	{"0x6B", "TP_MIB_CPL_OUT_ERR_3"},
332	{"0x6c", "TP_MIB_ENG_LINE_0"},
333	{"0x6d", "TP_MIB_ENG_LINE_1"},
334	{"0x6e", "TP_MIB_ENG_LINE_2"},
335	{"0x6f", "TP_MIB_ENG_LINE_3"},
336	{"0x70", "TP_MIB_TNL_ERR_0"},
337	{"0x71", "TP_MIB_TNL_ERR_1"},
338	{"0x72", "TP_MIB_TNL_ERR_2"},
339	{"0x73", "TP_MIB_TNL_ERR_3"}
340};
341
342static struct tp1_reg_info t5_tp_mib_index_reg_array[] = {
343	{"0x0", "TP_MIB_MAC_IN_ERR_0"},
344	{"0x1", "TP_MIB_MAC_IN_ERR_1"},
345	{"0x2", "TP_MIB_MAC_IN_ERR_2"},
346	{"0x3", "TP_MIB_MAC_IN_ERR_3"},
347	{"0x4", "TP_MIB_HDR_IN_ERR_0"},
348	{"0x5", "TP_MIB_HDR_IN_ERR_1"},
349	{"0x6", "TP_MIB_HDR_IN_ERR_2"},
350	{"0x7", "TP_MIB_HDR_IN_ERR_3"},
351	{"0x8", "TP_MIB_TCP_IN_ERR_0"},
352	{"0x9", "TP_MIB_TCP_IN_ERR_1"},
353	{"0xA", "TP_MIB_TCP_IN_ERR_2"},
354	{"0xB", "TP_MIB_TCP_IN_ERR_3"},
355	{"0xC", "TP_MIB_TCP_OUT_RST"},
356	{"0x10", "TP_MIB_TCP_IN_SEG_HI"},
357	{"0x11", "TP_MIB_TCP_IN_SEG_LO"},
358	{"0x12", "TP_MIB_TCP_OUT_SEG_HI"},
359	{"0x13", "TP_MIB_TCP_OUT_SEG_LO"},
360	{"0x14", "TP_MIB_TCP_RXT_SEG_HI"},
361	{"0x15", "TP_MIB_TCP_RXT_SEG_LO"},
362	{"0x18", "TP_MIB_TNL_CNG_DROP_0"},
363	{"0x19", "TP_MIB_TNL_CNG_DROP_1"},
364	{"0x1A", "TP_MIB_TNL_CNG_DROP_2"},
365	{"0x1B", "TP_MIB_TNL_CNG_DROP_3"},
366	{"0x1C", "TP_MIB_OFD_CHN_DROP_0"},
367	{"0x1D", "TP_MIB_OFD_CHN_DROP_1"},
368	{"0x1E", "TP_MIB_OFD_CHN_DROP_2"},
369	{"0x1F", "TP_MIB_OFD_CHN_DROP_3"},
370	{"0x20", "TP_MIB_TNL_OUT_PKT_0"},
371	{"0x21", "TP_MIB_TNL_OUT_PKT_1"},
372	{"0x22", "TP_MIB_TNL_OUT_PKT_2"},
373	{"0x23", "TP_MIB_TNL_OUT_PKT_3"},
374	{"0x24", "TP_MIB_TNL_IN_PKT_0"},
375	{"0x25", "TP_MIB_TNL_IN_PKT_1"},
376	{"0x26", "TP_MIB_TNL_IN_PKT_2"},
377	{"0x27", "TP_MIB_TNL_IN_PKT_3"},
378	{"0x28", "TP_MIB_TCP_V6IN_ERR_0"},
379	{"0x29", "TP_MIB_TCP_V6IN_ERR_1"},
380	{"0x2A", "TP_MIB_TCP_V6IN_ERR_2"},
381	{"0x2B", "TP_MIB_TCP_V6IN_ERR_3"},
382	{"0x2C", "TP_MIB_TCP_V6OUT_RST"},
383	{"0x30", "TP_MIB_TCP_V6IN_SEG_HI"},
384	{"0x31", "TP_MIB_TCP_V6IN_SEG_LO"},
385	{"0x32", "TP_MIB_TCP_V6OUT_SEG_HI"},
386	{"0x33", "TP_MIB_TCP_V6OUT_SEG_LO"},
387	{"0x34", "TP_MIB_TCP_V6RXT_SEG_HI"},
388	{"0x35", "TP_MIB_TCP_V6RXT_SEG_LO"},
389	{"0x36", "TP_MIB_OFD_ARP_DROP"},
390	{"0x37", "TP_MIB_OFD_DFR_DROP"},
391	{"0x38", "TP_MIB_CPL_IN_REQ_0"},
392	{"0x39", "TP_MIB_CPL_IN_REQ_1"},
393	{"0x3A", "TP_MIB_CPL_IN_REQ_2"},
394	{"0x3B", "TP_MIB_CPL_IN_REQ_3"},
395	{"0x3C", "TP_MIB_CPL_OUT_RSP_0"},
396	{"0x3D", "TP_MIB_CPL_OUT_RSP_1"},
397	{"0x3E", "TP_MIB_CPL_OUT_RSP_2"},
398	{"0x3F", "TP_MIB_CPL_OUT_RSP_3"},
399	{"0x40", "TP_MIB_TNL_LPBK_0"},
400	{"0x41", "TP_MIB_TNL_LPBK_1"},
401	{"0x42", "TP_MIB_TNL_LPBK_2"},
402	{"0x43", "TP_MIB_TNL_LPBK_3"},
403	{"0x44", "TP_MIB_TNL_DROP_0"},
404	{"0x45", "TP_MIB_TNL_DROP_1"},
405	{"0x46", "TP_MIB_TNL_DROP_2"},
406	{"0x47", "TP_MIB_TNL_DROP_3"},
407	{"0x48", "TP_MIB_FCOE_DDP_0"},
408	{"0x49", "TP_MIB_FCOE_DDP_1"},
409	{"0x4A", "TP_MIB_FCOE_DDP_2"},
410	{"0x4B", "TP_MIB_FCOE_DDP_3"},
411	{"0x4C", "TP_MIB_FCOE_DROP_0"},
412	{"0x4D", "TP_MIB_FCOE_DROP_1"},
413	{"0x4E", "TP_MIB_FCOE_DROP_2"},
414	{"0x4F", "TP_MIB_FCOE_DROP_3"},
415	{"0x50", "TP_MIB_FCOE_BYTE_0_HI"},
416	{"0x51", "TP_MIB_FCOE_BYTE_0_LO"},
417	{"0x52", "TP_MIB_FCOE_BYTE_1_HI"},
418	{"0x53", "TP_MIB_FCOE_BYTE_1_LO"},
419	{"0x54", "TP_MIB_FCOE_BYTE_2_HI"},
420	{"0x55", "TP_MIB_FCOE_BYTE_2_LO"},
421	{"0x56", "TP_MIB_FCOE_BYTE_3_HI"},
422	{"0x57", "TP_MIB_FCOE_BYTE_3_LO"},
423	{"0x58", "TP_MIB_OFD_VLN_DROP_0"},
424	{"0x59", "TP_MIB_OFD_VLN_DROP_1"},
425	{"0x5A", "TP_MIB_OFD_VLN_DROP_2"},
426	{"0x5B", "TP_MIB_OFD_VLN_DROP_3"},
427	{"0x5C", "TP_MIB_USM_PKTS"},
428	{"0x5D", "TP_MIB_USM_DROP"},
429	{"0x5E", "TP_MIB_USM_BYTES_HI"},
430	{"0x5F", "TP_MIB_USM_BYTES_LO"},
431	{"0x60", "TP_MIB_TID_DEL"},
432	{"0x61", "TP_MIB_TID_INV"},
433	{"0x62", "TP_MIB_TID_ACT"},
434	{"0x63", "TP_MIB_TID_PAS"},
435	{"0x64", "TP_MIB_RQE_DFR_PKT"},
436	{"0x65", "TP_MIB_RQE_DFR_MOD"},
437	{"0x68", "TP_MIB_CPL_OUT_ERR_0"},
438	{"0x69", "TP_MIB_CPL_OUT_ERR_1"},
439	{"0x6A", "TP_MIB_CPL_OUT_ERR_2"},
440	{"0x6B", "TP_MIB_CPL_OUT_ERR_3"}
441};
442
443static struct cudbg_reg_info t6_tp_tm_regs[] = {
444	{ "TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR", 0x0, 0 },
445	{ "S_TXTIMERSEPQ7", 16, 16 },
446	{ "S_TXTIMERSEPQ6", 0, 16 },
447	{ "TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR", 0x1, 0 },
448	{ "S_TXTIMERSEPQ4", 16, 16 },
449	{ "S_TXTIMERSEPQ4", 0, 16 },
450	{ "TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR", 0x2, 0 },
451	{ "S_TXTIMERSEPQ3", 16, 16 },
452	{ "S_TXTIMERSEPQ2", 0, 16 },
453	{ "TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR", 0x3, 0 },
454	{ "S_TXTIMERSEPQ1", 16, 16 },
455	{ "S_TXTIMERSEPQ0", 0, 16 },
456	{ "TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR", 0x4, 0 },
457	{ "S_RXTIMERSEPQ1", 16, 16 },
458	{ "S_RXTIMERSEPQ0", 0, 16 },
459	{ "TP_TX_MOD_Q7_Q6_RATE_LIMIT", 0x5, 0 },
460	{ "S_TXRATEINCQ7", 24, 8 },
461	{ "S_TXRATETCKQ7", 16, 8 },
462	{ "S_TXRATEINCQ6", 8, 8 },
463	{ "S_TXRATETCKQ6", 0, 8 },
464	{ "TP_TX_MOD_Q5_Q4_RATE_LIMIT", 0x6, 0 },
465	{ "S_TXRATEINCQ5", 24, 8 },
466	{ "S_TXRATETCKQ5", 16, 8 },
467	{ "S_TXRATEINCQ4", 8, 8 },
468	{ "S_TXRATETCKQ4", 0, 8 },
469	{ "TP_TX_MOD_Q3_Q2_RATE_LIMIT", 0x7, 0 },
470	{ "S_TXRATEINCQ3", 24, 8 },
471	{ "S_TXRATETCKQ3", 16, 8 },
472	{ "S_TXRATEINCQ2", 8, 8 },
473	{ "S_TXRATETCKQ2", 0, 8 },
474	{ "TP_TX_MOD_Q1_Q0_RATE_LIMIT", 0x8, 0 },
475	{ "S_TXRATEINCQ1", 24, 8 },
476	{ "S_TXRATETCKQ1", 16, 8 },
477	{ "S_TXRATEINCQ0", 8, 8 },
478	{ "S_TXRATETCKQ0", 0, 8 },
479	{ "TP_RX_MOD_Q1_Q0_RATE_LIMIT", 0x9, 0 },
480	{ "S_RXRATEINCQ1", 24, 8 },
481	{ "S_RXRATETCKQ1", 16, 8 },
482	{ "S_RXRATEINCQ0", 8, 8 },
483	{ "S_RXRATETCKQ0", 0, 8 },
484	{ "TP_TX_MOD_C3_C2_RATE_LIMIT", 0xA, 0 },
485	{ "TP_TX_MOD_C1_C0_RATE_LIMIT", 0xB, 0 },
486	{ NULL }
487};
488
489static struct cudbg_reg_info t5_tp_tm_regs[] = {
490	{ "TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR", 0x0, 0 },
491	{ "S_TXTIMERSEPQ7", 16, 16 },
492	{ "S_TXTIMERSEPQ6", 0, 16 },
493	{ "TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR", 0x1, 0 },
494	{ "S_TXTIMERSEPQ4", 16, 16 },
495	{ "S_TXTIMERSEPQ4", 0, 16 },
496	{ "TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR", 0x2, 0 },
497	{ "S_TXTIMERSEPQ3", 16, 16 },
498	{ "S_TXTIMERSEPQ2", 0, 16 },
499	{ "TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR", 0x3, 0 },
500	{ "S_TXTIMERSEPQ1", 16, 16 },
501	{ "S_TXTIMERSEPQ0", 0, 16 },
502	{ "TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR", 0x4, 0 },
503	{ "S_RXTIMERSEPQ1", 16, 16 },
504	{ "S_RXTIMERSEPQ0", 0, 16 },
505	{ "TP_TX_MOD_Q7_Q6_RATE_LIMIT", 0x5, 0 },
506	{ "S_TXRATEINCQ7", 24, 8 },
507	{ "S_TXRATETCKQ7", 16, 8 },
508	{ "S_TXRATEINCQ6", 8, 8 },
509	{ "S_TXRATETCKQ6", 0, 8 },
510	{ "TP_TX_MOD_Q5_Q4_RATE_LIMIT", 0x6, 0 },
511	{ "S_TXRATEINCQ5", 24, 8 },
512	{ "S_TXRATETCKQ5", 16, 8 },
513	{ "S_TXRATEINCQ4", 8, 8 },
514	{ "S_TXRATETCKQ4", 0, 8 },
515	{ "TP_TX_MOD_Q3_Q2_RATE_LIMIT", 0x7, 0 },
516	{ "S_TXRATEINCQ3", 24, 8 },
517	{ "S_TXRATETCKQ3", 16, 8 },
518	{ "S_TXRATEINCQ2", 8, 8 },
519	{ "S_TXRATETCKQ2", 0, 8 },
520	{ "TP_TX_MOD_Q1_Q0_RATE_LIMIT", 0x8, 0 },
521	{ "S_TXRATEINCQ1", 24, 8 },
522	{ "S_TXRATETCKQ1", 16, 8 },
523	{ "S_TXRATEINCQ0", 8, 8 },
524	{ "S_TXRATETCKQ0", 0, 8 },
525	{ "TP_RX_MOD_Q1_Q0_RATE_LIMIT", 0x9, 0 },
526	{ "S_RXRATEINCQ1", 24, 8 },
527	{ "S_RXRATETCKQ1", 16, 8 },
528	{ "S_RXRATEINCQ0", 8, 8 },
529	{ "S_RXRATETCKQ0", 0, 8 },
530	{ "TP_TX_MOD_C3_C2_RATE_LIMIT", 0xA, 0 },
531	{ "TP_TX_MOD_C1_C0_RATE_LIMIT", 0xB, 0 },
532	{ NULL }
533};
534
535static struct cudbg_reg_info t6_tp_pio_regs_20_to_3b[] = {
536	{ "TP_RX_SCHED_MAP", 0x20, 0 },
537	{ "S_RXMAPCHANNEL3", 24, 8 },
538	{ "S_RXMAPCHANNEL2", 16, 8 },
539	{ "S_RXMAPCHANNEL1", 8, 8 },
540	{ "S_RXMAPCHANNEL0", 0, 8 },
541	{ "TP_RX_SCHED_SGE", 0x21, 0 },
542	{ "S_RXSGEMOD1", 12, 4 },
543	{ "S_RXSGEMOD0", 8, 4 },
544	{ "S_RXSGECHANNEL3", 3, 1 },
545	{ "S_RXSGECHANNEL2", 2, 1 },
546	{ "S_RXSGECHANNEL1", 1, 1 },
547	{ "S_RXSGECHANNEL0", 0, 1 },
548	{ "TP_TX_SCHED_MAP", 0x22, 0 },
549	{ "S_TXMAPCHANNEL3", 12, 4 },
550	{ "S_TXMAPCHANNEL2", 8, 4 },
551	{ "S_TXMAPCHANNEL1", 4, 4 },
552	{ "S_TXMAPCHANNEL0", 0, 4 },
553	{ "TP_TX_SCHED_HDR", 0x23, 0 },
554	{ "S_TXMAPHDRCHANNEL7", 28, 4 },
555	{ "S_TXMAPHDRCHANNEL6", 24, 4 },
556	{ "S_TXMAPHDRCHANNEL5", 20, 4 },
557	{ "S_TXMAPHDRCHANNEL4", 16, 4 },
558	{ "S_TXMAPHDRCHANNEL3", 12, 4 },
559	{ "S_TXMAPHDRCHANNEL2", 8, 4 },
560	{ "S_TXMAPHDRCHANNEL1", 4, 4 },
561	{ "S_TXMAPHDRCHANNEL0", 0, 4 },
562	{ "TP_TX_SCHED_FIFO", 0x24, 0 },
563	{ "S_TXMAPFIFOCHANNEL7", 28, 4 },
564	{ "S_TXMAPFIFOCHANNEL6", 24, 4 },
565	{ "S_TXMAPFIFOCHANNEL5", 20, 4 },
566	{ "S_TXMAPFIFOCHANNEL4", 16, 4 },
567	{ "S_TXMAPFIFOCHANNEL3", 12, 4 },
568	{ "S_TXMAPFIFOCHANNEL2", 8, 4 },
569	{ "S_TXMAPFIFOCHANNEL1", 4, 4 },
570	{ "S_TXMAPFIFOCHANNEL0", 0, 4 },
571	{ "TP_TX_SCHED_PCMD", 0x25, 0 },
572	{ "S_TXMAPPCMDCHANNEL7", 28, 4 },
573	{ "S_TXMAPPCMDCHANNEL6", 24, 4 },
574	{ "S_TXMAPPCMDCHANNEL5", 20, 4 },
575	{ "S_TXMAPPCMDCHANNEL4", 16, 4 },
576	{ "S_TXMAPPCMDCHANNEL3", 12, 4 },
577	{ "S_TXMAPPCMDCHANNEL2", 8, 4 },
578	{ "S_TXMAPPCMDCHANNEL1", 4, 4 },
579	{ "S_TXMAPPCMDCHANNEL0", 0, 4 },
580	{ "TP_TX_SCHED_LPBK", 0x26, 0 },
581	{ "S_TXMAPLPBKCHANNEL7", 28, 4 },
582	{ "S_TXMAPLPBKCHANNEL6", 24, 4 },
583	{ "S_TXMAPLPBKCHANNEL5", 20, 4 },
584	{ "S_TXMAPLPBKCHANNEL4", 16, 4 },
585	{ "S_TXMAPLPBKCHANNEL3", 12, 4 },
586	{ "S_TXMAPLPBKCHANNEL2", 8, 4 },
587	{ "S_TXMAPLPBKCHANNEL1", 4, 4 },
588	{ "S_TXMAPLPBKCHANNEL0", 0, 4 },
589	{ "TP_CHANNEL_MAP", 0x27, 0 },
590	{ "RxMapChannelELN", 16, 4 },
591	{ "RxMapE2LChannel3", 14, 2 },
592	{ "RxMapE2LChannel2", 12, 2 },
593	{ "RxMapE2LChannel1", 10, 2 },
594	{ "RxMapE2LChannel0", 8, 2 },
595	{ "RxMapC2CChannel3", 7, 1 },
596	{ "RxMapC2CChannel2", 6, 1 },
597	{ "RxMapC2CChannel1", 5, 1 },
598	{ "RxMapC2CChannel0", 4, 1 },
599	{ "RxMapE2CChannel3", 3, 1 },
600	{ "RxMapE2CChannel2", 2, 1 },
601	{ "RxMapE2CChannel1", 1, 1 },
602	{ "RxMapE2CChannel0", 0, 1 },
603	{ "TP_RX_LPBK", 0x28, 0 },
604	{ "CommitReset3", 31, 1 },
605	{ "CommitReset2", 30, 1 },
606	{ "CommitReset1", 29, 1 },
607	{ "CommitReset0", 28, 1 },
608	{ "ForceCong3", 27, 1 },
609	{ "ForceCong2", 26, 1 },
610	{ "ForceCong1", 25, 1 },
611	{ "ForceCong0", 24, 1 },
612	{ "CommitLimit3", 18, 6 },
613	{ "CommitLimit2", 12, 6},
614	{ "CommitLimit1", 6, 6 },
615	{ "CommitLimit0", 0, 6 },
616	{ "TP_TX_LPBK", 0x29, 0 },
617	{ "CommitReset3", 31, 1 },
618	{ "CommitReset2", 30, 1 },
619	{ "CommitReset1", 29, 1 },
620	{ "CommitReset0", 28, 1 },
621	{ "ForceCong3", 27, 1 },
622	{ "ForceCong2", 26, 1 },
623	{ "ForceCong1", 25, 1 },
624	{ "ForceCong0", 24, 1 },
625	{ "CommitLimit3", 18, 6 },
626	{ "CommitLimit2", 12, 6},
627	{ "CommitLimit1", 6, 6 },
628	{ "CommitLimit0", 0, 6 },
629
630	{ "TP_TX_SCHED_PPP", 0x2A, 0 },
631	{ "S_TXPPPENPORT3", 24, 8 },
632	{ "S_TXPPPENPORT2", 16, 8 },
633	{ "S_TXPPPENPORT1", 8, 8 },
634	{ "S_TXPPPENPORT0", 0, 8 },
635	{ "TP_RX_SCHED_FIFO", 0x2B, 0 },
636	{ "S_COMMITLIMIT1H", 24, 8 },
637	{ "S_COMMITLIMIT1L", 16, 8 },
638	{ "S_COMMITLIMIT0H", 8, 8 },
639	{ "S_COMMITLIMIT0L", 0, 8 },
640	{ "TP_IPMI_CFG1", 0x2E, 0 },
641	{ "S_VLANENABLE", 31, 1 },
642	{ "S_PRIMARYPORTENABLE", 30, 1 },
643	{ "S_SECUREPORTENABLE", 29, 1 },
644	{ "S_ARPENABLE", 28, 1 },
645	{ "S_IPMI_VLAN", 0, 16 },
646	{ "TP_IPMI_CFG2", 0x2F, 0 },
647	{ "S_SECUREPORT", 16, 16 },
648	{ "S_PRIMARYPORT", 0, 16 },
649	{ "TP_RSS_PF0_CONFIG", 0x30, 0 },
650	{ "S_MAPENABLE", 31, 1 },
651	{ "S_CHNENABLE", 30, 1 },
652	{ "S_PRTENABLE", 29, 1 },
653	{ "S_UDPFOURTUPEN", 28, 1 },
654	{ "S_IP6FOURTUPEN", 27, 1 },
655	{ "S_IP6TWOTUPEN", 26, 1 },
656	{ "S_IP4FOURTUPEN", 25, 1 },
657	{ "S_IP4TWOTUPEN", 24, 1 },
658	{ "S_IVFWIDTH", 20, 4 },
659	{ "S_CH1DEFAULTQUEUE", 10, 10 },
660	{ "S_CH0DEFAULTQUEUE", 0, 10 },
661	{ "TP_RSS_PF1_CONFIG", 0x31, 0 },
662	{ "S_MAPENABLE", 31, 1 },
663	{ "S_CHNENABLE", 30, 1 },
664	{ "S_PRTENABLE", 29, 1 },
665	{ "S_UDPFOURTUPEN", 28, 1 },
666	{ "S_IP6FOURTUPEN", 27, 1 },
667	{ "S_IP6TWOTUPEN", 26, 1 },
668	{ "S_IP4FOURTUPEN", 25, 1 },
669	{ "S_IP4TWOTUPEN", 24, 1 },
670	{ "S_IVFWIDTH", 20, 4 },
671	{ "S_CH1DEFAULTQUEUE", 10, 10 },
672	{ "S_CH0DEFAULTQUEUE", 0, 10 },
673	{ "TP_RSS_PF2_CONFIG", 0x32, 0 },
674	{ "S_MAPENABLE", 31, 1 },
675	{ "S_CHNENABLE", 30, 1 },
676	{ "S_PRTENABLE", 29, 1 },
677	{ "S_UDPFOURTUPEN", 28, 1 },
678	{ "S_IP6FOURTUPEN", 27, 1 },
679	{ "S_IP6TWOTUPEN", 26, 1 },
680	{ "S_IP4FOURTUPEN", 25, 1 },
681	{ "S_IP4TWOTUPEN", 24, 1 },
682	{ "S_IVFWIDTH", 20, 4 },
683	{ "S_CH1DEFAULTQUEUE", 10, 10 },
684	{ "S_CH0DEFAULTQUEUE", 0, 10 },
685	{ "TP_RSS_PF3_CONFIG", 0x33, 0 },
686	{ "S_MAPENABLE", 31, 1 },
687	{ "S_CHNENABLE", 30, 1 },
688	{ "S_PRTENABLE", 29, 1 },
689	{ "S_UDPFOURTUPEN", 28, 1 },
690	{ "S_IP6FOURTUPEN", 27, 1 },
691	{ "S_IP6TWOTUPEN", 26, 1 },
692	{ "S_IP4FOURTUPEN", 25, 1 },
693	{ "S_IP4TWOTUPEN", 24, 1 },
694	{ "S_IVFWIDTH", 20, 4 },
695	{ "S_CH1DEFAULTQUEUE", 10, 10 },
696	{ "S_CH0DEFAULTQUEUE", 0, 10 },
697	{ "TP_RSS_PF4_CONFIG", 0x34, 0 },
698	{ "S_MAPENABLE", 31, 1 },
699	{ "S_CHNENABLE", 30, 1 },
700	{ "S_PRTENABLE", 29, 1 },
701	{ "S_UDPFOURTUPEN", 28, 1 },
702	{ "S_IP6FOURTUPEN", 27, 1 },
703	{ "S_IP6TWOTUPEN", 26, 1 },
704	{ "S_IP4FOURTUPEN", 25, 1 },
705	{ "S_IP4TWOTUPEN", 24, 1 },
706	{ "S_IVFWIDTH", 20, 4 },
707	{ "S_CH1DEFAULTQUEUE", 10, 10 },
708	{ "S_CH0DEFAULTQUEUE", 0, 10 },
709	{ "TP_RSS_PF5_CONFIG", 0x35, 0 },
710	{ "S_MAPENABLE", 31, 1 },
711	{ "S_CHNENABLE", 30, 1 },
712	{ "S_PRTENABLE", 29, 1 },
713	{ "S_UDPFOURTUPEN", 28, 1 },
714	{ "S_IP6FOURTUPEN", 27, 1 },
715	{ "S_IP6TWOTUPEN", 26, 1 },
716	{ "S_IP4FOURTUPEN", 25, 1 },
717	{ "S_IP4TWOTUPEN", 24, 1 },
718	{ "S_IVFWIDTH", 20, 4 },
719	{ "S_CH1DEFAULTQUEUE", 10, 10 },
720	{ "S_CH0DEFAULTQUEUE", 0, 10 },
721	{ "TP_RSS_PF6_CONFIG", 0x36, 0 },
722	{ "S_MAPENABLE", 31, 1 },
723	{ "S_CHNENABLE", 30, 1 },
724	{ "S_PRTENABLE", 29, 1 },
725	{ "S_UDPFOURTUPEN", 28, 1 },
726	{ "S_IP6FOURTUPEN", 27, 1 },
727	{ "S_IP6TWOTUPEN", 26, 1 },
728	{ "S_IP4FOURTUPEN", 25, 1 },
729	{ "S_IP4TWOTUPEN", 24, 1 },
730	{ "S_IVFWIDTH", 20, 4 },
731	{ "S_CH1DEFAULTQUEUE", 10, 10 },
732	{ "S_CH0DEFAULTQUEUE", 0, 10 },
733	{ "TP_RSS_PF7_CONFIG", 0x37, 0 },
734	{ "S_MAPENABLE", 31, 1 },
735	{ "S_CHNENABLE", 30, 1 },
736	{ "S_PRTENABLE", 29, 1 },
737	{ "S_UDPFOURTUPEN", 28, 1 },
738	{ "S_IP6FOURTUPEN", 27, 1 },
739	{ "S_IP6TWOTUPEN", 26, 1 },
740	{ "S_IP4FOURTUPEN", 25, 1 },
741	{ "S_IP4TWOTUPEN", 24, 1 },
742	{ "S_IVFWIDTH", 20, 4 },
743	{ "S_CH1DEFAULTQUEUE", 10, 10 },
744	{ "S_CH0DEFAULTQUEUE", 0, 10 },
745	{ "TP_RSS_PF_MAP", 0x38, 0 },
746	{ "S_LKPIDXSIZE", 24, 2 },
747	{ "S_PF7LKPIDX", 21, 3 },
748	{ "S_PF6LKPIDX", 18, 3 },
749	{ "S_PF5LKPIDX", 15, 3 },
750	{ "S_PF4LKPIDX", 12, 3 },
751	{ "S_PF3LKPIDX", 9, 3 },
752	{ "S_PF2LKPIDX", 6, 3 },
753	{ "S_PF1LKPIDX", 3, 3 },
754	{ "S_PF0LKPIDX", 0, 3 },
755	{ "TP_RSS_PF_MSK", 0x39, 0 },
756	{ "S_PF7MSKSIZE", 28, 4 },
757	{ "S_PF6MSKSIZE", 24, 4 },
758	{ "S_PF5MSKSIZE", 20, 4 },
759	{ "S_PF4MSKSIZE", 16, 4 },
760	{ "S_PF3MSKSIZE", 12, 4 },
761	{ "S_PF2MSKSIZE", 8, 4 },
762	{ "S_PF1MSKSIZE", 4, 4 },
763	{ "S_PF0MSKSIZE", 0, 4 },
764	{ "TP_RSS_VFL_CONFIG", 0x3A, 0 },
765	{ "S_KEYSCRAMBLE", 0, 32 },
766	{ "TP_RSS_VFH_CONFIG", 0x3B, 0 },
767	{ "S_ENABLEUDPHASH", 31, 1 },
768	{ "S_VFUPEN", 30, 1 },
769	{ "S_RESERVED", 29, 1 },
770	{ "S_VFVLNEX", 28, 1 },
771	{ "S_VFPRTEN", 27, 1 },
772	{ "S_VFCHNEN", 26, 1 },
773	{ "S_DEFAULTQUEUE", 16, 10 },
774	{ "S_VFLKPIDX", 8, 8 },
775	{ "S_VFIP6FOURTUPEN", 7, 1 },
776	{ "S_VFIP6TWOTUPEN", 6, 1 },
777	{ "S_VFIP4FOURTUPEN", 5, 1 },
778	{ "S_VFIP4TWOTUPEN", 4, 1 },
779	{ "S_KEYINDEX", 0, 4 },
780	{ NULL }
781};
782
783static struct cudbg_reg_info t5_tp_pio_regs_20_to_3b[] = {
784	{ "TP_RX_SCHED_MAP", 0x20, 0 },
785	{ "S_RXMAPCHANNEL3", 24, 8 },
786	{ "S_RXMAPCHANNEL2", 16, 8 },
787	{ "S_RXMAPCHANNEL1", 8, 8 },
788	{ "S_RXMAPCHANNEL0", 0, 8 },
789	{ "TP_RX_SCHED_SGE", 0x21, 0 },
790	{ "S_RXSGEMOD1", 12, 4 },
791	{ "S_RXSGEMOD0", 8, 4 },
792	{ "S_RXSGECHANNEL3", 3, 1 },
793	{ "S_RXSGECHANNEL2", 2, 1 },
794	{ "S_RXSGECHANNEL1", 1, 1 },
795	{ "S_RXSGECHANNEL0", 0, 1 },
796	{ "TP_TX_SCHED_MAP", 0x22, 0 },
797	{ "S_TXMAPCHANNEL3", 12, 4 },
798	{ "S_TXMAPCHANNEL2", 8, 4 },
799	{ "S_TXMAPCHANNEL1", 4, 4 },
800	{ "S_TXMAPCHANNEL0", 0, 4 },
801	{ "TP_TX_SCHED_HDR", 0x23, 0 },
802	{ "S_TXMAPHDRCHANNEL7", 28, 4 },
803	{ "S_TXMAPHDRCHANNEL6", 24, 4 },
804	{ "S_TXMAPHDRCHANNEL5", 20, 4 },
805	{ "S_TXMAPHDRCHANNEL4", 16, 4 },
806	{ "S_TXMAPHDRCHANNEL3", 12, 4 },
807	{ "S_TXMAPHDRCHANNEL2", 8, 4 },
808	{ "S_TXMAPHDRCHANNEL1", 4, 4 },
809	{ "S_TXMAPHDRCHANNEL0", 0, 4 },
810	{ "TP_TX_SCHED_FIFO", 0x24, 0 },
811	{ "S_TXMAPFIFOCHANNEL7", 28, 4 },
812	{ "S_TXMAPFIFOCHANNEL6", 24, 4 },
813	{ "S_TXMAPFIFOCHANNEL5", 20, 4 },
814	{ "S_TXMAPFIFOCHANNEL4", 16, 4 },
815	{ "S_TXMAPFIFOCHANNEL3", 12, 4 },
816	{ "S_TXMAPFIFOCHANNEL2", 8, 4 },
817	{ "S_TXMAPFIFOCHANNEL1", 4, 4 },
818	{ "S_TXMAPFIFOCHANNEL0", 0, 4 },
819	{ "TP_TX_SCHED_PCMD", 0x25, 0 },
820	{ "S_TXMAPPCMDCHANNEL7", 28, 4 },
821	{ "S_TXMAPPCMDCHANNEL6", 24, 4 },
822	{ "S_TXMAPPCMDCHANNEL5", 20, 4 },
823	{ "S_TXMAPPCMDCHANNEL4", 16, 4 },
824	{ "S_TXMAPPCMDCHANNEL3", 12, 4 },
825	{ "S_TXMAPPCMDCHANNEL2", 8, 4 },
826	{ "S_TXMAPPCMDCHANNEL1", 4, 4 },
827	{ "S_TXMAPPCMDCHANNEL0", 0, 4 },
828	{ "TP_TX_SCHED_LPBK", 0x26, 0 },
829	{ "S_TXMAPLPBKCHANNEL7", 28, 4 },
830	{ "S_TXMAPLPBKCHANNEL6", 24, 4 },
831	{ "S_TXMAPLPBKCHANNEL5", 20, 4 },
832	{ "S_TXMAPLPBKCHANNEL4", 16, 4 },
833	{ "S_TXMAPLPBKCHANNEL3", 12, 4 },
834	{ "S_TXMAPLPBKCHANNEL2", 8, 4 },
835	{ "S_TXMAPLPBKCHANNEL1", 4, 4 },
836	{ "S_TXMAPLPBKCHANNEL0", 0, 4 },
837	{ "TP_CHANNEL_MAP", 0x27, 0 },
838	{ "RxMapChannelELN", 16, 4 },
839	{ "RxMapE2LChannel3", 14, 2 },
840	{ "RxMapE2LChannel2", 12, 2 },
841	{ "RxMapE2LChannel1", 10, 2 },
842	{ "RxMapE2LChannel0", 8, 2 },
843	{ "RxMapC2CChannel3", 7, 1 },
844	{ "RxMapC2CChannel2", 6, 1 },
845	{ "RxMapC2CChannel1", 5, 1 },
846	{ "RxMapC2CChannel0", 4, 1 },
847	{ "RxMapE2CChannel3", 3, 1 },
848	{ "RxMapE2CChannel2", 2, 1 },
849	{ "RxMapE2CChannel1", 1, 1 },
850	{ "RxMapE2CChannel0", 0, 1 },
851	{ "TP_RX_LPBK", 0x28, 0 },
852	{ "TP_TX_LPBK", 0x29, 0 },
853	{ "TP_TX_SCHED_PPP", 0x2A, 0 },
854	{ "S_TXPPPENPORT3", 24, 8 },
855	{ "S_TXPPPENPORT2", 16, 8 },
856	{ "S_TXPPPENPORT1", 8, 8 },
857	{ "S_TXPPPENPORT0", 0, 8 },
858	{ "TP_RX_SCHED_FIFO", 0x2B, 0 },
859	{ "S_COMMITLIMIT1H", 24, 8 },
860	{ "S_COMMITLIMIT1L", 16, 8 },
861	{ "S_COMMITLIMIT0H", 8, 8 },
862	{ "S_COMMITLIMIT0L", 0, 8 },
863	{ "TP_IPMI_CFG1", 0x2E, 0 },
864	{ "S_VLANENABLE", 31, 1 },
865	{ "S_PRIMARYPORTENABLE", 30, 1 },
866	{ "S_SECUREPORTENABLE", 29, 1 },
867	{ "S_ARPENABLE", 28, 1 },
868	{ "S_IPMI_VLAN", 0, 16 },
869	{ "TP_IPMI_CFG2", 0x2F, 0 },
870	{ "S_SECUREPORT", 16, 16 },
871	{ "S_PRIMARYPORT", 0, 16 },
872	{ "TP_RSS_PF0_CONFIG", 0x30, 0 },
873	{ "S_MAPENABLE", 31, 1 },
874	{ "S_PRTENABLE", 30, 1 },
875	{ "S_CHNENABLE", 29, 1 },
876	{ "S_UDPFOURTUPEN", 28, 1 },
877	{ "S_IP6FOURTUPEN", 27, 1 },
878	{ "S_IP6TWOTUPEN", 26, 1 },
879	{ "S_IP4FOURTUPEN", 25, 1 },
880	{ "S_IP4TWOTUPEN", 24, 1 },
881	{ "S_IVFWIDTH", 20, 4 },
882	{ "S_CH1DEFAULTQUEUE", 10, 10 },
883	{ "S_CH0DEFAULTQUEUE", 0, 10 },
884	{ "TP_RSS_PF1_CONFIG", 0x31, 0 },
885	{ "S_MAPENABLE", 31, 1 },
886	{ "S_PRTENABLE", 30, 1 },
887	{ "S_CHNENABLE", 29, 1 },
888	{ "S_UDPFOURTUPEN", 28, 1 },
889	{ "S_IP6FOURTUPEN", 27, 1 },
890	{ "S_IP6TWOTUPEN", 26, 1 },
891	{ "S_IP4FOURTUPEN", 25, 1 },
892	{ "S_IP4TWOTUPEN", 24, 1 },
893	{ "S_IVFWIDTH", 20, 4 },
894	{ "S_CH1DEFAULTQUEUE", 10, 10 },
895	{ "S_CH0DEFAULTQUEUE", 0, 10 },
896	{ "TP_RSS_PF2_CONFIG", 0x32, 0 },
897	{ "S_MAPENABLE", 31, 1 },
898	{ "S_PRTENABLE", 30, 1 },
899	{ "S_CHNENABLE", 29, 1 },
900	{ "S_UDPFOURTUPEN", 28, 1 },
901	{ "S_IP6FOURTUPEN", 27, 1 },
902	{ "S_IP6TWOTUPEN", 26, 1 },
903	{ "S_IP4FOURTUPEN", 25, 1 },
904	{ "S_IP4TWOTUPEN", 24, 1 },
905	{ "S_IVFWIDTH", 20, 4 },
906	{ "S_CH1DEFAULTQUEUE", 10, 10 },
907	{ "S_CH0DEFAULTQUEUE", 0, 10 },
908	{ "TP_RSS_PF3_CONFIG", 0x33, 0 },
909	{ "S_MAPENABLE", 31, 1 },
910	{ "S_PRTENABLE", 30, 1 },
911	{ "S_CHNENABLE", 29, 1 },
912	{ "S_UDPFOURTUPEN", 28, 1 },
913	{ "S_IP6FOURTUPEN", 27, 1 },
914	{ "S_IP6TWOTUPEN", 26, 1 },
915	{ "S_IP4FOURTUPEN", 25, 1 },
916	{ "S_IP4TWOTUPEN", 24, 1 },
917	{ "S_IVFWIDTH", 20, 4 },
918	{ "S_CH1DEFAULTQUEUE", 10, 10 },
919	{ "S_CH0DEFAULTQUEUE", 0, 10 },
920	{ "TP_RSS_PF4_CONFIG", 0x34, 0 },
921	{ "S_MAPENABLE", 31, 1 },
922	{ "S_PRTENABLE", 30, 1 },
923	{ "S_CHNENABLE", 29, 1 },
924	{ "S_UDPFOURTUPEN", 28, 1 },
925	{ "S_IP6FOURTUPEN", 27, 1 },
926	{ "S_IP6TWOTUPEN", 26, 1 },
927	{ "S_IP4FOURTUPEN", 25, 1 },
928	{ "S_IP4TWOTUPEN", 24, 1 },
929	{ "S_IVFWIDTH", 20, 4 },
930	{ "S_CH1DEFAULTQUEUE", 10, 10 },
931	{ "S_CH0DEFAULTQUEUE", 0, 10 },
932	{ "TP_RSS_PF5_CONFIG", 0x35, 0 },
933	{ "S_MAPENABLE", 31, 1 },
934	{ "S_PRTENABLE", 30, 1 },
935	{ "S_CHNENABLE", 29, 1 },
936	{ "S_UDPFOURTUPEN", 28, 1 },
937	{ "S_IP6FOURTUPEN", 27, 1 },
938	{ "S_IP6TWOTUPEN", 26, 1 },
939	{ "S_IP4FOURTUPEN", 25, 1 },
940	{ "S_IP4TWOTUPEN", 24, 1 },
941	{ "S_IVFWIDTH", 20, 4 },
942	{ "S_CH1DEFAULTQUEUE", 10, 10 },
943	{ "S_CH0DEFAULTQUEUE", 0, 10 },
944	{ "TP_RSS_PF6_CONFIG", 0x36, 0 },
945	{ "S_MAPENABLE", 31, 1 },
946	{ "S_PRTENABLE", 30, 1 },
947	{ "S_CHNENABLE", 29, 1 },
948	{ "S_UDPFOURTUPEN", 28, 1 },
949	{ "S_IP6FOURTUPEN", 27, 1 },
950	{ "S_IP6TWOTUPEN", 26, 1 },
951	{ "S_IP4FOURTUPEN", 25, 1 },
952	{ "S_IP4TWOTUPEN", 24, 1 },
953	{ "S_IVFWIDTH", 20, 4 },
954	{ "S_CH1DEFAULTQUEUE", 10, 10 },
955	{ "S_CH0DEFAULTQUEUE", 0, 10 },
956	{ "TP_RSS_PF7_CONFIG", 0x37, 0 },
957	{ "S_MAPENABLE", 31, 1 },
958	{ "S_PRTENABLE", 30, 1 },
959	{ "S_CHNENABLE", 29, 1 },
960	{ "S_UDPFOURTUPEN", 28, 1 },
961	{ "S_IP6FOURTUPEN", 27, 1 },
962	{ "S_IP6TWOTUPEN", 26, 1 },
963	{ "S_IP4FOURTUPEN", 25, 1 },
964	{ "S_IP4TWOTUPEN", 24, 1 },
965	{ "S_IVFWIDTH", 20, 4 },
966	{ "S_CH1DEFAULTQUEUE", 10, 10 },
967	{ "S_CH0DEFAULTQUEUE", 0, 10 },
968	{ "TP_RSS_PF_MAP", 0x38, 0 },
969	{ "S_LKPIDXSIZE", 24, 2 },
970	{ "S_PF7LKPIDX", 21, 3 },
971	{ "S_PF6LKPIDX", 18, 3 },
972	{ "S_PF5LKPIDX", 15, 3 },
973	{ "S_PF4LKPIDX", 12, 3 },
974	{ "S_PF3LKPIDX", 9, 3 },
975	{ "S_PF2LKPIDX", 6, 3 },
976	{ "S_PF1LKPIDX", 3, 3 },
977	{ "S_PF0LKPIDX", 0, 3 },
978	{ "TP_RSS_PF_MSK", 0x39, 0 },
979	{ "S_PF7MSKSIZE", 28, 4 },
980	{ "S_PF6MSKSIZE", 24, 4 },
981	{ "S_PF5MSKSIZE", 20, 4 },
982	{ "S_PF4MSKSIZE", 16, 4 },
983	{ "S_PF3MSKSIZE", 12, 4 },
984	{ "S_PF2MSKSIZE", 8, 4 },
985	{ "S_PF1MSKSIZE", 4, 4 },
986	{ "S_PF0MSKSIZE", 0, 4 },
987	{ "TP_RSS_VFL_CONFIG", 0x3A, 0 },
988	{ "S_KEYSCRAMBLE", 0, 32 },
989	{ "TP_RSS_VFH_CONFIG", 0x3B, 0 },
990	{ "S_ENABLEUDPHASH", 31, 1 },
991	{ "S_VFUPEN", 30, 1 },
992	{ "S_RESERVED", 29, 1 },
993	{ "S_VFVLNEX", 28, 1 },
994	{ "S_VFPRTEN", 27, 1 },
995	{ "S_VFCHNEN", 26, 1 },
996	{ "S_DEFAULTQUEUE", 16, 10 },
997	{ "S_VFLKPIDX", 8, 8 },
998	{ "S_VFIP6FOURTUPEN", 7, 1 },
999	{ "S_VFIP6TWOTUPEN", 6, 1 },
1000	{ "S_VFIP4FOURTUPEN", 5, 1 },
1001	{ "S_VFIP4TWOTUPEN", 4, 1 },
1002	{ "S_KEYINDEX", 0, 4 },
1003	{ NULL }
1004};
1005
1006static struct cudbg_reg_info t6_tp_pio_regs_40_to_49[] = {
1007	{ "TP_RSS_SECRET_KEY0", 0x40, 0 },
1008	{ "TP_RSS_SECRET_KEY1", 0x41, 0 },
1009	{ "TP_RSS_SECRET_KEY2", 0x42, 0 },
1010	{ "TP_RSS_SECRET_KEY3", 0x43, 0 },
1011	{ "TP_RSS_SECRET_KEY4", 0x44, 0 },
1012	{ "TP_RSS_SECRET_KEY5", 0x45, 0 },
1013	{ "TP_RSS_SECRET_KEY6", 0x46, 0 },
1014	{ "TP_RSS_SECRET_KEY7", 0x47, 0 },
1015	{ "TP_RSS_SECRET_KEY8", 0x48, 0 },
1016	{ "TP_RSS_SECRET_KEY9", 0x49, 0 },
1017	{ NULL }
1018};
1019
1020static struct cudbg_reg_info t6_tp_pio_regs_50_to_59[] = {
1021	{ "TP_ETHER_TYPE_VL", 0x50, 0 },
1022	{ "S_CQFCTYPE", 16, 16 },
1023	{ "S_VLANTYPE", 0, 16 },
1024	{ "TP_ETHER_TYPE_IP", 0x51, 0 },
1025	{ "S_IPV6TYPE", 16, 16 },
1026	{ "S_IPV4TYPE", 0, 16 },
1027	{ "TP_ETHER_TYPE_FW", 0x52, 0 },
1028	{ "S_ETHTYPE1", 16, 16 },
1029	{ "S_ETHTYPE0", 0, 16 },
1030	{ "TP_VXLAN_HEADER", 0x53, 0 },
1031	{ "S_VXLANPORT", 0, 16 },
1032	{ "TP_CORE_POWER", 0x54, 0 },
1033	{ "S_SLEEPRDYVNT", 12, 1 },
1034	{ "S_SLEEPRDYTBL", 11, 1 },
1035	{ "S_SLEEPRDYMIB", 10, 1 },
1036	{ "S_SLEEPRDYARP", 9, 1 },
1037	{ "S_SLEEPRDYRSS", 8, 1 },
1038	{ "S_SLEEPREQVNT", 4, 1 },
1039	{ "S_SLEEPREQTBL", 3, 1 },
1040	{ "S_SLEEPREQMIB", 2, 1 },
1041	{ "S_SLEEPREQARP", 1, 1 },
1042	{ "S_SLEEPREQRSS", 0, 1 },
1043	{ "TP_CORE_RDMA", 0x55, 0 },
1044	{ "S_SHAREDRQEN", 31, 1 },
1045	{ "S_SHAREDXRC", 30, 1 },
1046	{ "S_IMMEDIATEOP", 20, 4 },
1047	{ "S_IMMEDIATESE", 16, 4 },
1048	{ "S_ATOMICREQOP", 12, 4 },
1049	{ "S_ATOMICRSPOP", 8, 4 },
1050	{ "S_IMMEDIASEEN", 1, 1 },
1051	{ "S_IMMEDIATEEN", 0, 1 },
1052	{ "TP_FRAG_CONFIG", 0x56, 0 },
1053	{ "Reserved", 16, 16 },
1054	{ "UserMode", 14, 2 },
1055	{ "FcoeMode", 12, 2 },
1056	{ "IandpMode", 10, 2 },
1057	{ "RddpMode", 8, 2 },
1058	{ "IwarpMode", 6, 2 },
1059	{ "IscsiMode", 4, 2 },
1060	{ "DdpMode", 2, 2 },
1061	{ "PassMode", 0, 2 },
1062	{ "TP_CMM_CONFIG", 0x57, 0 },
1063	{ "WrCntIdle", 16, 16 },
1064	{ "RdThreshold", 8, 7 },
1065	{ "WrThrLevel2", 7, 1 },
1066	{ "WrThrLevel1", 6, 1 },
1067	{ "WrThrThreshEn", 5, 1 },
1068	{ "WrThrThresh", 0, 5},
1069	{ "TP_VXLAN_CONFIG", 0x58, 0 },
1070	{ "VxLanFlags", 16, 16},
1071	{ "VxLanType", 0, 16},
1072	{ "TP_NVGRE_CONFIG", 0x59, 0 },
1073	{ "GreFlags", 16, 16 },
1074	{ "GreType", 0, 16 },
1075	{ NULL }
1076};
1077
1078static struct cudbg_reg_info t5_tp_pio_regs_40_to_52[] = {
1079	{ "TP_RSS_SECRET_KEY0", 0x40, 0 },
1080	{ "TP_RSS_SECRET_KEY1", 0x41, 0 },
1081	{ "TP_RSS_SECRET_KEY2", 0x42, 0 },
1082	{ "TP_RSS_SECRET_KEY3", 0x43, 0 },
1083	{ "TP_RSS_SECRET_KEY4", 0x44, 0 },
1084	{ "TP_RSS_SECRET_KEY5", 0x45, 0 },
1085	{ "TP_RSS_SECRET_KEY6", 0x46, 0 },
1086	{ "TP_RSS_SECRET_KEY7", 0x47, 0 },
1087	{ "TP_RSS_SECRET_KEY8", 0x48, 0 },
1088	{ "TP_RSS_SECRET_KEY9", 0x49, 0 },
1089	{ "TP_ETHER_TYPE_VL", 0x50, 0 },
1090	{ "S_CQFCTYPE", 16, 16 },
1091	{ "S_VLANTYPE", 0, 16 },
1092	{ "TP_ETHER_TYPE_IP", 0x51, 0 },
1093	{ "S_IPV6TYPE", 16, 16 },
1094	{ "S_IPV4TYPE", 0, 16 },
1095	{ "TP_ETHER_TYPE_FW", 0x52, 0 },
1096	{ "S_ETHTYPE1", 16, 16 },
1097	{ "S_ETHTYPE0", 0, 16 },
1098	{ NULL }
1099};
1100
1101static struct cudbg_reg_info t5_tp_pio_regs_54_to_55[] = {
1102	{ "TP_CORE_POWER", 0x54, 0 },
1103	{ "S_SLEEPRDYVNT", 12, 1 },
1104	{ "S_SLEEPRDYTBL", 11, 1 },
1105	{ "S_SLEEPRDYMIB", 10, 1 },
1106	{ "S_SLEEPRDYARP", 9, 1 },
1107	{ "S_SLEEPRDYRSS", 8, 1 },
1108	{ "S_SLEEPREQVNT", 4, 1 },
1109	{ "S_SLEEPREQTBL", 3, 1 },
1110	{ "S_SLEEPREQMIB", 2, 1 },
1111	{ "S_SLEEPREQARP", 1, 1 },
1112	{ "S_SLEEPREQRSS", 0, 1 },
1113	{ "TP_CORE_RDMA", 0x55, 0 },
1114	{ "S_IMMEDIATEOP", 20, 4 },
1115	{ "S_IMMEDIATESE", 16, 4 },
1116	{ "S_ATOMICREQOP", 12, 4 },
1117	{ "S_ATOMICRSPOP", 8, 4 },
1118	{ "S_IMMEDIASEEN", 1, 1 },
1119	{ "S_IMMEDIATEEN", 0, 1 },
1120	{ NULL }
1121};
1122
1123static struct cudbg_reg_info sge_debug_data_high[] = {
1124	{"SGE_DEBUG_DATA_HIGH_INDEX_0", 0x1280},
1125	{"SGE_DEBUG_DATA_HIGH_INDEX_1", 0x1284},
1126	{"SGE_DEBUG_DATA_HIGH_INDEX_2", 0x1288},
1127	{"SGE_DEBUG_DATA_HIGH_INDEX_3", 0x128c},
1128	{"SGE_DEBUG_DATA_HIGH_INDEX_4", 0x1290},
1129	{"SGE_DEBUG_DATA_HIGH_INDEX_5", 0x1294},
1130	{"SGE_DEBUG_DATA_HIGH_INDEX_6", 0x1298},
1131	{"SGE_DEBUG_DATA_HIGH_INDEX_7", 0x129c},
1132	{"SGE_DEBUG_DATA_HIGH_INDEX_8", 0x12a0},
1133	{"SGE_DEBUG_DATA_HIGH_INDEX_9", 0x12a4},
1134	{"SGE_DEBUG_DATA_HIGH_INDEX_10", 0x12a8},
1135	{"SGE_DEBUG_DATA_HIGH_INDEX_11", 0x12ac},
1136	{"SGE_DEBUG_DATA_HIGH_INDEX_12", 0x12b0},
1137	{"SGE_DEBUG_DATA_HIGH_INDEX_13", 0x12b4},
1138	{"SGE_DEBUG_DATA_HIGH_INDEX_14", 0x12b8},
1139	{"SGE_DEBUG_DATA_HIGH_INDEX_15", 0x12bc},
1140
1141};
1142
1143static struct cudbg_reg_info sge_debug_data_low[] = {
1144	{"SGE_DEBUG_DATA_LOW_INDEX_0", 0x12c0},
1145	{"SGE_DEBUG_DATA_LOW_INDEX_1", 0x12c4},
1146	{"SGE_DEBUG_DATA_LOW_INDEX_2", 0x12c8},
1147	{"SGE_DEBUG_DATA_LOW_INDEX_3", 0x12cc},
1148	{"SGE_DEBUG_DATA_LOW_INDEX_4", 0x12d0},
1149	{"SGE_DEBUG_DATA_LOW_INDEX_5", 0x12d4},
1150	{"SGE_DEBUG_DATA_LOW_INDEX_6", 0x12d8},
1151	{"SGE_DEBUG_DATA_LOW_INDEX_7", 0x12dc},
1152	{"SGE_DEBUG_DATA_LOW_INDEX_8", 0x12e0},
1153	{"SGE_DEBUG_DATA_LOW_INDEX_9", 0x12e4},
1154	{"SGE_DEBUG_DATA_LOW_INDEX_10", 0x12e8},
1155	{"SGE_DEBUG_DATA_LOW_INDEX_11", 0x12ec},
1156	{"SGE_DEBUG_DATA_LOW_INDEX_12", 0x12f0},
1157	{"SGE_DEBUG_DATA_LOW_INDEX_13", 0x12f4},
1158	{"SGE_DEBUG_DATA_LOW_INDEX_14", 0x12f8},
1159	{"SGE_DEBUG_DATA_LOW_INDEX_15", 0x12fc},
1160};
1161
1162static struct cudbg_reg_info t6_tp_pio_regs_60_to_6d[] = {
1163	{ "TP_DBG_CLEAR", 0x60, 0 },
1164	{ "TP_DBG_CORE_HDR0", 0x61, 0 },
1165	{ "S_RESERVED", 17, 15 },
1166	{ "S_E_TCP_OP_SRDY", 16, 1 },
1167	{ "S_E_PLD_TXZEROP_SRDY", 15, 1 },
1168	{ "S_E_PLD_RX_SRDY", 14, 1 },
1169	{ "S_E_RX_ERROR_SRDY", 13, 1 },
1170	{ "S_E_RX_ISS_SRDY", 12, 1 },
1171	{ "S_C_TCP_OP_SRDY", 11, 1 },
1172	{ "S_C_PLD_TXZEROP_SRDY", 10, 1 },
1173	{ "S_C_PLD_RX_SRDY", 9, 1 },
1174	{ "S_C_RX_ERROR_SRDY", 8, 1 },
1175	{ "S_C_RX_ISS_SRDY", 7, 1 },
1176	{ "S_E_CPL5_TXVALID", 6, 1 },
1177	{ "S_E_ETH_TXVALID", 5, 1 },
1178	{ "S_E_IP_TXVALID", 4, 1 },
1179	{ "S_E_TCP_TXVALID", 3, 1 },
1180	{ "S_C_CPL5_RXVALID", 2, 1 },
1181	{ "S_C_CPL5_TXVALID", 1, 1 },
1182	{ "S_E_TCP_OPT_RXVALID", 0, 1 },
1183	{ "TP_DBG_CORE_HDR1", 0x62, 0 },
1184	{ "S_RESERVED", 7, 25 },
1185	{ "S_E_CPL5_TXFULL", 6, 1 },
1186	{ "S_E_ETH_TXFULL", 5, 1 },
1187	{ "S_E_IP_TXFULL", 4, 1 },
1188	{ "S_E_TCP_TXFULL", 3, 1 },
1189	{ "S_C_CPL5_RXFULL", 2, 1 },
1190	{ "S_C_CPL5_TXFULL", 1, 1 },
1191	{ "S_E_TCP_OPT_RXFULL", 0, 1 },
1192	{ "TP_DBG_CORE_FATAL", 0x63, 0 },
1193	{ "S_EMSGFATAL", 31, 1 },
1194	{ "S_CMSGFATAL", 30, 1 },
1195	{ "S_PAWSFATAL", 29, 1 },
1196	{ "S_SRAMFATAL", 28, 1 },
1197	{ "S_CPCMDCONG", 24, 4 },
1198	{ "S_EPCMDCONG", 22, 2 },
1199	{ "S_CPCMDLENFATAL", 21, 1 },
1200	{ "S_EPCMDLENFATAL", 20, 1 },
1201	{ "S_CPCMDVALID", 16, 4 },
1202	{ "S_CPCMDAFULL", 12, 4 },
1203	{ "S_EPCMDVALID", 10, 2 },
1204	{ "S_EPCMDAFULL", 8, 2 },
1205	{ "S_CPCMDEOIFATAL", 7, 1 },
1206	{ "S_CPCMDTTLFATAL", 6, 1 },
1207	{ "S_CDATACHNFATAL", 5, 1 },
1208	{ "S_RESERVED", 4, 1 },
1209	{ "S_CNONZEROPPOPCNT", 2, 2 },
1210	{ "S_CPCMDEOICNT", 0, 2 },
1211	{ "TP_DBG_CORE_OUT", 0x64, 0 },
1212	{ "S_CRXBUSYOUT", 31, 1 },
1213	{ "S_CTXBUSYOUT", 30, 1 },
1214	{ "S_CRDCPLPKT", 29, 1 },
1215	{ "S_CRDTCPPKT", 28, 1 },
1216	{ "S_CNEWMSG", 27, 1 },
1217	{ "S_CCPLENC", 26, 1 },
1218	{ "S_CWRCPLPKT", 25, 1 },
1219	{ "S_CWRETHPKT", 24, 1 },
1220	{ "S_CWRIPPKT", 23, 1 },
1221	{ "S_CWRTCPPKT", 22, 1 },
1222	{ "S_CWRZEROP", 21, 1 },
1223	{ "S_CCPLTXFULL", 20, 1 },
1224	{ "S_CETHTXFULL", 19, 1 },
1225	{ "S_CIPTXFULL", 18, 1 },
1226	{ "S_CTCPTXFULL", 17, 1 },
1227	{ "S_CPLDTXZEROPDRDY", 16, 1 },
1228	{ "S_ERXBUSYOUT", 15, 1 },
1229	{ "S_ETXBUSYOUT", 14, 1 },
1230	{ "S_ERDCPLPKT", 13, 1 },
1231	{ "S_ERDTCPPKT", 12, 1 },
1232	{ "S_ENEWMSG", 11, 1 },
1233	{ "S_RESERVED1", 10, 1 },
1234	{ "S_EWRCPLPKT", 9, 1 },
1235	{ "S_EWRETHPKT", 8, 1 },
1236	{ "S_EWRIPPKT", 7, 1 },
1237	{ "S_EWRTCPPKT", 6, 1 },
1238	{ "S_EWRZEROP", 5, 1 },
1239	{ "S_ECPLTXFULL", 4, 1 },
1240	{ "S_EETHTXFULL", 3, 1 },
1241	{ "S_EIPTXFULL", 2, 1 },
1242	{ "S_ETCPTXFULL", 1, 1 },
1243	{ "S_EPLDTXZEROPDRDY", 0, 1 },
1244	{ "TP_DBG_CORE_TID", 0x65, 0 },
1245	{ "S_LINENUMBER", 24, 7 },
1246	{ "S_SPURIOUSMSG", 23, 1 },
1247	{ "S_SRC", 21, 2 },
1248	{ "S_SYNLEARNED", 20, 1 },
1249	{ "S_TIDVALUE", 0, 20 },
1250	{ "TP_DBG_ENG_RES0", 0x66, 0 },
1251	{ "S_RESOURCESREADY", 31, 1 },
1252	{ "S_RCFOPCODEOUTSRDY", 30, 1 },
1253	{ "S_RCFDATAOUTSRDY", 29, 1 },
1254	{ "S_FLUSHINPUTMSG", 28, 1 },
1255	{ "S_RCFOPSRCOUT", 26, 2 },
1256	{ "S_C_MSG", 25, 1 },
1257	{ "S_E_MSG", 24, 1 },
1258	{ "S_RCFOPCODEOUT", 20, 4 },
1259	{ "S_EFFRCFOPCODEOUT", 16, 4 },
1260	{ "S_SEENRESOURCESREADY", 15, 1 },
1261	{ "S_DELDRDY", 14, 1 },
1262	{ "S_OPCODEWAITSFORDATA", 13, 1 },
1263	{ "S_CPLDRXSRDY", 12, 1 },
1264	{ "S_CPLDRXZEROPSRDY", 11, 1 },
1265	{ "S_EPLDRXZEROPSRDY", 10, 1 },
1266	{ "S_ERXERRORSRDY", 9, 1 },
1267	{ "S_EPLDRXSRDY", 8, 1 },
1268	{ "S_CRXBUSY", 7, 1 },
1269	{ "S_ERXBUSY", 6, 1 },
1270	{ "S_TIMERINSERTBUSY", 5, 1 },
1271	{ "S_WCFBUSY", 4, 1 },
1272	{ "S_CTXBUSY", 3, 1 },
1273	{ "S_CPCMDBUSY", 2, 1 },
1274	{ "S_ETXBUSY", 1, 1 },
1275	{ "S_EPCMDBUSY", 0, 1 },
1276	{ "TP_DBG_ENG_RES1", 0x67, 0 },
1277	{ "S_RXCPLSRDY", 31, 1 },
1278	{ "S_RXOPTSRDY", 30, 1 },
1279	{ "S_RXPLDLENSRDY", 29, 1 },
1280	{ "S_RXISSSRDY", 28, 1 },
1281	{ "S_CPLCMDIN", 20, 8 },
1282	{ "S_RCFPTIDSRDY", 19, 1 },
1283	{ "S_EPDUHDRSRDY", 18, 1 },
1284	{ "S_TUNNELPKTREG", 17, 1 },
1285	{ "S_TXPKTCSUMSRDY", 16, 1 },
1286	{ "S_TABLEACCESSLATENCY", 12, 4 },
1287	{ "S_MMGRDONE", 11, 1 },
1288	{ "S_SEENMMGRDONE", 10, 1 },
1289	{ "S_RXERRORSRDY", 9, 1 },
1290	{ "S_RCFOPTIONSTCPSRDY", 8, 1 },
1291	{ "S_ENGINESTATE", 6, 2 },
1292	{ "S_TABLEACCESINCREMENT", 5, 1 },
1293	{ "S_TABLEACCESCOMPLETE", 4, 1 },
1294	{ "S_RCFOPCODEOUTUSABLE", 3, 1 },
1295	{ "S_RCFDATAOUTUSABLE", 2, 1 },
1296	{ "TP_DBG_ENG_RES2", 0x68, 0 },
1297	{ "S_CPLCMDRAW", 24, 8 },
1298	{ "S_RXMACPORT", 20, 4 },
1299	{ "S_TXECHANNEL", 18, 2 },
1300	{ "S_RXECHANNEL", 16, 2 },
1301	{ "S_CDATAOUT", 15, 1 },
1302	{ "S_CREADPDU", 14, 1 },
1303	{ "S_EDATAOUT", 13, 1 },
1304	{ "S_EREADPDU", 12, 1 },
1305	{ "S_ETCPOPSRDY", 11, 1 },
1306	{ "S_CTCPOPSRDY", 10, 1 },
1307	{ "S_CPKTOUT", 9, 1 },
1308	{ "S_CMDBRSPSRDY", 8, 1 },
1309	{ "S_RXPSTRUCTSFULL", 6, 2 },
1310	{ "S_RXPAGEPOOLFULL", 4, 2 },
1311	{ "S_RCFREASONOUT", 0, 4 },
1312	{ "TP_DBG_CORE_PCMD", 0x69, 0 },
1313	{ "S_CPCMDEOPCNT", 30, 2 },
1314	{ "S_CPCMDLENSAVE", 16, 14 },
1315	{ "S_EPCMDEOPCNT", 14, 2 },
1316	{ "S_EPCMDLENSAVE", 0, 14 },
1317	{ "TP_DBG_SCHED_TX", 0x6A, 0 },
1318	{ "S_TXCHNXOFF", 28, 4 },
1319	{ "S_TXFIFOCNG", 24, 4 },
1320	{ "S_TXPCMDCNG", 20, 4 },
1321	{ "S_TXLPBKCNG", 16, 4 },
1322	{ "S_TXHDRCNG", 8, 8 },
1323	{ "S_TXMODXOFF", 0, 8 },
1324	{ "TP_DBG_SCHED_RX", 0x6B, 0 },
1325	{ "S_RXCHNXOFF", 28, 4 },
1326	{ "S_RXSGECNG", 24, 4 },
1327	{ "S_RXFIFOCNG", 20, 4 },
1328	{ "S_RXLPBKCNG", 16, 4 },
1329	{ "S_RXPCMDCNG", 14, 2 },
1330	{ "S_RESERVED0", 12, 2 },
1331	{ "S_RXHDRCNG", 8, 4 },
1332	{ "S_RESERVED0", 2, 6 },
1333	{ "S_RXMODXOFF", 0, 2 },
1334	{ "TP_DBG_ERROR_CNT", 0x6C, 0 },
1335	{ "TP_DBG_CORE_CPL", 0x6d, 0 },
1336	{ "CplCmdOut3", 24, 8 },
1337	{ "CplCmdOut2", 16, 8 },
1338	{ "CplCmdOut1", 8, 8 },
1339	{ "CplCmdOut0", 0, 8 },
1340	{ NULL }
1341};
1342
1343
1344static struct cudbg_reg_info t5_tp_pio_regs_60_to_6c[] = {
1345	{ "TP_DBG_CLEAR", 0x60, 0 },
1346	{ "TP_DBG_CORE_HDR0", 0x61, 0 },
1347	{ "S_RESERVED", 17, 15 },
1348	{ "S_E_TCP_OP_SRDY", 16, 1 },
1349	{ "S_E_PLD_TXZEROP_SRDY", 15, 1 },
1350	{ "S_E_PLD_RX_SRDY", 14, 1 },
1351	{ "S_E_RX_ERROR_SRDY", 13, 1 },
1352	{ "S_E_RX_ISS_SRDY", 12, 1 },
1353	{ "S_C_TCP_OP_SRDY", 11, 1 },
1354	{ "S_C_PLD_TXZEROP_SRDY", 10, 1 },
1355	{ "S_C_PLD_RX_SRDY", 9, 1 },
1356	{ "S_C_RX_ERROR_SRDY", 8, 1 },
1357	{ "S_C_RX_ISS_SRDY", 7, 1 },
1358	{ "S_E_CPL5_TXVALID", 6, 1 },
1359	{ "S_E_ETH_TXVALID", 5, 1 },
1360	{ "S_E_IP_TXVALID", 4, 1 },
1361	{ "S_E_TCP_TXVALID", 3, 1 },
1362	{ "S_C_CPL5_RXVALID", 2, 1 },
1363	{ "S_C_CPL5_TXVALID", 1, 1 },
1364	{ "S_E_TCP_OPT_RXVALID", 0, 1 },
1365	{ "TP_DBG_CORE_HDR1", 0x62, 0 },
1366	{ "S_RESERVED", 7, 25 },
1367	{ "S_E_CPL5_TXFULL", 6, 1 },
1368	{ "S_E_ETH_TXFULL", 5, 1 },
1369	{ "S_E_IP_TXFULL", 4, 1 },
1370	{ "S_E_TCP_TXFULL", 3, 1 },
1371	{ "S_C_CPL5_RXFULL", 2, 1 },
1372	{ "S_C_CPL5_TXFULL", 1, 1 },
1373	{ "S_E_TCP_OPT_RXFULL", 0, 1 },
1374	{ "TP_DBG_CORE_FATAL", 0x63, 0 },
1375	{ "S_EMSGFATAL", 31, 1 },
1376	{ "S_CMSGFATAL", 30, 1 },
1377	{ "S_PAWSFATAL", 29, 1 },
1378	{ "S_SRAMFATAL", 28, 1 },
1379	{ "S_CPCMDCONG", 24, 4 },
1380	{ "S_EPCMDCONG", 22, 2 },
1381	{ "S_CPCMDLENFATAL", 21, 1 },
1382	{ "S_EPCMDLENFATAL", 20, 1 },
1383	{ "S_CPCMDVALID", 16, 4 },
1384	{ "S_CPCMDAFULL", 12, 4 },
1385	{ "S_EPCMDVALID", 10, 2 },
1386	{ "S_EPCMDAFULL", 8, 2 },
1387	{ "S_CPCMDEOIFATAL", 7, 1 },
1388	{ "S_CPCMDTTLFATAL", 6, 1 },
1389	{ "S_CDATACHNFATAL", 5, 1 },
1390	{ "S_RESERVED", 4, 1 },
1391	{ "S_CNONZEROPPOPCNT", 2, 2 },
1392	{ "S_CPCMDEOICNT", 0, 2 },
1393	{ "TP_DBG_CORE_OUT", 0x64, 0 },
1394	{ "S_CRXBUSYOUT", 31, 1 },
1395	{ "S_CTXBUSYOUT", 30, 1 },
1396	{ "S_CRDCPLPKT", 29, 1 },
1397	{ "S_CRDTCPPKT", 28, 1 },
1398	{ "S_CNEWMSG", 27, 1 },
1399	{ "S_CCPLENC", 26, 1 },
1400	{ "S_CWRCPLPKT", 25, 1 },
1401	{ "S_CWRETHPKT", 24, 1 },
1402	{ "S_CWRIPPKT", 23, 1 },
1403	{ "S_CWRTCPPKT", 22, 1 },
1404	{ "S_CWRZEROP", 21, 1 },
1405	{ "S_CCPLTXFULL", 20, 1 },
1406	{ "S_CETHTXFULL", 19, 1 },
1407	{ "S_CIPTXFULL", 18, 1 },
1408	{ "S_CTCPTXFULL", 17, 1 },
1409	{ "S_CPLDTXZEROPDRDY", 16, 1 },
1410	{ "S_RESERVED1", 10, 1 },
1411	{ "S_EWRCPLPKT", 9, 1 },
1412	{ "S_EWRETHPKT", 8, 1 },
1413	{ "S_EWRIPPKT", 7, 1 },
1414	{ "S_EWRTCPPKT", 6, 1 },
1415	{ "S_EWRZEROP", 5, 1 },
1416	{ "S_ECPLTXFULL", 4, 1 },
1417	{ "S_EETHTXFULL", 3, 1 },
1418	{ "S_EIPTXFULL", 2, 1 },
1419	{ "S_ETCPTXFULL", 1, 1 },
1420	{ "S_EPLDTXZEROPDRDY", 0, 1 },
1421	{ "TP_DBG_CORE_TID", 0x65, 0 },
1422	{ "S_LINENUMBER", 24, 7 },
1423	{ "S_SPURIOUSMSG", 23, 1 },
1424	{ "S_SRC", 21, 2 },
1425	{ "S_SYNLEARNED", 20, 1 },
1426	{ "S_TIDVALUE", 0, 20 },
1427	{ "TP_DBG_ENG_RES0", 0x66, 0 },
1428	{ "S_RESOURCESREADY", 31, 1 },
1429	{ "S_RCFOPCODEOUTSRDY", 30, 1 },
1430	{ "S_RCFDATAOUTSRDY", 29, 1 },
1431	{ "S_FLUSHINPUTMSG", 28, 1 },
1432	{ "S_RCFOPSRCOUT", 26, 2 },
1433	{ "S_C_MSG", 25, 1 },
1434	{ "S_E_MSG", 24, 1 },
1435	{ "S_RCFOPCODEOUT", 20, 4 },
1436	{ "S_EFFRCFOPCODEOUT", 16, 4 },
1437	{ "S_SEENRESOURCESREADY", 15, 1 },
1438	{ "S_DELDRDY", 14, 1 },
1439	{ "S_OPCODEWAITSFORDATA", 13, 1 },
1440	{ "S_CPLDRXSRDY", 12, 1 },
1441	{ "S_CPLDRXZEROPSRDY", 11, 1 },
1442	{ "S_EPLDRXZEROPSRDY", 10, 1 },
1443	{ "S_ERXERRORSRDY", 9, 1 },
1444	{ "S_EPLDRXSRDY", 8, 1 },
1445	{ "S_CRXBUSY", 7, 1 },
1446	{ "S_ERXBUSY", 6, 1 },
1447	{ "S_TIMERINSERTBUSY", 5, 1 },
1448	{ "S_WCFBUSY", 4, 1 },
1449	{ "S_CTXBUSY", 3, 1 },
1450	{ "S_CPCMDBUSY", 2, 1 },
1451	{ "S_ETXBUSY", 1, 1 },
1452	{ "S_EPCMDBUSY", 0, 1 },
1453	{ "TP_DBG_ENG_RES1", 0x67, 0 },
1454	{ "S_RXCPLSRDY", 31, 1 },
1455	{ "S_RXOPTSRDY", 30, 1 },
1456	{ "S_RXPLDLENSRDY", 29, 1 },
1457	{ "S_RXNOTBUSY", 28, 1 },
1458	{ "S_CPLCMDIN", 20, 8 },
1459	{ "S_RCFPTIDSRDY", 19, 1 },
1460	{ "S_EPDUHDRSRDY", 18, 1 },
1461	{ "S_TUNNELPKTREG", 17, 1 },
1462	{ "S_TXPKTCSUMSRDY", 16, 1 },
1463	{ "S_TABLEACCESSLATENCY", 12, 4 },
1464	{ "S_MMGRDONE", 11, 1 },
1465	{ "S_SEENMMGRDONE", 10, 1 },
1466	{ "S_RXERRORSRDY", 9, 1 },
1467	{ "S_RCFOPTIONSTCPSRDY", 8, 1 },
1468	{ "S_ENGINESTATE", 6, 2 },
1469	{ "S_TABLEACCESINCREMENT", 5, 1 },
1470	{ "S_TABLEACCESCOMPLETE", 4, 1 },
1471	{ "S_RCFOPCODEOUTUSABLE", 3, 1 },
1472	{ "S_RCFDATAOUTUSABLE", 2, 1 },
1473	{ "S_RCFDATAWAITAFTERRD", 1, 1 },
1474	{ "S_RCFDATACMRDY", 0, 1 },
1475	{ "TP_DBG_ENG_RES2", 0x68, 0 },
1476	{ "S_CPLCMDRAW", 24, 8 },
1477	{ "S_RXMACPORT", 20, 4 },
1478	{ "S_TXECHANNEL", 18, 2 },
1479	{ "S_RXECHANNEL", 16, 2 },
1480	{ "S_CDATAOUT", 15, 1 },
1481	{ "S_CREADPDU", 14, 1 },
1482	{ "S_EDATAOUT", 13, 1 },
1483	{ "S_EREADPDU", 12, 1 },
1484	{ "S_ETCPOPSRDY", 11, 1 },
1485	{ "S_CTCPOPSRDY", 10, 1 },
1486	{ "S_CPKTOUT", 9, 1 },
1487	{ "S_CMDBRSPSRDY", 8, 1 },
1488	{ "S_RXPSTRUCTSFULL", 6, 2 },
1489	{ "S_RXPAGEPOOLFULL", 4, 2 },
1490	{ "S_RCFREASONOUT", 0, 4 },
1491	{ "TP_DBG_CORE_PCMD", 0x69, 0 },
1492	{ "S_CPCMDEOPCNT", 30, 2 },
1493	{ "S_CPCMDLENSAVE", 16, 14 },
1494	{ "S_EPCMDEOPCNT", 14, 2 },
1495	{ "S_EPCMDLENSAVE", 0, 14 },
1496	{ "TP_DBG_SCHED_TX", 0x6A, 0 },
1497	{ "S_TXCHNXOFF", 28, 4 },
1498	{ "S_TXFIFOCNG", 24, 4 },
1499	{ "S_TXPCMDCNG", 20, 4 },
1500	{ "S_TXLPBKCNG", 16, 4 },
1501	{ "S_TXHDRCNG", 8, 8 },
1502	{ "S_TXMODXOFF", 0, 8 },
1503	{ "TP_DBG_SCHED_RX", 0x6B, 0 },
1504	{ "S_RXCHNXOFF", 28, 4 },
1505	{ "S_RXSGECNG", 24, 4 },
1506	{ "S_RXFIFOCNG", 20, 4 },
1507	{ "S_RXLPBKCNG", 16, 4 },
1508	{ "S_RXPCMDCNG", 14, 2 },
1509	{ "S_RESERVED0", 12, 2 },
1510	{ "S_RXHDRCNG", 8, 4 },
1511	{ "S_RESERVED0", 2, 6 },
1512	{ "S_RXMODXOFF", 0, 2 },
1513	{ "TP_DBG_ERROR_CNT", 0x6C, 0 },
1514	{ NULL }
1515};
1516
1517static struct cudbg_reg_info t6_tp_pio_regs_6f[] = {
1518	{ "TP_MIB_DEBUG", 0x6F, 0 },
1519	{ "S_SRC3", 31, 1 },
1520	{ "S_LINENUM3", 24, 7 },
1521	{ "S_SRC2", 23, 1 },
1522	{ "S_LINENUM2", 16, 7 },
1523	{ "S_SRC1", 15, 1 },
1524	{ "S_LINENUM1", 8, 7 },
1525	{ "S_SRC0", 7, 1 },
1526	{ "S_LINENUM0", 0, 7 },
1527	{ NULL }
1528};
1529
1530static struct cudbg_reg_info t6_tp_pio_regs_130_to_141[] = {
1531	{ "TP_DBG_ESIDE_PKT0", 0x130, 0 },
1532	{ "S_ETXSOPCNT", 28, 4 },
1533	{ "S_ETXEOPCNT", 24, 4 },
1534	{ "S_ETXPLDSOPCNT", 20, 4 },
1535	{ "S_ETXPLDEOPCNT", 16, 4 },
1536	{ "S_ERXSOPCNT", 12, 4 },
1537	{ "S_ERXEOPCNT", 8, 4 },
1538	{ "S_ERXPLDSOPCNT", 4, 4 },
1539	{ "S_ERXPLDEOPCNT", 0, 4 },
1540	{ "TP_DBG_ESIDE_PKT1", 0x131, 0 },
1541	{ "S_ETXSOPCNT", 28, 4 },
1542	{ "S_ETXEOPCNT", 24, 4 },
1543	{ "S_ETXPLDSOPCNT", 20, 4 },
1544	{ "S_ETXPLDEOPCNT", 16, 4 },
1545	{ "S_ERXSOPCNT", 12, 4 },
1546	{ "S_ERXEOPCNT", 8, 4 },
1547	{ "S_ERXPLDSOPCNT", 4, 4 },
1548	{ "S_ERXPLDEOPCNT", 0, 4 },
1549	{ "TP_DBG_ESIDE_PKT2", 0x132, 0 },
1550	{ "S_ETXSOPCNT", 28, 4 },
1551	{ "S_ETXEOPCNT", 24, 4 },
1552	{ "S_ETXPLDSOPCNT", 20, 4 },
1553	{ "S_ETXPLDEOPCNT", 16, 4 },
1554	{ "S_ERXSOPCNT", 12, 4 },
1555	{ "S_ERXEOPCNT", 8, 4 },
1556	{ "S_ERXPLDSOPCNT", 4, 4 },
1557	{ "S_ERXPLDEOPCNT", 0, 4 },
1558	{ "TP_DBG_ESIDE_PKT3", 0x133, 0 },
1559	{ "S_ETXSOPCNT", 28, 4 },
1560	{ "S_ETXEOPCNT", 24, 4 },
1561	{ "S_ETXPLDSOPCNT", 20, 4 },
1562	{ "S_ETXPLDEOPCNT", 16, 4 },
1563	{ "S_ERXSOPCNT", 12, 4 },
1564	{ "S_ERXEOPCNT", 8, 4 },
1565	{ "S_ERXPLDSOPCNT", 4, 4 },
1566	{ "S_ERXPLDEOPCNT", 0, 4 },
1567	{ "TP_DBG_ESIDE_FIFO0", 0x134, 0 },
1568	{ "S_PLDRXCSUMVALID1", 31, 1 },
1569	{ "S_PLDRXZEROPSRDY1", 30, 1 },
1570	{ "S_PLDRXVALID1", 29, 1 },
1571	{ "S_TCPRXVALID1", 28, 1 },
1572	{ "S_IPRXVALID1", 27, 1 },
1573	{ "S_ETHRXVALID1", 26, 1 },
1574	{ "S_CPLRXVALID1", 25, 1 },
1575	{ "S_FSTATIC1", 24, 1 },
1576	{ "S_ERRORSRDY1", 23, 1 },
1577	{ "S_PLDTXSRDY1", 22, 1 },
1578	{ "S_DBVLD1", 21, 1 },
1579	{ "S_PLDTXVALID1", 20, 1 },
1580	{ "S_ETXVALID1", 19, 1 },
1581	{ "S_ETXFULL1", 18, 1 },
1582	{ "S_ERXVALID1", 17, 1 },
1583	{ "S_ERXFULL1", 16, 1 },
1584	{ "S_PLDRXCSUMVALID0", 15, 1 },
1585	{ "S_PLDRXZEROPSRDY0", 14,  1},
1586	{ "S_PLDRXVALID0", 13, 1 },
1587	{ "S_TCPRXVALID0", 12, 1 },
1588	{ "S_IPRXVALID0", 11, 1 },
1589	{ "S_ETHRXVALID0", 10, 1 },
1590	{ "S_CPLRXVALID0", 9, 1 },
1591	{ "S_FSTATIC0", 8, 1 },
1592	{ "S_ERRORSRDY0", 7, 1 },
1593	{ "S_PLDTXSRDY0", 6, 1 },
1594	{ "S_DBVLD0", 5, 1 },
1595	{ "S_PLDTXVALID0", 4, 1 },
1596	{ "S_ETXVALID0", 3, 1 },
1597	{ "S_ETXFULL0", 2, 1 },
1598	{ "S_ERXVALID0", 1, 1 },
1599	{ "S_ERXFULL0", 0, 1 },
1600	{ "TP_DBG_ESIDE_FIFO1", 0x135, 0 },
1601	{ "S_PLDRXCSUMVALID3", 31, 1 },
1602	{ "S_PLDRXZEROPSRDY3", 30, 1 },
1603	{ "S_PLDRXVALID3", 29, 1 },
1604	{ "S_TCPRXVALID3", 28, 1 },
1605	{ "S_IPRXVALID3", 27, 1 },
1606	{ "S_ETHRXVALID3", 26, 1 },
1607	{ "S_CPLRXVALID3", 25, 1 },
1608	{ "S_FSTATIC3", 24, 1 },
1609	{ "S_ERRORSRDY3", 23, 1 },
1610	{ "S_PLDTXSRDY3", 22, 1 },
1611	{ "S_DBVLD3", 21, 1 },
1612	{ "S_PLDTXVALID3", 20, 1 },
1613	{ "S_ETXVALID3", 19, 1 },
1614	{ "S_ETXFULL3", 18, 1 },
1615	{ "S_ERXVALID3", 17, 1 },
1616	{ "S_ERXFULL3", 16, 1 },
1617	{ "S_PLDRXCSUMVALID2", 15, 1 },
1618	{ "S_PLDRXZEROPSRDY2", 14,  1},
1619	{ "S_PLDRXVALID2", 13, 1 },
1620	{ "S_TCPRXVALID2", 12, 1 },
1621	{ "S_IPRXVALID2", 11, 1 },
1622	{ "S_ETHRXVALID2", 10, 1 },
1623	{ "S_CPLRXVALID2", 9, 1 },
1624	{ "S_FSTATIC2", 8, 1 },
1625	{ "S_ERRORSRDY2", 7, 1 },
1626	{ "S_PLDTXSRDY2", 6, 1 },
1627	{ "S_DBVLD2", 5, 1 },
1628	{ "S_PLDTXVALID2", 4, 1 },
1629	{ "S_ETXVALID2", 3, 1 },
1630	{ "S_ETXFULL2", 2, 1 },
1631	{ "S_ERXVALID2", 1, 1 },
1632	{ "S_ERXFULL2", 0, 1 },
1633	{ "TP_DBG_ESIDE_DISP0", 0x136, 0 },
1634	{ "S_RESRDY", 31, 1 },
1635	{ "S_STATE", 28, 3 },
1636	{ "S_FIFOCPL5RXVALID", 27, 1 },
1637	{ "S_FIFOETHRXVALID", 26, 1 },
1638	{ "S_FIFOETHRXSOCP", 25, 1 },
1639	{ "S_FIFOPLDRXZEROP", 24, 1 },
1640	{ "S_PLDRXVALID", 23, 1 },
1641	{ "S_FIFOPLDRXZEROP_SRDY", 22, 1 },
1642	{ "S_FIFOIPRXVALID", 21, 1 },
1643	{ "S_FIFOTCPRXVALID", 20, 1 },
1644	{ "S_PLDRXCSUMVALID", 19, 1 },
1645	{ "S_FIFOIPCSUMSRDY", 18, 1 },
1646	{ "S_FIFOIPPSEUDOCSUMSRDY", 17, 1 },
1647	{ "S_FIFOTCPCSUMSRDY", 16, 1 },
1648	{ "S_FIFOGRERXVALID", 15, 1 },
1649	{ "S_FIFOGRERXREADY", 14, 1 },
1650	{ "S_FIFOGRERXSOCP", 13, 1 },
1651	{ "S_ESTATIC4", 12, 1 },
1652	{ "S_FIFOCPLSOCPCNT", 10, 2 },
1653	{ "S_FIFOETHSOCPCNT", 8, 2 },
1654	{ "S_FIFOIPSOCPCNT", 6,  2},
1655	{ "S_FIFOTCPSOCPCNT", 4, 2 },
1656	{ "S_PLD_RXZEROP_CNT", 2, 2 },
1657	{ "S_ESTATIC6", 1, 1 },
1658	{ "S_TXFULL", 0, 1 },
1659	{ "TP_DBG_ESIDE_DISP1", 0x137, 0 },
1660	{ "S_RESRDY", 31, 1 },
1661	{ "S_STATE", 28, 3 },
1662	{ "S_FIFOCPL5RXVALID", 27, 1 },
1663	{ "S_FIFOETHRXVALID", 26, 1 },
1664	{ "S_FIFOETHRXSOCP", 25, 1 },
1665	{ "S_FIFOPLDRXZEROP", 24, 1 },
1666	{ "S_PLDRXVALID", 23, 1 },
1667	{ "S_FIFOPLDRXZEROP_SRDY", 22, 1 },
1668	{ "S_FIFOIPRXVALID", 21, 1 },
1669	{ "S_FIFOTCPRXVALID", 20, 1 },
1670	{ "S_PLDRXCSUMVALID", 19, 1 },
1671	{ "S_FIFOIPCSUMSRDY", 18, 1 },
1672	{ "S_FIFOIPPSEUDOCSUMSRDY", 17, 1 },
1673	{ "S_FIFOTCPCSUMSRDY", 16, 1 },
1674	{ "S_FIFOGRERXVALID", 15, 1 },
1675	{ "S_FIFOGRERXREADY", 14, 1 },
1676	{ "S_FIFOGRERXSOCP", 13, 1 },
1677	{ "S_ESTATIC4", 12, 1 },
1678	{ "S_FIFOCPLSOCPCNT", 10, 2 },
1679	{ "S_FIFOETHSOCPCNT", 8, 2 },
1680	{ "S_FIFOIPSOCPCNT", 6,  2},
1681	{ "S_FIFOTCPSOCPCNT", 4, 2 },
1682	{ "S_PLD_RXZEROP_CNT", 2, 2 },
1683	{ "S_ESTATIC6", 1, 1 },
1684	{ "S_TXFULL", 0, 1 },
1685	{ "TP_MAC_MATCH_MAP0", 0x138, 0 },
1686	{ "S_MAPVALUEWR", 16, 8 },
1687	{ "S_RESERVED", 11, 5 },
1688	{ "S_MAPINDEX", 2, 9 },
1689	{ "S_MAPREAD", 1, 1 },
1690	{ "S_MAPWRITE", 0, 1 },
1691	{ "TP_MAC_MATCH_MAP1", 0x139, 0 },
1692	{ "S_RESERVED", 9, 15 },
1693	{ "S_MAPVALUERD", 0, 9 },
1694	{ "TP_DBG_ESIDE_DISP2", 0x13A, 0 },
1695	{ "S_RESRDY", 31, 1 },
1696	{ "S_STATE", 28, 3 },
1697	{ "S_FIFOCPL5RXVALID", 27, 1 },
1698	{ "S_FIFOETHRXVALID", 26, 1 },
1699	{ "S_FIFOETHRXSOCP", 25, 1 },
1700	{ "S_FIFOPLDRXZEROP", 24, 1 },
1701	{ "S_PLDRXVALID", 23, 1 },
1702	{ "S_FIFOPLDRXZEROP_SRDY", 22, 1 },
1703	{ "S_FIFOIPRXVALID", 21, 1 },
1704	{ "S_FIFOTCPRXVALID", 20, 1 },
1705	{ "S_PLDRXCSUMVALID", 19, 1 },
1706	{ "S_FIFOIPCSUMSRDY", 18, 1 },
1707	{ "S_FIFOIPPSEUDOCSUMSRDY", 17, 1 },
1708	{ "S_FIFOTCPCSUMSRDY", 16, 1 },
1709	{ "S_FIFOGRERXVALID", 15, 1 },
1710	{ "S_FIFOGRERXREADY", 14, 1 },
1711	{ "S_FIFOGRERXSOCP", 13, 1 },
1712	{ "S_ESTATIC4", 12, 1 },
1713	{ "S_FIFOCPLSOCPCNT", 10, 2 },
1714	{ "S_FIFOETHSOCPCNT", 8, 2 },
1715	{ "S_FIFOIPSOCPCNT", 6,  2},
1716	{ "S_FIFOTCPSOCPCNT", 4, 2 },
1717	{ "S_PLD_RXZEROP_CNT", 2, 2 },
1718	{ "S_ESTATIC6", 1, 1 },
1719	{ "S_TXFULL", 0, 1 },
1720	{ "TP_DBG_ESIDE_DISP3", 0x13B, 0 },
1721	{ "S_RESRDY", 31, 1 },
1722	{ "S_STATE", 28, 3 },
1723	{ "S_FIFOCPL5RXVALID", 27, 1 },
1724	{ "S_FIFOETHRXVALID", 26, 1 },
1725	{ "S_FIFOETHRXSOCP", 25, 1 },
1726	{ "S_FIFOPLDRXZEROP", 24, 1 },
1727	{ "S_PLDRXVALID", 23, 1 },
1728	{ "S_FIFOPLDRXZEROP_SRDY", 22, 1 },
1729	{ "S_FIFOIPRXVALID", 21, 1 },
1730	{ "S_FIFOTCPRXVALID", 20, 1 },
1731	{ "S_PLDRXCSUMVALID", 19, 1 },
1732	{ "S_FIFOIPCSUMSRDY", 18, 1 },
1733	{ "S_FIFOIPPSEUDOCSUMSRDY", 17, 1 },
1734	{ "S_FIFOTCPCSUMSRDY", 16, 1 },
1735	{ "S_FIFOGRERXVALID", 15, 1 },
1736	{ "S_FIFOGRERXREADY", 14, 1 },
1737	{ "S_FIFOGRERXSOCP", 13, 1 },
1738	{ "S_ESTATIC4", 12, 1 },
1739	{ "S_FIFOCPLSOCPCNT", 10, 2 },
1740	{ "S_FIFOETHSOCPCNT", 8, 2 },
1741	{ "S_FIFOIPSOCPCNT", 6,  2},
1742	{ "S_FIFOTCPSOCPCNT", 4, 2 },
1743	{ "S_PLD_RXZEROP_CNT", 2, 2 },
1744	{ "S_ESTATIC6", 1, 1 },
1745	{ "S_TXFULL", 0, 1 },
1746	{ "TP_DBG_ESIDE_HDR0", 0x13C, 0 },
1747	{ "S_TCPSOPCNT", 28, 4 },
1748	{ "S_TCPEOPCNT", 24, 4 },
1749	{ "S_IPSOPCNT", 20, 4 },
1750	{ "S_IPEOPCNT", 16, 4 },
1751	{ "S_ETHSOPCNT", 12, 4 },
1752	{ "S_ETHEOPCNT", 8, 4 },
1753	{ "S_CPLSOPCNT", 4, 4 },
1754	{ "S_CPLEOPCNT", 0, 4 },
1755	{ "TP_DBG_ESIDE_HDR1", 0x13D, 0 },
1756	{ "S_TCPSOPCNT", 28, 4 },
1757	{ "S_TCPEOPCNT", 24, 4 },
1758	{ "S_IPSOPCNT", 20, 4 },
1759	{ "S_IPEOPCNT", 16, 4 },
1760	{ "S_ETHSOPCNT", 12, 4 },
1761	{ "S_ETHEOPCNT", 8, 4 },
1762	{ "S_CPLSOPCNT", 4, 4 },
1763	{ "S_CPLEOPCNT", 0, 4 },
1764	{ "TP_DBG_ESIDE_HDR2", 0x13E, 0 },
1765	{ "S_TCPSOPCNT", 28, 4 },
1766	{ "S_TCPEOPCNT", 24, 4 },
1767	{ "S_IPSOPCNT", 20, 4 },
1768	{ "S_IPEOPCNT", 16, 4 },
1769	{ "S_ETHSOPCNT", 12, 4 },
1770	{ "S_ETHEOPCNT", 8, 4 },
1771	{ "S_CPLSOPCNT", 4, 4 },
1772	{ "S_CPLEOPCNT", 0, 4 },
1773	{ "TP_DBG_ESIDE_HDR3", 0x13F, 0 },
1774	{ "S_TCPSOPCNT", 28, 4 },
1775	{ "S_TCPEOPCNT", 24, 4 },
1776	{ "S_IPSOPCNT", 20, 4 },
1777	{ "S_IPEOPCNT", 16, 4 },
1778	{ "S_ETHSOPCNT", 12, 4 },
1779	{ "S_ETHEOPCNT", 8, 4 },
1780	{ "S_CPLSOPCNT", 4, 4 },
1781	{ "S_CPLEOPCNT", 0, 4 },
1782	{ "TP_VLAN_PRI_MAP", 0x140, 0 },
1783	{ "S_FILTERMODE", 15, 1 },
1784	{ "S_FCOEMASK", 14, 1 },
1785	{ "S_SRVRSRAM", 13, 1 },
1786	{ "S_FRAGMENTATION", 9, 1 },
1787	{ "S_MPSHITTYPE", 8, 1 },
1788	{ "S_MACMATCH", 7, 1 },
1789	{ "S_ETHERTYPE", 6, 1 },
1790	{ "S_PROTOCOL", 5, 1 },
1791	{ "S_TOS", 4,  1},
1792	{ "S_VLAN", 3, 1 },
1793	{ "S_VNIC_ID", 2, 1 },
1794	{ "S_PORT", 1, 1 },
1795	{ "S_FCOE", 0, 1 },
1796	{ "TP_INGRESS_CONFIG", 0x141, 0 },
1797	{ "S_OPAQUE_TYPE", 16, 16 },
1798	{ "S_OPAQUE_RM", 15, 1 },
1799	{ "S_OPAQUE_HDR_SIZE", 14,  1},
1800	{ "S_OPAQUE_RM_MAC_IN_MAC", 13, 1 },
1801	{ "S_FRAG_LEN_MOD8_COMPAT", 12, 1 },
1802	{ "S_VNIC", 11, 1 },
1803	{ "S_CSUM_HAS_PSEUDO_HDR", 10, 1 },
1804	{ "S_RM_OVLAN", 9, 1 },
1805	{ "S_LOOKUPEVERYPKT", 8, 1 },
1806	{ "S_IPV6_EXT_HDR_SKIP", 0, 8 },
1807	{ NULL }
1808};
1809
1810static struct cudbg_reg_info t6_tp_pio_regs_145_to_157[] = {
1811	{ "TP_INGRESS_CONFIG2", 0x145, 0 },
1812	{ "S_IPV6_UDP_CSUM_COMPAT", 31, 1 },
1813	{ "S_VNTAGPLDENABLE", 30, 1 },
1814	{ "S_TCP_PLD_FILTER_OFFSET", 20,  10},
1815	{ "S_UDP_PLD_FILTER_OFFSET", 10, 10 },
1816	{ "S_TNL_PLD_FILTER_OFFSET", 0, 10 },
1817	{ "TP_EHDR_CONFIG_LO", 0x146, 0 },
1818	{ "S_CPLLIMIT", 24, 8 },
1819	{ "S_ETHLIMIT", 16, 8 },
1820	{ "S_IPLIMIT", 8, 8 },
1821	{ "S_TCPLIMIT", 0, 8 },
1822	{ "TP_EHDR_CONFIG_HI", 0x147, 0 },
1823	{ "S_CPLLIMIT", 24, 8 },
1824	{ "S_ETHLIMIT", 16, 8 },
1825	{ "S_IPLIMIT", 8, 8 },
1826	{ "S_TCPLIMIT", 0, 8 },
1827	{ "TP_DBG_ESIDE_INT", 0x148, 0 },
1828	{ "S_ERXSOP2X", 28, 4 },
1829	{ "S_ERXEOP2X", 24, 4 },
1830	{ "S_ERXVALID2X", 20, 4 },
1831	{ "S_ERXAFULL2X", 16, 4 },
1832	{ "S_PLD2XTXVALID", 12, 4 },
1833	{ "S_PLD2XTXAFULL", 8, 4 },
1834	{ "S_ERRORSRDY", 7, 1 },
1835	{ "S_ERRORDRDY", 6, 1 },
1836	{ "S_TCPOPSRDY", 5, 1 },
1837	{ "S_TCPOPDRDY", 4, 1 },
1838	{ "S_PLDTXSRDY", 3, 1 },
1839	{ "S_PLDTXDRDY", 2, 1 },
1840	{ "S_TCPOPTTXVALID", 1, 1 },
1841	{ "S_TCPOPTTXFULL", 0, 1 },
1842	{ "TP_DBG_ESIDE_DEMUX", 0x149, 0 },
1843	{ "S_EALLDONE", 28, 4 },
1844	{ "S_EFIFOPLDDONE", 24, 4 },
1845	{ "S_EDBDONE", 20, 4 },
1846	{ "S_EISSFIFODONE", 16, 4 },
1847	{ "S_EACKERRFIFODONE", 12, 4 },
1848	{ "S_EFIFOERRORDONE", 8, 4 },
1849	{ "S_ERXPKTATTRFIFOFDONE", 4, 4 },
1850	{ "S_ETCPOPDONE", 0, 4 },
1851	{ "TP_DBG_ESIDE_IN0", 0x14A, 0 },
1852	{ "S_RXVALID", 31, 1 },
1853	{ "S_RXFULL", 30, 1 },
1854	{ "S_RXSOCP", 29, 1 },
1855	{ "S_RXEOP", 28, 1 },
1856	{ "S_RXVALID_I", 27, 1 },
1857	{ "S_RXFULL_I", 26, 1 },
1858	{ "S_RXRUNT", 25, 1 },
1859	{ "S_RXRUNTPARSER", 24, 1 },
1860	{ "S_RXVALID_I2", 23, 1 },
1861	{ "S_RXFULL_I2", 22, 1 },
1862	{ "S_RXSOCP_I2", 21, 1 },
1863	{ "S_RXEOP_I2", 20, 1 },
1864	{ "S_CT_MPA_TXVALID_FIFO", 19, 1 },
1865	{ "S_CT_MPA_TXFULL_FIFO", 18, 1 },
1866	{ "S_CT_MPA_TXVALID", 17, 1 },
1867	{ "S_CT_MPA_TXFULL", 16, 1 },
1868	{ "S_RXVALID_BUF", 15, 1 },
1869	{ "S_RXFULL_BUF", 14, 1 },
1870	{ "S_PLD_TXVALID", 13, 1 },
1871	{ "S_PLD_TXFULL", 12, 1 },
1872	{ "S_ISS_FIFO_SRDY", 11, 1 },
1873	{ "S_ISS_FIFO_DRDY", 10, 1 },
1874	{ "S_CT_TCP_OP_ISS_SRDY", 9, 1 },
1875	{ "S_CT_TCP_OP_ISS_DRDY", 8, 1 },
1876	{ "S_P2CSUMERROR_SRDY", 7, 1 },
1877	{ "S_P2CSUMERROR_DRDY", 6, 1 },
1878	{ "S_ERROR_SRDY", 5, 1 },
1879	{ "S_ERROR_DRDY", 4, 1 },
1880	{ "S_PLD_SRDY", 3, 1 },
1881	{ "S_PLD_DRDY", 2, 1 },
1882	{ "S_RX_PKT_ATTR_SRDY", 1, 1 },
1883	{ "S_RX_PKT_ATTR_DRDY", 0, 1 },
1884	{ "TP_DBG_ESIDE_IN1", 0x14B, 0 },
1885	{ "S_RXVALID", 31, 1 },
1886	{ "S_RXFULL", 30, 1 },
1887	{ "S_RXSOCP", 29, 1 },
1888	{ "S_RXEOP", 28, 1 },
1889	{ "S_RXVALID_I", 27, 1 },
1890	{ "S_RXFULL_I", 26, 1 },
1891	{ "S_RXRUNT", 25, 1 },
1892	{ "S_RXRUNTPARSER", 24, 1 },
1893	{ "S_RXVALID_I2", 23, 1 },
1894	{ "S_RXFULL_I2", 22, 1 },
1895	{ "S_RXSOCP_I2", 21, 1 },
1896	{ "S_RXEOP_I2", 20, 1 },
1897	{ "S_CT_MPA_TXVALID_FIFO", 19, 1 },
1898	{ "S_CT_MPA_TXFULL_FIFO", 18, 1 },
1899	{ "S_CT_MPA_TXVALID", 17, 1 },
1900	{ "S_CT_MPA_TXFULL", 16, 1 },
1901	{ "S_RXVALID_BUF", 15, 1 },
1902	{ "S_RXFULL_BUF", 14, 1 },
1903	{ "S_PLD_TXVALID", 13, 1 },
1904	{ "S_PLD_TXFULL", 12, 1 },
1905	{ "S_ISS_FIFO_SRDY", 11, 1 },
1906	{ "S_ISS_FIFO_DRDY", 10, 1 },
1907	{ "S_CT_TCP_OP_ISS_SRDY", 9, 1 },
1908	{ "S_CT_TCP_OP_ISS_DRDY", 8, 1 },
1909	{ "S_P2CSUMERROR_SRDY", 7, 1 },
1910	{ "S_P2CSUMERROR_DRDY", 6, 1 },
1911	{ "S_ERROR_SRDY", 5, 1 },
1912	{ "S_ERROR_DRDY", 4, 1 },
1913	{ "S_PLD_SRDY", 3, 1 },
1914	{ "S_PLD_DRDY", 2, 1 },
1915	{ "S_RX_PKT_ATTR_SRDY", 1, 1 },
1916	{ "S_RX_PKT_ATTR_DRDY", 0, 1 },
1917	{ "TP_DBG_ESIDE_IN2", 0x14C, 0 },
1918	{ "S_RXVALID", 31, 1 },
1919	{ "S_RXFULL", 30, 1 },
1920	{ "S_RXSOCP", 29, 1 },
1921	{ "S_RXEOP", 28, 1 },
1922	{ "S_RXVALID_I", 27, 1 },
1923	{ "S_RXFULL_I", 26, 1 },
1924	{ "S_RXRUNT", 25, 1 },
1925	{ "S_RXRUNTPARSER", 24, 1 },
1926	{ "S_RXVALID_I2", 23, 1 },
1927	{ "S_RXFULL_I2", 22, 1 },
1928	{ "S_RXSOCP_I2", 21, 1 },
1929	{ "S_RXEOP_I2", 20, 1 },
1930	{ "S_CT_MPA_TXVALID_FIFO", 19, 1 },
1931	{ "S_CT_MPA_TXFULL_FIFO", 18, 1 },
1932	{ "S_CT_MPA_TXVALID", 17, 1 },
1933	{ "S_CT_MPA_TXFULL", 16, 1 },
1934	{ "S_RXVALID_BUF", 15, 1 },
1935	{ "S_RXFULL_BUF", 14, 1 },
1936	{ "S_PLD_TXVALID", 13, 1 },
1937	{ "S_PLD_TXFULL", 12, 1 },
1938	{ "S_ISS_FIFO_SRDY", 11, 1 },
1939	{ "S_ISS_FIFO_DRDY", 10, 1 },
1940	{ "S_CT_TCP_OP_ISS_SRDY", 9, 1 },
1941	{ "S_CT_TCP_OP_ISS_DRDY", 8, 1 },
1942	{ "S_P2CSUMERROR_SRDY", 7, 1 },
1943	{ "S_P2CSUMERROR_DRDY", 6, 1 },
1944	{ "S_ERROR_SRDY", 5, 1 },
1945	{ "S_ERROR_DRDY", 4, 1 },
1946	{ "S_PLD_SRDY", 3, 1 },
1947	{ "S_PLD_DRDY", 2, 1 },
1948	{ "S_RX_PKT_ATTR_SRDY", 1, 1 },
1949	{ "S_RX_PKT_ATTR_DRDY", 0, 1 },
1950	{ "TP_DBG_ESIDE_IN3", 0x14D, 0 },
1951	{ "S_RXVALID", 31, 1 },
1952	{ "S_RXFULL", 30, 1 },
1953	{ "S_RXSOCP", 29, 1 },
1954	{ "S_RXEOP", 28, 1 },
1955	{ "S_RXVALID_I", 27, 1 },
1956	{ "S_RXFULL_I", 26, 1 },
1957	{ "S_RXRUNT", 25, 1 },
1958	{ "S_RXRUNTPARSER", 24, 1 },
1959	{ "S_RXVALID_I2", 23, 1 },
1960	{ "S_RXFULL_I2", 22, 1 },
1961	{ "S_RXSOCP_I2", 21, 1 },
1962	{ "S_RXEOP_I2", 20, 1 },
1963	{ "S_CT_MPA_TXVALID_FIFO", 19, 1 },
1964	{ "S_CT_MPA_TXFULL_FIFO", 18, 1 },
1965	{ "S_CT_MPA_TXVALID", 17, 1 },
1966	{ "S_CT_MPA_TXFULL", 16, 1 },
1967	{ "S_RXVALID_BUF", 15, 1 },
1968	{ "S_RXFULL_BUF", 14, 1 },
1969	{ "S_PLD_TXVALID", 13, 1 },
1970	{ "S_PLD_TXFULL", 12, 1 },
1971	{ "S_ISS_FIFO_SRDY", 11, 1 },
1972	{ "S_ISS_FIFO_DRDY", 10, 1 },
1973	{ "S_CT_TCP_OP_ISS_SRDY", 9, 1 },
1974	{ "S_CT_TCP_OP_ISS_DRDY", 8, 1 },
1975	{ "S_P2CSUMERROR_SRDY", 7, 1 },
1976	{ "S_P2CSUMERROR_DRDY", 6, 1 },
1977	{ "S_ERROR_SRDY", 5, 1 },
1978	{ "S_ERROR_DRDY", 4, 1 },
1979	{ "S_PLD_SRDY", 3, 1 },
1980	{ "S_PLD_DRDY", 2, 1 },
1981	{ "S_RX_PKT_ATTR_SRDY", 1, 1 },
1982	{ "S_RX_PKT_ATTR_DRDY", 0, 1 },
1983	{ "TP_DBG_ESIDE_FRM", 0x14E, 0 },
1984	{ "S_ERX2XERROR", 28, 4 },
1985	{ "S_EPLDTX2XERROR", 24, 4 },
1986	{ "S_ETXERROR", 20, 4 },
1987	{ "S_EPLDRXERROR", 16, 4 },
1988	{ "S_ERXSIZEERROR3", 12, 4 },
1989	{ "S_ERXSIZEERROR2", 8, 4 },
1990	{ "S_ERXSIZEERROR1", 4, 4 },
1991	{ "S_ERXSIZEERROR0", 0, 4 },
1992	{ "TP_DBG_ESIDE_DRP", 0x14F, 0 },
1993	{ "S_RXDROP3", 24, 8 },
1994	{ "S_RXDROP2", 16, 8 },
1995	{ "S_RXDROP1", 8, 8 },
1996	{ "S_RXDROP0", 0, 8 },
1997	{ "TP_DBG_ESIDE_TX", 0x150, 0 },
1998	{ "TXERRORCNT", 8, 24 },
1999	{ "S_ETXVALID", 4, 4 },
2000	{ "S_ETXFULL", 0, 4 },
2001	{ "TP_ESIDE_SVID_MASK", 0x151, 0 },
2002	{ "TP_ESIDE_DVID_MASK", 0x152, 0 },
2003	{ "TP_ESIDE_ALIGN_MASK", 0x153, 0 },
2004	{ "S_USE_LOOP_BIT", 24, 1 },
2005	{ "S_LOOP_OFFSET", 16, 8 },
2006	{ "S_DVID_ID_OFFSET", 8, 8 },
2007	{ "S_SVID_ID_OFFSET", 0, 8 },
2008	{ "TP_DBG_ESIDE_OP", 0x154, 0 },
2009	{ "S_RESERVED0", 30, 2 },
2010	{ "S_OPT_PARSER_FATAL_CHANNEL0", 29, 1 },
2011	{ "S_OPT_PARSER_BUSY_CHANNEL0", 28, 1 },
2012	{ "S_OPT_PARSER_ITCP_STATE_CHANNEL0", 26, 2 },
2013	{ "S_OPT_PARSER_OTK_STATE_CHANNEL0", 24, 2 },
2014	{ "S_RESERVED1", 22, 2 },
2015	{ "S_OPT_PARSER_FATAL_CHANNEL1", 21, 1 },
2016	{ "S_OPT_PARSER_BUSY_CHANNEL1", 20, 1 },
2017	{ "S_OPT_PARSER_ITCP_STATE_CHANNEL1", 18, 2 },
2018	{ "S_OPT_PARSER_OTK_STATE_CHANNEL1", 16, 2 },
2019	{ "S_RESERVED2", 14, 2 },
2020	{ "S_OPT_PARSER_FATAL_CHANNEL2", 13, 1 },
2021	{ "S_OPT_PARSER_BUSY_CHANNEL2", 12, 1 },
2022	{ "S_OPT_PARSER_ITCP_STATE_CHANNEL2", 10, 2 },
2023	{ "S_OPT_PARSER_OTK_STATE_CHANNEL2", 8, 2 },
2024	{ "S_RESERVED3", 6, 2 },
2025	{ "S_OPT_PARSER_FATAL_CHANNEL3", 5, 1 },
2026	{ "S_OPT_PARSER_BUSY_CHANNEL3", 4, 1 },
2027	{ "S_OPT_PARSER_ITCP_STATE_CHANNEL3", 2, 2 },
2028	{ "S_OPT_PARSER_OTK_STATE_CHANNEL3", 0, 2 },
2029	{ "TP_DBG_ESIDE_OP_ALT", 0x155, 0 },
2030	{ "S_RESERVED0", 30, 2 },
2031	{ "S_OPT_PARSER_PSTATE_FATAL_CHANNEL0", 29, 1 },
2032	{ "S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0", 24, 5 },
2033	{ "S_RESERVED1", 22, 2 },
2034	{ "S_OPT_PARSER_PSTATE_FATAL_CHANNEL1", 21, 1 },
2035	{ "S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1", 16, 5 },
2036	{ "S_RESERVED2", 14, 2 },
2037	{ "S_OPT_PARSER_PSTATE_FATAL_CHANNEL2", 13, 1 },
2038	{ "S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2", 8, 5 },
2039	{ "S_RESERVED3", 6, 2 },
2040	{ "S_OPT_PARSER_PSTATE_FATAL_CHANNEL3", 5, 1 },
2041	{ "S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3", 0, 5 },
2042	{ "TP_DBG_ESIDE_OP_BUSY", 0x156, 0 },
2043	{ "S_OPT_PARSER_BUSY_VEC_CHANNEL3", 24, 8 },
2044	{ "S_OPT_PARSER_BUSY_VEC_CHANNEL2", 16, 8 },
2045	{ "S_OPT_PARSER_BUSY_VEC_CHANNEL1", 8, 8 },
2046	{ "S_OPT_PARSER_BUSY_VEC_CHANNEL0", 0, 8 },
2047	{ "TP_DBG_ESIDE_OP_COOKIE", 0x157, 0 },
2048	{ "S_OPT_PARSER_COOKIE_CHANNEL3", 24, 8 },
2049	{ "S_OPT_PARSER_COOKIE_CHANNEL2", 16, 8 },
2050	{ "S_OPT_PARSER_COOKIE_CHANNEL1", 8, 8 },
2051	{ "S_OPT_PARSER_COOKIE_CHANNEL0", 0, 8 },
2052	{ NULL }
2053
2054};
2055
2056static struct cudbg_reg_info t6_tp_pio_regs_160[] = {
2057	{ "TP_ESIDE_CONFIG", 0x160, 0 },
2058	{ "VNI_EN", 26, 1 },
2059	{ "ENC_RX_EN", 25, 1 },
2060	{ "TNL_LKP_INNER_SEL", 24, 1 },
2061	{ "AttackFilterEnable", 23, 1 },
2062	{ "PingDrop", 20, 1 },
2063	{ "FragmentDrop", 19, 1 },
2064	{ "RoCEv2UDPPort", 0, 16 },
2065	{ NULL }
2066};
2067
2068static struct cudbg_reg_info t6_tp_pio_regs_70_to_75[] = {
2069	{ "TP_DBG_CACHE_WR_ALL", 0x70, 0 },
2070	{ "TP_DBG_CACHE_WR_HIT", 0x71, 0 },
2071	{ "TP_DBG_CACHE_RD_ALL", 0x72, 0 },
2072	{ "TP_DBG_CACHE_RD_HIT", 0x73, 0 },
2073	{ "TP_DBG_CACHE_MC_REQ", 0x74, 0 },
2074	{ "TP_DBG_CACHE_MC_RSP", 0x75, 0 },
2075	{ NULL }
2076};
2077
2078static struct cudbg_reg_info t5_tp_pio_regs_6f[] = {
2079	{ "TP_MIB_DEBUG", 0x6F, 0 },
2080	{ "S_SRC3", 31, 1 },
2081	{ "S_LINENUM3", 24, 7 },
2082	{ "S_SRC2", 23, 1 },
2083	{ "S_LINENUM2", 16, 7 },
2084	{ "S_SRC1", 15, 1 },
2085	{ "S_LINENUM1", 8, 7 },
2086	{ "S_SRC0", 7, 1 },
2087	{ "S_LINENUM0", 0, 7 },
2088	{ NULL }
2089};
2090
2091static struct cudbg_reg_info t5_tp_pio_regs_120_to_123[] = {
2092	{ "TP_TX_DROP_CNT_CH0", 0x120, 0 },
2093	{ "TP_TX_DROP_CNT_CH1", 0x121, 0 },
2094	{ "TP_TX_DROP_CNT_CH2", 0x122, 0 },
2095	{ "TP_TX_DROP_CNT_CH3", 0x123, 0 },
2096	{ NULL }
2097};
2098
2099static struct cudbg_reg_info t5_tp_pio_regs_12b_to_12c[] = {
2100	{ "TP_TX_DROP_CFG_CH0", 0x12B, 0 },
2101	{ "S_TIMERENABLED", 31, 1 },
2102	{ "S_TIMERERRORENABLE", 30, 1 },
2103	{ "S_TIMERTHRESHOLD", 4, 26 },
2104	{ "S_PACKETDROPS", 0, 4 },
2105	{ "TP_TX_DROP_CFG_CH1", 0x12C, 0 },
2106	{ "S_TIMERENABLED", 31, 1 },
2107	{ "S_TIMERERRORENABLE", 30, 1 },
2108	{ "S_TIMERTHRESHOLD", 4, 26 },
2109	{ "S_PACKETDROPS", 0, 4 },
2110	{ NULL }
2111};
2112
2113static struct cudbg_reg_info t5_tp_pio_regs_12f_to_143[] = {
2114	{ "TP_TX_DROP_MODE", 0x12F, 0 },
2115	{ "S_TXDROPMODECH3", 3, 1 },
2116	{ "S_TXDROPMODECH2", 2, 1 },
2117	{ "S_TXDROPMODECH1", 1, 1 },
2118	{ "S_TXDROPMODECH0", 0, 1 },
2119	{ "TP_DBG_ESIDE_PKT0", 0x130, 0 },
2120	{ "S_ETXSOPCNT", 28, 4 },
2121	{ "S_ETXEOPCNT", 24, 4 },
2122	{ "S_ETXPLDSOPCNT", 20, 4 },
2123	{ "S_ETXPLDEOPCNT", 16, 4 },
2124	{ "S_ERXSOPCNT", 12, 4 },
2125	{ "S_ERXEOPCNT", 8, 4 },
2126	{ "S_ERXPLDSOPCNT", 4, 4 },
2127	{ "S_ERXPLDEOPCNT", 0, 4 },
2128	{ "TP_DBG_ESIDE_PKT1", 0x131, 0 },
2129	{ "S_ETXSOPCNT", 28, 4 },
2130	{ "S_ETXEOPCNT", 24, 4 },
2131	{ "S_ETXPLDSOPCNT", 20, 4 },
2132	{ "S_ETXPLDEOPCNT", 16, 4 },
2133	{ "S_ERXSOPCNT", 12, 4 },
2134	{ "S_ERXEOPCNT", 8, 4 },
2135	{ "S_ERXPLDSOPCNT", 4, 4 },
2136	{ "S_ERXPLDEOPCNT", 0, 4 },
2137	{ "TP_DBG_ESIDE_PKT2", 0x132, 0 },
2138	{ "S_ETXSOPCNT", 28, 4 },
2139	{ "S_ETXEOPCNT", 24, 4 },
2140	{ "S_ETXPLDSOPCNT", 20, 4 },
2141	{ "S_ETXPLDEOPCNT", 16, 4 },
2142	{ "S_ERXSOPCNT", 12, 4 },
2143	{ "S_ERXEOPCNT", 8, 4 },
2144	{ "S_ERXPLDSOPCNT", 4, 4 },
2145	{ "S_ERXPLDEOPCNT", 0, 4 },
2146	{ "TP_DBG_ESIDE_PKT3", 0x133, 0 },
2147	{ "S_ETXSOPCNT", 28, 4 },
2148	{ "S_ETXEOPCNT", 24, 4 },
2149	{ "S_ETXPLDSOPCNT", 20, 4 },
2150	{ "S_ETXPLDEOPCNT", 16, 4 },
2151	{ "S_ERXSOPCNT", 12, 4 },
2152	{ "S_ERXEOPCNT", 8, 4 },
2153	{ "S_ERXPLDSOPCNT", 4, 4 },
2154	{ "S_ERXPLDEOPCNT", 0, 4 },
2155	{ "TP_DBG_ESIDE_FIFO0", 0x134, 0 },
2156	{ "S_PLDRXCSUMVALID1", 31, 1 },
2157	{ "S_PLDRXZEROPSRDY1", 30, 1 },
2158	{ "S_PLDRXVALID1", 29, 1 },
2159	{ "S_TCPRXVALID1", 28, 1 },
2160	{ "S_IPRXVALID1", 27, 1 },
2161	{ "S_ETHRXVALID1", 26, 1 },
2162	{ "S_CPLRXVALID1", 25, 1 },
2163	{ "S_FSTATIC1", 24, 1 },
2164	{ "S_ERRORSRDY1", 23, 1 },
2165	{ "S_PLDTXSRDY1", 22, 1 },
2166	{ "S_DBVLD1", 21, 1 },
2167	{ "S_PLDTXVALID1", 20, 1 },
2168	{ "S_ETXVALID1", 19, 1 },
2169	{ "S_ETXFULL1", 18, 1 },
2170	{ "S_ERXVALID1", 17, 1 },
2171	{ "S_ERXFULL1", 16, 1 },
2172	{ "S_PLDRXCSUMVALID0", 15, 1 },
2173	{ "S_PLDRXZEROPSRDY0", 14,  1},
2174	{ "S_PLDRXVALID0", 13, 1 },
2175	{ "S_TCPRXVALID0", 12, 1 },
2176	{ "S_IPRXVALID0", 11, 1 },
2177	{ "S_ETHRXVALID0", 10, 1 },
2178	{ "S_CPLRXVALID0", 9, 1 },
2179	{ "S_FSTATIC0", 8, 1 },
2180	{ "S_ERRORSRDY0", 7, 1 },
2181	{ "S_PLDTXSRDY0", 6, 1 },
2182	{ "S_DBVLD0", 5, 1 },
2183	{ "S_PLDTXVALID0", 4, 1 },
2184	{ "S_ETXVALID0", 3, 1 },
2185	{ "S_ETXFULL0", 2, 1 },
2186	{ "S_ERXVALID0", 1, 1 },
2187	{ "S_ERXFULL0", 0, 1 },
2188	{ "TP_DBG_ESIDE_FIFO1", 0x135, 0 },
2189	{ "S_PLDRXCSUMVALID3", 31, 1 },
2190	{ "S_PLDRXZEROPSRDY3", 30, 1 },
2191	{ "S_PLDRXVALID3", 29, 1 },
2192	{ "S_TCPRXVALID3", 28, 1 },
2193	{ "S_IPRXVALID3", 27, 1 },
2194	{ "S_ETHRXVALID3", 26, 1 },
2195	{ "S_CPLRXVALID3", 25, 1 },
2196	{ "S_FSTATIC3", 24, 1 },
2197	{ "S_ERRORSRDY3", 23, 1 },
2198	{ "S_PLDTXSRDY3", 22, 1 },
2199	{ "S_DBVLD3", 21, 1 },
2200	{ "S_PLDTXVALID3", 20, 1 },
2201	{ "S_ETXVALID3", 19, 1 },
2202	{ "S_ETXFULL3", 18, 1 },
2203	{ "S_ERXVALID3", 17, 1 },
2204	{ "S_ERXFULL3", 16, 1 },
2205	{ "S_PLDRXCSUMVALID2", 15, 1 },
2206	{ "S_PLDRXZEROPSRDY2", 14,  1},
2207	{ "S_PLDRXVALID2", 13, 1 },
2208	{ "S_TCPRXVALID2", 12, 1 },
2209	{ "S_IPRXVALID2", 11, 1 },
2210	{ "S_ETHRXVALID2", 10, 1 },
2211	{ "S_CPLRXVALID2", 9, 1 },
2212	{ "S_FSTATIC2", 8, 1 },
2213	{ "S_ERRORSRDY2", 7, 1 },
2214	{ "S_PLDTXSRDY2", 6, 1 },
2215	{ "S_DBVLD2", 5, 1 },
2216	{ "S_PLDTXVALID2", 4, 1 },
2217	{ "S_ETXVALID2", 3, 1 },
2218	{ "S_ETXFULL2", 2, 1 },
2219	{ "S_ERXVALID2", 1, 1 },
2220	{ "S_ERXFULL2", 0, 1 },
2221	{ "TP_DBG_ESIDE_DISP0", 0x136, 0 },
2222	{ "S_RESRDY", 31, 1 },
2223	{ "S_STATE", 28, 3 },
2224	{ "S_FIFOCPL5RXVALID", 27, 1 },
2225	{ "S_FIFOETHRXVALID", 26, 1 },
2226	{ "S_FIFOETHRXSOCP", 25, 1 },
2227	{ "S_FIFOPLDRXZEROP", 24, 1 },
2228	{ "S_PLDRXVALID", 23, 1 },
2229	{ "S_FIFOPLDRXZEROP_SRDY", 22, 1 },
2230	{ "S_FIFOIPRXVALID", 21, 1 },
2231	{ "S_FIFOTCPRXVALID", 20, 1 },
2232	{ "S_PLDRXCSUMVALID", 19, 1 },
2233	{ "S_FIFOIPCSUMSRDY", 18, 1 },
2234	{ "S_FIFOIPPSEUDOCSUMSRDY", 17, 1 },
2235	{ "S_FIFOTCPCSUMSRDY", 16, 1 },
2236	{ "S_ESTATIC4", 12, 4 },
2237	{ "S_FIFOCPLSOCPCNT", 10, 2 },
2238	{ "S_FIFOETHSOCPCNT", 8, 2 },
2239	{ "S_FIFOIPSOCPCNT", 6,  2},
2240	{ "S_FIFOTCPSOCPCNT", 4, 2 },
2241	{ "S_PLD_RXZEROP_CNT", 2, 2 },
2242	{ "S_ESTATIC6", 1, 1 },
2243	{ "S_TXFULL", 0, 1 },
2244	{ "TP_DBG_ESIDE_DISP1", 0x137, 0 },
2245	{ "S_RESRDY", 31, 1 },
2246	{ "S_STATE", 28, 3 },
2247	{ "S_FIFOCPL5RXVALID", 27, 1 },
2248	{ "S_FIFOETHRXVALID", 26, 1 },
2249	{ "S_FIFOETHRXSOCP", 25, 1 },
2250	{ "S_FIFOPLDRXZEROP", 24, 1 },
2251	{ "S_PLDRXVALID", 23, 1 },
2252	{ "S_FIFOPLDRXZEROP_SRDY", 22, 1 },
2253	{ "S_FIFOIPRXVALID", 21, 1 },
2254	{ "S_FIFOTCPRXVALID", 20, 1 },
2255	{ "S_PLDRXCSUMVALID", 19, 1 },
2256	{ "S_FIFOIPCSUMSRDY", 18, 1 },
2257	{ "S_FIFOIPPSEUDOCSUMSRDY", 17, 1 },
2258	{ "S_FIFOTCPCSUMSRDY", 16, 1 },
2259	{ "S_ESTATIC4", 12, 4 },
2260	{ "S_FIFOCPLSOCPCNT", 10, 2 },
2261	{ "S_FIFOETHSOCPCNT", 8, 2 },
2262	{ "S_FIFOIPSOCPCNT", 6,  2},
2263	{ "S_FIFOTCPSOCPCNT", 4, 2 },
2264	{ "S_PLD_RXZEROP_CNT", 2, 2 },
2265	{ "S_ESTATIC6", 1, 1 },
2266	{ "S_TXFULL", 0, 1 },
2267	{ "TP_MAC_MATCH_MAP0", 0x138, 0 },
2268	{ "S_MAPVALUEWR", 16, 8 },
2269	{ "S_RESERVED", 11, 5 },
2270	{ "S_MAPINDEX", 2, 9 },
2271	{ "S_MAPREAD", 1, 1 },
2272	{ "S_MAPWRITE", 0, 1 },
2273	{ "TP_MAC_MATCH_MAP1", 0x139, 0 },
2274	{ "S_RESERVED", 9, 15 },
2275	{ "S_MAPVALUERD", 0, 9 },
2276	{ "TP_DBG_ESIDE_DISP2", 0x13A, 0 },
2277	{ "S_RESRDY", 31, 1 },
2278	{ "S_STATE", 28, 3 },
2279	{ "S_FIFOCPL5RXVALID", 27, 1 },
2280	{ "S_FIFOETHRXVALID", 26, 1 },
2281	{ "S_FIFOETHRXSOCP", 25, 1 },
2282	{ "S_FIFOPLDRXZEROP", 24, 1 },
2283	{ "S_PLDRXVALID", 23, 1 },
2284	{ "S_FIFOPLDRXZEROP_SRDY", 22, 1 },
2285	{ "S_FIFOIPRXVALID", 21, 1 },
2286	{ "S_FIFOTCPRXVALID", 20, 1 },
2287	{ "S_PLDRXCSUMVALID", 19, 1 },
2288	{ "S_FIFOIPCSUMSRDY", 18, 1 },
2289	{ "S_FIFOIPPSEUDOCSUMSRDY", 17, 1 },
2290	{ "S_FIFOTCPCSUMSRDY", 16, 1 },
2291	{ "S_ESTATIC4", 12, 4 },
2292	{ "S_FIFOCPLSOCPCNT", 10, 2 },
2293	{ "S_FIFOETHSOCPCNT", 8, 2 },
2294	{ "S_FIFOIPSOCPCNT", 6,  2},
2295	{ "S_FIFOTCPSOCPCNT", 4, 2 },
2296	{ "S_PLD_RXZEROP_CNT", 2, 2 },
2297	{ "S_ESTATIC6", 1, 1 },
2298	{ "S_TXFULL", 0, 1 },
2299	{ "TP_DBG_ESIDE_DISP3", 0x13B, 0 },
2300	{ "S_RESRDY", 31, 1 },
2301	{ "S_STATE", 28, 3 },
2302	{ "S_FIFOCPL5RXVALID", 27, 1 },
2303	{ "S_FIFOETHRXVALID", 26, 1 },
2304	{ "S_FIFOETHRXSOCP", 25, 1 },
2305	{ "S_FIFOPLDRXZEROP", 24, 1 },
2306	{ "S_PLDRXVALID", 23, 1 },
2307	{ "S_FIFOPLDRXZEROP_SRDY", 22, 1 },
2308	{ "S_FIFOIPRXVALID", 21, 1 },
2309	{ "S_FIFOTCPRXVALID", 20, 1 },
2310	{ "S_PLDRXCSUMVALID", 19, 1 },
2311	{ "S_FIFOIPCSUMSRDY", 18, 1 },
2312	{ "S_FIFOIPPSEUDOCSUMSRDY", 17, 1 },
2313	{ "S_FIFOTCPCSUMSRDY", 16, 1 },
2314	{ "S_ESTATIC4", 12, 4 },
2315	{ "S_FIFOCPLSOCPCNT", 10, 2 },
2316	{ "S_FIFOETHSOCPCNT", 8, 2 },
2317	{ "S_FIFOIPSOCPCNT", 6,  2},
2318	{ "S_FIFOTCPSOCPCNT", 4, 2 },
2319	{ "S_PLD_RXZEROP_CNT", 2, 2 },
2320	{ "S_ESTATIC6", 1, 1 },
2321	{ "S_TXFULL", 0, 1 },
2322	{ "TP_DBG_ESIDE_HDR0", 0x13C, 0 },
2323	{ "S_TCPSOPCNT", 28, 4 },
2324	{ "S_TCPEOPCNT", 24, 4 },
2325	{ "S_IPSOPCNT", 20, 4 },
2326	{ "S_IPEOPCNT", 16, 4 },
2327	{ "S_ETHSOPCNT", 12, 4 },
2328	{ "S_ETHEOPCNT", 8, 4 },
2329	{ "S_CPLSOPCNT", 4, 4 },
2330	{ "S_CPLEOPCNT", 0, 4 },
2331	{ "TP_DBG_ESIDE_HDR1", 0x13D, 0 },
2332	{ "S_TCPSOPCNT", 28, 4 },
2333	{ "S_TCPEOPCNT", 24, 4 },
2334	{ "S_IPSOPCNT", 20, 4 },
2335	{ "S_IPEOPCNT", 16, 4 },
2336	{ "S_ETHSOPCNT", 12, 4 },
2337	{ "S_ETHEOPCNT", 8, 4 },
2338	{ "S_CPLSOPCNT", 4, 4 },
2339	{ "S_CPLEOPCNT", 0, 4 },
2340	{ "TP_DBG_ESIDE_HDR2", 0x13E, 0 },
2341	{ "S_TCPSOPCNT", 28, 4 },
2342	{ "S_TCPEOPCNT", 24, 4 },
2343	{ "S_IPSOPCNT", 20, 4 },
2344	{ "S_IPEOPCNT", 16, 4 },
2345	{ "S_ETHSOPCNT", 12, 4 },
2346	{ "S_ETHEOPCNT", 8, 4 },
2347	{ "S_CPLSOPCNT", 4, 4 },
2348	{ "S_CPLEOPCNT", 0, 4 },
2349	{ "TP_DBG_ESIDE_HDR3", 0x13F, 0 },
2350	{ "S_TCPSOPCNT", 28, 4 },
2351	{ "S_TCPEOPCNT", 24, 4 },
2352	{ "S_IPSOPCNT", 20, 4 },
2353	{ "S_IPEOPCNT", 16, 4 },
2354	{ "S_ETHSOPCNT", 12, 4 },
2355	{ "S_ETHEOPCNT", 8, 4 },
2356	{ "S_CPLSOPCNT", 4, 4 },
2357	{ "S_CPLEOPCNT", 0, 4 },
2358	{ "TP_VLAN_PRI_MAP", 0x140, 0 },
2359	{ "S_FILTERMODE", 15, 1 },
2360	{ "S_FCOEMASK", 14, 1 },
2361	{ "S_SRVRSRAM", 13, 1 },
2362	{ "S_FRAGMENTATION", 9, 1 },
2363	{ "S_MPSHITTYPE", 8, 1 },
2364	{ "S_MACMATCH", 7, 1 },
2365	{ "S_ETHERTYPE", 6, 1 },
2366	{ "S_PROTOCOL", 5, 1 },
2367	{ "S_TOS", 4,  1},
2368	{ "S_VLAN", 3, 1 },
2369	{ "S_VNIC_ID", 2, 1 },
2370	{ "S_PORT", 1, 1 },
2371	{ "S_FCOE", 0, 1 },
2372	{ "TP_INGRESS_CONFIG", 0x141, 0 },
2373	{ "S_OPAQUE_TYPE", 16, 16 },
2374	{ "S_OPAQUE_RM", 15, 1 },
2375	{ "S_OPAQUE_HDR_SIZE", 14,  1},
2376	{ "S_OPAQUE_RM_MAC_IN_MAC", 13, 1 },
2377	{ "S_FRAG_LEN_MOD8_COMPAT", 12, 1 },
2378	{ "S_VNIC", 11, 1 },
2379	{ "S_CSUM_HAS_PSEUDO_HDR", 10, 1 },
2380	{ "S_RM_OVLAN", 9, 1 },
2381	{ "S_LOOKUPEVERYPKT", 8, 1 },
2382	{ "S_IPV6_EXT_HDR_SKIP", 0, 8 },
2383	{ "TP_TX_DROP_CFG_CH2", 0x142, 0 },
2384	{ "S_TIMERENABLED", 31, 1 },
2385	{ "S_TIMERERRORENABLE", 30, 1 },
2386	{ "S_TIMERTHRESHOLD", 4, 26 },
2387	{ "S_PACKETDROPS", 0, 4 },
2388	{ "TP_TX_DROP_CFG_CH3", 0x143, 0 },
2389	{ "S_TIMERENABLED", 31, 1 },
2390	{ "S_TIMERERRORENABLE", 30, 1 },
2391	{ "S_TIMERTHRESHOLD", 4, 26 },
2392	{ "S_PACKETDROPS", 0, 4 },
2393	{ NULL }
2394};
2395
2396static struct cudbg_reg_info t5_tp_pio_regs_145_to_157[] = {
2397	{ "TP_INGRESS_CONFIG2", 0x145, 0 },
2398	{ "S_IPV6_UDP_CSUM_COMPAT", 31, 1 },
2399	{ "S_VNTAGPLDENABLE", 30, 1 },
2400	{ "S_TCP_PLD_FILTER_OFFSET", 20,  10},
2401	{ "S_UDP_PLD_FILTER_OFFSET", 10, 10 },
2402	{ "S_TNL_PLD_FILTER_OFFSET", 0, 10 },
2403	{ "TP_EHDR_CONFIG_LO", 0x146, 0 },
2404	{ "S_CPLLIMIT", 24, 8 },
2405	{ "S_ETHLIMIT", 16, 8 },
2406	{ "S_IPLIMIT", 8, 8 },
2407	{ "S_TCPLIMIT", 0, 8 },
2408	{ "TP_EHDR_CONFIG_HI", 0x147, 0 },
2409	{ "S_CPLLIMIT", 24, 8 },
2410	{ "S_ETHLIMIT", 16, 8 },
2411	{ "S_IPLIMIT", 8, 8 },
2412	{ "S_TCPLIMIT", 0, 8 },
2413	{ "TP_DBG_ESIDE_INT", 0x148, 0 },
2414	{ "S_ERXSOP2X", 28, 4 },
2415	{ "S_ERXEOP2X", 24, 4 },
2416	{ "S_ERXVALID2X", 20, 4 },
2417	{ "S_ERXAFULL2X", 16, 4 },
2418	{ "S_PLD2XTXVALID", 12, 4 },
2419	{ "S_PLD2XTXAFULL", 8, 4 },
2420	{ "S_ERRORSRDY", 7, 1 },
2421	{ "S_ERRORDRDY", 6, 1 },
2422	{ "S_TCPOPSRDY", 5, 1 },
2423	{ "S_TCPOPDRDY", 4, 1 },
2424	{ "S_PLDTXSRDY", 3, 1 },
2425	{ "S_PLDTXDRDY", 2, 1 },
2426	{ "S_TCPOPTTXVALID", 1, 1 },
2427	{ "S_TCPOPTTXFULL", 0, 1 },
2428	{ "TP_DBG_ESIDE_DEMUX", 0x149, 0 },
2429	{ "S_EALLDONE", 28, 4 },
2430	{ "S_EFIFOPLDDONE", 24, 4 },
2431	{ "S_EDBDONE", 20, 4 },
2432	{ "S_EISSFIFODONE", 16, 4 },
2433	{ "S_EACKERRFIFODONE", 12, 4 },
2434	{ "S_EFIFOERRORDONE", 8, 4 },
2435	{ "S_ERXPKTATTRFIFOFDONE", 4, 4 },
2436	{ "S_ETCPOPDONE", 0, 4 },
2437	{ "TP_DBG_ESIDE_IN0", 0x14A, 0 },
2438	{ "S_RXVALID", 31, 1 },
2439	{ "S_RXFULL", 30, 1 },
2440	{ "S_RXSOCP", 29, 1 },
2441	{ "S_RXEOP", 28, 1 },
2442	{ "S_RXVALID_I", 27, 1 },
2443	{ "S_RXFULL_I", 26, 1 },
2444	{ "S_RXRUNT", 25, 1 },
2445	{ "S_RXRUNTPARSER", 24, 1 },
2446	{ "S_RXVALID_I2", 23, 1 },
2447	{ "S_RXFULL_I2", 22, 1 },
2448	{ "S_RXSOCP_I2", 21, 1 },
2449	{ "S_RXEOP_I2", 20, 1 },
2450	{ "S_CT_MPA_TXVALID_FIFO", 19, 1 },
2451	{ "S_CT_MPA_TXFULL_FIFO", 18, 1 },
2452	{ "S_CT_MPA_TXVALID", 17, 1 },
2453	{ "S_CT_MPA_TXFULL", 16, 1 },
2454	{ "S_RXVALID_BUF", 15, 1 },
2455	{ "S_RXFULL_BUF", 14, 1 },
2456	{ "S_PLD_TXVALID", 13, 1 },
2457	{ "S_PLD_TXFULL", 12, 1 },
2458	{ "S_ISS_FIFO_SRDY", 11, 1 },
2459	{ "S_ISS_FIFO_DRDY", 10, 1 },
2460	{ "S_CT_TCP_OP_ISS_SRDY", 9, 1 },
2461	{ "S_CT_TCP_OP_ISS_DRDY", 8, 1 },
2462	{ "S_P2CSUMERROR_SRDY", 7, 1 },
2463	{ "S_P2CSUMERROR_DRDY", 6, 1 },
2464	{ "S_ERROR_SRDY", 5, 1 },
2465	{ "S_ERROR_DRDY", 4, 1 },
2466	{ "S_PLD_SRDY", 3, 1 },
2467	{ "S_PLD_DRDY", 2, 1 },
2468	{ "S_RX_PKT_ATTR_SRDY", 1, 1 },
2469	{ "S_RX_PKT_ATTR_DRDY", 0, 1 },
2470	{ "TP_DBG_ESIDE_IN1", 0x14B, 0 },
2471	{ "S_RXVALID", 31, 1 },
2472	{ "S_RXFULL", 30, 1 },
2473	{ "S_RXSOCP", 29, 1 },
2474	{ "S_RXEOP", 28, 1 },
2475	{ "S_RXVALID_I", 27, 1 },
2476	{ "S_RXFULL_I", 26, 1 },
2477	{ "S_RXRUNT", 25, 1 },
2478	{ "S_RXRUNTPARSER", 24, 1 },
2479	{ "S_RXVALID_I2", 23, 1 },
2480	{ "S_RXFULL_I2", 22, 1 },
2481	{ "S_RXSOCP_I2", 21, 1 },
2482	{ "S_RXEOP_I2", 20, 1 },
2483	{ "S_CT_MPA_TXVALID_FIFO", 19, 1 },
2484	{ "S_CT_MPA_TXFULL_FIFO", 18, 1 },
2485	{ "S_CT_MPA_TXVALID", 17, 1 },
2486	{ "S_CT_MPA_TXFULL", 16, 1 },
2487	{ "S_RXVALID_BUF", 15, 1 },
2488	{ "S_RXFULL_BUF", 14, 1 },
2489	{ "S_PLD_TXVALID", 13, 1 },
2490	{ "S_PLD_TXFULL", 12, 1 },
2491	{ "S_ISS_FIFO_SRDY", 11, 1 },
2492	{ "S_ISS_FIFO_DRDY", 10, 1 },
2493	{ "S_CT_TCP_OP_ISS_SRDY", 9, 1 },
2494	{ "S_CT_TCP_OP_ISS_DRDY", 8, 1 },
2495	{ "S_P2CSUMERROR_SRDY", 7, 1 },
2496	{ "S_P2CSUMERROR_DRDY", 6, 1 },
2497	{ "S_ERROR_SRDY", 5, 1 },
2498	{ "S_ERROR_DRDY", 4, 1 },
2499	{ "S_PLD_SRDY", 3, 1 },
2500	{ "S_PLD_DRDY", 2, 1 },
2501	{ "S_RX_PKT_ATTR_SRDY", 1, 1 },
2502	{ "S_RX_PKT_ATTR_DRDY", 0, 1 },
2503	{ "TP_DBG_ESIDE_IN2", 0x14C, 0 },
2504	{ "S_RXVALID", 31, 1 },
2505	{ "S_RXFULL", 30, 1 },
2506	{ "S_RXSOCP", 29, 1 },
2507	{ "S_RXEOP", 28, 1 },
2508	{ "S_RXVALID_I", 27, 1 },
2509	{ "S_RXFULL_I", 26, 1 },
2510	{ "S_RXRUNT", 25, 1 },
2511	{ "S_RXRUNTPARSER", 24, 1 },
2512	{ "S_RXVALID_I2", 23, 1 },
2513	{ "S_RXFULL_I2", 22, 1 },
2514	{ "S_RXSOCP_I2", 21, 1 },
2515	{ "S_RXEOP_I2", 20, 1 },
2516	{ "S_CT_MPA_TXVALID_FIFO", 19, 1 },
2517	{ "S_CT_MPA_TXFULL_FIFO", 18, 1 },
2518	{ "S_CT_MPA_TXVALID", 17, 1 },
2519	{ "S_CT_MPA_TXFULL", 16, 1 },
2520	{ "S_RXVALID_BUF", 15, 1 },
2521	{ "S_RXFULL_BUF", 14, 1 },
2522	{ "S_PLD_TXVALID", 13, 1 },
2523	{ "S_PLD_TXFULL", 12, 1 },
2524	{ "S_ISS_FIFO_SRDY", 11, 1 },
2525	{ "S_ISS_FIFO_DRDY", 10, 1 },
2526	{ "S_CT_TCP_OP_ISS_SRDY", 9, 1 },
2527	{ "S_CT_TCP_OP_ISS_DRDY", 8, 1 },
2528	{ "S_P2CSUMERROR_SRDY", 7, 1 },
2529	{ "S_P2CSUMERROR_DRDY", 6, 1 },
2530	{ "S_ERROR_SRDY", 5, 1 },
2531	{ "S_ERROR_DRDY", 4, 1 },
2532	{ "S_PLD_SRDY", 3, 1 },
2533	{ "S_PLD_DRDY", 2, 1 },
2534	{ "S_RX_PKT_ATTR_SRDY", 1, 1 },
2535	{ "S_RX_PKT_ATTR_DRDY", 0, 1 },
2536	{ "TP_DBG_ESIDE_IN3", 0x14D, 0 },
2537	{ "S_RXVALID", 31, 1 },
2538	{ "S_RXFULL", 30, 1 },
2539	{ "S_RXSOCP", 29, 1 },
2540	{ "S_RXEOP", 28, 1 },
2541	{ "S_RXVALID_I", 27, 1 },
2542	{ "S_RXFULL_I", 26, 1 },
2543	{ "S_RXRUNT", 25, 1 },
2544	{ "S_RXRUNTPARSER", 24, 1 },
2545	{ "S_RXVALID_I2", 23, 1 },
2546	{ "S_RXFULL_I2", 22, 1 },
2547	{ "S_RXSOCP_I2", 21, 1 },
2548	{ "S_RXEOP_I2", 20, 1 },
2549	{ "S_CT_MPA_TXVALID_FIFO", 19, 1 },
2550	{ "S_CT_MPA_TXFULL_FIFO", 18, 1 },
2551	{ "S_CT_MPA_TXVALID", 17, 1 },
2552	{ "S_CT_MPA_TXFULL", 16, 1 },
2553	{ "S_RXVALID_BUF", 15, 1 },
2554	{ "S_RXFULL_BUF", 14, 1 },
2555	{ "S_PLD_TXVALID", 13, 1 },
2556	{ "S_PLD_TXFULL", 12, 1 },
2557	{ "S_ISS_FIFO_SRDY", 11, 1 },
2558	{ "S_ISS_FIFO_DRDY", 10, 1 },
2559	{ "S_CT_TCP_OP_ISS_SRDY", 9, 1 },
2560	{ "S_CT_TCP_OP_ISS_DRDY", 8, 1 },
2561	{ "S_P2CSUMERROR_SRDY", 7, 1 },
2562	{ "S_P2CSUMERROR_DRDY", 6, 1 },
2563	{ "S_ERROR_SRDY", 5, 1 },
2564	{ "S_ERROR_DRDY", 4, 1 },
2565	{ "S_PLD_SRDY", 3, 1 },
2566	{ "S_PLD_DRDY", 2, 1 },
2567	{ "S_RX_PKT_ATTR_SRDY", 1, 1 },
2568	{ "S_RX_PKT_ATTR_DRDY", 0, 1 },
2569	{ "TP_DBG_ESIDE_FRM", 0x14E, 0 },
2570	{ "S_ERX2XERROR", 28, 4 },
2571	{ "S_EPLDTX2XERROR", 24, 4 },
2572	{ "S_ETXERROR", 20, 4 },
2573	{ "S_EPLDRXERROR", 16, 4 },
2574	{ "S_ERXSIZEERROR3", 12, 4 },
2575	{ "S_ERXSIZEERROR2", 8, 4 },
2576	{ "S_ERXSIZEERROR1", 4, 4 },
2577	{ "S_ERXSIZEERROR0", 0, 4 },
2578	{ "TP_DBG_ESIDE_DRP", 0x14F, 0 },
2579	{ "S_RXDROP3", 24, 8 },
2580	{ "S_RXDROP2", 16, 8 },
2581	{ "S_RXDROP1", 8, 8 },
2582	{ "S_RXDROP0", 0, 8 },
2583	{ "TP_DBG_ESIDE_TX", 0x150, 0 },
2584	{ "S_ETXVALID", 4, 4 },
2585	{ "S_ETXFULL", 0, 4 },
2586	{ "TP_ESIDE_SVID_MASK", 0x151, 0 },
2587	{ "TP_ESIDE_DVID_MASK", 0x152, 0 },
2588	{ "TP_ESIDE_ALIGN_MASK", 0x153, 0 },
2589	{ "S_USE_LOOP_BIT", 24, 1 },
2590	{ "S_LOOP_OFFSET", 16, 8 },
2591	{ "S_DVID_ID_OFFSET", 8, 8 },
2592	{ "S_SVID_ID_OFFSET", 0, 8 },
2593	{ "TP_DBG_ESIDE_OP", 0x154, 0 },
2594	{ "S_RESERVED0", 30, 2 },
2595	{ "S_OPT_PARSER_FATAL_CHANNEL0", 29, 1 },
2596	{ "S_OPT_PARSER_BUSY_CHANNEL0", 28, 1 },
2597	{ "S_OPT_PARSER_ITCP_STATE_CHANNEL0", 26, 2 },
2598	{ "S_OPT_PARSER_OTK_STATE_CHANNEL0", 24, 2 },
2599	{ "S_RESERVED1", 22, 2 },
2600	{ "S_OPT_PARSER_FATAL_CHANNEL1", 21, 1 },
2601	{ "S_OPT_PARSER_BUSY_CHANNEL1", 20, 1 },
2602	{ "S_OPT_PARSER_ITCP_STATE_CHANNEL1", 18, 2 },
2603	{ "S_OPT_PARSER_OTK_STATE_CHANNEL1", 16, 2 },
2604	{ "S_RESERVED2", 14, 2 },
2605	{ "S_OPT_PARSER_FATAL_CHANNEL2", 13, 1 },
2606	{ "S_OPT_PARSER_BUSY_CHANNEL2", 12, 1 },
2607	{ "S_OPT_PARSER_ITCP_STATE_CHANNEL2", 10, 2 },
2608	{ "S_OPT_PARSER_OTK_STATE_CHANNEL2", 8, 2 },
2609	{ "S_RESERVED3", 6, 2 },
2610	{ "S_OPT_PARSER_FATAL_CHANNEL3", 5, 1 },
2611	{ "S_OPT_PARSER_BUSY_CHANNEL3", 4, 1 },
2612	{ "S_OPT_PARSER_ITCP_STATE_CHANNEL3", 2, 2 },
2613	{ "S_OPT_PARSER_OTK_STATE_CHANNEL3", 0, 2 },
2614	{ "TP_DBG_ESIDE_OP_ALT", 0x155, 0 },
2615	{ "S_RESERVED0", 30, 2 },
2616	{ "S_OPT_PARSER_PSTATE_FATAL_CHANNEL0", 29, 1 },
2617	{ "S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0", 24, 5 },
2618	{ "S_RESERVED1", 22, 2 },
2619	{ "S_OPT_PARSER_PSTATE_FATAL_CHANNEL1", 21, 1 },
2620	{ "S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1", 16, 5 },
2621	{ "S_RESERVED2", 14, 2 },
2622	{ "S_OPT_PARSER_PSTATE_FATAL_CHANNEL2", 13, 1 },
2623	{ "S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2", 8, 5 },
2624	{ "S_RESERVED3", 6, 2 },
2625	{ "S_OPT_PARSER_PSTATE_FATAL_CHANNEL3", 5, 1 },
2626	{ "S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3", 0, 5 },
2627	{ "TP_DBG_ESIDE_OP_BUSY", 0x156, 0 },
2628	{ "S_OPT_PARSER_BUSY_VEC_CHANNEL3", 24, 8 },
2629	{ "S_OPT_PARSER_BUSY_VEC_CHANNEL2", 16, 8 },
2630	{ "S_OPT_PARSER_BUSY_VEC_CHANNEL1", 8, 8 },
2631	{ "S_OPT_PARSER_BUSY_VEC_CHANNEL0", 0, 8 },
2632	{ "TP_DBG_ESIDE_OP_COOKIE", 0x157, 0 },
2633	{ "S_OPT_PARSER_COOKIE_CHANNEL3", 24, 8 },
2634	{ "S_OPT_PARSER_COOKIE_CHANNEL2", 16, 8 },
2635	{ "S_OPT_PARSER_COOKIE_CHANNEL1", 8, 8 },
2636	{ "S_OPT_PARSER_COOKIE_CHANNEL0", 0, 8 },
2637	{ NULL }
2638};
2639
2640static struct cudbg_reg_info t6_tp_pio_regs_230_to_248[] = {
2641	{ "TP_DBG_CSIDE_RX0", 0x230, 0 },
2642	{ "S_CRXSOPCNT", 28, 4 },
2643	{ "S_CRXEOPCNT", 24, 4 },
2644	{ "S_CRXPLDSOPCNT", 20, 4 },
2645	{ "S_CRXPLDEOPCNT", 16, 4 },
2646	{ "S_CRXARBSOPCNT", 12, 4 },
2647	{ "S_CRXARBEOPCNT", 8, 4 },
2648	{ "S_CRXCPLSOPCNT", 4, 4 },
2649	{ "S_CRXCPLEOPCNT", 0, 4 },
2650	{ "TP_DBG_CSIDE_RX1", 0x231, 0 },
2651	{ "S_CRXSOPCNT", 28, 4 },
2652	{ "S_CRXEOPCNT", 24, 4 },
2653	{ "S_CRXPLDSOPCNT", 20, 4 },
2654	{ "S_CRXPLDEOPCNT", 16, 4 },
2655	{ "S_CRXARBSOPCNT", 12, 4 },
2656	{ "S_CRXARBEOPCNT", 8, 4 },
2657	{ "S_CRXCPLSOPCNT", 4, 4 },
2658	{ "S_CRXCPLEOPCNT", 0, 4 },
2659	{ "TP_DBG_CSIDE_RX2", 0x232, 0 },
2660	{ "S_CRXSOPCNT", 28, 4 },
2661	{ "S_CRXEOPCNT", 24, 4 },
2662	{ "S_CRXPLDSOPCNT", 20, 4 },
2663	{ "S_CRXPLDEOPCNT", 16, 4 },
2664	{ "S_CRXARBSOPCNT", 12, 4 },
2665	{ "S_CRXARBEOPCNT", 8, 4 },
2666	{ "S_CRXCPLSOPCNT", 4, 4 },
2667	{ "S_CRXCPLEOPCNT", 0, 4 },
2668	{ "TP_DBG_CSIDE_RX3", 0x233, 0 },
2669	{ "S_CRXSOPCNT", 28, 4 },
2670	{ "S_CRXEOPCNT", 24, 4 },
2671	{ "S_CRXPLDSOPCNT", 20, 4 },
2672	{ "S_CRXPLDEOPCNT", 16, 4 },
2673	{ "S_CRXARBSOPCNT", 12, 4 },
2674	{ "S_CRXARBEOPCNT", 8, 4 },
2675	{ "S_CRXCPLSOPCNT", 4, 4 },
2676	{ "S_CRXCPLEOPCNT", 0, 4 },
2677	{ "TP_DBG_CSIDE_TX0", 0x234, 0 },
2678	{ "S_TXSOPCNT", 28, 4 },
2679	{ "S_TXEOPCNT", 24, 4 },
2680	{ "S_TXPLDSOPCNT", 20, 4 },
2681	{ "S_TXPLDEOPCNT", 16, 4 },
2682	{ "S_TXARBSOPCNT", 12, 4 },
2683	{ "S_TXARBEOPCNT", 8, 4 },
2684	{ "S_TXCPLSOPCNT", 4, 4 },
2685	{ "S_TXCPLEOPCNT", 0, 4 },
2686	{ "TP_DBG_CSIDE_TX1", 0x235, 0 },
2687	{ "S_TXSOPCNT", 28, 4 },
2688	{ "S_TXEOPCNT", 24, 4 },
2689	{ "S_TXPLDSOPCNT", 20, 4 },
2690	{ "S_TXPLDEOPCNT", 16, 4 },
2691	{ "S_TXARBSOPCNT", 12, 4 },
2692	{ "S_TXARBEOPCNT", 8, 4 },
2693	{ "S_TXCPLSOPCNT", 4, 4 },
2694	{ "S_TXCPLEOPCNT", 0, 4 },
2695	{ "TP_DBG_CSIDE_TX2", 0x236, 0 },
2696	{ "S_TXSOPCNT", 28, 4 },
2697	{ "S_TXEOPCNT", 24, 4 },
2698	{ "S_TXPLDSOPCNT", 20, 4 },
2699	{ "S_TXPLDEOPCNT", 16, 4 },
2700	{ "S_TXARBSOPCNT", 12, 4 },
2701	{ "S_TXARBEOPCNT", 8, 4 },
2702	{ "S_TXCPLSOPCNT", 4, 4 },
2703	{ "S_TXCPLEOPCNT", 0, 4 },
2704	{ "TP_DBG_CSIDE_TX3", 0x237, 0 },
2705	{ "S_TXSOPCNT", 28, 4 },
2706	{ "S_TXEOPCNT", 24, 4 },
2707	{ "S_TXPLDSOPCNT", 20, 4 },
2708	{ "S_TXPLDEOPCNT", 16, 4 },
2709	{ "S_TXARBSOPCNT", 12, 4 },
2710	{ "S_TXARBEOPCNT", 8, 4 },
2711	{ "S_TXCPLSOPCNT", 4, 4 },
2712	{ "S_TXCPLEOPCNT", 0, 4 },
2713	{ "TP_DBG_CSIDE_FIFO0", 0x238, 0 },
2714	{ "S_PLD_RXZEROP_SRDY1", 31, 1 },
2715	{ "S_PLD_RXZEROP_DRDY1", 30, 1 },
2716	{ "S_PLD_TXZEROP_SRDY1", 29, 1 },
2717	{ "S_PLD_TXZEROP_DRDY1", 28, 1 },
2718	{ "S_PLD_TX_SRDY1", 27, 1 },
2719	{ "S_PLD_TX_DRDY1", 26, 1 },
2720	{ "S_ERROR_SRDY1", 25, 1 },
2721	{ "S_ERROR_DRDY1", 24, 1 },
2722	{ "S_DB_VLD1", 23, 1 },
2723	{ "S_DB_GT1", 22, 1 },
2724	{ "S_TXVALID1", 21, 1 },
2725	{ "S_TXFULL1", 20, 1 },
2726	{ "S_PLD_TXVALID1", 19 , 1 },
2727	{ "S_PLD_TXFULL1", 18, 1 },
2728	{ "S_CPL5_TXVALID1", 17, 1 },
2729	{ "S_CPL5_TXFULL1", 16, 1 },
2730	{ "S_PLD_RXZEROP_SRDY0", 15, 1 },
2731	{ "S_PLD_RXZEROP_DRDY0", 14, 1 },
2732	{ "S_PLD_TXZEROP_SRDY0", 13, 1 },
2733	{ "S_PLD_TXZEROP_DRDY0", 12, 1 },
2734	{ "S_PLD_TX_SRDY0", 11, 1 },
2735	{ "S_PLD_TX_DRDY0", 10, 1 },
2736	{ "S_ERROR_SRDY0", 9, 1 },
2737	{ "S_ERROR_DRDY0", 8, 1 },
2738	{ "S_DB_VLD0", 7, 1 },
2739	{ "S_DB_GT0", 6, 1 },
2740	{ "S_TXVALID0", 5, 1 },
2741	{ "S_TXFULL0", 4, 1 },
2742	{ "S_PLD_TXVALID0", 3, 1 },
2743	{ "S_PLD_TXFULL0", 2, 1 },
2744	{ "S_CPL5_TXVALID0", 1, 1 },
2745	{ "S_CPL5_TXFULL0", 0, 1 },
2746	{ "TP_DBG_CSIDE_FIFO1", 0x239, 0 },
2747	{ "S_PLD_RXZEROP_SRDY3", 31, 1 },
2748	{ "S_PLD_RXZEROP_DRDY3", 30, 1 },
2749	{ "S_PLD_TXZEROP_SRDY3", 29, 1 },
2750	{ "S_PLD_TXZEROP_DRDY3", 28, 1 },
2751	{ "S_PLD_TX_SRDY3", 27, 1 },
2752	{ "S_PLD_TX_DRDY3", 26, 1 },
2753	{ "S_ERROR_SRDY3", 25, 1 },
2754	{ "S_ERROR_DRDY3", 24, 1 },
2755	{ "S_DB_VLD3", 23, 1 },
2756	{ "S_DB_GT3", 22, 1 },
2757	{ "S_TXVALID3", 21, 1 },
2758	{ "S_TXFULL3", 20, 1 },
2759	{ "S_PLD_TXVALID3", 19 , 1 },
2760	{ "S_PLD_TXFULL3", 18, 1 },
2761	{ "S_CPL5_TXVALID3", 17, 1 },
2762	{ "S_CPL5_TXFULL3", 16, 1 },
2763	{ "S_PLD_RXZEROP_SRDY2", 15, 1 },
2764	{ "S_PLD_RXZEROP_DRDY2", 14, 1 },
2765	{ "S_PLD_TXZEROP_SRDY2", 13, 1 },
2766	{ "S_PLD_TXZEROP_DRDY2", 12, 1 },
2767	{ "S_PLD_TX_SRDY2", 11, 1 },
2768	{ "S_PLD_TX_DRDY2", 10, 1 },
2769	{ "S_ERROR_SRDY2", 9, 1 },
2770	{ "S_ERROR_DRDY2", 8, 1 },
2771	{ "S_DB_VLD2", 7, 1 },
2772	{ "S_DB_GT2", 6, 1 },
2773	{ "S_TXVALID2", 5, 1 },
2774	{ "S_TXFULL2", 4, 1 },
2775	{ "S_PLD_TXVALID2", 3, 1 },
2776	{ "S_PLD_TXFULL2", 2, 1 },
2777	{ "S_CPL5_TXVALID2", 1, 1 },
2778	{ "S_CPL5_TXFULL2", 0, 1 },
2779	{ "TP_DBG_CSIDE_DISP0", 0x23A, 0 },
2780	{ "S_TXFULL", 31, 1 },
2781	{ "S_STATE", 28, 3 },
2782	{ "S_CPL5RXVALID", 27, 1 },
2783	{ "S_CPL5RXFULL", 26, 1 },
2784	{ "S_PLD_RXZEROP_SRDY", 25, 1 },
2785	{ "S_PLD_RXZEROP", 24, 1 },
2786	{ "S_PLD2XRXVALID", 23, 1 },
2787	{ "S_DDP_SRDY", 22, 1 },
2788	{ "S_DDP_DRDY", 21, 1 },
2789	{ "S_DDPSTATE", 16, 5 },
2790	{ "S_DDPMSGCODE", 12, 4 },
2791	{ "S_CPL5SOCPCNT", 8, 4 },
2792	{ "S_PLDRXZEROPCNT", 4, 4 },
2793	{ "S_TXFRMERR2", 3, 1 },
2794	{ "S_TXFRMERR1", 2, 1 },
2795	{ "S_TXVALID2X", 1, 1 },
2796	{ "S_TXFULL2X", 0, 1 },
2797	{ "TP_DBG_CSIDE_DISP1", 0x23B, 0 },
2798	{ "S_TXFULL", 31, 1 },
2799	{ "S_STATE", 28, 3 },
2800	{ "S_CPL5RXVALID", 27, 1 },
2801	{ "S_CPL5RXFULL", 26, 1 },
2802	{ "S_PLD_RXZEROP_SRDY", 25, 1 },
2803	{ "S_PLD_RXZEROP", 24, 1 },
2804	{ "S_PLD2XRXVALID", 23, 1 },
2805	{ "S_DDP_SRDY", 22, 1 },
2806	{ "S_DDP_DRDY", 21, 1 },
2807	{ "S_DDPSTATE", 16, 5 },
2808	{ "S_DDPMSGCODE", 12, 4 },
2809	{ "S_CPL5SOCPCNT", 8, 4 },
2810	{ "S_PLDRXZEROPCNT", 4, 4 },
2811	{ "S_TXFRMERR2", 3, 1 },
2812	{ "S_TXFRMERR1", 2, 1 },
2813	{ "S_TXVALID2X", 1, 1 },
2814	{ "S_TXFULL2X", 0, 1 },
2815	{ "TP_DBG_CSIDE_DDP0", 0x23C, 0 },
2816	{ "S_DDPMSGLATEST7", 28, 4 },
2817	{ "S_DDPMSGLATEST6", 24, 4 },
2818	{ "S_DDPMSGLATEST5", 20, 4 },
2819	{ "S_DDPMSGLATEST4", 16, 4 },
2820	{ "S_DDPMSGLATEST3", 12, 4 },
2821	{ "S_DDPMSGLATEST2", 8, 4 },
2822	{ "S_DDPMSGLATEST1", 4, 4 },
2823	{ "S_DDPMSGLATEST0", 0, 4 },
2824	{ "TP_DBG_CSIDE_DDP1", 0x23D, 0 },
2825	{ "S_DDPMSGLATEST7", 28, 4 },
2826	{ "S_DDPMSGLATEST6", 24, 4 },
2827	{ "S_DDPMSGLATEST5", 20, 4 },
2828	{ "S_DDPMSGLATEST4", 16, 4 },
2829	{ "S_DDPMSGLATEST3", 12, 4 },
2830	{ "S_DDPMSGLATEST2", 8, 4 },
2831	{ "S_DDPMSGLATEST1", 4, 4 },
2832	{ "S_DDPMSGLATEST0", 0, 4 },
2833	{ "TP_DBG_CSIDE_FRM", 0x23E, 0 },
2834	{ "S_CRX2XERROR", 28, 4 },
2835	{ "S_CPLDTX2XERROR", 24, 4 },
2836	{ "S_CTXERROR", 22, 2 },
2837	{ "S_CPLDRXERROR", 20, 2 },
2838	{ "S_CPLRXERROR", 18, 2 },
2839	{ "S_CPLTXERROR", 16, 2 },
2840	{ "S_CPRSERROR", 0, 4 },
2841	{ "TP_DBG_CSIDE_INT", 0x23F, 0 },
2842	{ "S_CRXVALID2X", 28, 4 },
2843	{ "S_CRXAFULL2X", 24, 4 },
2844	{ "S_CTXVALID2X", 22, 2 },
2845	{ "S_CTXAFULL2X", 20, 2 },
2846	{ "S_PLD2X_RXVALID", 18, 2 },
2847	{ "S_PLD2X_RXAFULL", 16, 2 },
2848	{ "S_CSIDE_DDP_VALID", 14, 2 },
2849	{ "S_DDP_AFULL", 12, 2 },
2850	{ "S_TRC_RXVALID", 11, 1 },
2851	{ "S_TRC_RXFULL", 10, 1 },
2852	{ "S_CPL5_TXVALID", 9, 1 },
2853	{ "S_CPL5_TXFULL", 8, 1 },
2854	{ "S_PLD2X_TXVALID", 4, 4 },
2855	{ "S_PLD2X_TXAFULL", 0, 4 },
2856	{ "TP_CHDR_CONFIG", 0x240, 0 },
2857	{ "S_CH1HIGH", 24, 8 },
2858	{ "S_CH1LOW", 16, 8 },
2859	{ "S_CH0HIGH", 8, 8 },
2860	{ "S_CH0LOW", 0, 8 },
2861	{ "TP_UTRN_CONFIG", 0x241, 0 },
2862	{ "S_CH2FIFOLIMIT", 16, 8 },
2863	{ "S_CH1FIFOLIMIT", 8, 8 },
2864	{ "S_CH0FIFOLIMIT", 0, 8 },
2865	{ "TP_CDSP_CONFIG", 0x242, 0 },
2866	{ "S_SHAREDRQEN", 31, 1 },
2867	{ "S_ISCSICMDMODE", 28, 1 },
2868	{ "S_IMMEDIATEOP", 20, 4 },
2869	{ "S_IMMEDIATESE", 16, 4 },
2870	{ "S_ATOMICREQOP", 12, 4 },
2871	{ "S_ATOMICRSPOP", 8, 4 },
2872	{ "S_STARTSKIPPLD", 7, 1 },
2873	{ "S_ATOMICCMDEN", 5, 1 },
2874	{ "S_WRITEZEROEN", 4, 1 },
2875	{ "S_WRITEZEROOP", 0, 4 },
2876	{ "TP_CSPI_POWER", 0x243, 0 },
2877	{ "S_GATECHNTX3", 11, 1 },
2878	{ "S_GATECHNTX2", 10, 1 },
2879	{ "S_GATECHNTX1", 9, 1 },
2880	{ "S_GATECHNTX0", 8, 1 },
2881	{ "S_GATECHNRX1", 7, 1 },
2882	{ "S_GATECHNRX0", 6, 1 },
2883	{ "S_SLEEPRDYUTRN", 4, 1 },
2884	{ "S_SLEEPREQUTRN", 0, 1 },
2885	{ "TP_TRC_CONFIG", 0x244, 0 },
2886	{ "S_TRCRR", 1, 1 },
2887	{ "S_TRCCH", 0, 1 },
2888	{ "TP_TAG_CONFIG", 0x245, 0 },
2889	{ "S_ETAGTYPE", 16, 16 },
2890	{ "S_VLANTYPE", 0, 16 },
2891	{ "TP_DBG_CSIDE_PRS", 0x246, 0 },
2892	{ "S_C4TUPBUSY3", 31, 1 },
2893	{ "S_CDBVALID3", 30, 1 },
2894	{ "S_CRXVALID3", 29, 1 },
2895	{ "S_CRXFULL3", 28, 1 },
2896	{ "S_CPRSSTATE3", 24, 4 },
2897	{ "S_C4TUPBUSY2", 23, 1 },
2898	{ "S_CDBVALID2", 22, 1 },
2899	{ "S_CRXVALID2", 21, 1 },
2900	{ "S_CRXFULL2", 20, 1 },
2901	{ "S_CPRSSTATE2", 16, 4 },
2902	{ "S_C4TUPBUSY1", 15, 1 },
2903	{ "S_CDBVALID1", 14, 1 },
2904	{ "S_CRXVALID1", 13, 1 },
2905	{ "S_CRXFULL1", 12, 1 },
2906	{ "S_CPRSSTATE1", 8, 4 },
2907	{ "S_C4TUPBUSY0", 7, 1 },
2908	{ "S_CDBVALID0", 6, 1 },
2909	{ "S_CRXVALID0", 5, 1 },
2910	{ "S_CRXFULL0", 4, 1 },
2911	{ "S_CPRSSTATE0", 0, 4 },
2912	{ "TP_DBG_CSIDE_DEMUX", 0x247, 0 },
2913	{ "S_CARBVALID", 28, 4 },
2914	{ "S_CCPL5DONE", 24, 4 },
2915	{ "S_CTXZEROPDONE", 20, 4 },
2916	{ "S_CPLDDONE", 16, 4 },
2917	{ "S_CTCPOPDONE", 12, 4 },
2918	{ "S_CDBDONE", 8, 4 },
2919	{ "S_CISSFIFODONE", 4, 4 },
2920	{ "S_CTXPKTCSUMDONE", 0, 4 },
2921	{ "TP_DBG_CSIDE_ARBIT", 0x248, 0 },
2922	{ "S_CPLVALID3", 31, 1 },
2923	{ "S_PLDVALID3", 30, 1 },
2924	{ "S_CRCVALID3", 29, 1 },
2925	{ "S_ISSVALID3", 28, 1 },
2926	{ "S_DBVALID3", 27, 1 },
2927	{ "S_CHKVALID3", 26, 1 },
2928	{ "S_ZRPVALID3", 25, 1 },
2929	{ "S_ERRVALID3", 24, 1 },
2930	{ "S_CPLVALID2", 23, 1 },
2931	{ "S_PLDVALID2", 22, 1 },
2932	{ "S_CRCVALID2", 21, 1 },
2933	{ "S_ISSVALID2", 20, 1 },
2934	{ "S_DBVALID2", 19, 1 },
2935	{ "S_CHKVALID2", 18, 1 },
2936	{ "S_ZRPVALID2", 17, 1 },
2937	{ "S_ERRVALID2", 16, 1 },
2938	{ "S_CPLVALID1", 15, 1 },
2939	{ "S_PLDVALID1", 14, 1 },
2940	{ "S_CRCVALID1", 13, 1 },
2941	{ "S_ISSVALID1", 12, 1 },
2942	{ "S_DBVALID1", 11, 1 },
2943	{ "S_CHKVALID1", 10, 1 },
2944	{ "S_ZRPVALID1", 9, 1 },
2945	{ "S_ERRVALID1", 8, 1 },
2946	{ "S_CPLVALID0", 7, 1 },
2947	{ "S_PLDVALID0", 6, 1 },
2948	{ "S_CRCVALID0", 5, 1 },
2949	{ "S_ISSVALID0", 4, 1 },
2950	{ "S_DBVALID0", 3, 1 },
2951	{ "S_CHKVALID0", 2, 1 },
2952	{ "S_ZRPVALID0", 1, 1 },
2953	{ "S_ERRVALID0", 0, 1 },
2954	{ NULL }
2955};
2956
2957static struct cudbg_reg_info t6_tp_pio_regs_24c[] = {
2958	{ "TP_DBG_CSIDE_TRACE_CNT", 0x24a, 0 },
2959	{ "TrcSopCnt", 24, 8 },
2960	{ "TrcEopCnt", 16, 8 },
2961	{ "TrcFltHit", 12, 4 },
2962	{ "TrcRntPkt", 8, 4 },
2963	{ "TrcPktLen", 0, 8 },
2964	{ "TP_DBG_CSIDE_TRACE_RSS", 0x24b, 0 },
2965	{ "TP_VLN_CONFIG", 0x24c, 0 },
2966	{ "EthTypeQinQ", 16, 16 },
2967	{ "EthTypeVlan", 0, 16 },
2968	{ NULL }
2969};
2970
2971static struct cudbg_reg_info t5_tp_pio_regs_230_to_248[] = {
2972	{ "TP_DBG_CSIDE_RX0", 0x230, 0 },
2973	{ "S_CRXSOPCNT", 28, 4 },
2974	{ "S_CRXEOPCNT", 24, 4 },
2975	{ "S_CRXPLDSOPCNT", 20, 4 },
2976	{ "S_CRXPLDEOPCNT", 16, 4 },
2977	{ "S_CRXARBSOPCNT", 12, 4 },
2978	{ "S_CRXARBEOPCNT", 8, 4 },
2979	{ "S_CRXCPLSOPCNT", 4, 4 },
2980	{ "S_CRXCPLEOPCNT", 0, 4 },
2981	{ "TP_DBG_CSIDE_RX1", 0x231, 0 },
2982	{ "S_CRXSOPCNT", 28, 4 },
2983	{ "S_CRXEOPCNT", 24, 4 },
2984	{ "S_CRXPLDSOPCNT", 20, 4 },
2985	{ "S_CRXPLDEOPCNT", 16, 4 },
2986	{ "S_CRXARBSOPCNT", 12, 4 },
2987	{ "S_CRXARBEOPCNT", 8, 4 },
2988	{ "S_CRXCPLSOPCNT", 4, 4 },
2989	{ "S_CRXCPLEOPCNT", 0, 4 },
2990	{ "TP_DBG_CSIDE_RX2", 0x232, 0 },
2991	{ "S_CRXSOPCNT", 28, 4 },
2992	{ "S_CRXEOPCNT", 24, 4 },
2993	{ "S_CRXPLDSOPCNT", 20, 4 },
2994	{ "S_CRXPLDEOPCNT", 16, 4 },
2995	{ "S_CRXARBSOPCNT", 12, 4 },
2996	{ "S_CRXARBEOPCNT", 8, 4 },
2997	{ "S_CRXCPLSOPCNT", 4, 4 },
2998	{ "S_CRXCPLEOPCNT", 0, 4 },
2999	{ "TP_DBG_CSIDE_RX3", 0x233, 0 },
3000	{ "S_CRXSOPCNT", 28, 4 },
3001	{ "S_CRXEOPCNT", 24, 4 },
3002	{ "S_CRXPLDSOPCNT", 20, 4 },
3003	{ "S_CRXPLDEOPCNT", 16, 4 },
3004	{ "S_CRXARBSOPCNT", 12, 4 },
3005	{ "S_CRXARBEOPCNT", 8, 4 },
3006	{ "S_CRXCPLSOPCNT", 4, 4 },
3007	{ "S_CRXCPLEOPCNT", 0, 4 },
3008	{ "TP_DBG_CSIDE_TX0", 0x234, 0 },
3009	{ "S_TXSOPCNT", 28, 4 },
3010	{ "S_TXEOPCNT", 24, 4 },
3011	{ "S_TXPLDSOPCNT", 20, 4 },
3012	{ "S_TXPLDEOPCNT", 16, 4 },
3013	{ "S_TXARBSOPCNT", 12, 4 },
3014	{ "S_TXARBEOPCNT", 8, 4 },
3015	{ "S_TXCPLSOPCNT", 4, 4 },
3016	{ "S_TXCPLEOPCNT", 0, 4 },
3017	{ "TP_DBG_CSIDE_TX1", 0x235, 0 },
3018	{ "S_TXSOPCNT", 28, 4 },
3019	{ "S_TXEOPCNT", 24, 4 },
3020	{ "S_TXPLDSOPCNT", 20, 4 },
3021	{ "S_TXPLDEOPCNT", 16, 4 },
3022	{ "S_TXARBSOPCNT", 12, 4 },
3023	{ "S_TXARBEOPCNT", 8, 4 },
3024	{ "S_TXCPLSOPCNT", 4, 4 },
3025	{ "S_TXCPLEOPCNT", 0, 4 },
3026	{ "TP_DBG_CSIDE_TX2", 0x236, 0 },
3027	{ "S_TXSOPCNT", 28, 4 },
3028	{ "S_TXEOPCNT", 24, 4 },
3029	{ "S_TXPLDSOPCNT", 20, 4 },
3030	{ "S_TXPLDEOPCNT", 16, 4 },
3031	{ "S_TXARBSOPCNT", 12, 4 },
3032	{ "S_TXARBEOPCNT", 8, 4 },
3033	{ "S_TXCPLSOPCNT", 4, 4 },
3034	{ "S_TXCPLEOPCNT", 0, 4 },
3035	{ "TP_DBG_CSIDE_TX3", 0x237, 0 },
3036	{ "S_TXSOPCNT", 28, 4 },
3037	{ "S_TXEOPCNT", 24, 4 },
3038	{ "S_TXPLDSOPCNT", 20, 4 },
3039	{ "S_TXPLDEOPCNT", 16, 4 },
3040	{ "S_TXARBSOPCNT", 12, 4 },
3041	{ "S_TXARBEOPCNT", 8, 4 },
3042	{ "S_TXCPLSOPCNT", 4, 4 },
3043	{ "S_TXCPLEOPCNT", 0, 4 },
3044	{ "TP_DBG_CSIDE_FIFO0", 0x238, 0 },
3045	{ "S_PLD_RXZEROP_SRDY1", 31, 1 },
3046	{ "S_PLD_RXZEROP_DRDY1", 30, 1 },
3047	{ "S_PLD_TXZEROP_SRDY1", 29, 1 },
3048	{ "S_PLD_TXZEROP_DRDY1", 28, 1 },
3049	{ "S_PLD_TX_SRDY1", 27, 1 },
3050	{ "S_PLD_TX_DRDY1", 26, 1 },
3051	{ "S_ERROR_SRDY1", 25, 1 },
3052	{ "S_ERROR_DRDY1", 24, 1 },
3053	{ "S_DB_VLD1", 23, 1 },
3054	{ "S_DB_GT1", 22, 1 },
3055	{ "S_TXVALID1", 21, 1 },
3056	{ "S_TXFULL1", 20, 1 },
3057	{ "S_PLD_TXVALID1", 19 , 1 },
3058	{ "S_PLD_TXFULL1", 18, 1 },
3059	{ "S_CPL5_TXVALID1", 17, 1 },
3060	{ "S_CPL5_TXFULL1", 16, 1 },
3061	{ "S_PLD_RXZEROP_SRDY0", 15, 1 },
3062	{ "S_PLD_RXZEROP_DRDY0", 14, 1 },
3063	{ "S_PLD_TXZEROP_SRDY0", 13, 1 },
3064	{ "S_PLD_TXZEROP_DRDY0", 12, 1 },
3065	{ "S_PLD_TX_SRDY0", 11, 1 },
3066	{ "S_PLD_TX_DRDY0", 10, 1 },
3067	{ "S_ERROR_SRDY0", 9, 1 },
3068	{ "S_ERROR_DRDY0", 8, 1 },
3069	{ "S_DB_VLD0", 7, 1 },
3070	{ "S_DB_GT0", 6, 1 },
3071	{ "S_TXVALID0", 5, 1 },
3072	{ "S_TXFULL0", 4, 1 },
3073	{ "S_PLD_TXVALID0", 3, 1 },
3074	{ "S_PLD_TXFULL0", 2, 1 },
3075	{ "S_CPL5_TXVALID0", 1, 1 },
3076	{ "S_CPL5_TXFULL0", 0, 1 },
3077	{ "TP_DBG_CSIDE_FIFO1", 0x239, 0 },
3078	{ "S_PLD_RXZEROP_SRDY3", 31, 1 },
3079	{ "S_PLD_RXZEROP_DRDY3", 30, 1 },
3080	{ "S_PLD_TXZEROP_SRDY3", 29, 1 },
3081	{ "S_PLD_TXZEROP_DRDY3", 28, 1 },
3082	{ "S_PLD_TX_SRDY3", 27, 1 },
3083	{ "S_PLD_TX_DRDY3", 26, 1 },
3084	{ "S_ERROR_SRDY3", 25, 1 },
3085	{ "S_ERROR_DRDY3", 24, 1 },
3086	{ "S_DB_VLD3", 23, 1 },
3087	{ "S_DB_GT3", 22, 1 },
3088	{ "S_TXVALID3", 21, 1 },
3089	{ "S_TXFULL3", 20, 1 },
3090	{ "S_PLD_TXVALID3", 19 , 1 },
3091	{ "S_PLD_TXFULL3", 18, 1 },
3092	{ "S_CPL5_TXVALID3", 17, 1 },
3093	{ "S_CPL5_TXFULL3", 16, 1 },
3094	{ "S_PLD_RXZEROP_SRDY2", 15, 1 },
3095	{ "S_PLD_RXZEROP_DRDY2", 14, 1 },
3096	{ "S_PLD_TXZEROP_SRDY2", 13, 1 },
3097	{ "S_PLD_TXZEROP_DRDY2", 12, 1 },
3098	{ "S_PLD_TX_SRDY2", 11, 1 },
3099	{ "S_PLD_TX_DRDY2", 10, 1 },
3100	{ "S_ERROR_SRDY2", 9, 1 },
3101	{ "S_ERROR_DRDY2", 8, 1 },
3102	{ "S_DB_VLD2", 7, 1 },
3103	{ "S_DB_GT2", 6, 1 },
3104	{ "S_TXVALID2", 5, 1 },
3105	{ "S_TXFULL2", 4, 1 },
3106	{ "S_PLD_TXVALID2", 3, 1 },
3107	{ "S_PLD_TXFULL2", 2, 1 },
3108	{ "S_CPL5_TXVALID2", 1, 1 },
3109	{ "S_CPL5_TXFULL2", 0, 1 },
3110	{ "TP_DBG_CSIDE_DISP0", 0x23A, 0 },
3111	{ "S_TXFULL", 31, 1 },
3112	{ "S_STATE", 28, 3 },
3113	{ "S_CPL5RXVALID", 27, 1 },
3114	{ "S_CPL5RXFULL", 26, 1 },
3115	{ "S_PLD_RXZEROP_SRDY", 25, 1 },
3116	{ "S_PLD_RXZEROP", 24, 1 },
3117	{ "S_PLD2XRXVALID", 23, 1 },
3118	{ "S_DDP_SRDY", 22, 1 },
3119	{ "S_DDP_DRDY", 21, 1 },
3120	{ "S_DDPSTATE", 16, 5 },
3121	{ "S_DDPMSGCODE", 12, 4 },
3122	{ "S_CPL5SOCPCNT", 8, 4 },
3123	{ "S_PLDRXZEROPCNT", 4, 4 },
3124	{ "S_TXFRMERR2", 3, 1 },
3125	{ "S_TXFRMERR1", 2, 1 },
3126	{ "S_TXVALID2X", 1, 1 },
3127	{ "S_TXFULL2X", 0, 1 },
3128	{ "TP_DBG_CSIDE_DISP1", 0x23B, 0 },
3129	{ "S_TXFULL", 31, 1 },
3130	{ "S_STATE", 28, 3 },
3131	{ "S_CPL5RXVALID", 27, 1 },
3132	{ "S_CPL5RXFULL", 26, 1 },
3133	{ "S_PLD_RXZEROP_SRDY", 25, 1 },
3134	{ "S_PLD_RXZEROP", 24, 1 },
3135	{ "S_PLD2XRXVALID", 23, 1 },
3136	{ "S_DDP_SRDY", 22, 1 },
3137	{ "S_DDP_DRDY", 21, 1 },
3138	{ "S_DDPSTATE", 16, 5 },
3139	{ "S_DDPMSGCODE", 12, 4 },
3140	{ "S_CPL5SOCPCNT", 8, 4 },
3141	{ "S_PLDRXZEROPCNT", 4, 4 },
3142	{ "S_TXFRMERR2", 3, 1 },
3143	{ "S_TXFRMERR1", 2, 1 },
3144	{ "S_TXVALID2X", 1, 1 },
3145	{ "S_TXFULL2X", 0, 1 },
3146	{ "TP_DBG_CSIDE_DDP0", 0x23C, 0 },
3147	{ "S_DDPMSGLATEST7", 28, 4 },
3148	{ "S_DDPMSGLATEST6", 24, 4 },
3149	{ "S_DDPMSGLATEST5", 20, 4 },
3150	{ "S_DDPMSGLATEST4", 16, 4 },
3151	{ "S_DDPMSGLATEST3", 12, 4 },
3152	{ "S_DDPMSGLATEST2", 8, 4 },
3153	{ "S_DDPMSGLATEST1", 4, 4 },
3154	{ "S_DDPMSGLATEST0", 0, 4 },
3155	{ "TP_DBG_CSIDE_DDP1", 0x23D, 0 },
3156	{ "S_DDPMSGLATEST7", 28, 4 },
3157	{ "S_DDPMSGLATEST6", 24, 4 },
3158	{ "S_DDPMSGLATEST5", 20, 4 },
3159	{ "S_DDPMSGLATEST4", 16, 4 },
3160	{ "S_DDPMSGLATEST3", 12, 4 },
3161	{ "S_DDPMSGLATEST2", 8, 4 },
3162	{ "S_DDPMSGLATEST1", 4, 4 },
3163	{ "S_DDPMSGLATEST0", 0, 4 },
3164	{ "TP_DBG_CSIDE_FRM", 0x23E, 0 },
3165	{ "S_CRX2XERROR", 28, 4 },
3166	{ "S_CPLDTX2XERROR", 24, 4 },
3167	{ "S_CTXERROR", 22, 2 },
3168	{ "S_CPLDRXERROR", 20, 2 },
3169	{ "S_CPLRXERROR", 18, 2 },
3170	{ "S_CPLTXERROR", 16, 2 },
3171	{ "S_CPRSERROR", 0, 4 },
3172	{ "TP_DBG_CSIDE_INT", 0x23F, 0 },
3173	{ "S_CRXVALID2X", 28, 4 },
3174	{ "S_CRXAFULL2X", 24, 4 },
3175	{ "S_CTXVALID2X", 22, 2 },
3176	{ "S_CTXAFULL2X", 20, 2 },
3177	{ "S_PLD2X_RXVALID", 18, 2 },
3178	{ "S_PLD2X_RXAFULL", 16, 2 },
3179	{ "S_CSIDE_DDP_VALID", 14, 2 },
3180	{ "S_DDP_AFULL", 12, 2 },
3181	{ "S_TRC_RXVALID", 11, 1 },
3182	{ "S_TRC_RXFULL", 10, 1 },
3183	{ "S_CPL5_TXVALID", 9, 1 },
3184	{ "S_CPL5_TXFULL", 8, 1 },
3185	{ "S_PLD2X_TXVALID", 4, 4 },
3186	{ "S_PLD2X_TXAFULL", 0, 4 },
3187	{ "TP_CHDR_CONFIG", 0x240, 0 },
3188	{ "S_CH1HIGH", 24, 8 },
3189	{ "S_CH1LOW", 16, 8 },
3190	{ "S_CH0HIGH", 8, 8 },
3191	{ "S_CH0LOW", 0, 8 },
3192	{ "TP_UTRN_CONFIG", 0x241, 0 },
3193	{ "S_CH2FIFOLIMIT", 16, 8 },
3194	{ "S_CH1FIFOLIMIT", 8, 8 },
3195	{ "S_CH0FIFOLIMIT", 0, 8 },
3196	{ "TP_CDSP_CONFIG", 0x242, 0 },
3197	{ "S_IMMEDIATEOP", 20, 4 },
3198	{ "S_IMMEDIATESE", 16, 4 },
3199	{ "S_ATOMICREQOP", 12, 4 },
3200	{ "S_ATOMICRSPOP", 8, 4 },
3201	{ "S_STARTSKIPPLD", 7, 1 },
3202	{ "S_ATOMICCMDEN", 5, 1 },
3203	{ "S_WRITEZEROEN", 4, 1 },
3204	{ "S_WRITEZEROOP", 0, 4 },
3205	{ "TP_CSPI_POWER", 0x243, 0 },
3206	{ "S_GATECHNTX3", 11, 1 },
3207	{ "S_GATECHNTX2", 10, 1 },
3208	{ "S_GATECHNTX1", 9, 1 },
3209	{ "S_GATECHNTX0", 8, 1 },
3210	{ "S_GATECHNRX1", 7, 1 },
3211	{ "S_GATECHNRX0", 6, 1 },
3212	{ "S_SLEEPRDYUTRN", 4, 1 },
3213	{ "S_SLEEPREQUTRN", 0, 1 },
3214	{ "TP_TRC_CONFIG", 0x244, 0 },
3215	{ "S_TRCRR", 1, 1 },
3216	{ "S_TRCCH", 0, 1 },
3217	{ "TP_TAG_CONFIG", 0x245, 0 },
3218	{ "S_ETAGTYPE", 16, 16 },
3219	{ "S_VLANTYPE", 0, 16 },
3220	{ "TP_DBG_CSIDE_PRS", 0x246, 0 },
3221	{ "S_C4TUPBUSY3", 31, 1 },
3222	{ "S_CDBVALID3", 30, 1 },
3223	{ "S_CRXVALID3", 29, 1 },
3224	{ "S_CRXFULL3", 28, 1 },
3225	{ "S_CPRSSTATE3", 24, 4 },
3226	{ "S_C4TUPBUSY2", 23, 1 },
3227	{ "S_CDBVALID2", 22, 1 },
3228	{ "S_CRXVALID2", 21, 1 },
3229	{ "S_CRXFULL2", 20, 1 },
3230	{ "S_CPRSSTATE2", 16, 4 },
3231	{ "S_C4TUPBUSY1", 15, 1 },
3232	{ "S_CDBVALID1", 14, 1 },
3233	{ "S_CRXVALID1", 13, 1 },
3234	{ "S_CRXFULL1", 12, 1 },
3235	{ "S_CPRSSTATE1", 8, 4 },
3236	{ "S_C4TUPBUSY0", 7, 1 },
3237	{ "S_CDBVALID0", 6, 1 },
3238	{ "S_CRXVALID0", 5, 1 },
3239	{ "S_CRXFULL0", 4, 1 },
3240	{ "S_CPRSSTATE0", 0, 4 },
3241	{ "TP_DBG_CSIDE_DEMUX", 0x247, 0 },
3242	{ "S_CARBVALID", 28, 4 },
3243	{ "S_CCPL5DONE", 24, 4 },
3244	{ "S_CTXZEROPDONE", 20, 4 },
3245	{ "S_CPLDDONE", 16, 4 },
3246	{ "S_CTCPOPDONE", 12, 4 },
3247	{ "S_CDBDONE", 8, 4 },
3248	{ "S_CISSFIFODONE", 4, 4 },
3249	{ "S_CTXPKTCSUMDONE", 0, 4 },
3250	{ "TP_DBG_CSIDE_ARBIT", 0x248, 0 },
3251	{ "S_CPLVALID3", 31, 1 },
3252	{ "S_PLDVALID3", 30, 1 },
3253	{ "S_CRCVALID3", 29, 1 },
3254	{ "S_ISSVALID3", 28, 1 },
3255	{ "S_DBVALID3", 27, 1 },
3256	{ "S_CHKVALID3", 26, 1 },
3257	{ "S_ZRPVALID3", 25, 1 },
3258	{ "S_ERRVALID3", 24, 1 },
3259	{ "S_CPLVALID2", 23, 1 },
3260	{ "S_PLDVALID2", 22, 1 },
3261	{ "S_CRCVALID2", 21, 1 },
3262	{ "S_ISSVALID2", 20, 1 },
3263	{ "S_DBVALID2", 19, 1 },
3264	{ "S_CHKVALID2", 18, 1 },
3265	{ "S_ZRPVALID2", 17, 1 },
3266	{ "S_ERRVALID2", 16, 1 },
3267	{ "S_CPLVALID1", 15, 1 },
3268	{ "S_PLDVALID1", 14, 1 },
3269	{ "S_CRCVALID1", 13, 1 },
3270	{ "S_ISSVALID1", 12, 1 },
3271	{ "S_DBVALID1", 11, 1 },
3272	{ "S_CHKVALID1", 10, 1 },
3273	{ "S_ZRPVALID1", 9, 1 },
3274	{ "S_ERRVALID1", 8, 1 },
3275	{ "S_CPLVALID0", 7, 1 },
3276	{ "S_PLDVALID0", 6, 1 },
3277	{ "S_CRCVALID0", 5, 1 },
3278	{ "S_ISSVALID0", 4, 1 },
3279	{ "S_DBVALID0", 3, 1 },
3280	{ "S_CHKVALID0", 2, 1 },
3281	{ "S_ZRPVALID0", 1, 1 },
3282	{ "S_ERRVALID0", 0, 1 },
3283	{ NULL }
3284};
3285
3286static struct cudbg_reg_info t6_tp_pio_regs_8c0[] = {
3287	{ "TP_FIFO_CONFIG", 0x8C0, 0 },
3288	{ "S_CH1_OUTPUT", 27, 5 },
3289	{ "S_CH2_OUTPUT", 22, 5 },
3290	{ "S_RESERVED", 17, 5 },
3291	{ "S_STROBE1", 16, 1 },
3292	{ "S_CH1_INPUT", 11, 5 },
3293	{ "S_CH2_INPUT", 6, 5 },
3294	{ "S_CH3_INPUT", 1, 5 },
3295	{ "S_STROBE0", 0, 1 },
3296	{ NULL }
3297};
3298
3299static struct cudbg_reg_info t5_tp_pio_regs_8c0[] = {
3300	{ "TP_FIFO_CONFIG", 0x8C0, 0 },
3301	{ "S_CH1_OUTPUT", 27, 5 },
3302	{ "S_CH2_OUTPUT", 22, 5 },
3303	{ "S_RESERVED", 17, 5 },
3304	{ "S_STROBE1", 16, 1 },
3305	{ "S_CH1_INPUT", 11, 5 },
3306	{ "S_CH2_INPUT", 6, 5 },
3307	{ "S_CH3_INPUT", 1, 5 },
3308	{ "S_STROBE0", 0, 1 },
3309	{ NULL }
3310};
3311
3312static struct cudbg_reg_info t5_pcie_pdbg_regs_00_to_20[] = {
3313	{ "PCIE_PDEBUG_REG_0x0", 0x00, 0 },
3314	{ "PCIE_PDEBUG_REG_0x1", 0x01, 0 },
3315	{ "PCIE_PDEBUG_REG_0x2", 0X02, 0 },
3316	{ "tagq_ch0_tags_used", 11, 8 },
3317	{ "tagq_ch0_data_empty", 10, 1 },
3318	{ "rdq_ch0_req_empty", 9, 1 },
3319	{ "req_ctl_rd_ch0_wait_for_tagtq", 8, 1 },
3320	{ "req_ctl_rd_ch0_wait_for_cmd", 7, 1 },
3321	{ "req_ctl_rd_ch0_wait_for_data_mem", 6, 1 },
3322	{ "req_ctl_rd_ch0_wait_for_rdq", 5, 1 },
3323	{ "req_ctl_rd_ch0_wait_for_txn_disable_fifo", 4, 1 },
3324	{ "req_ctl_rd_ch0_exit_bot_vld_started", 3, 1 },
3325	{ "req_ctl_rd_ch0_exit_top_vld_started", 2, 1 },
3326	{ "req_ctl_rd_ch0_wait_for_pause", 1, 1 },
3327	{ "req_ctl_rd_ch0_wait_for_fifo_data", 0, 1 },
3328	{ "PCIE_PDEBUG_REG_0x3", 0X03, 0 },
3329	{ "tagq_ch1_tags_used", 11, 8 },
3330	{ "req_ch1_data_empty", 10, 1 },
3331	{ "rdq_ch1_req_empty", 9, 1 },
3332	{ "req_ctl_rd_ch1_wait_for_tagtq", 8, 1 },
3333	{ "req_ctl_rd_ch1_wait_for_cmd", 7, 1 },
3334	{ "req_ctl_rd_ch1_wait_for_data_mem", 6, 1 },
3335	{ "req_ctl_rd_ch1_wait_for_rdq", 5, 1 },
3336	{ "req_ctl_rd_ch1_wait_for_txn_disable_fifo", 4, 1 },
3337	{ "req_ctl_rd_ch1_exit_bot_vld_started", 3, 1 },
3338	{ "req_ctl_rd_ch1_exit_top_vld_started", 2, 1 },
3339	{ "req_ctl_rd_ch1_wait_for_pause", 1, 1 },
3340	{ "req_ctl_rd_ch1_wait_for_fifo_data", 0, 1 },
3341	{ "PCIE_PDEBUG_REG_0x4", 0X04, 0 },
3342	{ "tagq_ch2_tags_used", 11, 8 },
3343	{ "req_ch2_data_empty", 10, 1 },
3344	{ "rdq_ch2_req_empty", 9, 1 },
3345	{ "req_ctl_rd_ch2_wait_for_tagtq", 8, 1 },
3346	{ "req_ctl_rd_ch2_wait_for_cmd", 7, 1 },
3347	{ "req_ctl_rd_ch2_wait_for_data_mem", 6, 1 },
3348	{ "req_ctl_rd_ch2_wait_for_rdq", 5, 1 },
3349	{ "req_ctl_rd_ch2_wait_for_txn_disable_fifo", 4, 1 },
3350	{ "req_ctl_rd_ch2_exit_bot_vld_started", 3, 1 },
3351	{ "req_ctl_rd_ch2_exit_top_vld_started", 2, 1 },
3352	{ "req_ctl_rd_ch2_wait_for_pause", 1, 1},
3353	{ "req_ctl_rd_ch2_wait_for_fifo_data", 0, 1},
3354	{ "PCIE_PDEBUG_REG_0x5", 0x05, 0 },
3355	{ "tagq_ch3_tags_used", 11, 8 },
3356	{ "req_ch3_data_empty", 10, 1 },
3357	{ "rdq_ch3_req_empty", 9, 1 },
3358	{ "req_ctl_rd_ch3_wait_for_tagtq", 8, 1 },
3359	{ "req_ctl_rd_ch3_wait_for_cmd", 7, 1 },
3360	{ "req_ctl_rd_ch3_wait_for_data_mem", 6, 1 },
3361	{ "req_ctl_rd_ch3_wait_for_rdq", 5, 1 },
3362	{ "req_ctl_rd_ch3_wait_for_txn_disable_fifo", 4, 1 },
3363	{ "req_ctl_rd_ch3_exit_bot_vld_started", 3, 1 },
3364	{ "req_ctl_rd_ch3_exit_top_vld_started", 2, 1 },
3365	{ "req_ctl_rd_ch3_wait_for_pause", 1, 1 },
3366	{ "req_ctl_rd_ch3_wait_for_fifo_data", 0, 1 },
3367	{ "PCIE_PDEBUG_REG_0x6", 0x06, 0 },
3368	{ "tagq_ch4_tags_used", 11, 8 },
3369	{ "req_ch4_data_empty", 10, 1 },
3370	{ "rdq_ch4_req_empty", 9, 1 },
3371	{ "req_ctl_rd_ch4_wait_for_tagtq", 8, 1 },
3372	{ "req_ctl_rd_ch4_wait_for_cmd", 7, 1 },
3373	{ "req_ctl_rd_ch4_wait_for_data_mem", 6, 1 },
3374	{ "req_ctl_rd_ch4_wait_for_rdq", 5, 1 },
3375	{ "req_ctl_rd_ch4_wait_for_txn_disable_fifo", 4, 1 },
3376	{ "req_ctl_rd_ch4_exit_bot_vld_started", 3, 1 },
3377	{ "req_ctl_rd_ch4_exit_top_vld_started", 2, 1 },
3378	{ "req_ctl_rd_ch4_wait_for_pause", 1, 1 },
3379	{ "req_ctl_rd_ch4_wait_for_fifo_data", 0, 1 },
3380	{ "PCIE_PDEBUG_REG_0x7", 0x07, 0 },
3381	{ "tagq_ch5_tags_used", 11, 8 },
3382	{ "req_ch5_data_empty", 10, 1 },
3383	{ "rdq_ch5_req_empty", 9, 1 },
3384	{ "req_ctl_rd_ch5_wait_for_tagtq", 8, 1 },
3385	{ "req_ctl_rd_ch5_wait_for_cmd", 7, 1 },
3386	{ "req_ctl_rd_ch5_wait_for_data_mem", 6, 1 },
3387	{ "req_ctl_rd_ch5_wait_for_rdq", 5, 1 },
3388	{ "req_ctl_rd_ch5_wait_for_txn_disable_fifo", 4, 1 },
3389	{ "req_ctl_rd_ch5_exit_bot_vld_started", 3, 1 },
3390	{ "req_ctl_rd_ch5_exit_top_vld_started", 2, 1 },
3391	{ "req_ctl_rd_ch5_wait_for_pause", 1, 1 },
3392	{ "req_ctl_rd_ch5_wait_for_fifo_data", 0, 1 },
3393	{ "PCIE_PDEBUG_REG_0x8", 0x08, 0 },
3394	{ "tagq_ch6_tags_used", 11, 8 },
3395	{ "req_ch6_data_empty", 10, 1 },
3396	{ "rdq_ch6_req_empty", 9, 1 },
3397	{ "req_ctl_rd_ch6_wait_for_tagtq", 8, 1 },
3398	{ "req_ctl_rd_ch6_wait_for_cmd", 7, 1 },
3399	{ "req_ctl_rd_ch6_wait_for_data_mem", 6, 1 },
3400	{ "req_ctl_rd_ch6_wait_for_rdq", 5, 1 },
3401	{ "req_ctl_rd_ch6_wait_for_txn_disable_fifo", 4, 1 },
3402	{ "req_ctl_rd_ch6_exit_bot_vld_started", 3, 1 },
3403	{ "req_ctl_rd_ch6_exit_top_vld_started", 2, 1 },
3404	{ "req_ctl_rd_ch6_wait_for_pause", 1, 1 },
3405	{ "req_ctl_rd_ch6_wait_for_fifo_data", 0, 1 },
3406	{ "PCIE_PDEBUG_REG_0x9", 0x09, 0 },
3407	{ "tagq_ch7_tags_used", 11, 8 },
3408	{ "req_ch7_data_empty", 10, 1 },
3409	{ "rdq_ch7_req_empty", 9, 1 },
3410	{ "req_ctl_rd_ch7_wait_for_tagtq", 8, 1 },
3411	{ "req_ctl_rd_ch7_wait_for_cmd", 7, 1 },
3412	{ "req_ctl_rd_ch7_wait_for_data_mem", 6, 1 },
3413	{ "req_ctl_rd_ch7_wait_for_rdq", 5, 1 },
3414	{ "req_ctl_rd_ch7_wait_for_txn_disable_fifo", 4, 1 },
3415	{ "req_ctl_rd_ch7_exit_bot_vld_started", 3, 1 },
3416	{ "req_ctl_rd_ch7_exit_top_vld_started", 2, 1 },
3417	{ "req_ctl_rd_ch7_wait_for_pause", 1, 1 },
3418	{ "req_ctl_rd_ch7_wait_for_fifo_data", 0, 1 },
3419	{ "PCIE_PDEBUG_REG_0xa", 0x0a, 0 },
3420	{ "req_ctl_rd_ch0_wait_for_seqnum", 27, 1 },
3421	{ "req_ctl_wr_ch0_seqnum", 19, 8 },
3422	{ "req_ctl_rd_ch0_seqnum", 11, 8 },
3423	{ "req_ctl_wr_ch0_wait_for_si_fifo", 4, 1 },
3424	{ "req_ctl_wr_ch0_exit_bot_vld_started", 3, 1 },
3425	{ "req_ctl_wr_ch0_exit_top_vld_started", 2, 1 },
3426	{ "req_ctl_wr_ch0_wait_for_pause", 1, 1 },
3427	{ "req_ctl_wr_ch0_wait_for_fifo_data", 0, 1 },
3428	{ "PCIE_PDEBUG_REG_0xb", 0x0b, 0 },
3429	{ "req_ctl_rd_ch1_wait_for_seqnum", 27, 1 },
3430	{ "req_ctl_wr_ch1_seqnum", 19, 8 },
3431	{ "req_ctl_rd_ch1_seqnum", 11, 8 },
3432	{ "req_ctl_wr_ch1_wait_for_si_fifo", 4, 1 },
3433	{ "req_ctl_wr_ch1_exit_bot_vld_started", 3, 1 },
3434	{ "req_ctl_wr_ch1_exit_top_vld_started", 2, 1 },
3435	{ "req_ctl_wr_ch1_wait_for_pause", 1, 1 },
3436	{ "req_ctl_wr_ch1_wait_for_fifo_data", 0, 1 },
3437	{ "PCIE_PDEBUG_REG_0xc", 0x0c, 0 },
3438	{ "req_ctl_rd_ch2_wait_for_seqnum", 27, 27},
3439	{ "req_ctl_wr_ch2_seqnum", 19, 8 },
3440	{ "req_ctl_rd_ch2_seqnum", 11, 8 },
3441	{ "req_ctl_wr_ch2_wait_for_si_fifo", 4, 1 },
3442	{ "req_ctl_wr_ch2_exit_bot_vld_started", 3, 1 },
3443	{ "req_ctl_wr_ch2_exit_top_vld_started", 2, 1 },
3444	{ "req_ctl_wr_ch2_wait_for_pause", 1, 1 },
3445	{ "req_ctl_wr_ch2_wait_for_fifo_data", 0, 1 },
3446	{ "PCIE_PDEBUG_REG_0xd", 0x0d, 0 },
3447	{ "req_ctl_rd_ch3_wait_for_seqnum", 27, 1 },
3448	{ "req_ctl_wr_ch3_seqnum", 19, 8 },
3449	{ "req_ctl_rd_ch3_seqnum", 11, 8 },
3450	{ "req_ctl_wr_ch3_wait_for_si_fifo", 4, 1 },
3451	{ "req_ctl_wr_ch3_exit_bot_vld_started", 3, 1 },
3452	{ "req_ctl_wr_ch3_exit_top_vld_started", 2, 1 },
3453	{ "req_ctl_wr_ch3_wait_for_pause", 1, 1 },
3454	{ "req_ctl_wr_ch3_wait_for_fifo_data", 0, 1 },
3455	{ "PCIE_PDEBUG_REG_0xe", 0x0e, 0 },
3456	{ "req_ctl_rd_ch4_wait_for_seqnum", 27, 1 },
3457	{ "req_ctl_wr_ch4_seqnum", 19, 8 },
3458	{ "req_ctl_rd_ch4_seqnum", 11, 8 },
3459	{ "req_ctl_wr_ch4_wait_for_si_fifo", 4, 1 },
3460	{ "req_ctl_wr_ch4_exit_bot_vld_started", 3, 1 },
3461	{ "req_ctl_wr_ch4_exit_top_vld_started", 2, 1 },
3462	{ "req_ctl_wr_ch4_wait_for_pause", 1, 1 },
3463	{ "req_ctl_wr_ch4_wait_for_fifo_data", 0, 1 },
3464	{ "PCIE_PDEBUG_REG_0xf", 0xf, 0 },
3465	{ "PCIE_PDEBUG_REG_0x10", 0x10, 0 },
3466	{ "pipe0_tx3_datak_0", 31, 1 },
3467	{ "pipe0_tx3_data_6_0", 24, 7 },
3468	{ "pipe0_tx2_data_7_0", 16, 8 },
3469	{ "pipe0_tx1_data_7_0", 8 , 8 },
3470	{ "pipe0_tx0_datak_0", 7, 1 },
3471	{ "pipe0_tx0_data_6_0", 0 , 7 },
3472	{ "PCIE_PDEBUG_REG_0x11", 0x11, 0 },
3473	{ "pipe0_tx3_datak_1", 31, 1 },
3474	{ "pipe0_tx3_data_14_8", 24, 7 },
3475	{ "pipe0_tx2_data_15_8", 16, 8 },
3476	{ "pipe0_tx1_data_15_8", 8, 8 },
3477	{ "pipe0_tx0_datak_1", 7, 1 },
3478	{ "pipe0_tx0_data_14_8", 0, 7 },
3479	{ "PCIE_PDEBUG_REG_0x12", 0x12, 0 },
3480	{ "pipe0_tx7_datak_0", 31, 1 },
3481	{ "pipe0_tx7_data_6_0", 24, 7 },
3482	{ "pipe0_tx6_data_7_0", 16, 8 },
3483	{ "pipe0_tx5_data_7_0", 8, 8 },
3484	{ "pipe0_tx4_datak_0", 7, 1 },
3485	{ "pipe0_tx4_data_6_0", 0, 7 },
3486	{ "PCIE_PDEBUG_REG_0x13", 0x13, 0 },
3487	{ "pipe0_tx7_datak_1", 31, 1 },
3488	{ "pipe0_tx7_data_14_8", 24, 7 },
3489	{ "pipe0_tx6_data_15_8", 16, 8 },
3490	{ "pipe0_tx5_data_15_8", 8, 8 },
3491	{ "pipe0_tx4_datak_1", 7, 1 },
3492	{ "pipe0_tx4_data_14_8", 0, 7 },
3493	{ "PCIE_PDEBUG_REG_0x14", 0x14, 0 },
3494	{ "pipe0_rx3_valid_14", 31, 1 },
3495	{ "pipe0_rx3_valid2_14", 24, 7 },
3496	{ "pipe0_rx2_valid_14", 16, 8 },
3497	{ "pipe0_rx1_valid_14", 8, 8 },
3498	{ "pipe0_rx0_valid_14", 7, 1 },
3499	{ "pipe0_rx0_valid2_14", 0, 7 },
3500	{ "PCIE_PDEBUG_REG_0x15", 0x15, 0 },
3501	{ "pipe0_rx3_valid_15", 31, 1 },
3502	{ "pipe0_rx3_valid2_15", 24, 7 },
3503	{ "pipe0_rx2_valid_15", 16, 8 },
3504	{ "pipe0_rx1_valid_15", 8, 8 },
3505	{ "pipe0_rx0_valid_15", 7, 1 },
3506	{ "pipe0_rx0_valid2+15", 0, 7 },
3507	{ "PCIE_PDEBUG_REG_0x16", 0x16, 0 },
3508	{ "pipe0_rx7_valid_16", 31, 1 },
3509	{ "pipe0_rx7_valid2_16", 24, 7 },
3510	{ "pipe0_rx6_valid_16", 16, 8 },
3511	{ "pipe0_rx5_valid_16", 8, 8 },
3512	{ "pipe0_rx4_valid_16", 7, 1 },
3513	{ "pipe0_rx4_valid2_16", 0, 7 },
3514	{ "PCIE_PDEBUG_REG_0x17", 0x17, 0 },
3515	{ "pipe0_rx7_valid_17", 31, 1 },
3516	{ "pipe0_rx7_valid2_17", 24, 7 },
3517	{ "pipe0_rx6_valid_17", 16, 8 },
3518	{ "pipe0_rx5_valid_17", 8, 8 },
3519	{ "pipe0_rx4_valid_17", 7, 1 },
3520	{ "pipe0_rx4_valid2_17", 0, 7 },
3521	{ "PCIE_PDEBUG_REG_0x18", 0x18, 0 },
3522	{ "pipe0_rx7_polarity", 31, 1 },
3523	{ "pipe0_rx7_status", 28, 3 },
3524	{ "pipe0_rx6_polarity", 27, 1 },
3525	{ "pipe0_rx6_status", 24 , 3 },
3526	{ "pipe0_rx5_polarity", 23, 1 },
3527	{ "pipe0_rx5_status", 20, 3 },
3528	{ "pipe0_rx4_polarity", 19, 1 },
3529	{ "pipe0_rx4_status", 16, 3 },
3530	{ "pipe0_rx3_polarity", 15, 1 },
3531	{ "pipe0_rx3_status", 12, 3 },
3532	{ "pipe0_rx2_polarity", 11, 1 },
3533	{ "pipe0_rx2_status", 8, 3 },
3534	{ "pipe0_rx1_polarity", 7, 1 },
3535	{ "pipe0_rx1_status", 4, 3 },
3536	{ "pipe0_rx0_polarity", 3, 1 },
3537	{ "pipe0_rx0_status", 0, 3 },
3538	{ "PCIE_PDEBUG_REG_0x19", 0x19, 0 },
3539	{ "pipe0_tx7_compliance", 31, 1 },
3540	{ "pipe0_tx6_compliance", 30, 1 },
3541	{ "pipe0_tx5_compliance", 29, 1 },
3542	{ "pipe0_tx4_compliance", 28, 1 },
3543	{ "pipe0_tx3_compliance", 27, 1 },
3544	{ "pipe0_tx2_compliance", 26, 1 },
3545	{ "pipe0_tx1_compliance", 25, 1 },
3546	{ "pipe0_tx0_compliance", 24, 1 },
3547	{ "pipe0_tx7_elecidle", 23, 1 },
3548	{ "pipe0_tx6_elecidle", 22, 1 },
3549	{ "pipe0_tx5_elecidle", 21, 1 },
3550	{ "pipe0_tx4_elecidle", 20, 1 },
3551	{ "pipe0_tx3_elecidle", 19, 1 },
3552	{ "pipe0_tx2_elecidle", 18, 1 },
3553	{ "pipe0_tx1_elecidle", 17, 1 },
3554	{ "pipe0_tx0_elecidle", 16, 1 },
3555	{ "pipe0_rx7_polarity_19", 15, 1 },
3556	{ "pipe0_rx6_polarity_19", 14, 1 },
3557	{ "pipe0_rx5_polarity_19", 13, 1 },
3558	{ "pipe0_rx4_polarity_19", 12, 1 },
3559	{ "pipe0_rx3_polarity_19", 11, 1 },
3560	{ "pipe0_rx2_polarity_19", 10, 1 },
3561	{ "pipe0_rx1_polarity_19", 9, 1 },
3562	{ "pipe0_rx0_polarity_19", 8, 1 },
3563	{ "pipe0_rx7_elecidle", 7, 1 },
3564	{ "pipe0_rx6_elecidle", 6, 1 },
3565	{ "pipe0_rx5_elecidle", 5, 1 },
3566	{ "pipe0_rx4_elecidle", 4, 1 },
3567	{ "pipe0_rx3_elecidle", 3, 1 },
3568	{ "pipe0_rx2_elecidle", 2, 1 },
3569	{ "pipe0_rx1_elecidle", 1, 1 },
3570	{ "pipe0_rx0_elecidle", 0, 1 },
3571	{ "PCIE_PDEBUG_REG_0x1a", 0x1a , 0 },
3572	{ "reserved", 22 , 10 },
3573	{ "pipe0_reset_n", 21, 1 },
3574	{ "pcs_common_clocks", 20, 1 },
3575	{ "pcs_clk_req", 19, 1 },
3576	{ "pipe_clkreq_n", 18, 1 },
3577	{ "mac_clkreq_n_to_mux", 17, 1 },
3578	{ "pipe0_tx2rx_loopbk", 16, 1 },
3579	{ "pipe0_tx_swing", 15, 1 },
3580	{ "pipe0_tx_margin", 12, 3 },
3581	{ "pipe0_tx_deemph", 11, 1 },
3582	{ "pipe0_tx_detectrx", 10, 1 },
3583	{ "pipe0_powerdown", 8, 2 },
3584	{ "phy_mac_phystatus", 0, 8 },
3585	{ "PCIE_PDEBUG_REG_0x1b", 0x1b, 0 },
3586	{ "pipe0_rx7_eq_in_prog", 31, 1 },
3587	{ "pipe0_rx7_eq_invld_req", 30, 1 },
3588	{ "pipe0_rx7_syncheader", 28, 2 },
3589	{ "pipe0_rx6_eq_in_prog", 27, 1 },
3590	{ "pipe0_rx6_eq_invld_req", 26, 1 },
3591	{ "pipe0_rx6_syncheader", 24, 2 },
3592	{ "pipe0_rx5_eq_in_prog", 23, 1 },
3593	{ "pipe0_rx5_eq_invld_req", 22, 1 },
3594	{ "pipe0_rx5_syncheader", 20, 2 },
3595	{ "pipe0_rx4_eq_in_prog", 19, 1 },
3596	{ "pipe0_rx4_eq_invld_req", 18, 1 },
3597	{ "pipe0_rx4_syncheader", 16, 2 },
3598	{ "pipe0_rx3_eq_in_prog", 15, 1 },
3599	{ "pipe0_rx3_eq_invld_req", 14, 1 },
3600	{ "pipe0_rx3_syncheader", 12, 2 },
3601	{ "pipe0_rx2_eq_in_prog", 11, 1 },
3602	{ "pipe0_rx2_eq_invld_req", 10, 1 },
3603	{ "pipe0_rx2_syncheader", 8, 2 },
3604	{ "pipe0_rx1_eq_in_prog", 7, 1 },
3605	{ "pipe0_rx1_eq_invld_req", 6, 1 },
3606	{ "pipe0_rx1_syncheader", 4, 2 },
3607	{ "pipe0_rx0_eq_in_prog", 3, 1 },
3608	{ "pipe0_rx0_eq_invld_req", 2, 1 },
3609	{ "pipe0_rx0_syncheader", 0, 2 },
3610	{ "PCIE_PDEBUG_REG_0x1c", 0x1c, 0 },
3611	{ "SI_ReqVFID", 24, 8 },
3612	{ "SI_ReqVec", 13, 11 },
3613	{ "SI_ReqTCVal", 10, 3 },
3614	{ "SI_ReqRdy", 9, 1 },
3615	{ "SI_ReqVld", 8, 1 },
3616	{ "AI", 0, 8 },
3617	{ "PCIE_PDEBUG_REG_0x1d", 0x1d, 0 },
3618	{ "GntSI", 31, 1 },
3619	{ "DropIntForFLR", 30, 1 },
3620	{ "SmArb", 27, 3 },
3621	{ "SmDefr", 24, 3 },
3622	{ "sys_int", 16, 8 },
3623	{ "CFG_INTXClr", 8, 8 },
3624	{ "PIO_INTXClr", 0, 8 },
3625	{ "PCIE_PDEBUG_REG_0x1e", 0x1e, 0 },
3626	{ "PLI_TABDatWrEn", 31, 1 },
3627	{ "TAB_RdEna", 30, 1 },
3628	{ "TAB_RdEna2", 19, 11 },
3629	{ "PLI_ReqAddr", 10, 9 },
3630	{ "PLI_ReqVFID", 2, 8 },
3631	{ "PLI_ReqTabHit", 1, 1 },
3632	{ "PLI_ReqRdVld", 0, 1 },
3633	{ "PCIE_PDEBUG_REG_0x1f", 0x1f, 0 },
3634	{ "PLI_ReqVld", 0, 32 },
3635	{ "PCIE_PDEBUG_REG_0x20", 0x20, 0 },
3636	{"PLI_RspVld", 0, 32 },
3637	{ NULL }
3638};
3639
3640static struct cudbg_reg_info t5_pcie_pdbg_regs_21_to_40[] = {
3641	{ "PCIE_PDEBUG_REG_0x21", 0x21, 0 },
3642	{ "PLI_ReqPbaStart", 20, 12 },
3643	{ "PLI_ReqPbaEnd", 9, 11 },
3644	{ "PLI_ReqVFID", 2, 7 },
3645	{ "PLI_ReqPbaHit", 1, 1 },
3646	{ "PLI_ReqRdVld", 0, 1 },
3647	{ "PCIE_PDEBUG_REG_0x22", 0x22, 0 },
3648	{ "GntSI1", 31, 1 },
3649	{ "GntSI2", 30, 1 },
3650	{ "GntSI3", 27, 3 },
3651	{ "GntSI4", 16, 11 },
3652	{ "GntSI5", 8, 8 },
3653	{ "GntSI6", 7, 1 },
3654	{ "GntSI7", 6, 1 },
3655	{ "GntSI8", 5, 1 },
3656	{ "GntSI9", 4, 1 },
3657	{ "GntSIa", 3, 1 },
3658	{ "GntAI", 2, 1 },
3659	{ "GntDB", 1, 1 },
3660	{ "GntDI", 0, 1 },
3661	{ "PCIE_PDEBUG_REG_0x23", 0x23, 0 },
3662	{ "DI_ReqVld", 31, 1 },
3663	{ "DI_ReqRdy", 30, 1 },
3664	{ "DI_ReqWrEn", 19, 11 },
3665	{ "DI_ReqMsiEn", 18, 1 },
3666	{ "DI_ReqMsxEn", 17, 1 },
3667	{ "DI_ReqMsxVFIDMsk", 16, 1 },
3668	{ "DI_ReqWrEn2", 2, 14 },
3669	{ "DI_ReqRdEn", 1, 1 },
3670	{ "DI_ReqWrEn3", 0, 1 },
3671	{ "PCIE_PDEBUG_REG_0x24", 0x24, 0 },
3672	{ "ven_msi_req_24", 0, 32 },
3673	{ "PCIE_PDEBUG_REG_0x25", 0x25, 0 },
3674	{ "ven_msi_req", 0, 32 },
3675	{ "PCIE_PDEBUG_REG_0x26", 0x26, 0 },
3676	{ "ven_msi_req", 0, 32 },
3677	{ "PCIE_PDEBUG_REG_0x27", 0x27, 0 },
3678	{ "FID_STI_RspVld", 31, 1 },
3679	{ "TAB_StiRdEna", 30, 1 },
3680	{ "TAB_StiWrEna", 29, 1 },
3681	{ "TAB_StiRdEna2", 18, 11 },
3682	{ "PLI_ReqTabHit", 7, 11 },
3683	{ "GntSI", 0, 7 },
3684	{ "PCIE_PDEBUG_REG_0x28", 0x28, 0 },
3685	{ "PLI_ReqWrVld", 31, 1 },
3686	{ "PLI_ReqPbaHit", 30, 1 },
3687	{ "PLI_TABAddrLWrEn", 29, 1 },
3688	{ "PLI_TABAddrHWrEn", 28, 1 },
3689	{ "PLI_TABDatWrEn", 27, 1 },
3690	{ "PLI_TABMskWrEn", 26, 1 },
3691	{ "AI_ReqVld", 23, 3 },
3692	{ "AI_ReqVld2", 22, 1 },
3693	{ "AI_ReqRdy", 21, 1 },
3694	{ "ven_msi_req_28", 18, 3 },
3695	{ "ven_msi_req2", 11, 7 },
3696	{ "ven_msi_req3", 6, 5 },
3697	{ "ven_msi_req4", 3 , 3 },
3698	{ "ven_msi_req5", 2, 1 },
3699	{ "ven_msi_grant", 1, 1 },
3700	{ "ven_msi_req6", 0, 1 },
3701	{ "PCIE_PDEBUG_REG_0x29", 0x29, 0 },
3702	{ "TRGT1_ReqDataVld", 16, 26 },
3703	{ "TRGT1_ReqDataVld2", 12, 4 },
3704	{ "TRGT1_ReqDataVld3", 11, 1 },
3705	{ "TRGT1_ReqDataVld4", 10, 1 },
3706	{ "TRGT1_ReqDataVld5", 9, 1 },
3707	{ "TRGT1_ReqDataVld6", 8, 1 },
3708	{ "TRGT1_ReqDataVld7", 4, 4 },
3709	{ "TRGT1_ReqDataVld8", 2, 2 },
3710	{ "TRGT1_ReqDataRdy", 1, 1 },
3711	{ "TRGT1_ReqDataVld0", 0, 1 },
3712	{ "PCIE_PDEBUG_REG_0x2a", 0x2a, 0 },
3713	{ "TRGT1_ReqDataVld", 0, 32 },
3714	{ "PCIE_PDEBUG_REG_0x2b", 0x2b, 0 },
3715	{ "radm_trgt1_addr", 20, 12 },
3716	{ "radm_trgt1_dwen", 16, 4 },
3717	{ "radm_trgt1_fmt", 14, 2 },
3718	{ "radm_trgt1_type", 9, 5 },
3719	{ "radm_trgt1_in_membar_range", 6, 3 },
3720	{ "radm_trgt1_ecrc_err", 5, 1 },
3721	{ "radm_trgt1_dllp_abort", 4, 1 },
3722	{ "radm_trgt1_tlp_abort", 3, 1 },
3723	{ "radm_trgt1_eot", 2, 1 },
3724	{ "radm_trgt1_dv_2b", 1, 1 },
3725	{ "radm_trgt1_hv_2b", 0, 1 },
3726	{ "PCIE_PDEBUG_REG_0x2c", 0x2c, 0 },
3727	{ "StateMPIO", 29, 3 },
3728	{ "StateCPL", 25, 4 },
3729	{ "StateAlin", 22, 3 },
3730	{ "StatePL", 19, 3 },
3731	{ "StateMARsp", 18, 1 },
3732	{ "MA_TagsInUse", 11, 7 },
3733	{ "radm_trgt1_hsrdy", 10, 1 },
3734	{ "radm_trgt1_dsrdy", 9, 1 },
3735	{ "ALIND_ReqWrDataVld", 8, 1 },
3736	{ "FID_LkUpWrHdrVld", 7, 1 },
3737	{ "MPIO_WrVld", 6, 1 },
3738	{ "trgt1_radm_halt", 5, 1 },
3739	{ "radm_trgt1_dv_2c", 4, 1 },
3740	{ "radm_trgt1_dv_2c_2", 3, 1 },
3741	{ "radm_trgt1_tlp_abort_2c", 2, 1 },
3742	{ "radm_trgt1_dllp_abort_2c", 1, 1 },
3743	{ "radm_trgt1_ecrc_err_2c", 0, 1 },
3744	{ "PCIE_PDEBUG_REG_0x2d", 0x2d, 0 },
3745	{ "radm_trgt1_hv_2d", 31, 1 },
3746	{ "radm_trgt1_dv_2d", 30, 1 },
3747	{ "radm_trgt1_hv2", 23, 7 },
3748	{ "radm_trgt1_hv3", 20, 3 },
3749	{ "radm_trgt1_hv4", 16, 4 },
3750	{ "radm_trgt1_hv5", 12, 4 },
3751	{ "radm_trgt1_hv6", 11, 1 },
3752	{ "radm_trgt1_hv7", 10, 1 },
3753	{ "radm_trgt1_hv8", 7, 3 },
3754	{ "radm_trgt1_hv9", 6, 1 },
3755	{ "radm_trgt1_hva", 5, 1 },
3756	{ "radm_trgt1_dsrdy_2d", 4, 1 },
3757	{ "radm_trgt1_WrCnt", 0, 4 },
3758	{ "PCIE_PDEBUG_REG_0x2e", 0x2e, 0 },
3759	{ "radm_trgt1_hv_2e", 30, 2 },
3760	{ "radm_trgt1_hv_2e_2", 20, 10 },
3761	{ "radm_trgt1_hv_we_3", 12, 8 },
3762	{ "ALIN_ReqDataVld4", 8, 4 },
3763	{ "ALIN_ReqDataVld5", 7, 1 },
3764	{ "ALIN_ReqDataVld6", 6, 1 },
3765	{ "ALIN_ReqDataVld7", 4, 2 },
3766	{ "ALIN_ReqDataVld8", 3, 1 },
3767	{ "ALIN_ReqDataVld9", 2, 1 },
3768	{ "ALIN_ReqDataRdy", 1, 1 },
3769	{ "ALIN_ReqDataVlda", 0, 1 },
3770	{ "PCIE_PDEBUG_REG_0x2f", 0x2f, 0 },
3771	{"ALIN_ReqDataVld", 0, 32 },
3772	{ "PCIE_PDEBUG_REG_0x30", 0x30, 0 },
3773	{ "radm_trgt1_hv_30", 25, 7 },
3774	{ "PIO_WrCnt", 15, 10 },
3775	{ "ALIND_ReqWrCnt", 12, 3 },
3776	{ "FID_LkUpWrCnt", 9, 3 },
3777	{ "ALIND_ReqRdDataVld", 8, 1 },
3778	{ "ALIND_ReqRdDataRdy", 7, 1 },
3779	{ "ALIND_ReqRdDataVld2", 6, 1 },
3780	{ "ALIND_ReqWrDataVld3", 3, 3 },
3781	{ "ALIND_ReqWrDataVld4", 2, 1 },
3782	{ "ALIND_ReqWrDataRdyOpen", 1, 1 },
3783	{ "ALIND_ReqWrDataVld5", 0, 1 },
3784	{ "PCIE_PDEBUG_REG_0x31", 0x31, 0 },
3785	{ "ALIND_ReqWrDataVld", 0, 32 },
3786	{ "PCIE_PDEBUG_REG_0x32", 0x32, 0 },
3787	{ "ALIND_ReqWrDataVld", 0, 32 },
3788	{ "PCIE_PDEBUG_REG_0x33", 0x33, 0 },
3789	{ "ALIND_ReqWrDataVld", 0, 32 },
3790	{ "PCIE_PDEBUG_REG_0x34", 0x34, 0 },
3791	{ "ALIND_ReqWrDataVld", 0, 32 },
3792	{ "PCIE_PDEBUG_REG_0x35", 0x35, 0 },
3793	{ "MPIO_WrVld", 19, 13 },
3794	{ "FID_LkUpRdHdrVld", 18, 1 },
3795	{ "FID_LkUpRdHdrVld2", 17, 1 },
3796	{ "FID_LkUpRdHdrVld3", 16, 1 },
3797	{ "FID_LkUpRdHdrVld4", 15, 1 },
3798	{ "FID_LkUpRdHdrVld5", 14, 1 },
3799	{ "FID_LkUpRdHdrVld6", 13, 1 },
3800	{ "FID_LkUpRdHdrVld7", 12, 1 },
3801	{ "FID_LkUpRdHdrVld8", 11, 1 },
3802	{ "FID_LkUpRdHdrVld9", 10, 1 },
3803	{ "FID_LkUpRdHdrVlda", 9, 1 },
3804	{ "FID_LkUpRdHdrVldb", 8, 1 },
3805	{ "FID_LkUpRdHdrVldc", 7, 1 },
3806	{ "MPIO_WrVld1", 6, 1 },
3807	{ "MPIO_WrVld2", 5, 1 },
3808	{ "MPIO_WrVld3", 4, 1 },
3809	{ "MPIO_WrVld4", 0, 4 },
3810	{ "PCIE_PDEBUG_REG_0x36", 0x36, 0 },
3811	{ "MPIO_WrVld", 0, 32 },
3812	{ "PCIE_PDEBUG_REG_0x37", 0x37, 0},
3813	{ "MPIO_WrVld", 0, 32 },
3814	{ "PCIE_PDEBUG_REG_0x38", 0x38, 0 },
3815	{ "MPIO_WrVld", 0, 32 },
3816	{ "PCIE_PDEBUG_REG_0x39", 0x39, 0 },
3817	{ "MPIO_WrVld", 0, 32 },
3818	{ "PCIE_PDEBUG_REG_0x3a", 0x3a, 0 },
3819	{ "client0_tlp_vfunc_active", 31, 1 },
3820	{ "client0_tlp_vfunc_num", 24, 7 },
3821	{ "client0_tlp_func_num", 21, 3 },
3822	{ "client0_tlp_byte_en", 13, 8 },
3823	{ "client0_tlp_byte_len", 0, 13 },
3824	{ "PCIE_PDEBUG_REG_0x3b", 0x3b, 0 },
3825	{ "xadm_client0_halt", 31, 1 },
3826	{ "client0_tlp_dv", 30, 1 },
3827	{ "client0_addr_align_en", 29, 1 },
3828	{ "client0_cpl_bcm", 28, 1 },
3829	{ "client0_tlp_ep", 27, 1 },
3830	{ "client0_cpl_status", 24, 3 },
3831	{ "client0_tlp_td", 23, 1 },
3832	{ "client0_tlp_type", 18 , 5 },
3833	{ "client0_tlp_fmt", 16, 2 },
3834	{ "client0_tlp_bad_eot", 15, 1 },
3835	{ "client0_tlp_eot", 14, 1 },
3836	{ "client0_tlp_attr", 11, 3 },
3837	{ "client0_tlp_tc", 8, 3 },
3838	{ "client0_tlp_tid", 0, 8 },
3839	{ "PCIE_PDEBUG_REG_0x3c", 0x3c, 0 },
3840	{ "MEM_RspRRAVld", 31, 1 },
3841	{ "MEM_RspRRARdy", 30, 1 },
3842	{ "PIO_RspRRAVld", 29, 1 },
3843	{ "PIO_RspRRARdy", 28, 1 },
3844	{ "MEM_RspRdVld", 27, 1 },
3845	{ "MEM_RspRdRRARdy", 26, 1 },
3846	{ "PIO_RspRdVld", 25, 1 },
3847	{ "PIO_RspRdRRARdy", 24, 1 },
3848	{ "TGT_TAGQ_RdVld", 16 , 8},
3849	{ "CplTxnDisable", 8, 8 },
3850	{ "CplTxnDisable2", 7, 1 },
3851	{ "client0_tlp_hv", 0, 7 },
3852	{ "PCIE_PDEBUG_REG_0x3D", 0x3d, 0 },
3853	{ "pdebug_0x3D", 0, 32 },
3854	{ "PCIE_PDEBUG_REG_0x3E", 0x3e, 0 },
3855	{ "pdebug_0x3E", 0, 32 },
3856	{ "PCIE_PDEBUG_REG_0x3F", 0x3f, 0 },
3857	{ "pdebug_0x3F", 0, 32 },
3858	{ "PCIE_PDEBUG_REG_0x40", 0x40, 0 },
3859	{ "pdebug_0x40", 0, 32 },
3860	{ NULL }
3861};
3862
3863static struct cudbg_reg_info t5_pcie_pdbg_regs_41_to_50[] = {
3864	{ "PCIE_PDEBUG_REG_0x41", 0x41, 0 },
3865	{ "pdebug_0x41", 0, 32 },
3866	{ "PCIE_PDEBUG_REG_0x42", 0x42, 0 },
3867	{ "pdebug_0x42", 0, 32 },
3868	{ "PCIE_PDEBUG_REG_0x43", 0x43, 0 },
3869	{ "pdebug_0x43", 0, 32 },
3870	{ "PCIE_PDEBUG_REG_0x44", 0x44, 0 },
3871	{ "pdebug_0x44", 0, 32 },
3872	{ "PCIE_PDEBUG_REG_0x45", 0x45, 0 },
3873	{ "pdebug_0x45", 0, 32 },
3874	{ "PCIE_PDEBUG_REG_0x46", 0x46, 0 },
3875	{ "pdebug_0x46", 0, 32 },
3876	{ "PCIE_PDEBUG_REG_0x47", 0x47, 0 },
3877	{ "pdebug_0x47", 0, 32 },
3878	{ "PCIE_PDEBUG_REG_0x48", 0x48, 0 },
3879	{ "pdebug_0x48", 0, 32 },
3880	{ "PCIE_PDEBUG_REG_0x49", 0x49, 0 },
3881	{ "pdebug_0x49", 0, 32 },
3882	{ "PCIE_PDEBUG_REG_0x4a", 0x4a, 0 },
3883	{ "pdebug_0x4A", 0, 32 },
3884	{ "PCIE_PDEBUG_REG_0x4b", 0x4b, 0 },
3885	{ "pdebug_0xaB", 0, 32 },
3886	{ "PCIE_PDEBUG_REG_0x4c", 0x4c, 0 },
3887	{ "pdebug_0x4C", 0, 32 },
3888	{ "PCIE_PDEBUG_REG_0x4d", 0x4d, 0 },
3889	{ "pdebug_0x4D", 0, 32 },
3890	{ "PCIE_PDEBUG_REG_0x4e", 0x4e, 0 },
3891	{ "pdebug_0x4E", 0, 32 },
3892	{ "PCIE_PDEBUG_REG_0x4f", 0x4f, 0 },
3893	{ "pdebug_0x4F", 0, 32 },
3894	{ "PCIE_PDEBUG_REG_0x50", 0x50, 0 },
3895	{ "pdebug_0x50", 0, 32 },
3896	{ NULL }
3897};
3898
3899static struct cudbg_reg_info t5_pcie_cdbg_regs_00_to_20[] = {
3900	{ "PCIE_CDEBUG_REG_0x0", 0x00, 0 },
3901	{ "PCIE_CDEBUG_REG_0x1", 0x01, 0 },
3902	{ "PCIE_CDEBUG_REG_0x2", 0x02, 0 },
3903	{ "FLR_ReqVld", 31, 1 },
3904	{ "D_RspVld", 28, 3 },
3905	{ "D_RspVld2", 27, 1 },
3906	{ "D_RspVld3", 26, 1 },
3907	{ "D_RspVld4", 25, 1 },
3908	{ "D_RspVld5", 24, 1 },
3909	{ "D_RspVld6", 20, 4 },
3910	{ "D_RspAFull", 16, 4 },
3911	{ "D_RdReqVld", 12, 4 },
3912	{ "D_RdReqAFull", 8, 4 },
3913	{ "D_WrReqVld", 4, 4 },
3914	{ "D_WrReqAFull", 0, 4 },
3915	{ "PCIE_CDEBUG_REG_0x3", 0x03, 0 },
3916	{ "C_ReqVld", 19, 13 },
3917	{ "C_RspVld2", 16, 3 },
3918	{ "C_RspVld3", 15, 1 },
3919	{ "C_RspVld4", 14, 1 },
3920	{ "C_RspVld5", 13, 1 },
3921	{ "C_RspVld6", 12, 1 },
3922	{ "C_RspVld7", 9, 3 },
3923	{ "C_RspAFull", 6, 3 },
3924	{ "C_ReqVld8", 3, 3 },
3925	{ "C_ReqAFull", 0, 3 },
3926	{ "PCIE_CDEBUG_REG_0x4", 0x04, 0 },
3927	{ "H_ReqVld", 7, 25 },
3928	{ "H_RspVld", 6, 1 },
3929	{ "H_RspVld2", 5, 1 },
3930	{ "H_RspVld3", 4, 1 },
3931	{ "H_RspVld4", 3, 1 },
3932	{ "H_RspAFull", 2, 1 },
3933	{ "H_ReqVld2", 1, 1 },
3934	{ "H_ReqAFull", 0, 1 },
3935	{ "PCIE_CDEBUG_REG_0x5", 0x05, 0 },
3936	{ "ER_RspVld", 16, 16 },
3937	{ "ER_ReqVld2", 5, 10 },
3938	{ "ER_ReqVld3", 2, 3 },
3939	{ "ER_RspVld4", 1, 1 },
3940	{ "ER_ReqVld5", 0, 1 },
3941	{ "PCIE_CDEBUG_REG_0x6", 0x06, 0 },
3942	{ "PL_BAR2_ReqVld", 4, 28 },
3943	{ "PL_BAR2_ReqVld2", 3, 1 },
3944	{ "PL_BAR2_ReqVlde", 2, 1 },
3945	{ "PL_BAR2_ReqFull", 1, 1 },
3946	{ "PL_BAR2_ReqVld4", 0, 1},
3947	{ "PCIE_CDEBUG_REG_0x7", 0x07, 0 },
3948	{"PL_BAR2_ReqVld_7", 0, 32 },
3949	{ "PCIE_CDEBUG_REG_0x8", 0x08, 0 },
3950	{"PL_BAR2_ReqVld_8", 0, 32 },
3951	{ "PCIE_CDEBUG_REG_0x9", 0x09, 0 },
3952	{"PL_BAR2_ReqVld_9", 0, 32 },
3953	{ "PCIE_CDEBUG_REG_0xa", 0x0a, 0 },
3954	{ "VPD_RspVld", 20, 12 },
3955	{ "VPD_ReqVld2", 9, 11 },
3956	{ "VPD_ReqVld3", 6, 3 },
3957	{ "VPD_ReqVld4", 5, 1 },
3958	{ "VPD_ReqVld5", 3, 2 },
3959	{ "VPD_RspVld2", 2, 1 },
3960	{ "VPD_RspVld3", 1, 1 },
3961	{ "VPD_ReqVld6", 0, 1 },
3962	{ "PCIE_CDEBUG_REG_0xb", 0x0b, 0 },
3963	{ "MA_ReqDataVld", 28, 4 },
3964	{ "MA_ReqAddrVld", 27, 1 },
3965	{ "MA_ReqAddrVld2", 26, 1 },
3966	{ "MA_RspDataVld2", 22, 4 },
3967	{ "MA_ReqAddrVld3", 20, 2 },
3968	{ "MA_ReqAddrVld4", 4, 16 },
3969	{ "MA_ReqAddrVld5", 3, 1 },
3970	{ "MA_ReqAddrVld6", 2, 1 },
3971	{ "MA_ReqAddrRdy", 1, 1 },
3972	{ "MA_ReqAddrVld7", 0, 1 },
3973	{ "PCIE_CDEBUG_REG_0xc", 0x0c, 0 },
3974	{ "MA_ReqAddrVld_c", 0, 32 },
3975	{ "PCIE_CDEBUG_REG_0xd", 0x0d, 0 },
3976	{ "MA_ReqAddrVld_d", 0, 32 },
3977	{ "PCIE_CDEBUG_REG_0xe", 0x0e, 0 },
3978	{ "MA_ReqAddrVld_e", 0, 32 },
3979	{ "PCIE_CDEBUG_REG_0xf", 0x0f, 0 },
3980	{ "MA_ReqAddrVld_f", 0, 32 },
3981	{ "PCIE_CDEBUG_REG_0x10", 0x10, 0 },
3982	{ "MA_ReqAddrVld_10", 0, 32 },
3983	{ "PCIE_CDEBUG_REG_0x11", 0x11, 0 },
3984	{ "MA_ReqAddrVld_11", 0, 32 },
3985	{ "PCIE_CDEBUG_REG_0x12", 0x12, 0 },
3986	{ "MA_ReqAddrVld_12", 0, 32 },
3987	{ "PCIE_CDEBUG_REG_0x13", 0x13, 0 },
3988	{ "MA_ReqAddrVld_13", 0, 32 },
3989	{ "PCIE_CDEBUG_REG_0x14", 0x14, 0 },
3990	{ "MA_ReqAddrVld_14", 0, 32 },
3991	{ "PCIE_CDEBUG_REG_0x15", 0x15, 0 },
3992	{ "PLM_ReqVld",  19, 13 },
3993	{ "PLM_ReqVld2", 18, 1 },
3994	{ "PLM_RspVld3", 17, 1 },
3995	{ "PLM_ReqVld4", 16, 1 },
3996	{ "PLM_ReqVld5", 15, 1 },
3997	{ "PLM_ReqVld6", 14, 1 },
3998	{ "PLM_ReqVld7", 13, 1 },
3999	{ "PLM_ReqVld8", 12, 1 },
4000	{ "PLM_ReqVld9", 4, 8 },
4001	{ "PLM_ReqVlda", 1, 3 },
4002	{ "PLM_ReqVldb", 0, 1 },
4003	{ "PCIE_CDEBUG_REG_0x16", 0x16, 0 },
4004	{ "PLM_RspVld", 0, 32 },
4005	{ "PCIE_CDEBUG_REG_0x17", 0x17, 0 },
4006	{ "cdebug_0x17", 0, 32 },
4007	{ "PCIE_CDEBUG_REG_0x18", 0x18, 0 },
4008	{ "cdebug_0x18", 0, 32 },
4009	{ "PCIE_CDEBUG_REG_0x19", 0x19, 0 },
4010	{ "cdebug_0x19", 0, 32 },
4011	{ "PCIE_CDEBUG_REG_0x1A", 0x1a, 0 },
4012	{ "cdebug_0x1A", 0, 32 },
4013	{ "PCIE_CDEBUG_REG_0x1B", 0x1b, 0 },
4014	{ "cdebug_0x1B", 0, 32 },
4015	{ "PCIE_CDEBUG_REG_0x1C", 0x1c, 0 },
4016	{ "cdebug_0x1C", 0, 32 },
4017	{ "PCIE_CDEBUG_REG_0x1D", 0x1d, 0 },
4018	{ "cdebug_0x1D", 0, 32 },
4019	{ "PCIE_CDEBUG_REG_0x1E", 0x1e, 0 },
4020	{ "cdebug_0x1E", 0, 32 },
4021	{ "PCIE_CDEBUG_REG_0x1F", 0x1f, 0 },
4022	{ "cdebug_0x1F", 0, 32 },
4023	{ "PCIE_CDEBUG_REG_0x20", 0x20, 0 },
4024	{ "cdebug_0x20", 0, 32 },
4025	{ NULL }
4026};
4027
4028static struct cudbg_reg_info t5_pcie_cdbg_regs_21_to_37[] = {
4029	{ "PCIE_CDEBUG_REG_0x21", 0x21, 0 },
4030	{ "cdebug_0x21", 0, 32 },
4031	{ "PCIE_CDEBUG_REG_0x22", 0x22, 0 },
4032	{ "cdebug_0x22", 0, 32 },
4033	{ "PCIE_CDEBUG_REG_0x23", 0x23, 0 },
4034	{ "cdebug_0x23", 0, 32 },
4035	{ "PCIE_CDEBUG_REG_0x24", 0x24, 0 },
4036	{ "cdebug_0x24", 0, 32 },
4037	{ "PCIE_CDEBUG_REG_0x25", 0x25, 0 },
4038	{ "cdebug_0x25", 0, 32 },
4039	{ "PCIE_CDEBUG_REG_0x26", 0x26, 0 },
4040	{ "cdebug_0x26", 0, 32 },
4041	{ "PCIE_CDEBUG_REG_0x27", 0x27, 0 },
4042	{ "cdebug_0x27", 0, 32 },
4043	{ "PCIE_CDEBUG_REG_0x28", 0x28, 0 },
4044	{ "cdebug_0x28", 0, 32 },
4045	{ "PCIE_CDEBUG_REG_0x29", 0x29, 0 },
4046	{ "cdebug_0x29", 0, 32 },
4047	{ "PCIE_CDEBUG_REG_0x2a", 0x2a, 0 },
4048	{ "cdebug_0x2A", 0, 32 },
4049	{ "PCIE_CDEBUG_REG_0x2b", 0x2b, 0 },
4050	{ "cdebug_0x2B", 0, 32 },
4051	{ "PCIE_CDEBUG_REG_0x2c", 0x2c, 0 },
4052	{ "cdebug_0x2C", 0, 32 },
4053	{ "PCIE_CDEBUG_REG_0x2d", 0x2d, 0 },
4054	{ "cdebug_0x2D", 0, 32 },
4055	{ "PCIE_CDEBUG_REG_0x2e", 0x2e, 0 },
4056	{ "cdebug_0x2E", 0, 32 },
4057	{ "PCIE_CDEBUG_REG_0x2f", 0x2f, 0 },
4058	{ "cdebug_0x2F", 0, 32 },
4059	{ "PCIE_CDEBUG_REG_0x30", 0x30, 0 },
4060	{ "cdebug_0x30", 0, 32 },
4061	{ "PCIE_CDEBUG_REG_0x31", 0x31, 0 },
4062	{ "cdebug_0x31", 0, 32 },
4063	{ "PCIE_CDEBUG_REG_0x32", 0x32, 0 },
4064	{ "cdebug_0x32", 0, 32 },
4065	{ "PCIE_CDEBUG_REG_0x33", 0x33, 0 },
4066	{ "cdebug_0x33", 0, 32 },
4067	{ "PCIE_CDEBUG_REG_0x34", 0x34, 0 },
4068	{ "cdebug_0x34", 0, 32 },
4069	{ "PCIE_CDEBUG_REG_0x35", 0x35, 0 },
4070	{ "cdebug_0x35", 0, 32 },
4071	{ "PCIE_CDEBUG_REG_0x36", 0x36, 0 },
4072	{ "cdebug_0x36", 0, 32 },
4073	{ "PCIE_CDEBUG_REG_0x37", 0x37, 0 },
4074	{ "cdebug_0x37", 0, 32 },
4075	{ NULL }
4076};
4077
4078static struct cudbg_reg_info t5_pm_rx_regs_10000_to_10020[] = {
4079	{ "PM_TX_ISPI_DBG_4B_DATA0", 0x10000, 0 },
4080	{ "ispi_dbg_data", 0, 32 },
4081	{ "PM_RX_ISPI_DBG_4B_DATA1", 0x10001, 0 },
4082	{ "ispi_dbg_data", 0, 32 },
4083	{ "PM_RX_ISPI_DBG_4B_DATA2", 0x10002, 0 },
4084	{ "ispi_dbg_data", 0, 32 },
4085	{ "PM_RX_ISPI_DBG_4B_DATA3", 0x10003, 0 },
4086	{ "ispi_dbg_data", 0, 32 },
4087	{ "PM_RX_ISPI_DBG_4B_DATA4", 0x10004, 0 },
4088	{ "ispi_dbg_data", 0, 32 },
4089	{ "PM_RX_ISPI_DBG_4B_DATA5", 0x10005, 0 },
4090	{ "ispi_dbg_data", 0, 32 },
4091	{ "PM_RX_ISPI_DBG_4B_DATA6", 0x10006, 0 },
4092	{ "ispi_dbg_data", 0, 32 },
4093	{ "PM_RX_ISPI_DBG_4B_DATA7", 0x10007, 0 },
4094	{ "ispi_dbg_data", 0, 32 },
4095	{ "PM_RX_ISPI_DBG_4B_DATA8", 0x10008, 0 },
4096	{ "ispi_dbg_data", 0, 32 },
4097	{ "PM_RX_OSPI_DBG_4B_DATA0", 0x10009, 0 },
4098	{ "ospi_dbg_data", 0, 32 },
4099	{ "PM_RX_OSPI_DBG_4B_DATA1", 0x1000a, 0 },
4100	{ "ospi_dbg_data", 0, 32 },
4101	{ "PM_RX_OSPI_DBG_4B_DATA2", 0x1000b, 0 },
4102	{ "ospi_dbg_data", 0, 32 },
4103	{ "PM_RX_OSPI_DBG_4B_DATA3", 0x1000c, 0 },
4104	{ "ospi_dbg_data", 0, 32 },
4105	{ "PM_RX_OSPI_DBG_4B_DATA4", 0x1000d, 0 },
4106	{ "ospi_dbg_data", 0, 32 },
4107	{ "PM_RX_OSPI_DBG_4B_DATA5", 0x1000e, 0 },
4108	{ "ospi_dbg_data", 0, 32 },
4109	{ "PM_RX_OSPI_DBG_4B_DATA6", 0x1000f, 0 },
4110	{ "ospi_dbg_data", 0, 32 },
4111	{ "PM_RX_OSPI_DBG_4B_DATA7", 0x10010, 0 },
4112	{ "ospi_dbg_data", 0, 32 },
4113	{ "PM_RX_OSPI_DBG_4B_DATA8", 0x10011, 0 },
4114	{ "ospi_dbg_data", 0, 32 },
4115	{ "PM_RX_OSPI_DBG_4B_DATA9", 0x10012, 0 },
4116	{ "ospi_dbg_data", 0, 32 },
4117	{ "PM_RX_DBG_STAT_MSB", 0x10013, 0 },
4118	{ "stat_msb", 0, 32 },
4119	{ "PM_RX_DBG_STAT_LSB", 0x10014, 0 },
4120	{ "stat_lsb", 0, 32 },
4121	{ "PM_RX_DBG_RSVD_FLIT_CNT", 0x10015, 0 },
4122	{ "i_to_o_path_rsvd_flit_backup", 12, 4 },
4123	{ "i_to_o_path_rsvd_flit", 8, 4 },
4124	{ "prfch_rsvd_flit", 4, 4 },
4125	{ "ospi_rsvd_flit", 0, 4 },
4126	{ "PM_RX_SDC_EN", 0x10016, 0 },
4127	{ "sdc_en", 0, 1 },
4128	{ "PM_RX_INOUT_FIFO_DBG_CHNL_SEL", 0x10017, 0 },
4129	{ "chnl_3_sel", 3, 1 },
4130	{ "chnl_2_sel", 2, 1 },
4131	{ "chnl_1_sel", 1, 1 },
4132	{ "chnl_0_sel", 0, 1 },
4133	{ "PM_RX_INOUT_FIFO_DBG_WR", 0x10018, 0 },
4134	{ "o_fifo_write", 3, 1 },
4135	{ "i_fifo_write", 2, 1 },
4136	{ "o_fifo_read", 1, 1 },
4137	{ "i_fifo_read", 0, 1 },
4138	{ "PM_RX_INPUT_FIFO_STR_FWD_EN", 0x10019, 0 },
4139	{ "ispi_str_fwd_en", 0, 1 },
4140	{ "PM_RX_PRFTCH_ACROSS_BNDLE_EN", 0x1001a, 0 },
4141	{ "prftch_across_bndle_en", 0, 1 },
4142	{ "PM_RX_PRFTCH_WRR_ENABLE", 0x1001b, 0 },
4143	{ "prftch_wrr_enable", 0, 1 },
4144	{ "PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT", 0x1001c, 0 },
4145	{ "chnl1_max_deficit_cnt", 16, 16 },
4146	{ "chnl0_max_deficit_cnt", 0, 16 },
4147	{ "PM_RX_FEATURE_EN", 0x1001d, 0 },
4148	{ "pio_ch_deficit_ctl_en", 0, 1 },
4149	{ "PM_RX_CH0_OSPI_DEFICIT_THRSHLD", 0x1001e, 0 },
4150	{ "CH0_OSPI_DEFICIT_THRSHLD", 0, 12 },
4151	{ "PM_RX_CH1_OSPI_DEFICIT_THRSHLD", 0x1001f, 0 },
4152	{ "CH1_OSPI_DEFICIT_THRSHLD", 0, 12 },
4153	{ "PM_RX_INT_CAUSE_MASK_HALT", 0x10020, 0 },
4154	{ "INT_CAUSE_MASK", 0, 32 },
4155	{ NULL }
4156};
4157
4158static struct cudbg_reg_info t5_pm_rx_regs_10021_to_1002c[] = {
4159	{ "PM_RX_DBG_STAT0", 0x10021, 0 },
4160	{ "rx_rd_i_busy", 29, 1 },
4161	{ "rx_wr_to_o_busy", 28, 1 },
4162	{ "rx_m_to_o_busy", 27, 1 },
4163	{ "rx_i_to_m_busy", 26, 1 },
4164	{ "rx_pcmd_fb_only", 25, 1 },
4165	{ "rx_pcmd_mem", 24, 1 },
4166	{ "rx_pcmd_bypass", 23, 1 },
4167	{ "rx_pcmd_eop", 22, 1 },
4168	{ "rx_dumplicate_pcmd_eop", 21, 1 },
4169	{ "rx_pcmd_eob", 20, 1 },
4170	{ "rx_pcmd_fb", 16, 4 },
4171	{ "rx_pcmd_len", 0, 16 },
4172	{ "PM_RX_DBG_STAT1", 0x10022, 0 },
4173	{ "rx_PCMD0_mem", 30, 1 },
4174	{ "rx_free_ospi_cnt0", 18, 12 },
4175	{ "rx_PCMD0_flit_len", 6, 12 },
4176	{ "rx_PCMD0_cmd", 2, 4 },
4177	{ "rx_ofifo_full0", 1, 1 },
4178	{ "rx_PCMD0_bypass", 0, 1 },
4179	{ "PM_RX_DBG_STAT2", 0x10023, 0 },
4180	{ "rx_PCMD1_mem", 30, 1 },
4181	{ "rx_free_ospi_cnt1", 18, 12 },
4182	{ "rx_PCMD1_flit_len", 6, 12 },
4183	{ "rx_PCMD1_cmd", 2, 4 },
4184	{ "rx_ofifo_full1", 1, 1 },
4185	{ "rx_PCMD1_bypass", 0, 1 },
4186	{ "PM_RX_DBG_STAT3", 0x10024, 0 },
4187	{ "rx_set_pcmd_res_rdy_rd", 10, 2 },
4188	{ "rx_issued_prefetch_rd_e_clr", 8, 2 },
4189	{ "rx_issued_prefetch_rd", 6, 2 },
4190	{ "rx_pcmd_res_rdy", 4, 2 },
4191	{ "rx_db_vld", 3, 1 },
4192	{ "rx_first_bundle", 1, 2 },
4193	{ "rx_sdc_drdy", 0, 1 },
4194	{ "PM_RX_DBG_STAT4", 0x10025, 0 },
4195	{ "rx_pcmd_vld", 26, 1 },
4196	{ "rx_pcmd_to_ch", 25, 1 },
4197	{ "rx_pcmd_from_ch", 23, 2 },
4198	{ "rx_line", 18, 5 },
4199	{ "rx_iespi_TxValid", 14, 4 },
4200	{ "rx_iespi_TxFull", 10, 4 },
4201	{ "rx_PCMD_srdy", 8, 2 },
4202	{ "rx_PCMD_drdy", 6, 2 },
4203	{ "rx_pcmd_cmd", 2 , 4},
4204	{ "rx_pcmd_res_rdy", 0, 2 },
4205	{ "PM_RX_DBG_STAT5", 0x10026, 0 },
4206	{ "rx_atlst_1_pcmd_ch1", 29, 1 },
4207	{ "rx_atlst_1_pcmd_ch0", 28, 1 },
4208	{ "rx_pcmd_drdy", 26, 2 },
4209	{ "rx_pcmd_srdy", 24, 2 },
4210	{ "rx_Ispi_TxValid", 20, 4 },
4211	{ "rx_Ispi_Full", 16, 4 },
4212	{ "rx_Ospi_TxValid", 14, 2 },
4213	{ "rx_Ospi_Full", 12, 2 },
4214	{ "rx_E_RxValid", 8, 4 },
4215	{ "rx_E_RxAFull", 4, 4 },
4216	{ "rx_C_TxValid", 2, 2 },
4217	{ "rx_C_TxAFull", 0, 2 },
4218	{ "PM_RX_DBG_STAT6", 0x10027, 0 },
4219	{ "rx_m_intrnl_fifo_cnt", 4, 2 },
4220	{ "rx_M_ReqAddrRdy", 3, 1 },
4221	{ "rx_M_ReqWrite", 2, 1 },
4222	{ "rx_M_ReqDataVld", 1, 1 },
4223	{ "rx_M_ReqDataRdy", 0, 1 },
4224	{ "PM_RX_DBG_STAT7", 0x10028, 0 },
4225	{ "rx_pcmd1_free_cnt", 7, 7 },
4226	{ "rx_pcmd0_free_cnt", 0, 7 },
4227	{ "PM_RX_DBG_STAT8", 0x10029, 0 },
4228	{ "rx_In_Eop_Cnt3", 28, 4 },
4229	{ "rx_In_Eop_Cnt2", 24, 4 },
4230	{ "rx_In_Eop_Cnt1", 20, 4 },
4231	{ "rx_In_Eop_Cnt0", 16, 4 },
4232	{ "rx_In_Sop_Cnt3", 12, 4 },
4233	{ "rx_In_Sop_Cnt2", 8, 4 },
4234	{ "rx_In_Sop_Cnt1", 4, 4 },
4235	{ "rx_In_Sop_Cnt0", 0, 4 },
4236	{ "PM_RX_DBG_STAT9", 0x1002a, 0 },
4237	{ "rx_rsvd0", 28, 4 },
4238	{ "rx_rsvd1", 24, 4 },
4239	{ "rx_Out_Eop_Cnt1", 20, 4 },
4240	{ "rx_Out_Eop_Cnt0", 16, 4 },
4241	{ "rx_rsvd2", 12, 4 },
4242	{ "rx_rsvd3", 8, 4 },
4243	{ "rx_Out_Sop_Cnt1", 4, 4 },
4244	{ "rx_Out_Sop_Cnt0", 0, 4 },
4245	{ "PM_RX_DBG_STAT10", 0x1002b, 0 },
4246	{ "rx_ch_deficit_blowed", 24, 1 },
4247	{ "rx_ch1_deficit", 12, 12 },
4248	{ "rx_ch0_deficit", 0, 12 },
4249	{ "PM_RX_DBG_STAT11", 0x1002c, 0 },
4250	{ "rx_bundle_len_srdy", 30, 2 },
4251	{ "rx_rsvd11_1", 28, 2 },
4252	{ "rx_bundle_len1", 16, 12 },
4253	{ "rx_rsvd11", 12, 4 },
4254	{ "rx_bundle_len0", 0, 12 },
4255	{ NULL }
4256};
4257
4258static struct cudbg_reg_info t5_pm_tx_regs_10000_to_10020[] = {
4259	{ "PM_TX_ISPI_DBG_4B_DATA0", 0x10000, 0 },
4260	{ "ispi_dbg_data", 0, 32 },
4261	{ "PM_TX_ISPI_DBG_4B_DATA1", 0x10001, 0 },
4262	{ "ispi_dbg_data", 0, 32 },
4263	{ "PM_TX_ISPI_DBG_4B_DATA2", 0x10002, 0 },
4264	{ "ispi_dbg_data", 0, 32 },
4265	{ "PM_TX_ISPI_DBG_4B_DATA3", 0x10003, 0 },
4266	{ "ispi_dbg_data", 0, 32 },
4267	{ "PM_TX_ISPI_DBG_4B_DATA4", 0x10004, 0 },
4268	{ "ispi_dbg_data", 0, 32 },
4269	{ "PM_TX_ISPI_DBG_4B_DATA5", 0x10005, 0 },
4270	{ "ispi_dbg_data", 0, 32 },
4271	{ "PM_TX_ISPI_DBG_4B_DATA6", 0x10006, 0 },
4272	{ "ispi_dbg_data", 0, 32 },
4273	{ "PM_TX_ISPI_DBG_4B_DATA7", 0x10007, 0 },
4274	{ "ispi_dbg_data", 0, 32 },
4275	{ "PM_TX_ISPI_DBG_4B_DATA8", 0x10008, 0 },
4276	{ "ispi_dbg_data", 0, 32 },
4277	{ "PM_TX_OSPI_DBG_4B_DATA0", 0x10009, 0 },
4278	{ "ospi_dbg_data", 0, 32 },
4279	{ "PM_TX_OSPI_DBG_4B_DATA1", 0x1000a, 0 },
4280	{ "ospi_dbg_data", 0, 32 },
4281	{ "PM_TX_OSPI_DBG_4B_DATA2", 0x1000b, 0 },
4282	{ "ospi_dbg_data", 0, 32 },
4283	{ "PM_TX_OSPI_DBG_4B_DATA3", 0x1000c, 0 },
4284	{ "ospi_dbg_data", 0, 32 },
4285	{ "PM_TX_OSPI_DBG_4B_DATA4", 0x1000d, 0 },
4286	{ "ospi_dbg_data", 0, 32 },
4287	{ "PM_TX_OSPI_DBG_4B_DATA5", 0x1000e, 0 },
4288	{ "ospi_dbg_data", 0, 32 },
4289	{ "PM_TX_OSPI_DBG_4B_DATA6", 0x1000f, 0 },
4290	{ "ospi_dbg_data", 0, 32 },
4291	{ "PM_TX_OSPI_DBG_4B_DATA7", 0x10010, 0 },
4292	{ "ospi_dbg_data", 0, 32 },
4293	{ "PM_TX_OSPI_DBG_4B_DATA8", 0x10011, 0 },
4294	{ "ospi_dbg_data", 0, 32 },
4295	{ "PM_TX_OSPI_DBG_4B_DATA9", 0x10012, 0 },
4296	{ "ospi_dbg_data", 0, 32 },
4297	{ "PM_TX_OSPI_DBG_4B_DATA10", 0x10013, 0 },
4298	{ "ospi_dbg_data", 0, 32 },
4299	{ "PM_TX_OSPI_DBG_4B_DATA11", 0x10014, 0 },
4300	{ "ospi_dbg_data", 0, 32 },
4301	{ "PM_TX_OSPI_DBG_4B_DATA12", 0x10015, 0 },
4302	{ "ospi_dbg_data", 0, 32 },
4303	{ "PM_TX_OSPI_DBG_4B_DATA13", 0x10016, 0 },
4304	{ "ospi_dbg_data", 0, 32 },
4305	{ "PM_TX_OSPI_DBG_4B_DATA14", 0x10017, 0 },
4306	{ "ospi_dbg_data", 0, 32 },
4307	{ "PM_TX_OSPI_DBG_4B_DATA15", 0x10018, 0 },
4308	{ "ospi_dbg_data", 0, 32 },
4309	{ "PM_TX_OSPI_DBG_4B_DATA16", 0x10019, 0 },
4310	{ "ospi_dbg_data", 0, 32 },
4311	{ "PM_TX_DBG_STAT_MSB", 0x1001a, 0 },
4312	{ "stat_msb", 0, 32 },
4313	{ "PM_TX_DBG_STAT_LSB", 0x1001b, 0 },
4314	{ "stat_lsb", 0, 32 },
4315	{ "PM_TX_DBG_RSVD_FLIT_CNT", 0x1001c, 0 },
4316	{ "i_to_o_path_rsvd_flit_backup", 12, 4 },
4317	{ "i_to_o_path_rsvd_flit", 8, 4 },
4318	{ "prfch_rsvd_flit", 4, 4 },
4319	{ "ospi_rsvd_flit", 0, 4 },
4320	{ "PM_TX_SDC_EN", 0x1001d, 0 },
4321	{ "sdc_en", 0, 1 },
4322	{ "PM_TX_INOUT_FIFO_DBG_CHNL_SEL", 0x1001e, 0 },
4323	{ "chnl_3_sel", 3, 1 },
4324	{ "chnl_2_sel", 2, 1 },
4325	{ "chnl_1_sel", 1, 1 },
4326	{ "chnl_0_sel", 0, 1 },
4327	{ "PM_TX_INOUT_FIFO_DBG_WR", 0x1001f, 0 },
4328	{ "o_fifo_write", 3, 1 },
4329	{ "i_fifo_write", 2, 1 },
4330	{ "o_fifo_read", 1, 1 },
4331	{ "i_fifo_read", 0, 1 },
4332	{ "PM_TX_INPUT_FIFO_STR_FWD_EN", 0x10020, 0 },
4333	{ "ispi_str_fwd_en", 0, 1 },
4334	{ NULL }
4335};
4336
4337static struct cudbg_reg_info t5_pcie_config_regs_00_to_208[] = {
4338	{ "PCIE_DEVID_VENID", 0x00, 0 },
4339	{ "VendorID", 0, 16 },
4340	{ "DeviceID", 16, 16 },
4341	{ "PCIE_STAT_CMD", 0x04, 0 },
4342	{ "IOEnable", 0, 1 },
4343	{ "MemEnable", 1, 1 },
4344	{ "BusMasterEnable", 2, 1 },
4345	{ "Rsvdl", 3, 3 },
4346	{ "PERREnable", 6, 1 },
4347	{ "Rsvd2", 7, 1 },
4348	{ "SERREnable", 8, 1 },
4349	{ "Rsvd3", 9, 1 },
4350	{ "IntDisable", 10, 1 },
4351	{ "Rsvd4", 11, 8 },
4352	{ "IntStatus", 19, 1 },
4353	{ "CapList", 20, 1 },
4354	{ "Rsvd5", 21, 3 },
4355	{ "MstDatParErr", 24, 1 },
4356	{ "Rsvd6", 25, 2 },
4357	{ "SigTgtAbort", 27, 1 },
4358	{ "RcvTgtAbort", 28, 1 },
4359	{ "RcvMstAbort", 29, 1 },
4360	{ "SigSERR", 30, 1 },
4361	{ "DetPERR", 31, 1 },
4362	{ "PCIE_CCODE_REVID", 0x08, 0 },
4363	{ "RevisionID", 0, 8, },
4364	{ "ClassCode", 8, 24 },
4365	{ "PCIE_BIST_HDR_TMR_CLS", 0xc, 0 },
4366	{ "CacheLineSize", 0, 8 },
4367	{ "MstLatTimer", 8, 8 },
4368	{ "HdrType", 16, 8 },
4369	{ "BIST", 24, 8 },
4370	{ "PCIE_BAR0", 0x10, 0 },
4371	{ "MemSpaceInd", 0, 1 },
4372	{ "Type", 1, 2 },
4373	{ "Prefetchable", 3, 1 },
4374	{ "BaseAddress", 4, 28 },
4375	{ "PCIE_BAR1", 0x14, 0 },
4376	{ "PCIE_BAR2", 0x18, 0 },
4377	{ "MemSpaceInd", 0, 1 },
4378	{ "Type", 1, 2 },
4379	{ "Prefetchable", 3, 1 },
4380	{ "BaseAddress", 4, 28 },
4381	{ "PCIE_BAR3", 0x1c, 0 },
4382	{ "PCIE_BAR4", 0x20, 0 },
4383	{ "MemSpaceInd", 0, 1 },
4384	{ "Type", 1, 2 },
4385	{ "Prefetchable", 3, 1 },
4386	{ "BaseAddress", 4, 28 },
4387	{ "PCIE_BAR5", 0x24, 0 },
4388	{ "PCIE_CIS", 0x28, 0 },
4389	{ "PCIE_SSID_SSVENID", 0x2c, 0 },
4390	{ "SSVenID", 0, 16 },
4391	{ "SSID", 16, 16 },
4392	{ "PCIE_EXPROM", 0x30, 0 },
4393	{ "ExpROMEn", 0, 1 },
4394	{ "Rsvd", 1, 10 },
4395	{ "BaseAddr", 11, 21 },
4396	{ "PCIE_CAP_PTR", 0x34, 0 },
4397	{ "CapPtr", 0, 8 },
4398	{ "Rsvd", 8, 24 },
4399	{ "PCIE_INT_LINE_PIN", 0x3c, 0 },
4400	{ "IntLine", 0, 8 },
4401	{ "IntPin", 8, 8 },
4402	{ "Rsvd", 16, 16 },
4403	{ "PCIE_PM_CAP", 0x40, 0 },
4404	{ "PMCapID", 0, 8 },
4405	{ "NextCapPtr", 8, 8 },
4406	{ "PMVer", 16, 3 },
4407	{ "PMEClock", 19, 1 },
4408	{ "Rsvd", 20, 1 },
4409	{ "DSI", 21, 1 },
4410	{ "AuxCur", 22, 3 },
4411	{ "D1Sup", 25, 1 },
4412	{ "D2Sup", 26, 1 },
4413	{ "PMESup", 27, 5 },
4414	{ "PCIE_MSI_CAP", 0x50, 0 },
4415	{ "MSICapID", 0, 8 },
4416	{ "NextCapPtr", 8, 8 },
4417	{ "MSIEn", 16, 1 },
4418	{ "MultMsgCap", 17, 3 },
4419	{ "MultMsgEn", 20, 3 },
4420	{ "MSI64Cap", 23, 1 },
4421	{ "PerVecMaskCap", 24, 1 },
4422	{ "Rsvd", 25, 7 },
4423	{ "PCIE_MSI_ADDR", 0x54, 0 },
4424	{ "Rsvd", 0, 2 },
4425	{ "MsgAddr", 2, 30 },
4426	{ "PCIE_MSI_UPR_ADDR", 0x58, 0 },
4427	{ "MsgUprAddr", 0, 32 },
4428	{ "PCIE_MSI_DATA", 0x5c, 0 },
4429	{ "MsgData", 0, 16 },
4430	{ "Rsvd", 16, 16 },
4431	{ "PCIE_MSI_MASK", 0x60, 0 },
4432	{ "MSIMask", 0, 32 },
4433	{ "PCIE_MSI_PND", 0x64, 0 },
4434	{ "MSIPnd", 0, 32 },
4435	{ "PCIE_PCIE_CAP", 0x70, 0 },
4436	{ "PCIECapID", 0, 8 },
4437	{ "NextCapPtr", 8, 8 },
4438	{ "PCIECapVer", 16, 4 },
4439	{ "DeviceType", 20, 4 },
4440	{ "SlotImpl", 24, 1 },
4441	{ "IntMsgNum", 25, 5 },
4442	{ "Rsvd", 30, 2 },
4443	{ "PCIE_DEV_CAP", 0x74, 0 },
4444	{ "MaxPyldSzSup", 0, 3 },
4445	{ "PhantomFuncSup", 3, 2 },
4446	{ "ExtTagSup", 5, 1 },
4447	{ "L0sAccLat", 6, 3 },
4448	{ "L1AccLat", 9, 3 },
4449	{ "Rsvd1", 13, 3 },
4450	{ "RoleBasedErr", 15, 1 },
4451	{ "Rsvd2", 16, 2 },
4452	{ "CapSlotPwrLmtVal", 18, 8 },
4453	{ "CapSlotPwrLmtScl", 26, 2 },
4454	{ "FLRCap", 28, 1 },
4455	{ "Rsvd3", 29, 3 },
4456	{ "PCIE_DEV_STAT_CNTL", 0x78, 0 },
4457	{ "CorErrRptEn", 0, 1 },
4458	{ "NonFatErrRptEn", 1, 1 },
4459	{ "FatErrRptEn", 2, 1 },
4460	{ "UnSupReqRptEn", 3, 1 },
4461	{ "RlxOrdEn", 4, 1 },
4462	{ "MaxPyldSz", 5, 3 },
4463	{ "ExtTagEn", 8, 1 },
4464	{ "PhantomFuncEn", 9, 1 },
4465	{ "AuxPwrPMEn", 10, 1 },
4466	{ "NoSnoopEn", 11, 1 },
4467	{ "MaxRdReqSz", 12, 3 },
4468	{ "InitiateFLR", 15, 1 },
4469	{ "CorErrDet", 16, 1 },
4470	{ "NonFatErrDet", 17, 1 },
4471	{ "FatErrDet", 18, 1 },
4472	{ "UnSupReqDet", 19, 1 },
4473	{ "AuxPwrDet", 20, 1 },
4474	{ "TxnPnd", 21, 1 },
4475	{ "Rsvd", 22, 10 },
4476	{ "PCIE_LINK_CAP", 0x7c, 0 },
4477	{ "MaxLinkSpeed", 0, 4 },
4478	{ "MaxLinkWidth", 4, 6 },
4479	{ "ASPMSup", 10, 2 },
4480	{ "L0sExitLat", 12, 3 },
4481	{ "L1ExitLat", 15, 3 },
4482	{ "ClkPwrMgmt", 18, 1 },
4483	{ "SurpriseDnErrRptCap", 19, 1 },
4484	{ "DLLActvRptCap", 20, 1 },
4485	{ "LnkBWNotifCap", 21, 1 },
4486	{ "ASPMOptComp", 22, 1 },
4487	{ "Rsvd", 23, 1 },
4488	{ "PortNum", 24, 8 },
4489	{ "PCIE_LINK_STAT_CNTL", 0x80, 0 },
4490	{ "ASPMCtl", 0, 2 },
4491	{ "Rsvd1", 2, 1 },
4492	{ "RCB", 3, 1 },
4493	{ "LinkDisable", 4, 1 },
4494	{ "RetrainLink", 5, 1 },
4495	{ "ComClkCfg", 6, 1 },
4496	{ "ExtendedSync", 7, 1 },
4497	{ "ClkPwrMgmtEn", 8, 1 },
4498	{ "HWAutoWidthDis", 9, 1 },
4499	{ "LnkBWMgmtIntEn", 10, 1 },
4500	{ "LnkAutoBWIntEn", 11, 1 },
4501	{ "Rsvd2", 12, 4 },
4502	{ "CurLinkSpeed", 16, 4 },
4503	{ "NegLinkWidth", 20, 6 },
4504	{ "Rsvd3", 26, 1 },
4505	{ "LnkTraining", 27, 1 },
4506	{ "SlotClkCfg", 28, 1 },
4507	{ "DLLActive", 29, 1 },
4508	{ "LnkBWMgmtStat", 30, 1 },
4509	{ "LnkAutoBWStat", 31, 1 },
4510	{ "PCIE_DEV_CAP2", 0x94, 0 },
4511	{ "CplTORangesSup", 0, 4 },
4512	{ "CplTODisSup", 4, 1 },
4513	{ "ARIFwdSup", 5, 1 },
4514	{ "AtomicOpRouteSup", 5, 1 },
4515	{ "32bAtomicOpCplSup", 7, 1 },
4516	{ "64bAtomicOpCplSup", 8, 1 },
4517	{ "128bCASCplSup", 9, 1 },
4518	{ "NoROPRPRPass", 10, 1 },
4519	{ "LTRMechSupp", 11, 1 },
4520	{ "TPHCplSupp", 12, 2 },
4521	{ "Rsvd1", 14, 4 },
4522	{ "OBFFSupp", 18, 2 },
4523	{ "ExtFmtSupp", 20, 1 },
4524	{ "EndEndTLPPrSupp", 21, 1 },
4525	{ "MaxEndEndTLPPr", 22, 2 },
4526	{ "Rsvd2", 24, 8 },
4527	{ "PCIE_DEV_STAT_CNTL2", 0x98, 0 },
4528	{ "CplTOValue", 0, 4 },
4529	{ "CplTODis", 4, 1 },
4530	{ "ARIFwdEn", 5, 1 },
4531	{ "AtomicOpRqstEn", 6, 1 },
4532	{ "AtomicOpEgBlock", 7, 1 },
4533	{ "IDORqstEn", 8, 1 },
4534	{ "IDOCplEn", 9, 1 },
4535	{ "LTRMechEn", 10, 1 },
4536	{ "Rsvd1", 11, 2 },
4537	{ "OBFFEn", 13, 2 },
4538	{ "EndEndTLPPrBlock", 15, 1 },
4539	{ "Rsvd2", 16, 16 },
4540	{ "PCIE_LINK_CAP2", 0x9c, 0 },
4541	{ "Rsvd1", 0, 1 },
4542	{ "SupLinkSpeeds", 1, 7 },
4543	{ "CrossLinkSup", 8, 1 },
4544	{ "Rsvd2", 9, 23 },
4545	{ "PCIE_LINK_STAT_CNTL2", 0xa0, 0 },
4546	{ "TarLnkSpeed", 0, 4 },
4547	{ "EnterComp", 4, 1 },
4548	{ "HWAutoSpeedDis", 5, 1 },
4549	{ "SelDeEmph", 6, 1 },
4550	{ "TxMargin", 7, 3 },
4551	{ "EnterModComp", 10, 1 },
4552	{ "CompSOS", 11, 1 },
4553	{ "CompDeEmph", 12, 4 },
4554	{ "CurDeEmph", 16, 1 },
4555	{ "EqComplete", 17, 1 },
4556	{ "EqPh1Succ", 18, 1 },
4557	{ "EqPh2Succ", 19, 1 },
4558	{ "EqPh3Succ", 20, 1 },
4559	{ "LinkEqRqst", 21, 1 },
4560	{ "Rsvd", 22, 10 },
4561	{ "PCIE_MSIX_CAP", 0xb0, 0 },
4562	{ "MSIXCapID", 0, 8 },
4563	{ "NextCapPtr", 8, 8 },
4564	{ "TableSize", 16, 11 },
4565	{ "Rsvd", 27, 3 },
4566	{ "FuncMask", 30, 1 },
4567	{ "MSIXEn", 31, 1 },
4568	{ "PCIE_MSIX_TBL_OFST_BIR", 0xb4, 0 },
4569	{ "TblBIR", 0, 3 },
4570	{ "TblOfst", 3, 29 },
4571	{ "PCIE_MSIX_PBA_OFST_BIR", 0xb8, 0 },
4572	{ "PBABIR", 0, 3 },
4573	{ "PBAOfst", 3, 29 },
4574	{ "PCIE_VPD_CAP", 0xd0, 0 },
4575	{ "VPDCapID", 0, 8 },
4576	{ "NextCapPtr", 8, 8 },
4577	{ "VPDAddr", 16, 15 },
4578	{ "VPDFBit", 31, 1 },
4579	{ "PCIE_VPD_DATA", 0xd4, 0 },
4580	{ "Data", 0, 32 },
4581	{ "PCIE_AER_CAP", 0x100, 0 },
4582	{ "AERCapID", 0, 16 },
4583	{ "AERCapVer", 16, 4 },
4584	{ "NextCapPtr", 20, 12 },
4585	{ "PCIE_AER_UNCOR_ERR_STAT", 0x104, 0 },
4586	{ "Undefined", 0, 1 },
4587	{ "Rsvd1", 1, 3 },
4588	{ "DLLProtErr", 4, 1 },
4589	{ "SurpriseDnErr", 5, 1 },
4590	{ "Rsvd2", 6, 6 },
4591	{ "PsndTLP", 12, 1 },
4592	{ "FlowCtlProtErr", 13, 1 },
4593	{ "ComplTO", 14, 1 },
4594	{ "ComplAbort", 15, 1 },
4595	{ "UnExpCpl", 16, 1 },
4596	{ "RcvrOFlow", 17, 1 },
4597	{ "MalTLP", 18, 1 },
4598	{ "ECRCErr", 19, 1 },
4599	{ "UnSupReqErr", 20, 1 },
4600	{ "ACSViol", 21, 1 },
4601	{ "UnIntErr", 22, 1 },
4602	{ "MCBlockTLP", 23, 1 },
4603	{ "AtomicOPEgBlock", 24, 1 },
4604	{ "TLPPrBlockErr", 25, 1 },
4605	{ "Rsvd3", 26, 6 },
4606	{ "PCIE_AER_UNCOR_ERR_MASK", 0x108, 0 },
4607	{ "Rsvd1", 0, 4 },
4608	{ "DLLProtErr", 4, 1 },
4609	{ "SurpriseDnErr", 5, 1 },
4610	{ "Rsvd2", 6, 6 },
4611	{ "PsndTLP", 12, 1 },
4612	{ "FlowCtlProtErr", 13, 1 },
4613	{ "ComplTO", 14, 1 },
4614	{ "ComplAbort", 15, 1 },
4615	{ "UnExpCpl", 16, 1 },
4616	{ "RcvrOFlow", 17, 1 },
4617	{ "MalTLP", 18, 1 },
4618	{ "ECRCErr", 19, 1 },
4619	{ "UnSupReqErr", 20, 1 },
4620	{ "ACSViol", 21, 1 },
4621	{ "UnIntErr", 22, 1 },
4622	{ "MCBlockTLP", 23, 1 },
4623	{ "AtomicOPEgBlock", 24, 1 },
4624	{ "TLPPrBlockErr", 25, 1 },
4625	{ "Rsvd3", 26, 6 },
4626	{ "PCIE_AER_UNCOR_ERR_SEV", 0x10c, 0 },
4627	{ "Rsvd1", 0, 4 },
4628	{ "DLLProtErr", 4, 1 },
4629	{ "SurpriseDnErr", 5, 1 },
4630	{ "Rsvd2", 6, 6 },
4631	{ "PsndTLP", 12, 1 },
4632	{ "FlowCtlProtErr", 13, 1 },
4633	{ "ComplTO", 14, 1 },
4634	{ "ComplAbort", 15, 1 },
4635	{ "UnExpCpl", 16, 1 },
4636	{ "RcvrOFlow", 17, 1 },
4637	{ "MalTLP", 18, 1 },
4638	{ "ECRCErr", 19, 1 },
4639	{ "UnSupReqErr", 20, 1 },
4640	{ "ACSViol", 21, 1 },
4641	{ "UnIntErr", 22, 1 },
4642	{ "MCBlockTLP", 23, 1 },
4643	{ "AtomicOPEgBlock", 24, 1 },
4644	{ "TLPPrBlockErr", 25, 1 },
4645	{ "Rsvd3", 26, 6 },
4646	{ "PCIE_AER_COR_ERR_STAT", 0x110, 0 },
4647	{ "RcvrErr", 0, 1 },
4648	{ "Rsvd1", 1, 5 },
4649	{ "BadTLP", 6, 1 },
4650	{ "BadDLLP", 7, 1 },
4651	{ "RplNumRollOver", 8, 1 },
4652	{ "Rsvd2", 9, 3 },
4653	{ "RplTimerTO", 12, 1 },
4654	{ "AdvNonFatErr", 13, 1 },
4655	{ "CorIntErr", 14, 1 },
4656	{ "HdrLogOFl", 15, 1 },
4657	{ "Rsvd3", 16, 16 },
4658	{ "PCIE_AER_COR_ERR_MASK", 0x114, 0 },
4659	{ "RcvrErr", 0, 1 },
4660	{ "Rsvd1", 1, 5 },
4661	{ "BadTLP", 6, 1 },
4662	{ "BadDLLP", 7, 1 },
4663	{ "RplNumRollOver", 8, 1 },
4664	{ "RplNumRollOver", 9, 3 },
4665	{ "RplTimerTO", 12, 1 },
4666	{ "AdvNonFatErr", 13, 1 },
4667	{ "CorIntErr", 14, 1 },
4668	{ "HdrLogOFl", 15, 1 },
4669	{ "Rsvd3", 16, 16 },
4670	{ "PCIE_AER_CAP_CNTL", 0x118, 0 },
4671	{ "FirstErrPtr", 0, 5 },
4672	{ "ECRCGenCap", 5, 1 },
4673	{ "ECRCGenEn", 6, 1 },
4674	{ "ECRCChkCap", 7, 1 },
4675	{ "ECRCChkEn", 8, 1 },
4676	{ "MultHdrRecCap", 9, 1 },
4677	{ "MultHdrRecEn", 10, 1 },
4678	{ "TLPPrLog", 11, 1 },
4679	{ "Rsvd", 12, 20 },
4680	{ "CIE_AER_HDR_LOG1", 0x11c, 0 },
4681	{ "Hdr1DW", 0, 32 },
4682	{ "CIE_AER_HDR_LOG2", 0x120, 0 },
4683	{ "Hdr2DW", 0, 32 },
4684	{ "CIE_AER_HDR_LOG3", 0x124, 0 },
4685	{ "Hdr3DW", 0, 32 },
4686	{ "CIE_AER_HDR_LOG4", 0x128, 0 },
4687	{ "Hdr4DW", 0, 32 },
4688	{ "PCIE_MFVC_CAP", 0x140, 0 },
4689	{ "MFVCCapID", 0, 16 },
4690	{ "MFVCCapVer", 16, 4 },
4691	{ "NextCapPtr", 20, 12 },
4692	{ "PCIE_MFVC_PORT_VC_CAP1", 0x144, 0 },
4693	{ "ExtVCCount", 0, 3 },
4694	{ "Rsvd1", 3, 1 },
4695	{ "LPExtVCCount", 4, 3 },
4696	{ "Rsvd2", 7, 1 },
4697	{ "RefClk", 8, 2 },
4698	{ "PortArbTblSz", 10, 2 },
4699	{ "Rsvd3", 12, 20 },
4700	{ "PCIE_MFVC_PORT_VC_CAP2", 0x148, 0 },
4701	{ "LoadVCArbTbl", 0, 1 },
4702	{ "VCArbSel", 1, 3 },
4703	{ "Rsvd1", 4, 12 },
4704	{ "PortVCArbStat", 16, 1 },
4705	{ "Rsvd2", 17, 15 },
4706	{ "PCIE_MFVC_VC0_RES_CAP", 0x150, 0 },
4707	{ "PortArbCap", 0, 8 },
4708	{ "Rsvd1", 8, 7 },
4709	{ "RejectSnoopTxns", 15, 1 },
4710	{ "MaxTimeSlots", 16, 7 },
4711	{ "Rsvd2", 23, 1 },
4712	{ "PortArbTblOfst", 24, 8 },
4713	{ "PCIE_MFVC_VC0_RES_CNTL", 0x154, 0 },
4714	{ "TCVCMapBit0", 0, 1 },
4715	{ "TCVCMap", 1, 7 },
4716	{ "Rsvd1", 8, 8 },
4717	{ "LoadPortArbTbl", 16, 1 },
4718	{ "PortArbSel", 17, 3 },
4719	{ "Rsvd2", 20, 4 },
4720	{ "VCID", 24, 3 },
4721	{ "Rsvd3", 27, 4 },
4722	{ "VCEnable", 31, 1 },
4723	{ "PCIE_MFVC_VC0_RES_STAT", 0x158, 0 },
4724	{ "Rsvd1", 0, 16 },
4725	{ "PortArbTblStat", 16, 1 },
4726	{ "VC0NegPnd", 17, 1 },
4727	{ "Rsvd2", 18, 14 },
4728	{ "PCIE_MFVC_VC1_RES_CAP", 0x15c, 0 },
4729	{ "PortArbCap", 0, 8 },
4730	{ "Rsvd1", 8, 7 },
4731	{ "RejectSnoopTxns", 15, 1 },
4732	{ "MaxTimeSlots", 16, 7 },
4733	{ "Rsvd2", 23, 1 },
4734	{ "PortArbTblOfst", 24, 8 },
4735	{ "PCIE_MFVC_VC1_RES_CNTL", 0x160, 0 },
4736	{ "TCVCMap", 0, 8 },
4737	{ "Rsvd1", 8, 8 },
4738	{ "LoadPortArbTbl", 16, 1 },
4739	{ "PortArbSel", 17, 3 },
4740	{ "Rsvd2", 20, 4 },
4741	{ "VCID", 24, 3 },
4742	{ "Rsvd3", 27, 4 },
4743	{ "VCEnable", 31, 1 },
4744	{ "PCIE_MFVC_VC1_RES_STAT", 0x164, 0 },
4745	{ "Rsvd1", 0, 16 },
4746	{ "PortArbTblStat", 16, 1 },
4747	{ "VC1NegPnd", 17, 1 },
4748	{ "Rsvd2", 18, 14 },
4749	{ "PCIE_DSN_CAP", 0x170, 0 },
4750	{ "DSNCapID", 0, 16 },
4751	{ "DSNCapVer", 16, 4 },
4752	{ "NextCapPtr", 20, 12 },
4753	{ "PCIE_DSN_DW1", 0x174, 0 },
4754	{ "DSN1Dw", 0, 32 },
4755	{ "PCIE_DSN_DW2", 0x178, 0 },
4756	{ "DSN2Dw", 0, 32 },
4757	{ "PCIE_PB_CAP_HDR", 0x180, 0 },
4758	{ "PBCapID", 0, 16 },
4759	{ "PBCapVer", 16, 4 },
4760	{ "NextCapPtr", 20, 12 },
4761	{ "PCIE_PB_DATA_SEL", 0x184, 0 },
4762	{ "DataSelReg", 0, 8 },
4763	{ "Rsvd", 8, 24 },
4764	{ "PCIE_PB_DATA_REG", 0x188, 0 },
4765	{ "BasePower", 0, 8 },
4766	{ "DataScale", 8, 2 },
4767	{ "PMSubState", 10, 3 },
4768	{ "PMState", 13, 2 },
4769	{ "Type", 15, 3 },
4770	{ "PowerRail", 18, 3 },
4771	{ "Rsvd", 21, 11 },
4772	{ "PCIE_PB_CAP_REG", 0x18c, 0 },
4773	{ "SysAlloc", 0, 1 },
4774	{ "Rsvd", 1, 31 },
4775	{ "PCIE_ARI_CAP_HDR", 0x190, 0 },
4776	{ "ARICapID", 0, 16 },
4777	{ "ARICapVer", 16, 4 },
4778	{ "NextCapPtr", 20, 12 },
4779	{ "PCIE_ARI_CAP_CNTL", 0x194, 0 },
4780	{ "MFVCFnGrpCap", 0, 1 },
4781	{ "ACSFnGrpCap", 1, 1 },
4782	{ "Rsvd1", 2, 6 },
4783	{ "NextFnNum", 8, 8 },
4784	{ "MFVCFnGrpEn", 16, 1 },
4785	{ "ACSFnGrpEn", 17, 1 },
4786	{ "Rsvd2", 18, 2 },
4787	{ "FnGrp", 20, 3 },
4788	{ "Rsvd3", 23, 9 },
4789	{ "PCIE_SEC_PCIE_EXTENDED_CAP_HDR", 0x1a0, 0 },
4790	{ "PCIeExtCapID", 0, 16 },
4791	{ "PCIeExtCapVer", 16, 4 },
4792	{ "NextCapPtr", 20, 12 },
4793	{ "PCIE_LINK_CNTL3", 0x1a4, 0 },
4794	{ "PerfEql", 0, 1 },
4795	{ "LinkEqlReqIntEn", 1, 1 },
4796	{ "Rsvd", 2, 30 },
4797	{ "PCIE_LANE_ERR_STAT", 0x1a8, 0 },
4798	{ "LaneErrStat", 0, 8 },
4799	{ "Rsvd", 8, 24 },
4800	{ "PCIE_LANE_EQL_CNTL0", 0x1ac, 0 },
4801	{ "Ln0DnPrtXmtrPrst", 0, 4 },
4802	{ "Ln0DnPrtRcvrPrst", 4, 3 },
4803	{ "Ln0UpPrtXmtrPrst", 8, 4 },
4804	{ "Ln0UpPrtRcvrPrst", 12, 3 },
4805	{ "Ln1DnPrtXmtrPrst", 16, 4 },
4806	{ "Ln1DnPrtRcvrPrst", 20, 3 },
4807	{ "Ln1UpPrtXmtrPrst", 24, 4 },
4808	{ "Ln1UpPrtRcvrPrst", 28, 3 },
4809	{ "PCIE_LANE_EQL_CNTL1", 0x1b0, 0 },
4810	{ "Ln2DnPrtXmtrPrst", 0, 4 },
4811	{ "Ln2DnPrtRcvrPrst", 4, 3 },
4812	{ "Ln2UpPrtXmtrPrst", 8, 4 },
4813	{ "Ln2UpPrtRcvrPrst", 12, 3 },
4814	{ "Ln3DnPrtXmtrPrst", 16, 4 },
4815	{ "Ln3DnPrtRcvrPrst", 20, 3 },
4816	{ "Ln3UpPrtXmtrPrst", 24, 4 },
4817	{ "Ln3UpPrtRcvrPrst", 28, 3 },
4818	{ "PCIE_LANE_EQL_CNTL2", 0x1b4, 0 },
4819	{ "Ln4DnPrtXmtrPrst", 0, 4 },
4820	{ "Ln4DnPrtRcvrPrst", 4, 3 },
4821	{ "Ln4UpPrtXmtrPrst", 8, 4 },
4822	{ "Ln4UpPrtRcvrPrst", 12, 3 },
4823	{ "Ln5DnPrtXmtrPrst", 16, 4 },
4824	{ "Ln5DnPrtRcvrPrst", 20, 3 },
4825	{ "Ln5UpPrtXmtrPrst", 24, 4 },
4826	{ "Ln5UpPrtRcvrPrst", 28, 3 },
4827	{"PCIE_LANE_EQL_CNTL3", 0x1b8, 0 },
4828	{ "Ln6DnPrtXmtrPrst", 0, 4 },
4829	{ "Ln6DnPrtRcvrPrst", 4, 3 },
4830	{ "Ln6UpPrtXmtrPrst", 8, 4 },
4831	{ "Ln6UpPrtRcvrPrst", 12, 3 },
4832	{ "Ln7DnPrtXmtrPrst", 16, 4 },
4833	{ "Ln7DnPrtRcvrPrst", 20, 3 },
4834	{ "Ln7UpPrtXmtrPrst", 24, 4 },
4835	{ "Ln7UpPrtRcvrPrst", 28, 3 },
4836	{ "PCIE_SR_CAP_HDR", 0x1c0, 0 },
4837	{ "SRIOVCapID", 0, 16 },
4838	{ "SRIOVCapVer", 16, 4 },
4839	{ "NextCapPtr", 20, 12 },
4840	{ "PCIE_SR_CAP Register", 0x1c4, 0 },
4841	{ "VFMigCap", 0, 1 },
4842	{ "ARICapHierPrsrvd", 1, 1 },
4843	{ "Rsvd", 2, 19 },
4844	{ "VFMigIntMsgNum", 21, 11 },
4845	{ "PCIE_SR_STAT_CNTL", 0x1c8, 0 },
4846	{ "VFEn", 0, 1 },
4847	{ "VFMigEn", 1, 1 },
4848	{ "VFMigIntEn", 2, 1 },
4849	{ "VFMSE", 3, 1 },
4850	{ "ARICapHier", 4, 1 },
4851	{ "Rsvd1", 5, 11 },
4852	{ "VFMigStatus", 16, 1 },
4853	{ "Rsvd2", 17, 15 },
4854	{ "PCIE_SR_INIT_TOT_VFS", 0x1cc, 0 },
4855	{ "InitVFs", 0, 16 },
4856	{ "TotVFs", 16, 16 },
4857	{ "PCIE_SR_NUMVFS_FUNCDEPLINK", 0x1d0, 0 },
4858	{ "NumVFs", 0, 16 },
4859	{ "FuncDepLink", 16, 8 },
4860	{ "PCIE_SR_VF_OFST_STRIDE", 0x1d4 },
4861	{ "FirstVFOfst", 0, 16 },
4862	{ "VFStride", 16, 16 },
4863	{ "PCIE_SR_VF_DEVID", 0x1d8, 0 },
4864	{ "Rsvd", 0, 16 },
4865	{ "VFDevID",  16, 16 },
4866	{ "PCIE_SR_SUPP_PAGE_SIZES", 0x1dc, 0 },
4867	{ "SuppPageSzs", 0, 32 },
4868	{ "PCIE_SR_SYS_PAGE_SIZE", 0x1e0 },
4869	{ "SysPageSz", 0, 32 },
4870	{ "PCIE_SR_VFBAR0", 0x1e4, 0 },
4871	{ "MemSpaceInd", 0, 1 },
4872	{ "Type", 1, 2 },
4873	{ "Rsvd", 3, 9 },
4874	{ "BaseAddress", 12, 20 },
4875	{ "PCIE_SR_VFBAR1", 0x1e8, 0 },
4876	{ "MemSpaceInd", 0, 1 },
4877	{ "Type", 1, 2 },
4878	{ "Rsvd", 3, 9 },
4879	{ "BaseAddress", 12, 20 },
4880	{ "PCIE_SR_VFBAR2", 0x1ec, 0 },
4881	{ "MemSpaceInd", 0, 1 },
4882	{ "Type", 1, 2 },
4883	{ "Rsvd", 3, 9 },
4884	{ "BaseAddress", 12, 20 },
4885	{ "PCIE_SR_VFBAR3", 0x1f0, 0 },
4886	{ "MemSpaceInd", 0, 1 },
4887	{ "Type", 1, 2 },
4888	{ "Rsvd", 3, 9 },
4889	{ "BaseAddress", 12, 20 },
4890	{ "PCIE_SR_VFBAR4", 0x1f4, 0 },
4891	{ "MemSpaceInd", 0, 1 },
4892	{ "Type", 1, 2 },
4893	{ "Rsvd", 3, 9 },
4894	{ "BaseAddress", 12, 20 },
4895	{ "PCIE_SR_VFBAR5", 0x1f8, 0 },
4896	{ "MemSpaceInd", 0, 1 },
4897	{ "Type", 1, 2 },
4898	{ "Rsvd", 3, 9 },
4899	{ "BaseAddress", 12, 20 },
4900	{ "PCIE_SR_MIG_STATE_ARRAY_OFST", 0x1fc, 0 },
4901	{ "Rsvd", 0, 32 },
4902	{ "PCIE_TPH_CAP_HDR", 0x200, 0 },
4903	{ "TPHCap", 0, 16 },
4904	{ "TPHCapVer", 16, 4 },
4905	{ "NextCapPtr", 20, 12 },
4906	{ "PCIE_TPH_REQ_CAP", 0x204, 0 },
4907	{ "NoSTModeSup", 0, 1 },
4908	{ "IntVecModeSup", 1, 1 },
4909	{ "DevSpModeSup", 2, 1 },
4910	{ "ExtTPHReqSup", 8, 1 },
4911	{ "STTblLoc", 9, 2 },
4912	{ "STTblSize", 16, 11 },
4913	{ "PCIE_TPH_REQ_CNTL", 0x208, 0 },
4914	{ "STModeSel", 0, 3 },
4915	{ "TPHRqstEn", 8, 1 },
4916	{ "ExtTPHRqstEn", 9, 1 },
4917	{ NULL }
4918};
4919
4920static struct cudbg_reg_info t5_pm_tx_regs_10021_to_1003c[] = {
4921	{ "PM_TX_FEATURE_EN", 0x10021, 0 },
4922	{ "pio_ch_deficit_ctl_en", 2, 1 },
4923	{ "pio_wrr_based_prftch_en", 1, 1 },
4924	{ "prftch_across_bndle_en", 0, 1 },
4925	{ "PM_TX_T5_PM_TX_INT_ENABLE", 0x10022, 0 },
4926	{ "ospi_overflow3", 7, 1 },
4927	{ "ospi_overflow2", 6, 1 },
4928	{ "ospi_overflow1", 5, 1 },
4929	{ "ospi_overflow0", 4, 1 },
4930	{ "M_IntfPerrEn", 3, 1 },
4931	{ "bundle_len_ParErr_en", 2, 1 },
4932	{ "bundle_len_ovfl_en", 1, 1 },
4933	{ "sdc_err_en", 0, 1 },
4934	{ "PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD0", 0x10023, 0 },
4935	{ "pio_wrr_wait_cnt_thrshld0", 0, 32 },
4936	{ "PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD1", 0x10024, 0 },
4937	{ "pio_wrr_wait_cnt_thrshld1", 0, 32 },
4938	{ "PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD2", 0x10025, 0 },
4939	{ "pio_wrr_wait_cnt_thrshld2", 0, 32 },
4940	{ "PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3", 0x10026, 0 },
4941	{ "pio_wrr_wait_cnt_thrshld3", 0, 32 },
4942	{ "PM_TX_CH0_OSPI_DEFICIT_THRSHLD", 0x10027, 0 },
4943	{ "CH0_OSPI_DEFICIT_THRSHLD", 0, 12 },
4944	{ "PM_TX_CH1_OSPI_DEFICIT_THRSHLD", 0x10028, 0 },
4945	{ "CH1_OSPI_DEFICIT_THRSHLD", 0, 12 },
4946	{ "PM_TX_CH2_OSPI_DEFICIT_THRSHLD", 0x10029, 0 },
4947	{ "CH2_OSPI_DEFICIT_THRSHLD", 0, 12 },
4948	{ "PM_TX_CH3_OSPI_DEFICIT_THRSHLD", 0x1002a, 0 },
4949	{ "CH3_OSPI_DEFICIT_THRSHLD", 0, 12 },
4950	{ "PM_TX_INT_CAUSE_MASK_HALT", 0x1002b, 0 },
4951	{ "INT_CAUSE_MASK", 0, 32 },
4952	{ "PM_TX_DBG_STAT0", 0x1002c, 0 },
4953	{ "rd_i_busy", 29, 1 },
4954	{ "wr_o_busy", 28, 1 },
4955	{ "m_to_o_busy", 27, 1 },
4956	{ "i_to_m_busy", 26, 1 },
4957	{ "pcmd_fb_only", 25, 1 },
4958	{ "pcmd_mem", 24, 1 },
4959	{ "pcmd_bypass", 23, 1 },
4960	{ "pcmd_eop2", 22, 1 },
4961	{ "pcmd_eop", 21, 1 },
4962	{ "pcmd_end_bundle", 20, 1 },
4963	{ "pcmd_fb_cmd", 16, 4 },
4964	{ "cur_pcmd_len", 0, 16 },
4965	{ "PM_TX_DBG_STAT1", 0x1002d, 0 },
4966	{ "pcmd_mem0", 31, 1 },
4967	{ "free_oespi_cnt0", 19, 12 },
4968	{ "pcmd_flit_len0", 7, 12 },
4969	{ "pcmd_cmd0", 3, 4 },
4970	{ "ofifo_full0", 2, 1 },
4971	{ "gcsum_drdy0", 1, 1 },
4972	{ "Bypass0", 0, 1 },
4973	{ "PM_TX_DBG_STAT2", 0x1002e, 0 },
4974	{ "pcmd_mem1", 31, 1 },
4975	{ "free_oespi_cnt1", 19, 12 },
4976	{ "pcmd_flit_len1", 7, 12 },
4977	{ "pcmd_cmd1", 3, 4 },
4978	{ "ofifo_full1", 2, 1 },
4979	{ "gcsum_drdy1", 1, 1 },
4980	{ "Bypass1", 0, 1 },
4981	{ "PM_TX_DBG_STAT3", 0x1002f, 0 },
4982	{ "pcmd_mem2", 31, 1 },
4983	{ "free_oespi_cnt2", 19, 12 },
4984	{ "pcmd_flit_len2", 7, 12 },
4985	{ "pcmd_cmd2", 3, 4 },
4986	{ "ofifo_full2", 2, 1 },
4987	{ "gcsum_drdy2", 1, 1 },
4988	{ "Bypass2", 0, 1 },
4989	{ "PM_TX_DBG_STAT4", 0x10030, 0 },
4990	{ "pcmd_mem3", 31, 1 },
4991	{ "free_oespi_cnt3", 19, 12 },
4992	{ "pcmd_flit_len3", 7, 12 },
4993	{ "pcmd_cmd3", 3, 4 },
4994	{ "ofifo_full3", 2, 1 },
4995	{ "gcsum_drdy3", 1, 1 },
4996	{ "Bypass3", 0, 1 },
4997	{ "PM_TX_DBG_STAT5", 0x10031, 0 },
4998	{ "set_pcmd_res_rdy_rd", 24, 4 },
4999	{ "issued_pref_rd_er_clr", 20, 4 },
5000	{ "issued_pref_rd", 16, 4},
5001	{ "pcmd_res_rdy", 12, 4 },
5002	{ "db_vld", 11, 1 },
5003	{ "inject0_drdy", 10, 1 },
5004	{ "inject1_drdy", 9, 1 },
5005	{ "first_bundle", 5, 4 },
5006	{ "gcsum_more_than_2_left", 1, 5 },
5007	{ "sdc_drdy", 0, 1 },
5008	{ "PM_TX_DBG_STAT6", 0x10032, 0 },
5009	{ "pcmd_vld", 31, 1 },
5010	{ "pcmd_ch", 29, 2 },
5011	{ "state_machine_loc", 24, 4 },
5012	{ "icspi_TxValid", 20, 4 },
5013	{ "icspi_TxFull", 16, 4 },
5014	{ "PCMD_srdy", 12, 4 },
5015	{ "PCMD_drdy", 8, 4 },
5016	{ "pcmd_cmd", 4, 4 },
5017	{ "oefifo_full3", 3, 1 },
5018	{ "oefifo_full2", 2, 1 },
5019	{ "oefifo_full1", 1, 1 },
5020	{ "oefifo_full0", 0, 1 },
5021	{ "PM_TX_DBG_STAT7", 0x10033, 0 },
5022	{ "icspi_RxValid", 28, 4 },
5023	{ "icspi_RxFull", 24, 4 },
5024	{ "oespi_valid", 20, 4 },
5025	{ "oespi_full", 16, 4 },
5026	{ "C_RxValid", 12, 4 },
5027	{ "C_RxAFull", 8, 4 },
5028	{ "E_TxValid3", 7, 1 },
5029	{ "E_TxValid2", 6, 1 },
5030	{ "E_TxValid1", 5, 1 },
5031	{ "E_TxValid0", 4, 1 },
5032	{ "E_TxFull3", 3, 1 },
5033	{ "E_TxFull2", 2, 1 },
5034	{ "E_TxFull1", 1, 1 },
5035	{ "E_TxFull0", 0, 1 },
5036	{ "PM_TX_DBG_STAT8", 0x10034, 0 },
5037	{ "mc_rsp_fifo_cnt", 24, 2 },
5038	{ "pcmd_free_cnt0", 14, 10 },
5039	{ "pcmd_free_cnt1", 4, 10 },
5040	{ "M_ReqAddrRdy", 3, 1 },
5041	{ "M_ReqWrite", 2, 1 },
5042	{ "M_ReqDataVld", 1, 1 },
5043	{ "M_ReqDataRdy", 0, 1 },
5044	{ "PM_TX_DBG_STAT9", 0x10035, 0 },
5045	{ "pcmd_free_cnt2", 10, 10 },
5046	{ "pcmd_free_cnt3", 0, 10 },
5047	{ "PM_TX_DBG_STAT10", 0x10036, 0 },
5048	{ "In_Eop_Cnt3", 28, 4 },
5049	{ "In_Eop_Cnt2", 24, 4 },
5050	{ "In_Eop_Cnt1", 20, 4 },
5051	{ "In_Eop_Cnt0", 16, 4 },
5052	{ "In_Sop_Cnt3", 12, 4 },
5053	{ "In_Sop_Cnt2", 8, 4 },
5054	{ "In_Sop_Cnt1", 4, 4 },
5055	{ "In_Sop_Cnt0", 0, 4 },
5056	{ "PM_TX_DBG_STAT11", 0x10037, 0 },
5057	{ "Out_Eop_Cnt3", 28, 4 },
5058	{ "Out_Eop_Cnt2", 24, 4 },
5059	{ "Out_Eop_Cnt1", 20, 4 },
5060	{ "Out_Eop_Cnt0", 16, 4 },
5061	{ "Out_Sop_Cnt3", 12, 4 },
5062	{ "Out_Sop_Cnt2", 8, 4 },
5063	{ "Out_Sop_Cnt1", 4, 4 },
5064	{ "Out_Sop_Cnt0", 0, 4 },
5065	{ "PM_TX_DBG_STAT12", 0x10038, 0 },
5066	{ "dbg_stat12", 0, 32 },
5067	{ "PM_TX_DBG_STAT13", 0x10039, 0 },
5068	{ "ch_deficit_blowed", 31, 1 },
5069	{ "rsvd_13_1", 28, 3 },
5070	{ "ch1_deficit", 16, 12},
5071	{ "rsvd_13", 12, 4 },
5072	{ "ch0_deficit", 0, 12 },
5073	{ "PM_TX_DBG_STAT14", 0x1003a, 0 },
5074	{ "rsvd_14_1", 28, 4 },
5075	{ "ch3_deficit", 16, 12 },
5076	{ "rsvd_14", 12, 4 },
5077	{ "ch2_deficit", 0, 12 },
5078	{ "PM_TX_DBG_STAT15", 0x1003b, 0 },
5079	{ "bundle_len_srdy", 28, 4 },
5080	{ "bundle_len1", 16, 12 },
5081	{ "rsvd_15", 12, 4 },
5082	{ "bundle_len0", 0, 12 },
5083	{ "PM_TX_DBG_STAT16", 0x1003c, 0 },
5084	{ "rsvd_16_1", 28, 4 },
5085	{ "bundle_len3", 16, 12 },
5086	{ "rsvd_16", 12, 4 },
5087	{ "bundle_len2", 0, 12 },
5088	{ NULL }
5089};
5090
5091static struct cudbg_cntxt_field t6_egress_cntxt[] = {
5092	{ "DCA_ST:", 181, 191, 0, 0 },
5093	{ "StatusPgNS:", 180, 180, 0, 0 },
5094	{ "StatusPgRO:", 179, 179, 0, 0 },
5095	{ "FetchNS:", 178, 178, 0, 0 },
5096	{ "FetchRO:", 177, 177, 0, 0 },
5097	{ "Valid:", 176, 176, 0, 0 },
5098	{ "ReschedulePending_1:", 175, 175, 0, 0 },
5099	{ "PCIeDataChannel:", 174, 174, 0, 0 },
5100	{ "StatusPgTPHintEn:", 173, 173, 0, 0 },
5101	{ "StatusPgTPHint:", 171, 172, 0, 0 },
5102	{ "FetchTPHintEn:", 170, 170, 0, 0 },
5103	{ "FetchTPHint:", 168, 169, 0, 0 },
5104	{ "FCThreshOverride:", 167, 167, 0, 0 },
5105	{ "WRLength:", 162, 166, 0, 0 },
5106	{ "WRLengthKnown:", 161, 161, 9, 1 },
5107	{ "ReschedulePending:", 160, 160, 0, 0 },
5108	{ "TimerIx:", 157, 159, 0, 0 },
5109	{ "FetchBurstMin:", 156, 157, 4, 1},
5110	{ "FLMPacking:", 155, 155, 0, 0 },
5111	{ "FetchBurstMax:", 153, 154, 0, 0 },
5112	{ "uPToken:", 133, 152, 0, 0 },
5113	{ "uPTokenEn:", 132, 132, 0, 0 },
5114	{ "UserModeIO:", 131, 131, 0, 0 },
5115	{ "uPFLCredits:", 123, 130, 0, 0 },
5116	{ "uPFLCreditEn:", 122, 122, 0, 0 },
5117	{ "FID:", 111, 121, 0, 0 },
5118	{ "HostFCMode:", 109, 110, 0, 0 },
5119	{ "HostFCOwner:", 108, 108, 0, 0 },
5120	{ "CIDXFlushThresh:", 105, 107, 0, 1 },
5121	{ "CIDX:", 89, 104, 0, 0 },
5122	{ "PIDX:", 73, 88, 0, 0 },
5123	{ "BaseAddress:", 18, 72, 9, 0 },
5124	{ "QueueSize:", 2, 17, 0, 0 },
5125	{ "QueueType:", 1, 1, 0, 0 },
5126	{ "CachePriority:", 0, 0, 0 },
5127	{ NULL }
5128};
5129
5130static struct cudbg_cntxt_field t5_egress_cntxt[] = {
5131	{ "DCA_ST:", 181, 191, 0, 0 },
5132	{ "StatusPgNS:", 180, 180, 0, 0 },
5133	{ "StatusPgRO:", 179, 179, 0, 0 },
5134	{ "FetchNS:", 178, 178, 0, 0 },
5135	{ "FetchRO:", 177, 177, 0, 0 },
5136	{ "Valid:", 176, 176, 0, 0 },
5137	{ "PCIeDataChannel:", 174, 175, 0, 0 },
5138	{ "StatusPgTPHintEn:", 173, 173, 0, 0 },
5139	{ "StatusPgTPHint:", 171, 172, 0, 0 },
5140	{ "FetchTPHintEn:", 170, 170, 0, 0 },
5141	{ "FetchTPHint:", 168, 169, 0, 0 },
5142	{ "FCThreshOverride:", 167, 167, 0, 0 },
5143	{ "WRLength:", 162, 166, 0, 0 },
5144	{ "WRLengthKnown:", 161, 161, 9, 1 },
5145	{ "ReschedulePending:", 160, 160, 0, 0 },
5146	{ "OnChipQueue:", 159, 159, 0, 0 },
5147	{ "FetchSizeMode:", 158, 158, 0, 0 },
5148	{ "FetchBurstMin:", 156, 157, 4, 1},
5149	{ "FLMPacking:", 155, 155, 0, 0 },
5150	{ "FetchBurstMax:", 153, 154, 0, 0 },
5151	{ "uPToken:", 133, 152, 0, 0 },
5152	{ "uPTokenEn:", 132, 132, 0, 0 },
5153	{ "UserModeIO:", 131, 131, 0, 0 },
5154	{ "uPFLCredits:", 123, 130, 0, 0 },
5155	{ "uPFLCreditEn:", 122, 122, 0, 0 },
5156	{ "FID:", 111, 121, 0, 0 },
5157	{ "HostFCMode:", 109, 110, 0, 0 },
5158	{ "HostFCOwner:", 108, 108, 0, 0 },
5159	{ "CIDXFlushThresh:", 105, 107, 0, 1 },
5160	{ "CIDX:", 89, 104, 0, 0 },
5161	{ "PIDX:", 73, 88, 0, 0 },
5162	{ "BaseAddress:", 18, 72, 9, 0 },
5163	{ "QueueSize:", 2, 17, 0, 0 },
5164	{ "QueueType:", 1, 1, 0, 0 },
5165	{ "CachePriority:", 0, 0, 0 },
5166	{ NULL }
5167};
5168
5169static struct cudbg_cntxt_field t6_ingress_cntxt[] = {
5170	{ "SP_NS:", 158, 158 },
5171	{ "SP_RO:", 157, 157 },
5172	{ "SP_TPHintEn:", 156, 156 },
5173	{ "SP_TPHint:", 154, 155 },
5174	{ "DCA_ST:", 143, 153 },
5175	{ "ISCSICoalescing:", 142, 142 },
5176	{ "Queue_Valid:", 141, 141 },
5177	{ "TimerPending:", 140, 140 },
5178	{ "DropRSS:", 139, 139 },
5179	{ "PCIeChannel:", 137, 138 },
5180	{ "SEInterruptArmed:", 136, 136 },
5181	{ "CongestionMgtEnable:", 135, 135 },
5182	{ "NoSnoop:", 134, 134 },
5183	{ "RelaxedOrdering:", 133, 133 },
5184	{ "GTSmode:", 132, 132 },
5185	{ "TPHintEn:", 131, 131 },
5186	{ "TPHint:", 129, 130 },
5187	{ "UpdateScheduling:", 128, 128 },
5188	{ "UpdateDelivery:", 126, 127 },
5189	{ "InterruptSent:", 125, 125 },
5190	{ "InterruptIDX:", 114, 124 },
5191	{ "InterruptDestination:", 113, 113 },
5192	{ "InterruptArmed:", 112, 112 },
5193	{ "RxIntCounter:", 106, 111 },
5194	{ "RxIntCounterThreshold:", 104, 105 },
5195	{ "Generation:", 103, 103 },
5196	{ "BaseAddress:", 48, 102, 9, 0 },
5197	{ "PIDX:", 32, 47 },
5198	{ "CIDX:", 16, 31 },
5199	{ "QueueSize:", 4, 15, 4, 0 },
5200	{ "QueueEntrySize:", 2, 3, 4, 1 },
5201	{ "QueueEntryOverride:", 1, 1 },
5202	{ "CachePriority:", 0, 0 },
5203	{ NULL }
5204};
5205
5206static struct cudbg_cntxt_field t5_ingress_cntxt[] = {
5207	{ "DCA_ST:", 143, 153 },
5208	{ "ISCSICoalescing:", 142, 142 },
5209	{ "Queue_Valid:", 141, 141 },
5210	{ "TimerPending:", 140, 140 },
5211	{ "DropRSS:", 139, 139 },
5212	{ "PCIeChannel:", 137, 138 },
5213	{ "SEInterruptArmed:", 136, 136 },
5214	{ "CongestionMgtEnable:", 135, 135 },
5215	{ "NoSnoop:", 134, 134 },
5216	{ "RelaxedOrdering:", 133, 133 },
5217	{ "GTSmode:", 132, 132 },
5218	{ "TPHintEn:", 131, 131 },
5219	{ "TPHint:", 129, 130 },
5220	{ "UpdateScheduling:", 128, 128 },
5221	{ "UpdateDelivery:", 126, 127 },
5222	{ "InterruptSent:", 125, 125 },
5223	{ "InterruptIDX:", 114, 124 },
5224	{ "InterruptDestination:", 113, 113 },
5225	{ "InterruptArmed:", 112, 112 },
5226	{ "RxIntCounter:", 106, 111 },
5227	{ "RxIntCounterThreshold:", 104, 105 },
5228	{ "Generation:", 103, 103 },
5229	{ "BaseAddress:", 48, 102, 9, 0 },
5230	{ "PIDX:", 32, 47 },
5231	{ "CIDX:", 16, 31 },
5232	{ "QueueSize:", 4, 15, 4, 0 },
5233	{ "QueueEntrySize:", 2, 3, 4, 1 },
5234	{ "QueueEntryOverride:", 1, 1 },
5235	{ "CachePriority:", 0, 0 },
5236	{ NULL }
5237};
5238
5239static struct cudbg_cntxt_field t5_cnm_cntxt[] = {
5240	{ "CngMPSEnable:", 21, 21 },
5241	{ "CngTPMode:", 19, 20 },
5242	{ "CngDBPHdr:", 18, 18 },
5243	{ "CngDBPData:", 17, 17 },
5244	{ "CngIMSG:", 16, 16 },
5245	{ "CngChMap:", 0, 15, 0, 0 },
5246	{ NULL }
5247};
5248
5249static struct cudbg_cntxt_field t6_flm_cntxt[] = {
5250	{ "Valid:", 89, 89 },
5251	{ "SplitLenMode:", 87, 88 },
5252	{ "TPHintEn:", 86, 86 },
5253	{ "TPHint:", 84, 85 },
5254	{ "NoSnoop:", 83, 83 },
5255	{ "RelaxedOrdering:", 82, 82 },
5256	{ "DCA_ST:", 71, 81 },
5257	{ "EQid:", 54, 70 },
5258	{ "SplitEn:", 52, 53 },
5259	{ "PadEn:", 51, 51 },
5260	{ "PackEn:", 50, 50 },
5261	{ "Cache_Lock :", 49, 49 },
5262	{ "CongDrop:", 48, 48 },
5263	{ "Inflifght:", 47, 47 },
5264	{ "CongEn:", 46, 46 },
5265	{ "CongMode:", 45, 45 },
5266	{ "PackOffset:", 20, 39 },
5267	{ "CIDX:", 8, 15 },
5268	{ "PIDX:", 0, 7 },
5269	{ NULL }
5270};
5271
5272static struct cudbg_cntxt_field t5_flm_cntxt[] = {
5273	{ "Valid:", 89, 89 },
5274	{ "SplitLenMode:", 87, 88 },
5275	{ "TPHintEn:", 86, 86 },
5276	{ "TPHint:", 84, 85 },
5277	{ "NoSnoop:", 83, 83 },
5278	{ "RelaxedOrdering:", 82, 82 },
5279	{ "DCA_ST:", 71, 81 },
5280	{ "EQid:", 54, 70 },
5281	{ "SplitEn:", 52, 53 },
5282	{ "PadEn:", 51, 51 },
5283	{ "PackEn:", 50, 50 },
5284	{ "Cache_Lock :", 49, 49 },
5285	{ "CongDrop:", 48, 48 },
5286	{ "PackOffset:", 16, 47 },
5287	{ "CIDX:", 8, 15 },
5288	{ "PIDX:", 0, 7 },
5289	{ NULL }
5290};
5291
5292static struct cudbg_reg_info t6_hma_regs_a000_to_a01f[] = {
5293	{ "HMAT6_DEBUG_FSM_0", 0xa000, 0 },
5294	{ "edc_fsm", 18, 5 },
5295	{ "ras_fsm_slv", 15, 3 },
5296	{ "fc_fsm", 10, 5 },
5297	{ "cookie_arb_fsm", 8, 2 },
5298	{ "pcie_chunk_fsm", 6, 2 },
5299	{ "wtransfer_fsm", 4, 2 },
5300	{ "wd_fsm", 2, 2 },
5301	{ "rd_fsm", 0, 2 },
5302	{ "HMAT6_DEBUG_FSM_1", 0xa001, 0 },
5303	{ "sync_fsm", 11, 10 },
5304	{ "ochk_fsm", 9, 2 },
5305	{ "tlb_fsm", 5, 4 },
5306	{ "pio_fsm", 0, 5 },
5307	{ "HMAT6_DEBUG_PCIE_INTF", 0xa002, 0 },
5308	{ "H_ReqVld", 28, 1 },
5309	{ "H_ReqFull", 27, 1 },
5310	{ "H_ReqSOP", 26, 1 },
5311	{ "H_ReqEOP", 25, 1 },
5312	{ "H_RspVld", 24, 1 },
5313	{ "H_RspFull", 23, 1 },
5314	{ "H_RspSOP", 22, 1 },
5315	{ "H_RspEOP", 21, 1 },
5316	{ "H_RspErr", 20, 1 },
5317	{ "pcie_cmd_avail", 19, 1 },
5318	{ "pcie_cmd_rdy", 18, 1 },
5319	{ "pcie_wnr", 17, 1 },
5320	{ "pcie_len", 9, 8 },
5321	{ "pcie_trwdat_rdy", 8, 1 },
5322	{ "pcie_trwdat_avail", 7, 1 },
5323	{ "pcie_trwsop", 6, 1 },
5324	{ "pcie_trweop", 5, 1 },
5325	{ "pcie_trrdat_rdy", 4, 1 },
5326	{ "pcie_trrdat_avail", 3, 1 },
5327	{ "pcie_trrsop", 2, 1 },
5328	{ "pcie_trreop", 1, 1 },
5329	{ "pcie_trrerr", 0, 1 },
5330	{ "HMAT6_DEBUG_PCIE_ADDR_INTERNAL_LO", 0xa003, 0 },
5331	{ "pcie_addr_lo", 0, 32 },
5332	{ "HMAT6_DEBUG_PCIE_ADDR_INTERNAL_HI", 0xa004, 0 },
5333	{ "pcie_addr_hi", 0, 32 },
5334	{ "HMAT6_DEBUG_PCIE_REQ_DATA_EXTERNAL", 0xa005, 0 },
5335	{ "ReqData2", 24, 8 },
5336	{ "ReqData1", 21, 3 },
5337	{ "ReqData0", 0, 21 },
5338	{ "HMAT6_DEBUG_PCIE_RSP_DATA_EXTERNAL", 0xa006, 0 },
5339	{ "RspData3", 24, 8 },
5340	{ "RspData2", 16, 8 },
5341	{ "RspData1", 8, 8 },
5342	{ "RspData0", 0, 8 },
5343	{ "HMAT6_DEBUG_MA_SLV_CTL", 0xa007, 0 },
5344	{ "ma_cmd_avail", 19, 1 },
5345	{ "ma_clnt", 15, 4 },
5346	{ "ma_wnr", 14, 1 },
5347	{ "ma_len", 6, 8 },
5348	{ "ma_mst_rd", 5, 1 },
5349	{ "ma_mst_vld", 4, 1 },
5350	{ "ma_mst_err", 3, 1 },
5351	{ "mas_tlb_req", 2, 1 },
5352	{ "mas_tlb_ack", 1, 1 },
5353	{ "mas_tlb_err", 0, 1 },
5354	{ "HMAT6_DEBUG_MA_SLV_ADDR_INTERNAL", 0xa008, 0 },
5355	{ "ma_addr", 0, 32 },
5356	{ "HMAT6_DEBUG_TLB_HIT_ENTRY", 0xa009, 0 },
5357	{ "tlb_hit_entry", 0, 32 },
5358	{ "HMAT6_DEBUG_TLB_HIT_CNT", 0xa00a, 0 },
5359	{ "tlb_hit_cnt", 0, 32 },
5360	{ "HMAT6_DEBUG_TLB_MISS_CNT", 0xa00b, 0 },
5361	{ "tlb_miss_cnt", 0, 32 },
5362	{ "HMAT6_DEBUG_PAGE_TBL_LKP_CTL", 0xa00c, 0 },
5363	{ "lkp_req_vld", 4, 1 },
5364	{ "lkp_desc_sel", 1, 4 },
5365	{ "lkp_rsp_vld", 0, 1 },
5366	{ "HMAT6_DEBUG_PAGE_TBL_LKP_REQ_ADDR", 0xa00d, 0 },
5367	{ "lkp_req_addr", 0, 32 },
5368	{ "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_0", 0xa00e, 0 },
5369	{ "lkp_rsp_0", 0, 32, },
5370	{ "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_1", 0xa00f, 0 },
5371	{ "lkp_rsp_1", 0, 32 },
5372	{ "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_2", 0xa010, 0 },
5373	{ "lkp_rsp_2", 0, 32 },
5374	{ "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_3", 0xa011, 0 },
5375	{ "lkp_rsp_3", 0, 32 },
5376	{ "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_4", 0xa012, 0 },
5377	{ "lkp_rsp_4", 0, 32 },
5378	{ "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_5", 0xa013, 0 },
5379	{ "lkp_rsp_5", 0, 32 },
5380	{ "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_6", 0xa014, 0 },
5381	{ "lkp_rsp_6", 0, 32 },
5382	{ "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_7", 0xa015, 0 },
5383	{ "lkp_rsp_7", 0, 32 },
5384	{ "HMAT6_DEBUG_PHYS_DESC_INTERNAL_LO", 0xa016, 0 },
5385	{ "paddr_lo", 0, 32 },
5386	{ "HMAT6_DEBUG_PCIE_RD_REQ_CNT_LO", 0xa017, 0 },
5387	{ "rd_req_cnt_lo", 0, 32 },
5388	{ "HMAT6_DEBUG_PCIE_RD_REQ_CNT_HI", 0xa018, 0 },
5389	{ "rd_req_cnt_hi", 0, 32 },
5390	{ "HMAT6_DEBUG_PCIE_WR_REQ_CNT_LO", 0xa019, 0 },
5391	{ "wr_req_cnt_lo", 0, 32 },
5392	{ "HMAT6_DEBUG_PCIE_WR_REQ_CNT_HI", 0xa01a, 0 },
5393	{ "wr_req_cnt_hi", 0, 32 },
5394	{ "HMAT6_DEBUG_PCIE_RD_DATA_CYC_CNT_LO", 0xa01b, 0 },
5395	{ "rd_data_cnt_lo", 0, 32 },
5396	{ "HMAT6_DEBUG_PCIE_RD_DATA_CYC_CNT_HI", 0xa01c, 0 },
5397	{ "rd_data_cnt_hi", 0, 32 },
5398	{ "HMAT6_DEBUG_PCIE_WR_DATA_CYC_CNT_LO", 0xa01d, 0 },
5399	{ "wr_data_cnt_lo", 0, 32 },
5400	{ "HMAT6_DEBUG_PCIE_WR_DATA_CYC_CNT_HI", 0xa01e, 0 },
5401	{ "wr_data_cnt_hi", 0, 32 },
5402	{ "HMAT6_DEBUG_PCIE_SOP_EOP_CNT", 0xa01f, 0 },
5403	{ "wr_eop_cnt", 16, 8 },
5404	{ "rd_sop_cnt", 8, 8 },
5405	{ "rd_eop_cnt", 0, 8 },
5406	{ NULL }
5407};
5408
5409static struct cudbg_reg_info t6_ma_regs_a000_to_a016[] = {
5410	{ "MA_SGE_THREAD_0_CLIENT_INTERFACE_EXTERNAL", 0xa000, 0 },
5411	{ "CmdVld0", 31, 1 },
5412	{ "CmdRdy0", 30, 1 },
5413	{ "CmdType0", 29, 1 },
5414	{ "CmdLen0", 21, 8 },
5415	{ "CmdAddr0", 8, 13 },
5416	{ "WrDataVld0", 7, 1 },
5417	{ "WrDataRdy0", 6, 1 },
5418	{ "RdDataRdy0", 5, 1 },
5419	{ "RdDataVld0", 4, 1 },
5420	{ "RdData0", 0, 4 },
5421	{ "MA_SGE_THREAD_1_CLIENT_INTERFACE_EXTERNAL", 0xa001, 0 },
5422	{ "CmdVld1", 31, 1 },
5423	{ "CmdRdy1", 30, 1 },
5424	{ "CmdType1", 29, 1 },
5425	{ "CmdLen1", 21, 8 },
5426	{ "CmdAddr1", 8, 13 },
5427	{ "WrDataVld1", 7, 1 },
5428	{ "WrDataRdy1", 6, 1 },
5429	{ "RdDataRdy1", 5, 1 },
5430	{ "RdDataVld1", 4, 1 },
5431	{ "RdData1", 0, 4 },
5432	{ "MA_ULP_TX_CLIENT_INTERFACE_EXTERNAL", 0xa002, 0 },
5433	{ "CmdVld2", 31, 1 },
5434	{ "CmdRdy2", 30, 1 },
5435	{ "CmdType2", 29, 1 },
5436	{ "CmdLen2", 21, 8 },
5437	{ "CmdAddr2", 8, 13 },
5438	{ "WrDataVld2", 7, 1 },
5439	{ "WrDataRdy2", 6, 1 },
5440	{ "RdDataRdy2", 5, 1 },
5441	{ "RdDataVld2", 4, 1 },
5442	{ "RdData2", 0, 4 },
5443	{ "MA_ULP_RX_CLIENT_INTERFACE_EXTERNAL", 0xa003, 0 },
5444	{ "CmdVld3", 31, 1 },
5445	{ "CmdRdy3", 30, 1 },
5446	{ "CmdType3", 29, 1 },
5447	{ "CmdLen3", 21, 8 },
5448	{ "CmdAddr3", 8, 13 },
5449	{ "WrDataVld3", 7, 1 },
5450	{ "WrDataRdy3", 6, 1 },
5451	{ "RdDataRdy3", 5, 1 },
5452	{ "RdDataVld3", 4, 1 },
5453	{ "RdData3", 0, 4 },
5454	{ "MA_ULP_TX_RX_CLIENT_INTERFACE_EXTERNAL", 0xa004, 0 },
5455	{ "CmdVld4", 31, 1 },
5456	{ "CmdRdy4", 30, 1 },
5457	{ "CmdType4", 29, 1 },
5458	{ "CmdLen4", 21, 8 },
5459	{ "CmdAddr4", 8, 13 },
5460	{ "WrDataVld4", 7, 1 },
5461	{ "WrDataRdy4", 6, 1 },
5462	{ "RdDataRdy4", 5, 1 },
5463	{ "RdDataVld4", 4, 1 },
5464	{ "RdData4", 0, 4 },
5465	{ "MA_TP_THREAD_0_CLIENT_INTERFACE_EXTERNAL", 0xa005, 0 },
5466	{ "CmdVld5", 31, 1 },
5467	{ "CmdRdy5", 30, 1 },
5468	{ "CmdType5", 29, 1 },
5469	{ "CmdLen5", 21, 8 },
5470	{ "CmdAddr5", 8, 13 },
5471	{ "WrDataVld5", 7, 1 },
5472	{ "WrDataRdy5", 6, 1 },
5473	{ "RdDataRdy5", 5, 1 },
5474	{ "RdDataVld5", 4, 1 },
5475	{ "RdData5", 0, 4 },
5476	{ "MA_TP_THREAD_1_CLIENT_INTERFACE_EXTERNAL", 0xa006, 0 },
5477	{ "CmdVld6", 31, 1 },
5478	{ "CmdRdy6", 30, 1 },
5479	{ "CmdType6", 29, 1 },
5480	{ "CmdLen6", 21, 8 },
5481	{ "CmdAddr6", 8, 13 },
5482	{ "WrDataVld6", 7, 1 },
5483	{ "WrDataRdy6", 6, 1 },
5484	{ "RdDataRdy6", 5, 1 },
5485	{ "RdDataVld6", 4, 1 },
5486	{ "RdData6", 0, 4 },
5487	{ "MA_LE_CLIENT_INTERFACE_EXTERNAL", 0xa007, 0 },
5488	{ "CmdVld7", 31, 1 },
5489	{ "CmdRdy7", 30, 1 },
5490	{ "CmdType7", 29, 1 },
5491	{ "CmdLen7", 21, 8 },
5492	{ "CmdAddr7", 8, 13 },
5493	{ "WrDataVld7", 7, 1 },
5494	{ "WrDataRdy7", 6, 1 },
5495	{ "RdDataRdy7", 5, 1 },
5496	{ "RdDataVld7", 4, 1 },
5497	{ "RdData7", 0, 4 },
5498	{ "MA_CIM_CLIENT_INTERFACE_EXTERNAL", 0xa008, 0 },
5499	{ "CmdVld8", 31, 1 },
5500	{ "CmdRdy8", 30, 1 },
5501	{ "CmdType8", 29, 1 },
5502	{ "CmdLen8", 21, 8 },
5503	{ "CmdAddr8", 8, 13 },
5504	{ "WrDataVld8", 7, 1 },
5505	{ "WrDataRdy8", 6, 1 },
5506	{ "RdDataRdy8", 5, 1 },
5507	{ "RdDataVld8", 4, 1 },
5508	{ "RdData8", 0, 4 },
5509	{ "MA_PCIE_CLIENT_INTERFACE_EXTERNAL", 0xa009, 0 },
5510	{ "CmdVld9", 31, 1 },
5511	{ "CmdRdy9", 30, 1 },
5512	{ "CmdType9", 29, 1 },
5513	{ "CmdLen9", 21, 8 },
5514	{ "CmdAddr9", 8, 13 },
5515	{ "WrDataVld9", 7, 1 },
5516	{ "WrDataRdy9", 6, 1 },
5517	{ "RdDataRdy9", 5, 1 },
5518	{ "RdDataVld9", 4, 1 },
5519	{ "RdData9", 0, 4 },
5520	{ "MA_PM_TX_CLIENT_INTERFACE_EXTERNAL", 0xa00a, 0 },
5521	{ "CmdVld10", 31, 1 },
5522	{ "CmdRdy10", 30, 1 },
5523	{ "CmdType10", 29, 1 },
5524	{ "CmdLen10", 21, 8 },
5525	{ "CmdAddr10", 8, 13 },
5526	{ "WrDataVld10", 7, 1 },
5527	{ "WrDataRdy10", 6, 1 },
5528	{ "RdDataRdy10", 5, 1 },
5529	{ "RdDataVld10", 4, 1 },
5530	{ "RdData10", 0, 4 },
5531	{ "MA_PM_RX_CLIENT_INTERFACE_EXTERNAL", 0xa00b, 0 },
5532	{ "CmdVld11", 31, 1 },
5533	{ "CmdRdy11", 30, 1 },
5534	{ "CmdType11", 29, 1 },
5535	{ "CmdLen11", 21, 8 },
5536	{ "CmdAddr11", 8, 13 },
5537	{ "WrDataVld11", 7, 1 },
5538	{ "WrDataRdy11", 6, 1 },
5539	{ "RdDataRdy11", 5, 1 },
5540	{ "RdDataVld11", 4, 1 },
5541	{ "RdData11", 0, 4 },
5542	{ "MA_HMA_CLIENT_INTERFACE_EXTERNAL", 0xa00c, 0 },
5543	{ "CmdVld12", 31, 1 },
5544	{ "CmdRdy12", 30, 1 },
5545	{ "CmdType12", 29, 1 },
5546	{ "CmdLen12", 21, 8 },
5547	{ "CmdAddr12", 8, 13 },
5548	{ "WrDataVld12", 7, 1 },
5549	{ "WrDataRdy12", 6, 1 },
5550	{ "RdDataRdy12", 5, 1 },
5551	{ "RdDataVld12", 4, 1 },
5552	{ "RdData12", 0, 4 },
5553	{ "MA_TARGET_0_ARBITER_INTERFACE_EXTERNAL_REG0", 0xa00d, 0 },
5554	{ "ci0_arb0_Req", 31, 1 },
5555	{ "arb0_ci0_Gnt", 30, 1 },
5556	{ "ci0_dm0_wdata_vld", 29, 1 },
5557	{ "dm0_ci0_rdata_vld", 28, 1 },
5558	{ "ci1_arb0_Req", 27, 1 },
5559	{ "arb0_ci1_Gnt", 26, 1 },
5560	{ "ci1_dm0_wdata_vld", 25, 1 },
5561	{ "dm0_ci1_rdata_vld", 24, 1 },
5562	{ "ci2_arb0_Req", 23, 1 },
5563	{ "arb0_ci2_Gnt", 22, 1 },
5564	{ "ci2_dm0_wdata_vld", 21, 1 },
5565	{ "dm0_ci2_rdata_vld", 20, 1 },
5566	{ "ci3_arb0_Req", 19, 1},
5567	{ "arb0_ci3_Gnt", 18, 1 },
5568	{ "ci3_dm0_wdata_vld", 17, 1 },
5569	{ "dm0_ci3_rdata_vld", 16, 1 },
5570	{ "ci4_arb0_Req", 15, 1 },
5571	{ "arb0_ci4_Gnt", 14, 1 },
5572	{ "ci4_dm0_wdata_vld", 13, 1 },
5573	{ "dm0_ci4_rdata_vld", 12, 1 },
5574	{ "ci5_arb0_Req", 11, 1 },
5575	{ "arb0_ci5_Gnt", 10, 1 },
5576	{ "ci5_dm0_wdata_vld", 9, 1 },
5577	{ "dm0_ci5_rdata_vld", 8, 1 },
5578	{ "ci6_arb0_Req", 7, 1 },
5579	{ "arb0_ci6_Gnt", 6, 1 },
5580	{ "ci6_dm0_wdata_vld", 5, 1 },
5581	{ "dm0_ci6_rdata_vld", 4, 1 },
5582	{ "ci7_arb0_Req", 3, 1 },
5583	{ "arb0_ci7_Gnt", 2, 1 },
5584	{ "ci7_dm0_wdata_vld", 1, 1},
5585	{ "dm0_ci7_rdata_vld", 0, 1 },
5586	{ "MA_TARGET_1_ARBITER_INTERFACE_EXTERNAL_REG0", 0xa00e, 0 },
5587	{ "ci0_arb1_Req", 31, 1 },
5588	{ "arb1_ci0_Gnt", 30, 1 },
5589	{ "ci0_dm1_wdata_vld", 29, 1 },
5590	{ "dm1_ci0_rdata_vld", 28, 1 },
5591	{ "ci1_arb1_Req", 27, 1 },
5592	{ "arb1_ci1_Gnt", 26, 1 },
5593	{ "ci1_dm1_wdata_vld", 25, 1 },
5594	{ "dm1_ci1_rdata_vld", 24, 1 },
5595	{ "ci2_arb1_Req", 23, 1 },
5596	{ "arb1_ci2_Gnt", 22, 1 },
5597	{ "ci2_dm1_wdata_vld", 21, 1 },
5598	{ "dm1_ci2_rdata_vld", 20, 1 },
5599	{ "ci3_arb1_Req", 19, 1 },
5600	{ "arb1_ci3_Gnt", 18, 1 },
5601	{ "ci3_dm1_wdata_vld", 17, 1 },
5602	{ "dm1_ci3_rdata_vld", 16, 1 },
5603	{ "ci4_arb1_Req", 15, 1 },
5604	{ "arb1_ci4_Gnt", 14, 1 },
5605	{ "ci4_dm1_wdata_vld", 13, 1 },
5606	{ "dm1_ci4_rdata_vld", 12, 1 },
5607	{ "ci5_arb1_Req", 11, 1 },
5608	{ "arb1_ci5_Gnt", 10, 1 },
5609	{ "ci5_dm1_wdata_vld", 9, 1 },
5610	{ "dm1_ci5_rdata_vld", 8, 1 },
5611	{ "ci6_arb1_Req", 7, 1 },
5612	{ "arb1_ci6_Gnt", 6, 1 },
5613	{ "ci6_dm1_wdata_vld", 5, 1 },
5614	{ "dm1_ci6_rdata_vld", 4, 1 },
5615	{ "ci7_arb1_Req", 3, 1 },
5616	{ "arb1_ci7_Gnt", 2, 1 },
5617	{ "ci7_dm1_wdata_vld", 1, 1 },
5618	{ "dm1_ci7_rdata_vld", 0, 1 },
5619	{ "MA_TARGET_2_ARBITER_INTERFACE_EXTERNAL_REG0", 0xa00f, 0 },
5620	{ "ci0_arb2_Req", 31, 1 },
5621	{ "arb2_ci0_Gnt", 30, 1 },
5622	{ "ci0_dm2_wdata_vld", 29, 1 },
5623	{ "dm2_ci0_rdata_vld", 28, 1 },
5624	{ "ci1_arb2_Req", 27, 1 },
5625	{ "arb2_ci1_Gnt", 26, 1 },
5626	{ "ci1_dm2_wdata_vld", 25, 1 },
5627	{ "dm2_ci1_rdata_vld", 24, 1 },
5628	{ "ci2_arb2_Req", 23, 1 },
5629	{ "arb2_ci2_Gnt", 22, 1 },
5630	{ "ci2_dm2_wdata_vld", 21, 1 },
5631	{ "dm2_ci2_rdata_vld", 20, 1 },
5632	{ "ci3_arb2_Req", 19, 1 },
5633	{ "arb2_ci3_Gnt", 18, 1 },
5634	{ "ci3_dm2_wdata_vld", 17, 1 },
5635	{ "dm2_ci3_rdata_vld", 16, 1 },
5636	{ "ci4_arb2_Req", 15, 1 },
5637	{ "arb2_ci4_Gnt", 14, 1 },
5638	{ "ci4_dm2_wdata_vld", 13, 1 },
5639	{ "dm2_ci4_rdata_vld", 12, 1 },
5640	{ "ci5_arb2_Req", 11, 1 },
5641	{ "arb2_ci5_Gnt", 10, 1 },
5642	{ "ci5_dm2_wdata_vld", 9, 1 },
5643	{ "dm2_ci5_rdata_vld", 8, 1 },
5644	{ "ci6_arb2_Req", 7, 1 },
5645	{ "arb2_ci6_Gnt", 6, 1 },
5646	{ "ci6_dm2_wdata_vld", 5, 1 },
5647	{ "dm2_ci6_rdata_vld", 4, 1 },
5648	{ "ci7_arb2_Req", 3, 1 },
5649	{ "arb2_ci7_Gnt", 2, 1 },
5650	{ "ci7_dm2_wdata_vld", 1, 1 },
5651	{ "dm2_ci7_rdata_vld", 0, 1 },
5652	{ "MA_TARGET_3_ARBITER_INTERFACE_EXTERNAL_REG0", 0xa010, 0 },
5653	{ "ci0_arb3_Req", 31, 1 },
5654	{ "arb3_ci0_Gnt", 30, 1 },
5655	{ "ci0_dm3_wdata_vld", 29, 1 },
5656	{ "dm3_ci0_rdata_vld", 28, 1 },
5657	{ "ci1_arb3_Req", 27, 1 },
5658	{ "arb3_ci1_Gnt", 26, 1 },
5659	{ "ci1_dm3_wdata_vld", 25, 1 },
5660	{ "dm3_ci1_rdata_vld", 24, 1 },
5661	{ "ci2_arb3_Req", 23, 1 },
5662	{ "arb3_ci2_Gnt", 22, 1 },
5663	{ "ci2_dm3_wdata_vld", 21, 1 },
5664	{ "dm3_ci2_rdata_vld", 20, 1 },
5665	{ "ci3_arb3_Req", 19, 1 },
5666	{ "arb3_ci3_Gnt", 18, 1 },
5667	{ "ci3_dm3_wdata_vld", 17, 1 },
5668	{ "dm3_ci3_rdata_vld", 16, 1 },
5669	{ "ci4_arb3_Req", 15, 1 },
5670	{ "arb3_ci4_Gnt", 14, 1 },
5671	{ "ci4_dm3_wdata_vld", 13, 1 },
5672	{ "dm3_ci4_rdata_vld", 12, 1 },
5673	{ "ci5_arb3_Req", 11, 1 },
5674	{ "arb3_ci5_Gnt", 10, 1 },
5675	{ "ci5_dm3_wdata_vld", 9, 1 },
5676	{ "dm3_ci5_rdata_vld", 8, 1 },
5677	{ "ci6_arb3_Req", 7, 1 },
5678	{ "arb3_ci6_Gnt", 6, 1 },
5679	{ "ci6_dm3_wdata_vld", 5, 1 },
5680	{ "dm3_ci6_rdata_vld", 4, 1 },
5681	{ "ci7_arb3_Req", 3, 1 },
5682	{ "arb3_ci7_Gnt", 2, 1 },
5683	{ "ci7_dm3_wdata_vld", 1, 1 },
5684	{ "dm3_ci7_rdata_vld", 0, 1 },
5685	{ "MA_MA_DEBUG_SIGNATURE_LTL_END", 0xa011, 0 },
5686	{ "MA_MA_DEBUG_SIGNATURE_BIG_END_INVERSE", 0xa012, 0 },
5687	{ "MA_TARGET_0_ARBITER_INTERFACE_EXTERNAL_REG1", 0xa013, 0 },
5688	{ "ci8_arb0_Req", 31, 1 },
5689	{ "arb0_ci8_Gnt", 30, 1 },
5690	{ "ci8_dm0_wdata_vld", 29, 1 },
5691	{ "dm0_ci8_rdata_vld", 28, 1 },
5692	{ "ci9_arb0_Req", 27, 1 },
5693	{ "arb0_ci9_Gnt", 26, 1 },
5694	{ "ci9_dm0_wdata_vld", 25, 1 },
5695	{ "dm0_ci9_rdata_vld", 24, 1 },
5696	{ "ci10_arb0_Req", 23, 1 },
5697	{ "arb0_ci10_Gnt", 22, 1 },
5698	{ "ci10_dm0_wdata_vld", 21, 1 },
5699	{ "dm0_ci10_rdata_vld", 20, 1 },
5700	{ "ci11_arb0_Req", 19, 1 },
5701	{ "arb0_ci11_Gnt", 18, 1 },
5702	{ "ci11_dm0_wdata_vld", 17, 1 },
5703	{ "dm0_ci11_rdata_vld", 16, 1 },
5704	{ "ci12_arb0_Req", 15, 1 },
5705	{ "arb0_ci12_Gnt", 14, 1 },
5706	{ "ci12_dm0_wdata_vld", 13, 1 },
5707	{ "dm0_ci12_rdata_vld", 12, 1 },
5708	{ "RSVD", 0, 12 },
5709	{ "MA_TARGET_1_ARBITER_INTERFACE_EXTERNAL_REG1", 0xa014, 0 },
5710	{ "ci8_arb1_Req", 31, 1 },
5711	{ "arb1_ci8_Gnt", 30, 1 },
5712	{ "ci8_dm1_wdata_vld", 29, 1 },
5713	{ "dm1_ci8_rdata_vld", 28, 1 },
5714	{ "ci9_arb1_Req", 27, 1 },
5715	{ "arb1_ci9_Gnt", 26, 1 },
5716	{ "ci9_dm1_wdata_vld", 25, 1 },
5717	{ "dm1_ci9_rdata_vld", 24, 1 },
5718	{ "ci10_arb1_Req", 23, 1 },
5719	{ "arb1_ci10_Gnt", 22, 1 },
5720	{ "ci10_dm1_wdata_vld", 21, 1 },
5721	{ "dm1_ci10_rdata_vld", 20, 1 },
5722	{ "ci11_arb1_Req", 19, 1 },
5723	{ "arb1_ci11_Gnt", 18, 1 },
5724	{ "ci11_dm1_wdata_vld", 17, 1 },
5725	{ "dm1_ci11_rdata_vld", 16, 1 },
5726	{ "ci12_arb1_Req", 15, 1 },
5727	{ "arb1_ci12_Gnt", 14, 1 },
5728	{ "ci12_dm1_wdata_vld", 13, 1 },
5729	{ "dm1_ci12_rdata_vld", 12, 1 },
5730	{ "RSVD", 0, 12 },
5731	{ "MA_TARGET_2_ARBITER_INTERFACE_EXTERNAL_REG1", 0xa015, 0 },
5732	{ "ci8_arb2_Req", 31, 1 },
5733	{ "arb2_ci8_Gnt", 30, 1 },
5734	{ "ci8_dm2_wdata_vld", 29, 1 },
5735	{ "dm2_ci8_rdata_vld", 28, 1 },
5736	{ "ci9_arb2_Req", 27, 1 },
5737	{ "arb2_ci9_Gnt", 26, 1 },
5738	{ "ci9_dm2_wdata_vld", 25, 1 },
5739	{ "dm2_ci9_rdata_vld", 24, 1 },
5740	{ "ci10_arb2_Req", 23, 1 },
5741	{ "arb2_ci10_Gnt", 22, 1 },
5742	{ "ci10_dm2_wdata_vld", 21, 1 },
5743	{ "dm2_ci10_rdata_vld", 20, 1 },
5744	{ "ci11_arb2_Req", 19, 1 },
5745	{ "arb2_ci11_Gnt", 18, 1 },
5746	{ "ci11_dm2_wdata_vld", 17, 1 },
5747	{ "dm2_ci11_rdata_vld", 16, 1 },
5748	{ "ci12_arb2_Req", 15, 1 },
5749	{ "arb2_ci12_Gnt", 14, 1 },
5750	{ "ci12_dm2_wdata_vld", 13, 1 },
5751	{ "dm2_ci12_rdata_vld", 12, 1 },
5752	{ "RSVD", 0, 12 },
5753	{ "MA_TARGET_3_ARBITER_INTERFACE_EXTERNAL_REG1", 0xa016, 0 },
5754	{ "ci8_arb3_Req", 31, 1 },
5755	{ "arb3_ci8_Gnt", 30, 1 },
5756	{ "ci8_dm3_wdata_vld", 29, 1 },
5757	{ "dm3_ci8_rdata_vld", 28, 1 },
5758	{ "ci9_arb3_Req", 27, 1 },
5759	{ "arb3_ci9_Gnt", 26, 1 },
5760	{ "ci9_dm3_wdata_vld", 25, 1 },
5761	{ "dm3_ci9_rdata_vld", 24, 1 },
5762	{ "ci10_arb3_Req", 23, 1 },
5763	{ "arb3_ci10_Gnt", 22, 1 },
5764	{ "ci10_dm3_wdata_vld", 21, 1 },
5765	{ "dm3_ci10_rdata_vld", 20, 1},
5766	{ "ci11_arb3_Req", 19, 1 },
5767	{ "arb3_ci11_Gnt", 18, 1 },
5768	{ "ci11_dm3_wdata_vld", 17, 1 },
5769	{ "dm3_ci11_rdata_vld", 16, 1 },
5770	{ "ci12_arb3_Req", 15, 1 },
5771	{ "arb3_ci12_Gnt", 14, 1 },
5772	{ "ci12_dm3_wdata_vld", 13, 1 },
5773	{ "dm3_ci12_rdata_vld", 12, 1 },
5774	{"RSVD", 0, 12 },
5775	{ NULL }
5776};
5777static struct cudbg_reg_info t6_ma_regs_a400_to_a41e[] = {
5778	{ "MA_SGE_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG0", 0xa400, 0 },
5779	{ "Cmd_In_FIFO_Cnt0", 30, 2 },
5780	{ "Cmd_Split_FIFO_Cnt0", 28, 2 },
5781	{ "Cmd_Throttle_FIFO_Cnt0", 22, 6 },
5782	{ "Rd_Chnl_FIFO_Cnt0", 15, 7 },
5783	{ "Rd_Data_Ext_FIFO_Cnt0", 13, 2 },
5784	{ "Rd_Data_512b_FIFO_Cnt0", 5, 8 },
5785	{ "Rd_Req_Tag_FIFO_Cnt0", 1, 4 },
5786	{ "RSVD", 0, 1 },
5787	{ "MA_SGE_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG0", 0xa401, 0 },
5788	{ "Cmd_In_FIFO_Cnt1", 30, 2 },
5789	{ "Cmd_Split_FIFO_Cnt1", 28, 2 },
5790	{ "Cmd_Throttle_FIFO_Cnt1", 22, 6 },
5791	{ "Rd_Chnl_FIFO_Cnt1", 15, 7 },
5792	{ "Rd_Data_Ext_FIFO_Cnt1", 13, 2 },
5793	{ "Rd_Data_512b_FIFO_Cnt1", 5, 8 },
5794	{ "Rd_Req_Tag_FIFO_Cnt1", 1, 4 },
5795	{ "RSVD", 0, 1 },
5796	{ "MA_ULP_TX_CLIENT_INTERFACE_INTERNAL_REG0", 0xa402, 0 },
5797	{ "Cmd_In_FIFO_Cnt2", 30, 2 },
5798	{ "Cmd_Split_FIFO_Cnt2", 28, 2 },
5799	{ "Cmd_Throttle_FIFO_Cnt2", 22, 6 },
5800	{ "Rd_Chnl_FIFO_Cnt2", 15, 7 },
5801	{ "Rd_Data_Ext_FIFO_Cnt2", 13, 2 },
5802	{ "Rd_Data_512b_FIFO_Cnt2", 5, 8 },
5803	{ "Rd_Req_Tag_FIFO_Cnt2", 1, 4 },
5804	{ "RSVD", 0, 1 },
5805	{ "MA_ULP_RX_CLIENT_INTERFACE_INTERNAL_REG0", 0xa403, 0 },
5806	{ "Cmd_In_FIFO_Cnt3", 30, 2 },
5807	{ "Cmd_Split_FIFO_Cnt3", 28, 2 },
5808	{ "Cmd_Throttle_FIFO_Cnt3", 22, 6 },
5809	{ "Rd_Chnl_FIFO_Cnt3", 15, 7 },
5810	{ "Rd_Data_Ext_FIFO_Cnt3", 13, 2 },
5811	{ "Rd_Data_512b_FIFO_Cnt3", 5, 8 },
5812	{ "Rd_Req_Tag_FIFO_Cnt3", 1, 4 },
5813	{ "RSVD", 0, 1 },
5814	{ "MA_ULP_TX_RX_CLIENT_INTERFACE_INTERNAL_REG0", 0xa404, 0 },
5815	{ "Cmd_In_FIFO_Cnt4", 30, 2 },
5816	{ "Cmd_Split_FIFO_Cnt4", 28, 2 },
5817	{ "Cmd_Throttle_FIFO_Cnt4", 22, 6 },
5818	{ "Rd_Chnl_FIFO_Cnt4", 15, 7 },
5819	{ "Rd_Data_Ext_FIFO_Cnt4", 13, 2 },
5820	{ "Rd_Data_512b_FIFO_Cnt4", 5, 8 },
5821	{ "Rd_Req_Tag_FIFO_Cnt4", 1, 4 },
5822	{ "RSVD", 0, 1 },
5823	{ "MA_TP_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG0", 0xa405, 0 },
5824	{ "Cmd_In_FIFO_Cnt5", 30, 2 },
5825	{ "Cmd_Split_FIFO_Cnt5", 28, 2 },
5826	{ "Cmd_Throttle_FIFO_Cnt5", 22, 6 },
5827	{ "Rd_Chnl_FIFO_Cnt5", 15, 7 },
5828	{ "Rd_Data_Ext_FIFO_Cnt5", 13, 2 },
5829	{ "Rd_Data_512b_FIFO_Cnt5", 5, 8 },
5830	{ "Rd_Req_Tag_FIFO_Cnt5", 1, 4 },
5831	{ "RSVD", 0, 1 },
5832	{ "MA_TP_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG0", 0xa406, 0 },
5833	{ "Cmd_In_FIFO_Cnt6", 30, 2 },
5834	{ "Cmd_Split_FIFO_Cnt6", 28, 2 },
5835	{ "Cmd_Throttle_FIFO_Cnt6", 22, 6 },
5836	{ "Rd_Chnl_FIFO_Cnt6", 15, 7 },
5837	{ "Rd_Data_Ext_FIFO_Cnt6", 13, 2 },
5838	{ "Rd_Data_512b_FIFO_Cnt6", 5, 8 },
5839	{ "Rd_Req_Tag_FIFO_Cnt6", 1, 4 },
5840	{ "RSVD", 0, 1 },
5841	{ "MA_LE_CLIENT_INTERFACE_INTERNAL_REG0", 0xa407, 0 },
5842	{ "Cmd_In_FIFO_Cnt7", 30, 2 },
5843	{ "Cmd_Split_FIFO_Cnt7", 28, 2 },
5844	{ "Cmd_Throttle_FIFO_Cnt7", 22, 6 },
5845	{ "Rd_Chnl_FIFO_Cnt7", 15, 7 },
5846	{ "Rd_Data_Ext_FIFO_Cnt7", 13, 2 },
5847	{ "Rd_Data_512b_FIFO_Cnt7", 5, 8 },
5848	{ "Rd_Req_Tag_FIFO_Cnt7", 1, 4 },
5849	{ "RSVD", 0, 1 },
5850	{ "MA_CIM_CLIENT_INTERFACE_INTERNAL_REG0", 0xa408, 0 },
5851	{ "Cmd_In_FIFO_Cnt8", 30, 2 },
5852	{ "Cmd_Split_FIFO_Cnt8", 28, 2 },
5853	{ "Cmd_Throttle_FIFO_Cnt8", 22, 6 },
5854	{ "Rd_Chnl_FIFO_Cnt8", 15, 7 },
5855	{ "Rd_Data_Ext_FIFO_Cnt8", 13, 2 },
5856	{ "Rd_Data_512b_FIFO_Cnt8", 5, 8 },
5857	{ "Rd_Req_Tag_FIFO_Cnt8", 1, 4 },
5858	{ "RSVD", 0, 1 },
5859	{ "MA_PCIE_CLIENT_INTERFACE_INTERNAL_REG0", 0xa409, 0 },
5860	{ "Cmd_In_FIFO_Cnt9", 30, 2 },
5861	{ "Cmd_Split_FIFO_Cnt9", 28, 2 },
5862	{ "Cmd_Throttle_FIFO_Cnt9", 22, 6 },
5863	{ "Rd_Chnl_FIFO_Cnt9", 15, 7 },
5864	{ "Rd_Data_Ext_FIFO_Cnt9", 13, 2 },
5865	{ "Rd_Data_512b_FIFO_Cnt9", 5, 8 },
5866	{ "Rd_Req_Tag_FIFO_Cnt9", 1, 4 },
5867	{ "RSVD", 0, 1 },
5868	{ "MA_PM_TX_CLIENT_INTERFACE_INTERNAL_REG0", 0xa40a, 0 },
5869	{ "Cmd_In_FIFO_Cnt10", 30, 2 },
5870	{ "Cmd_Split_FIFO_Cnt10", 28, 2 },
5871	{ "Cmd_Throttle_FIFO_Cnt10", 22, 6 },
5872	{ "Rd_Chnl_FIFO_Cnt10", 15, 7 },
5873	{ "Rd_Data_Ext_FIFO_Cnt10", 13, 2 },
5874	{ "Rd_Data_512b_FIFO_Cnt10", 5, 8 },
5875	{ "Rd_Req_Tag_FIFO_Cnt10", 1, 4 },
5876	{ "RSVD", 0, 1 },
5877	{ "MA_PM_RX_CLIENT_INTERFACE_INTERNAL_REG0", 0xa40b, 0 },
5878	{ "Cmd_In_FIFO_Cnt11", 30, 2 },
5879	{ "Cmd_Split_FIFO_Cnt11", 28, 2 },
5880	{ "Cmd_Throttle_FIFO_Cnt11", 22, 6 },
5881	{ "Rd_Chnl_FIFO_Cnt11", 15, 7 },
5882	{ "Rd_Data_Ext_FIFO_Cnt11", 13, 2 },
5883	{ "Rd_Data_512b_FIFO_Cnt11", 5, 8 },
5884	{ "Rd_Req_Tag_FIFO_Cnt11", 1, 4 },
5885	{ "RSVD", 0, 1 },
5886	{ "MA_HMA_CLIENT_INTERFACE_INTERNAL_REG0", 0xa40c, 0 },
5887	{ "Cmd_In_FIFO_Cnt12", 30, 2 },
5888	{ "Cmd_Split_FIFO_Cnt12", 28, 2 },
5889	{ "Cmd_Throttle_FIFO_Cnt12", 22, 6 },
5890	{ "Rd_Chnl_FIFO_Cnt12", 15, 7 },
5891	{ "Rd_Data_Ext_FIFO_Cnt12", 13, 2 },
5892	{ "Rd_Data_512b_FIFO_Cnt12", 5, 8 },
5893	{ "Rd_Req_Tag_FIFO_Cnt12", 1, 4 },
5894	{ "RSVD", 0, 1 },
5895	{ "MA_TARGET_0_ARBITER_INTERFACE_INTERNAL_REG0", 0xa40d, 0 },
5896	{ "RSVD", 24, 8 },
5897	{ "Wr_data_FSM0", 23, 1 },
5898	{ "Rd_Data_FSM0", 22, 1 },
5899	{ "Tgt_Cmd_FIFO_Cnt0", 19, 2 },
5900	{ "Clnt_Num_FIFO_Cnt0", 16, 3 },
5901	{ "Wr_Cmd_Tag_FIFO_Cnt_tgt0", 8, 8},
5902	{ "Wr_Data_512b_FIFO_Cnt_tgt0", 0, 8 },
5903	{ "MA_TARGET_1_ARBITER_INTERFACE_INTERNAL_REG0", 0xa40e, 0 },
5904	{ "RSVD", 24, 8 },
5905	{ "Wr_data_FSM1", 23, 1 },
5906	{ "Rd_Data_FSM1", 22, 1 },
5907	{ "Tgt_Cmd_FIFO_Cnt1", 19, 2 },
5908	{ "Clnt_Num_FIFO_Cnt1", 16, 3 },
5909	{ "Wr_Cmd_Tag_FIFO_Cnt_tgt1", 8, 8},
5910	{ "Wr_Data_512b_FIFO_Cnt_tgt1", 0, 8 },
5911	{"MA_TARGET_2_ARBITER_INTERFACE_INTERNAL_REG0", 0xa40f, 0 },
5912	{ "RSVD", 24, 8 },
5913	{ "Wr_data_FSM2", 23, 1 },
5914	{ "Rd_Data_FSM2", 22, 1 },
5915	{ "Tgt_Cmd_FIFO_Cnt2", 19, 2 },
5916	{ "Clnt_Num_FIFO_Cnt2", 16, 3 },
5917	{ "Wr_Cmd_Tag_FIFO_Cnt_tgt2", 8, 8},
5918	{ "Wr_Data_512b_FIFO_Cnt_tgt2", 0, 8 },
5919	{ "MA_TARGET_3_ARBITER_INTERFACE_INTERNAL_REG0", 0xa410, 0 },
5920	{ "RSVD", 24, 8 },
5921	{ "Wr_data_FSM3", 23, 1 },
5922	{ "Rd_Data_FSM3", 22, 1 },
5923	{ "Tgt_Cmd_FIFO_Cnt3", 19, 2 },
5924	{ "Clnt_Num_FIFO_Cnt3", 16, 3 },
5925	{ "Wr_Cmd_Tag_FIFO_Cnt_tgt3", 8, 8},
5926	{ "Wr_Data_512b_FIFO_Cnt_tgt3", 0, 8 },
5927	{ "MA_SGE_THREAD_0_CLNT_EXP_RD_CYC_CNT", 0xa412, 0 },
5928	{ "MA_SGE_THREAD_1_CLNT_EXP_RD_CYC_CNT", 0xa413, 0 },
5929	{ "MA_ULP_TX_CLNT_EXP_RD_CYC_CNT", 0xa414, 0 },
5930	{ "MA_ULP_RX_CLNT_EXP_RD_CYC_CNT", 0xa415, 0 },
5931	{ "MA_ULP_TX_RX_CLNT_EXP_RD_CYC_CNT", 0xa416, 0 },
5932	{ "MA_TP_THREAD_0_CLNT_EXP_RD_CYC_CNT", 0xa417, 0 },
5933	{ "MA_TP_THREAD_1_CLNT_EXP_RD_CYC_CNT", 0xa418, 0 },
5934	{ "MA_LE_CLNT_EXP_RD_CYC_CNT", 0xa419, 0 },
5935	{ "MA_CIM_CLNT_EXP_RD_CYC_CNT", 0xa41a, 0 },
5936	{ "MA_PCIE_CLNT_EXP_RD_CYC_CNT", 0xa41b, 0 },
5937	{ "MA_PM_TX_CLNT_EXP_RD_CYC_CNT", 0xa41c, 0 },
5938	{ "MA_PM_RX_CLNT_EXP_RD_CYC_CNT", 0xa41d, 0 },
5939	{ "MA_HMA_CLNT_EXP_RD_CYC_CNT", 0xa41e, 0 },
5940	{ NULL }
5941};
5942
5943static struct cudbg_reg_info t6_ma_regs_a800_to_a813[] = {
5944	{ "MA_EDRAM0_WRDATA_CNT1", 0xa800, 0 },
5945	{ "MA_EDRAM0_WRDATA_CNT0", 0xa801, 0 },
5946	{ "MA_EDRAM1_WRDATA_CNT1", 0xa802, 0 },
5947	{ "MA_EDRAM1_WRDATA_CNT0", 0xa803, 0 },
5948	{ "MA_EXT_MEMORY0_WRDATA_CNT1", 0xa804, 0 },
5949	{ "MA_EXT_MEMORY0_WRDATA_CNT0", 0xa805, 0 },
5950	{ "MA_HOST_MEMORY_WRDATA_CNT1", 0xa806, 0 },
5951	{ "MA_HOST_MEMORY_WRDATA_CNT0", 0xa807, 0 },
5952	{ "MA_EXT_MEMORY1_WRDATA_CNT1", 0xa808, 0 },
5953	{ "MA_EXT_MEMORY1_WRDATA_CNT0", 0xa809, 0 },
5954	{ "MA_EDRAM0_RDDATA_CNT1", 0xa80a, 0 },
5955	{ "MA_EDRAM0_RDDATA_CNT0", 0xa80b, 0 },
5956	{ "MA_EDRAM1_RDDATA_CNT1", 0xa80c, 0 },
5957	{ "MA_EDRAM1_RDDATA_CNT0", 0xa80d, 0 },
5958	{ "MA_EXT_MEMORY0_RDDATA_CNT1", 0xa80e, 0 },
5959	{ "MA_EXT_MEMORY0_RDDATA_CNT0", 0xa80f, 0 },
5960	{ "MA_HOST_MEMORY_RDDATA_CNT1", 0xa810, 0 },
5961	{ "MA_HOST_MEMORY_RDDATA_CNT0", 0xa811, 0 },
5962	{ "MA_EXT_MEMORY1_RDDATA_CNT1", 0xa812, 0 },
5963	{ "MA_EXT_MEMORY1_RDDATA_CNT0", 0xa813, 0 },
5964	{ NULL }
5965};
5966
5967static struct cudbg_reg_info t6_ma_regs_e400_to_e600[] = {
5968	{ "MA_SGE_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG1", 0xe400, 0 },
5969	{ "Wr_Data_Ext_FIFO_Cnt0", 30, 2 },
5970	{ "Wr_Cmd_Tag_FIFO_Cnt0", 26, 4 },
5971	{ "Wr_Data_512b_FIFO_Cnt0", 18, 8 },
5972	{ "Rd_Data_Align_FSM0", 17, 1 },
5973	{ "Rd_Data_Fetch_FSM0", 16, 1 },
5974	{ "Coherency_Tx_FSM0", 15, 1 },
5975	{ "Coherency_Rx_FSM0", 14, 1 },
5976	{ "Arb_Req_FSM0", 13, 1 },
5977	{ "Cmd_Split_FSM0", 11, 2},
5978	{ "RSVD", 0, 11 },
5979	{ "MA_SGE_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG1", 0xe420, 0 },
5980	{ "Wr_Data_Ext_FIFO_Cnt1", 30, 2 },
5981	{ "Wr_Cmd_Tag_FIFO_Cnt1", 26, 4 },
5982	{ "Wr_Data_512b_FIFO_Cnt1", 18, 8 },
5983	{ "Rd_Data_Align_FSM1", 17, 1 },
5984	{ "Rd_Data_Fetch_FSM1", 16, 1 },
5985	{ "Coherency_Tx_FSM1", 15, 1 },
5986	{ "Coherency_Rx_FSM1", 14, 1 },
5987	{ "Arb_Req_FSM1", 13, 1 },
5988	{ "Cmd_Split_FSM1", 11, 2},
5989	{ "RSVD", 0, 11 },
5990	{ "MA_ULP_TX_CLIENT_INTERFACE_INTERNAL_REG1", 0xe440, 0 },
5991	{ "Wr_Data_Ext_FIFO_Cnt2", 30, 2 },
5992	{ "Wr_Cmd_Tag_FIFO_Cnt2", 26, 4 },
5993	{ "Wr_Data_512b_FIFO_Cnt2", 18, 8 },
5994	{ "Rd_Data_Align_FSM2", 17, 1 },
5995	{ "Rd_Data_Fetch_FSM2", 16, 1 },
5996	{ "Coherency_Tx_FSM2", 15, 1 },
5997	{ "Coherency_Rx_FSM2", 14, 1 },
5998	{ "Arb_Req_FSM2", 13, 1 },
5999	{ "Cmd_Split_FSM2", 11, 2},
6000	{ "RSVD", 0, 11 },
6001	{ "MA_ULP_RX_CLIENT_INTERFACE_INTERNAL_REG1", 0xe460, 0 },
6002	{ "Wr_Data_Ext_FIFO_Cnt3", 30, 2 },
6003	{ "Wr_Cmd_Tag_FIFO_Cnt3", 26, 4 },
6004	{ "Wr_Data_512b_FIFO_Cnt3", 18, 8 },
6005	{ "Rd_Data_Align_FSM3", 17, 1 },
6006	{ "Rd_Data_Fetch_FSM3", 16, 1 },
6007	{ "Coherency_Tx_FSM3", 15, 1 },
6008	{ "Coherency_Rx_FSM3", 14, 1 },
6009	{ "Arb_Req_FSM3", 13, 1 },
6010	{ "Cmd_Split_FSM3", 11, 2},
6011	{ "RSVD", 0, 11 },
6012	{ "MA_ULP_TX_RX_CLIENT_INTERFACE_INTERNAL_REG1", 0xe480, 0 },
6013	{ "Wr_Data_Ext_FIFO_Cnt4", 30, 2 },
6014	{ "Wr_Cmd_Tag_FIFO_Cnt4", 26, 4 },
6015	{ "Wr_Data_512b_FIFO_Cnt4", 18, 8 },
6016	{ "Rd_Data_Align_FSM4", 17, 1 },
6017	{ "Rd_Data_Fetch_FSM4", 16, 1 },
6018	{ "Coherency_Tx_FSM4", 15, 1 },
6019	{ "Coherency_Rx_FSM4", 14, 1 },
6020	{ "Arb_Req_FSM4", 13, 1 },
6021	{ "Cmd_Split_FSM4", 11, 2},
6022	{ "RSVD", 0, 11 },
6023	{ "MA_TP_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG1", 0xe4a0, 0 },
6024	{ "Wr_Data_Ext_FIFO_Cnt5", 30, 2 },
6025	{ "Wr_Cmd_Tag_FIFO_Cnt5", 26, 4 },
6026	{ "Wr_Data_512b_FIFO_Cnt5", 18, 8 },
6027	{ "Rd_Data_Align_FSM5", 17, 1 },
6028	{ "Rd_Data_Fetch_FSM5", 16, 1 },
6029	{ "Coherency_Tx_FSM5", 15, 1 },
6030	{ "Coherency_Rx_FSM5", 14, 1 },
6031	{ "Arb_Req_FSM5", 13, 1 },
6032	{ "Cmd_Split_FSM5", 11, 2},
6033	{ "RSVD", 0, 11 },
6034	{ "MA_TP_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG1", 0xe4c0, 0 },
6035	{ "Wr_Data_Ext_FIFO_Cnt6", 30, 2 },
6036	{ "Wr_Cmd_Tag_FIFO_Cnt6", 26, 4 },
6037	{ "Wr_Data_512b_FIFO_Cnt6", 18, 8 },
6038	{ "Rd_Data_Align_FSM6", 17, 1 },
6039	{ "Rd_Data_Fetch_FSM6", 16, 1 },
6040	{ "Coherency_Tx_FSM6", 15, 1 },
6041	{ "Coherency_Rx_FSM6", 14, 1 },
6042	{ "Arb_Req_FSM6", 13, 1 },
6043	{ "Cmd_Split_FSM6", 11, 2},
6044	{ "RSVD", 0, 11 },
6045	{ "MA_LE_CLIENT_INTERFACE_INTERNAL_REG1", 0xe4e0, 0 },
6046	{ "Wr_Data_Ext_FIFO_Cnt7", 30, 2 },
6047	{ "Wr_Cmd_Tag_FIFO_Cnt7", 26, 4 },
6048	{ "Wr_Data_512b_FIFO_Cnt7", 18, 8 },
6049	{ "Rd_Data_Align_FSM7", 17, 1 },
6050	{ "Rd_Data_Fetch_FSM7", 16, 1 },
6051	{ "Coherency_Tx_FSM7", 15, 1 },
6052	{ "Coherency_Rx_FSM7", 14, 1 },
6053	{ "Arb_Req_FSM7", 13, 1 },
6054	{ "Cmd_Split_FSM7", 11, 2},
6055	{ "RSVD", 0, 11 },
6056	{ "MA_CIM_CLIENT_INTERFACE_INTERNAL_REG1", 0xe500, 0 },
6057	{ "Wr_Data_Ext_FIFO_Cnt8", 30, 2 },
6058	{ "Wr_Cmd_Tag_FIFO_Cnt8", 26, 4 },
6059	{ "Wr_Data_512b_FIFO_Cnt8", 18, 8 },
6060	{ "Rd_Data_Align_FSM8", 17, 1 },
6061	{ "Rd_Data_Fetch_FSM8", 16, 1 },
6062	{ "Coherency_Tx_FSM8", 15, 1 },
6063	{ "Coherency_Rx_FSM8", 14, 1 },
6064	{ "Arb_Req_FSM8", 13, 1 },
6065	{ "Cmd_Split_FSM8", 11, 2},
6066	{ "RSVD", 0, 11 },
6067	{ "MA_PCIE_CLIENT_INTERFACE_INTERNAL_REG1", 0xe520, 0 },
6068	{ "Wr_Data_Ext_FIFO_Cnt9", 30, 2 },
6069	{ "Wr_Cmd_Tag_FIFO_Cnt9", 26, 4 },
6070	{ "Wr_Data_512b_FIFO_Cnt9", 18, 8 },
6071	{ "Rd_Data_Align_FSM9", 17, 1 },
6072	{ "Rd_Data_Fetch_FSM9", 16, 1 },
6073	{ "Coherency_Tx_FSM9", 15, 1 },
6074	{ "Coherency_Rx_FSM9", 14, 1 },
6075	{ "Arb_Req_FSM9", 13, 1 },
6076	{ "Cmd_Split_FSM9", 11, 2},
6077	{ "RSVD", 0, 11 },
6078	{ "MA_PM_TX_CLIENT_INTERFACE_INTERNAL_REG1", 0xe540, 0 },
6079	{ "Wr_Data_Ext_FIFO_Cnt10", 30, 2 },
6080	{ "Wr_Cmd_Tag_FIFO_Cnt10", 26, 4 },
6081	{ "Wr_Data_512b_FIFO_Cnt10", 18, 8 },
6082	{ "Rd_Data_Align_FSM10", 17, 1 },
6083	{ "Rd_Data_Fetch_FSM10", 16, 1 },
6084	{ "Coherency_Tx_FSM10", 15, 1 },
6085	{ "Coherency_Rx_FSM10", 14, 1 },
6086	{ "Arb_Req_FSM10", 13, 1 },
6087	{ "Cmd_Split_FSM10", 11, 2},
6088	{ "RSVD", 0, 11 },
6089	{ "MA_PM_RX_CLIENT_INTERFACE_INTERNAL_REG1", 0xe560, 0 },
6090	{ "Wr_Data_Ext_FIFO_Cnt11", 30, 2 },
6091	{ "Wr_Cmd_Tag_FIFO_Cnt11", 26, 4 },
6092	{ "Wr_Data_512b_FIFO_Cnt11", 18, 8 },
6093	{ "Rd_Data_Align_FSM11", 17, 1 },
6094	{ "Rd_Data_Fetch_FSM11", 16, 1 },
6095	{ "Coherency_Tx_FSM11", 15, 1 },
6096	{ "Coherency_Rx_FSM11", 14, 1 },
6097	{ "Arb_Req_FSM11", 13, 1 },
6098	{ "Cmd_Split_FSM11", 11, 2},
6099	{ "RSVD", 0, 11 },
6100	{ "MA_HMA_CLIENT_INTERFACE_INTERNAL_REG1", 0xe580, 0 },
6101	{ "Wr_Data_Ext_FIFO_Cnt12", 30, 2 },
6102	{ "Wr_Cmd_Tag_FIFO_Cnt12", 26, 4 },
6103	{ "Wr_Data_512b_FIFO_Cnt12", 18, 8 },
6104	{ "Rd_Data_Align_FSM12", 17, 1 },
6105	{ "Rd_Data_Fetch_FSM12", 16, 1 },
6106	{ "Coherency_Tx_FSM12", 15, 1 },
6107	{ "Coherency_Rx_FSM12", 14, 1 },
6108	{ "Arb_Req_FSM12", 13, 1 },
6109	{ "Cmd_Split_FSM12", 11, 2},
6110	{ "RSVD", 0, 11 },
6111	{ "MA_TARGET_0_ARBITER_INTERFACE_INTERNAL_REG1", 0xe5a0, 0 },
6112	{ "RSVD", 16, 16 },
6113	{ "Rd_Cmd_Tag_FIFO_Cnt0", 8, 8 },
6114	{ "Rd_Data_FIFO_Cnt0", 0, 8 },
6115	{ "MA_TARGET_1_ARBITER_INTERFACE_INTERNAL_REG1", 0xe5c0, 0 },
6116	{ "RSVD", 16, 16 },
6117	{ "Rd_Cmd_Tag_FIFO_Cnt1", 8, 8 },
6118	{ "Rd_Data_FIFO_Cnt1", 0, 8 },
6119	{ "MA_TARGET_2_ARBITER_INTERFACE_INTERNAL_REG1", 0xe5e0, 0 },
6120	{ "RSVD", 16, 16 },
6121	{ "Rd_Cmd_Tag_FIFO_Cnt2", 8, 8 },
6122	{ "Rd_Data_FIFO_Cnt2", 0, 8 },
6123	{ "MA_TARGET_3_ARBITER_INTERFACE_INTERNAL_REG1", 0xe600, 0 },
6124	{ "RSVD", 16, 16 },
6125	{ "Rd_Cmd_Tag_FIFO_Cnt3", 8, 8 },
6126	{ "Rd_Data_FIFO_Cnt3", 0, 8 },
6127	{ NULL }
6128};
6129
6130static struct cudbg_reg_info t6_ma_regs_e640_to_e7c0[] = {
6131	{ "MA_SGE_THREAD_0_CLNT_EXP_WR_CYC_CNT", 0xe640, 0 },
6132	{ "MA_SGE_THREAD_1_CLNT_EXP_WR_CYC_CNT", 0xe660, 0 },
6133	{ "MA_ULP_TX_CLNT_EXP_WR_CYC_CNT", 0xe680, 0 },
6134	{ "MA_ULP_RX_CLNT_EXP_WR_CYC_CNT", 0xe6a0, 0 },
6135	{ "MA_ULP_TX_RX_CLNT_EXP_WR_CYC_CNT", 0xe6c0, 0 },
6136	{ "MA_TP_THREAD_0_CLNT_EXP_WR_CYC_CNT", 0xe6e0, 0 },
6137	{ "MA_TP_THREAD_1_CLNT_EXP_WR_CYC_CNT", 0xe700, 0 },
6138	{ "MA_LE_CLNT_EXP_WR_CYC_CNT", 0xe720, 0 },
6139	{ "MA_CIM_CLNT_EXP_WR_CYC_CNT", 0xe740, 0 },
6140	{ "MA_PCIE_CLNT_EXP_WR_CYC_CNT", 0xe760, 0 },
6141	{ "MA_PM_TX_CLNT_EXP_WR_CYC_CNT", 0xe780, 0 },
6142	{ "MA_PM_RX_CLNT_EXP_WR_CYC_CNT", 0xe7a0, 0 },
6143	{ "MA_HMA_CLNT_EXP_WR_CYC_CNT", 0xe7c0, 0 },
6144	{ NULL }
6145};
6146
6147static char *cudbg_ulptx_rdptr[] = {
6148	"ULP_TX_LA_RDPTR_0" ,
6149	"ULP_TX_LA_RDPTR_1" ,
6150	"ULP_TX_LA_RDPTR_2" ,
6151	"ULP_TX_LA_RDPTR_3" ,
6152	"ULP_TX_LA_RDPTR_4" ,
6153	"ULP_TX_LA_RDPTR_5" ,
6154	"ULP_TX_LA_RDPTR_6" ,
6155	"ULP_TX_LA_RDPTR_7" ,
6156	"ULP_TX_LA_RDPTR_8" ,
6157	"ULP_TX_LA_RDPTR_9" ,
6158	"ULP_TX_LA_RDPTR_10"
6159};
6160
6161static char *cudbg_ulptx_wrptr[] = {
6162	"ULP_TX_LA_WRPTR_0",
6163	"ULP_TX_LA_WRPTR_1",
6164	"ULP_TX_LA_WRPTR_2",
6165	"ULP_TX_LA_WRPTR_3",
6166	"ULP_TX_LA_WRPTR_4",
6167	"ULP_TX_LA_WRPTR_5",
6168	"ULP_TX_LA_WRPTR_6",
6169	"ULP_TX_LA_WRPTR_7",
6170	"ULP_TX_LA_WRPTR_8",
6171	"ULP_TX_LA_WRPTR_9",
6172	"ULP_TX_LA_WRPTR_10"
6173};
6174
6175static char *cudbg_ulptx_rddata[] = {
6176	"ULP_TX_LA_RDDATA_0",
6177	"ULP_TX_LA_RDDATA_1",
6178	"ULP_TX_LA_RDDATA_2",
6179	"ULP_TX_LA_RDDATA_3",
6180	"ULP_TX_LA_RDDATA_4",
6181	"ULP_TX_LA_RDDATA_5",
6182	"ULP_TX_LA_RDDATA_6",
6183	"ULP_TX_LA_RDDATA_7",
6184	"ULP_TX_LA_RDDATA_8",
6185	"ULP_TX_LA_RDDATA_9",
6186	"ULP_TX_LA_RDDATA_10"
6187};
6188
6189static struct cudbg_reg_info t6_up_cim_2000_to_207c[] = {
6190	{"CIM_CTL_CONFIG", 0x2000, 0},
6191	{"AutoPrefLoc", 17, 5},
6192	{"AutoPrefEn", 16, 1},
6193	{"DisMATimeOut", 15, 1},
6194	{"DisSlowTimeOut", 14, 1},
6195	{"IntlRspEn", 9, 1},
6196	{"PIFMultiCmd", 8, 1},
6197	{"UPSelfResetTOut", 7, 1},
6198	{"PLSwapDisWr", 6, 1},
6199	{"PLSwapDisRd", 5, 1},
6200	{"Timer1En", 4, 1},
6201	{"Timer0En", 3, 1},
6202	{"TimerEn", 1, 1},
6203	{"PrefEn", 0, 1},
6204	{"CIM_CTL_PREFADDR", 0x2004, 0},
6205	{"PrefAddr", 0, 32},
6206	{"CIM_CTL_ALLOCADDR", 0x2008, 0},
6207	{"IbqGen0", 0, 32},
6208	{"CIM_CTL_INVLDTADDR", 0x200c, 0},
6209	{"InvldtAddr", 0, 32},
6210	{"CIM_CTL_STATIC_PREFADDR0", 0x2010, 0},
6211	{"StaticPrefAddr", 0, 32},
6212	{"CIM_CTL_STATIC_PREFADDR1", 0x2014, 0},
6213	{"StaticPrefAddr", 0, 32},
6214	{"CIM_CTL_STATIC_PREFADDR2", 0x2018, 0},
6215	{"StaticPrefAddr", 0, 32},
6216	{"CIM_CTL_STATIC_PREFADDR3", 0x201c, 0},
6217	{"StaticPrefAddr", 0, 32},
6218	{"CIM_CTL_STATIC_PREFADDR4", 0x2020, 0},
6219	{"StaticPrefAddr", 0, 32},
6220	{"CIM_CTL_STATIC_PREFADDR5", 0x2024, 0},
6221	{"StaticPrefAddr", 0, 32},
6222	{"CIM_CTL_STATIC_PREFADDR6", 0x2028, 0},
6223	{"StaticPrefAddr", 0, 32},
6224	{"CIM_CTL_STATIC_PREFADDR7", 0x202c, 0},
6225	{"StaticPrefAddr", 0, 32},
6226	{"CIM_CTL_STATIC_PREFADDR8", 0x2030, 0},
6227	{"StaticPrefAddr", 0, 32},
6228	{"CIM_CTL_STATIC_PREFADDR9", 0x2034, 0},
6229	{"StaticPrefAddr", 0, 32},
6230	{"CIM_CTL_STATIC_PREFADDR10", 0x2038, 0},
6231	{"StaticPrefAddr", 0, 32},
6232	{"CIM_CTL_STATIC_PREFADDR11", 0x203c, 0},
6233	{"StaticPrefAddr", 0, 32},
6234	{"CIM_CTL_STATIC_PREFADDR12", 0x2040, 0},
6235	{"StaticPrefAddr", 0, 32},
6236	{"CIM_CTL_STATIC_PREFADDR13", 0x2044, 0},
6237	{"StaticPrefAddr", 0, 32},
6238	{"CIM_CTL_STATIC_PREFADDR14", 0x2048, 0},
6239	{"StaticPrefAddr", 0, 32},
6240	{"CIM_CTL_STATIC_PREFADDR15", 0x204c, 0},
6241	{"StaticPrefAddr", 0, 32},
6242	{"CIM_CTL_STATIC_ALLOCADDR0", 0x2050, 0},
6243	{"StaticAllocAddr", 0, 32},
6244	{"CIM_CTL_STATIC_ALLOCADDR1", 0x2054, 0},
6245	{"StaticAllocAddr", 0, 32},
6246	{"CIM_CTL_STATIC_ALLOCADDR2", 0x2058, 0},
6247	{"StaticAllocAddr", 0, 32},
6248	{"CIM_CTL_STATIC_ALLOCADDR3", 0x205c, 0},
6249	{"StaticAllocAddr", 0, 32},
6250	{"CIM_CTL_STATIC_ALLOCADDR4", 0x2060, 0},
6251	{"StaticAllocAddr", 0, 32},
6252	{"CIM_CTL_STATIC_ALLOCADDR5", 0x2064, 0},
6253	{"StaticAllocAddr", 0, 32},
6254	{"CIM_CTL_STATIC_ALLOCADDR6", 0x2068, 0},
6255	{"StaticAllocAddr", 0, 32},
6256	{"CIM_CTL_STATIC_ALLOCADDR7", 0x206c, 0},
6257	{"StaticAllocAddr", 0, 32},
6258	{"CIM_CTL_STATIC_ALLOCADDR8", 0x2070, 0},
6259	{"StaticAllocAddr", 0, 32},
6260	{"CIM_CTL_STATIC_ALLOCADDR9", 0x2074, 0},
6261	{"StaticAllocAddr", 0, 32},
6262	{"CIM_CTL_STATIC_ALLOCADDR10", 0x2078, 0},
6263	{"StaticAllocAddr", 0, 32},
6264	{"CIM_CTL_STATIC_ALLOCADDR11", 0x207c, 0},
6265	{"StaticAllocAddr", 0, 32},
6266	{ NULL }
6267};
6268
6269static struct cudbg_reg_info t5_up_cim_2000_to_207c[] = {
6270	{"CIM_CTL_CONFIG", 0x2000, 0},
6271	{"AutoPrefLoc", 17, 5},
6272	{"AutoPrefEn", 16, 1},
6273	{"DisMATimeOut", 15, 1},
6274	{"PIFMultiCmd", 8, 1},
6275	{"UPSelfResetTOut", 7, 1},
6276	{"PLSwapDisWr", 6, 1},
6277	{"PLSwapDisRd", 5, 1},
6278	{"Timer1En", 4, 1},
6279	{"Timer0En", 3, 1},
6280	{"TimerEn", 1, 1},
6281	{"PrefEn", 0, 1},
6282	{"CIM_CTL_PREFADDR", 0x2004, 0},
6283	{"PrefAddr", 0, 32},
6284	{"CIM_CTL_ALLOCADDR", 0x2008, 0},
6285	{"IbqGen0", 0, 32},
6286	{"CIM_CTL_INVLDTADDR", 0x200c, 0},
6287	{"InvldtAddr", 0, 32},
6288	{"CIM_CTL_STATIC_PREFADDR0", 0x2010, 0},
6289	{"StaticPrefAddr", 0, 32},
6290	{"CIM_CTL_STATIC_PREFADDR1", 0x2014, 0},
6291	{"StaticPrefAddr", 0, 32},
6292	{"CIM_CTL_STATIC_PREFADDR2", 0x2018, 0},
6293	{"StaticPrefAddr", 0, 32},
6294	{"CIM_CTL_STATIC_PREFADDR3", 0x201c, 0},
6295	{"StaticPrefAddr", 0, 32},
6296	{"CIM_CTL_STATIC_PREFADDR4", 0x2020, 0},
6297	{"StaticPrefAddr", 0, 32},
6298	{"CIM_CTL_STATIC_PREFADDR5", 0x2024, 0},
6299	{"StaticPrefAddr", 0, 32},
6300	{"CIM_CTL_STATIC_PREFADDR6", 0x2028, 0},
6301	{"StaticPrefAddr", 0, 32},
6302	{"CIM_CTL_STATIC_PREFADDR7", 0x202c, 0},
6303	{"StaticPrefAddr", 0, 32},
6304	{"CIM_CTL_STATIC_PREFADDR8", 0x2030, 0},
6305	{"StaticPrefAddr", 0, 32},
6306	{"CIM_CTL_STATIC_PREFADDR9", 0x2034, 0},
6307	{"StaticPrefAddr", 0, 32},
6308	{"CIM_CTL_STATIC_PREFADDR10", 0x2038, 0},
6309	{"StaticPrefAddr", 0, 32},
6310	{"CIM_CTL_STATIC_PREFADDR11", 0x203c, 0},
6311	{"StaticPrefAddr", 0, 32},
6312	{"CIM_CTL_STATIC_PREFADDR12", 0x2040, 0},
6313	{"StaticPrefAddr", 0, 32},
6314	{"CIM_CTL_STATIC_PREFADDR13", 0x2044, 0},
6315	{"StaticPrefAddr", 0, 32},
6316	{"CIM_CTL_STATIC_PREFADDR14", 0x2048, 0},
6317	{"StaticPrefAddr", 0, 32},
6318	{"CIM_CTL_STATIC_PREFADDR15", 0x204c, 0},
6319	{"StaticPrefAddr", 0, 32},
6320	{"CIM_CTL_STATIC_ALLOCADDR0", 0x2050, 0},
6321	{"StaticAllocAddr", 0, 32},
6322	{"CIM_CTL_STATIC_ALLOCADDR1", 0x2054, 0},
6323	{"StaticAllocAddr", 0, 32},
6324	{"CIM_CTL_STATIC_ALLOCADDR2", 0x2058, 0},
6325	{"StaticAllocAddr", 0, 32},
6326	{"CIM_CTL_STATIC_ALLOCADDR3", 0x205c, 0},
6327	{"StaticAllocAddr", 0, 32},
6328	{"CIM_CTL_STATIC_ALLOCADDR4", 0x2060, 0},
6329	{"StaticAllocAddr", 0, 32},
6330	{"CIM_CTL_STATIC_ALLOCADDR5", 0x2064, 0},
6331	{"StaticAllocAddr", 0, 32},
6332	{"CIM_CTL_STATIC_ALLOCADDR6", 0x2068, 0},
6333	{"StaticAllocAddr", 0, 32},
6334	{"CIM_CTL_STATIC_ALLOCADDR7", 0x206c, 0},
6335	{"StaticAllocAddr", 0, 32},
6336	{"CIM_CTL_STATIC_ALLOCADDR8", 0x2070, 0},
6337	{"StaticAllocAddr", 0, 32},
6338	{"CIM_CTL_STATIC_ALLOCADDR9", 0x2074, 0},
6339	{"StaticAllocAddr", 0, 32},
6340	{"CIM_CTL_STATIC_ALLOCADDR10", 0x2078, 0},
6341	{"StaticAllocAddr", 0, 32},
6342	{"CIM_CTL_STATIC_ALLOCADDR11", 0x207c, 0},
6343	{"StaticAllocAddr", 0, 32},
6344	{ NULL }
6345};
6346
6347static struct cudbg_reg_info t6_up_cim_4900_to_4c60[] = {
6348	{"CIM_CTL_0_TSCH_CHANNEL_TSCH_CHNLN_CTL", 0x4900, 0},
6349	{"TSCHNLEN", 31, 1},
6350	{"TSCHNRESET", 30, 1},
6351	{"MIN_MAX_EN", 29, 1},
6352	{"CIM_CTL_1_TSCH_CHANNEL_TSCH_CHNLN_CTL", 0x4a20, 0},
6353	{"TSCHNLEN", 31, 1},
6354	{"TSCHNRESET", 30, 1},
6355	{"MIN_MAX_EN", 29, 1},
6356	{"CIM_CTL_2_TSCH_CHANNEL_TSCH_CHNLN_CTL", 0x4b40, 0},
6357	{"TSCHNLEN", 31, 1},
6358	{"TSCHNRESET", 30, 1},
6359	{"MIN_MAX_EN", 29, 1},
6360	{"CIM_CTL_3_TSCH_CHANNEL_TSCH_CHNLN_CTL", 0x4c60, 0},
6361	{"TSCHNLEN", 31, 1},
6362	{"TSCHNRESET", 30, 1},
6363	{"MIN_MAX_EN", 29, 1},
6364	{ NULL }
6365};
6366
6367static struct cudbg_reg_info t6_up_cim_4904_to_4c64[] = {
6368	{"CIM_CTL_0_TSCH_CHANNEL_TSCH_CHNLN_CLASS_RATECTL", 0x4904, 0},
6369	{"TSC0RATECTL", 0, 1},
6370	{"TSC1RATECTL", 1, 1},
6371	{"TSC2RATECTL", 2, 1},
6372	{"TSC3RATECTL", 3, 1},
6373	{"TSC4RATECTL", 4, 1},
6374	{"TSC5RATECTL", 5, 1},
6375	{"TSC6RATECTL", 6, 1},
6376	{"TSC7RATECTL", 7, 1},
6377	{"TSC8RATECTL", 8, 1},
6378	{"TSC9RATECTL", 9, 1},
6379	{"TSC10RATECTL", 10, 1},
6380	{"TSC11RATECTL", 11, 1},
6381	{"TSC12RATECTL", 12, 1},
6382	{"TSC13RATECTL", 13, 1},
6383	{"TSC14RATECTL", 14, 1},
6384	{"TSC15RATECTL", 15, 1},
6385	{"CIM_CTL_1_TSCH_CHANNEL_TSCH_CHNLN_CLASS_RATECTL", 0x4a24, 0},
6386	{"TSC0RATECTL", 0, 1},
6387	{"TSC1RATECTL", 1, 1},
6388	{"TSC2RATECTL", 2, 1},
6389	{"TSC3RATECTL", 3, 1},
6390	{"TSC4RATECTL", 4, 1},
6391	{"TSC5RATECTL", 5, 1},
6392	{"TSC6RATECTL", 6, 1},
6393	{"TSC7RATECTL", 7, 1},
6394	{"TSC8RATECTL", 8, 1},
6395	{"TSC9RATECTL", 9, 1},
6396	{"TSC10RATECTL", 10, 1},
6397	{"TSC11RATECTL", 11, 1},
6398	{"TSC12RATECTL", 12, 1},
6399	{"TSC13RATECTL", 13, 1},
6400	{"TSC14RATECTL", 14, 1},
6401	{"TSC15RATECTL", 15, 1},
6402	{"CIM_CTL_2_TSCH_CHANNEL_TSCH_CHNLN_CLASS_RATECTL", 0x4b44, 0},
6403	{"TSC0RATECTL", 0, 1},
6404	{"TSC1RATECTL", 1, 1},
6405	{"TSC2RATECTL", 2, 1},
6406	{"TSC3RATECTL", 3, 1},
6407	{"TSC4RATECTL", 4, 1},
6408	{"TSC5RATECTL", 5, 1},
6409	{"TSC6RATECTL", 6, 1},
6410	{"TSC7RATECTL", 7, 1},
6411	{"TSC8RATECTL", 8, 1},
6412	{"TSC9RATECTL", 9, 1},
6413	{"TSC10RATECTL", 10, 1},
6414	{"TSC11RATECTL", 11, 1},
6415	{"TSC12RATECTL", 12, 1},
6416	{"TSC13RATECTL", 13, 1},
6417	{"TSC14RATECTL", 14, 1},
6418	{"TSC15RATECTL", 15, 1},
6419	{"CIM_CTL_3_TSCH_CHANNEL_TSCH_CHNLN_CLASS_RATECTL", 0x4c64, 0},
6420	{"TSC0RATECTL", 0, 1},
6421	{"TSC1RATECTL", 1, 1},
6422	{"TSC2RATECTL", 2, 1},
6423	{"TSC3RATECTL", 3, 1},
6424	{"TSC4RATECTL", 4, 1},
6425	{"TSC5RATECTL", 5, 1},
6426	{"TSC6RATECTL", 6, 1},
6427	{"TSC7RATECTL", 7, 1},
6428	{"TSC8RATECTL", 8, 1},
6429	{"TSC9RATECTL", 9, 1},
6430	{"TSC10RATECTL", 10, 1},
6431	{"TSC11RATECTL", 11, 1},
6432	{"TSC12RATECTL", 12, 1},
6433	{"TSC13RATECTL", 13, 1},
6434	{"TSC14RATECTL", 14, 1},
6435	{"TSC15RATECTL", 15, 1},
6436	{ NULL }
6437};
6438
6439static struct cudbg_reg_info t6_up_cim_4908_to_4c68[] = {
6440	{"CIM_CTL_0_TSCH_CHANNEL_TSCH_CHNLN_CLASS_ENABLE_A", 0x4908, 0},
6441	{"TSC15WRREN", 31, 1},
6442	{"TSC15RATEEN", 30, 1},
6443	{"TSC14WRREN", 29, 1},
6444	{"TSC14RATEEN", 28, 1},
6445	{"TSC13WRREN", 27, 1},
6446	{"TSC13RATEEN", 26, 1},
6447	{"TSC12WRREN", 25, 1},
6448	{"TSC12RATEEN", 24, 1},
6449	{"TSC11WRREN", 23, 1},
6450	{"TSC11RATEEN", 22, 1},
6451	{"TSC10WRREN", 21, 1},
6452	{"TSC10RATEEN", 20, 1},
6453	{"TSC9WRREN", 19, 1},
6454	{"TSC9RATEEN", 18, 1},
6455	{"TSC8WRREN", 17, 1},
6456	{"TSC8RATEEN", 16, 1},
6457	{"TSC7WRREN", 15, 1},
6458	{"TSC7RATEEN", 14, 1},
6459	{"TSC6WRREN", 13, 1},
6460	{"TSC6RATEEN", 12, 1},
6461	{"TSC5WRREN", 11, 1},
6462	{"TSC5RATEEN", 10, 1},
6463	{"TSC4WRREN", 9, 1},
6464	{"TSC4RATEEN", 8, 1},
6465	{"TSC3WRREN", 7, 1},
6466	{"TSC3RATEEN", 6, 1},
6467	{"TSC2WRREN", 5, 1},
6468	{"TSC2RATEEN", 4, 1},
6469	{"TSC1WRREN", 3, 1},
6470	{"TSC1RATEEN", 2, 1},
6471	{"TSC0WRREN", 1, 1},
6472	{"TSC0RATEEN", 0, 1},
6473	{"CIM_CTL_1_TSCH_CHANNEL_TSCH_CHNLN_CLASS_ENABLE_A", 0x4a28, 0},
6474	{"TSC15WRREN", 31, 1},
6475	{"TSC15RATEEN", 30, 1},
6476	{"TSC14WRREN", 29, 1},
6477	{"TSC14RATEEN", 28, 1},
6478	{"TSC13WRREN", 27, 1},
6479	{"TSC13RATEEN", 26, 1},
6480	{"TSC12WRREN", 25, 1},
6481	{"TSC12RATEEN", 24, 1},
6482	{"TSC11WRREN", 23, 1},
6483	{"TSC11RATEEN", 22, 1},
6484	{"TSC10WRREN", 21, 1},
6485	{"TSC10RATEEN", 20, 1},
6486	{"TSC9WRREN", 19, 1},
6487	{"TSC9RATEEN", 18, 1},
6488	{"TSC8WRREN", 17, 1},
6489	{"TSC8RATEEN", 16, 1},
6490	{"TSC7WRREN", 15, 1},
6491	{"TSC7RATEEN", 14, 1},
6492	{"TSC6WRREN", 13, 1},
6493	{"TSC6RATEEN", 12, 1},
6494	{"TSC5WRREN", 11, 1},
6495	{"TSC5RATEEN", 10, 1},
6496	{"TSC4WRREN", 9, 1},
6497	{"TSC4RATEEN", 8, 1},
6498	{"TSC3WRREN", 7, 1},
6499	{"TSC3RATEEN", 6, 1},
6500	{"TSC2WRREN", 5, 1},
6501	{"TSC2RATEEN", 4, 1},
6502	{"TSC1WRREN", 3, 1},
6503	{"TSC1RATEEN", 2, 1},
6504	{"TSC0WRREN", 1, 1},
6505	{"TSC0RATEEN", 0, 1},
6506	{"CIM_CTL_2_TSCH_CHANNEL_TSCH_CHNLN_CLASS_ENABLE_A", 0x4b48, 0},
6507	{"TSC15WRREN", 31, 1},
6508	{"TSC15RATEEN", 30, 1},
6509	{"TSC14WRREN", 29, 1},
6510	{"TSC14RATEEN", 28, 1},
6511	{"TSC13WRREN", 27, 1},
6512	{"TSC13RATEEN", 26, 1},
6513	{"TSC12WRREN", 25, 1},
6514	{"TSC12RATEEN", 24, 1},
6515	{"TSC11WRREN", 23, 1},
6516	{"TSC11RATEEN", 22, 1},
6517	{"TSC10WRREN", 21, 1},
6518	{"TSC10RATEEN", 20, 1},
6519	{"TSC9WRREN", 19, 1},
6520	{"TSC9RATEEN", 18, 1},
6521	{"TSC8WRREN", 17, 1},
6522	{"TSC8RATEEN", 16, 1},
6523	{"TSC7WRREN", 15, 1},
6524	{"TSC7RATEEN", 14, 1},
6525	{"TSC6WRREN", 13, 1},
6526	{"TSC6RATEEN", 12, 1},
6527	{"TSC5WRREN", 11, 1},
6528	{"TSC5RATEEN", 10, 1},
6529	{"TSC4WRREN", 9, 1},
6530	{"TSC4RATEEN", 8, 1},
6531	{"TSC3WRREN", 7, 1},
6532	{"TSC3RATEEN", 6, 1},
6533	{"TSC2WRREN", 5, 1},
6534	{"TSC2RATEEN", 4, 1},
6535	{"TSC1WRREN", 3, 1},
6536	{"TSC1RATEEN", 2, 1},
6537	{"TSC0WRREN", 1, 1},
6538	{"TSC0RATEEN", 0, 1},
6539	{"CIM_CTL_3_TSCH_CHANNEL_TSCH_CHNLN_CLASS_ENABLE_A", 0x4c68, 0},
6540	{"TSC15WRREN", 31, 1},
6541	{"TSC15RATEEN", 30, 1},
6542	{"TSC14WRREN", 29, 1},
6543	{"TSC14RATEEN", 28, 1},
6544	{"TSC13WRREN", 27, 1},
6545	{"TSC13RATEEN", 26, 1},
6546	{"TSC12WRREN", 25, 1},
6547	{"TSC12RATEEN", 24, 1},
6548	{"TSC11WRREN", 23, 1},
6549	{"TSC11RATEEN", 22, 1},
6550	{"TSC10WRREN", 21, 1},
6551	{"TSC10RATEEN", 20, 1},
6552	{"TSC9WRREN", 19, 1},
6553	{"TSC9RATEEN", 18, 1},
6554	{"TSC8WRREN", 17, 1},
6555	{"TSC8RATEEN", 16, 1},
6556	{"TSC7WRREN", 15, 1},
6557	{"TSC7RATEEN", 14, 1},
6558	{"TSC6WRREN", 13, 1},
6559	{"TSC6RATEEN", 12, 1},
6560	{"TSC5WRREN", 11, 1},
6561	{"TSC5RATEEN", 10, 1},
6562	{"TSC4WRREN", 9, 1},
6563	{"TSC4RATEEN", 8, 1},
6564	{"TSC3WRREN", 7, 1},
6565	{"TSC3RATEEN", 6, 1},
6566	{"TSC2WRREN", 5, 1},
6567	{"TSC2RATEEN", 4, 1},
6568	{"TSC1WRREN", 3, 1},
6569	{"TSC1RATEEN", 2, 1},
6570	{"TSC0WRREN", 1, 1},
6571	{"TSC0RATEEN", 0, 1},
6572	{ NULL }
6573};
6574
6575static struct cudbg_reg_info t6_up_cim_4910_to_4c70[] = {
6576	{"CIM_CTL_0_TSCH_CHANNEL_TSCH_CHNLN_RATE_LIMITER", 0x4910, 0},
6577	{"TSCHNLRATENEG", 31, 1},
6578	{"TSCHNLRATEPROT", 30, 1},
6579	{"TSCHNLRATEL", 0, 30},
6580	{"CIM_CTL_1_TSCH_CHANNEL_TSCH_CHNLN_RATE_LIMITER", 0x4a30, 0},
6581	{"TSCHNLRATENEG", 31, 1},
6582	{"TSCHNLRATEPROT", 30, 1},
6583	{"TSCHNLRATEL", 0, 30},
6584	{"CIM_CTL_2_TSCH_CHANNEL_TSCH_CHNLN_RATE_LIMITER", 0x4b50, 0},
6585	{"TSCHNLRATENEG", 31, 1},
6586	{"TSCHNLRATEPROT", 30, 1},
6587	{"TSCHNLRATEL", 0, 30},
6588	{"CIM_CTL_3_TSCH_CHANNEL_TSCH_CHNLN_RATE_LIMITER", 0x4c70, 0},
6589	{"TSCHNLRATENEG", 31, 1},
6590	{"TSCHNLRATEPROT", 30, 1},
6591	{"TSCHNLRATEL", 0, 30},
6592	{ NULL }
6593};
6594
6595static struct cudbg_reg_info t6_up_cim_4914_to_4c74[] = {
6596	{"CIM_CTL_0_TSCH_CHANNEL_TSCH_CHNLN_RATE_PROPERTIES", 0x4914, 0},
6597	{"TSCHNLRMAX", 16, 16},
6598	{"TSCHNLRTSEL", 14, 2},
6599	{"TSCHNLRINCR", 0, 14},
6600	{"CIM_CTL_1_TSCH_CHANNEL_TSCH_CHNLN_RATE_PROPERTIES", 0x4a34, 0},
6601	{"TSCHNLRMAX", 16, 16},
6602	{"TSCHNLRTSEL", 14, 2},
6603	{"TSCHNLRINCR", 0, 14},
6604	{"CIM_CTL_2_TSCH_CHANNEL_TSCH_CHNLN_RATE_PROPERTIES", 0x4b54, 0},
6605	{"TSCHNLRMAX", 16, 16},
6606	{"TSCHNLRTSEL", 14, 2},
6607	{"TSCHNLRINCR", 0, 14},
6608	{"CIM_CTL_3_TSCH_CHANNEL_TSCH_CHNLN_RATE_PROPERTIES", 0x4c74, 0},
6609	{"TSCHNLRMAX", 16, 16},
6610	{"TSCHNLRTSEL", 14, 2},
6611	{"TSCHNLRINCR", 0, 14},
6612	{ NULL }
6613};
6614
6615static struct cudbg_reg_info t6_up_cim_4920_to_4a10[] = {
6616	{"CIM_CTL_0_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4920, 0},
6617	{"TSCCLRATENEG", 31, 1},
6618	{"TSCCLRATEPROT", 30, 1},
6619	{"TSCCLRATEL", 0, 24},
6620	{"CIM_CTL_1_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4930, 0},
6621	{"TSCCLRATENEG", 31, 1},
6622	{"TSCCLRATEPROT", 30, 1},
6623	{"TSCCLRATEL", 0, 24},
6624	{"CIM_CTL_2_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4940, 0},
6625	{"TSCCLRATENEG", 31, 1},
6626	{"TSCCLRATEPROT", 30, 1},
6627	{"TSCCLRATEL", 0, 24},
6628	{"CIM_CTL_3_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4950, 0},
6629	{"TSCCLRATENEG", 31, 1},
6630	{"TSCCLRATEPROT", 30, 1},
6631	{"TSCCLRATEL", 0, 24},
6632	{"CIM_CTL_4_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4960, 0},
6633	{"TSCCLRATENEG", 31, 1},
6634	{"TSCCLRATEPROT", 30, 1},
6635	{"TSCCLRATEL", 0, 24},
6636	{"CIM_CTL_5_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4970, 0},
6637	{"TSCCLRATENEG", 31, 1},
6638	{"TSCCLRATEPROT", 30, 1},
6639	{"TSCCLRATEL", 0, 24},
6640	{"CIM_CTL_6_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4980, 0},
6641	{"TSCCLRATENEG", 31, 1},
6642	{"TSCCLRATEPROT", 30, 1},
6643	{"TSCCLRATEL", 0, 24},
6644	{"CIM_CTL_7_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4990, 0},
6645	{"TSCCLRATENEG", 31, 1},
6646	{"TSCCLRATEPROT", 30, 1},
6647	{"TSCCLRATEL", 0, 24},
6648	{"CIM_CTL_8_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x49a0, 0},
6649	{"TSCCLRATENEG", 31, 1},
6650	{"TSCCLRATEPROT", 30, 1},
6651	{"TSCCLRATEL", 0, 24},
6652	{"CIM_CTL_9_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x49b0, 0},
6653	{"TSCCLRATENEG", 31, 1},
6654	{"TSCCLRATEPROT", 30, 1},
6655	{"TSCCLRATEL", 0, 24},
6656	{"CIM_CTL_10_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x49c0, 0},
6657	{"TSCCLRATENEG", 31, 1},
6658	{"TSCCLRATEPROT", 30, 1},
6659	{"TSCCLRATEL", 0, 24},
6660	{"CIM_CTL_11_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x49d0, 0},
6661	{"TSCCLRATENEG", 31, 1},
6662	{"TSCCLRATEPROT", 30, 1},
6663	{"TSCCLRATEL", 0, 24},
6664	{"CIM_CTL_12_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x49e0, 0},
6665	{"TSCCLRATENEG", 31, 1},
6666	{"TSCCLRATEPROT", 30, 1},
6667	{"TSCCLRATEL", 0, 24},
6668	{"CIM_CTL_13_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x49f0, 0},
6669	{"TSCCLRATENEG", 31, 1},
6670	{"TSCCLRATEPROT", 30, 1},
6671	{"TSCCLRATEL", 0, 24},
6672	{"CIM_CTL_14_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4a00, 0},
6673	{"TSCCLRATENEG", 31, 1},
6674	{"TSCCLRATEPROT", 30, 1},
6675	{"TSCCLRATEL", 0, 24},
6676	{"CIM_CTL_15_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4a10, 0},
6677	{"TSCCLRATENEG", 31, 1},
6678	{"TSCCLRATEPROT", 30, 1},
6679	{"TSCCLRATEL", 0, 24},
6680	{ NULL }
6681};
6682
6683static struct cudbg_reg_info t6_up_cim_4924_to_4a14[] = {
6684	{"CIM_CTL_0_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4924, 0},
6685	{"TSCCLRMAX", 16, 16},
6686	{"TSCCLRTSEL", 14, 2},
6687	{"TSCCLRINCR", 0, 14},
6688	{"CIM_CTL_1_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4934, 0},
6689	{"TSCCLRMAX", 16, 16},
6690	{"TSCCLRTSEL", 14, 2},
6691	{"TSCCLRINCR", 0, 14},
6692	{"CIM_CTL_2_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4944, 0},
6693	{"TSCCLRMAX", 16, 16},
6694	{"TSCCLRTSEL", 14, 2},
6695	{"TSCCLRINCR", 0, 14},
6696	{"CIM_CTL_3_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4954, 0},
6697	{"TSCCLRMAX", 16, 16},
6698	{"TSCCLRTSEL", 14, 2},
6699	{"TSCCLRINCR", 0, 14},
6700	{"CIM_CTL_4_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4964, 0},
6701	{"TSCCLRMAX", 16, 16},
6702	{"TSCCLRTSEL", 14, 2},
6703	{"TSCCLRINCR", 0, 14},
6704	{"CIM_CTL_5_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4974, 0},
6705	{"TSCCLRMAX", 16, 16},
6706	{"TSCCLRTSEL", 14, 2},
6707	{"TSCCLRINCR", 0, 14},
6708	{"CIM_CTL_6_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4984, 0},
6709	{"TSCCLRMAX", 16, 16},
6710	{"TSCCLRTSEL", 14, 2},
6711	{"TSCCLRINCR", 0, 14},
6712	{"CIM_CTL_7_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4994, 0},
6713	{"TSCCLRMAX", 16, 16},
6714	{"TSCCLRTSEL", 14, 2},
6715	{"TSCCLRINCR", 0, 14},
6716	{"CIM_CTL_8_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x49a4, 0},
6717	{"TSCCLRMAX", 16, 16},
6718	{"TSCCLRTSEL", 14, 2},
6719	{"TSCCLRINCR", 0, 14},
6720	{"CIM_CTL_9_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x49b4, 0},
6721	{"TSCCLRMAX", 16, 16},
6722	{"TSCCLRTSEL", 14, 2},
6723	{"TSCCLRINCR", 0, 14},
6724	{"CIM_CTL_10_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x49c4, 0},
6725	{"TSCCLRMAX", 16, 16},
6726	{"TSCCLRTSEL", 14, 2},
6727	{"TSCCLRINCR", 0, 14},
6728	{"CIM_CTL_11_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x49d4, 0},
6729	{"TSCCLRMAX", 16, 16},
6730	{"TSCCLRTSEL", 14, 2},
6731	{"TSCCLRINCR", 0, 14},
6732	{"CIM_CTL_12_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x49e4, 0},
6733	{"TSCCLRMAX", 16, 16},
6734	{"TSCCLRTSEL", 14, 2},
6735	{"TSCCLRINCR", 0, 14},
6736	{"CIM_CTL_13_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x49f4, 0},
6737	{"TSCCLRMAX", 16, 16},
6738	{"TSCCLRTSEL", 14, 2},
6739	{"TSCCLRINCR", 0, 14},
6740	{"CIM_CTL_14_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4a04, 0},
6741	{"TSCCLRMAX", 16, 16},
6742	{"TSCCLRTSEL", 14, 2},
6743	{"TSCCLRINCR", 0, 14},
6744	{"CIM_CTL_15_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4a14, 0},
6745	{"TSCCLRMAX", 16, 16},
6746	{"TSCCLRTSEL", 14, 2},
6747	{"TSCCLRINCR", 0, 14},
6748	{ NULL }
6749};
6750
6751static struct cudbg_reg_info t6_up_cim_4928_to_4a18[] = {
6752	{"CIM_CTL_0_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4928, 0},
6753	{"TSCCLWRRNEG", 31, 1},
6754	{"TSCCLWRRPROT", 30, 1},
6755	{"TSCCLWRR", 0, 26},
6756	{"CIM_CTL_1_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4938, 0},
6757	{"TSCCLWRRNEG", 31, 1},
6758	{"TSCCLWRRPROT", 30, 1},
6759	{"TSCCLWRR", 0, 26},
6760	{"CIM_CTL_2_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4948, 0},
6761	{"TSCCLWRRNEG", 31, 1},
6762	{"TSCCLWRRPROT", 30, 1},
6763	{"TSCCLWRR", 0, 26},
6764	{"CIM_CTL_3_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4958, 0},
6765	{"TSCCLWRRNEG", 31, 1},
6766	{"TSCCLWRRPROT", 30, 1},
6767	{"TSCCLWRR", 0, 26},
6768	{"CIM_CTL_4_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4968, 0},
6769	{"TSCCLWRRNEG", 31, 1},
6770	{"TSCCLWRRPROT", 30, 1},
6771	{"TSCCLWRR", 0, 26},
6772	{"CIM_CTL_5_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4978, 0},
6773	{"TSCCLWRRNEG", 31, 1},
6774	{"TSCCLWRRPROT", 30, 1},
6775	{"TSCCLWRR", 0, 26},
6776	{"CIM_CTL_6_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4988, 0},
6777	{"TSCCLWRRNEG", 31, 1},
6778	{"TSCCLWRRPROT", 30, 1},
6779	{"TSCCLWRR", 0, 26},
6780	{"CIM_CTL_7_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4998, 0},
6781	{"TSCCLWRRNEG", 31, 1},
6782	{"TSCCLWRRPROT", 30, 1},
6783	{"TSCCLWRR", 0, 26},
6784	{"CIM_CTL_8_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x49a8, 0},
6785	{"TSCCLWRRNEG", 31, 1},
6786	{"TSCCLWRRPROT", 30, 1},
6787	{"TSCCLWRR", 0, 26},
6788	{"CIM_CTL_9_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x49b8, 0},
6789	{"TSCCLWRRNEG", 31, 1},
6790	{"TSCCLWRRPROT", 30, 1},
6791	{"TSCCLWRR", 0, 26},
6792	{"CIM_CTL_10_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x49c8, 0},
6793	{"TSCCLWRRNEG", 31, 1},
6794	{"TSCCLWRRPROT", 30, 1},
6795	{"TSCCLWRR", 0, 26},
6796	{"CIM_CTL_11_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x49d8, 0},
6797	{"TSCCLWRRNEG", 31, 1},
6798	{"TSCCLWRRPROT", 30, 1},
6799	{"TSCCLWRR", 0, 26},
6800	{"CIM_CTL_12_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x49e8, 0},
6801	{"TSCCLWRRNEG", 31, 1},
6802	{"TSCCLWRRPROT", 30, 1},
6803	{"TSCCLWRR", 0, 26},
6804	{"CIM_CTL_13_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x49f8, 0},
6805	{"TSCCLWRRNEG", 31, 1},
6806	{"TSCCLWRRPROT", 30, 1},
6807	{"TSCCLWRR", 0, 26},
6808	{"CIM_CTL_14_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4a08, 0},
6809	{"TSCCLWRRNEG", 31, 1},
6810	{"TSCCLWRRPROT", 30, 1},
6811	{"TSCCLWRR", 0, 26},
6812	{"CIM_CTL_15_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4a18, 0},
6813	{"TSCCLWRRNEG", 31, 1},
6814	{"TSCCLWRRPROT", 30, 1},
6815	{"TSCCLWRR", 0, 26},
6816	{ NULL }
6817};
6818
6819static struct cudbg_reg_info t6_up_cim_492c_to_4a1c[] = {
6820	{"CIM_CTL_0_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x492c, 0},
6821	{"PAUSEVECSEL", 28, 2},
6822	{"MPSPAUSEMASK", 20, 8},
6823	{"TSCCLWEIGHT", 0, 16},
6824	{"CIM_CTL_1_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x493c, 0},
6825	{"PAUSEVECSEL", 28, 2},
6826	{"MPSPAUSEMASK", 20, 8},
6827	{"TSCCLWEIGHT", 0, 16},
6828	{"CIM_CTL_2_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x494c, 0},
6829	{"PAUSEVECSEL", 28, 2},
6830	{"MPSPAUSEMASK", 20, 8},
6831	{"TSCCLWEIGHT", 0, 16},
6832	{"CIM_CTL_3_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x495c, 0},
6833	{"PAUSEVECSEL", 28, 2},
6834	{"MPSPAUSEMASK", 20, 8},
6835	{"TSCCLWEIGHT", 0, 16},
6836	{"CIM_CTL_4_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x496c, 0},
6837	{"PAUSEVECSEL", 28, 2},
6838	{"MPSPAUSEMASK", 20, 8},
6839	{"TSCCLWEIGHT", 0, 16},
6840	{"CIM_CTL_5_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x497c, 0},
6841	{"PAUSEVECSEL", 28, 2},
6842	{"MPSPAUSEMASK", 20, 8},
6843	{"TSCCLWEIGHT", 0, 16},
6844	{"CIM_CTL_6_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x498c, 0},
6845	{"PAUSEVECSEL", 28, 2},
6846	{"MPSPAUSEMASK", 20, 8},
6847	{"TSCCLWEIGHT", 0, 16},
6848	{"CIM_CTL_7_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x499c, 0},
6849	{"PAUSEVECSEL", 28, 2},
6850	{"MPSPAUSEMASK", 20, 8},
6851	{"TSCCLWEIGHT", 0, 16},
6852	{"CIM_CTL_8_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x49ac, 0},
6853	{"PAUSEVECSEL", 28, 2},
6854	{"MPSPAUSEMASK", 20, 8},
6855	{"TSCCLWEIGHT", 0, 16},
6856	{"CIM_CTL_9_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x49bc, 0},
6857	{"PAUSEVECSEL", 28, 2},
6858	{"MPSPAUSEMASK", 20, 8},
6859	{"TSCCLWEIGHT", 0, 16},
6860	{"CIM_CTL_10_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x49cc, 0},
6861	{"PAUSEVECSEL", 28, 2},
6862	{"MPSPAUSEMASK", 20, 8},
6863	{"TSCCLWEIGHT", 0, 16},
6864	{"CIM_CTL_11_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x49dc, 0},
6865	{"PAUSEVECSEL", 28, 2},
6866	{"MPSPAUSEMASK", 20, 8},
6867	{"TSCCLWEIGHT", 0, 16},
6868	{"CIM_CTL_12_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x49ec, 0},
6869	{"PAUSEVECSEL", 28, 2},
6870	{"MPSPAUSEMASK", 20, 8},
6871	{"TSCCLWEIGHT", 0, 16},
6872	{"CIM_CTL_13_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x49fc, 0},
6873	{"PAUSEVECSEL", 28, 2},
6874	{"MPSPAUSEMASK", 20, 8},
6875	{"TSCCLWEIGHT", 0, 16},
6876	{"CIM_CTL_14_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x4a0c, 0},
6877	{"PAUSEVECSEL", 28, 2},
6878	{"MPSPAUSEMASK", 20, 8},
6879	{"TSCCLWEIGHT", 0, 16},
6880	{"CIM_CTL_15_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x4a1c, 0},
6881	{"PAUSEVECSEL", 28, 2},
6882	{"MPSPAUSEMASK", 20, 8},
6883	{"TSCCLWEIGHT", 0, 16},
6884	{ NULL }
6885};
6886
6887static struct cudbg_reg_info t6_up_cim_2080_to_20fc[] = {
6888	{"CIM_CTL_STATIC_ALLOCADDR12", 0x2080, 0},
6889	{"StaticAllocAddr", 0, 32},
6890	{"CIM_CTL_STATIC_ALLOCADDR13", 0x2084, 0},
6891	{"StaticAllocAddr", 0, 32},
6892	{"CIM_CTL_STATIC_ALLOCADDR14", 0x2088, 0},
6893	{"StaticAllocAddr", 0, 32},
6894	{"CIM_CTL_STATIC_ALLOCADDR15", 0x208c, 0},
6895	{"StaticAllocAddr", 0, 32},
6896	{"CIM_CTL_FIFO_CNT", 0x2090, 0},
6897	{"CtlFifoCnt", 0, 4},
6898	{"CIM_CTL_GLB_TIMER", 0x2094, 0},
6899	{"GlblTimer", 0, 32},
6900	{"CIM_CTL_TIMER0", 0x2098, 0},
6901	{"Timer0", 0, 32},
6902	{"CIM_CTL_TIMER1", 0x209c, 0},
6903	{"Timer1", 0, 32},
6904	{"CIM_CTL_GEN0", 0x20a0, 0},
6905	{"Gen0", 0, 32},
6906	{"CIM_CTL_GEN1", 0x20a4, 0},
6907	{"Gen1", 0, 32},
6908	{"CIM_CTL_GEN2", 0x20a8, 0},
6909	{"Gen2", 0, 32},
6910	{"CIM_CTL_GEN3", 0x20ac, 0},
6911	{"Gen3", 0, 32},
6912	{"CIM_CTL_GLB_TIMER_TICK", 0x20b0, 0},
6913	{"GlblTTick", 0, 16},
6914	{"CIM_CTL_GEN_TIMER0_CTL", 0x20b4, 0},
6915	{"GenTimerRun", 7, 1},
6916	{"GenTimerTrig", 6, 1},
6917	{"GenTimerAct", 4, 2},
6918	{"GenTimerCfg", 2, 2},
6919	{"GenTimerStop", 1, 1},
6920	{"GenTimerStrt", 0, 1},
6921	{"CIM_CTL_GEN_TIMER0", 0x20b8, 0},
6922	{"GenTimer0", 0, 32},
6923	{"CIM_CTL_GEN_TIMER1_CTL", 0x20bc, 0},
6924	{"GenTimerRun", 7, 1},
6925	{"GenTimerTrig", 6, 1},
6926	{"GenTimerAct", 4, 2},
6927	{"GenTimerCfg", 2, 2},
6928	{"GenTimerStop", 1, 1},
6929	{"GenTimerStrt", 0, 1},
6930	{"CIM_CTL_GEN_TIMER1", 0x20c0, 0},
6931	{"GenTimer0", 0, 32},
6932	{"CIM_CTL_GEN_TIMER2_CTL", 0x20c4, 0},
6933	{"GenTimerRun", 7, 1},
6934	{"GenTimerTrig", 6, 1},
6935	{"GenTimerAct", 4, 2},
6936	{"GenTimerCfg", 2, 2},
6937	{"GenTimerStop", 1, 1},
6938	{"GenTimerStrt", 0, 1},
6939	{"CIM_CTL_GEN_TIMER2", 0x20c8, 0},
6940	{"GenTimer0", 0, 32},
6941	{"CIM_CTL_GEN_TIMER3_CTL", 0x20cc, 0},
6942	{"GenTimerRun", 7, 1},
6943	{"GenTimerTrig", 6, 1},
6944	{"GenTimerAct", 4, 2},
6945	{"GenTimerCfg", 2, 2},
6946	{"GenTimerStop", 1, 1},
6947	{"GenTimerStrt", 0, 1},
6948	{"CIM_CTL_GEN_TIMER3", 0x20d0, 0},
6949	{"GenTimer0", 0, 32},
6950	{"CIM_CTL_0_MAILBOX_VF_STATUS", 0x20e0, 0},
6951	{"MBVFStatus", 0, 32},
6952	{"CIM_CTL_1_MAILBOX_VF_STATUS", 0x20e4, 0},
6953	{"MBVFStatus", 0, 32},
6954	{"CIM_CTL_2_MAILBOX_VF_STATUS", 0x20e8, 0},
6955	{"MBVFStatus", 0, 32},
6956	{"CIM_CTL_3_MAILBOX_VF_STATUS", 0x20ec, 0},
6957	{"MBVFStatus", 0, 32},
6958	{"CIM_CTL_4_MAILBOX_VF_STATUS", 0x20f0, 0},
6959	{"MBVFStatus", 0, 32},
6960	{"CIM_CTL_5_MAILBOX_VF_STATUS", 0x20f4, 0},
6961	{"MBVFStatus", 0, 32},
6962	{"CIM_CTL_6_MAILBOX_VF_STATUS", 0x20f8, 0},
6963	{"MBVFStatus", 0, 32},
6964	{"CIM_CTL_7_MAILBOX_VF_STATUS", 0x20fc, 0},
6965	{"MBVFStatus", 0, 32},
6966	{ NULL }
6967};
6968
6969static struct cudbg_reg_info t5_up_cim_2080_to_20ec[] = {
6970	{"CIM_CTL_STATIC_ALLOCADDR12", 0x2080, 0},
6971	{"StaticAllocAddr", 0, 32},
6972	{"CIM_CTL_STATIC_ALLOCADDR13", 0x2084, 0},
6973	{"StaticAllocAddr", 0, 32},
6974	{"CIM_CTL_STATIC_ALLOCADDR14", 0x2088, 0},
6975	{"StaticAllocAddr", 0, 32},
6976	{"CIM_CTL_STATIC_ALLOCADDR15", 0x208c, 0},
6977	{"StaticAllocAddr", 0, 32},
6978	{"CIM_CTL_FIFO_CNT", 0x2090, 0},
6979	{"CtlFifoCnt", 0, 4},
6980	{"CIM_CTL_GLB_TIMER", 0x2094, 0},
6981	{"GlblTimer", 0, 32},
6982	{"CIM_CTL_TIMER0", 0x2098, 0},
6983	{"Timer0", 0, 32},
6984	{"CIM_CTL_TIMER1", 0x209c, 0},
6985	{"Timer1", 0, 32},
6986	{"CIM_CTL_GEN0", 0x20a0, 0},
6987	{"Gen0", 0, 32},
6988	{"CIM_CTL_GEN1", 0x20a4, 0},
6989	{"Gen1", 0, 32},
6990	{"CIM_CTL_GEN2", 0x20a8, 0},
6991	{"Gen2", 0, 32},
6992	{"CIM_CTL_GEN3", 0x20ac, 0},
6993	{"Gen3", 0, 32},
6994	{"CIM_CTL_GLB_TIMER_TICK", 0x20b0, 0},
6995	{"GlblTTick", 0, 16},
6996	{"CIM_CTL_GEN_TIMER0_CTL", 0x20b4, 0},
6997	{"GenTimerRun", 7, 1},
6998	{"GenTimerTrig", 6, 1},
6999	{"GenTimerAct", 4, 2},
7000	{"GenTimerCfg", 2, 2},
7001	{"GenTimerStop", 1, 1},
7002	{"GenTimerStrt", 0, 1},
7003	{"CIM_CTL_GEN_TIMER0", 0x20b8, 0},
7004	{"GenTimer0", 0, 32},
7005	{"CIM_CTL_GEN_TIMER1_CTL", 0x20bc, 0},
7006	{"GenTimerRun", 7, 1},
7007	{"GenTimerTrig", 6, 1},
7008	{"GenTimerAct", 4, 2},
7009	{"GenTimerCfg", 2, 2},
7010	{"GenTimerStop", 1, 1},
7011	{"GenTimerStrt", 0, 1},
7012	{"CIM_CTL_GEN_TIMER1", 0x20c0, 0},
7013	{"GenTimer0", 0, 32},
7014	{"CIM_CTL_GEN_TIMER2_CTL", 0x20c4, 0},
7015	{"GenTimerRun", 7, 1},
7016	{"GenTimerTrig", 6, 1},
7017	{"GenTimerAct", 4, 2},
7018	{"GenTimerCfg", 2, 2},
7019	{"GenTimerStop", 1, 1},
7020	{"GenTimerStrt", 0, 1},
7021	{"CIM_CTL_GEN_TIMER2", 0x20c8, 0},
7022	{"GenTimer0", 0, 32},
7023	{"CIM_CTL_GEN_TIMER3_CTL", 0x20cc, 0},
7024	{"GenTimerRun", 7, 1},
7025	{"GenTimerTrig", 6, 1},
7026	{"GenTimerAct", 4, 2},
7027	{"GenTimerCfg", 2, 2},
7028	{"GenTimerStop", 1, 1},
7029	{"GenTimerStrt", 0, 1},
7030	{"CIM_CTL_GEN_TIMER3", 0x20d0, 0},
7031	{"GenTimer0", 0, 32},
7032	{"CIM_CTL_0_MAILBOX_VF_STATUS", 0x20e0, 0},
7033	{"MBVFStatus", 0, 32},
7034	{"CIM_CTL_1_MAILBOX_VF_STATUS", 0x20e4, 0},
7035	{"MBVFStatus", 0, 32},
7036	{"CIM_CTL_2_MAILBOX_VF_STATUS", 0x20e8, 0},
7037	{"MBVFStatus", 0, 32},
7038	{"CIM_CTL_3_MAILBOX_VF_STATUS", 0x20ec, 0},
7039	{"MBVFStatus", 0, 32},
7040	{ NULL }
7041};
7042
7043static struct cudbg_reg_info t5_up_cim_00_to_7c[] = {
7044	{"UP_IBQ_CONFIG", 0x0, 0},
7045	{"IbqGen2", 2, 30},
7046	{"IbqBusy", 1, 1},
7047	{"IbqEn", 0, 1},
7048	{"UP_OBQ_CONFIG", 0x4, 0},
7049	{"ObqGen2", 2, 30},
7050	{"ObqBusy", 1, 1},
7051	{"ObqEn", 0, 1},
7052	{"UP_IBQ_GEN", 0x8, 0},
7053	{"IbqGen0", 22, 10},
7054	{"IbqTSCHChnlRdy", 18, 5},
7055	{"IbqMBVFStatus", 17, 1},
7056	{"IbqMBStatus", 16, 1},
7057	{"IbqGen1", 6, 10},
7058	{"IbqEmpty", 0, 6},
7059	{"UP_OBQ_GEN", 0xc, 0},
7060	{"ObqGen", 8, 25},
7061	{"ObqFull", 0, 8},
7062	{"UP_IBQ_0_RDADDR", 0x10, 0},
7063	{"QueID", 13, 19},
7064	{"QueRdAddr", 0, 13},
7065	{"UP_IBQ_0_WRADDR", 0x14, 0},
7066	{"QueID", 13, 19},
7067	{"QueWrAddr", 0, 13},
7068	{"UP_IBQ_0_STATUS", 0x18, 0},
7069	{"QueErrFrame", 31, 1},
7070	{"QueRemFlits", 0, 11},
7071	{"UP_IBQ_0_PKTCNT", 0x1c, 0},
7072	{"QueEOPCnt", 16, 12},
7073	{"QueSOPCnt", 0, 12},
7074	{"UP_IBQ_1_RDADDR", 0x20, 0},
7075	{"QueID", 13, 19},
7076	{"UP_IBQ_1_WRADDR", 0x24, 0},
7077	{"QueID", 13, 19},
7078	{"UP_IBQ_1_STATUS", 0x28, 0},
7079	{"QueErrFrame", 31, 1},
7080	{"QueRemFlits", 0, 11},
7081	{"UP_IBQ_1_PKTCNT", 0x2c, 0},
7082	{"QueEOPCnt", 16, 12},
7083	{"QueSOPCnt", 0, 12},
7084	{"UP_IBQ_2_RDADDR", 0x30, 0},
7085	{"QueID", 13, 19},
7086	{"UP_IBQ_2_WRADDR", 0x34, 0},
7087	{"QueID", 13, 19},
7088	{"UP_IBQ_2_STATUS", 0x38, 0},
7089	{"QueRemFlits", 0, 11},
7090	{"UP_IBQ_2_PKTCNT", 0x3c, 0},
7091	{"QueEOPCnt", 16, 12},
7092	{"QueSOPCnt", 0, 12},
7093	{"UP_IBQ_3_RDADDR", 0x40, 0},
7094	{"QueID", 13, 19},
7095	{"UP_IBQ_3_WRADDR", 0x44, 0},
7096	{"QueID", 13, 19},
7097	{"UP_IBQ_3_STATUS", 0x48, 0},
7098	{"QueRemFlits", 0, 11},
7099	{"UP_IBQ_3_PKTCNT", 0x4c, 0},
7100	{"QueEOPCnt", 16, 12},
7101	{"QueSOPCnt", 0, 12},
7102	{"UP_IBQ_4_RDADDR", 0x50, 0},
7103	{"QueID", 13, 19},
7104	{"UP_IBQ_4_WRADDR", 0x54, 0},
7105	{"QueID", 13, 19},
7106	{"UP_IBQ_4_STATUS", 0x58, 0},
7107	{"QueRemFlits", 0, 11},
7108	{"UP_IBQ_4_PKTCNT", 0x5c, 0},
7109	{"QueEOPCnt", 16, 12},
7110	{"QueSOPCnt", 0, 12},
7111	{"UP_IBQ_5_RDADDR", 0x60, 0},
7112	{"QueID", 13, 19},
7113	{"UP_IBQ_5_WRADDR", 0x64, 0},
7114	{"QueID", 13, 19},
7115	{"UP_IBQ_5_STATUS", 0x68, 0},
7116	{"QueRemFlits", 0, 11},
7117	{"UP_IBQ_5_PKTCNT", 0x6c, 0},
7118	{"QueEOPCnt", 16, 12},
7119	{"QueSOPCnt", 0, 12},
7120	{"UP_OBQ_0_RDADDR", 0x70, 0},
7121	{"QueID", 15, 17},
7122	{"QueRdAddr", 0, 15},
7123	{"UP_OBQ_0_WRADDR", 0x74, 0},
7124	{"QueID", 15, 17},
7125	{"QueWrAddr", 0, 15},
7126	{"UP_OBQ_0_STATUS", 0x78, 0},
7127	{"QueRemFlits", 0, 11},
7128	{"UP_OBQ_0_PKTCNT", 0x7c, 0},
7129	{"QueEOPCnt", 16, 12},
7130	{"QueSOPCnt", 0, 12},
7131	{ NULL }
7132};
7133
7134static struct cudbg_reg_info t6_up_cim_80_to_fc[] = {
7135	{"UP_OBQ_1_RDADDR", 0x80, 0},
7136	{"QueID", 15, 17},
7137	{"QueRdAddr", 0, 15},
7138	{"UP_OBQ_1_WRADDR", 0x84, 0},
7139	{"QueID", 15, 17},
7140	{"QueWrAddr", 0, 15},
7141	{"UP_OBQ_1_STATUS", 0x88, 0},
7142	{"QueRemFlits", 0, 11},
7143	{"UP_OBQ_1_PKTCNT", 0x8c, 0},
7144	{"QueEOPCnt", 16, 12},
7145	{"QueSOPCnt", 0, 12},
7146	{"UP_OBQ_2_RDADDR", 0x90, 0},
7147	{"QueID", 15, 17},
7148	{"QueRdAddr", 0, 15},
7149	{"UP_OBQ_2_WRADDR", 0x94, 0},
7150	{"QueID", 15, 17},
7151	{"QueWrAddr", 0, 15},
7152	{"UP_OBQ_2_STATUS", 0x98, 0},
7153	{"QueRemFlits", 0, 11},
7154	{"UP_OBQ_2_PKTCNT", 0x9c, 0},
7155	{"QueEOPCnt", 16, 12},
7156	{"QueSOPCnt", 0, 12},
7157	{"UP_OBQ_3_RDADDR", 0xa0, 0},
7158	{"QueID", 15, 17},
7159	{"QueRdAddr", 0, 15},
7160	{"UP_OBQ_3_WRADDR", 0xa4, 0},
7161	{"QueID", 15, 17},
7162	{"QueWrAddr", 0, 15},
7163	{"UP_OBQ_3_STATUS", 0xa8, 0},
7164	{"QueRemFlits", 0, 11},
7165	{"UP_OBQ_3_PKTCNT", 0xac, 0},
7166	{"QueEOPCnt", 16, 12},
7167	{"QueSOPCnt", 0, 12},
7168	{"UP_OBQ_4_RDADDR", 0xb0, 0},
7169	{"QueID", 15, 17},
7170	{"QueRdAddr", 0, 15},
7171	{"UP_OBQ_4_WRADDR", 0xb4, 0},
7172	{"QueID", 15, 17},
7173	{"QueWrAddr", 0, 15},
7174	{"UP_OBQ_4_STATUS", 0xb8, 0},
7175	{"QueRemFlits", 0, 11},
7176	{"UP_OBQ_4_PKTCNT", 0xbc, 0},
7177	{"QueEOPCnt", 16, 12},
7178	{"QueSOPCnt", 0, 12},
7179	{"UP_OBQ_5_RDADDR", 0xc0, 0},
7180	{"QueID", 15, 17},
7181	{"QueRdAddr", 0, 15},
7182	{"UP_OBQ_5_WRADDR", 0xc4, 0},
7183	{"QueID", 15, 17},
7184	{"QueWrAddr", 0, 15},
7185	{"UP_OBQ_5_STATUS", 0xc8, 0},
7186	{"QueRemFlits", 0, 11},
7187	{"UP_OBQ_5_PKTCNT", 0xcc, 0},
7188	{"QueEOPCnt", 16, 12},
7189	{"QueSOPCnt", 0, 12},
7190	{"UP_IBQ_0_CONFIG", 0xd0, 0},
7191	{"QueSize", 26, 6},
7192	{"QueBase", 8, 6},
7193	{"QueDbg8BEn", 7, 1},
7194	{"Que1KEn", 6, 1},
7195	{"QueBareAddr", 0, 1},
7196	{"UP_IBQ_0_REALADDR", 0xd4, 0},
7197	{"QueRdAddrWrap", 31, 1},
7198	{"QueWrAddrWrap", 30, 1},
7199	{"QueMemAddr", 3, 11},
7200	{"UP_IBQ_1_CONFIG", 0xd8, 0},
7201	{"QueSize", 26, 6},
7202	{"QueBase", 8, 6},
7203	{"QueDbg8BEn", 7, 1},
7204	{"Que1KEn", 6, 1},
7205	{"QueBareAddr", 0, 1},
7206	{"UP_IBQ_1_REALADDR", 0xdc, 0},
7207	{"QueRdAddrWrap", 31, 1},
7208	{"QueWrAddrWrap", 30, 1},
7209	{"QueMemAddr", 3, 11},
7210	{"UP_IBQ_2_CONFIG", 0xe0, 0},
7211	{"QueSize", 26, 6},
7212	{"QueBase", 8, 6},
7213	{"QueDbg8BEn", 7, 1},
7214	{"Que1KEn", 6, 1},
7215	{"QueBareAddr", 0, 1},
7216	{"UP_IBQ_2_REALADDR", 0xe4, 0},
7217	{"QueRdAddrWrap", 31, 1},
7218	{"QueWrAddrWrap", 30, 1},
7219	{"QueMemAddr", 3, 11},
7220	{"UP_IBQ_3_CONFIG", 0xe8, 0},
7221	{"QueSize", 26, 6},
7222	{"QueBase", 8, 6},
7223	{"QueDbg8BEn", 7, 1},
7224	{"Que1KEn", 6, 1},
7225	{"QueBareAddr", 0, 1},
7226	{"UP_IBQ_3_REALADDR", 0xec, 0},
7227	{"QueRdAddrWrap", 31, 1},
7228	{"QueWrAddrWrap", 30, 1},
7229	{"QueMemAddr", 3, 11},
7230	{"UP_IBQ_4_CONFIG", 0xf0, 0},
7231	{"QueSize", 26, 6},
7232	{"QueBase", 8, 6},
7233	{"QueDbg8BEn", 7, 1},
7234	{"Que1KEn", 6, 1},
7235	{"QueBareAddr", 0, 1},
7236	{"UP_IBQ_4_REALADDR", 0xf4, 0},
7237	{"QueRdAddrWrap", 31, 1},
7238	{"QueWrAddrWrap", 30, 1},
7239	{"QueMemAddr", 3, 11},
7240	{"UP_IBQ_5_CONFIG", 0xf8, 0},
7241	{"QueSize", 26, 6},
7242	{"QueBase", 8, 6},
7243	{"QueDbg8BEn", 7, 1},
7244	{"Que1KEn", 6, 1},
7245	{"QueBareAddr", 0, 1},
7246	{"UP_IBQ_5_REALADDR", 0xfc, 0},
7247	{"QueRdAddrWrap", 31, 1},
7248	{"QueWrAddrWrap", 30, 1},
7249	{"QueMemAddr", 3, 11},
7250	{ NULL }
7251};
7252
7253static struct cudbg_reg_info t5_up_cim_80_to_fc[] = {
7254	{"UP_OBQ_1_RDADDR", 0x80, 0},
7255	{"QueID", 15, 17},
7256	{"QueRdAddr", 0, 15},
7257	{"UP_OBQ_1_WRADDR", 0x84, 0},
7258	{"QueID", 15, 17},
7259	{"QueWrAddr", 0, 15},
7260	{"UP_OBQ_1_STATUS", 0x88, 0},
7261	{"QueRemFlits", 0, 11},
7262	{"UP_OBQ_1_PKTCNT", 0x8c, 0},
7263	{"QueEOPCnt", 16, 12},
7264	{"QueSOPCnt", 0, 12},
7265	{"UP_OBQ_2_RDADDR", 0x90, 0},
7266	{"QueID", 15, 17},
7267	{"QueRdAddr", 0, 15},
7268	{"UP_OBQ_2_WRADDR", 0x94, 0},
7269	{"QueID", 15, 17},
7270	{"QueWrAddr", 0, 15},
7271	{"UP_OBQ_2_STATUS", 0x98, 0},
7272	{"QueRemFlits", 0, 11},
7273	{"UP_OBQ_2_PKTCNT", 0x9c, 0},
7274	{"QueEOPCnt", 16, 12},
7275	{"QueSOPCnt", 0, 12},
7276	{"UP_OBQ_3_RDADDR", 0xa0, 0},
7277	{"QueID", 15, 17},
7278	{"QueRdAddr", 0, 15},
7279	{"UP_OBQ_3_WRADDR", 0xa4, 0},
7280	{"QueID", 15, 17},
7281	{"QueWrAddr", 0, 15},
7282	{"UP_OBQ_3_STATUS", 0xa8, 0},
7283	{"QueRemFlits", 0, 11},
7284	{"UP_OBQ_3_PKTCNT", 0xac, 0},
7285	{"QueEOPCnt", 16, 12},
7286	{"QueSOPCnt", 0, 12},
7287	{"UP_OBQ_4_RDADDR", 0xb0, 0},
7288	{"QueID", 15, 17},
7289	{"QueRdAddr", 0, 15},
7290	{"UP_OBQ_4_WRADDR", 0xb4, 0},
7291	{"QueID", 15, 17},
7292	{"QueWrAddr", 0, 15},
7293	{"UP_OBQ_4_STATUS", 0xb8, 0},
7294	{"QueRemFlits", 0, 11},
7295	{"UP_OBQ_4_PKTCNT", 0xbc, 0},
7296	{"QueEOPCnt", 16, 12},
7297	{"QueSOPCnt", 0, 12},
7298	{"UP_OBQ_5_RDADDR", 0xc0, 0},
7299	{"QueID", 15, 17},
7300	{"QueRdAddr", 0, 15},
7301	{"UP_OBQ_5_WRADDR", 0xc4, 0},
7302	{"QueID", 15, 17},
7303	{"QueWrAddr", 0, 15},
7304	{"UP_OBQ_5_STATUS", 0xc8, 0},
7305	{"QueRemFlits", 0, 11},
7306	{"UP_OBQ_5_PKTCNT", 0xcc, 0},
7307	{"QueEOPCnt", 16, 12},
7308	{"QueSOPCnt", 0, 12},
7309	{"UP_IBQ_0_CONFIG", 0xd0, 0},
7310	{"QueSize", 26, 6},
7311	{"QueBase", 8, 6},
7312	{"QueDbg8BEn", 7, 1},
7313	{"QueBareAddr", 0, 1},
7314	{"UP_IBQ_0_REALADDR", 0xd4, 0},
7315	{"QueRdAddrWrap", 31, 1},
7316	{"QueWrAddrWrap", 30, 1},
7317	{"QueMemAddr", 3, 11},
7318	{"UP_IBQ_1_CONFIG", 0xd8, 0},
7319	{"QueSize", 26, 6},
7320	{"QueBase", 8, 6},
7321	{"QueDbg8BEn", 7, 1},
7322	{"QueBareAddr", 0, 1},
7323	{"UP_IBQ_1_REALADDR", 0xdc, 0},
7324	{"QueRdAddrWrap", 31, 1},
7325	{"QueWrAddrWrap", 30, 1},
7326	{"QueMemAddr", 3, 11},
7327	{"UP_IBQ_2_CONFIG", 0xe0, 0},
7328	{"QueSize", 26, 6},
7329	{"QueBase", 8, 6},
7330	{"QueDbg8BEn", 7, 1},
7331	{"QueBareAddr", 0, 1},
7332	{"UP_IBQ_2_REALADDR", 0xe4, 0},
7333	{"QueRdAddrWrap", 31, 1},
7334	{"QueWrAddrWrap", 30, 1},
7335	{"QueMemAddr", 3, 11},
7336	{"UP_IBQ_3_CONFIG", 0xe8, 0},
7337	{"QueSize", 26, 6},
7338	{"QueBase", 8, 6},
7339	{"QueDbg8BEn", 7, 1},
7340	{"QueBareAddr", 0, 1},
7341	{"UP_IBQ_3_REALADDR", 0xec, 0},
7342	{"QueRdAddrWrap", 31, 1},
7343	{"QueWrAddrWrap", 30, 1},
7344	{"QueMemAddr", 3, 11},
7345	{"UP_IBQ_4_CONFIG", 0xf0, 0},
7346	{"QueSize", 26, 6},
7347	{"QueBase", 8, 6},
7348	{"QueDbg8BEn", 7, 1},
7349	{"QueBareAddr", 0, 1},
7350	{"UP_IBQ_4_REALADDR", 0xf4, 0},
7351	{"QueRdAddrWrap", 31, 1},
7352	{"QueWrAddrWrap", 30, 1},
7353	{"QueMemAddr", 3, 11},
7354	{"UP_IBQ_5_CONFIG", 0xf8, 0},
7355	{"QueSize", 26, 6},
7356	{"QueBase", 8, 6},
7357	{"QueDbg8BEn", 7, 1},
7358	{"QueBareAddr", 0, 1},
7359	{"UP_IBQ_5_REALADDR", 0xfc, 0},
7360	{"QueRdAddrWrap", 31, 1},
7361	{"QueWrAddrWrap", 30, 1},
7362	{"QueMemAddr", 3, 11},
7363	{ NULL }
7364};
7365
7366static struct cudbg_reg_info t6_up_cim_100_to_14c[] = {
7367	{"UP_OBQ_0_CONFIG", 0x100, 0},
7368	{"QueSize", 26, 6},
7369	{"QueBase", 8, 6},
7370	{"QueDbg8BEn", 7, 1},
7371	{"QueBareAddr", 0, 1},
7372	{"UP_OBQ_0_REALADDR", 0x104, 0},
7373	{"QueMemAddr", 3, 11},
7374	{"UP_OBQ_1_CONFIG", 0x108, 0},
7375	{"QueSize", 26, 6},
7376	{"QueBase", 8, 6},
7377	{"QueDbg8BEn", 7, 1},
7378	{"QueBareAddr", 0, 1},
7379	{"UP_OBQ_1_REALADDR", 0x10c, 0},
7380	{"QueMemAddr", 3, 11},
7381	{"UP_OBQ_2_CONFIG", 0x110, 0},
7382	{"QueSize", 26, 6},
7383	{"QueBase", 8, 6},
7384	{"QueDbg8BEn", 7, 1},
7385	{"QueBareAddr", 0, 1},
7386	{"UP_OBQ_2_REALADDR", 0x114, 0},
7387	{"QueMemAddr", 3, 11},
7388	{"UP_OBQ_3_CONFIG", 0x118, 0},
7389	{"QueSize", 26, 6},
7390	{"QueBase", 8, 6},
7391	{"QueDbg8BEn", 7, 1},
7392	{"QueBareAddr", 0, 1},
7393	{"UP_OBQ_3_REALADDR", 0x11c, 0},
7394	{"QueMemAddr", 3, 11},
7395	{"UP_OBQ_4_CONFIG", 0x120, 0},
7396	{"QueSize", 26, 6},
7397	{"QueBase", 8, 6},
7398	{"QueDbg8BEn", 7, 1},
7399	{"QueBareAddr", 0, 1},
7400	{"UP_OBQ_4_REALADDR", 0x124, 0},
7401	{"QueMemAddr", 3, 11},
7402	{"UP_OBQ_5_CONFIG", 0x128, 0},
7403	{"QueSize", 26, 6},
7404	{"QueBase", 8, 6},
7405	{"QueDbg8BEn", 7, 1},
7406	{"QueBareAddr", 0, 1},
7407	{"UP_OBQ_5_REALADDR", 0x12c, 0},
7408	{"QueMemAddr", 3, 11},
7409	{"UP_MAILBOX_STATUS", 0x130, 0},
7410	{"MBGen0", 31, 20},
7411	{"GenTimerTrig", 19, 16},
7412	{"MBGen1", 8, 8},
7413	{"MBPFInt", 0, 8},
7414	{"UP_UP_DBG_LA_CFG", 0x140, 0},
7415	{"UpDbgLaCaptBub", 31, 1},
7416	{"UpDbgLaCaptPCOnly", 30, 1},
7417	{"UpDbgLaMaskStop", 29, 1},
7418	{"UpDbgLaMaskTrig", 28, 1},
7419	{"UpDbgLaWrPtr", 16, 12},
7420	{"UpDbgLaBusy", 14, 1},
7421	{"UpDbgLaRdPtr", 2, 12},
7422	{"UpDbgLaRdEn", 1, 1},
7423	{"UpDbgLaEn", 0, 1},
7424	{"UP_UP_DBG_LA_DATA", 0x144, 0},
7425	{"UpDbgLaWrData", 0, 32},
7426	{"UP_PIO_MST_CONFIG", 0x148, 0},
7427	{"ReqVFVld", 27, 1},
7428	{"FLSrc", 24, 3},
7429	{"SEProt", 23, 1},
7430	{"SESrc", 20, 3},
7431	{"UpRgn", 19, 1},
7432	{"UpPF", 16, 3},
7433	{"UpRID", 8, 8},
7434	{"UP_UP_SELF_CONTROL", 0x14c, 0},
7435	{"UpSelfReset", 0, 1},
7436	{ NULL }
7437};
7438
7439static struct cudbg_reg_info t5_up_cim_100_to_14c[] = {
7440	{"UP_OBQ_0_CONFIG", 0x100, 0},
7441	{"QueSize", 26, 6},
7442	{"QueBase", 8, 6},
7443	{"QueDbg8BEn", 7, 1},
7444	{"QueBareAddr", 0, 1},
7445	{"UP_OBQ_0_REALADDR", 0x104, 0},
7446	{"QueMemAddr", 3, 11},
7447	{"UP_OBQ_1_CONFIG", 0x108, 0},
7448	{"QueSize", 26, 6},
7449	{"QueBase", 8, 6},
7450	{"QueDbg8BEn", 7, 1},
7451	{"QueBareAddr", 0, 1},
7452	{"UP_OBQ_1_REALADDR", 0x10c, 0},
7453	{"QueMemAddr", 3, 11},
7454	{"UP_OBQ_2_CONFIG", 0x110, 0},
7455	{"QueSize", 26, 6},
7456	{"QueBase", 8, 6},
7457	{"QueDbg8BEn", 7, 1},
7458	{"QueBareAddr", 0, 1},
7459	{"UP_OBQ_2_REALADDR", 0x114, 0},
7460	{"QueMemAddr", 3, 11},
7461	{"UP_OBQ_3_CONFIG", 0x118, 0},
7462	{"QueSize", 26, 6},
7463	{"QueBase", 8, 6},
7464	{"QueDbg8BEn", 7, 1},
7465	{"QueBareAddr", 0, 1},
7466	{"UP_OBQ_3_REALADDR", 0x11c, 0},
7467	{"QueMemAddr", 3, 11},
7468	{"UP_OBQ_4_CONFIG", 0x120, 0},
7469	{"QueSize", 26, 6},
7470	{"QueBase", 8, 6},
7471	{"QueDbg8BEn", 7, 1},
7472	{"QueBareAddr", 0, 1},
7473	{"UP_OBQ_4_REALADDR", 0x124, 0},
7474	{"QueMemAddr", 3, 11},
7475	{"UP_OBQ_5_CONFIG", 0x128, 0},
7476	{"QueSize", 26, 6},
7477	{"QueBase", 8, 6},
7478	{"QueDbg8BEn", 7, 1},
7479	{"QueBareAddr", 0, 1},
7480	{"UP_OBQ_5_REALADDR", 0x12c, 0},
7481	{"QueMemAddr", 3, 11},
7482	{"UP_MAILBOX_STATUS", 0x130, 0},
7483	{"MBGen0", 31, 20},
7484	{"GenTimerTrig", 19, 16},
7485	{"MBGen1", 8, 8},
7486	{"MBPFInt", 0, 8},
7487	{"UP_UP_DBG_LA_CFG", 0x140, 0},
7488	{"UpDbgLaCaptBub", 31, 1},
7489	{"UpDbgLaCaptPCOnly", 30, 1},
7490	{"UpDbgLaMaskStop", 29, 1},
7491	{"UpDbgLaMaskTrig", 28, 1},
7492	{"UpDbgLaWrPtr", 16, 12},
7493	{"UpDbgLaBusy", 14, 1},
7494	{"UpDbgLaRdPtr", 2, 12},
7495	{"UpDbgLaRdEn", 1, 1},
7496	{"UpDbgLaEn", 0, 1},
7497	{"UP_UP_DBG_LA_DATA", 0x144, 0},
7498	{"UpDbgLaWrData", 0, 32},
7499	{"UP_PIO_MST_CONFIG", 0x148, 0},
7500	{"ReqVFVld", 27, 1},
7501	{"FLSrc", 24, 3},
7502	{"SEProt", 23, 1},
7503	{"SESrc", 20, 3},
7504	{"UpRgn", 19, 1},
7505	{"UpPF", 16, 3},
7506	{"RSVD", 8, 8},
7507	{"UpRID", 0, 8},
7508	{"UP_UP_SELF_CONTROL", 0x14c, 0},
7509	{"UpSelfReset", 0, 1},
7510	{ NULL }
7511};
7512
7513static struct cudbg_reg_info t6_up_cim_200_to_23c[] = {
7514	{"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_RDY", 0x200, 0},
7515	{"TSCHCHNLCRDY", 0, 32},
7516	{"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_WATCH_RDY", 0x204, 0},
7517	{"TSCHWRRLIMIT", 16, 16},
7518	{"TSCHCHNLCWRDY", 0, 16},
7519	{"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_WATCH_LIST", 0x208, 0},
7520	{"TSCHWRRRELOAD", 16, 16},
7521	{"TSCHCHNLCWATCH", 0, 16},
7522	{"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_TAKE", 0x20c, 0},
7523	{"TSCHCHNLCHDIS", 31, 1},
7524	{"TSCHCHNLWDIS", 30, 1},
7525	{"TSCHCHNLCLDIS", 29, 1},
7526	{"TSCHCHNLCNUM", 24, 5},
7527	{"TSCHCHNLCCNT", 0, 24},
7528	{"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_RDY", 0x210, 0},
7529	{"TSCHCHNLCRDY", 0, 32},
7530	{"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_WATCH_RDY", 0x214, 0},
7531	{"TSCHWRRLIMIT", 16, 16},
7532	{"TSCHCHNLCWRDY", 0, 16},
7533	{"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_WATCH_LIST", 0x218, 0},
7534	{"TSCHWRRRELOAD", 16, 16},
7535	{"TSCHCHNLCWATCH", 0, 16},
7536	{"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_TAKE", 0x21c, 0},
7537	{"TSCHCHNLCHDIS", 31, 1},
7538	{"TSCHCHNLWDIS", 30, 1},
7539	{"TSCHCHNLCLDIS", 29, 1},
7540	{"TSCHCHNLCNUM", 24, 5},
7541	{"TSCHCHNLCCNT", 0, 24},
7542	{"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_RDY", 0x220, 0},
7543	{"TSCHCHNLCRDY", 0, 32},
7544	{"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_WATCH_RDY", 0x224, 0},
7545	{"TSCHWRRLIMIT", 16, 16},
7546	{"TSCHCHNLCWRDY", 0, 16},
7547	{"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_WATCH_LIST", 0x228, 0},
7548	{"TSCHWRRRELOAD", 16, 16},
7549	{"TSCHCHNLCWATCH", 0, 16},
7550	{"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_TAKE", 0x22c, 0},
7551	{"TSCHCHNLCHDIS", 31, 1},
7552	{"TSCHCHNLWDIS", 30, 1},
7553	{"TSCHCHNLCLDIS", 29, 1},
7554	{"TSCHCHNLCNUM", 24, 5},
7555	{"TSCHCHNLCCNT", 0, 24},
7556	{"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_RDY", 0x230, 0},
7557	{"TSCHCHNLCRDY", 0, 32},
7558	{"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_WATCH_RDY", 0x234, 0},
7559	{"TSCHWRRLIMIT", 16, 16},
7560	{"TSCHCHNLCWRDY", 0, 16},
7561	{"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_WATCH_LIST", 0x238, 0},
7562	{"TSCHWRRRELOAD", 16, 16},
7563	{"TSCHCHNLCWATCH", 0, 16},
7564	{"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_TAKE", 0x23c, 0},
7565	{"TSCHCHNLCHDIS", 31, 1},
7566	{"TSCHCHNLWDIS", 30, 1},
7567	{"TSCHCHNLCLDIS", 29, 1},
7568	{"TSCHCHNLCNUM", 24, 5},
7569	{"TSCHCHNLCCNT", 0, 24},
7570	{ NULL }
7571};
7572
7573static struct cudbg_reg_info t5_up_cim_200_to_23c[] = {
7574	{"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_RDY", 0x200, 0},
7575	{"ECO_15444_SGE_DB_BUSY", 31, 1},
7576	{"ECO_15444_PL_INTF_BUSY", 30, 1},
7577	{"TSCHCHNLCRDY", 0, 30},
7578	{"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_WATCH_RDY", 0x204, 0},
7579	{"TSCHWRRLIMIT", 16, 16},
7580	{"TSCHCHNLCWRDY", 0, 16},
7581	{"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_WATCH_LIST", 0x208, 0},
7582	{"TSCHWRRRELOAD", 16, 16},
7583	{"TSCHCHNLCWATCH", 0, 16},
7584	{"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_TAKE", 0x20c, 0},
7585	{"TSCHCHNLCNUM", 24, 5},
7586	{"TSCHCHNLCCNT", 0, 24},
7587	{"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_RDY",