1*7e6ad469SVishal Kulkarni /* 2*7e6ad469SVishal Kulkarni * This file and its contents are supplied under the terms of the 3*7e6ad469SVishal Kulkarni * Common Development and Distribution License ("CDDL"), version 1.0. 4*7e6ad469SVishal Kulkarni * You may only use this file in accordance with the terms of version 5*7e6ad469SVishal Kulkarni * 1.0 of the CDDL. 6*7e6ad469SVishal Kulkarni * 7*7e6ad469SVishal Kulkarni * A full copy of the text of the CDDL should have accompanied this 8*7e6ad469SVishal Kulkarni * source. A copy of the CDDL is also available via the Internet at 9*7e6ad469SVishal Kulkarni * http://www.illumos.org/license/CDDL. 10*7e6ad469SVishal Kulkarni */ 11*7e6ad469SVishal Kulkarni 12*7e6ad469SVishal Kulkarni /* 13*7e6ad469SVishal Kulkarni * Copyright (c) 2019 by Chelsio Communications, Inc. 14*7e6ad469SVishal Kulkarni */ 15*7e6ad469SVishal Kulkarni 16*7e6ad469SVishal Kulkarni #include <stdio.h> 17*7e6ad469SVishal Kulkarni #include <stddef.h> 18*7e6ad469SVishal Kulkarni #include <stdlib.h> 19*7e6ad469SVishal Kulkarni #include <string.h> 20*7e6ad469SVishal Kulkarni #include <ctype.h> 21*7e6ad469SVishal Kulkarni #include <fcntl.h> 22*7e6ad469SVishal Kulkarni #include <unistd.h> 23*7e6ad469SVishal Kulkarni #include <assert.h> 24*7e6ad469SVishal Kulkarni 25*7e6ad469SVishal Kulkarni #include "t4_regs.h" 26*7e6ad469SVishal Kulkarni #include "t4_chip_type.h" 27*7e6ad469SVishal Kulkarni #include "cudbg_view.h" 28*7e6ad469SVishal Kulkarni #include "osdep.h" 29*7e6ad469SVishal Kulkarni #include "t4fw_interface.h" 30*7e6ad469SVishal Kulkarni 31*7e6ad469SVishal Kulkarni #include "cudbg_view_entity.h" 32*7e6ad469SVishal Kulkarni #include "cudbg_entity.h" 33*7e6ad469SVishal Kulkarni #include "cudbg.h" 34*7e6ad469SVishal Kulkarni #include "cudbg_lib_common.h" 35*7e6ad469SVishal Kulkarni #include "fastlz.h" 36*7e6ad469SVishal Kulkarni 37*7e6ad469SVishal Kulkarni extern struct reg_info t6_sge_regs[]; 38*7e6ad469SVishal Kulkarni extern struct reg_info t6_pcie_regs[]; 39*7e6ad469SVishal Kulkarni extern struct reg_info t6_dbg_regs[]; 40*7e6ad469SVishal Kulkarni extern struct reg_info t6_ma_regs[]; 41*7e6ad469SVishal Kulkarni extern struct reg_info t6_cim_regs[]; 42*7e6ad469SVishal Kulkarni extern struct reg_info t6_tp_regs[]; 43*7e6ad469SVishal Kulkarni extern struct reg_info t6_ulp_tx_regs[]; 44*7e6ad469SVishal Kulkarni extern struct reg_info t6_pm_rx_regs[]; 45*7e6ad469SVishal Kulkarni extern struct reg_info t6_pm_tx_regs[]; 46*7e6ad469SVishal Kulkarni extern struct reg_info t6_mps_regs[]; 47*7e6ad469SVishal Kulkarni extern struct reg_info t6_cpl_switch_regs[]; 48*7e6ad469SVishal Kulkarni extern struct reg_info t6_smb_regs[]; 49*7e6ad469SVishal Kulkarni extern struct reg_info t6_i2cm_regs[]; 50*7e6ad469SVishal Kulkarni extern struct reg_info t6_mi_regs[]; 51*7e6ad469SVishal Kulkarni extern struct reg_info t6_uart_regs[]; 52*7e6ad469SVishal Kulkarni extern struct reg_info t6_pmu_regs[]; 53*7e6ad469SVishal Kulkarni extern struct reg_info t6_ulp_rx_regs[]; 54*7e6ad469SVishal Kulkarni extern struct reg_info t6_sf_regs[]; 55*7e6ad469SVishal Kulkarni extern struct reg_info t6_pl_regs[]; 56*7e6ad469SVishal Kulkarni extern struct reg_info t6_le_regs[]; 57*7e6ad469SVishal Kulkarni extern struct reg_info t6_ncsi_regs[]; 58*7e6ad469SVishal Kulkarni extern struct reg_info t6_mac_regs[]; 59*7e6ad469SVishal Kulkarni extern struct reg_info t6_mc_0_regs[]; 60*7e6ad469SVishal Kulkarni extern struct reg_info t6_edc_t60_regs[]; 61*7e6ad469SVishal Kulkarni extern struct reg_info t6_edc_t61_regs[]; 62*7e6ad469SVishal Kulkarni extern struct reg_info t6_hma_t6_regs[]; 63*7e6ad469SVishal Kulkarni 64*7e6ad469SVishal Kulkarni extern struct reg_info t5_sge_regs[]; 65*7e6ad469SVishal Kulkarni extern struct reg_info t5_pcie_regs[]; 66*7e6ad469SVishal Kulkarni extern struct reg_info t5_dbg_regs[]; 67*7e6ad469SVishal Kulkarni extern struct reg_info t5_ma_regs[]; 68*7e6ad469SVishal Kulkarni extern struct reg_info t5_cim_regs[]; 69*7e6ad469SVishal Kulkarni extern struct reg_info t5_tp_regs[]; 70*7e6ad469SVishal Kulkarni extern struct reg_info t5_ulp_tx_regs[]; 71*7e6ad469SVishal Kulkarni extern struct reg_info t5_pm_rx_regs[]; 72*7e6ad469SVishal Kulkarni extern struct reg_info t5_pm_tx_regs[]; 73*7e6ad469SVishal Kulkarni extern struct reg_info t5_mps_regs[]; 74*7e6ad469SVishal Kulkarni extern struct reg_info t5_cpl_switch_regs[]; 75*7e6ad469SVishal Kulkarni extern struct reg_info t5_smb_regs[]; 76*7e6ad469SVishal Kulkarni extern struct reg_info t5_i2cm_regs[]; 77*7e6ad469SVishal Kulkarni extern struct reg_info t5_mi_regs[]; 78*7e6ad469SVishal Kulkarni extern struct reg_info t5_uart_regs[]; 79*7e6ad469SVishal Kulkarni extern struct reg_info t5_pmu_regs[]; 80*7e6ad469SVishal Kulkarni extern struct reg_info t5_ulp_rx_regs[]; 81*7e6ad469SVishal Kulkarni extern struct reg_info t5_sf_regs[]; 82*7e6ad469SVishal Kulkarni extern struct reg_info t5_pl_regs[]; 83*7e6ad469SVishal Kulkarni extern struct reg_info t5_le_regs[]; 84*7e6ad469SVishal Kulkarni extern struct reg_info t5_ncsi_regs[]; 85*7e6ad469SVishal Kulkarni extern struct reg_info t5_mac_regs[]; 86*7e6ad469SVishal Kulkarni extern struct reg_info t5_mc_0_regs[]; 87*7e6ad469SVishal Kulkarni extern struct reg_info t5_mc_1_regs[]; 88*7e6ad469SVishal Kulkarni extern struct reg_info t5_edc_t50_regs[]; 89*7e6ad469SVishal Kulkarni extern struct reg_info t5_edc_t51_regs[]; 90*7e6ad469SVishal Kulkarni extern struct reg_info t5_hma_t5_regs[]; 91*7e6ad469SVishal Kulkarni 92*7e6ad469SVishal Kulkarni #include "reg_defs_t5.c" 93*7e6ad469SVishal Kulkarni #include "reg_defs_t6.c" 94*7e6ad469SVishal Kulkarni 95*7e6ad469SVishal Kulkarni #include <time.h> 96*7e6ad469SVishal Kulkarni #include <stdarg.h> 97*7e6ad469SVishal Kulkarni 98*7e6ad469SVishal Kulkarni int is_t5(enum chip_type chip) 99*7e6ad469SVishal Kulkarni { 100*7e6ad469SVishal Kulkarni return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5); 101*7e6ad469SVishal Kulkarni } 102*7e6ad469SVishal Kulkarni 103*7e6ad469SVishal Kulkarni int is_t6(enum chip_type chip) 104*7e6ad469SVishal Kulkarni { 105*7e6ad469SVishal Kulkarni return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6); 106*7e6ad469SVishal Kulkarni } 107*7e6ad469SVishal Kulkarni 108*7e6ad469SVishal Kulkarni enum { /* adapter flags */ 109*7e6ad469SVishal Kulkarni FULL_INIT_DONE = (1 << 0), 110*7e6ad469SVishal Kulkarni USING_MSI = (1 << 1), 111*7e6ad469SVishal Kulkarni USING_MSIX = (1 << 2), 112*7e6ad469SVishal Kulkarni QUEUES_BOUND = (1 << 3), 113*7e6ad469SVishal Kulkarni FW_OK = (1 << 4), 114*7e6ad469SVishal Kulkarni RSS_TNLALLLOOKUP = (1 << 5), 115*7e6ad469SVishal Kulkarni USING_SOFT_PARAMS = (1 << 6), 116*7e6ad469SVishal Kulkarni MASTER_PF = (1 << 7), 117*7e6ad469SVishal Kulkarni BYPASS_DROP = (1 << 8), 118*7e6ad469SVishal Kulkarni FW_OFLD_CONN = (1 << 9), 119*7e6ad469SVishal Kulkarni }; 120*7e6ad469SVishal Kulkarni 121*7e6ad469SVishal Kulkarni static struct ver_cs { 122*7e6ad469SVishal Kulkarni int major; 123*7e6ad469SVishal Kulkarni int minor; 124*7e6ad469SVishal Kulkarni int changeset; 125*7e6ad469SVishal Kulkarni } ver_to_cs[] = { 126*7e6ad469SVishal Kulkarni {1, 9, 12852}, 127*7e6ad469SVishal Kulkarni {1, 10, 13182}, 128*7e6ad469SVishal Kulkarni {1, 11, 13257}, 129*7e6ad469SVishal Kulkarni {1, 12, 13495}, 130*7e6ad469SVishal Kulkarni {1, 13, 13905}, 131*7e6ad469SVishal Kulkarni {1, 14, 13969}, 132*7e6ad469SVishal Kulkarni }; 133*7e6ad469SVishal Kulkarni 134*7e6ad469SVishal Kulkarni static bool flash_info_banner = true; 135*7e6ad469SVishal Kulkarni 136*7e6ad469SVishal Kulkarni #include "cudbg_view_compat.c" 137*7e6ad469SVishal Kulkarni 138*7e6ad469SVishal Kulkarni int 139*7e6ad469SVishal Kulkarni cudbg_sge_ctxt_check_valid(u32 *buf, int type) 140*7e6ad469SVishal Kulkarni { 141*7e6ad469SVishal Kulkarni int index, bit, bit_pos = 0; 142*7e6ad469SVishal Kulkarni 143*7e6ad469SVishal Kulkarni switch (type) { 144*7e6ad469SVishal Kulkarni case CTXT_EGRESS: 145*7e6ad469SVishal Kulkarni bit_pos = 176; 146*7e6ad469SVishal Kulkarni break; 147*7e6ad469SVishal Kulkarni case CTXT_INGRESS: 148*7e6ad469SVishal Kulkarni bit_pos = 141; 149*7e6ad469SVishal Kulkarni break; 150*7e6ad469SVishal Kulkarni case CTXT_FLM: 151*7e6ad469SVishal Kulkarni bit_pos = 89; 152*7e6ad469SVishal Kulkarni break; 153*7e6ad469SVishal Kulkarni } 154*7e6ad469SVishal Kulkarni index = bit_pos / 32; 155*7e6ad469SVishal Kulkarni bit = bit_pos % 32; 156*7e6ad469SVishal Kulkarni return buf[index] & (1U << bit); 157*7e6ad469SVishal Kulkarni } 158*7e6ad469SVishal Kulkarni 159*7e6ad469SVishal Kulkarni int 160*7e6ad469SVishal Kulkarni cudbg_view_decompress_buff(char *pbuf, 161*7e6ad469SVishal Kulkarni struct cudbg_entity_hdr *entity_hdr, 162*7e6ad469SVishal Kulkarni struct cudbg_buffer *c_buff, 163*7e6ad469SVishal Kulkarni struct cudbg_buffer *dc_buff) 164*7e6ad469SVishal Kulkarni { 165*7e6ad469SVishal Kulkarni int rc = 0; 166*7e6ad469SVishal Kulkarni 167*7e6ad469SVishal Kulkarni c_buff->data = pbuf + entity_hdr->start_offset; 168*7e6ad469SVishal Kulkarni /* Remove padding bytes, if any */ 169*7e6ad469SVishal Kulkarni if (entity_hdr->num_pad) 170*7e6ad469SVishal Kulkarni c_buff->size = entity_hdr->size - entity_hdr->num_pad; 171*7e6ad469SVishal Kulkarni else 172*7e6ad469SVishal Kulkarni c_buff->size = entity_hdr->size; 173*7e6ad469SVishal Kulkarni c_buff->offset = 0; 174*7e6ad469SVishal Kulkarni memset(dc_buff, 0, sizeof(struct cudbg_buffer)); 175*7e6ad469SVishal Kulkarni 176*7e6ad469SVishal Kulkarni rc = validate_buffer(c_buff); 177*7e6ad469SVishal Kulkarni if (rc) 178*7e6ad469SVishal Kulkarni return rc; 179*7e6ad469SVishal Kulkarni 180*7e6ad469SVishal Kulkarni rc = decompress_buffer_wrapper(c_buff, dc_buff); 181*7e6ad469SVishal Kulkarni if (rc) { 182*7e6ad469SVishal Kulkarni free(dc_buff->data); 183*7e6ad469SVishal Kulkarni return rc; 184*7e6ad469SVishal Kulkarni } 185*7e6ad469SVishal Kulkarni return rc; 186*7e6ad469SVishal Kulkarni } 187*7e6ad469SVishal Kulkarni 188*7e6ad469SVishal Kulkarni int 189*7e6ad469SVishal Kulkarni get_entity_rev(struct cudbg_ver_hdr *ver_hdr) 190*7e6ad469SVishal Kulkarni { 191*7e6ad469SVishal Kulkarni if (ver_hdr->signature == CUDBG_ENTITY_SIGNATURE) 192*7e6ad469SVishal Kulkarni return ver_hdr->revision; 193*7e6ad469SVishal Kulkarni return 0; 194*7e6ad469SVishal Kulkarni } 195*7e6ad469SVishal Kulkarni 196*7e6ad469SVishal Kulkarni /* Find Mercurial sw repo changeset number 197*7e6ad469SVishal Kulkarni * where major or minor number set to given number 198*7e6ad469SVishal Kulkarni * */ 199*7e6ad469SVishal Kulkarni int 200*7e6ad469SVishal Kulkarni cudbg_find_changeset(int major, int minor) 201*7e6ad469SVishal Kulkarni { 202*7e6ad469SVishal Kulkarni int i; 203*7e6ad469SVishal Kulkarni 204*7e6ad469SVishal Kulkarni for (i = 0; i < sizeof(ver_to_cs)/sizeof(struct ver_cs); i++) { 205*7e6ad469SVishal Kulkarni if (ver_to_cs[i].major == major && 206*7e6ad469SVishal Kulkarni ver_to_cs[i].minor == minor) 207*7e6ad469SVishal Kulkarni return ver_to_cs[i].changeset; 208*7e6ad469SVishal Kulkarni } 209*7e6ad469SVishal Kulkarni 210*7e6ad469SVishal Kulkarni return -1; 211*7e6ad469SVishal Kulkarni } 212*7e6ad469SVishal Kulkarni 213*7e6ad469SVishal Kulkarni /* Format a value in a unit that differs from the 214*7e6ad469SVishal Kulkarni * value's native unit by the 215*7e6ad469SVishal Kulkarni * given factor. 216*7e6ad469SVishal Kulkarni */ 217*7e6ad469SVishal Kulkarni static void 218*7e6ad469SVishal Kulkarni unit_conv(char *buf, size_t len, unsigned int val, 219*7e6ad469SVishal Kulkarni unsigned int factor) 220*7e6ad469SVishal Kulkarni { 221*7e6ad469SVishal Kulkarni unsigned int rem = val % factor; 222*7e6ad469SVishal Kulkarni 223*7e6ad469SVishal Kulkarni if (rem == 0) 224*7e6ad469SVishal Kulkarni (void) snprintf(buf, len, "%u", val / factor); 225*7e6ad469SVishal Kulkarni else { 226*7e6ad469SVishal Kulkarni while (rem % 10 == 0) 227*7e6ad469SVishal Kulkarni rem /= 10; 228*7e6ad469SVishal Kulkarni (void) snprintf(buf, len, "%u.%u", val / factor, rem); 229*7e6ad469SVishal Kulkarni } 230*7e6ad469SVishal Kulkarni } 231*7e6ad469SVishal Kulkarni 232*7e6ad469SVishal Kulkarni int 233*7e6ad469SVishal Kulkarni validate_next_rec_offset(void *pinbuf, u32 inbuf_size, u32 234*7e6ad469SVishal Kulkarni next_rec_offset) 235*7e6ad469SVishal Kulkarni { 236*7e6ad469SVishal Kulkarni struct cudbg_hdr *cudbg_hdr; 237*7e6ad469SVishal Kulkarni 238*7e6ad469SVishal Kulkarni if (inbuf_size <= next_rec_offset) 239*7e6ad469SVishal Kulkarni return 0; 240*7e6ad469SVishal Kulkarni 241*7e6ad469SVishal Kulkarni cudbg_hdr = (struct cudbg_hdr *)((char *)pinbuf + next_rec_offset); 242*7e6ad469SVishal Kulkarni if ((cudbg_hdr->signature != CUDBG_SIGNATURE) && 243*7e6ad469SVishal Kulkarni (cudbg_hdr->signature != CUDBG_LEGACY_SIGNATURE)) 244*7e6ad469SVishal Kulkarni return 0; /* no next rec */ 245*7e6ad469SVishal Kulkarni 246*7e6ad469SVishal Kulkarni return next_rec_offset; 247*7e6ad469SVishal Kulkarni } 248*7e6ad469SVishal Kulkarni 249*7e6ad469SVishal Kulkarni int 250*7e6ad469SVishal Kulkarni view_ext_entity(char *pinbuf, struct cudbg_entity_hdr *ent_hdr, 251*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, 252*7e6ad469SVishal Kulkarni enum chip_type chip) 253*7e6ad469SVishal Kulkarni { 254*7e6ad469SVishal Kulkarni struct cudbg_entity_hdr *entity_hdr = NULL; 255*7e6ad469SVishal Kulkarni u32 size, total_size = 0; 256*7e6ad469SVishal Kulkarni u32 next_ext_offset = 0; 257*7e6ad469SVishal Kulkarni u32 entity_type; 258*7e6ad469SVishal Kulkarni int rc = 0; 259*7e6ad469SVishal Kulkarni 260*7e6ad469SVishal Kulkarni entity_hdr = (struct cudbg_entity_hdr *) 261*7e6ad469SVishal Kulkarni (pinbuf + ent_hdr->start_offset); 262*7e6ad469SVishal Kulkarni /* Remove padding bytes, if any */ 263*7e6ad469SVishal Kulkarni size = ent_hdr->num_pad ? ent_hdr->size - ent_hdr->num_pad : 264*7e6ad469SVishal Kulkarni ent_hdr->size; 265*7e6ad469SVishal Kulkarni while ((entity_hdr->flag & CUDBG_EXT_DATA_VALID) 266*7e6ad469SVishal Kulkarni && (total_size < size)) { 267*7e6ad469SVishal Kulkarni entity_type = entity_hdr->entity_type; 268*7e6ad469SVishal Kulkarni if (entity_hdr->sys_warn) 269*7e6ad469SVishal Kulkarni printf("Entity warning: Type %s , %d\n", 270*7e6ad469SVishal Kulkarni entity_list[entity_type].name, 271*7e6ad469SVishal Kulkarni entity_hdr->sys_warn); 272*7e6ad469SVishal Kulkarni 273*7e6ad469SVishal Kulkarni if (entity_hdr->hdr_flags) { 274*7e6ad469SVishal Kulkarni printf("Entity error: Type %s, %s\n", 275*7e6ad469SVishal Kulkarni entity_list[entity_type].name, 276*7e6ad469SVishal Kulkarni err_msg[-entity_hdr->hdr_flags]); 277*7e6ad469SVishal Kulkarni if (entity_hdr->sys_err) 278*7e6ad469SVishal Kulkarni printf("System error %d\n", 279*7e6ad469SVishal Kulkarni entity_hdr->sys_err); 280*7e6ad469SVishal Kulkarni 281*7e6ad469SVishal Kulkarni next_ext_offset = entity_hdr->next_ext_offset; 282*7e6ad469SVishal Kulkarni entity_hdr = (struct cudbg_entity_hdr *) 283*7e6ad469SVishal Kulkarni (pinbuf + ent_hdr->start_offset + 284*7e6ad469SVishal Kulkarni next_ext_offset); 285*7e6ad469SVishal Kulkarni continue; 286*7e6ad469SVishal Kulkarni } 287*7e6ad469SVishal Kulkarni if (entity_hdr->size > 0) { 288*7e6ad469SVishal Kulkarni total_size += entity_hdr->size + 289*7e6ad469SVishal Kulkarni sizeof(struct cudbg_entity_hdr); 290*7e6ad469SVishal Kulkarni 291*7e6ad469SVishal Kulkarni rc = view_entity[entity_type - 1] 292*7e6ad469SVishal Kulkarni (pinbuf + ent_hdr->start_offset, 293*7e6ad469SVishal Kulkarni entity_hdr, 294*7e6ad469SVishal Kulkarni cudbg_poutbuf, 295*7e6ad469SVishal Kulkarni chip); 296*7e6ad469SVishal Kulkarni if (rc < 0) 297*7e6ad469SVishal Kulkarni goto out; 298*7e6ad469SVishal Kulkarni } 299*7e6ad469SVishal Kulkarni next_ext_offset = entity_hdr->next_ext_offset; 300*7e6ad469SVishal Kulkarni entity_hdr = (struct cudbg_entity_hdr *) 301*7e6ad469SVishal Kulkarni (pinbuf + ent_hdr->start_offset + next_ext_offset); 302*7e6ad469SVishal Kulkarni } 303*7e6ad469SVishal Kulkarni 304*7e6ad469SVishal Kulkarni if (total_size != size) 305*7e6ad469SVishal Kulkarni printf("Entity warning: Extended entity size mismatch\n"); 306*7e6ad469SVishal Kulkarni 307*7e6ad469SVishal Kulkarni out: 308*7e6ad469SVishal Kulkarni return rc; 309*7e6ad469SVishal Kulkarni } 310*7e6ad469SVishal Kulkarni 311*7e6ad469SVishal Kulkarni static void 312*7e6ad469SVishal Kulkarni cudbg_print_cudbg_header(struct cudbg_hdr *hdr) 313*7e6ad469SVishal Kulkarni { 314*7e6ad469SVishal Kulkarni printf("\n/***************Header Information***************/\n"); 315*7e6ad469SVishal Kulkarni printf("Library Version: %u.%u\n", hdr->major_ver, hdr->minor_ver); 316*7e6ad469SVishal Kulkarni printf("Compressed with: "); 317*7e6ad469SVishal Kulkarni printf("Chip Version: "); 318*7e6ad469SVishal Kulkarni switch (CHELSIO_CHIP_VERSION(hdr->chip_ver)) { 319*7e6ad469SVishal Kulkarni case CHELSIO_T4: 320*7e6ad469SVishal Kulkarni printf("T4 rev: %u\n", CHELSIO_CHIP_RELEASE(hdr->chip_ver)); 321*7e6ad469SVishal Kulkarni break; 322*7e6ad469SVishal Kulkarni case CHELSIO_T5: 323*7e6ad469SVishal Kulkarni printf("T5 rev: %u\n", CHELSIO_CHIP_RELEASE(hdr->chip_ver)); 324*7e6ad469SVishal Kulkarni break; 325*7e6ad469SVishal Kulkarni case CHELSIO_T6: 326*7e6ad469SVishal Kulkarni printf("T6 rev: %u\n", CHELSIO_CHIP_RELEASE(hdr->chip_ver)); 327*7e6ad469SVishal Kulkarni break; 328*7e6ad469SVishal Kulkarni default: 329*7e6ad469SVishal Kulkarni printf("%u (unknown)\n", hdr->chip_ver); 330*7e6ad469SVishal Kulkarni break; 331*7e6ad469SVishal Kulkarni } 332*7e6ad469SVishal Kulkarni printf("/************************************************/\n\n"); 333*7e6ad469SVishal Kulkarni } 334*7e6ad469SVishal Kulkarni 335*7e6ad469SVishal Kulkarni void 336*7e6ad469SVishal Kulkarni cudbg_print_flash_header(void *pinbuf) 337*7e6ad469SVishal Kulkarni { 338*7e6ad469SVishal Kulkarni struct cudbg_flash_hdr *fl_hdr = (struct cudbg_flash_hdr *)pinbuf; 339*7e6ad469SVishal Kulkarni 340*7e6ad469SVishal Kulkarni if (fl_hdr->signature == CUDBG_FL_SIGNATURE && flash_info_banner) { 341*7e6ad469SVishal Kulkarni printf("\n/***************Flash Header information***************/\n"); 342*7e6ad469SVishal Kulkarni printf("Flash signature: %c%c%c%c\n", 343*7e6ad469SVishal Kulkarni (fl_hdr->signature >> 24) & 0xFF, 344*7e6ad469SVishal Kulkarni (fl_hdr->signature >> 16) & 0xFF, 345*7e6ad469SVishal Kulkarni (fl_hdr->signature >> 8) & 0xFF, 346*7e6ad469SVishal Kulkarni fl_hdr->signature & 0xFF); 347*7e6ad469SVishal Kulkarni 348*7e6ad469SVishal Kulkarni printf("Flash payload timestamp (GMT): %s", 349*7e6ad469SVishal Kulkarni asctime(gmtime((time_t *)&fl_hdr->timestamp))); 350*7e6ad469SVishal Kulkarni printf("Flash payload size: %u bytes\n", fl_hdr->data_len); 351*7e6ad469SVishal Kulkarni printf("/******************************************************/\n"); 352*7e6ad469SVishal Kulkarni flash_info_banner = false; 353*7e6ad469SVishal Kulkarni } 354*7e6ad469SVishal Kulkarni } 355*7e6ad469SVishal Kulkarni 356*7e6ad469SVishal Kulkarni int 357*7e6ad469SVishal Kulkarni cudbg_view(void *handle, void *pinbuf, u32 inbuf_size, 358*7e6ad469SVishal Kulkarni void *poutbuf, s64 *poutbuf_size) 359*7e6ad469SVishal Kulkarni { 360*7e6ad469SVishal Kulkarni 361*7e6ad469SVishal Kulkarni struct cudbg_buffer cudbg_poutbuf = {0}; 362*7e6ad469SVishal Kulkarni struct cudbg_entity_hdr *entity_hdr; 363*7e6ad469SVishal Kulkarni u32 info, offset, max_entities, i; 364*7e6ad469SVishal Kulkarni struct cudbg_hdr *tmp_hdr; 365*7e6ad469SVishal Kulkarni u32 next_rec_offset = 0; 366*7e6ad469SVishal Kulkarni int index, bit, all; 367*7e6ad469SVishal Kulkarni int rc = 0, cs; 368*7e6ad469SVishal Kulkarni u8 *dbg_bitmap; 369*7e6ad469SVishal Kulkarni int count = 0; 370*7e6ad469SVishal Kulkarni 371*7e6ad469SVishal Kulkarni dbg_bitmap = ((struct cudbg_private *)handle)->dbg_init.dbg_bitmap; 372*7e6ad469SVishal Kulkarni info = ((struct cudbg_private *)handle)->dbg_init.info; 373*7e6ad469SVishal Kulkarni 374*7e6ad469SVishal Kulkarni if (inbuf_size < (sizeof(struct cudbg_entity_hdr) + 375*7e6ad469SVishal Kulkarni sizeof(struct cudbg_hdr))) { 376*7e6ad469SVishal Kulkarni printf("\n\tInvalid cudbg dump file\n"); 377*7e6ad469SVishal Kulkarni return CUDBG_STATUS_NO_SIGNATURE; 378*7e6ad469SVishal Kulkarni } 379*7e6ad469SVishal Kulkarni 380*7e6ad469SVishal Kulkarni tmp_hdr = (struct cudbg_hdr *)pinbuf; 381*7e6ad469SVishal Kulkarni if ((tmp_hdr->signature != CUDBG_SIGNATURE) && 382*7e6ad469SVishal Kulkarni (tmp_hdr->signature != CUDBG_LEGACY_SIGNATURE)) { 383*7e6ad469SVishal Kulkarni printf("\n\tInvalid cudbg dump file\n"); 384*7e6ad469SVishal Kulkarni return CUDBG_STATUS_NO_SIGNATURE; 385*7e6ad469SVishal Kulkarni } 386*7e6ad469SVishal Kulkarni 387*7e6ad469SVishal Kulkarni if ((tmp_hdr->major_ver != CUDBG_MAJOR_VERSION) || 388*7e6ad469SVishal Kulkarni (tmp_hdr->minor_ver != CUDBG_MINOR_VERSION)) { 389*7e6ad469SVishal Kulkarni printf("\n\tMeta data version mismatch\n"); 390*7e6ad469SVishal Kulkarni printf("\tMeta data version expected %d.%d\n", 391*7e6ad469SVishal Kulkarni CUDBG_MAJOR_VERSION, CUDBG_MINOR_VERSION); 392*7e6ad469SVishal Kulkarni printf("\tMeta data version in dump %d.%d\n", 393*7e6ad469SVishal Kulkarni tmp_hdr->major_ver, tmp_hdr->minor_ver); 394*7e6ad469SVishal Kulkarni 395*7e6ad469SVishal Kulkarni cs = cudbg_find_changeset(tmp_hdr->major_ver, 396*7e6ad469SVishal Kulkarni tmp_hdr->minor_ver); 397*7e6ad469SVishal Kulkarni if (cs != -1) { 398*7e6ad469SVishal Kulkarni printf("\n\tPlease use changeset %d in sw Mercurial "\ 399*7e6ad469SVishal Kulkarni "repo to build cudbg_app with version %d.%d\n", 400*7e6ad469SVishal Kulkarni cs, tmp_hdr->major_ver, tmp_hdr->minor_ver); 401*7e6ad469SVishal Kulkarni 402*7e6ad469SVishal Kulkarni printf("\n\tOr\n\n\tUse precompiled cudbg_app binary for RHEL 5.x from "\ 403*7e6ad469SVishal Kulkarni "vnc52:/home/surendra/vnc52/"\ 404*7e6ad469SVishal Kulkarni "cudbg_app/cudbg_app_<version>\"\n\n"); 405*7e6ad469SVishal Kulkarni 406*7e6ad469SVishal Kulkarni 407*7e6ad469SVishal Kulkarni } 408*7e6ad469SVishal Kulkarni return CUDBG_METADATA_VERSION_MISMATCH; 409*7e6ad469SVishal Kulkarni } 410*7e6ad469SVishal Kulkarni 411*7e6ad469SVishal Kulkarni if (info) 412*7e6ad469SVishal Kulkarni cudbg_print_cudbg_header(tmp_hdr); 413*7e6ad469SVishal Kulkarni 414*7e6ad469SVishal Kulkarni next_rec_offset += tmp_hdr->data_len; 415*7e6ad469SVishal Kulkarni offset = tmp_hdr->hdr_len; 416*7e6ad469SVishal Kulkarni all = dbg_bitmap[0] & (1 << CUDBG_ALL); 417*7e6ad469SVishal Kulkarni max_entities = min(tmp_hdr->max_entities, CUDBG_MAX_ENTITY); 418*7e6ad469SVishal Kulkarni 419*7e6ad469SVishal Kulkarni for (i = 1; i < max_entities; i++) { 420*7e6ad469SVishal Kulkarni index = i / 8; 421*7e6ad469SVishal Kulkarni bit = i % 8; 422*7e6ad469SVishal Kulkarni 423*7e6ad469SVishal Kulkarni if (all || (dbg_bitmap[index] & (1 << bit))) { 424*7e6ad469SVishal Kulkarni entity_hdr = 425*7e6ad469SVishal Kulkarni (struct cudbg_entity_hdr *)((char *)pinbuf + offset); 426*7e6ad469SVishal Kulkarni 427*7e6ad469SVishal Kulkarni if (entity_hdr->sys_warn) 428*7e6ad469SVishal Kulkarni printf("Entity warning: Type %s , %d\n", 429*7e6ad469SVishal Kulkarni entity_list[i].name, 430*7e6ad469SVishal Kulkarni entity_hdr->sys_warn); 431*7e6ad469SVishal Kulkarni 432*7e6ad469SVishal Kulkarni if (entity_hdr->hdr_flags) { 433*7e6ad469SVishal Kulkarni offset += sizeof(struct cudbg_entity_hdr); 434*7e6ad469SVishal Kulkarni printf("Entity error: Type %s, %s\n", 435*7e6ad469SVishal Kulkarni entity_list[i].name, 436*7e6ad469SVishal Kulkarni err_msg[-entity_hdr->hdr_flags]); 437*7e6ad469SVishal Kulkarni if (entity_hdr->sys_err) 438*7e6ad469SVishal Kulkarni printf("System error %d\n", 439*7e6ad469SVishal Kulkarni entity_hdr->sys_err); 440*7e6ad469SVishal Kulkarni 441*7e6ad469SVishal Kulkarni if (poutbuf) 442*7e6ad469SVishal Kulkarni *poutbuf_size = 0; 443*7e6ad469SVishal Kulkarni 444*7e6ad469SVishal Kulkarni continue; 445*7e6ad469SVishal Kulkarni } 446*7e6ad469SVishal Kulkarni memset(&cudbg_poutbuf, 0, sizeof(cudbg_poutbuf)); 447*7e6ad469SVishal Kulkarni if (entity_hdr->size > 0) { 448*7e6ad469SVishal Kulkarni if (poutbuf) { 449*7e6ad469SVishal Kulkarni cudbg_poutbuf.data = poutbuf; 450*7e6ad469SVishal Kulkarni /* poutbuf_size value should not be 451*7e6ad469SVishal Kulkarni * more than 32 bit value 452*7e6ad469SVishal Kulkarni */ 453*7e6ad469SVishal Kulkarni assert(!((*poutbuf_size) >> 32)); 454*7e6ad469SVishal Kulkarni cudbg_poutbuf.size = (u32)*poutbuf_size; 455*7e6ad469SVishal Kulkarni cudbg_poutbuf.offset = 0; 456*7e6ad469SVishal Kulkarni } 457*7e6ad469SVishal Kulkarni 458*7e6ad469SVishal Kulkarni if (info) 459*7e6ad469SVishal Kulkarni printf("%-20s compressed size %u\n", 460*7e6ad469SVishal Kulkarni entity_list[i].name, 461*7e6ad469SVishal Kulkarni entity_hdr->size); 462*7e6ad469SVishal Kulkarni else { 463*7e6ad469SVishal Kulkarni if (entity_hdr->entity_type != 464*7e6ad469SVishal Kulkarni CUDBG_EXT_ENTITY) 465*7e6ad469SVishal Kulkarni printf("%s() dbg entity : %s\n", 466*7e6ad469SVishal Kulkarni __func__, 467*7e6ad469SVishal Kulkarni entity_list[i].name); 468*7e6ad469SVishal Kulkarni 469*7e6ad469SVishal Kulkarni rc = view_entity[i - 1] 470*7e6ad469SVishal Kulkarni ((char *)pinbuf, 471*7e6ad469SVishal Kulkarni entity_hdr, 472*7e6ad469SVishal Kulkarni &cudbg_poutbuf, 473*7e6ad469SVishal Kulkarni tmp_hdr->chip_ver); 474*7e6ad469SVishal Kulkarni 475*7e6ad469SVishal Kulkarni count++; 476*7e6ad469SVishal Kulkarni } 477*7e6ad469SVishal Kulkarni } else if (!all && i != 478*7e6ad469SVishal Kulkarni CUDBG_EXT_ENTITY) { 479*7e6ad469SVishal Kulkarni printf("%s() dbg entity : %s\n", 480*7e6ad469SVishal Kulkarni __func__, entity_list[i].name); 481*7e6ad469SVishal Kulkarni printf("\t%s not available\n", 482*7e6ad469SVishal Kulkarni entity_list[i].name); 483*7e6ad469SVishal Kulkarni } 484*7e6ad469SVishal Kulkarni if (rc < 0) 485*7e6ad469SVishal Kulkarni goto out; 486*7e6ad469SVishal Kulkarni } 487*7e6ad469SVishal Kulkarni offset += sizeof(struct cudbg_entity_hdr); 488*7e6ad469SVishal Kulkarni } 489*7e6ad469SVishal Kulkarni 490*7e6ad469SVishal Kulkarni /* if max_entities in dump is less than current CUDBG_MAX_ENTITY 491*7e6ad469SVishal Kulkarni * it means entities after tmp_hdr->max_entities does not exist 492*7e6ad469SVishal Kulkarni * in that dump 493*7e6ad469SVishal Kulkarni */ 494*7e6ad469SVishal Kulkarni if (tmp_hdr->max_entities < CUDBG_MAX_ENTITY) { 495*7e6ad469SVishal Kulkarni for (i = tmp_hdr->max_entities; i < CUDBG_MAX_ENTITY; i++) { 496*7e6ad469SVishal Kulkarni index = i / 8; 497*7e6ad469SVishal Kulkarni bit = i % 8; 498*7e6ad469SVishal Kulkarni 499*7e6ad469SVishal Kulkarni if (all || (dbg_bitmap[index] & (1 << bit))) { 500*7e6ad469SVishal Kulkarni printf("%s() dbg entity : %s\n", 501*7e6ad469SVishal Kulkarni __func__, entity_list[i].name); 502*7e6ad469SVishal Kulkarni printf("\t%s does not Exist\n", 503*7e6ad469SVishal Kulkarni entity_list[i].name); 504*7e6ad469SVishal Kulkarni } 505*7e6ad469SVishal Kulkarni } 506*7e6ad469SVishal Kulkarni } 507*7e6ad469SVishal Kulkarni if (poutbuf) { 508*7e6ad469SVishal Kulkarni if (!count) 509*7e6ad469SVishal Kulkarni *poutbuf_size = 0; 510*7e6ad469SVishal Kulkarni else 511*7e6ad469SVishal Kulkarni *poutbuf_size = cudbg_poutbuf.size; 512*7e6ad469SVishal Kulkarni } 513*7e6ad469SVishal Kulkarni 514*7e6ad469SVishal Kulkarni return validate_next_rec_offset(pinbuf, inbuf_size, next_rec_offset); 515*7e6ad469SVishal Kulkarni 516*7e6ad469SVishal Kulkarni out: 517*7e6ad469SVishal Kulkarni if (poutbuf) 518*7e6ad469SVishal Kulkarni *poutbuf_size = cudbg_poutbuf.size; 519*7e6ad469SVishal Kulkarni return rc; 520*7e6ad469SVishal Kulkarni } 521*7e6ad469SVishal Kulkarni 522*7e6ad469SVishal Kulkarni int 523*7e6ad469SVishal Kulkarni view_cim_q(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 524*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, 525*7e6ad469SVishal Kulkarni enum chip_type chip) 526*7e6ad469SVishal Kulkarni { 527*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 528*7e6ad469SVishal Kulkarni u32 i, *pdata = NULL; 529*7e6ad469SVishal Kulkarni int rc; 530*7e6ad469SVishal Kulkarni 531*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 532*7e6ad469SVishal Kulkarni if (rc) 533*7e6ad469SVishal Kulkarni return rc; 534*7e6ad469SVishal Kulkarni 535*7e6ad469SVishal Kulkarni pdata = (u32 *)dc_buff.data; 536*7e6ad469SVishal Kulkarni for (i = 0; i < dc_buff.offset / 4; i += 4) 537*7e6ad469SVishal Kulkarni printf("%#06x: %08x %08x %08x "\ 538*7e6ad469SVishal Kulkarni "%08x\n", i * 4, 539*7e6ad469SVishal Kulkarni pdata[i + 0], pdata[i + 1], 540*7e6ad469SVishal Kulkarni pdata[i + 2], pdata[i + 3]); 541*7e6ad469SVishal Kulkarni 542*7e6ad469SVishal Kulkarni return rc; 543*7e6ad469SVishal Kulkarni } 544*7e6ad469SVishal Kulkarni 545*7e6ad469SVishal Kulkarni static int 546*7e6ad469SVishal Kulkarni view_cim_la_t6(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 547*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf) 548*7e6ad469SVishal Kulkarni { 549*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 550*7e6ad469SVishal Kulkarni u32 i, *p, cfg, dc_size; 551*7e6ad469SVishal Kulkarni int rc; 552*7e6ad469SVishal Kulkarni 553*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 554*7e6ad469SVishal Kulkarni if (rc) 555*7e6ad469SVishal Kulkarni return rc; 556*7e6ad469SVishal Kulkarni 557*7e6ad469SVishal Kulkarni dc_size = dc_buff.offset; 558*7e6ad469SVishal Kulkarni p = (u32 *)((char *)dc_buff.data + sizeof(cfg)); 559*7e6ad469SVishal Kulkarni cfg = *((u32 *)dc_buff.data); 560*7e6ad469SVishal Kulkarni dc_size -= sizeof(cfg); 561*7e6ad469SVishal Kulkarni 562*7e6ad469SVishal Kulkarni if (cfg & F_UPDBGLACAPTPCONLY) { 563*7e6ad469SVishal Kulkarni printf("Status Inst Data "\ 564*7e6ad469SVishal Kulkarni "PC\r\n"); 565*7e6ad469SVishal Kulkarni 566*7e6ad469SVishal Kulkarni for (i = 0; i < dc_size; i += 40, p += 10) { 567*7e6ad469SVishal Kulkarni printf(" %02x %08x %08x %08x\n", 568*7e6ad469SVishal Kulkarni p[3] & 0xff, p[2], p[1], p[0]); 569*7e6ad469SVishal Kulkarni 570*7e6ad469SVishal Kulkarni printf(" %02x %02x%06x %02x%06x %02x%06x\n", 571*7e6ad469SVishal Kulkarni (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 572*7e6ad469SVishal Kulkarni p[5] & 0xff, p[4] >> 8, p[4] & 0xff, 573*7e6ad469SVishal Kulkarni p[3] >> 8); 574*7e6ad469SVishal Kulkarni 575*7e6ad469SVishal Kulkarni printf(" %02x %04x%04x %04x%04x %04x%04x\n", 576*7e6ad469SVishal Kulkarni (p[9] >> 16) & 0xff, p[9] & 0xffff, 577*7e6ad469SVishal Kulkarni p[8] >> 16, p[8] & 0xffff, p[7] >> 16, 578*7e6ad469SVishal Kulkarni p[7] & 0xffff, p[6] >> 16); 579*7e6ad469SVishal Kulkarni } 580*7e6ad469SVishal Kulkarni goto err1; 581*7e6ad469SVishal Kulkarni } 582*7e6ad469SVishal Kulkarni 583*7e6ad469SVishal Kulkarni printf("Status Inst Data PC "\ 584*7e6ad469SVishal Kulkarni "LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data\n"); 585*7e6ad469SVishal Kulkarni 586*7e6ad469SVishal Kulkarni for (i = 0; i < dc_size; i += 40, p += 10) { 587*7e6ad469SVishal Kulkarni printf(" %02x %04x%04x %04x%04x "\ 588*7e6ad469SVishal Kulkarni "%04x%04x %08x %08x %08x %08x %08x %08x\n", 589*7e6ad469SVishal Kulkarni (p[9] >> 16) & 0xff, /* Status */ 590*7e6ad469SVishal Kulkarni p[9] & 0xffff, p[8] >> 16, /* Inst */ 591*7e6ad469SVishal Kulkarni p[8] & 0xffff, p[7] >> 16, /* Data */ 592*7e6ad469SVishal Kulkarni p[7] & 0xffff, p[6] >> 16, /* PC */ 593*7e6ad469SVishal Kulkarni p[2], p[1], p[0], /* LS0 Stat, Addr 594*7e6ad469SVishal Kulkarni and Data */ 595*7e6ad469SVishal Kulkarni p[5], p[4], p[3]); /* LS1 Stat, Addr 596*7e6ad469SVishal Kulkarni and Data */ 597*7e6ad469SVishal Kulkarni } 598*7e6ad469SVishal Kulkarni 599*7e6ad469SVishal Kulkarni err1: 600*7e6ad469SVishal Kulkarni return rc; 601*7e6ad469SVishal Kulkarni } 602*7e6ad469SVishal Kulkarni 603*7e6ad469SVishal Kulkarni static int 604*7e6ad469SVishal Kulkarni view_cim_la_t5(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 605*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf) 606*7e6ad469SVishal Kulkarni { 607*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 608*7e6ad469SVishal Kulkarni u32 i, *p, cfg, dc_size; 609*7e6ad469SVishal Kulkarni int rc; 610*7e6ad469SVishal Kulkarni 611*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 612*7e6ad469SVishal Kulkarni if (rc) 613*7e6ad469SVishal Kulkarni return rc; 614*7e6ad469SVishal Kulkarni 615*7e6ad469SVishal Kulkarni dc_size = dc_buff.offset; 616*7e6ad469SVishal Kulkarni p = (u32 *)((char *)dc_buff.data + sizeof(cfg)); 617*7e6ad469SVishal Kulkarni cfg = *((u32 *)dc_buff.data); 618*7e6ad469SVishal Kulkarni dc_size -= sizeof(cfg); 619*7e6ad469SVishal Kulkarni 620*7e6ad469SVishal Kulkarni if (cfg & F_UPDBGLACAPTPCONLY) { 621*7e6ad469SVishal Kulkarni /* as per cim_la_show_3in1() (in 622*7e6ad469SVishal Kulkarni * sw\dev\linux\drv\cxgb4_main.c)*/ 623*7e6ad469SVishal Kulkarni printf("Status Data PC\r\n"); 624*7e6ad469SVishal Kulkarni 625*7e6ad469SVishal Kulkarni for (i = 0; i < dc_size; i += 32, p += 8) { 626*7e6ad469SVishal Kulkarni printf(" %02X %08X %08X\r\n", 627*7e6ad469SVishal Kulkarni (p[5] & 0xFF), p[6], p[7]); 628*7e6ad469SVishal Kulkarni 629*7e6ad469SVishal Kulkarni printf( 630*7e6ad469SVishal Kulkarni " %02X %02X%06X %02X%06X\n", 631*7e6ad469SVishal Kulkarni ((p[3] >> 8) & 0xFF), (p[3] & 0xFF), 632*7e6ad469SVishal Kulkarni (p[4] >> 8), (p[4] & 0xFF), (p[5] >> 8)); 633*7e6ad469SVishal Kulkarni 634*7e6ad469SVishal Kulkarni printf( 635*7e6ad469SVishal Kulkarni " %02X %X%07X %X%07X\r\n", 636*7e6ad469SVishal Kulkarni ((p[0] >> 4) & 0xFF), (p[0] & 0xF), 637*7e6ad469SVishal Kulkarni (p[1] >> 4), (p[1] & 0xF), (p[2] >> 4)); 638*7e6ad469SVishal Kulkarni } 639*7e6ad469SVishal Kulkarni goto err1; 640*7e6ad469SVishal Kulkarni } 641*7e6ad469SVishal Kulkarni 642*7e6ad469SVishal Kulkarni printf("Status Data PC LS0Stat "\ 643*7e6ad469SVishal Kulkarni "LS0Addr LS0Data\n"); 644*7e6ad469SVishal Kulkarni 645*7e6ad469SVishal Kulkarni for (i = 0; i < dc_size; i += 32, p += 8) { 646*7e6ad469SVishal Kulkarni printf("%02x %x%07x %x%07x %08x "\ 647*7e6ad469SVishal Kulkarni "%08x %08x%08x%08x%08x\n", 648*7e6ad469SVishal Kulkarni ((p[0] >> 4) & 0xFF), (p[0] & 0xF), (p[1] >> 4), 649*7e6ad469SVishal Kulkarni (p[1] & 0xF), (p[2] >> 4), (p[2] & 0xF), p[3], 650*7e6ad469SVishal Kulkarni p[4], p[5], p[6], p[7]); 651*7e6ad469SVishal Kulkarni } 652*7e6ad469SVishal Kulkarni err1: 653*7e6ad469SVishal Kulkarni return rc; 654*7e6ad469SVishal Kulkarni } 655*7e6ad469SVishal Kulkarni 656*7e6ad469SVishal Kulkarni int 657*7e6ad469SVishal Kulkarni view_cim_la(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 658*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 659*7e6ad469SVishal Kulkarni { 660*7e6ad469SVishal Kulkarni int rc = -1; 661*7e6ad469SVishal Kulkarni 662*7e6ad469SVishal Kulkarni if (is_t5(chip)) 663*7e6ad469SVishal Kulkarni rc = view_cim_la_t5(pbuf, entity_hdr, cudbg_poutbuf); 664*7e6ad469SVishal Kulkarni else if (is_t6(chip)) 665*7e6ad469SVishal Kulkarni rc = view_cim_la_t6(pbuf, entity_hdr, cudbg_poutbuf); 666*7e6ad469SVishal Kulkarni 667*7e6ad469SVishal Kulkarni return rc; 668*7e6ad469SVishal Kulkarni } 669*7e6ad469SVishal Kulkarni 670*7e6ad469SVishal Kulkarni int 671*7e6ad469SVishal Kulkarni view_cim_ma_la(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 672*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 673*7e6ad469SVishal Kulkarni { 674*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 675*7e6ad469SVishal Kulkarni int rc, i, j; 676*7e6ad469SVishal Kulkarni u32 *p; 677*7e6ad469SVishal Kulkarni 678*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 679*7e6ad469SVishal Kulkarni if (rc) 680*7e6ad469SVishal Kulkarni return rc; 681*7e6ad469SVishal Kulkarni 682*7e6ad469SVishal Kulkarni p = (u32 *)dc_buff.data; 683*7e6ad469SVishal Kulkarni for (i = 0; i <= CIM_MALA_SIZE; i++, p += 4) { 684*7e6ad469SVishal Kulkarni if (i < CIM_MALA_SIZE) { 685*7e6ad469SVishal Kulkarni printf( 686*7e6ad469SVishal Kulkarni "%02x%08x%08x%08x%08x\n", 687*7e6ad469SVishal Kulkarni p[4], p[3], p[2], p[1], p[0]); 688*7e6ad469SVishal Kulkarni } else { 689*7e6ad469SVishal Kulkarni printf("\nCnt ID Tag UE "\ 690*7e6ad469SVishal Kulkarni " Data RDY VLD\n"); 691*7e6ad469SVishal Kulkarni for (j = 0; j < CIM_MALA_SIZE ; j++, p += 3) { 692*7e6ad469SVishal Kulkarni printf( 693*7e6ad469SVishal Kulkarni "%3u %2u %x %u %08x%08x %u "\ 694*7e6ad469SVishal Kulkarni "%u\n", 695*7e6ad469SVishal Kulkarni (p[2] >> 10) & 0xff, 696*7e6ad469SVishal Kulkarni (p[2] >> 7) & 7, (p[2] >> 3) & 0xf, 697*7e6ad469SVishal Kulkarni (p[2] >> 2) & 1, 698*7e6ad469SVishal Kulkarni (p[1] >> 2) | ((p[2] & 3) << 30), 699*7e6ad469SVishal Kulkarni (p[0] >> 2) | ((p[1] & 3) << 30), 700*7e6ad469SVishal Kulkarni (p[0] >> 1) & 1, p[0] & 1); 701*7e6ad469SVishal Kulkarni } 702*7e6ad469SVishal Kulkarni } 703*7e6ad469SVishal Kulkarni } 704*7e6ad469SVishal Kulkarni 705*7e6ad469SVishal Kulkarni return rc; 706*7e6ad469SVishal Kulkarni } 707*7e6ad469SVishal Kulkarni 708*7e6ad469SVishal Kulkarni int 709*7e6ad469SVishal Kulkarni view_cim_qcfg(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 710*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 711*7e6ad469SVishal Kulkarni { 712*7e6ad469SVishal Kulkarni static const char * const pQname[] = { 713*7e6ad469SVishal Kulkarni "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", 714*7e6ad469SVishal Kulkarni "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI" 715*7e6ad469SVishal Kulkarni }; 716*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 717*7e6ad469SVishal Kulkarni struct struct_cim_qcfg *q_cfg_data; 718*7e6ad469SVishal Kulkarni u32 *p, *wr; 719*7e6ad469SVishal Kulkarni int rc, i; 720*7e6ad469SVishal Kulkarni 721*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 722*7e6ad469SVishal Kulkarni if (rc) 723*7e6ad469SVishal Kulkarni return rc; 724*7e6ad469SVishal Kulkarni 725*7e6ad469SVishal Kulkarni q_cfg_data = (struct struct_cim_qcfg *) (dc_buff.data); 726*7e6ad469SVishal Kulkarni p = q_cfg_data->stat; 727*7e6ad469SVishal Kulkarni wr = q_cfg_data->obq_wr; 728*7e6ad469SVishal Kulkarni 729*7e6ad469SVishal Kulkarni printf(" Queue Base Size Thres RdPtr "\ 730*7e6ad469SVishal Kulkarni "WrPtr SOP EOP Avail\n"); 731*7e6ad469SVishal Kulkarni for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) { 732*7e6ad469SVishal Kulkarni printf("%5s %5x %5u %4u %6x %4x "\ 733*7e6ad469SVishal Kulkarni "%4u %4u %5u\n", 734*7e6ad469SVishal Kulkarni pQname[i], 735*7e6ad469SVishal Kulkarni q_cfg_data->base[i], q_cfg_data->size[i], 736*7e6ad469SVishal Kulkarni q_cfg_data->thres[i], G_IBQRDADDR(p[0]), 737*7e6ad469SVishal Kulkarni G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), 738*7e6ad469SVishal Kulkarni G_QUEEOPCNT(p[3]), G_QUEREMFLITS(p[2]) * 16); 739*7e6ad469SVishal Kulkarni } 740*7e6ad469SVishal Kulkarni 741*7e6ad469SVishal Kulkarni for (; i < CIM_NUM_IBQ + CIM_NUM_OBQ; i++, p += 4, wr += 2) { 742*7e6ad469SVishal Kulkarni printf("%5s %5x %5u %11x %4x %4u "\ 743*7e6ad469SVishal Kulkarni "%4u %5u\n", 744*7e6ad469SVishal Kulkarni pQname[i], 745*7e6ad469SVishal Kulkarni q_cfg_data->base[i], q_cfg_data->size[i], 746*7e6ad469SVishal Kulkarni G_QUERDADDR(p[0]) & 0x3fff, 747*7e6ad469SVishal Kulkarni wr[0] - q_cfg_data->base[i], G_QUESOPCNT(p[3]), 748*7e6ad469SVishal Kulkarni G_QUEEOPCNT(p[3]), G_QUEREMFLITS(p[2]) * 16); 749*7e6ad469SVishal Kulkarni } 750*7e6ad469SVishal Kulkarni 751*7e6ad469SVishal Kulkarni return rc; 752*7e6ad469SVishal Kulkarni } 753*7e6ad469SVishal Kulkarni 754*7e6ad469SVishal Kulkarni int 755*7e6ad469SVishal Kulkarni decompress_buffer_wrapper(struct cudbg_buffer *pc_buff, 756*7e6ad469SVishal Kulkarni struct cudbg_buffer *pdc_buff) 757*7e6ad469SVishal Kulkarni { 758*7e6ad469SVishal Kulkarni int rc = 0; 759*7e6ad469SVishal Kulkarni pdc_buff->data = malloc(2 * CUDBG_CHUNK_SIZE); 760*7e6ad469SVishal Kulkarni if (pdc_buff->data == NULL) { 761*7e6ad469SVishal Kulkarni rc = CUDBG_STATUS_NOSPACE; 762*7e6ad469SVishal Kulkarni goto err; 763*7e6ad469SVishal Kulkarni } 764*7e6ad469SVishal Kulkarni pdc_buff->size = 2 * CUDBG_CHUNK_SIZE; 765*7e6ad469SVishal Kulkarni 766*7e6ad469SVishal Kulkarni rc = decompress_buffer(pc_buff, pdc_buff); 767*7e6ad469SVishal Kulkarni if (rc == CUDBG_STATUS_SMALL_BUFF) { 768*7e6ad469SVishal Kulkarni free(pdc_buff->data); 769*7e6ad469SVishal Kulkarni pdc_buff->data = malloc(pdc_buff->size); 770*7e6ad469SVishal Kulkarni 771*7e6ad469SVishal Kulkarni if (pdc_buff->data == NULL) { 772*7e6ad469SVishal Kulkarni printf("malloc failed for size %u\n", pdc_buff->size); 773*7e6ad469SVishal Kulkarni rc = CUDBG_STATUS_NOSPACE; 774*7e6ad469SVishal Kulkarni goto err; 775*7e6ad469SVishal Kulkarni } 776*7e6ad469SVishal Kulkarni rc = decompress_buffer(pc_buff, pdc_buff); 777*7e6ad469SVishal Kulkarni } 778*7e6ad469SVishal Kulkarni err: 779*7e6ad469SVishal Kulkarni return rc; 780*7e6ad469SVishal Kulkarni } 781*7e6ad469SVishal Kulkarni 782*7e6ad469SVishal Kulkarni int 783*7e6ad469SVishal Kulkarni copy_bin_data(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 784*7e6ad469SVishal Kulkarni const char *fname, struct cudbg_buffer *cudbg_poutbuf) 785*7e6ad469SVishal Kulkarni { 786*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 787*7e6ad469SVishal Kulkarni int rc = 0; 788*7e6ad469SVishal Kulkarni 789*7e6ad469SVishal Kulkarni if (cudbg_poutbuf->data == NULL) 790*7e6ad469SVishal Kulkarni return 0; 791*7e6ad469SVishal Kulkarni 792*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 793*7e6ad469SVishal Kulkarni if (rc) 794*7e6ad469SVishal Kulkarni return rc; 795*7e6ad469SVishal Kulkarni 796*7e6ad469SVishal Kulkarni if (dc_buff.size > cudbg_poutbuf->size) { 797*7e6ad469SVishal Kulkarni rc = CUDBG_STATUS_OUTBUFF_OVERFLOW; 798*7e6ad469SVishal Kulkarni cudbg_poutbuf->size = dc_buff.size; 799*7e6ad469SVishal Kulkarni goto err1; 800*7e6ad469SVishal Kulkarni } 801*7e6ad469SVishal Kulkarni 802*7e6ad469SVishal Kulkarni memcpy(cudbg_poutbuf->data, dc_buff.data, dc_buff.size); 803*7e6ad469SVishal Kulkarni cudbg_poutbuf->size = dc_buff.size; 804*7e6ad469SVishal Kulkarni 805*7e6ad469SVishal Kulkarni err1: 806*7e6ad469SVishal Kulkarni return rc; 807*7e6ad469SVishal Kulkarni } 808*7e6ad469SVishal Kulkarni 809*7e6ad469SVishal Kulkarni int 810*7e6ad469SVishal Kulkarni view_edc0_data(char *pbuf, struct cudbg_entity_hdr *ent_hdr, 811*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 812*7e6ad469SVishal Kulkarni { 813*7e6ad469SVishal Kulkarni return copy_bin_data(pbuf, ent_hdr, "_cudbg_edc0.bin", cudbg_poutbuf); 814*7e6ad469SVishal Kulkarni } 815*7e6ad469SVishal Kulkarni 816*7e6ad469SVishal Kulkarni int 817*7e6ad469SVishal Kulkarni view_edc1_data(char *pbuf, struct cudbg_entity_hdr *ent_hdr, 818*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 819*7e6ad469SVishal Kulkarni { 820*7e6ad469SVishal Kulkarni return copy_bin_data(pbuf, ent_hdr, "_cudbg_edc1.bin", cudbg_poutbuf); 821*7e6ad469SVishal Kulkarni } 822*7e6ad469SVishal Kulkarni 823*7e6ad469SVishal Kulkarni int 824*7e6ad469SVishal Kulkarni view_mc0_data(char *pbuf, struct cudbg_entity_hdr *ent_hdr, 825*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 826*7e6ad469SVishal Kulkarni { 827*7e6ad469SVishal Kulkarni return copy_bin_data(pbuf, ent_hdr, "_cudbg_mc0.bin", cudbg_poutbuf); 828*7e6ad469SVishal Kulkarni } 829*7e6ad469SVishal Kulkarni 830*7e6ad469SVishal Kulkarni int 831*7e6ad469SVishal Kulkarni view_mc1_data(char *pbuf, struct cudbg_entity_hdr *ent_hdr, 832*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 833*7e6ad469SVishal Kulkarni { 834*7e6ad469SVishal Kulkarni return copy_bin_data(pbuf, ent_hdr, "_cudbg_mc1.bin", cudbg_poutbuf); 835*7e6ad469SVishal Kulkarni } 836*7e6ad469SVishal Kulkarni 837*7e6ad469SVishal Kulkarni int 838*7e6ad469SVishal Kulkarni view_hma_data(char *pbuf, struct cudbg_entity_hdr *ent_hdr, 839*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 840*7e6ad469SVishal Kulkarni { 841*7e6ad469SVishal Kulkarni return copy_bin_data(pbuf, ent_hdr, "_cudbg_hma.bin", cudbg_poutbuf); 842*7e6ad469SVishal Kulkarni } 843*7e6ad469SVishal Kulkarni 844*7e6ad469SVishal Kulkarni int 845*7e6ad469SVishal Kulkarni view_sw_state(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 846*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 847*7e6ad469SVishal Kulkarni { 848*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 849*7e6ad469SVishal Kulkarni u8 os_type, *caller_string; 850*7e6ad469SVishal Kulkarni struct sw_state *swstate; 851*7e6ad469SVishal Kulkarni char *os, *fwstate; 852*7e6ad469SVishal Kulkarni u32 fw_state; 853*7e6ad469SVishal Kulkarni int rc = 0; 854*7e6ad469SVishal Kulkarni 855*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 856*7e6ad469SVishal Kulkarni if (rc) 857*7e6ad469SVishal Kulkarni return rc; 858*7e6ad469SVishal Kulkarni 859*7e6ad469SVishal Kulkarni swstate = (struct sw_state *) dc_buff.data; 860*7e6ad469SVishal Kulkarni fw_state = swstate->fw_state; 861*7e6ad469SVishal Kulkarni caller_string = swstate->caller_string; 862*7e6ad469SVishal Kulkarni os_type = swstate->os_type; 863*7e6ad469SVishal Kulkarni 864*7e6ad469SVishal Kulkarni printf("\n"); 865*7e6ad469SVishal Kulkarni if (fw_state & F_PCIE_FW_ERR && G_PCIE_FW_EVAL(fw_state) == 866*7e6ad469SVishal Kulkarni PCIE_FW_EVAL_CRASH) 867*7e6ad469SVishal Kulkarni fwstate = "Crashed"; 868*7e6ad469SVishal Kulkarni else 869*7e6ad469SVishal Kulkarni fwstate = "Alive"; 870*7e6ad469SVishal Kulkarni 871*7e6ad469SVishal Kulkarni switch (os_type) { 872*7e6ad469SVishal Kulkarni case CUDBG_OS_TYPE_WINDOWS: 873*7e6ad469SVishal Kulkarni os = "Windows"; 874*7e6ad469SVishal Kulkarni break; 875*7e6ad469SVishal Kulkarni case CUDBG_OS_TYPE_LINUX: 876*7e6ad469SVishal Kulkarni os = "Linux"; 877*7e6ad469SVishal Kulkarni break; 878*7e6ad469SVishal Kulkarni case CUDBG_OS_TYPE_ESX: 879*7e6ad469SVishal Kulkarni os = "ESX"; 880*7e6ad469SVishal Kulkarni break; 881*7e6ad469SVishal Kulkarni case CUDBG_OS_TYPE_UNKNOWN: 882*7e6ad469SVishal Kulkarni default: 883*7e6ad469SVishal Kulkarni os = "Unknown"; 884*7e6ad469SVishal Kulkarni } 885*7e6ad469SVishal Kulkarni 886*7e6ad469SVishal Kulkarni printf("\tFW STATE : %s\n", fwstate); 887*7e6ad469SVishal Kulkarni printf("\tOS : %s\n", os); 888*7e6ad469SVishal Kulkarni printf("\tCALLER : %s\n", caller_string); 889*7e6ad469SVishal Kulkarni printf("\n"); 890*7e6ad469SVishal Kulkarni 891*7e6ad469SVishal Kulkarni return rc; 892*7e6ad469SVishal Kulkarni } 893*7e6ad469SVishal Kulkarni 894*7e6ad469SVishal Kulkarni int 895*7e6ad469SVishal Kulkarni view_cpl_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 896*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 897*7e6ad469SVishal Kulkarni { 898*7e6ad469SVishal Kulkarni struct struct_tp_cpl_stats *tp_cpl_stats_buff; 899*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 900*7e6ad469SVishal Kulkarni struct tp_cpl_stats stats; 901*7e6ad469SVishal Kulkarni int rc = 0; 902*7e6ad469SVishal Kulkarni 903*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 904*7e6ad469SVishal Kulkarni if (rc) 905*7e6ad469SVishal Kulkarni return rc; 906*7e6ad469SVishal Kulkarni 907*7e6ad469SVishal Kulkarni tp_cpl_stats_buff = (struct struct_tp_cpl_stats *) dc_buff.data; 908*7e6ad469SVishal Kulkarni stats = tp_cpl_stats_buff->stats; 909*7e6ad469SVishal Kulkarni if (tp_cpl_stats_buff->nchan == NCHAN) { 910*7e6ad469SVishal Kulkarni printf(" channel 0"\ 911*7e6ad469SVishal Kulkarni " channel 1 channel 2 channel 3\n"); 912*7e6ad469SVishal Kulkarni printf("CPL requests: %10u %10u "\ 913*7e6ad469SVishal Kulkarni "%10u %10u\n", 914*7e6ad469SVishal Kulkarni stats.req[0], stats.req[1], stats.req[2], 915*7e6ad469SVishal Kulkarni stats.req[3]); 916*7e6ad469SVishal Kulkarni printf("CPL responses: %10u %10u "\ 917*7e6ad469SVishal Kulkarni "%10u %10u\n", 918*7e6ad469SVishal Kulkarni stats.rsp[0], stats.rsp[1], stats.rsp[2], 919*7e6ad469SVishal Kulkarni stats.rsp[3]); 920*7e6ad469SVishal Kulkarni } else { 921*7e6ad469SVishal Kulkarni printf(" channel 0"\ 922*7e6ad469SVishal Kulkarni " channel 1\n"); 923*7e6ad469SVishal Kulkarni printf("CPL requests: %10u %10u\n", 924*7e6ad469SVishal Kulkarni stats.req[0], stats.req[1]); 925*7e6ad469SVishal Kulkarni printf("CPL responses: %10u %10u\n", 926*7e6ad469SVishal Kulkarni stats.rsp[0], stats.rsp[1]); 927*7e6ad469SVishal Kulkarni } 928*7e6ad469SVishal Kulkarni 929*7e6ad469SVishal Kulkarni return rc; 930*7e6ad469SVishal Kulkarni } 931*7e6ad469SVishal Kulkarni 932*7e6ad469SVishal Kulkarni int 933*7e6ad469SVishal Kulkarni view_ddp_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 934*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 935*7e6ad469SVishal Kulkarni { 936*7e6ad469SVishal Kulkarni struct tp_usm_stats *tp_usm_stats_buff; 937*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 938*7e6ad469SVishal Kulkarni int rc = 0; 939*7e6ad469SVishal Kulkarni 940*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 941*7e6ad469SVishal Kulkarni if (rc) 942*7e6ad469SVishal Kulkarni return rc; 943*7e6ad469SVishal Kulkarni 944*7e6ad469SVishal Kulkarni tp_usm_stats_buff = (struct tp_usm_stats *) dc_buff.data; 945*7e6ad469SVishal Kulkarni printf("Frames: %u\n", 946*7e6ad469SVishal Kulkarni tp_usm_stats_buff->frames); 947*7e6ad469SVishal Kulkarni printf("Octets: %llu\n", 948*7e6ad469SVishal Kulkarni (unsigned long long)tp_usm_stats_buff->octets); 949*7e6ad469SVishal Kulkarni printf("Drops: %u\n", 950*7e6ad469SVishal Kulkarni tp_usm_stats_buff->drops); 951*7e6ad469SVishal Kulkarni 952*7e6ad469SVishal Kulkarni return rc; 953*7e6ad469SVishal Kulkarni } 954*7e6ad469SVishal Kulkarni 955*7e6ad469SVishal Kulkarni int 956*7e6ad469SVishal Kulkarni view_macstats(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 957*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 958*7e6ad469SVishal Kulkarni { 959*7e6ad469SVishal Kulkarni struct struct_mac_stats_rev1 *macstats_buff1; 960*7e6ad469SVishal Kulkarni struct struct_mac_stats *mac_stats_buff; 961*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 962*7e6ad469SVishal Kulkarni struct port_stats *stats; 963*7e6ad469SVishal Kulkarni u32 port_count, i; 964*7e6ad469SVishal Kulkarni int rc = 0, rev; 965*7e6ad469SVishal Kulkarni 966*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 967*7e6ad469SVishal Kulkarni if (rc) 968*7e6ad469SVishal Kulkarni return rc; 969*7e6ad469SVishal Kulkarni 970*7e6ad469SVishal Kulkarni rev = get_entity_rev((struct cudbg_ver_hdr *)dc_buff.data); 971*7e6ad469SVishal Kulkarni if (rev) { 972*7e6ad469SVishal Kulkarni macstats_buff1 = (struct struct_mac_stats_rev1 *)(dc_buff.data); 973*7e6ad469SVishal Kulkarni port_count = macstats_buff1->port_count; 974*7e6ad469SVishal Kulkarni stats = macstats_buff1->stats; 975*7e6ad469SVishal Kulkarni 976*7e6ad469SVishal Kulkarni } else { 977*7e6ad469SVishal Kulkarni mac_stats_buff = (struct struct_mac_stats *)(dc_buff.data); 978*7e6ad469SVishal Kulkarni port_count = mac_stats_buff->port_count; 979*7e6ad469SVishal Kulkarni stats = mac_stats_buff->stats; 980*7e6ad469SVishal Kulkarni } 981*7e6ad469SVishal Kulkarni 982*7e6ad469SVishal Kulkarni for (i = 0; i < port_count; i++) { 983*7e6ad469SVishal Kulkarni printf("\nMac %d Stats:\n", i); 984*7e6ad469SVishal Kulkarni printf("tx_octets "\ 985*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_octets); 986*7e6ad469SVishal Kulkarni printf("tx_frames "\ 987*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_frames); 988*7e6ad469SVishal Kulkarni printf("tx_bcast_frames "\ 989*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_bcast_frames); 990*7e6ad469SVishal Kulkarni printf("tx_mcast_frames "\ 991*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_mcast_frames); 992*7e6ad469SVishal Kulkarni printf("tx_ucast_frames "\ 993*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_ucast_frames); 994*7e6ad469SVishal Kulkarni printf("tx_error_frames "\ 995*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_error_frames); 996*7e6ad469SVishal Kulkarni printf("tx_frames_64 "\ 997*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_frames_64); 998*7e6ad469SVishal Kulkarni printf("tx_frames_65_127 "\ 999*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_frames_65_127); 1000*7e6ad469SVishal Kulkarni printf("tx_frames_128_255 "\ 1001*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_frames_128_255); 1002*7e6ad469SVishal Kulkarni printf("tx_frames_256_511 "\ 1003*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_frames_256_511); 1004*7e6ad469SVishal Kulkarni printf("tx_frames_512_1023 "\ 1005*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_frames_512_1023); 1006*7e6ad469SVishal Kulkarni printf("tx_frames_1024_1518 "\ 1007*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_frames_1024_1518); 1008*7e6ad469SVishal Kulkarni printf("tx_frames_1519_max "\ 1009*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_frames_1519_max); 1010*7e6ad469SVishal Kulkarni printf("tx_drop "\ 1011*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_drop); 1012*7e6ad469SVishal Kulkarni printf("tx_pause "\ 1013*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_pause); 1014*7e6ad469SVishal Kulkarni printf("tx_ppp0 "\ 1015*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_ppp0); 1016*7e6ad469SVishal Kulkarni printf("tx_ppp1 "\ 1017*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_ppp1); 1018*7e6ad469SVishal Kulkarni printf("tx_ppp2 "\ 1019*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_ppp2); 1020*7e6ad469SVishal Kulkarni printf("tx_ppp3 "\ 1021*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_ppp3); 1022*7e6ad469SVishal Kulkarni printf("tx_ppp4 "\ 1023*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_ppp4); 1024*7e6ad469SVishal Kulkarni printf("tx_ppp5 "\ 1025*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_ppp5); 1026*7e6ad469SVishal Kulkarni printf("tx_ppp6 "\ 1027*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_ppp6); 1028*7e6ad469SVishal Kulkarni printf("tx_ppp7 "\ 1029*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].tx_ppp7); 1030*7e6ad469SVishal Kulkarni printf("rx_octets "\ 1031*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_octets); 1032*7e6ad469SVishal Kulkarni printf("rx_frames "\ 1033*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_frames); 1034*7e6ad469SVishal Kulkarni printf("rx_bcast_frames "\ 1035*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_bcast_frames); 1036*7e6ad469SVishal Kulkarni printf("rx_mcast_frames "\ 1037*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_mcast_frames); 1038*7e6ad469SVishal Kulkarni printf("rx_ucast_frames "\ 1039*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_ucast_frames); 1040*7e6ad469SVishal Kulkarni printf("rx_too_long "\ 1041*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_too_long); 1042*7e6ad469SVishal Kulkarni printf("rx_jabber "\ 1043*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_jabber); 1044*7e6ad469SVishal Kulkarni printf("rx_fcs_err "\ 1045*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_fcs_err); 1046*7e6ad469SVishal Kulkarni printf("rx_len_err "\ 1047*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_len_err); 1048*7e6ad469SVishal Kulkarni printf("rx_symbol_err "\ 1049*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_symbol_err); 1050*7e6ad469SVishal Kulkarni printf("rx_runt "\ 1051*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_runt); 1052*7e6ad469SVishal Kulkarni printf("rx_frames_64 "\ 1053*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_frames_64); 1054*7e6ad469SVishal Kulkarni printf("rx_frames_65_127 "\ 1055*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_frames_65_127); 1056*7e6ad469SVishal Kulkarni printf("rx_frames_128_255 "\ 1057*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_frames_128_255); 1058*7e6ad469SVishal Kulkarni printf("rx_frames_256_511 "\ 1059*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_frames_256_511); 1060*7e6ad469SVishal Kulkarni printf("rx_frames_512_1023 "\ 1061*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_frames_512_1023); 1062*7e6ad469SVishal Kulkarni printf("rx_frames_1024_1518 "\ 1063*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_frames_1024_1518); 1064*7e6ad469SVishal Kulkarni printf("rx_frames_1519_max "\ 1065*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_frames_1519_max); 1066*7e6ad469SVishal Kulkarni printf("rx_pause "\ 1067*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_pause); 1068*7e6ad469SVishal Kulkarni printf("rx_ppp0 "\ 1069*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_ppp0); 1070*7e6ad469SVishal Kulkarni printf("rx_ppp1 "\ 1071*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_ppp1); 1072*7e6ad469SVishal Kulkarni printf("rx_ppp2 "\ 1073*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_ppp2); 1074*7e6ad469SVishal Kulkarni printf("rx_ppp3 "\ 1075*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_ppp3); 1076*7e6ad469SVishal Kulkarni printf("rx_ppp4 "\ 1077*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_ppp4); 1078*7e6ad469SVishal Kulkarni printf("rx_ppp5 "\ 1079*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_ppp5); 1080*7e6ad469SVishal Kulkarni printf("rx_ppp6 "\ 1081*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_ppp6); 1082*7e6ad469SVishal Kulkarni printf("rx_ppp7 "\ 1083*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_ppp7); 1084*7e6ad469SVishal Kulkarni printf("rx_ovflow0 "\ 1085*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_ovflow0); 1086*7e6ad469SVishal Kulkarni printf("rx_ovflow1 "\ 1087*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_ovflow1); 1088*7e6ad469SVishal Kulkarni printf("rx_ovflow2 "\ 1089*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_ovflow2); 1090*7e6ad469SVishal Kulkarni printf("rx_ovflow3 "\ 1091*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_ovflow3); 1092*7e6ad469SVishal Kulkarni printf("rx_trunc0 "\ 1093*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_trunc0); 1094*7e6ad469SVishal Kulkarni printf("rx_trunc1 "\ 1095*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_trunc1); 1096*7e6ad469SVishal Kulkarni printf("rx_trunc2 "\ 1097*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_trunc2); 1098*7e6ad469SVishal Kulkarni printf("rx_trunc3 "\ 1099*7e6ad469SVishal Kulkarni "%64llu\n", stats[i].rx_trunc3); 1100*7e6ad469SVishal Kulkarni } 1101*7e6ad469SVishal Kulkarni 1102*7e6ad469SVishal Kulkarni return rc; 1103*7e6ad469SVishal Kulkarni } 1104*7e6ad469SVishal Kulkarni 1105*7e6ad469SVishal Kulkarni int 1106*7e6ad469SVishal Kulkarni view_ulptx_la(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 1107*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 1108*7e6ad469SVishal Kulkarni { 1109*7e6ad469SVishal Kulkarni struct struct_ulptx_la *ulptx_la_buff; 1110*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 1111*7e6ad469SVishal Kulkarni void *data; 1112*7e6ad469SVishal Kulkarni int i, rc = 0, rev; 1113*7e6ad469SVishal Kulkarni 1114*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 1115*7e6ad469SVishal Kulkarni if (rc) 1116*7e6ad469SVishal Kulkarni return rc; 1117*7e6ad469SVishal Kulkarni 1118*7e6ad469SVishal Kulkarni data = dc_buff.data + sizeof(struct cudbg_ver_hdr); 1119*7e6ad469SVishal Kulkarni rev = get_entity_rev((struct cudbg_ver_hdr *)dc_buff.data); 1120*7e6ad469SVishal Kulkarni switch (rev) { 1121*7e6ad469SVishal Kulkarni case 0: 1122*7e6ad469SVishal Kulkarni /* for rev 0 there is no version hdr so 1123*7e6ad469SVishal Kulkarni * passing dc_buff.data */ 1124*7e6ad469SVishal Kulkarni rc = view_ulptx_la_rev0(dc_buff.data, cudbg_poutbuf); 1125*7e6ad469SVishal Kulkarni goto err1; 1126*7e6ad469SVishal Kulkarni case CUDBG_ULPTX_LA_REV: 1127*7e6ad469SVishal Kulkarni /* for rev 1, print first rev 0 and then remaining of rev 1 */ 1128*7e6ad469SVishal Kulkarni rc = view_ulptx_la_rev0(data, cudbg_poutbuf); 1129*7e6ad469SVishal Kulkarni if (rc < 0) 1130*7e6ad469SVishal Kulkarni goto err1; 1131*7e6ad469SVishal Kulkarni ulptx_la_buff = (struct struct_ulptx_la *)data; 1132*7e6ad469SVishal Kulkarni break; 1133*7e6ad469SVishal Kulkarni default: 1134*7e6ad469SVishal Kulkarni printf("Unsupported revision %u. Only supports <= %u\n", 1135*7e6ad469SVishal Kulkarni rev, CUDBG_ULPTX_LA_REV); 1136*7e6ad469SVishal Kulkarni goto err1; 1137*7e6ad469SVishal Kulkarni } 1138*7e6ad469SVishal Kulkarni 1139*7e6ad469SVishal Kulkarni printf("\n=======================DUMPING ULP_TX_ASIC_DEBUG=======================\n\n"); 1140*7e6ad469SVishal Kulkarni 1141*7e6ad469SVishal Kulkarni for (i = 0; i < CUDBG_NUM_ULPTX_ASIC_READ; i++) { 1142*7e6ad469SVishal Kulkarni printf("[0x%x][%#2x] %-24s %#-16x [%u]\n", 1143*7e6ad469SVishal Kulkarni A_ULP_TX_ASIC_DEBUG_CTRL, i, 1144*7e6ad469SVishal Kulkarni "A_ULP_TX_ASIC_DEBUG_CTRL", 1145*7e6ad469SVishal Kulkarni ulptx_la_buff->rdptr_asic[i], 1146*7e6ad469SVishal Kulkarni ulptx_la_buff->rdptr_asic[i]); 1147*7e6ad469SVishal Kulkarni printf("[0x%x][%#2x] %-24s %#-16x [%u]\n", 1148*7e6ad469SVishal Kulkarni A_ULP_TX_ASIC_DEBUG_0, 1149*7e6ad469SVishal Kulkarni i, "A_ULP_TX_ASIC_DEBUG_0", 1150*7e6ad469SVishal Kulkarni ulptx_la_buff->rddata_asic[i][0], 1151*7e6ad469SVishal Kulkarni ulptx_la_buff->rddata_asic[i][0]); 1152*7e6ad469SVishal Kulkarni printf("[0x%x][%#2x] %-24s %#-16x [%u]\n", 1153*7e6ad469SVishal Kulkarni A_ULP_TX_ASIC_DEBUG_1, 1154*7e6ad469SVishal Kulkarni i, "A_ULP_TX_ASIC_DEBUG_1", 1155*7e6ad469SVishal Kulkarni ulptx_la_buff->rddata_asic[i][1], 1156*7e6ad469SVishal Kulkarni ulptx_la_buff->rddata_asic[i][1]); 1157*7e6ad469SVishal Kulkarni printf("[0x%x][%#2x] %-24s %#-16x [%u]\n", 1158*7e6ad469SVishal Kulkarni A_ULP_TX_ASIC_DEBUG_2, 1159*7e6ad469SVishal Kulkarni i, "A_ULP_TX_ASIC_DEBUG_2", 1160*7e6ad469SVishal Kulkarni ulptx_la_buff->rddata_asic[i][2], 1161*7e6ad469SVishal Kulkarni ulptx_la_buff->rddata_asic[i][2]); 1162*7e6ad469SVishal Kulkarni printf("[0x%x][%#2x] %-24s %#-16x [%u]\n", 1163*7e6ad469SVishal Kulkarni A_ULP_TX_ASIC_DEBUG_3, 1164*7e6ad469SVishal Kulkarni i, "A_ULP_TX_ASIC_DEBUG_3", 1165*7e6ad469SVishal Kulkarni ulptx_la_buff->rddata_asic[i][3], 1166*7e6ad469SVishal Kulkarni ulptx_la_buff->rddata_asic[i][3]); 1167*7e6ad469SVishal Kulkarni printf("[0x%x][%#2x] %-24s %#-16x [%u]\n", 1168*7e6ad469SVishal Kulkarni A_ULP_TX_ASIC_DEBUG_4, 1169*7e6ad469SVishal Kulkarni i, "A_ULP_TX_ASIC_DEBUG_4", 1170*7e6ad469SVishal Kulkarni ulptx_la_buff->rddata_asic[i][4], 1171*7e6ad469SVishal Kulkarni ulptx_la_buff->rddata_asic[i][4]); 1172*7e6ad469SVishal Kulkarni printf("[0x%x][%#2x] %-24s %#-16x [%u]\n", 1173*7e6ad469SVishal Kulkarni PM_RX_BASE_ADDR, 1174*7e6ad469SVishal Kulkarni i, "PM_RX_BASE_ADDR", 1175*7e6ad469SVishal Kulkarni ulptx_la_buff->rddata_asic[i][5], 1176*7e6ad469SVishal Kulkarni ulptx_la_buff->rddata_asic[i][5]); 1177*7e6ad469SVishal Kulkarni printf("\n"); 1178*7e6ad469SVishal Kulkarni } 1179*7e6ad469SVishal Kulkarni 1180*7e6ad469SVishal Kulkarni err1: 1181*7e6ad469SVishal Kulkarni return rc; 1182*7e6ad469SVishal Kulkarni 1183*7e6ad469SVishal Kulkarni } 1184*7e6ad469SVishal Kulkarni 1185*7e6ad469SVishal Kulkarni int 1186*7e6ad469SVishal Kulkarni view_ulprx_la(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 1187*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 1188*7e6ad469SVishal Kulkarni { 1189*7e6ad469SVishal Kulkarni struct struct_ulprx_la *ulprx_la_buff; 1190*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 1191*7e6ad469SVishal Kulkarni int rc = 0; 1192*7e6ad469SVishal Kulkarni u32 i, *p; 1193*7e6ad469SVishal Kulkarni 1194*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 1195*7e6ad469SVishal Kulkarni if (rc) 1196*7e6ad469SVishal Kulkarni return rc; 1197*7e6ad469SVishal Kulkarni 1198*7e6ad469SVishal Kulkarni ulprx_la_buff = (struct struct_ulprx_la *) dc_buff.data; 1199*7e6ad469SVishal Kulkarni p = ulprx_la_buff->data; 1200*7e6ad469SVishal Kulkarni 1201*7e6ad469SVishal Kulkarni printf( 1202*7e6ad469SVishal Kulkarni " Pcmd Type Message Data\n"); 1203*7e6ad469SVishal Kulkarni for (i = 0; i < ulprx_la_buff->size; i++, p += 8) 1204*7e6ad469SVishal Kulkarni printf( 1205*7e6ad469SVishal Kulkarni "%08x%08x %4x %08x %08x%08x%08x%08x\n", 1206*7e6ad469SVishal Kulkarni p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 1207*7e6ad469SVishal Kulkarni 1208*7e6ad469SVishal Kulkarni return rc; 1209*7e6ad469SVishal Kulkarni } 1210*7e6ad469SVishal Kulkarni 1211*7e6ad469SVishal Kulkarni int 1212*7e6ad469SVishal Kulkarni view_wc_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 1213*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 1214*7e6ad469SVishal Kulkarni { 1215*7e6ad469SVishal Kulkarni struct struct_wc_stats *wc_stats_buff; 1216*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 1217*7e6ad469SVishal Kulkarni int rc = 0; 1218*7e6ad469SVishal Kulkarni 1219*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 1220*7e6ad469SVishal Kulkarni if (rc) 1221*7e6ad469SVishal Kulkarni return rc; 1222*7e6ad469SVishal Kulkarni 1223*7e6ad469SVishal Kulkarni wc_stats_buff = (struct struct_wc_stats *) dc_buff.data; 1224*7e6ad469SVishal Kulkarni 1225*7e6ad469SVishal Kulkarni printf("WriteCoalSuccess: %u\n", 1226*7e6ad469SVishal Kulkarni wc_stats_buff->wr_cl_success); 1227*7e6ad469SVishal Kulkarni printf("WriteCoalFail: %u\n", 1228*7e6ad469SVishal Kulkarni wc_stats_buff->wr_cl_fail); 1229*7e6ad469SVishal Kulkarni 1230*7e6ad469SVishal Kulkarni return rc; 1231*7e6ad469SVishal Kulkarni } 1232*7e6ad469SVishal Kulkarni 1233*7e6ad469SVishal Kulkarni static int 1234*7e6ad469SVishal Kulkarni field_desc_show(u64 v, const struct field_desc *p, 1235*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf) 1236*7e6ad469SVishal Kulkarni { 1237*7e6ad469SVishal Kulkarni int line_size = 0; 1238*7e6ad469SVishal Kulkarni char buf[32]; 1239*7e6ad469SVishal Kulkarni int rc = 0; 1240*7e6ad469SVishal Kulkarni 1241*7e6ad469SVishal Kulkarni while (p->name) { 1242*7e6ad469SVishal Kulkarni u64 mask = (1ULL << p->width) - 1; 1243*7e6ad469SVishal Kulkarni int len = snprintf(buf, sizeof(buf), "%s: %llu", p->name, 1244*7e6ad469SVishal Kulkarni ((unsigned long long)v >> p->start) & mask); 1245*7e6ad469SVishal Kulkarni 1246*7e6ad469SVishal Kulkarni if (line_size + len >= 79) { 1247*7e6ad469SVishal Kulkarni line_size = 8; 1248*7e6ad469SVishal Kulkarni printf("\n "); 1249*7e6ad469SVishal Kulkarni } 1250*7e6ad469SVishal Kulkarni printf("%s ", buf); 1251*7e6ad469SVishal Kulkarni line_size += len + 1; 1252*7e6ad469SVishal Kulkarni p++; 1253*7e6ad469SVishal Kulkarni } 1254*7e6ad469SVishal Kulkarni printf("\n"); 1255*7e6ad469SVishal Kulkarni 1256*7e6ad469SVishal Kulkarni return rc; 1257*7e6ad469SVishal Kulkarni } 1258*7e6ad469SVishal Kulkarni 1259*7e6ad469SVishal Kulkarni static int 1260*7e6ad469SVishal Kulkarni tp_la_show(void *v, int idx, struct cudbg_buffer *cudbg_poutbuf) 1261*7e6ad469SVishal Kulkarni { 1262*7e6ad469SVishal Kulkarni const u64 *p = v; 1263*7e6ad469SVishal Kulkarni int rc; 1264*7e6ad469SVishal Kulkarni 1265*7e6ad469SVishal Kulkarni rc = field_desc_show(*p, tp_la0, cudbg_poutbuf); 1266*7e6ad469SVishal Kulkarni return rc; 1267*7e6ad469SVishal Kulkarni } 1268*7e6ad469SVishal Kulkarni 1269*7e6ad469SVishal Kulkarni static int 1270*7e6ad469SVishal Kulkarni tp_la_show2(void *v, int idx, struct cudbg_buffer *cudbg_poutbuf) 1271*7e6ad469SVishal Kulkarni { 1272*7e6ad469SVishal Kulkarni const u64 *p = v; 1273*7e6ad469SVishal Kulkarni int rc; 1274*7e6ad469SVishal Kulkarni 1275*7e6ad469SVishal Kulkarni if (idx) 1276*7e6ad469SVishal Kulkarni printf("'\n"); 1277*7e6ad469SVishal Kulkarni rc = field_desc_show(p[0], tp_la0, cudbg_poutbuf); 1278*7e6ad469SVishal Kulkarni if (rc < 0) 1279*7e6ad469SVishal Kulkarni goto err1; 1280*7e6ad469SVishal Kulkarni if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 1281*7e6ad469SVishal Kulkarni rc = field_desc_show(p[1], tp_la0, cudbg_poutbuf); 1282*7e6ad469SVishal Kulkarni 1283*7e6ad469SVishal Kulkarni err1: 1284*7e6ad469SVishal Kulkarni return rc; 1285*7e6ad469SVishal Kulkarni } 1286*7e6ad469SVishal Kulkarni 1287*7e6ad469SVishal Kulkarni static int 1288*7e6ad469SVishal Kulkarni tp_la_show3(void *v, int idx, struct cudbg_buffer *cudbg_poutbuf) 1289*7e6ad469SVishal Kulkarni { 1290*7e6ad469SVishal Kulkarni const u64 *p = v; 1291*7e6ad469SVishal Kulkarni int rc; 1292*7e6ad469SVishal Kulkarni 1293*7e6ad469SVishal Kulkarni if (idx) 1294*7e6ad469SVishal Kulkarni printf("\n"); 1295*7e6ad469SVishal Kulkarni rc = field_desc_show(p[0], tp_la0, cudbg_poutbuf); 1296*7e6ad469SVishal Kulkarni if (rc < 0) 1297*7e6ad469SVishal Kulkarni goto err1; 1298*7e6ad469SVishal Kulkarni if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 1299*7e6ad469SVishal Kulkarni rc = field_desc_show(p[1], (p[0] & BIT(17)) ? tp_la2 : tp_la1, 1300*7e6ad469SVishal Kulkarni cudbg_poutbuf); 1301*7e6ad469SVishal Kulkarni 1302*7e6ad469SVishal Kulkarni err1: 1303*7e6ad469SVishal Kulkarni return rc; 1304*7e6ad469SVishal Kulkarni } 1305*7e6ad469SVishal Kulkarni 1306*7e6ad469SVishal Kulkarni int 1307*7e6ad469SVishal Kulkarni view_tp_la(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 1308*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 1309*7e6ad469SVishal Kulkarni { 1310*7e6ad469SVishal Kulkarni static int (*la_show) (void *v, int idx, 1311*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf); 1312*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 1313*7e6ad469SVishal Kulkarni struct struct_tp_la *tp_la_buff; 1314*7e6ad469SVishal Kulkarni int i, rc = 0; 1315*7e6ad469SVishal Kulkarni 1316*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 1317*7e6ad469SVishal Kulkarni if (rc) 1318*7e6ad469SVishal Kulkarni return rc; 1319*7e6ad469SVishal Kulkarni 1320*7e6ad469SVishal Kulkarni tp_la_buff = (struct struct_tp_la *) dc_buff.data; 1321*7e6ad469SVishal Kulkarni switch (tp_la_buff->mode) { 1322*7e6ad469SVishal Kulkarni case 2: 1323*7e6ad469SVishal Kulkarni la_show = tp_la_show2; 1324*7e6ad469SVishal Kulkarni break; 1325*7e6ad469SVishal Kulkarni case 3: 1326*7e6ad469SVishal Kulkarni la_show = tp_la_show3; 1327*7e6ad469SVishal Kulkarni break; 1328*7e6ad469SVishal Kulkarni default: 1329*7e6ad469SVishal Kulkarni la_show = tp_la_show; 1330*7e6ad469SVishal Kulkarni } 1331*7e6ad469SVishal Kulkarni 1332*7e6ad469SVishal Kulkarni for (i = 0; i < TPLA_SIZE/2; i++) { 1333*7e6ad469SVishal Kulkarni rc = la_show((u64 *)tp_la_buff->data + i*2, i, cudbg_poutbuf); 1334*7e6ad469SVishal Kulkarni if (rc < 0) 1335*7e6ad469SVishal Kulkarni goto err1; 1336*7e6ad469SVishal Kulkarni } 1337*7e6ad469SVishal Kulkarni 1338*7e6ad469SVishal Kulkarni err1: 1339*7e6ad469SVishal Kulkarni return rc; 1340*7e6ad469SVishal Kulkarni } 1341*7e6ad469SVishal Kulkarni 1342*7e6ad469SVishal Kulkarni static unsigned long 1343*7e6ad469SVishal Kulkarni do_div(unsigned long *number, u32 divisor) 1344*7e6ad469SVishal Kulkarni { 1345*7e6ad469SVishal Kulkarni unsigned long remainder = *number % divisor; 1346*7e6ad469SVishal Kulkarni 1347*7e6ad469SVishal Kulkarni (*number) /= divisor; 1348*7e6ad469SVishal Kulkarni return remainder; 1349*7e6ad469SVishal Kulkarni } 1350*7e6ad469SVishal Kulkarni 1351*7e6ad469SVishal Kulkarni static int 1352*7e6ad469SVishal Kulkarni string_get_size(unsigned long size, 1353*7e6ad469SVishal Kulkarni const enum string_size_units units, char *buf, 1354*7e6ad469SVishal Kulkarni int len) 1355*7e6ad469SVishal Kulkarni { 1356*7e6ad469SVishal Kulkarni const char *units_10[] = { 1357*7e6ad469SVishal Kulkarni "B", "kB", "MB", "GB", "TB", "PB", 1358*7e6ad469SVishal Kulkarni "EB", "ZB", "YB", NULL 1359*7e6ad469SVishal Kulkarni }; 1360*7e6ad469SVishal Kulkarni const char *units_2[] = { 1361*7e6ad469SVishal Kulkarni "B", "KiB", "MiB", "GiB", "TiB", "PiB", 1362*7e6ad469SVishal Kulkarni "EiB", "ZiB", "YiB", NULL 1363*7e6ad469SVishal Kulkarni }; 1364*7e6ad469SVishal Kulkarni const char **units_str[2];/* = {units_10, units_2};*/ 1365*7e6ad469SVishal Kulkarni const u32 divisor[] = {1000, 1024}; 1366*7e6ad469SVishal Kulkarni unsigned long remainder = 0; 1367*7e6ad469SVishal Kulkarni unsigned long sf_cap = 0; 1368*7e6ad469SVishal Kulkarni char tmp[8] = {0}; 1369*7e6ad469SVishal Kulkarni int i, j; 1370*7e6ad469SVishal Kulkarni 1371*7e6ad469SVishal Kulkarni tmp[0] = '\0'; 1372*7e6ad469SVishal Kulkarni i = 0; 1373*7e6ad469SVishal Kulkarni 1374*7e6ad469SVishal Kulkarni units_str[STRING_UNITS_10] = units_10; 1375*7e6ad469SVishal Kulkarni units_str[STRING_UNITS_2] = units_2; 1376*7e6ad469SVishal Kulkarni 1377*7e6ad469SVishal Kulkarni if (size >= divisor[units]) { 1378*7e6ad469SVishal Kulkarni while (size >= divisor[units] && units_str[units][i]) { 1379*7e6ad469SVishal Kulkarni remainder = do_div(&size, divisor[units]); 1380*7e6ad469SVishal Kulkarni i++; 1381*7e6ad469SVishal Kulkarni } 1382*7e6ad469SVishal Kulkarni 1383*7e6ad469SVishal Kulkarni sf_cap = size; 1384*7e6ad469SVishal Kulkarni 1385*7e6ad469SVishal Kulkarni for (j = 0; sf_cap*10 < 1000; j++) 1386*7e6ad469SVishal Kulkarni sf_cap *= 10; 1387*7e6ad469SVishal Kulkarni 1388*7e6ad469SVishal Kulkarni if (j) { 1389*7e6ad469SVishal Kulkarni remainder *= 1000; 1390*7e6ad469SVishal Kulkarni do_div(&remainder, divisor[units]); 1391*7e6ad469SVishal Kulkarni 1392*7e6ad469SVishal Kulkarni (void)snprintf(tmp, sizeof(tmp), ".%03lu", 1393*7e6ad469SVishal Kulkarni (unsigned long)remainder); 1394*7e6ad469SVishal Kulkarni tmp[j + 1] = '\0'; 1395*7e6ad469SVishal Kulkarni } 1396*7e6ad469SVishal Kulkarni } 1397*7e6ad469SVishal Kulkarni 1398*7e6ad469SVishal Kulkarni (void)snprintf(buf, len, "%lu%s %s", (unsigned long)size, tmp, 1399*7e6ad469SVishal Kulkarni units_str[units][i]); 1400*7e6ad469SVishal Kulkarni 1401*7e6ad469SVishal Kulkarni return 0; 1402*7e6ad469SVishal Kulkarni } 1403*7e6ad469SVishal Kulkarni 1404*7e6ad469SVishal Kulkarni static int 1405*7e6ad469SVishal Kulkarni mem_region_show(const char *name, u32 from, u32 to, 1406*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf) 1407*7e6ad469SVishal Kulkarni { 1408*7e6ad469SVishal Kulkarni char buf[40] = {0}; 1409*7e6ad469SVishal Kulkarni int rc = 0; 1410*7e6ad469SVishal Kulkarni 1411*7e6ad469SVishal Kulkarni string_get_size((u64)to - from + 1, STRING_UNITS_2, 1412*7e6ad469SVishal Kulkarni buf, sizeof(buf)); 1413*7e6ad469SVishal Kulkarni printf("%-14s %#x-%#x [%s]\n", name, from, 1414*7e6ad469SVishal Kulkarni to, buf); 1415*7e6ad469SVishal Kulkarni 1416*7e6ad469SVishal Kulkarni return rc; 1417*7e6ad469SVishal Kulkarni } /* mem_region_show */ 1418*7e6ad469SVishal Kulkarni 1419*7e6ad469SVishal Kulkarni int 1420*7e6ad469SVishal Kulkarni view_meminfo(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 1421*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 1422*7e6ad469SVishal Kulkarni { 1423*7e6ad469SVishal Kulkarni struct struct_meminfo *meminfo_buff; 1424*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 1425*7e6ad469SVishal Kulkarni u32 i, lo, idx; 1426*7e6ad469SVishal Kulkarni int rc = 0, rev; 1427*7e6ad469SVishal Kulkarni 1428*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 1429*7e6ad469SVishal Kulkarni if (rc) 1430*7e6ad469SVishal Kulkarni return rc; 1431*7e6ad469SVishal Kulkarni 1432*7e6ad469SVishal Kulkarni rev = get_entity_rev((struct cudbg_ver_hdr *)dc_buff.data); 1433*7e6ad469SVishal Kulkarni switch (rev) { 1434*7e6ad469SVishal Kulkarni case 0: 1435*7e6ad469SVishal Kulkarni meminfo_buff = (struct struct_meminfo *)dc_buff.data; 1436*7e6ad469SVishal Kulkarni break; 1437*7e6ad469SVishal Kulkarni case CUDBG_MEMINFO_REV: 1438*7e6ad469SVishal Kulkarni meminfo_buff = (struct struct_meminfo *) 1439*7e6ad469SVishal Kulkarni (dc_buff.data + 1440*7e6ad469SVishal Kulkarni sizeof(struct cudbg_ver_hdr)); 1441*7e6ad469SVishal Kulkarni break; 1442*7e6ad469SVishal Kulkarni default: 1443*7e6ad469SVishal Kulkarni printf("Unsupported revision %u. Only supports <= %u\n", 1444*7e6ad469SVishal Kulkarni rev, CUDBG_MEMINFO_REV); 1445*7e6ad469SVishal Kulkarni goto err1; 1446*7e6ad469SVishal Kulkarni } 1447*7e6ad469SVishal Kulkarni 1448*7e6ad469SVishal Kulkarni for (lo = 0; lo < meminfo_buff->avail_c; lo++) { 1449*7e6ad469SVishal Kulkarni idx = meminfo_buff->avail[lo].idx; 1450*7e6ad469SVishal Kulkarni rc = mem_region_show(memory[idx], meminfo_buff->avail[lo].base, 1451*7e6ad469SVishal Kulkarni meminfo_buff->avail[lo].limit - 1, 1452*7e6ad469SVishal Kulkarni cudbg_poutbuf); 1453*7e6ad469SVishal Kulkarni if (rc < 0) 1454*7e6ad469SVishal Kulkarni goto err1; 1455*7e6ad469SVishal Kulkarni } 1456*7e6ad469SVishal Kulkarni 1457*7e6ad469SVishal Kulkarni for (i = 0; i < meminfo_buff->mem_c; i++) { 1458*7e6ad469SVishal Kulkarni if (meminfo_buff->mem[i].idx >= ARRAY_SIZE(region)) 1459*7e6ad469SVishal Kulkarni continue; /* skip holes */ 1460*7e6ad469SVishal Kulkarni if (!(meminfo_buff->mem[i].limit)) 1461*7e6ad469SVishal Kulkarni meminfo_buff->mem[i].limit = 1462*7e6ad469SVishal Kulkarni i < meminfo_buff->mem_c - 1 ? 1463*7e6ad469SVishal Kulkarni meminfo_buff->mem[i + 1].base - 1 : ~0; 1464*7e6ad469SVishal Kulkarni 1465*7e6ad469SVishal Kulkarni idx = meminfo_buff->mem[i].idx; 1466*7e6ad469SVishal Kulkarni rc = mem_region_show(region[idx], meminfo_buff->mem[i].base, 1467*7e6ad469SVishal Kulkarni meminfo_buff->mem[i].limit, cudbg_poutbuf); 1468*7e6ad469SVishal Kulkarni if (rc < 0) 1469*7e6ad469SVishal Kulkarni goto err1; 1470*7e6ad469SVishal Kulkarni } 1471*7e6ad469SVishal Kulkarni 1472*7e6ad469SVishal Kulkarni rc = mem_region_show("uP RAM:", meminfo_buff->up_ram_lo, 1473*7e6ad469SVishal Kulkarni meminfo_buff->up_ram_hi, cudbg_poutbuf); 1474*7e6ad469SVishal Kulkarni if (rc < 0) 1475*7e6ad469SVishal Kulkarni goto err1; 1476*7e6ad469SVishal Kulkarni rc = mem_region_show("uP Extmem2:", meminfo_buff->up_extmem2_lo, 1477*7e6ad469SVishal Kulkarni meminfo_buff->up_extmem2_hi, cudbg_poutbuf); 1478*7e6ad469SVishal Kulkarni if (rc < 0) 1479*7e6ad469SVishal Kulkarni goto err1; 1480*7e6ad469SVishal Kulkarni 1481*7e6ad469SVishal Kulkarni if (rev == 0) { 1482*7e6ad469SVishal Kulkarni struct struct_meminfo_rev0 *meminfo_buff_rev0 = 1483*7e6ad469SVishal Kulkarni (struct struct_meminfo_rev0 *)meminfo_buff; 1484*7e6ad469SVishal Kulkarni 1485*7e6ad469SVishal Kulkarni printf("\n%u Rx pages of size %uKiB for %u channels\n", 1486*7e6ad469SVishal Kulkarni meminfo_buff_rev0->rx_pages_data[0], 1487*7e6ad469SVishal Kulkarni meminfo_buff_rev0->rx_pages_data[1], 1488*7e6ad469SVishal Kulkarni meminfo_buff_rev0->rx_pages_data[2]); 1489*7e6ad469SVishal Kulkarni printf("%u Tx pages of size %u%ciB for %u channels\n\n", 1490*7e6ad469SVishal Kulkarni meminfo_buff_rev0->tx_pages_data[0], 1491*7e6ad469SVishal Kulkarni meminfo_buff_rev0->tx_pages_data[1], 1492*7e6ad469SVishal Kulkarni meminfo_buff_rev0->tx_pages_data[2], 1493*7e6ad469SVishal Kulkarni meminfo_buff_rev0->tx_pages_data[3]); 1494*7e6ad469SVishal Kulkarni } else if (rev == CUDBG_MEMINFO_REV) { 1495*7e6ad469SVishal Kulkarni printf("\n%u Rx pages (%u free) of size %uKiB for %u channels\n", 1496*7e6ad469SVishal Kulkarni meminfo_buff->rx_pages_data[0], 1497*7e6ad469SVishal Kulkarni meminfo_buff->free_rx_cnt, 1498*7e6ad469SVishal Kulkarni meminfo_buff->rx_pages_data[1], 1499*7e6ad469SVishal Kulkarni meminfo_buff->rx_pages_data[2]); 1500*7e6ad469SVishal Kulkarni printf("%u Tx pages (%u free) of size %u%ciB for %u channels\n", 1501*7e6ad469SVishal Kulkarni meminfo_buff->tx_pages_data[0], 1502*7e6ad469SVishal Kulkarni meminfo_buff->free_tx_cnt, 1503*7e6ad469SVishal Kulkarni meminfo_buff->tx_pages_data[1], 1504*7e6ad469SVishal Kulkarni meminfo_buff->tx_pages_data[2], 1505*7e6ad469SVishal Kulkarni meminfo_buff->tx_pages_data[3]); 1506*7e6ad469SVishal Kulkarni printf("%u p-structs (%u free)\n\n", 1507*7e6ad469SVishal Kulkarni meminfo_buff->p_structs, 1508*7e6ad469SVishal Kulkarni meminfo_buff->pstructs_free_cnt); 1509*7e6ad469SVishal Kulkarni } 1510*7e6ad469SVishal Kulkarni 1511*7e6ad469SVishal Kulkarni for (i = 0; i < 4; i++) { 1512*7e6ad469SVishal Kulkarni printf("Port %d using %u pages out "\ 1513*7e6ad469SVishal Kulkarni "of %u allocated\n", 1514*7e6ad469SVishal Kulkarni i, meminfo_buff->port_used[i], 1515*7e6ad469SVishal Kulkarni meminfo_buff->port_alloc[i]); 1516*7e6ad469SVishal Kulkarni } 1517*7e6ad469SVishal Kulkarni 1518*7e6ad469SVishal Kulkarni for (i = 0; i < NCHAN; i++) { 1519*7e6ad469SVishal Kulkarni printf("Loopback %d using %u pages "\ 1520*7e6ad469SVishal Kulkarni "out of %u allocated\n", 1521*7e6ad469SVishal Kulkarni i, meminfo_buff->loopback_used[i], 1522*7e6ad469SVishal Kulkarni meminfo_buff->loopback_alloc[i]); 1523*7e6ad469SVishal Kulkarni } 1524*7e6ad469SVishal Kulkarni 1525*7e6ad469SVishal Kulkarni err1: 1526*7e6ad469SVishal Kulkarni return rc; 1527*7e6ad469SVishal Kulkarni } 1528*7e6ad469SVishal Kulkarni 1529*7e6ad469SVishal Kulkarni int 1530*7e6ad469SVishal Kulkarni view_lb_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 1531*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 1532*7e6ad469SVishal Kulkarni { 1533*7e6ad469SVishal Kulkarni struct struct_lb_stats *lb_stats_buff; 1534*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 1535*7e6ad469SVishal Kulkarni struct lb_port_stats *tmp_stats; 1536*7e6ad469SVishal Kulkarni int i, j, rc = 0; 1537*7e6ad469SVishal Kulkarni u64 *p0, *p1; 1538*7e6ad469SVishal Kulkarni 1539*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 1540*7e6ad469SVishal Kulkarni if (rc) 1541*7e6ad469SVishal Kulkarni return rc; 1542*7e6ad469SVishal Kulkarni 1543*7e6ad469SVishal Kulkarni lb_stats_buff = (struct struct_lb_stats *) dc_buff.data; 1544*7e6ad469SVishal Kulkarni tmp_stats = lb_stats_buff->s; 1545*7e6ad469SVishal Kulkarni for (i = 0; i < lb_stats_buff->nchan; i += 2, tmp_stats += 2) { 1546*7e6ad469SVishal Kulkarni p0 = &(tmp_stats[0].octets); 1547*7e6ad469SVishal Kulkarni p1 = &(tmp_stats[1].octets); 1548*7e6ad469SVishal Kulkarni printf("%s "\ 1549*7e6ad469SVishal Kulkarni "Loopback %u Loopback %u\n", 1550*7e6ad469SVishal Kulkarni i == 0 ? "" : "\n", i, i + 1); 1551*7e6ad469SVishal Kulkarni 1552*7e6ad469SVishal Kulkarni for (j = 0; j < ARRAY_SIZE(lb_stat_name); j++) 1553*7e6ad469SVishal Kulkarni printf("%-17s %20llu "\ 1554*7e6ad469SVishal Kulkarni "%20llu\n", lb_stat_name[j], 1555*7e6ad469SVishal Kulkarni (unsigned long long)*p0++, 1556*7e6ad469SVishal Kulkarni (unsigned long long)*p1++); 1557*7e6ad469SVishal Kulkarni } 1558*7e6ad469SVishal Kulkarni 1559*7e6ad469SVishal Kulkarni return rc; 1560*7e6ad469SVishal Kulkarni } 1561*7e6ad469SVishal Kulkarni 1562*7e6ad469SVishal Kulkarni int 1563*7e6ad469SVishal Kulkarni view_rdma_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 1564*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 1565*7e6ad469SVishal Kulkarni { 1566*7e6ad469SVishal Kulkarni struct tp_rdma_stats *rdma_stats_buff; 1567*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 1568*7e6ad469SVishal Kulkarni int rc = 0; 1569*7e6ad469SVishal Kulkarni 1570*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 1571*7e6ad469SVishal Kulkarni if (rc) 1572*7e6ad469SVishal Kulkarni return rc; 1573*7e6ad469SVishal Kulkarni 1574*7e6ad469SVishal Kulkarni rdma_stats_buff = (struct tp_rdma_stats *) dc_buff.data; 1575*7e6ad469SVishal Kulkarni printf("NoRQEModDefferals: %u\n", 1576*7e6ad469SVishal Kulkarni rdma_stats_buff->rqe_dfr_mod); 1577*7e6ad469SVishal Kulkarni printf("NoRQEPktDefferals: %u\n", 1578*7e6ad469SVishal Kulkarni rdma_stats_buff->rqe_dfr_pkt); 1579*7e6ad469SVishal Kulkarni 1580*7e6ad469SVishal Kulkarni return rc; 1581*7e6ad469SVishal Kulkarni } 1582*7e6ad469SVishal Kulkarni 1583*7e6ad469SVishal Kulkarni int 1584*7e6ad469SVishal Kulkarni view_clk_info(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 1585*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 1586*7e6ad469SVishal Kulkarni { 1587*7e6ad469SVishal Kulkarni struct struct_clk_info *clk_info_buff; 1588*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 1589*7e6ad469SVishal Kulkarni char tmp[32] = { 0 }; 1590*7e6ad469SVishal Kulkarni int rc = 0; 1591*7e6ad469SVishal Kulkarni 1592*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 1593*7e6ad469SVishal Kulkarni if (rc) 1594*7e6ad469SVishal Kulkarni return rc; 1595*7e6ad469SVishal Kulkarni 1596*7e6ad469SVishal Kulkarni clk_info_buff = (struct struct_clk_info *) dc_buff.data; 1597*7e6ad469SVishal Kulkarni 1598*7e6ad469SVishal Kulkarni unit_conv(tmp, 32, clk_info_buff->cclk_ps, 1000); 1599*7e6ad469SVishal Kulkarni printf("Core clock period: %s ns\n", tmp); 1600*7e6ad469SVishal Kulkarni 1601*7e6ad469SVishal Kulkarni unit_conv(tmp, 32, clk_info_buff->cclk_ps << clk_info_buff->tre, 1602*7e6ad469SVishal Kulkarni 1000000); 1603*7e6ad469SVishal Kulkarni printf("TP timer tick: %s us\n", tmp); 1604*7e6ad469SVishal Kulkarni 1605*7e6ad469SVishal Kulkarni unit_conv(tmp, 32, 1606*7e6ad469SVishal Kulkarni clk_info_buff->cclk_ps << G_TIMESTAMPRESOLUTION(clk_info_buff->res), 1607*7e6ad469SVishal Kulkarni 1000000); 1608*7e6ad469SVishal Kulkarni printf("TCP timestamp tick: %s us\n", tmp); 1609*7e6ad469SVishal Kulkarni 1610*7e6ad469SVishal Kulkarni unit_conv(tmp, 32, clk_info_buff->cclk_ps << clk_info_buff->dack_re, 1611*7e6ad469SVishal Kulkarni 1000000); 1612*7e6ad469SVishal Kulkarni printf("DACK tick: %s us\n", tmp); 1613*7e6ad469SVishal Kulkarni 1614*7e6ad469SVishal Kulkarni printf("DACK timer: %u us\n", 1615*7e6ad469SVishal Kulkarni clk_info_buff->dack_timer); 1616*7e6ad469SVishal Kulkarni printf("Retransmit min: %llu us\n", 1617*7e6ad469SVishal Kulkarni clk_info_buff->retransmit_min); 1618*7e6ad469SVishal Kulkarni printf("Retransmit max: %llu us\n", 1619*7e6ad469SVishal Kulkarni clk_info_buff->retransmit_max); 1620*7e6ad469SVishal Kulkarni printf("Persist timer min: %llu us\n", 1621*7e6ad469SVishal Kulkarni clk_info_buff->persist_timer_min); 1622*7e6ad469SVishal Kulkarni printf("Persist timer max: %llu us\n", 1623*7e6ad469SVishal Kulkarni clk_info_buff->persist_timer_max); 1624*7e6ad469SVishal Kulkarni printf("Keepalive idle timer: %llu us\n", 1625*7e6ad469SVishal Kulkarni clk_info_buff->keepalive_idle_timer); 1626*7e6ad469SVishal Kulkarni printf("Keepalive interval: %llu us\n", 1627*7e6ad469SVishal Kulkarni clk_info_buff->keepalive_interval); 1628*7e6ad469SVishal Kulkarni printf("Initial SRTT: %llu us\n", 1629*7e6ad469SVishal Kulkarni clk_info_buff->initial_srtt); 1630*7e6ad469SVishal Kulkarni printf("FINWAIT2 timer: %llu us\n", 1631*7e6ad469SVishal Kulkarni clk_info_buff->finwait2_timer); 1632*7e6ad469SVishal Kulkarni 1633*7e6ad469SVishal Kulkarni return rc; 1634*7e6ad469SVishal Kulkarni } 1635*7e6ad469SVishal Kulkarni 1636*7e6ad469SVishal Kulkarni int 1637*7e6ad469SVishal Kulkarni view_cim_pif_la(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 1638*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 1639*7e6ad469SVishal Kulkarni { 1640*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 1641*7e6ad469SVishal Kulkarni struct cim_pif_la *cim_pif_la_buff; 1642*7e6ad469SVishal Kulkarni int i, rc = 0; 1643*7e6ad469SVishal Kulkarni u32 *p; 1644*7e6ad469SVishal Kulkarni 1645*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 1646*7e6ad469SVishal Kulkarni if (rc) 1647*7e6ad469SVishal Kulkarni return rc; 1648*7e6ad469SVishal Kulkarni 1649*7e6ad469SVishal Kulkarni cim_pif_la_buff = (struct cim_pif_la *) dc_buff.data; 1650*7e6ad469SVishal Kulkarni p = (u32 *)cim_pif_la_buff->data; 1651*7e6ad469SVishal Kulkarni 1652*7e6ad469SVishal Kulkarni printf("Cntl ID DataBE Addr "\ 1653*7e6ad469SVishal Kulkarni " Data\n"); 1654*7e6ad469SVishal Kulkarni for (i = 0; i < cim_pif_la_buff->size; i++, p = p + 6) 1655*7e6ad469SVishal Kulkarni printf(" %02x %02x %04x %08x "\ 1656*7e6ad469SVishal Kulkarni "%08x%08x%08x%08x\n", 1657*7e6ad469SVishal Kulkarni (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, 1658*7e6ad469SVishal Kulkarni p[5] & 0xffff, p[4], p[3], p[2], p[1], p[0]); 1659*7e6ad469SVishal Kulkarni 1660*7e6ad469SVishal Kulkarni p = (u32 *) cim_pif_la_buff->data + 6 * CIM_PIFLA_SIZE; 1661*7e6ad469SVishal Kulkarni 1662*7e6ad469SVishal Kulkarni printf("\nCntl ID Data\n"); 1663*7e6ad469SVishal Kulkarni for (i = 0; i < cim_pif_la_buff->size; i++, p = p + 6) 1664*7e6ad469SVishal Kulkarni printf(" %02x %02x "\ 1665*7e6ad469SVishal Kulkarni "%08x%08x%08x%08x\n", 1666*7e6ad469SVishal Kulkarni (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], 1667*7e6ad469SVishal Kulkarni p[0]); 1668*7e6ad469SVishal Kulkarni 1669*7e6ad469SVishal Kulkarni return rc; 1670*7e6ad469SVishal Kulkarni } 1671*7e6ad469SVishal Kulkarni 1672*7e6ad469SVishal Kulkarni int 1673*7e6ad469SVishal Kulkarni view_fcoe_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 1674*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 1675*7e6ad469SVishal Kulkarni { 1676*7e6ad469SVishal Kulkarni struct struct_tp_fcoe_stats *tp_fcoe_stats_buff; 1677*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 1678*7e6ad469SVishal Kulkarni struct tp_fcoe_stats stats[4]; 1679*7e6ad469SVishal Kulkarni int rc = 0; 1680*7e6ad469SVishal Kulkarni 1681*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 1682*7e6ad469SVishal Kulkarni if (rc) 1683*7e6ad469SVishal Kulkarni return rc; 1684*7e6ad469SVishal Kulkarni 1685*7e6ad469SVishal Kulkarni tp_fcoe_stats_buff = (struct struct_tp_fcoe_stats *) dc_buff.data; 1686*7e6ad469SVishal Kulkarni memcpy(stats, tp_fcoe_stats_buff->stats, sizeof(stats)); 1687*7e6ad469SVishal Kulkarni 1688*7e6ad469SVishal Kulkarni if (tp_fcoe_stats_buff->nchan == NCHAN) { 1689*7e6ad469SVishal Kulkarni printf(" channel "\ 1690*7e6ad469SVishal Kulkarni "0 channel 1 channel 2 "\ 1691*7e6ad469SVishal Kulkarni "channel 3\n"); 1692*7e6ad469SVishal Kulkarni printf("octetsDDP: %16llu %16llu "\ 1693*7e6ad469SVishal Kulkarni "%16llu %16llu\n", 1694*7e6ad469SVishal Kulkarni stats[0].octets_ddp, stats[1].octets_ddp, 1695*7e6ad469SVishal Kulkarni stats[2].octets_ddp, stats[3].octets_ddp); 1696*7e6ad469SVishal Kulkarni printf("framesDDP: %16u %16u %16u "\ 1697*7e6ad469SVishal Kulkarni "%16u\n", 1698*7e6ad469SVishal Kulkarni stats[0].frames_ddp, stats[1].frames_ddp, 1699*7e6ad469SVishal Kulkarni stats[2].frames_ddp, stats[3].frames_ddp); 1700*7e6ad469SVishal Kulkarni printf("framesDrop: %16u %16u %16u "\ 1701*7e6ad469SVishal Kulkarni "%16u\n", 1702*7e6ad469SVishal Kulkarni stats[0].frames_drop, stats[1].frames_drop, 1703*7e6ad469SVishal Kulkarni stats[2].frames_drop, stats[3].frames_drop); 1704*7e6ad469SVishal Kulkarni } else { 1705*7e6ad469SVishal Kulkarni printf(" channel "\ 1706*7e6ad469SVishal Kulkarni "0 channel 1\n"); 1707*7e6ad469SVishal Kulkarni printf("octetsDDP: %16llu "\ 1708*7e6ad469SVishal Kulkarni "%16llu\n", 1709*7e6ad469SVishal Kulkarni stats[0].octets_ddp, stats[1].octets_ddp); 1710*7e6ad469SVishal Kulkarni printf("framesDDP: %16u %16u\n", 1711*7e6ad469SVishal Kulkarni stats[0].frames_ddp, stats[1].frames_ddp); 1712*7e6ad469SVishal Kulkarni printf("framesDrop: %16u %16u\n", 1713*7e6ad469SVishal Kulkarni stats[0].frames_drop, stats[1].frames_drop); 1714*7e6ad469SVishal Kulkarni } 1715*7e6ad469SVishal Kulkarni 1716*7e6ad469SVishal Kulkarni return rc; 1717*7e6ad469SVishal Kulkarni } 1718*7e6ad469SVishal Kulkarni 1719*7e6ad469SVishal Kulkarni int 1720*7e6ad469SVishal Kulkarni view_tp_err_stats_show(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 1721*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, 1722*7e6ad469SVishal Kulkarni enum chip_type chip) 1723*7e6ad469SVishal Kulkarni { 1724*7e6ad469SVishal Kulkarni struct struct_tp_err_stats *tp_err_stats_buff; 1725*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 1726*7e6ad469SVishal Kulkarni struct tp_err_stats stats; 1727*7e6ad469SVishal Kulkarni int rc = 0; 1728*7e6ad469SVishal Kulkarni 1729*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 1730*7e6ad469SVishal Kulkarni if (rc) 1731*7e6ad469SVishal Kulkarni return rc; 1732*7e6ad469SVishal Kulkarni 1733*7e6ad469SVishal Kulkarni tp_err_stats_buff = (struct struct_tp_err_stats *) dc_buff.data; 1734*7e6ad469SVishal Kulkarni stats = tp_err_stats_buff->stats; 1735*7e6ad469SVishal Kulkarni if (tp_err_stats_buff->nchan == NCHAN) { 1736*7e6ad469SVishal Kulkarni printf(" channel 0"\ 1737*7e6ad469SVishal Kulkarni " channel 1 channel 2 channel 3\n"); 1738*7e6ad469SVishal Kulkarni printf("macInErrs: %10u %10u "\ 1739*7e6ad469SVishal Kulkarni "%10u %10u\n", 1740*7e6ad469SVishal Kulkarni stats.mac_in_errs[0], stats.mac_in_errs[1], 1741*7e6ad469SVishal Kulkarni stats.mac_in_errs[2], stats.mac_in_errs[3]); 1742*7e6ad469SVishal Kulkarni printf("hdrInErrs: %10u %10u "\ 1743*7e6ad469SVishal Kulkarni "%10u %10u\n", 1744*7e6ad469SVishal Kulkarni stats.hdr_in_errs[0], stats.hdr_in_errs[1], 1745*7e6ad469SVishal Kulkarni stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 1746*7e6ad469SVishal Kulkarni printf("tcpInErrs: %10u %10u "\ 1747*7e6ad469SVishal Kulkarni "%10u %10u\n", 1748*7e6ad469SVishal Kulkarni stats.tcp_in_errs[0], stats.tcp_in_errs[1], 1749*7e6ad469SVishal Kulkarni stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 1750*7e6ad469SVishal Kulkarni printf("tcp6InErrs: %10u %10u "\ 1751*7e6ad469SVishal Kulkarni "%10u %10u\n", 1752*7e6ad469SVishal Kulkarni stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 1753*7e6ad469SVishal Kulkarni stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 1754*7e6ad469SVishal Kulkarni printf("tnlCongDrops: %10u %10u "\ 1755*7e6ad469SVishal Kulkarni "%10u %10u\n", 1756*7e6ad469SVishal Kulkarni stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 1757*7e6ad469SVishal Kulkarni stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 1758*7e6ad469SVishal Kulkarni printf("tnlTxDrops: %10u %10u "\ 1759*7e6ad469SVishal Kulkarni "%10u %10u\n", 1760*7e6ad469SVishal Kulkarni stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 1761*7e6ad469SVishal Kulkarni stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 1762*7e6ad469SVishal Kulkarni printf("ofldVlanDrops: %10u %10u "\ 1763*7e6ad469SVishal Kulkarni "%10u %10u\n", 1764*7e6ad469SVishal Kulkarni stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 1765*7e6ad469SVishal Kulkarni stats.ofld_vlan_drops[2], 1766*7e6ad469SVishal Kulkarni stats.ofld_vlan_drops[3]); 1767*7e6ad469SVishal Kulkarni printf("ofldChanDrops: %10u %10u "\ 1768*7e6ad469SVishal Kulkarni "%10u %10u\n\n", 1769*7e6ad469SVishal Kulkarni stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 1770*7e6ad469SVishal Kulkarni stats.ofld_chan_drops[2], 1771*7e6ad469SVishal Kulkarni stats.ofld_chan_drops[3]); 1772*7e6ad469SVishal Kulkarni } else { 1773*7e6ad469SVishal Kulkarni printf(" channel 0"\ 1774*7e6ad469SVishal Kulkarni " channel 1\n"); 1775*7e6ad469SVishal Kulkarni printf("macInErrs: %10u %10u\n", 1776*7e6ad469SVishal Kulkarni stats.mac_in_errs[0], stats.mac_in_errs[1]); 1777*7e6ad469SVishal Kulkarni printf("hdrInErrs: %10u %10u\n", 1778*7e6ad469SVishal Kulkarni stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 1779*7e6ad469SVishal Kulkarni printf("tcpInErrs: %10u %10u\n", 1780*7e6ad469SVishal Kulkarni stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 1781*7e6ad469SVishal Kulkarni printf("tcp6InErrs: %10u %10u\n", 1782*7e6ad469SVishal Kulkarni stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 1783*7e6ad469SVishal Kulkarni printf("tnlCongDrops: %10u %10u\n", 1784*7e6ad469SVishal Kulkarni stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 1785*7e6ad469SVishal Kulkarni printf("tnlTxDrops: %10u %10u\n", 1786*7e6ad469SVishal Kulkarni stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 1787*7e6ad469SVishal Kulkarni printf("ofldVlanDrops: %10u %10u\n", 1788*7e6ad469SVishal Kulkarni stats.ofld_vlan_drops[0], 1789*7e6ad469SVishal Kulkarni stats.ofld_vlan_drops[1]); 1790*7e6ad469SVishal Kulkarni printf("ofldChanDrops: %10u %10u"\ 1791*7e6ad469SVishal Kulkarni "\n\n", stats.ofld_chan_drops[0], 1792*7e6ad469SVishal Kulkarni stats.ofld_chan_drops[1]); 1793*7e6ad469SVishal Kulkarni } 1794*7e6ad469SVishal Kulkarni 1795*7e6ad469SVishal Kulkarni printf("ofldNoNeigh: %u\nofldCongDefer: "\ 1796*7e6ad469SVishal Kulkarni " %u\n", stats.ofld_no_neigh, stats.ofld_cong_defer); 1797*7e6ad469SVishal Kulkarni 1798*7e6ad469SVishal Kulkarni return rc; 1799*7e6ad469SVishal Kulkarni } 1800*7e6ad469SVishal Kulkarni 1801*7e6ad469SVishal Kulkarni int 1802*7e6ad469SVishal Kulkarni view_tcp_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 1803*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 1804*7e6ad469SVishal Kulkarni { 1805*7e6ad469SVishal Kulkarni struct struct_tcp_stats *tcp_stats_buff; 1806*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 1807*7e6ad469SVishal Kulkarni int rc = 0; 1808*7e6ad469SVishal Kulkarni 1809*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 1810*7e6ad469SVishal Kulkarni if (rc) 1811*7e6ad469SVishal Kulkarni return rc; 1812*7e6ad469SVishal Kulkarni 1813*7e6ad469SVishal Kulkarni tcp_stats_buff = (struct struct_tcp_stats *) dc_buff.data; 1814*7e6ad469SVishal Kulkarni printf(" IP"\ 1815*7e6ad469SVishal Kulkarni " IPv6\n"); 1816*7e6ad469SVishal Kulkarni printf("OutRsts: %20u %20u\n", 1817*7e6ad469SVishal Kulkarni tcp_stats_buff->v4.tcp_out_rsts, 1818*7e6ad469SVishal Kulkarni tcp_stats_buff->v6.tcp_out_rsts); 1819*7e6ad469SVishal Kulkarni printf("InSegs: %20llu %20llu\n", 1820*7e6ad469SVishal Kulkarni (unsigned long long)(tcp_stats_buff->v4.tcp_in_segs), 1821*7e6ad469SVishal Kulkarni (unsigned long long)(tcp_stats_buff->v6.tcp_in_segs)); 1822*7e6ad469SVishal Kulkarni printf("OutSegs: %20llu %20llu\n", 1823*7e6ad469SVishal Kulkarni (unsigned long long)(tcp_stats_buff->v4.tcp_out_segs), 1824*7e6ad469SVishal Kulkarni (unsigned long long)(tcp_stats_buff->v6.tcp_out_segs)); 1825*7e6ad469SVishal Kulkarni printf("RetransSegs: %20llu %20llu\n", 1826*7e6ad469SVishal Kulkarni (unsigned long long)(tcp_stats_buff->v4.tcp_retrans_segs), 1827*7e6ad469SVishal Kulkarni (unsigned long long)(tcp_stats_buff->v6.tcp_retrans_segs)); 1828*7e6ad469SVishal Kulkarni 1829*7e6ad469SVishal Kulkarni return rc; 1830*7e6ad469SVishal Kulkarni } 1831*7e6ad469SVishal Kulkarni 1832*7e6ad469SVishal Kulkarni int 1833*7e6ad469SVishal Kulkarni view_hw_sched(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 1834*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 1835*7e6ad469SVishal Kulkarni { 1836*7e6ad469SVishal Kulkarni struct struct_hw_sched *hw_sched_buff; 1837*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 1838*7e6ad469SVishal Kulkarni int i, rc = 0; 1839*7e6ad469SVishal Kulkarni 1840*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 1841*7e6ad469SVishal Kulkarni if (rc) 1842*7e6ad469SVishal Kulkarni return rc; 1843*7e6ad469SVishal Kulkarni 1844*7e6ad469SVishal Kulkarni hw_sched_buff = (struct struct_hw_sched *)dc_buff.data; 1845*7e6ad469SVishal Kulkarni 1846*7e6ad469SVishal Kulkarni printf("Scheduler Mode Channel Rate "\ 1847*7e6ad469SVishal Kulkarni "(Kbps) Class IPG (0.1 ns) Flow IPG (us)\n"); 1848*7e6ad469SVishal Kulkarni for (i = 0; i < NTX_SCHED; ++i, hw_sched_buff->map >>= 2) { 1849*7e6ad469SVishal Kulkarni printf(" %u %-5s %u"\ 1850*7e6ad469SVishal Kulkarni " ", i, 1851*7e6ad469SVishal Kulkarni (hw_sched_buff->mode & (1 << i)) ? 1852*7e6ad469SVishal Kulkarni "flow" : "class", 1853*7e6ad469SVishal Kulkarni hw_sched_buff->map & 3); 1854*7e6ad469SVishal Kulkarni if (hw_sched_buff->kbps[i]) { 1855*7e6ad469SVishal Kulkarni printf("%9u ", 1856*7e6ad469SVishal Kulkarni hw_sched_buff->kbps[i]); 1857*7e6ad469SVishal Kulkarni } else { 1858*7e6ad469SVishal Kulkarni printf(" disabled "); 1859*7e6ad469SVishal Kulkarni } 1860*7e6ad469SVishal Kulkarni 1861*7e6ad469SVishal Kulkarni if (hw_sched_buff->ipg[i]) { 1862*7e6ad469SVishal Kulkarni printf("%13u ", 1863*7e6ad469SVishal Kulkarni hw_sched_buff->ipg[i]); 1864*7e6ad469SVishal Kulkarni } else { 1865*7e6ad469SVishal Kulkarni printf(" disabled "\ 1866*7e6ad469SVishal Kulkarni " "); 1867*7e6ad469SVishal Kulkarni } 1868*7e6ad469SVishal Kulkarni 1869*7e6ad469SVishal Kulkarni if (hw_sched_buff->pace_tab[i]) { 1870*7e6ad469SVishal Kulkarni printf("%10u\n", 1871*7e6ad469SVishal Kulkarni hw_sched_buff->pace_tab[i]); 1872*7e6ad469SVishal Kulkarni } else { 1873*7e6ad469SVishal Kulkarni printf(" disabled\n"); 1874*7e6ad469SVishal Kulkarni } 1875*7e6ad469SVishal Kulkarni } 1876*7e6ad469SVishal Kulkarni 1877*7e6ad469SVishal Kulkarni return rc; 1878*7e6ad469SVishal Kulkarni } 1879*7e6ad469SVishal Kulkarni 1880*7e6ad469SVishal Kulkarni int 1881*7e6ad469SVishal Kulkarni view_pm_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 1882*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 1883*7e6ad469SVishal Kulkarni { 1884*7e6ad469SVishal Kulkarni static const char * const tx_pm_stats[] = { 1885*7e6ad469SVishal Kulkarni "Read:", "Write bypass:", "Write mem:", "Bypass + mem:" 1886*7e6ad469SVishal Kulkarni }; 1887*7e6ad469SVishal Kulkarni static const char * const rx_pm_stats[] = { 1888*7e6ad469SVishal Kulkarni "Read:", "Write bypass:", "Write mem:", "Flush:" 1889*7e6ad469SVishal Kulkarni }; 1890*7e6ad469SVishal Kulkarni struct struct_pm_stats *pm_stats_buff; 1891*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 1892*7e6ad469SVishal Kulkarni int i, rc = 0; 1893*7e6ad469SVishal Kulkarni 1894*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 1895*7e6ad469SVishal Kulkarni if (rc) 1896*7e6ad469SVishal Kulkarni return rc; 1897*7e6ad469SVishal Kulkarni 1898*7e6ad469SVishal Kulkarni pm_stats_buff = (struct struct_pm_stats *)dc_buff.data; 1899*7e6ad469SVishal Kulkarni 1900*7e6ad469SVishal Kulkarni printf("%13s %10s %20s\n", " ", "Tx pcmds", 1901*7e6ad469SVishal Kulkarni "Tx bytes"); 1902*7e6ad469SVishal Kulkarni for (i = 0; i < PM_NSTATS - 1; i++) 1903*7e6ad469SVishal Kulkarni printf("%-13s %10u %20llu\n", 1904*7e6ad469SVishal Kulkarni tx_pm_stats[i], pm_stats_buff->tx_cnt[i], 1905*7e6ad469SVishal Kulkarni pm_stats_buff->tx_cyc[i]); 1906*7e6ad469SVishal Kulkarni 1907*7e6ad469SVishal Kulkarni printf("%13s %10s %20s\n", " ", "Rx pcmds", 1908*7e6ad469SVishal Kulkarni "Rx bytes"); 1909*7e6ad469SVishal Kulkarni for (i = 0; i < PM_NSTATS - 1; i++) 1910*7e6ad469SVishal Kulkarni printf("%-13s %10u %20llu\n", 1911*7e6ad469SVishal Kulkarni rx_pm_stats[i], pm_stats_buff->rx_cnt[i], 1912*7e6ad469SVishal Kulkarni pm_stats_buff->rx_cyc[i]); 1913*7e6ad469SVishal Kulkarni 1914*7e6ad469SVishal Kulkarni if (CHELSIO_CHIP_VERSION(chip) > CHELSIO_T5) { 1915*7e6ad469SVishal Kulkarni /* In T5 the granularity of the total wait is too fine. 1916*7e6ad469SVishal Kulkarni * It is not useful as it reaches the max value too fast. 1917*7e6ad469SVishal Kulkarni * Hence display this Input FIFO wait for T6 onwards. 1918*7e6ad469SVishal Kulkarni */ 1919*7e6ad469SVishal Kulkarni printf("%13s %10s %20s\n", 1920*7e6ad469SVishal Kulkarni " ", "Total wait", "Total Occupancy"); 1921*7e6ad469SVishal Kulkarni printf("Tx FIFO wait " 1922*7e6ad469SVishal Kulkarni "%10u %20llu\n", pm_stats_buff->tx_cnt[i], 1923*7e6ad469SVishal Kulkarni pm_stats_buff->tx_cyc[i]); 1924*7e6ad469SVishal Kulkarni printf("Rx FIFO wait %10u " 1925*7e6ad469SVishal Kulkarni "%20llu\n", pm_stats_buff->rx_cnt[i], 1926*7e6ad469SVishal Kulkarni pm_stats_buff->rx_cyc[i]); 1927*7e6ad469SVishal Kulkarni 1928*7e6ad469SVishal Kulkarni /* Skip index 6 as there is nothing useful here */ 1929*7e6ad469SVishal Kulkarni i += 2; 1930*7e6ad469SVishal Kulkarni 1931*7e6ad469SVishal Kulkarni /* At index 7, a new stat for read latency (count, total wait) 1932*7e6ad469SVishal Kulkarni * is added. 1933*7e6ad469SVishal Kulkarni */ 1934*7e6ad469SVishal Kulkarni printf("%13s %10s %20s\n", 1935*7e6ad469SVishal Kulkarni " ", "Reads", "Total wait"); 1936*7e6ad469SVishal Kulkarni printf("Tx latency " 1937*7e6ad469SVishal Kulkarni "%10u %20llu\n", pm_stats_buff->tx_cnt[i], 1938*7e6ad469SVishal Kulkarni pm_stats_buff->tx_cyc[i]); 1939*7e6ad469SVishal Kulkarni printf("Rx latency " 1940*7e6ad469SVishal Kulkarni "%10u %20llu\n", pm_stats_buff->rx_cnt[i], 1941*7e6ad469SVishal Kulkarni pm_stats_buff->rx_cyc[i]); 1942*7e6ad469SVishal Kulkarni } 1943*7e6ad469SVishal Kulkarni 1944*7e6ad469SVishal Kulkarni return rc; 1945*7e6ad469SVishal Kulkarni } 1946*7e6ad469SVishal Kulkarni 1947*7e6ad469SVishal Kulkarni int 1948*7e6ad469SVishal Kulkarni view_path_mtu(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 1949*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 1950*7e6ad469SVishal Kulkarni { 1951*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 1952*7e6ad469SVishal Kulkarni int rc = 0; 1953*7e6ad469SVishal Kulkarni u16 *mtus; 1954*7e6ad469SVishal Kulkarni 1955*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 1956*7e6ad469SVishal Kulkarni if (rc) 1957*7e6ad469SVishal Kulkarni return rc; 1958*7e6ad469SVishal Kulkarni 1959*7e6ad469SVishal Kulkarni mtus = (u16 *)dc_buff.data; 1960*7e6ad469SVishal Kulkarni printf("%u %u %u %u %u %u %u %u %u %u %u %u"\ 1961*7e6ad469SVishal Kulkarni " %u %u %u %u\n", 1962*7e6ad469SVishal Kulkarni mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], 1963*7e6ad469SVishal Kulkarni mtus[6], mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], 1964*7e6ad469SVishal Kulkarni mtus[12], mtus[13], mtus[14], mtus[15]); 1965*7e6ad469SVishal Kulkarni 1966*7e6ad469SVishal Kulkarni return rc; 1967*7e6ad469SVishal Kulkarni } 1968*7e6ad469SVishal Kulkarni 1969*7e6ad469SVishal Kulkarni int 1970*7e6ad469SVishal Kulkarni view_rss_config(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 1971*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 1972*7e6ad469SVishal Kulkarni { 1973*7e6ad469SVishal Kulkarni static const char * const keymode[] = { 1974*7e6ad469SVishal Kulkarni "global", 1975*7e6ad469SVishal Kulkarni "global and per-VF scramble", 1976*7e6ad469SVishal Kulkarni "per-PF and per-VF scramble", 1977*7e6ad469SVishal Kulkarni "per-VF and per-VF scramble", 1978*7e6ad469SVishal Kulkarni }; 1979*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 1980*7e6ad469SVishal Kulkarni struct rss_config *struct_rss_conf; 1981*7e6ad469SVishal Kulkarni u32 rssconf; 1982*7e6ad469SVishal Kulkarni int rc = 0; 1983*7e6ad469SVishal Kulkarni 1984*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 1985*7e6ad469SVishal Kulkarni if (rc) 1986*7e6ad469SVishal Kulkarni return rc; 1987*7e6ad469SVishal Kulkarni 1988*7e6ad469SVishal Kulkarni struct_rss_conf = (struct rss_config *)dc_buff.data; 1989*7e6ad469SVishal Kulkarni rssconf = struct_rss_conf->tp_rssconf; 1990*7e6ad469SVishal Kulkarni printf("TP_RSS_CONFIG: %#x\n", rssconf); 1991*7e6ad469SVishal Kulkarni printf(" Tnl4TupEnIpv6: %3s\n", 1992*7e6ad469SVishal Kulkarni yesno(rssconf & F_TNL4TUPENIPV6)); 1993*7e6ad469SVishal Kulkarni printf(" Tnl2TupEnIpv6: %3s\n", 1994*7e6ad469SVishal Kulkarni yesno(rssconf & F_TNL2TUPENIPV6)); 1995*7e6ad469SVishal Kulkarni printf(" Tnl4TupEnIpv4: %3s\n", 1996*7e6ad469SVishal Kulkarni yesno(rssconf & F_TNL4TUPENIPV4)); 1997*7e6ad469SVishal Kulkarni printf(" Tnl2TupEnIpv4: %3s\n", 1998*7e6ad469SVishal Kulkarni yesno(rssconf & F_TNL2TUPENIPV4)); 1999*7e6ad469SVishal Kulkarni printf(" TnlTcpSel: %3s\n", 2000*7e6ad469SVishal Kulkarni yesno(rssconf & F_TNLTCPSEL)); 2001*7e6ad469SVishal Kulkarni printf(" TnlIp6Sel: %3s\n", 2002*7e6ad469SVishal Kulkarni yesno(rssconf & F_TNLIP6SEL)); 2003*7e6ad469SVishal Kulkarni printf(" TnlVrtSel: %3s\n", 2004*7e6ad469SVishal Kulkarni yesno(rssconf & F_TNLVRTSEL)); 2005*7e6ad469SVishal Kulkarni printf(" TnlMapEn: %3s\n", 2006*7e6ad469SVishal Kulkarni yesno(rssconf & F_TNLMAPEN)); 2007*7e6ad469SVishal Kulkarni printf(" OfdHashSave: %3s\n", 2008*7e6ad469SVishal Kulkarni yesno(rssconf & F_OFDHASHSAVE)); 2009*7e6ad469SVishal Kulkarni printf(" OfdVrtSel: %3s\n", 2010*7e6ad469SVishal Kulkarni yesno(rssconf & F_OFDVRTSEL)); 2011*7e6ad469SVishal Kulkarni printf(" OfdMapEn: %3s\n", 2012*7e6ad469SVishal Kulkarni yesno(rssconf & F_OFDMAPEN)); 2013*7e6ad469SVishal Kulkarni printf(" OfdLkpEn: %3s\n", 2014*7e6ad469SVishal Kulkarni yesno(rssconf & F_OFDLKPEN)); 2015*7e6ad469SVishal Kulkarni printf(" Syn4TupEnIpv6: %3s\n", 2016*7e6ad469SVishal Kulkarni yesno(rssconf & F_SYN4TUPENIPV6)); 2017*7e6ad469SVishal Kulkarni printf(" Syn2TupEnIpv6: %3s\n", 2018*7e6ad469SVishal Kulkarni yesno(rssconf & F_SYN2TUPENIPV6)); 2019*7e6ad469SVishal Kulkarni printf(" Syn4TupEnIpv4: %3s\n", 2020*7e6ad469SVishal Kulkarni yesno(rssconf & F_SYN4TUPENIPV4)); 2021*7e6ad469SVishal Kulkarni printf(" Syn2TupEnIpv4: %3s\n", 2022*7e6ad469SVishal Kulkarni yesno(rssconf & F_SYN2TUPENIPV4)); 2023*7e6ad469SVishal Kulkarni printf(" Syn4TupEnIpv6: %3s\n", 2024*7e6ad469SVishal Kulkarni yesno(rssconf & F_SYN4TUPENIPV6)); 2025*7e6ad469SVishal Kulkarni printf(" SynIp6Sel: %3s\n", 2026*7e6ad469SVishal Kulkarni yesno(rssconf & F_SYNIP6SEL)); 2027*7e6ad469SVishal Kulkarni printf(" SynVrt6Sel: %3s\n", 2028*7e6ad469SVishal Kulkarni yesno(rssconf & F_SYNVRTSEL)); 2029*7e6ad469SVishal Kulkarni printf(" SynMapEn: %3s\n", 2030*7e6ad469SVishal Kulkarni yesno(rssconf & F_SYNMAPEN)); 2031*7e6ad469SVishal Kulkarni printf(" SynLkpEn: %3s\n", 2032*7e6ad469SVishal Kulkarni yesno(rssconf & F_SYNLKPEN)); 2033*7e6ad469SVishal Kulkarni printf(" ChnEn: %3s\n", 2034*7e6ad469SVishal Kulkarni yesno(rssconf & F_CHANNELENABLE)); 2035*7e6ad469SVishal Kulkarni printf(" PrtEn: %3s\n", 2036*7e6ad469SVishal Kulkarni yesno(rssconf & F_PORTENABLE)); 2037*7e6ad469SVishal Kulkarni printf(" TnlAllLkp: %3s\n", 2038*7e6ad469SVishal Kulkarni yesno(rssconf & F_TNLALLLOOKUP)); 2039*7e6ad469SVishal Kulkarni printf(" VrtEn: %3s\n", 2040*7e6ad469SVishal Kulkarni yesno(rssconf & F_VIRTENABLE)); 2041*7e6ad469SVishal Kulkarni printf(" CngEn: %3s\n", 2042*7e6ad469SVishal Kulkarni yesno(rssconf & F_CONGESTIONENABLE)); 2043*7e6ad469SVishal Kulkarni printf(" HashToeplitz: %3s\n", 2044*7e6ad469SVishal Kulkarni yesno(rssconf & F_HASHTOEPLITZ)); 2045*7e6ad469SVishal Kulkarni printf(" Udp4En: %3s\n", 2046*7e6ad469SVishal Kulkarni yesno(rssconf & F_UDPENABLE)); 2047*7e6ad469SVishal Kulkarni printf(" Disable: %3s\n", 2048*7e6ad469SVishal Kulkarni yesno(rssconf & F_DISABLE)); 2049*7e6ad469SVishal Kulkarni 2050*7e6ad469SVishal Kulkarni rssconf = struct_rss_conf->tp_rssconf_tnl; 2051*7e6ad469SVishal Kulkarni printf("TP_RSS_CONFIG_TNL: %#x\n", 2052*7e6ad469SVishal Kulkarni rssconf); 2053*7e6ad469SVishal Kulkarni printf(" MaskSize: %3d\n", 2054*7e6ad469SVishal Kulkarni G_MASKSIZE(rssconf)); 2055*7e6ad469SVishal Kulkarni printf(" MaskFilter: %3d\n", 2056*7e6ad469SVishal Kulkarni G_MASKFILTER(rssconf)); 2057*7e6ad469SVishal Kulkarni if (CHELSIO_CHIP_VERSION(struct_rss_conf->chip) > CHELSIO_T5) { 2058*7e6ad469SVishal Kulkarni printf(" HashAll: %3s\n", 2059*7e6ad469SVishal Kulkarni yesno(rssconf & F_HASHALL)); 2060*7e6ad469SVishal Kulkarni printf(" HashEth: %3s\n", 2061*7e6ad469SVishal Kulkarni yesno(rssconf & F_HASHETH)); 2062*7e6ad469SVishal Kulkarni } 2063*7e6ad469SVishal Kulkarni printf(" UseWireCh: %3s\n", 2064*7e6ad469SVishal Kulkarni yesno(rssconf & F_USEWIRECH)); 2065*7e6ad469SVishal Kulkarni 2066*7e6ad469SVishal Kulkarni rssconf = struct_rss_conf->tp_rssconf_ofd; 2067*7e6ad469SVishal Kulkarni printf("TP_RSS_CONFIG_OFD: %#x\n", 2068*7e6ad469SVishal Kulkarni rssconf); 2069*7e6ad469SVishal Kulkarni printf(" MaskSize: %3d\n", 2070*7e6ad469SVishal Kulkarni G_MASKSIZE(rssconf)); 2071*7e6ad469SVishal Kulkarni printf(" RRCplMapEn: %3s\n", 2072*7e6ad469SVishal Kulkarni yesno(rssconf & F_RRCPLMAPEN)); 2073*7e6ad469SVishal Kulkarni printf(" RRCplQueWidth: %3d\n", 2074*7e6ad469SVishal Kulkarni G_RRCPLQUEWIDTH(rssconf)); 2075*7e6ad469SVishal Kulkarni 2076*7e6ad469SVishal Kulkarni rssconf = struct_rss_conf->tp_rssconf_syn; 2077*7e6ad469SVishal Kulkarni printf("TP_RSS_CONFIG_SYN: %#x\n", 2078*7e6ad469SVishal Kulkarni rssconf); 2079*7e6ad469SVishal Kulkarni printf(" MaskSize: %3d\n", 2080*7e6ad469SVishal Kulkarni G_MASKSIZE(rssconf)); 2081*7e6ad469SVishal Kulkarni printf(" UseWireCh: %3s\n", 2082*7e6ad469SVishal Kulkarni yesno(rssconf & F_USEWIRECH)); 2083*7e6ad469SVishal Kulkarni 2084*7e6ad469SVishal Kulkarni rssconf = struct_rss_conf->tp_rssconf_vrt; 2085*7e6ad469SVishal Kulkarni printf("TP_RSS_CONFIG_VRT: %#x\n", 2086*7e6ad469SVishal Kulkarni rssconf); 2087*7e6ad469SVishal Kulkarni if (CHELSIO_CHIP_VERSION(struct_rss_conf->chip) > CHELSIO_T5) { 2088*7e6ad469SVishal Kulkarni printf(" KeyWrAddrX: %3d\n", 2089*7e6ad469SVishal Kulkarni G_KEYWRADDRX(rssconf)); 2090*7e6ad469SVishal Kulkarni printf(" KeyExtend: %3s\n", 2091*7e6ad469SVishal Kulkarni yesno(rssconf & F_KEYEXTEND)); 2092*7e6ad469SVishal Kulkarni } 2093*7e6ad469SVishal Kulkarni printf(" VfRdRg: %3s\n", 2094*7e6ad469SVishal Kulkarni yesno(rssconf & F_VFRDRG)); 2095*7e6ad469SVishal Kulkarni printf(" VfRdEn: %3s\n", 2096*7e6ad469SVishal Kulkarni yesno(rssconf & F_VFRDEN)); 2097*7e6ad469SVishal Kulkarni printf(" VfPerrEn: %3s\n", 2098*7e6ad469SVishal Kulkarni yesno(rssconf & F_VFPERREN)); 2099*7e6ad469SVishal Kulkarni printf(" KeyPerrEn: %3s\n", 2100*7e6ad469SVishal Kulkarni yesno(rssconf & F_KEYPERREN)); 2101*7e6ad469SVishal Kulkarni printf(" DisVfVlan: %3s\n", 2102*7e6ad469SVishal Kulkarni yesno(rssconf & F_DISABLEVLAN)); 2103*7e6ad469SVishal Kulkarni printf(" EnUpSwt: %3s\n", 2104*7e6ad469SVishal Kulkarni yesno(rssconf & F_ENABLEUP0)); 2105*7e6ad469SVishal Kulkarni printf(" HashDelay: %3d\n", 2106*7e6ad469SVishal Kulkarni G_HASHDELAY(rssconf)); 2107*7e6ad469SVishal Kulkarni if (CHELSIO_CHIP_VERSION(struct_rss_conf->chip) <= CHELSIO_T5) { 2108*7e6ad469SVishal Kulkarni printf(" VfWrAddr: %3d\n", 2109*7e6ad469SVishal Kulkarni G_VFWRADDR(rssconf)); 2110*7e6ad469SVishal Kulkarni } else { 2111*7e6ad469SVishal Kulkarni printf(" VfWrAddr: %3d\n", 2112*7e6ad469SVishal Kulkarni G_T6_VFWRADDR(rssconf)); 2113*7e6ad469SVishal Kulkarni } 2114*7e6ad469SVishal Kulkarni printf(" KeyMode: %s\n", 2115*7e6ad469SVishal Kulkarni keymode[G_KEYMODE(rssconf)]); 2116*7e6ad469SVishal Kulkarni printf(" VfWrEn: %3s\n", 2117*7e6ad469SVishal Kulkarni yesno(rssconf & F_VFWREN)); 2118*7e6ad469SVishal Kulkarni printf(" KeyWrEn: %3s\n", 2119*7e6ad469SVishal Kulkarni yesno(rssconf & F_KEYWREN)); 2120*7e6ad469SVishal Kulkarni printf(" KeyWrAddr: %3d\n", 2121*7e6ad469SVishal Kulkarni G_KEYWRADDR(rssconf)); 2122*7e6ad469SVishal Kulkarni 2123*7e6ad469SVishal Kulkarni rssconf = struct_rss_conf->tp_rssconf_cng; 2124*7e6ad469SVishal Kulkarni printf("TP_RSS_CONFIG_CNG: %#x\n", 2125*7e6ad469SVishal Kulkarni rssconf); 2126*7e6ad469SVishal Kulkarni printf(" ChnCount3: %3s\n", 2127*7e6ad469SVishal Kulkarni yesno(rssconf & F_CHNCOUNT3)); 2128*7e6ad469SVishal Kulkarni printf(" ChnCount2: %3s\n", 2129*7e6ad469SVishal Kulkarni yesno(rssconf & F_CHNCOUNT2)); 2130*7e6ad469SVishal Kulkarni printf(" ChnCount1: %3s\n", 2131*7e6ad469SVishal Kulkarni yesno(rssconf & F_CHNCOUNT1)); 2132*7e6ad469SVishal Kulkarni printf(" ChnCount0: %3s\n", 2133*7e6ad469SVishal Kulkarni yesno(rssconf & F_CHNCOUNT0)); 2134*7e6ad469SVishal Kulkarni printf(" ChnUndFlow3: %3s\n", 2135*7e6ad469SVishal Kulkarni yesno(rssconf & F_CHNUNDFLOW3)); 2136*7e6ad469SVishal Kulkarni printf(" ChnUndFlow2: %3s\n", 2137*7e6ad469SVishal Kulkarni yesno(rssconf & F_CHNUNDFLOW2)); 2138*7e6ad469SVishal Kulkarni printf(" ChnUndFlow1: %3s\n", 2139*7e6ad469SVishal Kulkarni yesno(rssconf & F_CHNUNDFLOW1)); 2140*7e6ad469SVishal Kulkarni printf(" ChnUndFlow0: %3s\n", 2141*7e6ad469SVishal Kulkarni yesno(rssconf & F_CHNUNDFLOW0)); 2142*7e6ad469SVishal Kulkarni printf(" RstChn3: %3s\n", 2143*7e6ad469SVishal Kulkarni yesno(rssconf & F_RSTCHN3)); 2144*7e6ad469SVishal Kulkarni printf(" RstChn2: %3s\n", 2145*7e6ad469SVishal Kulkarni yesno(rssconf & F_RSTCHN2)); 2146*7e6ad469SVishal Kulkarni printf(" RstChn1: %3s\n", 2147*7e6ad469SVishal Kulkarni yesno(rssconf & F_RSTCHN1)); 2148*7e6ad469SVishal Kulkarni printf(" RstChn0: %3s\n", 2149*7e6ad469SVishal Kulkarni yesno(rssconf & F_RSTCHN0)); 2150*7e6ad469SVishal Kulkarni printf(" UpdVld: %3s\n", 2151*7e6ad469SVishal Kulkarni yesno(rssconf & F_UPDVLD)); 2152*7e6ad469SVishal Kulkarni printf(" Xoff: %3s\n", 2153*7e6ad469SVishal Kulkarni yesno(rssconf & F_XOFF)); 2154*7e6ad469SVishal Kulkarni printf(" UpdChn3: %3s\n", 2155*7e6ad469SVishal Kulkarni yesno(rssconf & F_UPDCHN3)); 2156*7e6ad469SVishal Kulkarni printf(" UpdChn2: %3s\n", 2157*7e6ad469SVishal Kulkarni yesno(rssconf & F_UPDCHN2)); 2158*7e6ad469SVishal Kulkarni printf(" UpdChn1: %3s\n", 2159*7e6ad469SVishal Kulkarni yesno(rssconf & F_UPDCHN1)); 2160*7e6ad469SVishal Kulkarni printf(" UpdChn0: %3s\n", 2161*7e6ad469SVishal Kulkarni yesno(rssconf & F_UPDCHN0)); 2162*7e6ad469SVishal Kulkarni printf(" Queue: %3d\n", 2163*7e6ad469SVishal Kulkarni G_QUEUE(rssconf)); 2164*7e6ad469SVishal Kulkarni 2165*7e6ad469SVishal Kulkarni return rc; 2166*7e6ad469SVishal Kulkarni } 2167*7e6ad469SVishal Kulkarni 2168*7e6ad469SVishal Kulkarni int 2169*7e6ad469SVishal Kulkarni view_rss_key(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 2170*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 2171*7e6ad469SVishal Kulkarni { 2172*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 2173*7e6ad469SVishal Kulkarni int rc = 0; 2174*7e6ad469SVishal Kulkarni u32 *key; 2175*7e6ad469SVishal Kulkarni 2176*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 2177*7e6ad469SVishal Kulkarni if (rc) 2178*7e6ad469SVishal Kulkarni return rc; 2179*7e6ad469SVishal Kulkarni 2180*7e6ad469SVishal Kulkarni key = (u32 *)dc_buff.data; 2181*7e6ad469SVishal Kulkarni printf( 2182*7e6ad469SVishal Kulkarni "%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x\n", 2183*7e6ad469SVishal Kulkarni key[9], key[8], key[7], key[6], key[5], key[4], 2184*7e6ad469SVishal Kulkarni key[3], key[2], key[1], key[0]); 2185*7e6ad469SVishal Kulkarni 2186*7e6ad469SVishal Kulkarni return rc; 2187*7e6ad469SVishal Kulkarni } 2188*7e6ad469SVishal Kulkarni 2189*7e6ad469SVishal Kulkarni int 2190*7e6ad469SVishal Kulkarni view_rss_vf_config(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 2191*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 2192*7e6ad469SVishal Kulkarni { 2193*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 2194*7e6ad469SVishal Kulkarni struct rss_vf_conf *vfconf; 2195*7e6ad469SVishal Kulkarni int i, rc = 0; 2196*7e6ad469SVishal Kulkarni 2197*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 2198*7e6ad469SVishal Kulkarni if (rc) 2199*7e6ad469SVishal Kulkarni return rc; 2200*7e6ad469SVishal Kulkarni 2201*7e6ad469SVishal Kulkarni vfconf = (struct rss_vf_conf *) dc_buff.data; 2202*7e6ad469SVishal Kulkarni printf(" RSS Hash "\ 2203*7e6ad469SVishal Kulkarni "Tuple Enable\n"); 2204*7e6ad469SVishal Kulkarni printf(" Enable IVF Dis Enb IPv6 "\ 2205*7e6ad469SVishal Kulkarni " IPv4 UDP Def Secret Key\n"); 2206*7e6ad469SVishal Kulkarni printf(" VF Chn Prt Map VLAN uP Four "\ 2207*7e6ad469SVishal Kulkarni "Two Four Two Four Que Idx Hash\n"); 2208*7e6ad469SVishal Kulkarni for (i = 0; i < dc_buff.offset/sizeof(*vfconf); i += 1) { 2209*7e6ad469SVishal Kulkarni printf("%3d %3s %3s %3d %3s %3s"\ 2210*7e6ad469SVishal Kulkarni " %3s %3s %3s %3s %3s %4d %3d %#10x\n", 2211*7e6ad469SVishal Kulkarni i, yesno(vfconf->rss_vf_vfh & F_VFCHNEN), 2212*7e6ad469SVishal Kulkarni yesno(vfconf->rss_vf_vfh & F_VFPRTEN), 2213*7e6ad469SVishal Kulkarni G_VFLKPIDX(vfconf->rss_vf_vfh), 2214*7e6ad469SVishal Kulkarni yesno(vfconf->rss_vf_vfh & F_VFVLNEX), 2215*7e6ad469SVishal Kulkarni yesno(vfconf->rss_vf_vfh & F_VFUPEN), 2216*7e6ad469SVishal Kulkarni yesno(vfconf->rss_vf_vfh & F_VFIP4FOURTUPEN), 2217*7e6ad469SVishal Kulkarni yesno(vfconf->rss_vf_vfh & F_VFIP6TWOTUPEN), 2218*7e6ad469SVishal Kulkarni yesno(vfconf->rss_vf_vfh & F_VFIP4FOURTUPEN), 2219*7e6ad469SVishal Kulkarni yesno(vfconf->rss_vf_vfh & F_VFIP4TWOTUPEN), 2220*7e6ad469SVishal Kulkarni yesno(vfconf->rss_vf_vfh & F_ENABLEUDPHASH), 2221*7e6ad469SVishal Kulkarni G_DEFAULTQUEUE(vfconf->rss_vf_vfh), 2222*7e6ad469SVishal Kulkarni G_KEYINDEX(vfconf->rss_vf_vfh), 2223*7e6ad469SVishal Kulkarni vfconf->rss_vf_vfl); 2224*7e6ad469SVishal Kulkarni 2225*7e6ad469SVishal Kulkarni vfconf++; 2226*7e6ad469SVishal Kulkarni } 2227*7e6ad469SVishal Kulkarni 2228*7e6ad469SVishal Kulkarni return rc; 2229*7e6ad469SVishal Kulkarni } 2230*7e6ad469SVishal Kulkarni 2231*7e6ad469SVishal Kulkarni int 2232*7e6ad469SVishal Kulkarni view_rss_pf_config(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 2233*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 2234*7e6ad469SVishal Kulkarni { 2235*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 2236*7e6ad469SVishal Kulkarni struct rss_pf_conf *pfconf; 2237*7e6ad469SVishal Kulkarni int i, rc = 0; 2238*7e6ad469SVishal Kulkarni 2239*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 2240*7e6ad469SVishal Kulkarni if (rc) 2241*7e6ad469SVishal Kulkarni return rc; 2242*7e6ad469SVishal Kulkarni 2243*7e6ad469SVishal Kulkarni pfconf = (struct rss_pf_conf *) dc_buff.data; 2244*7e6ad469SVishal Kulkarni printf("PF Map Index Size = %d\n\n", 2245*7e6ad469SVishal Kulkarni G_LKPIDXSIZE(pfconf->rss_pf_map)); 2246*7e6ad469SVishal Kulkarni printf(" RSS PF VF "\ 2247*7e6ad469SVishal Kulkarni "Hash Tuple Enable Default\n"); 2248*7e6ad469SVishal Kulkarni printf(" Enable IPF Mask Mask "\ 2249*7e6ad469SVishal Kulkarni "IPv6 IPv4 UDP Queue\n"); 2250*7e6ad469SVishal Kulkarni printf(" PF Map Chn Prt Map Size Size "\ 2251*7e6ad469SVishal Kulkarni "Four Two Four Two Four Ch1 Ch0\n"); 2252*7e6ad469SVishal Kulkarni 2253*7e6ad469SVishal Kulkarni #define G_PFnLKPIDX(map, n) \ 2254*7e6ad469SVishal Kulkarni (((map) >> S_PF1LKPIDX*(n)) & M_PF0LKPIDX) 2255*7e6ad469SVishal Kulkarni #define G_PFnMSKSIZE(mask, n) \ 2256*7e6ad469SVishal Kulkarni (((mask) >> S_PF1MSKSIZE*(n)) & M_PF1MSKSIZE) 2257*7e6ad469SVishal Kulkarni 2258*7e6ad469SVishal Kulkarni for (i = 0; i < dc_buff.offset/sizeof(*pfconf); i += 1) { 2259*7e6ad469SVishal Kulkarni printf("%3d %3s %3s %3s %3d %3d"\ 2260*7e6ad469SVishal Kulkarni " %3d %3s %3s %3s %3s %3s %3d %3d\n", 2261*7e6ad469SVishal Kulkarni i, yesno(pfconf->rss_pf_config & F_MAPENABLE), 2262*7e6ad469SVishal Kulkarni yesno(pfconf->rss_pf_config & F_CHNENABLE), 2263*7e6ad469SVishal Kulkarni yesno(pfconf->rss_pf_config & F_PRTENABLE), 2264*7e6ad469SVishal Kulkarni G_PFnLKPIDX(pfconf->rss_pf_map, i), 2265*7e6ad469SVishal Kulkarni G_PFnMSKSIZE(pfconf->rss_pf_mask, i), 2266*7e6ad469SVishal Kulkarni G_IVFWIDTH(pfconf->rss_pf_config), 2267*7e6ad469SVishal Kulkarni yesno(pfconf->rss_pf_config & F_IP6FOURTUPEN), 2268*7e6ad469SVishal Kulkarni yesno(pfconf->rss_pf_config & F_IP6TWOTUPEN), 2269*7e6ad469SVishal Kulkarni yesno(pfconf->rss_pf_config & F_IP4FOURTUPEN), 2270*7e6ad469SVishal Kulkarni yesno(pfconf->rss_pf_config & F_IP4TWOTUPEN), 2271*7e6ad469SVishal Kulkarni yesno(pfconf->rss_pf_config & F_UDPFOURTUPEN), 2272*7e6ad469SVishal Kulkarni G_CH1DEFAULTQUEUE(pfconf->rss_pf_config), 2273*7e6ad469SVishal Kulkarni G_CH0DEFAULTQUEUE(pfconf->rss_pf_config)); 2274*7e6ad469SVishal Kulkarni 2275*7e6ad469SVishal Kulkarni pfconf++; 2276*7e6ad469SVishal Kulkarni } 2277*7e6ad469SVishal Kulkarni #undef G_PFnLKPIDX 2278*7e6ad469SVishal Kulkarni #undef G_PFnMSKSIZE 2279*7e6ad469SVishal Kulkarni 2280*7e6ad469SVishal Kulkarni return rc; 2281*7e6ad469SVishal Kulkarni } 2282*7e6ad469SVishal Kulkarni 2283*7e6ad469SVishal Kulkarni int 2284*7e6ad469SVishal Kulkarni view_rss(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 2285*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 2286*7e6ad469SVishal Kulkarni { 2287*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 2288*7e6ad469SVishal Kulkarni u16 *pdata = NULL; 2289*7e6ad469SVishal Kulkarni int rc = 0; 2290*7e6ad469SVishal Kulkarni u32 i; 2291*7e6ad469SVishal Kulkarni 2292*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 2293*7e6ad469SVishal Kulkarni if (rc) 2294*7e6ad469SVishal Kulkarni return rc; 2295*7e6ad469SVishal Kulkarni 2296*7e6ad469SVishal Kulkarni pdata = (u16 *) dc_buff.data; 2297*7e6ad469SVishal Kulkarni for (i = 0; i < dc_buff.offset / 2; i += 8) { 2298*7e6ad469SVishal Kulkarni printf("%4d: %4u %4u %4u %4u "\ 2299*7e6ad469SVishal Kulkarni "%4u %4u %4u %4u\n", 2300*7e6ad469SVishal Kulkarni i, pdata[i + 0], pdata[i + 1], pdata[i + 2], 2301*7e6ad469SVishal Kulkarni pdata[i + 3], pdata[i + 4], pdata[i + 5], 2302*7e6ad469SVishal Kulkarni pdata[i + 6], pdata[i + 7]); 2303*7e6ad469SVishal Kulkarni } 2304*7e6ad469SVishal Kulkarni 2305*7e6ad469SVishal Kulkarni return rc; 2306*7e6ad469SVishal Kulkarni } 2307*7e6ad469SVishal Kulkarni 2308*7e6ad469SVishal Kulkarni int 2309*7e6ad469SVishal Kulkarni view_fw_devlog(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 2310*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 2311*7e6ad469SVishal Kulkarni { 2312*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 2313*7e6ad469SVishal Kulkarni struct fw_devlog_e *e, *devlog; 2314*7e6ad469SVishal Kulkarni unsigned long index; 2315*7e6ad469SVishal Kulkarni u32 num_entries = 0; 2316*7e6ad469SVishal Kulkarni u32 first_entry = 0; 2317*7e6ad469SVishal Kulkarni int rc = 0; 2318*7e6ad469SVishal Kulkarni u32 itr; 2319*7e6ad469SVishal Kulkarni 2320*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 2321*7e6ad469SVishal Kulkarni if (rc) 2322*7e6ad469SVishal Kulkarni return rc; 2323*7e6ad469SVishal Kulkarni 2324*7e6ad469SVishal Kulkarni translate_fw_devlog(dc_buff.data, dc_buff.offset, 2325*7e6ad469SVishal Kulkarni &num_entries, &first_entry); 2326*7e6ad469SVishal Kulkarni 2327*7e6ad469SVishal Kulkarni devlog = (struct fw_devlog_e *)(dc_buff.data); 2328*7e6ad469SVishal Kulkarni printf("%10s %15s %8s %8s %s\n", 2329*7e6ad469SVishal Kulkarni "Seq#", "Tstamp", "Level", "Facility", "Message"); 2330*7e6ad469SVishal Kulkarni 2331*7e6ad469SVishal Kulkarni index = first_entry; 2332*7e6ad469SVishal Kulkarni for (itr = 0; itr < num_entries; itr++) { 2333*7e6ad469SVishal Kulkarni if (index >= num_entries) 2334*7e6ad469SVishal Kulkarni index = 0; 2335*7e6ad469SVishal Kulkarni 2336*7e6ad469SVishal Kulkarni e = &devlog[index++]; 2337*7e6ad469SVishal Kulkarni if (e->timestamp == 0) 2338*7e6ad469SVishal Kulkarni break; 2339*7e6ad469SVishal Kulkarni printf("%10d %15llu %8s %8s ", 2340*7e6ad469SVishal Kulkarni e->seqno, e->timestamp, 2341*7e6ad469SVishal Kulkarni (e->level < ARRAY_SIZE(devlog_level_strings) 2342*7e6ad469SVishal Kulkarni ? devlog_level_strings[e->level] : "UNKNOWN"), 2343*7e6ad469SVishal Kulkarni (e->facility < ARRAY_SIZE(devlog_facility_strings) 2344*7e6ad469SVishal Kulkarni ? devlog_facility_strings[e->facility] 2345*7e6ad469SVishal Kulkarni : "UNKNOWN")); 2346*7e6ad469SVishal Kulkarni printf((const char *)e->fmt, 2347*7e6ad469SVishal Kulkarni e->params[0], e->params[1], e->params[2], 2348*7e6ad469SVishal Kulkarni e->params[3], e->params[4], e->params[5], 2349*7e6ad469SVishal Kulkarni e->params[6], e->params[7]); 2350*7e6ad469SVishal Kulkarni } 2351*7e6ad469SVishal Kulkarni 2352*7e6ad469SVishal Kulkarni return rc; 2353*7e6ad469SVishal Kulkarni } 2354*7e6ad469SVishal Kulkarni 2355*7e6ad469SVishal Kulkarni void 2356*7e6ad469SVishal Kulkarni translate_fw_devlog(void *pbuf, u32 io_size, 2357*7e6ad469SVishal Kulkarni u32 *num_entries, u32 *first_entry) 2358*7e6ad469SVishal Kulkarni { 2359*7e6ad469SVishal Kulkarni struct fw_devlog_e *e = NULL; 2360*7e6ad469SVishal Kulkarni u64 ftstamp; 2361*7e6ad469SVishal Kulkarni u32 index; 2362*7e6ad469SVishal Kulkarni 2363*7e6ad469SVishal Kulkarni *num_entries = (io_size / sizeof(struct fw_devlog_e)); 2364*7e6ad469SVishal Kulkarni *first_entry = 0; 2365*7e6ad469SVishal Kulkarni e = (struct fw_devlog_e *)pbuf; 2366*7e6ad469SVishal Kulkarni for (ftstamp = ~0ULL, index = 0; index < *num_entries; index++) { 2367*7e6ad469SVishal Kulkarni int i; 2368*7e6ad469SVishal Kulkarni 2369*7e6ad469SVishal Kulkarni if (e->timestamp == 0) 2370*7e6ad469SVishal Kulkarni continue; 2371*7e6ad469SVishal Kulkarni 2372*7e6ad469SVishal Kulkarni e->timestamp = ntohll(e->timestamp); 2373*7e6ad469SVishal Kulkarni e->seqno = ntohl(e->seqno); 2374*7e6ad469SVishal Kulkarni for (i = 0; i < 8; i++) 2375*7e6ad469SVishal Kulkarni e->params[i] = ntohl(e->params[i]); 2376*7e6ad469SVishal Kulkarni 2377*7e6ad469SVishal Kulkarni if (e->timestamp < ftstamp) { 2378*7e6ad469SVishal Kulkarni ftstamp = e->timestamp; 2379*7e6ad469SVishal Kulkarni *first_entry = index; 2380*7e6ad469SVishal Kulkarni } 2381*7e6ad469SVishal Kulkarni 2382*7e6ad469SVishal Kulkarni e++; 2383*7e6ad469SVishal Kulkarni } 2384*7e6ad469SVishal Kulkarni } 2385*7e6ad469SVishal Kulkarni 2386*7e6ad469SVishal Kulkarni /* Regdump function */ 2387*7e6ad469SVishal Kulkarni static uint32_t 2388*7e6ad469SVishal Kulkarni xtract(uint32_t val, int shift, int len) 2389*7e6ad469SVishal Kulkarni { 2390*7e6ad469SVishal Kulkarni return (val >> shift) & ((1L << len) - 1); 2391*7e6ad469SVishal Kulkarni } 2392*7e6ad469SVishal Kulkarni 2393*7e6ad469SVishal Kulkarni static int 2394*7e6ad469SVishal Kulkarni dump_block_regs(const struct reg_info *reg_array, const u32 *regs, 2395*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf) 2396*7e6ad469SVishal Kulkarni { 2397*7e6ad469SVishal Kulkarni uint32_t reg_val = 0; /* silence compiler warning*/ 2398*7e6ad469SVishal Kulkarni int rc = 0; 2399*7e6ad469SVishal Kulkarni 2400*7e6ad469SVishal Kulkarni for (; reg_array->name; ++reg_array) { 2401*7e6ad469SVishal Kulkarni if (!reg_array->len) { 2402*7e6ad469SVishal Kulkarni reg_val = regs[reg_array->addr / 4]; 2403*7e6ad469SVishal Kulkarni printf("[%#7x] %-47s %#-10x"\ 2404*7e6ad469SVishal Kulkarni " %u\n", reg_array->addr, reg_array->name, 2405*7e6ad469SVishal Kulkarni reg_val, reg_val); 2406*7e6ad469SVishal Kulkarni } else { 2407*7e6ad469SVishal Kulkarni uint32_t v = xtract(reg_val, reg_array->addr, 2408*7e6ad469SVishal Kulkarni reg_array->len); 2409*7e6ad469SVishal Kulkarni 2410*7e6ad469SVishal Kulkarni printf(" %*u:%u %-47s "\ 2411*7e6ad469SVishal Kulkarni "%#-10x %u\n", 2412*7e6ad469SVishal Kulkarni reg_array->addr < 10 ? 3 : 2, 2413*7e6ad469SVishal Kulkarni reg_array->addr + reg_array->len - 1, 2414*7e6ad469SVishal Kulkarni reg_array->addr, reg_array->name, v, v); 2415*7e6ad469SVishal Kulkarni } 2416*7e6ad469SVishal Kulkarni } 2417*7e6ad469SVishal Kulkarni 2418*7e6ad469SVishal Kulkarni return 1; 2419*7e6ad469SVishal Kulkarni 2420*7e6ad469SVishal Kulkarni return rc; 2421*7e6ad469SVishal Kulkarni } 2422*7e6ad469SVishal Kulkarni 2423*7e6ad469SVishal Kulkarni static int 2424*7e6ad469SVishal Kulkarni dump_regs_table(const u32 *regs, const struct mod_regs *modtab, 2425*7e6ad469SVishal Kulkarni int nmodules, const char *modnames, 2426*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf) 2427*7e6ad469SVishal Kulkarni { 2428*7e6ad469SVishal Kulkarni int match = 0; 2429*7e6ad469SVishal Kulkarni int rc = 0; 2430*7e6ad469SVishal Kulkarni 2431*7e6ad469SVishal Kulkarni for (; nmodules; nmodules--, modtab++) { 2432*7e6ad469SVishal Kulkarni rc = dump_block_regs(modtab->ri, 2433*7e6ad469SVishal Kulkarni regs + modtab->offset, cudbg_poutbuf); 2434*7e6ad469SVishal Kulkarni if (rc < 0) 2435*7e6ad469SVishal Kulkarni goto err1; 2436*7e6ad469SVishal Kulkarni match += rc; 2437*7e6ad469SVishal Kulkarni } 2438*7e6ad469SVishal Kulkarni 2439*7e6ad469SVishal Kulkarni err1: 2440*7e6ad469SVishal Kulkarni return rc; 2441*7e6ad469SVishal Kulkarni } 2442*7e6ad469SVishal Kulkarni 2443*7e6ad469SVishal Kulkarni #define T6_MODREGS(name) { #name, t6_##name##_regs } 2444*7e6ad469SVishal Kulkarni static int 2445*7e6ad469SVishal Kulkarni dump_regs_t6(const u32 *regs, struct cudbg_buffer *cudbg_poutbuf) 2446*7e6ad469SVishal Kulkarni { 2447*7e6ad469SVishal Kulkarni static struct mod_regs t6_mod[] = { 2448*7e6ad469SVishal Kulkarni T6_MODREGS(sge), 2449*7e6ad469SVishal Kulkarni { "pci", t6_pcie_regs }, 2450*7e6ad469SVishal Kulkarni T6_MODREGS(dbg), 2451*7e6ad469SVishal Kulkarni { "mc0", t6_mc_0_regs }, 2452*7e6ad469SVishal Kulkarni T6_MODREGS(ma), 2453*7e6ad469SVishal Kulkarni { "edc0", t6_edc_t60_regs }, 2454*7e6ad469SVishal Kulkarni { "edc1", t6_edc_t61_regs }, 2455*7e6ad469SVishal Kulkarni T6_MODREGS(cim), 2456*7e6ad469SVishal Kulkarni T6_MODREGS(tp), 2457*7e6ad469SVishal Kulkarni { "ulprx", t6_ulp_rx_regs }, 2458*7e6ad469SVishal Kulkarni { "ulptx", t6_ulp_tx_regs }, 2459*7e6ad469SVishal Kulkarni { "pmrx", t6_pm_rx_regs }, 2460*7e6ad469SVishal Kulkarni { "pmtx", t6_pm_tx_regs }, 2461*7e6ad469SVishal Kulkarni T6_MODREGS(mps), 2462*7e6ad469SVishal Kulkarni { "cplsw", t6_cpl_switch_regs }, 2463*7e6ad469SVishal Kulkarni T6_MODREGS(smb), 2464*7e6ad469SVishal Kulkarni { "i2c", t6_i2cm_regs }, 2465*7e6ad469SVishal Kulkarni T6_MODREGS(mi), 2466*7e6ad469SVishal Kulkarni T6_MODREGS(uart), 2467*7e6ad469SVishal Kulkarni T6_MODREGS(pmu), 2468*7e6ad469SVishal Kulkarni T6_MODREGS(sf), 2469*7e6ad469SVishal Kulkarni T6_MODREGS(pl), 2470*7e6ad469SVishal Kulkarni T6_MODREGS(le), 2471*7e6ad469SVishal Kulkarni T6_MODREGS(ncsi), 2472*7e6ad469SVishal Kulkarni T6_MODREGS(mac), 2473*7e6ad469SVishal Kulkarni { "hma", t6_hma_t6_regs } 2474*7e6ad469SVishal Kulkarni }; 2475*7e6ad469SVishal Kulkarni 2476*7e6ad469SVishal Kulkarni return dump_regs_table(regs, t6_mod, 2477*7e6ad469SVishal Kulkarni ARRAY_SIZE(t6_mod), 2478*7e6ad469SVishal Kulkarni "sge, pci, dbg, mc0, ma, edc0, edc1, cim, "\ 2479*7e6ad469SVishal Kulkarni "tp, ulprx, ulptx, pmrx, pmtx, mps, cplsw, smb, "\ 2480*7e6ad469SVishal Kulkarni "i2c, mi, uart, pmu, sf, pl, le, ncsi, "\ 2481*7e6ad469SVishal Kulkarni "mac, hma", cudbg_poutbuf); 2482*7e6ad469SVishal Kulkarni } 2483*7e6ad469SVishal Kulkarni #undef T6_MODREGS 2484*7e6ad469SVishal Kulkarni 2485*7e6ad469SVishal Kulkarni #define T5_MODREGS(name) { #name, t5_##name##_regs } 2486*7e6ad469SVishal Kulkarni 2487*7e6ad469SVishal Kulkarni static int 2488*7e6ad469SVishal Kulkarni dump_regs_t5(const u32 *regs, struct cudbg_buffer *cudbg_poutbuf) 2489*7e6ad469SVishal Kulkarni { 2490*7e6ad469SVishal Kulkarni static struct mod_regs t5_mod[] = { 2491*7e6ad469SVishal Kulkarni T5_MODREGS(sge), 2492*7e6ad469SVishal Kulkarni { "pci", t5_pcie_regs }, 2493*7e6ad469SVishal Kulkarni T5_MODREGS(dbg), 2494*7e6ad469SVishal Kulkarni { "mc0", t5_mc_0_regs }, 2495*7e6ad469SVishal Kulkarni { "mc1", t5_mc_1_regs }, 2496*7e6ad469SVishal Kulkarni T5_MODREGS(ma), 2497*7e6ad469SVishal Kulkarni { "edc0", t5_edc_t50_regs }, 2498*7e6ad469SVishal Kulkarni { "edc1", t5_edc_t51_regs }, 2499*7e6ad469SVishal Kulkarni T5_MODREGS(cim), 2500*7e6ad469SVishal Kulkarni T5_MODREGS(tp), 2501*7e6ad469SVishal Kulkarni { "ulprx", t5_ulp_rx_regs }, 2502*7e6ad469SVishal Kulkarni { "ulptx", t5_ulp_tx_regs }, 2503*7e6ad469SVishal Kulkarni { "pmrx", t5_pm_rx_regs }, 2504*7e6ad469SVishal Kulkarni { "pmtx", t5_pm_tx_regs }, 2505*7e6ad469SVishal Kulkarni T5_MODREGS(mps), 2506*7e6ad469SVishal Kulkarni { "cplsw", t5_cpl_switch_regs }, 2507*7e6ad469SVishal Kulkarni T5_MODREGS(smb), 2508*7e6ad469SVishal Kulkarni { "i2c", t5_i2cm_regs }, 2509*7e6ad469SVishal Kulkarni T5_MODREGS(mi), 2510*7e6ad469SVishal Kulkarni T5_MODREGS(uart), 2511*7e6ad469SVishal Kulkarni T5_MODREGS(pmu), 2512*7e6ad469SVishal Kulkarni T5_MODREGS(sf), 2513*7e6ad469SVishal Kulkarni T5_MODREGS(pl), 2514*7e6ad469SVishal Kulkarni T5_MODREGS(le), 2515*7e6ad469SVishal Kulkarni T5_MODREGS(ncsi), 2516*7e6ad469SVishal Kulkarni T5_MODREGS(mac), 2517*7e6ad469SVishal Kulkarni { "hma", t5_hma_t5_regs } 2518*7e6ad469SVishal Kulkarni }; 2519*7e6ad469SVishal Kulkarni 2520*7e6ad469SVishal Kulkarni return dump_regs_table(regs, t5_mod, 2521*7e6ad469SVishal Kulkarni ARRAY_SIZE(t5_mod), 2522*7e6ad469SVishal Kulkarni "sge, pci, dbg, mc0, mc1, ma, edc0, edc1, cim, "\ 2523*7e6ad469SVishal Kulkarni "tp, ulprx, ulptx, pmrx, pmtx, mps, cplsw, smb, "\ 2524*7e6ad469SVishal Kulkarni "i2c, mi, uart, pmu, sf, pl, le, ncsi, "\ 2525*7e6ad469SVishal Kulkarni "mac, hma", cudbg_poutbuf); 2526*7e6ad469SVishal Kulkarni } 2527*7e6ad469SVishal Kulkarni #undef T5_MODREGS 2528*7e6ad469SVishal Kulkarni 2529*7e6ad469SVishal Kulkarni int 2530*7e6ad469SVishal Kulkarni view_reg_dump(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 2531*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 2532*7e6ad469SVishal Kulkarni { 2533*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 2534*7e6ad469SVishal Kulkarni int rc = 0; 2535*7e6ad469SVishal Kulkarni u32 *regs; 2536*7e6ad469SVishal Kulkarni 2537*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 2538*7e6ad469SVishal Kulkarni if (rc) 2539*7e6ad469SVishal Kulkarni return rc; 2540*7e6ad469SVishal Kulkarni 2541*7e6ad469SVishal Kulkarni regs = (u32 *) ((unsigned int *)dc_buff.data); 2542*7e6ad469SVishal Kulkarni if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) 2543*7e6ad469SVishal Kulkarni rc = dump_regs_t5((u32 *)regs, cudbg_poutbuf); 2544*7e6ad469SVishal Kulkarni else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6) 2545*7e6ad469SVishal Kulkarni rc = dump_regs_t6((u32 *)regs, cudbg_poutbuf); 2546*7e6ad469SVishal Kulkarni return rc; 2547*7e6ad469SVishal Kulkarni } 2548*7e6ad469SVishal Kulkarni 2549*7e6ad469SVishal Kulkarni static int 2550*7e6ad469SVishal Kulkarni t6_view_wtp(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 2551*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf) 2552*7e6ad469SVishal Kulkarni { 2553*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 2554*7e6ad469SVishal Kulkarni struct wtp_data *wtp = NULL; 2555*7e6ad469SVishal Kulkarni int rc = 0; 2556*7e6ad469SVishal Kulkarni int i = 0; 2557*7e6ad469SVishal Kulkarni /****Rx****/ 2558*7e6ad469SVishal Kulkarni u32 pcie_core_dmaw_sop = 0; 2559*7e6ad469SVishal Kulkarni u32 sge_pcie_sop = 0; 2560*7e6ad469SVishal Kulkarni u32 csw_sge_sop = 0; 2561*7e6ad469SVishal Kulkarni u32 tp_csw_sop = 0; 2562*7e6ad469SVishal Kulkarni u32 tpcside_csw_sop = 0; 2563*7e6ad469SVishal Kulkarni u32 ulprx_tpcside_sop = 0; 2564*7e6ad469SVishal Kulkarni u32 pmrx_ulprx_sop = 0; 2565*7e6ad469SVishal Kulkarni u32 mps_tpeside_sop = 0; 2566*7e6ad469SVishal Kulkarni u32 mps_tp_sop = 0; 2567*7e6ad469SVishal Kulkarni u32 xgm_mps_sop = 0; 2568*7e6ad469SVishal Kulkarni u32 rx_xgm_xgm_sop = 0; 2569*7e6ad469SVishal Kulkarni u32 wire_xgm_sop = 0; 2570*7e6ad469SVishal Kulkarni u32 rx_wire_macok_sop = 0; 2571*7e6ad469SVishal Kulkarni 2572*7e6ad469SVishal Kulkarni u32 pcie_core_dmaw_eop = 0; 2573*7e6ad469SVishal Kulkarni u32 sge_pcie_eop = 0; 2574*7e6ad469SVishal Kulkarni u32 csw_sge_eop = 0; 2575*7e6ad469SVishal Kulkarni u32 tp_csw_eop = 0; 2576*7e6ad469SVishal Kulkarni u32 tpcside_csw_eop = 0; 2577*7e6ad469SVishal Kulkarni u32 ulprx_tpcside_eop = 0; 2578*7e6ad469SVishal Kulkarni u32 pmrx_ulprx_eop = 0; 2579*7e6ad469SVishal Kulkarni u32 mps_tpeside_eop = 0; 2580*7e6ad469SVishal Kulkarni u32 mps_tp_eop = 0; 2581*7e6ad469SVishal Kulkarni u32 xgm_mps_eop = 0; 2582*7e6ad469SVishal Kulkarni u32 rx_xgm_xgm_eop = 0; 2583*7e6ad469SVishal Kulkarni u32 wire_xgm_eop = 0; 2584*7e6ad469SVishal Kulkarni u32 rx_wire_macok_eop = 0; 2585*7e6ad469SVishal Kulkarni 2586*7e6ad469SVishal Kulkarni /****Tx****/ 2587*7e6ad469SVishal Kulkarni u32 core_pcie_dma_rsp_sop = 0; 2588*7e6ad469SVishal Kulkarni u32 pcie_sge_dma_rsp_sop = 0; 2589*7e6ad469SVishal Kulkarni u32 sge_debug_index6_sop = 0; 2590*7e6ad469SVishal Kulkarni u32 sge_utx_sop = 0; 2591*7e6ad469SVishal Kulkarni u32 utx_tp_sop = 0; 2592*7e6ad469SVishal Kulkarni u32 sge_work_req_sop = 0; 2593*7e6ad469SVishal Kulkarni u32 utx_tpcside_sop = 0; 2594*7e6ad469SVishal Kulkarni u32 tpcside_rxarb_sop = 0; 2595*7e6ad469SVishal Kulkarni u32 tpeside_mps_sop = 0; 2596*7e6ad469SVishal Kulkarni u32 tp_mps_sop = 0; 2597*7e6ad469SVishal Kulkarni u32 mps_xgm_sop = 0; 2598*7e6ad469SVishal Kulkarni u32 tx_xgm_xgm_sop = 0; 2599*7e6ad469SVishal Kulkarni u32 xgm_wire_sop = 0; 2600*7e6ad469SVishal Kulkarni u32 tx_macok_wire_sop = 0; 2601*7e6ad469SVishal Kulkarni 2602*7e6ad469SVishal Kulkarni u32 core_pcie_dma_rsp_eop = 0; 2603*7e6ad469SVishal Kulkarni u32 pcie_sge_dma_rsp_eop = 0; 2604*7e6ad469SVishal Kulkarni u32 sge_debug_index6_eop = 0; 2605*7e6ad469SVishal Kulkarni u32 sge_utx_eop = 0; 2606*7e6ad469SVishal Kulkarni u32 utx_tp_eop = 0; 2607*7e6ad469SVishal Kulkarni u32 utx_tpcside_eop = 0; 2608*7e6ad469SVishal Kulkarni u32 tpcside_rxarb_eop = 0; 2609*7e6ad469SVishal Kulkarni u32 tpeside_mps_eop = 0; 2610*7e6ad469SVishal Kulkarni u32 tp_mps_eop = 0; 2611*7e6ad469SVishal Kulkarni u32 mps_xgm_eop = 0; 2612*7e6ad469SVishal Kulkarni u32 tx_xgm_xgm_eop = 0; 2613*7e6ad469SVishal Kulkarni u32 xgm_wire_eop = 0; 2614*7e6ad469SVishal Kulkarni u32 tx_macok_wire_eop = 0; 2615*7e6ad469SVishal Kulkarni 2616*7e6ad469SVishal Kulkarni u32 pcie_core_cmd_req_sop = 0; 2617*7e6ad469SVishal Kulkarni u32 sge_pcie_cmd_req_sop = 0; 2618*7e6ad469SVishal Kulkarni u32 core_pcie_cmd_rsp_sop = 0; 2619*7e6ad469SVishal Kulkarni u32 pcie_sge_cmd_rsp_sop = 0; 2620*7e6ad469SVishal Kulkarni u32 sge_cim_sop = 0; 2621*7e6ad469SVishal Kulkarni u32 pcie_core_dma_req_sop = 0; 2622*7e6ad469SVishal Kulkarni u32 sge_pcie_dma_req_sop = 0; 2623*7e6ad469SVishal Kulkarni u32 utx_sge_dma_req_sop = 0; 2624*7e6ad469SVishal Kulkarni 2625*7e6ad469SVishal Kulkarni u32 sge_pcie_cmd_req_eop = 0; 2626*7e6ad469SVishal Kulkarni u32 pcie_core_cmd_req_eop = 0; 2627*7e6ad469SVishal Kulkarni u32 core_pcie_cmd_rsp_eop = 0; 2628*7e6ad469SVishal Kulkarni u32 pcie_sge_cmd_rsp_eop = 0; 2629*7e6ad469SVishal Kulkarni u32 sge_cim_eop = 0; 2630*7e6ad469SVishal Kulkarni u32 pcie_core_dma_req_eop = 0; 2631*7e6ad469SVishal Kulkarni u32 sge_pcie_dma_req_eop = 0; 2632*7e6ad469SVishal Kulkarni u32 utx_sge_dma_req_eop = 0; 2633*7e6ad469SVishal Kulkarni 2634*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 2635*7e6ad469SVishal Kulkarni if (rc) 2636*7e6ad469SVishal Kulkarni return rc; 2637*7e6ad469SVishal Kulkarni 2638*7e6ad469SVishal Kulkarni wtp = (struct wtp_data *) dc_buff.data; 2639*7e6ad469SVishal Kulkarni /*Add up the sop/eop of all channels.*/ 2640*7e6ad469SVishal Kulkarni for (i = 0; i < 8; i++) { 2641*7e6ad469SVishal Kulkarni if (i < 2) { 2642*7e6ad469SVishal Kulkarni /*Rx Path*/ 2643*7e6ad469SVishal Kulkarni csw_sge_sop += 2644*7e6ad469SVishal Kulkarni (wtp->sge_debug_data_high_indx1.sop[i]); 2645*7e6ad469SVishal Kulkarni tp_csw_sop += 2646*7e6ad469SVishal Kulkarni (wtp->sge_debug_data_high_indx9.sop[i]); 2647*7e6ad469SVishal Kulkarni 2648*7e6ad469SVishal Kulkarni csw_sge_eop += (wtp->csw_sge.eop[i]); 2649*7e6ad469SVishal Kulkarni tp_csw_eop += (wtp->tp_csw.eop[i]); 2650*7e6ad469SVishal Kulkarni rx_wire_macok_sop += 2651*7e6ad469SVishal Kulkarni wtp->mac_porrx_etherstatspkts.sop[i]; 2652*7e6ad469SVishal Kulkarni rx_wire_macok_eop += 2653*7e6ad469SVishal Kulkarni wtp->mac_porrx_etherstatspkts.eop[i]; 2654*7e6ad469SVishal Kulkarni 2655*7e6ad469SVishal Kulkarni /*Tx Path*/ 2656*7e6ad469SVishal Kulkarni sge_pcie_cmd_req_sop += wtp->sge_pcie_cmd_req.sop[i]; 2657*7e6ad469SVishal Kulkarni pcie_sge_cmd_rsp_sop += wtp->pcie_sge_cmd_rsp.sop[i]; 2658*7e6ad469SVishal Kulkarni sge_cim_sop += wtp->sge_cim.sop[i]; 2659*7e6ad469SVishal Kulkarni tpcside_csw_sop += (wtp->utx_tpcside_tx.sop[i]); 2660*7e6ad469SVishal Kulkarni sge_work_req_sop += wtp->sge_work_req_pkt.sop[i]; 2661*7e6ad469SVishal Kulkarni tx_macok_wire_sop += 2662*7e6ad469SVishal Kulkarni wtp->mac_portx_etherstatspkts.sop[i]; 2663*7e6ad469SVishal Kulkarni tx_macok_wire_eop += 2664*7e6ad469SVishal Kulkarni wtp->mac_portx_etherstatspkts.eop[i]; 2665*7e6ad469SVishal Kulkarni 2666*7e6ad469SVishal Kulkarni sge_pcie_cmd_req_eop += wtp->sge_pcie_cmd_req.eop[i]; 2667*7e6ad469SVishal Kulkarni pcie_sge_cmd_rsp_eop += wtp->pcie_sge_cmd_rsp.eop[i]; 2668*7e6ad469SVishal Kulkarni sge_cim_eop += wtp->sge_cim.eop[i]; 2669*7e6ad469SVishal Kulkarni 2670*7e6ad469SVishal Kulkarni } 2671*7e6ad469SVishal Kulkarni 2672*7e6ad469SVishal Kulkarni if (i < 3) { 2673*7e6ad469SVishal Kulkarni pcie_core_cmd_req_sop += wtp->pcie_cmd_stat2.sop[i]; 2674*7e6ad469SVishal Kulkarni core_pcie_cmd_rsp_sop += wtp->pcie_cmd_stat3.sop[i]; 2675*7e6ad469SVishal Kulkarni 2676*7e6ad469SVishal Kulkarni core_pcie_cmd_rsp_eop += wtp->pcie_cmd_stat3.eop[i]; 2677*7e6ad469SVishal Kulkarni pcie_core_cmd_req_eop += wtp->pcie_cmd_stat2.eop[i]; 2678*7e6ad469SVishal Kulkarni } 2679*7e6ad469SVishal Kulkarni 2680*7e6ad469SVishal Kulkarni if (i < 4) { 2681*7e6ad469SVishal Kulkarni /*Rx Path*/ 2682*7e6ad469SVishal Kulkarni pcie_core_dmaw_sop += 2683*7e6ad469SVishal Kulkarni (wtp->pcie_dma1_stat2.sop[i]); 2684*7e6ad469SVishal Kulkarni sge_pcie_sop += 2685*7e6ad469SVishal Kulkarni (wtp->sge_debug_data_high_indx7.sop[i]); 2686*7e6ad469SVishal Kulkarni ulprx_tpcside_sop += (wtp->ulprx_tpcside.sop[i]); 2687*7e6ad469SVishal Kulkarni pmrx_ulprx_sop += (wtp->pmrx_ulprx.sop[i]); 2688*7e6ad469SVishal Kulkarni mps_tpeside_sop += 2689*7e6ad469SVishal Kulkarni (wtp->tp_dbg_eside_pktx.sop[i]); 2690*7e6ad469SVishal Kulkarni rx_xgm_xgm_sop += 2691*7e6ad469SVishal Kulkarni (wtp->mac_porrx_pkt_count.sop[i]); 2692*7e6ad469SVishal Kulkarni wire_xgm_sop += 2693*7e6ad469SVishal Kulkarni (wtp->mac_porrx_aframestra_ok.sop[i]); 2694*7e6ad469SVishal Kulkarni 2695*7e6ad469SVishal Kulkarni pcie_core_dmaw_eop += 2696*7e6ad469SVishal Kulkarni (wtp->pcie_dma1_stat2.eop[i]); 2697*7e6ad469SVishal Kulkarni sge_pcie_eop += (wtp->sge_pcie.eop[i]); 2698*7e6ad469SVishal Kulkarni tpcside_csw_eop += (wtp->tpcside_csw.eop[i]); 2699*7e6ad469SVishal Kulkarni ulprx_tpcside_eop += (wtp->ulprx_tpcside.eop[i]); 2700*7e6ad469SVishal Kulkarni pmrx_ulprx_eop += (wtp->pmrx_ulprx.eop[i]); 2701*7e6ad469SVishal Kulkarni mps_tpeside_eop += (wtp->mps_tpeside.eop[i]); 2702*7e6ad469SVishal Kulkarni rx_xgm_xgm_eop += 2703*7e6ad469SVishal Kulkarni (wtp->mac_porrx_pkt_count.eop[i]); 2704*7e6ad469SVishal Kulkarni wire_xgm_eop += 2705*7e6ad469SVishal Kulkarni (wtp->mac_porrx_aframestra_ok.eop[i]); 2706*7e6ad469SVishal Kulkarni 2707*7e6ad469SVishal Kulkarni /*special case type 3:*/ 2708*7e6ad469SVishal Kulkarni mps_tp_sop += (wtp->mps_tp.sop[i]); 2709*7e6ad469SVishal Kulkarni mps_tp_eop += (wtp->mps_tp.eop[i]); 2710*7e6ad469SVishal Kulkarni 2711*7e6ad469SVishal Kulkarni /*Tx Path*/ 2712*7e6ad469SVishal Kulkarni core_pcie_dma_rsp_sop += 2713*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.sop[i]; 2714*7e6ad469SVishal Kulkarni pcie_sge_dma_rsp_sop += wtp->pcie_sge_dma_rsp.sop[i]; 2715*7e6ad469SVishal Kulkarni sge_debug_index6_sop += 2716*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_6.sop[i]; 2717*7e6ad469SVishal Kulkarni sge_utx_sop += wtp->ulp_se_cnt_chx.sop[i]; 2718*7e6ad469SVishal Kulkarni utx_tp_sop += wtp->utx_tp.sop[i]; 2719*7e6ad469SVishal Kulkarni utx_tpcside_sop += wtp->utx_tpcside.sop[i]; 2720*7e6ad469SVishal Kulkarni tpcside_rxarb_sop += wtp->tpcside_rxarb.sop[i]; 2721*7e6ad469SVishal Kulkarni tpeside_mps_sop += wtp->tpeside_mps.sop[i]; 2722*7e6ad469SVishal Kulkarni tx_xgm_xgm_sop += 2723*7e6ad469SVishal Kulkarni wtp->mac_portx_pkt_count.sop[i]; 2724*7e6ad469SVishal Kulkarni xgm_wire_sop += 2725*7e6ad469SVishal Kulkarni wtp->mac_portx_aframestra_ok.sop[i]; 2726*7e6ad469SVishal Kulkarni 2727*7e6ad469SVishal Kulkarni core_pcie_dma_rsp_eop += 2728*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.eop[i]; 2729*7e6ad469SVishal Kulkarni pcie_sge_dma_rsp_eop += wtp->pcie_sge_dma_rsp.eop[i]; 2730*7e6ad469SVishal Kulkarni sge_debug_index6_eop += 2731*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_6.eop[i]; 2732*7e6ad469SVishal Kulkarni sge_utx_eop += wtp->sge_utx.eop[i]; 2733*7e6ad469SVishal Kulkarni utx_tp_eop += wtp->utx_tp.eop[i]; 2734*7e6ad469SVishal Kulkarni utx_tpcside_eop += wtp->utx_tpcside.eop[i]; 2735*7e6ad469SVishal Kulkarni tpcside_rxarb_eop += wtp->tpcside_rxarb.eop[i]; 2736*7e6ad469SVishal Kulkarni tpeside_mps_eop += wtp->tpeside_mps.eop[i]; 2737*7e6ad469SVishal Kulkarni tx_xgm_xgm_eop += 2738*7e6ad469SVishal Kulkarni wtp->mac_portx_pkt_count.eop[i]; 2739*7e6ad469SVishal Kulkarni xgm_wire_eop += 2740*7e6ad469SVishal Kulkarni wtp->mac_portx_aframestra_ok.eop[i]; 2741*7e6ad469SVishal Kulkarni 2742*7e6ad469SVishal Kulkarni /*special case type 3:*/ 2743*7e6ad469SVishal Kulkarni tp_mps_sop += wtp->tp_mps.sop[i]; 2744*7e6ad469SVishal Kulkarni mps_xgm_sop += wtp->mps_xgm.sop[i]; 2745*7e6ad469SVishal Kulkarni 2746*7e6ad469SVishal Kulkarni tp_mps_eop += wtp->tp_mps.eop[i]; 2747*7e6ad469SVishal Kulkarni mps_xgm_eop += wtp->mps_xgm.eop[i]; 2748*7e6ad469SVishal Kulkarni 2749*7e6ad469SVishal Kulkarni pcie_core_dma_req_sop += 2750*7e6ad469SVishal Kulkarni wtp->pcie_dma1_stat2_core.sop[i]; 2751*7e6ad469SVishal Kulkarni sge_pcie_dma_req_sop += 2752*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx5.sop[i]; 2753*7e6ad469SVishal Kulkarni utx_sge_dma_req_sop += wtp->utx_sge_dma_req.sop[i]; 2754*7e6ad469SVishal Kulkarni 2755*7e6ad469SVishal Kulkarni pcie_core_dma_req_eop += 2756*7e6ad469SVishal Kulkarni wtp->pcie_dma1_stat2_core.eop[i]; 2757*7e6ad469SVishal Kulkarni sge_pcie_dma_req_eop += 2758*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx5.eop[i]; 2759*7e6ad469SVishal Kulkarni utx_sge_dma_req_eop += wtp->utx_sge_dma_req.eop[i]; 2760*7e6ad469SVishal Kulkarni } 2761*7e6ad469SVishal Kulkarni 2762*7e6ad469SVishal Kulkarni if (i < 5) { 2763*7e6ad469SVishal Kulkarni xgm_mps_sop += (wtp->xgm_mps.sop[i]); 2764*7e6ad469SVishal Kulkarni xgm_mps_eop += (wtp->xgm_mps.eop[i]); 2765*7e6ad469SVishal Kulkarni } 2766*7e6ad469SVishal Kulkarni } 2767*7e6ad469SVishal Kulkarni printf("ifaces = nic0 nic1\n"); 2768*7e6ad469SVishal Kulkarni printf("*************************EGGRESS (TX) PATH **********************************\n"); 2769*7e6ad469SVishal Kulkarni printf("MOD : core---->PCIE---->SGE<-| #Ring Doorbell\n"); 2770*7e6ad469SVishal Kulkarni printf("SOP ? ??? |\n"); 2771*7e6ad469SVishal Kulkarni printf("EOP ? ??? |\n"); 2772*7e6ad469SVishal Kulkarni printf("MOD |<-core<----PCIE<----SGE<-| #Request Work Request\n"); 2773*7e6ad469SVishal Kulkarni printf("SOP_CH0 %02X %02x\n", 2774*7e6ad469SVishal Kulkarni wtp->pcie_cmd_stat2.sop[0], wtp->sge_pcie_cmd_req.sop[0]); 2775*7e6ad469SVishal Kulkarni printf("SOP | %02X %02X\n", 2776*7e6ad469SVishal Kulkarni pcie_core_cmd_req_sop, sge_pcie_cmd_req_sop); 2777*7e6ad469SVishal Kulkarni printf("EOP | %2X %2X\n", 2778*7e6ad469SVishal Kulkarni pcie_core_cmd_req_eop, sge_pcie_cmd_req_eop); 2779*7e6ad469SVishal Kulkarni printf("MOD |->core---->PCIE---->SGE------>CIM/uP->| uP<-CIM<-CSW #->Work req. <-Pkts\n"); 2780*7e6ad469SVishal Kulkarni printf("SOP_CH0 %02X %02X %02X"\ 2781*7e6ad469SVishal Kulkarni " | %2X\n", 2782*7e6ad469SVishal Kulkarni wtp->pcie_cmd_stat3.sop[0], wtp->pcie_sge_cmd_rsp.sop[1], 2783*7e6ad469SVishal Kulkarni wtp->sge_cim.sop[0], wtp->sge_work_req_pkt.sop[0]); 2784*7e6ad469SVishal Kulkarni 2785*7e6ad469SVishal Kulkarni printf("SOP_CH1 %02X"\ 2786*7e6ad469SVishal Kulkarni " |\n", wtp->pcie_sge_cmd_rsp.sop[1]); 2787*7e6ad469SVishal Kulkarni printf("SOP %02X %02X %2X"\ 2788*7e6ad469SVishal Kulkarni " | %2X\n", core_pcie_cmd_rsp_sop, 2789*7e6ad469SVishal Kulkarni pcie_sge_cmd_rsp_sop, sge_cim_sop, sge_work_req_sop); 2790*7e6ad469SVishal Kulkarni printf("EOP %2X %2X %2X"\ 2791*7e6ad469SVishal Kulkarni " |\n", core_pcie_cmd_rsp_eop, 2792*7e6ad469SVishal Kulkarni pcie_sge_cmd_rsp_eop, sge_cim_eop); 2793*7e6ad469SVishal Kulkarni printf("MOD |<-core<----PCIE<----SGE<------UTX<--------|#data dma requests\n"); 2794*7e6ad469SVishal Kulkarni printf("SOP_CH0 %02X\n", 2795*7e6ad469SVishal Kulkarni wtp->pcie_dma1_stat2_core.sop[0]); 2796*7e6ad469SVishal Kulkarni printf("SOP_CH1 %02X\n", 2797*7e6ad469SVishal Kulkarni wtp->pcie_dma1_stat2_core.sop[1]); 2798*7e6ad469SVishal Kulkarni printf("SOP | %2X\n", 2799*7e6ad469SVishal Kulkarni pcie_core_dma_req_sop); 2800*7e6ad469SVishal Kulkarni printf("EOP | %2X\n", 2801*7e6ad469SVishal Kulkarni pcie_core_dma_req_eop); 2802*7e6ad469SVishal Kulkarni 2803*7e6ad469SVishal Kulkarni printf("MOD |->core-->PCIE-->SGE-->UTX---->TPC------->TPE---->MPS--->MAC--->MACOK->wire\n"); 2804*7e6ad469SVishal Kulkarni printf("SOP_CH0 %02X %2X "\ 2805*7e6ad469SVishal Kulkarni " %2X %2X %2X %02X %02X %02X %02X "\ 2806*7e6ad469SVishal Kulkarni " %02X\n", 2807*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.sop[0], wtp->ulp_se_cnt_chx.sop[0], 2808*7e6ad469SVishal Kulkarni wtp->utx_tpcside.sop[0], wtp->tpcside_rxarb.sop[0], 2809*7e6ad469SVishal Kulkarni wtp->tpeside_mps.sop[0], wtp->tp_mps.sop[0], 2810*7e6ad469SVishal Kulkarni wtp->mps_xgm.sop[0], wtp->mac_portx_pkt_count.sop[0], 2811*7e6ad469SVishal Kulkarni wtp->mac_portx_aframestra_ok.sop[0], 2812*7e6ad469SVishal Kulkarni wtp->mac_portx_etherstatspkts.sop[0]); 2813*7e6ad469SVishal Kulkarni 2814*7e6ad469SVishal Kulkarni printf("EOP_CH0 %02X %2X "\ 2815*7e6ad469SVishal Kulkarni " %2X %2X %2X %02X %02X %02X %02X"\ 2816*7e6ad469SVishal Kulkarni " %02X\n", 2817*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.eop[0], wtp->ulp_se_cnt_chx.eop[0], 2818*7e6ad469SVishal Kulkarni wtp->utx_tpcside.eop[0], wtp->tpcside_rxarb.eop[0], 2819*7e6ad469SVishal Kulkarni wtp->tpeside_mps.eop[0], wtp->tp_mps.eop[0], 2820*7e6ad469SVishal Kulkarni wtp->mps_xgm.eop[0], wtp->mac_portx_pkt_count.eop[0], 2821*7e6ad469SVishal Kulkarni wtp->mac_portx_aframestra_ok.eop[0], 2822*7e6ad469SVishal Kulkarni wtp->mac_portx_etherstatspkts.eop[0]); 2823*7e6ad469SVishal Kulkarni printf("SOP_CH1 %02X %2X "\ 2824*7e6ad469SVishal Kulkarni " %2X %2X %2X %02X %02X %02X %02X "\ 2825*7e6ad469SVishal Kulkarni "%02X\n", 2826*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.sop[1], wtp->ulp_se_cnt_chx.sop[1], 2827*7e6ad469SVishal Kulkarni wtp->utx_tpcside.sop[1], wtp->tpcside_rxarb.sop[1], 2828*7e6ad469SVishal Kulkarni wtp->tpeside_mps.sop[1], wtp->tp_mps.sop[1], 2829*7e6ad469SVishal Kulkarni wtp->mps_xgm.sop[1], wtp->mac_portx_pkt_count.sop[1], 2830*7e6ad469SVishal Kulkarni wtp->mac_portx_aframestra_ok.sop[1], 2831*7e6ad469SVishal Kulkarni wtp->mac_portx_etherstatspkts.sop[1]); 2832*7e6ad469SVishal Kulkarni 2833*7e6ad469SVishal Kulkarni printf("EOP_CH1 %02X %2X "\ 2834*7e6ad469SVishal Kulkarni " %2X %2X %2X %02X %02X %02X %02X"\ 2835*7e6ad469SVishal Kulkarni " %02X\n", 2836*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.eop[1], wtp->ulp_se_cnt_chx.eop[1], 2837*7e6ad469SVishal Kulkarni wtp->utx_tpcside.eop[1], wtp->tpcside_rxarb.eop[1], 2838*7e6ad469SVishal Kulkarni wtp->tpeside_mps.eop[1], wtp->tp_mps.eop[1], 2839*7e6ad469SVishal Kulkarni wtp->mps_xgm.eop[1], wtp->mac_portx_pkt_count.eop[1], 2840*7e6ad469SVishal Kulkarni wtp->mac_portx_aframestra_ok.eop[1], 2841*7e6ad469SVishal Kulkarni wtp->mac_portx_etherstatspkts.eop[1]); 2842*7e6ad469SVishal Kulkarni printf("SOP_CH2 %02X %2X "\ 2843*7e6ad469SVishal Kulkarni " %2X %2X %2X %02X %02X\n", 2844*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.sop[2], wtp->ulp_se_cnt_chx.sop[2], 2845*7e6ad469SVishal Kulkarni wtp->utx_tpcside.sop[2], wtp->tpcside_rxarb.sop[2], 2846*7e6ad469SVishal Kulkarni wtp->tpeside_mps.sop[2], wtp->tp_mps.sop[2], 2847*7e6ad469SVishal Kulkarni wtp->mps_xgm.sop[2]); 2848*7e6ad469SVishal Kulkarni 2849*7e6ad469SVishal Kulkarni printf("EOP_CH2 %02X %2X "\ 2850*7e6ad469SVishal Kulkarni " %2X %2X %2X %02X %02X\n", 2851*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.eop[2], wtp->ulp_se_cnt_chx.eop[2], 2852*7e6ad469SVishal Kulkarni wtp->utx_tpcside.eop[2], wtp->tpcside_rxarb.eop[2], 2853*7e6ad469SVishal Kulkarni wtp->tpeside_mps.eop[2], wtp->tp_mps.eop[2], 2854*7e6ad469SVishal Kulkarni wtp->mps_xgm.eop[2]); 2855*7e6ad469SVishal Kulkarni printf("SOP_CH3 %02X %2X "\ 2856*7e6ad469SVishal Kulkarni " %2X %2X %2X %02X %02X\n", 2857*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.sop[3], wtp->ulp_se_cnt_chx.sop[3], 2858*7e6ad469SVishal Kulkarni wtp->utx_tpcside.sop[3], wtp->tpcside_rxarb.sop[3], 2859*7e6ad469SVishal Kulkarni wtp->tpeside_mps.sop[3], wtp->tp_mps.sop[3], 2860*7e6ad469SVishal Kulkarni wtp->mps_xgm.sop[3]); 2861*7e6ad469SVishal Kulkarni 2862*7e6ad469SVishal Kulkarni printf("EOP_CH3 %02X %2X "\ 2863*7e6ad469SVishal Kulkarni " %2X %2X %2X %02X %02X\n", 2864*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.eop[3], wtp->ulp_se_cnt_chx.eop[3], 2865*7e6ad469SVishal Kulkarni wtp->utx_tpcside.eop[3], wtp->tpcside_rxarb.eop[3], 2866*7e6ad469SVishal Kulkarni wtp->tpeside_mps.eop[3], wtp->tp_mps.eop[3], 2867*7e6ad469SVishal Kulkarni wtp->mps_xgm.eop[3]); 2868*7e6ad469SVishal Kulkarni printf("SOP %2X %2X "\ 2869*7e6ad469SVishal Kulkarni " %2X %2X %2X %2X %2X %2X %2X %2X\n", 2870*7e6ad469SVishal Kulkarni core_pcie_dma_rsp_sop, sge_utx_sop, utx_tp_sop, 2871*7e6ad469SVishal Kulkarni tpcside_rxarb_sop, tpeside_mps_sop, tp_mps_sop, 2872*7e6ad469SVishal Kulkarni mps_xgm_sop, tx_xgm_xgm_sop, xgm_wire_sop, 2873*7e6ad469SVishal Kulkarni tx_macok_wire_sop); 2874*7e6ad469SVishal Kulkarni printf("EOP %2X %2X "\ 2875*7e6ad469SVishal Kulkarni " %2X %2X %2X %2X %2X %2X %2X "\ 2876*7e6ad469SVishal Kulkarni " %2X\n", 2877*7e6ad469SVishal Kulkarni core_pcie_dma_rsp_eop, sge_utx_eop, utx_tp_eop, 2878*7e6ad469SVishal Kulkarni tpcside_rxarb_eop, tpeside_mps_eop, tp_mps_eop, 2879*7e6ad469SVishal Kulkarni mps_xgm_eop, tx_xgm_xgm_eop, xgm_wire_eop, 2880*7e6ad469SVishal Kulkarni tx_macok_wire_eop); 2881*7e6ad469SVishal Kulkarni printf("*************************INGRESS (RX) PATH **********************************\n"); 2882*7e6ad469SVishal Kulkarni 2883*7e6ad469SVishal Kulkarni printf("MOD core<-PCIE<---SGE<--CSW<-----TPC<-URX<-LE-TPE<-----MPS<--MAC<-MACOK<--wire\n"); 2884*7e6ad469SVishal Kulkarni 2885*7e6ad469SVishal Kulkarni printf("SOP_CH0 %2X %2X %2X %2X"\ 2886*7e6ad469SVishal Kulkarni " %2X %2X %2X %2X %2X %2X %02X %02X "\ 2887*7e6ad469SVishal Kulkarni " %02X %02X\n", 2888*7e6ad469SVishal Kulkarni wtp->pcie_dma1_stat2.sop[0], 2889*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx7.sop[0], 2890*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx1.sop[0], 2891*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx9.sop[0], 2892*7e6ad469SVishal Kulkarni wtp->utx_tpcside_tx.sop[0], wtp->ulprx_tpcside.sop[0], 2893*7e6ad469SVishal Kulkarni wtp->pmrx_ulprx.sop[0], wtp->le_db_rsp_cnt.sop, 2894*7e6ad469SVishal Kulkarni wtp->tp_dbg_eside_pktx.sop[0], wtp->mps_tp.sop[0], 2895*7e6ad469SVishal Kulkarni wtp->xgm_mps.sop[0], wtp->mac_porrx_pkt_count.sop[0], 2896*7e6ad469SVishal Kulkarni wtp->mac_porrx_aframestra_ok.sop[0], 2897*7e6ad469SVishal Kulkarni wtp->mac_porrx_etherstatspkts.sop[0]); 2898*7e6ad469SVishal Kulkarni 2899*7e6ad469SVishal Kulkarni printf("EOP_CH0 %2X %2X %2X "\ 2900*7e6ad469SVishal Kulkarni "%2X %2X %2X %2X %2X %2X %2X %02X %02X "\ 2901*7e6ad469SVishal Kulkarni " %02X %02X\n", 2902*7e6ad469SVishal Kulkarni wtp->pcie_dma1_stat2.eop[0], 2903*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx7.eop[0], 2904*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx1.eop[0], 2905*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx9.eop[0], 2906*7e6ad469SVishal Kulkarni wtp->utx_tpcside_tx.eop[0], wtp->ulprx_tpcside.eop[0], 2907*7e6ad469SVishal Kulkarni wtp->pmrx_ulprx.eop[0], wtp->le_db_rsp_cnt.eop, 2908*7e6ad469SVishal Kulkarni wtp->tp_dbg_eside_pktx.eop[0], wtp->mps_tp.eop[0], 2909*7e6ad469SVishal Kulkarni wtp->xgm_mps.eop[0], wtp->mac_porrx_pkt_count.eop[0], 2910*7e6ad469SVishal Kulkarni wtp->mac_porrx_aframestra_ok.eop[0], 2911*7e6ad469SVishal Kulkarni wtp->mac_porrx_etherstatspkts.eop[0]); 2912*7e6ad469SVishal Kulkarni printf("SOP_CH1 %2X %2X %2X "\ 2913*7e6ad469SVishal Kulkarni " %2X %2X %2X %2X %2X %2X %02X %02X "\ 2914*7e6ad469SVishal Kulkarni " %02X %02X\n", 2915*7e6ad469SVishal Kulkarni wtp->pcie_dma1_stat2.sop[1], 2916*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx7.sop[1], 2917*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx1.sop[1], 2918*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx9.sop[1], 2919*7e6ad469SVishal Kulkarni wtp->utx_tpcside_tx.sop[1], wtp->ulprx_tpcside.sop[1], 2920*7e6ad469SVishal Kulkarni wtp->pmrx_ulprx.sop[1], wtp->tp_dbg_eside_pktx.sop[1], 2921*7e6ad469SVishal Kulkarni wtp->mps_tp.sop[1], wtp->xgm_mps.sop[1], 2922*7e6ad469SVishal Kulkarni wtp->mac_porrx_pkt_count.sop[1], 2923*7e6ad469SVishal Kulkarni wtp->mac_porrx_aframestra_ok.sop[1], 2924*7e6ad469SVishal Kulkarni wtp->mac_porrx_etherstatspkts.sop[1]); 2925*7e6ad469SVishal Kulkarni 2926*7e6ad469SVishal Kulkarni printf("EOP_CH1 %2X %2X %2X %2X"\ 2927*7e6ad469SVishal Kulkarni " %2X %2X %2X %2X %2X %02X %02X "\ 2928*7e6ad469SVishal Kulkarni "%02X %02X\n", 2929*7e6ad469SVishal Kulkarni wtp->pcie_dma1_stat2.eop[1], 2930*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx7.eop[1], 2931*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx1.eop[1], 2932*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx9.eop[1], 2933*7e6ad469SVishal Kulkarni wtp->utx_tpcside_tx.eop[1], wtp->ulprx_tpcside.eop[1], 2934*7e6ad469SVishal Kulkarni wtp->pmrx_ulprx.eop[1], wtp->tp_dbg_eside_pktx.eop[1], 2935*7e6ad469SVishal Kulkarni wtp->mps_tp.eop[1], wtp->xgm_mps.eop[1], 2936*7e6ad469SVishal Kulkarni wtp->mac_porrx_pkt_count.eop[1], 2937*7e6ad469SVishal Kulkarni wtp->mac_porrx_aframestra_ok.eop[1], 2938*7e6ad469SVishal Kulkarni wtp->mac_porrx_etherstatspkts.eop[1]); 2939*7e6ad469SVishal Kulkarni printf("SOP_CH2 "\ 2940*7e6ad469SVishal Kulkarni " %2X %02X\n", 2941*7e6ad469SVishal Kulkarni wtp->tp_dbg_eside_pktx.sop[2], wtp->xgm_mps.sop[2]); 2942*7e6ad469SVishal Kulkarni 2943*7e6ad469SVishal Kulkarni printf("EOP_CH2 "\ 2944*7e6ad469SVishal Kulkarni " %2X %02X\n", 2945*7e6ad469SVishal Kulkarni wtp->tp_dbg_eside_pktx.eop[2], wtp->xgm_mps.eop[2]); 2946*7e6ad469SVishal Kulkarni printf("SOP_CH3 "\ 2947*7e6ad469SVishal Kulkarni " %2X %02X\n", 2948*7e6ad469SVishal Kulkarni wtp->tp_dbg_eside_pktx.sop[3], 2949*7e6ad469SVishal Kulkarni wtp->xgm_mps.sop[3]); 2950*7e6ad469SVishal Kulkarni 2951*7e6ad469SVishal Kulkarni printf("EOP_CH3 "\ 2952*7e6ad469SVishal Kulkarni " %2X %02X\n", 2953*7e6ad469SVishal Kulkarni wtp->tp_dbg_eside_pktx.eop[3], wtp->xgm_mps.eop[3]); 2954*7e6ad469SVishal Kulkarni printf("SOP_CH4 "\ 2955*7e6ad469SVishal Kulkarni " %02X\n", 2956*7e6ad469SVishal Kulkarni wtp->xgm_mps.sop[4]); 2957*7e6ad469SVishal Kulkarni printf("EOP_CH4 "\ 2958*7e6ad469SVishal Kulkarni " %02X\n", 2959*7e6ad469SVishal Kulkarni wtp->xgm_mps.eop[4]); 2960*7e6ad469SVishal Kulkarni printf("SOP_CH5 "\ 2961*7e6ad469SVishal Kulkarni " %02X\n", 2962*7e6ad469SVishal Kulkarni wtp->xgm_mps.sop[5]); 2963*7e6ad469SVishal Kulkarni printf("EOP_CH5 "\ 2964*7e6ad469SVishal Kulkarni " %02X\n", 2965*7e6ad469SVishal Kulkarni wtp->xgm_mps.eop[5]); 2966*7e6ad469SVishal Kulkarni printf("SOP_CH6\n"); 2967*7e6ad469SVishal Kulkarni printf("EOP_CH6\n"); 2968*7e6ad469SVishal Kulkarni printf("SOP_CH7\n"); 2969*7e6ad469SVishal Kulkarni printf("EOP_CH7\n"); 2970*7e6ad469SVishal Kulkarni 2971*7e6ad469SVishal Kulkarni printf("SOP %2X %2X %2X %2X"\ 2972*7e6ad469SVishal Kulkarni " %2X %2X %2X %2X %2X %2X %2X %2X "\ 2973*7e6ad469SVishal Kulkarni " %2X\n", 2974*7e6ad469SVishal Kulkarni pcie_core_dmaw_sop, sge_pcie_sop, csw_sge_sop, 2975*7e6ad469SVishal Kulkarni tp_csw_sop, tpcside_csw_sop, ulprx_tpcside_sop, 2976*7e6ad469SVishal Kulkarni pmrx_ulprx_sop, mps_tpeside_sop, 2977*7e6ad469SVishal Kulkarni mps_tp_sop, xgm_mps_sop, rx_xgm_xgm_sop, 2978*7e6ad469SVishal Kulkarni wire_xgm_sop, rx_wire_macok_sop); 2979*7e6ad469SVishal Kulkarni printf("EOP %2X %2X %2X "\ 2980*7e6ad469SVishal Kulkarni "%2X %2X %2X %2X %2X %2X %2X %2X "\ 2981*7e6ad469SVishal Kulkarni " %2X %2X\n", 2982*7e6ad469SVishal Kulkarni pcie_core_dmaw_eop, sge_pcie_eop, csw_sge_eop, 2983*7e6ad469SVishal Kulkarni tp_csw_eop, tpcside_csw_eop, ulprx_tpcside_eop, 2984*7e6ad469SVishal Kulkarni pmrx_ulprx_eop, mps_tpeside_eop, mps_tp_eop, 2985*7e6ad469SVishal Kulkarni xgm_mps_eop, rx_xgm_xgm_eop, wire_xgm_eop, 2986*7e6ad469SVishal Kulkarni rx_wire_macok_eop); 2987*7e6ad469SVishal Kulkarni printf("DROP: ??? ??? ??? "\ 2988*7e6ad469SVishal Kulkarni "%2X(mib) %2X(err) %2X(oflow) %X(cls)\n", 2989*7e6ad469SVishal Kulkarni (wtp->mps_tp.drops & 0xFF), (wtp->xgm_mps.err & 0xFF), 2990*7e6ad469SVishal Kulkarni (wtp->xgm_mps.drop & 0xFF), 2991*7e6ad469SVishal Kulkarni (wtp->xgm_mps.cls_drop & 0xFF)); 2992*7e6ad469SVishal Kulkarni printf("INTS: "); 2993*7e6ad469SVishal Kulkarni for (i = 0; i < 2; i++) { 2994*7e6ad469SVishal Kulkarni printf("%2X<- %2X ", 2995*7e6ad469SVishal Kulkarni (wtp->pcie_core_dmai.sop[i] & 0xF), 2996*7e6ad469SVishal Kulkarni (wtp->sge_pcie_ints.sop[i] & 0xF)); 2997*7e6ad469SVishal Kulkarni } 2998*7e6ad469SVishal Kulkarni printf("(PCIE<-SGE, channels 0 to 1)\n"); 2999*7e6ad469SVishal Kulkarni 3000*7e6ad469SVishal Kulkarni return rc; 3001*7e6ad469SVishal Kulkarni } 3002*7e6ad469SVishal Kulkarni 3003*7e6ad469SVishal Kulkarni static int 3004*7e6ad469SVishal Kulkarni t5_view_wtp(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 3005*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf) 3006*7e6ad469SVishal Kulkarni { 3007*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 3008*7e6ad469SVishal Kulkarni struct wtp_data *wtp = NULL; 3009*7e6ad469SVishal Kulkarni int rc = 0; 3010*7e6ad469SVishal Kulkarni int i = 0; 3011*7e6ad469SVishal Kulkarni /****Rx****/ 3012*7e6ad469SVishal Kulkarni u32 pcie_core_dmaw_sop = 0; 3013*7e6ad469SVishal Kulkarni u32 sge_pcie_sop = 0; 3014*7e6ad469SVishal Kulkarni u32 csw_sge_sop = 0; 3015*7e6ad469SVishal Kulkarni u32 tp_csw_sop = 0; 3016*7e6ad469SVishal Kulkarni u32 tpcside_csw_sop = 0; 3017*7e6ad469SVishal Kulkarni u32 ulprx_tpcside_sop = 0; 3018*7e6ad469SVishal Kulkarni u32 pmrx_ulprx_sop = 0; 3019*7e6ad469SVishal Kulkarni u32 mps_tpeside_sop = 0; 3020*7e6ad469SVishal Kulkarni u32 mps_tp_sop = 0; 3021*7e6ad469SVishal Kulkarni u32 xgm_mps_sop = 0; 3022*7e6ad469SVishal Kulkarni u32 rx_xgm_xgm_sop = 0; 3023*7e6ad469SVishal Kulkarni u32 wire_xgm_sop = 0; 3024*7e6ad469SVishal Kulkarni 3025*7e6ad469SVishal Kulkarni u32 pcie_core_dmaw_eop = 0; 3026*7e6ad469SVishal Kulkarni u32 sge_pcie_eop = 0; 3027*7e6ad469SVishal Kulkarni u32 csw_sge_eop = 0; 3028*7e6ad469SVishal Kulkarni u32 tp_csw_eop = 0; 3029*7e6ad469SVishal Kulkarni u32 tpcside_csw_eop = 0; 3030*7e6ad469SVishal Kulkarni u32 ulprx_tpcside_eop = 0; 3031*7e6ad469SVishal Kulkarni u32 pmrx_ulprx_eop = 0; 3032*7e6ad469SVishal Kulkarni u32 mps_tpeside_eop = 0; 3033*7e6ad469SVishal Kulkarni u32 mps_tp_eop = 0; 3034*7e6ad469SVishal Kulkarni u32 xgm_mps_eop = 0; 3035*7e6ad469SVishal Kulkarni u32 rx_xgm_xgm_eop = 0; 3036*7e6ad469SVishal Kulkarni u32 wire_xgm_eop = 0; 3037*7e6ad469SVishal Kulkarni 3038*7e6ad469SVishal Kulkarni /****Tx****/ 3039*7e6ad469SVishal Kulkarni u32 core_pcie_dma_rsp_sop = 0; 3040*7e6ad469SVishal Kulkarni u32 pcie_sge_dma_rsp_sop = 0; 3041*7e6ad469SVishal Kulkarni u32 sge_debug_index6_sop = 0; 3042*7e6ad469SVishal Kulkarni u32 sge_utx_sop = 0; 3043*7e6ad469SVishal Kulkarni u32 utx_tp_sop = 0; 3044*7e6ad469SVishal Kulkarni u32 sge_work_req_sop = 0; 3045*7e6ad469SVishal Kulkarni u32 utx_tpcside_sop = 0; 3046*7e6ad469SVishal Kulkarni u32 tpcside_rxarb_sop = 0; 3047*7e6ad469SVishal Kulkarni u32 tpeside_mps_sop = 0; 3048*7e6ad469SVishal Kulkarni u32 tp_mps_sop = 0; 3049*7e6ad469SVishal Kulkarni u32 mps_xgm_sop = 0; 3050*7e6ad469SVishal Kulkarni u32 tx_xgm_xgm_sop = 0; 3051*7e6ad469SVishal Kulkarni u32 xgm_wire_sop = 0; 3052*7e6ad469SVishal Kulkarni 3053*7e6ad469SVishal Kulkarni u32 core_pcie_dma_rsp_eop = 0; 3054*7e6ad469SVishal Kulkarni u32 pcie_sge_dma_rsp_eop = 0; 3055*7e6ad469SVishal Kulkarni u32 sge_debug_index6_eop = 0; 3056*7e6ad469SVishal Kulkarni u32 sge_utx_eop = 0; 3057*7e6ad469SVishal Kulkarni u32 utx_tp_eop = 0; 3058*7e6ad469SVishal Kulkarni u32 utx_tpcside_eop = 0; 3059*7e6ad469SVishal Kulkarni u32 tpcside_rxarb_eop = 0; 3060*7e6ad469SVishal Kulkarni u32 tpeside_mps_eop = 0; 3061*7e6ad469SVishal Kulkarni u32 tp_mps_eop = 0; 3062*7e6ad469SVishal Kulkarni u32 mps_xgm_eop = 0; 3063*7e6ad469SVishal Kulkarni u32 tx_xgm_xgm_eop = 0; 3064*7e6ad469SVishal Kulkarni u32 xgm_wire_eop = 0; 3065*7e6ad469SVishal Kulkarni 3066*7e6ad469SVishal Kulkarni u32 pcie_core_cmd_req_sop = 0; 3067*7e6ad469SVishal Kulkarni u32 sge_pcie_cmd_req_sop = 0; 3068*7e6ad469SVishal Kulkarni u32 core_pcie_cmd_rsp_sop = 0; 3069*7e6ad469SVishal Kulkarni u32 pcie_sge_cmd_rsp_sop = 0; 3070*7e6ad469SVishal Kulkarni u32 sge_cim_sop = 0; 3071*7e6ad469SVishal Kulkarni u32 pcie_core_dma_req_sop = 0; 3072*7e6ad469SVishal Kulkarni u32 sge_pcie_dma_req_sop = 0; 3073*7e6ad469SVishal Kulkarni u32 utx_sge_dma_req_sop = 0; 3074*7e6ad469SVishal Kulkarni 3075*7e6ad469SVishal Kulkarni u32 sge_pcie_cmd_req_eop = 0; 3076*7e6ad469SVishal Kulkarni u32 pcie_core_cmd_req_eop = 0; 3077*7e6ad469SVishal Kulkarni u32 core_pcie_cmd_rsp_eop = 0; 3078*7e6ad469SVishal Kulkarni u32 pcie_sge_cmd_rsp_eop = 0; 3079*7e6ad469SVishal Kulkarni u32 sge_cim_eop = 0; 3080*7e6ad469SVishal Kulkarni u32 pcie_core_dma_req_eop = 0; 3081*7e6ad469SVishal Kulkarni u32 sge_pcie_dma_req_eop = 0; 3082*7e6ad469SVishal Kulkarni u32 utx_sge_dma_req_eop = 0; 3083*7e6ad469SVishal Kulkarni 3084*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 3085*7e6ad469SVishal Kulkarni if (rc) 3086*7e6ad469SVishal Kulkarni return rc; 3087*7e6ad469SVishal Kulkarni 3088*7e6ad469SVishal Kulkarni wtp = (struct wtp_data *) dc_buff.data; 3089*7e6ad469SVishal Kulkarni /*Add up the sop/eop of all channels.*/ 3090*7e6ad469SVishal Kulkarni for (i = 0; i < 8; i++) { 3091*7e6ad469SVishal Kulkarni if (i < 2) { 3092*7e6ad469SVishal Kulkarni /*Rx Path*/ 3093*7e6ad469SVishal Kulkarni csw_sge_sop += 3094*7e6ad469SVishal Kulkarni (wtp->sge_debug_data_high_indx1.sop[i]); 3095*7e6ad469SVishal Kulkarni tp_csw_sop += 3096*7e6ad469SVishal Kulkarni (wtp->sge_debug_data_high_indx9.sop[i]); 3097*7e6ad469SVishal Kulkarni 3098*7e6ad469SVishal Kulkarni csw_sge_eop += (wtp->csw_sge.eop[i]); 3099*7e6ad469SVishal Kulkarni tp_csw_eop += (wtp->tp_csw.eop[i]); 3100*7e6ad469SVishal Kulkarni 3101*7e6ad469SVishal Kulkarni /*Tx Path*/ 3102*7e6ad469SVishal Kulkarni sge_pcie_cmd_req_sop += wtp->sge_pcie_cmd_req.sop[i]; 3103*7e6ad469SVishal Kulkarni pcie_sge_cmd_rsp_sop += wtp->pcie_sge_cmd_rsp.sop[i]; 3104*7e6ad469SVishal Kulkarni sge_cim_sop += wtp->sge_cim.sop[i]; 3105*7e6ad469SVishal Kulkarni tpcside_csw_sop += (wtp->utx_tpcside_tx.sop[i]); 3106*7e6ad469SVishal Kulkarni sge_work_req_sop += wtp->sge_work_req_pkt.sop[i]; 3107*7e6ad469SVishal Kulkarni 3108*7e6ad469SVishal Kulkarni sge_pcie_cmd_req_eop += wtp->sge_pcie_cmd_req.eop[i]; 3109*7e6ad469SVishal Kulkarni pcie_sge_cmd_rsp_eop += wtp->pcie_sge_cmd_rsp.eop[i]; 3110*7e6ad469SVishal Kulkarni sge_cim_eop += wtp->sge_cim.eop[i]; 3111*7e6ad469SVishal Kulkarni 3112*7e6ad469SVishal Kulkarni } 3113*7e6ad469SVishal Kulkarni 3114*7e6ad469SVishal Kulkarni if (i < 3) { 3115*7e6ad469SVishal Kulkarni pcie_core_cmd_req_sop += wtp->pcie_cmd_stat2.sop[i]; 3116*7e6ad469SVishal Kulkarni core_pcie_cmd_rsp_sop += wtp->pcie_cmd_stat3.sop[i]; 3117*7e6ad469SVishal Kulkarni 3118*7e6ad469SVishal Kulkarni core_pcie_cmd_rsp_eop += wtp->pcie_cmd_stat3.eop[i]; 3119*7e6ad469SVishal Kulkarni pcie_core_cmd_req_eop += wtp->pcie_cmd_stat2.eop[i]; 3120*7e6ad469SVishal Kulkarni } 3121*7e6ad469SVishal Kulkarni 3122*7e6ad469SVishal Kulkarni if (i < 4) { 3123*7e6ad469SVishal Kulkarni /*Rx Path*/ 3124*7e6ad469SVishal Kulkarni pcie_core_dmaw_sop += 3125*7e6ad469SVishal Kulkarni (wtp->pcie_dma1_stat2.sop[i]); 3126*7e6ad469SVishal Kulkarni sge_pcie_sop += 3127*7e6ad469SVishal Kulkarni (wtp->sge_debug_data_high_indx7.sop[i]); 3128*7e6ad469SVishal Kulkarni ulprx_tpcside_sop += (wtp->ulprx_tpcside.sop[i]); 3129*7e6ad469SVishal Kulkarni pmrx_ulprx_sop += (wtp->pmrx_ulprx.sop[i]); 3130*7e6ad469SVishal Kulkarni mps_tpeside_sop += 3131*7e6ad469SVishal Kulkarni (wtp->tp_dbg_eside_pktx.sop[i]); 3132*7e6ad469SVishal Kulkarni rx_xgm_xgm_sop += 3133*7e6ad469SVishal Kulkarni (wtp->mac_porrx_pkt_count.sop[i]); 3134*7e6ad469SVishal Kulkarni wire_xgm_sop += 3135*7e6ad469SVishal Kulkarni (wtp->mac_porrx_aframestra_ok.sop[i]); 3136*7e6ad469SVishal Kulkarni 3137*7e6ad469SVishal Kulkarni pcie_core_dmaw_eop += 3138*7e6ad469SVishal Kulkarni (wtp->pcie_dma1_stat2.eop[i]); 3139*7e6ad469SVishal Kulkarni sge_pcie_eop += (wtp->sge_pcie.eop[i]); 3140*7e6ad469SVishal Kulkarni tpcside_csw_eop += (wtp->tpcside_csw.eop[i]); 3141*7e6ad469SVishal Kulkarni ulprx_tpcside_eop += (wtp->ulprx_tpcside.eop[i]); 3142*7e6ad469SVishal Kulkarni pmrx_ulprx_eop += (wtp->pmrx_ulprx.eop[i]); 3143*7e6ad469SVishal Kulkarni mps_tpeside_eop += (wtp->mps_tpeside.eop[i]); 3144*7e6ad469SVishal Kulkarni rx_xgm_xgm_eop += 3145*7e6ad469SVishal Kulkarni (wtp->mac_porrx_pkt_count.eop[i]); 3146*7e6ad469SVishal Kulkarni wire_xgm_eop += (wtp->xgm_mps.eop[i]); 3147*7e6ad469SVishal Kulkarni 3148*7e6ad469SVishal Kulkarni /*special case type 3:*/ 3149*7e6ad469SVishal Kulkarni mps_tp_sop += (wtp->mps_tp.sop[i]); 3150*7e6ad469SVishal Kulkarni mps_tp_eop += (wtp->mps_tp.eop[i]); 3151*7e6ad469SVishal Kulkarni 3152*7e6ad469SVishal Kulkarni /*Tx Path*/ 3153*7e6ad469SVishal Kulkarni core_pcie_dma_rsp_sop += 3154*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.sop[i]; 3155*7e6ad469SVishal Kulkarni pcie_sge_dma_rsp_sop += wtp->pcie_sge_dma_rsp.sop[i]; 3156*7e6ad469SVishal Kulkarni sge_debug_index6_sop += 3157*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_6.sop[i]; 3158*7e6ad469SVishal Kulkarni sge_utx_sop += wtp->ulp_se_cnt_chx.sop[i]; 3159*7e6ad469SVishal Kulkarni utx_tp_sop += wtp->utx_tp.sop[i]; 3160*7e6ad469SVishal Kulkarni utx_tpcside_sop += wtp->utx_tpcside.sop[i]; 3161*7e6ad469SVishal Kulkarni tpcside_rxarb_sop += wtp->tpcside_rxarb.sop[i]; 3162*7e6ad469SVishal Kulkarni tpeside_mps_sop += wtp->tpeside_mps.sop[i]; 3163*7e6ad469SVishal Kulkarni tx_xgm_xgm_sop += 3164*7e6ad469SVishal Kulkarni wtp->mac_portx_pkt_count.sop[i]; 3165*7e6ad469SVishal Kulkarni xgm_wire_sop += 3166*7e6ad469SVishal Kulkarni wtp->mac_portx_aframestra_ok.sop[i]; 3167*7e6ad469SVishal Kulkarni 3168*7e6ad469SVishal Kulkarni core_pcie_dma_rsp_eop += 3169*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.eop[i]; 3170*7e6ad469SVishal Kulkarni pcie_sge_dma_rsp_eop += wtp->pcie_sge_dma_rsp.eop[i]; 3171*7e6ad469SVishal Kulkarni sge_debug_index6_eop += 3172*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_6.eop[i]; 3173*7e6ad469SVishal Kulkarni sge_utx_eop += wtp->sge_utx.eop[i]; 3174*7e6ad469SVishal Kulkarni utx_tp_eop += wtp->utx_tp.eop[i]; 3175*7e6ad469SVishal Kulkarni utx_tpcside_eop += wtp->utx_tpcside.eop[i]; 3176*7e6ad469SVishal Kulkarni tpcside_rxarb_eop += wtp->tpcside_rxarb.eop[i]; 3177*7e6ad469SVishal Kulkarni tpeside_mps_eop += wtp->tpeside_mps.eop[i]; 3178*7e6ad469SVishal Kulkarni tx_xgm_xgm_eop += 3179*7e6ad469SVishal Kulkarni wtp->mac_portx_pkt_count.eop[i]; 3180*7e6ad469SVishal Kulkarni xgm_wire_eop += 3181*7e6ad469SVishal Kulkarni wtp->mac_portx_aframestra_ok.eop[i]; 3182*7e6ad469SVishal Kulkarni 3183*7e6ad469SVishal Kulkarni /*special case type 3:*/ 3184*7e6ad469SVishal Kulkarni tp_mps_sop += wtp->tp_mps.sop[i]; 3185*7e6ad469SVishal Kulkarni mps_xgm_sop += wtp->mps_xgm.sop[i]; 3186*7e6ad469SVishal Kulkarni 3187*7e6ad469SVishal Kulkarni tp_mps_eop += wtp->tp_mps.eop[i]; 3188*7e6ad469SVishal Kulkarni mps_xgm_eop += wtp->mps_xgm.eop[i]; 3189*7e6ad469SVishal Kulkarni 3190*7e6ad469SVishal Kulkarni pcie_core_dma_req_sop += 3191*7e6ad469SVishal Kulkarni wtp->pcie_dma1_stat2_core.sop[i]; 3192*7e6ad469SVishal Kulkarni sge_pcie_dma_req_sop += 3193*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx5.sop[i]; 3194*7e6ad469SVishal Kulkarni utx_sge_dma_req_sop += wtp->utx_sge_dma_req.sop[i]; 3195*7e6ad469SVishal Kulkarni 3196*7e6ad469SVishal Kulkarni pcie_core_dma_req_eop += 3197*7e6ad469SVishal Kulkarni wtp->pcie_dma1_stat2_core.eop[i]; 3198*7e6ad469SVishal Kulkarni sge_pcie_dma_req_eop += 3199*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx5.eop[i]; 3200*7e6ad469SVishal Kulkarni utx_sge_dma_req_eop += wtp->utx_sge_dma_req.eop[i]; 3201*7e6ad469SVishal Kulkarni } 3202*7e6ad469SVishal Kulkarni 3203*7e6ad469SVishal Kulkarni xgm_mps_sop += (wtp->xgm_mps.sop[i]); 3204*7e6ad469SVishal Kulkarni xgm_mps_eop += (wtp->xgm_mps.eop[i]); 3205*7e6ad469SVishal Kulkarni } 3206*7e6ad469SVishal Kulkarni printf("ifaces = nic0 nic1\n"); 3207*7e6ad469SVishal Kulkarni printf("*************************EGGRESS (TX) PATH **********************************\n"); 3208*7e6ad469SVishal Kulkarni printf("MOD : core---->PCIE---->SGE<-| #Ring Doorbell\n"); 3209*7e6ad469SVishal Kulkarni printf("SOP ? ??? |\n"); 3210*7e6ad469SVishal Kulkarni printf("EOP ? ??? |\n"); 3211*7e6ad469SVishal Kulkarni printf("MOD |<-core<----PCIE<----SGE<-| #Request Work Request\n"); 3212*7e6ad469SVishal Kulkarni printf("SOP_CH0 %02X %02x\n", 3213*7e6ad469SVishal Kulkarni wtp->pcie_cmd_stat2.sop[0], 3214*7e6ad469SVishal Kulkarni wtp->sge_pcie_cmd_req.sop[0]); 3215*7e6ad469SVishal Kulkarni printf("SOP_CH1 %02X %02X\n", 3216*7e6ad469SVishal Kulkarni wtp->pcie_cmd_stat2.sop[1], wtp->sge_pcie_cmd_req.sop[1]); 3217*7e6ad469SVishal Kulkarni printf("SOP_CH2 %02X\n", 3218*7e6ad469SVishal Kulkarni wtp->pcie_cmd_stat2.sop[2]); 3219*7e6ad469SVishal Kulkarni printf("SOP | %02X %02X\n", 3220*7e6ad469SVishal Kulkarni pcie_core_cmd_req_sop, sge_pcie_cmd_req_sop); 3221*7e6ad469SVishal Kulkarni printf("EOP | %2X %2X\n", 3222*7e6ad469SVishal Kulkarni pcie_core_cmd_req_eop, sge_pcie_cmd_req_eop); 3223*7e6ad469SVishal Kulkarni printf("MOD |->core---->PCIE---->SGE------>CIM/uP->| uP<-CIM<-CSW #->Work req. <-Pkts\n"); 3224*7e6ad469SVishal Kulkarni printf("SOP_CH0 %02X %02X %02X"\ 3225*7e6ad469SVishal Kulkarni " | %2X\n", 3226*7e6ad469SVishal Kulkarni wtp->pcie_cmd_stat3.sop[0], wtp->pcie_sge_cmd_rsp.sop[0], 3227*7e6ad469SVishal Kulkarni wtp->sge_cim.sop[0], wtp->sge_work_req_pkt.sop[0]); 3228*7e6ad469SVishal Kulkarni printf("SOP_CH1 %02X %02X %02X"\ 3229*7e6ad469SVishal Kulkarni " | %2X\n", 3230*7e6ad469SVishal Kulkarni wtp->pcie_cmd_stat3.sop[1], wtp->pcie_sge_cmd_rsp.sop[1], 3231*7e6ad469SVishal Kulkarni wtp->sge_cim.sop[1], wtp->sge_work_req_pkt.sop[1]); 3232*7e6ad469SVishal Kulkarni printf("SOP_CH2 %02X "\ 3233*7e6ad469SVishal Kulkarni " |\n", wtp->pcie_cmd_stat3.sop[2]); 3234*7e6ad469SVishal Kulkarni printf("SOP %02X %02X %2X "\ 3235*7e6ad469SVishal Kulkarni " | %2X\n", 3236*7e6ad469SVishal Kulkarni core_pcie_cmd_rsp_sop, pcie_sge_cmd_rsp_sop, 3237*7e6ad469SVishal Kulkarni sge_cim_sop, sge_work_req_sop); 3238*7e6ad469SVishal Kulkarni printf("EOP %2X %2X %2X "\ 3239*7e6ad469SVishal Kulkarni " |\n", 3240*7e6ad469SVishal Kulkarni core_pcie_cmd_rsp_eop, 3241*7e6ad469SVishal Kulkarni pcie_sge_cmd_rsp_eop, sge_cim_eop); 3242*7e6ad469SVishal Kulkarni printf("MOD |<-core<----PCIE<----SGE<------UTX<--------|#data dma requests\n"); 3243*7e6ad469SVishal Kulkarni printf("SOP_CH0 %02X %02X "\ 3244*7e6ad469SVishal Kulkarni "%02X\n", wtp->pcie_dma1_stat2_core.sop[0], 3245*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx5.sop[0], 3246*7e6ad469SVishal Kulkarni wtp->utx_sge_dma_req.sop[0]); 3247*7e6ad469SVishal Kulkarni printf("SOP_CH1 %02X %02X "\ 3248*7e6ad469SVishal Kulkarni "%02X\n", wtp->pcie_dma1_stat2_core.sop[1], 3249*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx5.sop[1], 3250*7e6ad469SVishal Kulkarni wtp->utx_sge_dma_req.sop[1]); 3251*7e6ad469SVishal Kulkarni printf("SOP_CH2 %02X %02X "\ 3252*7e6ad469SVishal Kulkarni "%02X\n", wtp->pcie_dma1_stat2_core.sop[2], 3253*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx5.sop[2], 3254*7e6ad469SVishal Kulkarni wtp->utx_sge_dma_req.sop[2]); 3255*7e6ad469SVishal Kulkarni printf("SOP_CH3 %02X %02X "\ 3256*7e6ad469SVishal Kulkarni "%02X\n", wtp->pcie_dma1_stat2_core.sop[3], 3257*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx5.sop[3], 3258*7e6ad469SVishal Kulkarni wtp->utx_sge_dma_req.sop[3]); 3259*7e6ad469SVishal Kulkarni printf("SOP | %2X %2X %2X\n", 3260*7e6ad469SVishal Kulkarni pcie_core_dma_req_sop/*eop in perl??*/, 3261*7e6ad469SVishal Kulkarni sge_pcie_dma_req_sop, utx_sge_dma_req_sop); 3262*7e6ad469SVishal Kulkarni printf("EOP | %2X %2X %2X\n", 3263*7e6ad469SVishal Kulkarni pcie_core_dma_req_eop, 3264*7e6ad469SVishal Kulkarni sge_pcie_dma_req_eop, utx_sge_dma_req_eop); 3265*7e6ad469SVishal Kulkarni printf("MOD |->core-->PCIE-->SGE-->UTX---->TPC------->TPE---->MPS--->MAC--->wire\n"); 3266*7e6ad469SVishal Kulkarni printf("SOP_CH0 %02X %2X %2X %2X"\ 3267*7e6ad469SVishal Kulkarni " %2X %2X %2X %02X %02X %02X %02X\n", 3268*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.sop[0], 3269*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_6.sop[0], 3270*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_3.sop[0], 3271*7e6ad469SVishal Kulkarni wtp->ulp_se_cnt_chx.sop[0], wtp->utx_tpcside.sop[0], 3272*7e6ad469SVishal Kulkarni wtp->tpcside_rxarb.sop[0], wtp->tpeside_mps.sop[0], 3273*7e6ad469SVishal Kulkarni wtp->tp_mps.sop[0], wtp->mps_xgm.sop[0], 3274*7e6ad469SVishal Kulkarni wtp->mac_portx_pkt_count.sop[0], 3275*7e6ad469SVishal Kulkarni wtp->mac_portx_aframestra_ok.sop[0]); 3276*7e6ad469SVishal Kulkarni 3277*7e6ad469SVishal Kulkarni printf("EOP_CH0 %02X %2X %2X %2X"\ 3278*7e6ad469SVishal Kulkarni " %2X %2X %2X %02X %02X %02X %02X\n", 3279*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.eop[0], 3280*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_6.eop[0], 3281*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_3.eop[0], 3282*7e6ad469SVishal Kulkarni wtp->ulp_se_cnt_chx.eop[0], wtp->utx_tpcside.eop[0], 3283*7e6ad469SVishal Kulkarni wtp->tpcside_rxarb.eop[0], wtp->tpeside_mps.eop[0], 3284*7e6ad469SVishal Kulkarni wtp->tp_mps.eop[0], wtp->mps_xgm.eop[0], 3285*7e6ad469SVishal Kulkarni wtp->mac_portx_pkt_count.eop[0], 3286*7e6ad469SVishal Kulkarni wtp->mac_portx_aframestra_ok.eop[0]); 3287*7e6ad469SVishal Kulkarni printf("SOP_CH1 %02X %2X %2X %2X"\ 3288*7e6ad469SVishal Kulkarni " %2X %2X %2X %02X %02X %02X %02X\n", 3289*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.sop[1], 3290*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_6.sop[1], 3291*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_3.sop[1], 3292*7e6ad469SVishal Kulkarni wtp->ulp_se_cnt_chx.sop[1], wtp->utx_tpcside.sop[1], 3293*7e6ad469SVishal Kulkarni wtp->tpcside_rxarb.sop[1], wtp->tpeside_mps.sop[1], 3294*7e6ad469SVishal Kulkarni wtp->tp_mps.sop[1], wtp->mps_xgm.sop[1], 3295*7e6ad469SVishal Kulkarni wtp->mac_portx_pkt_count.sop[1], 3296*7e6ad469SVishal Kulkarni wtp->mac_portx_aframestra_ok.sop[1]); 3297*7e6ad469SVishal Kulkarni 3298*7e6ad469SVishal Kulkarni printf("EOP_CH1 %02X %2X %2X %2X"\ 3299*7e6ad469SVishal Kulkarni " %2X %2X %2X %02X %02X %02X %02X\n", 3300*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.eop[1], 3301*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_6.eop[1], 3302*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_3.eop[1], 3303*7e6ad469SVishal Kulkarni wtp->ulp_se_cnt_chx.eop[1], wtp->utx_tpcside.eop[1], 3304*7e6ad469SVishal Kulkarni wtp->tpcside_rxarb.eop[1], wtp->tpeside_mps.eop[1], 3305*7e6ad469SVishal Kulkarni wtp->tp_mps.eop[1], wtp->mps_xgm.eop[1], 3306*7e6ad469SVishal Kulkarni wtp->mac_portx_pkt_count.eop[1], 3307*7e6ad469SVishal Kulkarni wtp->mac_portx_aframestra_ok.eop[1]); 3308*7e6ad469SVishal Kulkarni printf("SOP_CH2 %02X %2X %2X %2X"\ 3309*7e6ad469SVishal Kulkarni " %2X %2X %2X %02X %02X %02X %02X\n", 3310*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.sop[2], 3311*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_6.sop[2], 3312*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_3.sop[2], 3313*7e6ad469SVishal Kulkarni wtp->ulp_se_cnt_chx.sop[2], wtp->utx_tpcside.sop[2], 3314*7e6ad469SVishal Kulkarni wtp->tpcside_rxarb.sop[2], wtp->tpeside_mps.sop[2], 3315*7e6ad469SVishal Kulkarni wtp->tp_mps.sop[2], wtp->mps_xgm.sop[2], 3316*7e6ad469SVishal Kulkarni wtp->mac_portx_pkt_count.sop[2], 3317*7e6ad469SVishal Kulkarni wtp->mac_portx_aframestra_ok.sop[2]); 3318*7e6ad469SVishal Kulkarni 3319*7e6ad469SVishal Kulkarni printf("EOP_CH2 %02X %2X %2X %2X"\ 3320*7e6ad469SVishal Kulkarni " %2X %2X %2X %02X %02X %02X %02X\n", 3321*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.eop[2], 3322*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_6.eop[2], 3323*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_3.eop[2], 3324*7e6ad469SVishal Kulkarni wtp->ulp_se_cnt_chx.eop[2], wtp->utx_tpcside.eop[2], 3325*7e6ad469SVishal Kulkarni wtp->tpcside_rxarb.eop[2], wtp->tpeside_mps.eop[2], 3326*7e6ad469SVishal Kulkarni wtp->tp_mps.eop[2], wtp->mps_xgm.eop[2], 3327*7e6ad469SVishal Kulkarni wtp->mac_portx_pkt_count.eop[2], 3328*7e6ad469SVishal Kulkarni wtp->mac_portx_aframestra_ok.eop[2]); 3329*7e6ad469SVishal Kulkarni printf("SOP_CH3 %02X %2X %2X %2X"\ 3330*7e6ad469SVishal Kulkarni " %2X %2X %2X %02X %02X %02X %02X\n", 3331*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.sop[3], 3332*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_6.sop[3], 3333*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_3.sop[3], 3334*7e6ad469SVishal Kulkarni wtp->ulp_se_cnt_chx.sop[3], wtp->utx_tpcside.sop[3], 3335*7e6ad469SVishal Kulkarni wtp->tpcside_rxarb.sop[3], wtp->tpeside_mps.sop[3], 3336*7e6ad469SVishal Kulkarni wtp->tp_mps.sop[3], wtp->mps_xgm.sop[3], 3337*7e6ad469SVishal Kulkarni wtp->mac_portx_pkt_count.sop[3], 3338*7e6ad469SVishal Kulkarni wtp->mac_portx_aframestra_ok.sop[3]); 3339*7e6ad469SVishal Kulkarni 3340*7e6ad469SVishal Kulkarni printf("EOP_CH3 %02X %2X %2X %2X"\ 3341*7e6ad469SVishal Kulkarni " %2X %2X %2X %02X %02X %02X %02X\n", 3342*7e6ad469SVishal Kulkarni wtp->pcie_t5_dma_stat3.eop[3], 3343*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_6.eop[3], 3344*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_index_3.eop[3], 3345*7e6ad469SVishal Kulkarni wtp->ulp_se_cnt_chx.eop[3], wtp->utx_tpcside.eop[3], 3346*7e6ad469SVishal Kulkarni wtp->tpcside_rxarb.eop[3], wtp->tpeside_mps.eop[3], 3347*7e6ad469SVishal Kulkarni wtp->tp_mps.eop[3], wtp->mps_xgm.eop[3], 3348*7e6ad469SVishal Kulkarni wtp->mac_portx_pkt_count.eop[3], 3349*7e6ad469SVishal Kulkarni wtp->mac_portx_aframestra_ok.eop[3]); 3350*7e6ad469SVishal Kulkarni printf("SOP %2X %2X %2X %2X "\ 3351*7e6ad469SVishal Kulkarni " %2X %2X %2X %2X %2X %2X %2X\n", 3352*7e6ad469SVishal Kulkarni core_pcie_dma_rsp_sop, sge_debug_index6_sop, 3353*7e6ad469SVishal Kulkarni pcie_sge_dma_rsp_sop, sge_utx_sop, utx_tp_sop, 3354*7e6ad469SVishal Kulkarni tpcside_rxarb_sop, tpeside_mps_sop, tp_mps_sop, 3355*7e6ad469SVishal Kulkarni mps_xgm_sop, tx_xgm_xgm_sop, xgm_wire_sop); 3356*7e6ad469SVishal Kulkarni printf("EOP %2X %2X %2X %2X "\ 3357*7e6ad469SVishal Kulkarni " %2X %2X %2X %2X %2X %2X %2X\n", 3358*7e6ad469SVishal Kulkarni core_pcie_dma_rsp_eop, sge_debug_index6_eop, 3359*7e6ad469SVishal Kulkarni pcie_sge_dma_rsp_eop, sge_utx_eop, utx_tp_eop, 3360*7e6ad469SVishal Kulkarni tpcside_rxarb_eop, tpeside_mps_eop, tp_mps_eop, 3361*7e6ad469SVishal Kulkarni mps_xgm_eop, tx_xgm_xgm_eop, xgm_wire_eop); 3362*7e6ad469SVishal Kulkarni printf("*************************INGRESS (RX) PATH **********************************\n"); 3363*7e6ad469SVishal Kulkarni 3364*7e6ad469SVishal Kulkarni printf("MOD core<-PCIE<---SGE<--CSW<-----TPC<-URX<-LE-TPE<-----MPS<--MAC<---wire\n"); 3365*7e6ad469SVishal Kulkarni 3366*7e6ad469SVishal Kulkarni printf("SOP_CH0 %2X %2X %2X %2X"\ 3367*7e6ad469SVishal Kulkarni " %2X %2X %2X %2X %2X %2X %02X %02X "\ 3368*7e6ad469SVishal Kulkarni "%02X\n", 3369*7e6ad469SVishal Kulkarni wtp->pcie_dma1_stat2.sop[0], 3370*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx7.sop[0], 3371*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx1.sop[0], 3372*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx9.sop[0], 3373*7e6ad469SVishal Kulkarni wtp->utx_tpcside_tx.sop[0], wtp->ulprx_tpcside.sop[0], 3374*7e6ad469SVishal Kulkarni wtp->pmrx_ulprx.sop[0], wtp->le_db_rsp_cnt.sop, 3375*7e6ad469SVishal Kulkarni wtp->tp_dbg_eside_pktx.sop[0], wtp->mps_tp.sop[0], 3376*7e6ad469SVishal Kulkarni wtp->xgm_mps.sop[0], wtp->mac_porrx_pkt_count.sop[0], 3377*7e6ad469SVishal Kulkarni wtp->mac_porrx_aframestra_ok.sop[0]); 3378*7e6ad469SVishal Kulkarni 3379*7e6ad469SVishal Kulkarni printf("EOP_CH0 %2X %2X %2X "\ 3380*7e6ad469SVishal Kulkarni "%2X %2X %2X %2X %2X %2X %2X %02X %02X "\ 3381*7e6ad469SVishal Kulkarni " %02X\n", 3382*7e6ad469SVishal Kulkarni wtp->pcie_dma1_stat2.eop[0], 3383*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx7.eop[0], 3384*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx1.eop[0], 3385*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx9.eop[0], 3386*7e6ad469SVishal Kulkarni wtp->utx_tpcside_tx.eop[0], wtp->ulprx_tpcside.eop[0], 3387*7e6ad469SVishal Kulkarni wtp->pmrx_ulprx.eop[0], wtp->le_db_rsp_cnt.eop, 3388*7e6ad469SVishal Kulkarni wtp->tp_dbg_eside_pktx.eop[0], wtp->mps_tp.eop[0], 3389*7e6ad469SVishal Kulkarni wtp->xgm_mps.eop[0], wtp->mac_porrx_pkt_count.eop[0], 3390*7e6ad469SVishal Kulkarni wtp->mac_porrx_aframestra_ok.eop[0]); 3391*7e6ad469SVishal Kulkarni printf("SOP_CH1 %2X %2X %2X "\ 3392*7e6ad469SVishal Kulkarni "%2X %2X %2X %2X %2X %2X %02X %02X "\ 3393*7e6ad469SVishal Kulkarni " %02X\n", 3394*7e6ad469SVishal Kulkarni wtp->pcie_dma1_stat2.sop[1], 3395*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx7.sop[1], 3396*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx1.sop[1], 3397*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx9.sop[1], 3398*7e6ad469SVishal Kulkarni wtp->utx_tpcside_tx.sop[1], wtp->ulprx_tpcside.sop[1], 3399*7e6ad469SVishal Kulkarni wtp->pmrx_ulprx.sop[1], wtp->tp_dbg_eside_pktx.sop[1], 3400*7e6ad469SVishal Kulkarni wtp->mps_tp.sop[1], wtp->xgm_mps.sop[1], 3401*7e6ad469SVishal Kulkarni wtp->mac_porrx_pkt_count.sop[1], 3402*7e6ad469SVishal Kulkarni wtp->mac_porrx_aframestra_ok.sop[1]); 3403*7e6ad469SVishal Kulkarni 3404*7e6ad469SVishal Kulkarni printf("EOP_CH1 %2X %2X %2X "\ 3405*7e6ad469SVishal Kulkarni "%2X %2X %2X %2X %2X %2X %02X %02X "\ 3406*7e6ad469SVishal Kulkarni " %02X\n", 3407*7e6ad469SVishal Kulkarni wtp->pcie_dma1_stat2.eop[1], 3408*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx7.eop[1], 3409*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx1.eop[1], 3410*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx9.eop[1], 3411*7e6ad469SVishal Kulkarni wtp->utx_tpcside_tx.eop[1], wtp->ulprx_tpcside.eop[1], 3412*7e6ad469SVishal Kulkarni wtp->pmrx_ulprx.eop[1], wtp->tp_dbg_eside_pktx.eop[1], 3413*7e6ad469SVishal Kulkarni wtp->mps_tp.eop[1], wtp->xgm_mps.eop[1], 3414*7e6ad469SVishal Kulkarni wtp->mac_porrx_pkt_count.eop[1], 3415*7e6ad469SVishal Kulkarni wtp->mac_porrx_aframestra_ok.eop[1]); 3416*7e6ad469SVishal Kulkarni printf("SOP_CH2 %2X %2X "\ 3417*7e6ad469SVishal Kulkarni " %2X %2X %02X %02X %02X\n", 3418*7e6ad469SVishal Kulkarni wtp->pcie_dma1_stat2.sop[2], 3419*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx7.sop[2], 3420*7e6ad469SVishal Kulkarni wtp->tp_dbg_eside_pktx.sop[2], wtp->mps_tp.sop[2], 3421*7e6ad469SVishal Kulkarni wtp->xgm_mps.sop[2], wtp->mac_porrx_pkt_count.sop[2], 3422*7e6ad469SVishal Kulkarni wtp->mac_porrx_aframestra_ok.sop[2]); 3423*7e6ad469SVishal Kulkarni 3424*7e6ad469SVishal Kulkarni printf("EOP_CH2 %2X %2X "\ 3425*7e6ad469SVishal Kulkarni " %2X %2X %02X %02X %02X\n", 3426*7e6ad469SVishal Kulkarni wtp->pcie_dma1_stat2.eop[2], 3427*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx7.eop[2], 3428*7e6ad469SVishal Kulkarni wtp->tp_dbg_eside_pktx.eop[2], wtp->mps_tp.eop[2], 3429*7e6ad469SVishal Kulkarni wtp->xgm_mps.eop[2], wtp->mac_porrx_pkt_count.eop[2], 3430*7e6ad469SVishal Kulkarni wtp->mac_porrx_aframestra_ok.eop[2]); 3431*7e6ad469SVishal Kulkarni printf("SOP_CH3 %2X %2X "\ 3432*7e6ad469SVishal Kulkarni " %2X %2X %02X %02X %02X\n", 3433*7e6ad469SVishal Kulkarni wtp->pcie_dma1_stat2.sop[3], 3434*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx7.sop[3], 3435*7e6ad469SVishal Kulkarni wtp->tp_dbg_eside_pktx.sop[3], wtp->mps_tp.sop[3], 3436*7e6ad469SVishal Kulkarni wtp->xgm_mps.sop[3], wtp->mac_porrx_pkt_count.sop[3], 3437*7e6ad469SVishal Kulkarni wtp->mac_porrx_aframestra_ok.sop[3]); 3438*7e6ad469SVishal Kulkarni 3439*7e6ad469SVishal Kulkarni printf("EOP_CH3 %2X %2X "\ 3440*7e6ad469SVishal Kulkarni " %2X %2X %02X %02X %02X\n", 3441*7e6ad469SVishal Kulkarni wtp->pcie_dma1_stat2.eop[3], 3442*7e6ad469SVishal Kulkarni wtp->sge_debug_data_high_indx7.eop[3], 3443*7e6ad469SVishal Kulkarni wtp->tp_dbg_eside_pktx.eop[3], wtp->mps_tp.eop[3], 3444*7e6ad469SVishal Kulkarni wtp->xgm_mps.eop[3], wtp->mac_porrx_pkt_count.eop[3], 3445*7e6ad469SVishal Kulkarni wtp->mac_porrx_aframestra_ok.eop[3]); 3446*7e6ad469SVishal Kulkarni printf("SOP_CH4 "\ 3447*7e6ad469SVishal Kulkarni " %02X\n", 3448*7e6ad469SVishal Kulkarni wtp->xgm_mps.sop[4]); 3449*7e6ad469SVishal Kulkarni printf("EOP_CH4 "\ 3450*7e6ad469SVishal Kulkarni " %02X\n", 3451*7e6ad469SVishal Kulkarni wtp->xgm_mps.eop[4]); 3452*7e6ad469SVishal Kulkarni printf("SOP_CH5 "\ 3453*7e6ad469SVishal Kulkarni " %02X\n", 3454*7e6ad469SVishal Kulkarni wtp->xgm_mps.sop[5]); 3455*7e6ad469SVishal Kulkarni printf("EOP_CH5 "\ 3456*7e6ad469SVishal Kulkarni " %02X\n", 3457*7e6ad469SVishal Kulkarni wtp->xgm_mps.eop[5]); 3458*7e6ad469SVishal Kulkarni printf("SOP_CH6 "\ 3459*7e6ad469SVishal Kulkarni " %02X\n", 3460*7e6ad469SVishal Kulkarni wtp->xgm_mps.sop[6]); 3461*7e6ad469SVishal Kulkarni printf("EOP_CH6 "\ 3462*7e6ad469SVishal Kulkarni " %02X\n", 3463*7e6ad469SVishal Kulkarni wtp->xgm_mps.eop[6]); 3464*7e6ad469SVishal Kulkarni printf("SOP_CH7 "\ 3465*7e6ad469SVishal Kulkarni " %02X\n", 3466*7e6ad469SVishal Kulkarni wtp->xgm_mps.sop[7]); 3467*7e6ad469SVishal Kulkarni printf("EOP_CH7 "\ 3468*7e6ad469SVishal Kulkarni " %02X\n", 3469*7e6ad469SVishal Kulkarni wtp->xgm_mps.eop[7]); 3470*7e6ad469SVishal Kulkarni 3471*7e6ad469SVishal Kulkarni printf("SOP %2X %2X %2X "\ 3472*7e6ad469SVishal Kulkarni "%2X %2X %2X %2X %2X %2X %2X %2X %2X\n", 3473*7e6ad469SVishal Kulkarni pcie_core_dmaw_sop, sge_pcie_sop, csw_sge_sop, 3474*7e6ad469SVishal Kulkarni tp_csw_sop, tpcside_csw_sop, ulprx_tpcside_sop, 3475*7e6ad469SVishal Kulkarni pmrx_ulprx_sop, mps_tpeside_sop, mps_tp_sop, 3476*7e6ad469SVishal Kulkarni xgm_mps_sop, rx_xgm_xgm_sop, wire_xgm_sop); 3477*7e6ad469SVishal Kulkarni printf("EOP %2X %2X %2X "\ 3478*7e6ad469SVishal Kulkarni "%2X %2X %2X %2X %2X %2X %2X %2X %2X\n", 3479*7e6ad469SVishal Kulkarni pcie_core_dmaw_eop, sge_pcie_eop, 3480*7e6ad469SVishal Kulkarni csw_sge_eop, tp_csw_eop, 3481*7e6ad469SVishal Kulkarni tpcside_csw_eop, ulprx_tpcside_eop, 3482*7e6ad469SVishal Kulkarni pmrx_ulprx_eop, mps_tpeside_eop, 3483*7e6ad469SVishal Kulkarni mps_tp_eop, xgm_mps_eop, rx_xgm_xgm_eop, 3484*7e6ad469SVishal Kulkarni wire_xgm_eop); 3485*7e6ad469SVishal Kulkarni printf("DROP: ??? ??? ??? "\ 3486*7e6ad469SVishal Kulkarni "%2X(mib) %2X(err) %2X(oflow) %X(cls)\n", 3487*7e6ad469SVishal Kulkarni (wtp->mps_tp.drops & 0xFF), 3488*7e6ad469SVishal Kulkarni (wtp->xgm_mps.err & 0xFF), 3489*7e6ad469SVishal Kulkarni (wtp->xgm_mps.drop & 0xFF), 3490*7e6ad469SVishal Kulkarni (wtp->xgm_mps.cls_drop & 0xFF)); 3491*7e6ad469SVishal Kulkarni printf("INTS: "); 3492*7e6ad469SVishal Kulkarni for (i = 0; i < 4; i++) { 3493*7e6ad469SVishal Kulkarni printf("%2X<- %2X ", 3494*7e6ad469SVishal Kulkarni (wtp->pcie_core_dmai.sop[i] & 0xF), 3495*7e6ad469SVishal Kulkarni (wtp->sge_pcie_ints.sop[i] & 0xF)); 3496*7e6ad469SVishal Kulkarni } 3497*7e6ad469SVishal Kulkarni printf("(PCIE<-SGE, channels 0 to 3)\n"); 3498*7e6ad469SVishal Kulkarni 3499*7e6ad469SVishal Kulkarni return rc; 3500*7e6ad469SVishal Kulkarni } 3501*7e6ad469SVishal Kulkarni 3502*7e6ad469SVishal Kulkarni int 3503*7e6ad469SVishal Kulkarni view_wtp(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 3504*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 3505*7e6ad469SVishal Kulkarni { 3506*7e6ad469SVishal Kulkarni int rc = -1; 3507*7e6ad469SVishal Kulkarni 3508*7e6ad469SVishal Kulkarni if (is_t5(chip)) 3509*7e6ad469SVishal Kulkarni rc = t5_view_wtp(pbuf, entity_hdr, cudbg_poutbuf); 3510*7e6ad469SVishal Kulkarni else if (is_t6(chip)) 3511*7e6ad469SVishal Kulkarni rc = t6_view_wtp(pbuf, entity_hdr, cudbg_poutbuf); 3512*7e6ad469SVishal Kulkarni 3513*7e6ad469SVishal Kulkarni return rc; 3514*7e6ad469SVishal Kulkarni } 3515*7e6ad469SVishal Kulkarni 3516*7e6ad469SVishal Kulkarni /* 3517*7e6ad469SVishal Kulkarni * * Small utility function to return the strings "yes" or "no" if the 3518*7e6ad469SVishal Kulkarni * supplied 3519*7e6ad469SVishal Kulkarni * * argument is non-zero. 3520*7e6ad469SVishal Kulkarni * */ 3521*7e6ad469SVishal Kulkarni static const char * 3522*7e6ad469SVishal Kulkarni yesno(int x) 3523*7e6ad469SVishal Kulkarni { 3524*7e6ad469SVishal Kulkarni static const char *yes = "yes"; 3525*7e6ad469SVishal Kulkarni static const char *no = "no"; 3526*7e6ad469SVishal Kulkarni 3527*7e6ad469SVishal Kulkarni return x ? yes : no; 3528*7e6ad469SVishal Kulkarni } 3529*7e6ad469SVishal Kulkarni 3530*7e6ad469SVishal Kulkarni static int 3531*7e6ad469SVishal Kulkarni dump_indirect_regs(const struct cudbg_reg_info *reg_array, 3532*7e6ad469SVishal Kulkarni u32 indirect_addr, const u32 *regs, 3533*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf) 3534*7e6ad469SVishal Kulkarni { 3535*7e6ad469SVishal Kulkarni uint32_t reg_val = 0; /* silence compiler warning*/ 3536*7e6ad469SVishal Kulkarni int i, rc; 3537*7e6ad469SVishal Kulkarni 3538*7e6ad469SVishal Kulkarni for (i = 0 ; reg_array->name; ++reg_array) { 3539*7e6ad469SVishal Kulkarni if (!reg_array->len) { 3540*7e6ad469SVishal Kulkarni reg_val = regs[i]; 3541*7e6ad469SVishal Kulkarni i++; 3542*7e6ad469SVishal Kulkarni printf("[0x%05x:0x%05x] "\ 3543*7e6ad469SVishal Kulkarni "%-47s %#-14x %u\n", 3544*7e6ad469SVishal Kulkarni indirect_addr, reg_array->addr, 3545*7e6ad469SVishal Kulkarni reg_array->name, reg_val, reg_val); 3546*7e6ad469SVishal Kulkarni } else { 3547*7e6ad469SVishal Kulkarni uint32_t v = xtract(reg_val, reg_array->addr, 3548*7e6ad469SVishal Kulkarni reg_array->len); 3549*7e6ad469SVishal Kulkarni printf(" %*u:%u %-55s "\ 3550*7e6ad469SVishal Kulkarni "%#-14x %u\n", 3551*7e6ad469SVishal Kulkarni reg_array->addr < 10 ? 3 : 2, 3552*7e6ad469SVishal Kulkarni reg_array->addr + reg_array->len - 1, 3553*7e6ad469SVishal Kulkarni reg_array->addr, reg_array->name, v, v); 3554*7e6ad469SVishal Kulkarni } 3555*7e6ad469SVishal Kulkarni } 3556*7e6ad469SVishal Kulkarni 3557*7e6ad469SVishal Kulkarni return 1; 3558*7e6ad469SVishal Kulkarni 3559*7e6ad469SVishal Kulkarni return rc; 3560*7e6ad469SVishal Kulkarni } 3561*7e6ad469SVishal Kulkarni 3562*7e6ad469SVishal Kulkarni int 3563*7e6ad469SVishal Kulkarni view_cctrl(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 3564*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 3565*7e6ad469SVishal Kulkarni { 3566*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 3567*7e6ad469SVishal Kulkarni u16 (*incr)[NCCTRL_WIN]; 3568*7e6ad469SVishal Kulkarni int rc = 0; 3569*7e6ad469SVishal Kulkarni u32 i = 0; 3570*7e6ad469SVishal Kulkarni 3571*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 3572*7e6ad469SVishal Kulkarni if (rc) 3573*7e6ad469SVishal Kulkarni return rc; 3574*7e6ad469SVishal Kulkarni 3575*7e6ad469SVishal Kulkarni incr = (void *)dc_buff.data; 3576*7e6ad469SVishal Kulkarni for (i = 0; i < NCCTRL_WIN; i++) { 3577*7e6ad469SVishal Kulkarni printf("%2d: %4u %4u %4u %4u %4u "\ 3578*7e6ad469SVishal Kulkarni "%4u %4u %4u\n", i, 3579*7e6ad469SVishal Kulkarni incr[0][i], incr[1][i], incr[2][i], incr[3][i], 3580*7e6ad469SVishal Kulkarni incr[4][i], incr[5][i], incr[6][i], incr[7][i]); 3581*7e6ad469SVishal Kulkarni printf("%8u %4u %4u %4u %4u %4u %4u"\ 3582*7e6ad469SVishal Kulkarni " %4u\n", incr[8][i], incr[9][i], incr[10][i], 3583*7e6ad469SVishal Kulkarni incr[11][i], incr[12][i], incr[13][i], 3584*7e6ad469SVishal Kulkarni incr[14][i], incr[15][i]); 3585*7e6ad469SVishal Kulkarni } 3586*7e6ad469SVishal Kulkarni 3587*7e6ad469SVishal Kulkarni return rc; 3588*7e6ad469SVishal Kulkarni } 3589*7e6ad469SVishal Kulkarni 3590*7e6ad469SVishal Kulkarni int 3591*7e6ad469SVishal Kulkarni view_up_cim_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 3592*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, 3593*7e6ad469SVishal Kulkarni enum chip_type chip) 3594*7e6ad469SVishal Kulkarni { 3595*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 3596*7e6ad469SVishal Kulkarni struct ireg_buf *up_cim_indr; 3597*7e6ad469SVishal Kulkarni u32 indirect_addr; 3598*7e6ad469SVishal Kulkarni int rc = 0; 3599*7e6ad469SVishal Kulkarni int i = 0; 3600*7e6ad469SVishal Kulkarni int n = 0; 3601*7e6ad469SVishal Kulkarni 3602*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 3603*7e6ad469SVishal Kulkarni if (rc) 3604*7e6ad469SVishal Kulkarni return rc; 3605*7e6ad469SVishal Kulkarni 3606*7e6ad469SVishal Kulkarni indirect_addr = A_CIM_HOST_ACC_CTRL; 3607*7e6ad469SVishal Kulkarni up_cim_indr = (struct ireg_buf *)dc_buff.data; 3608*7e6ad469SVishal Kulkarni if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5) 3609*7e6ad469SVishal Kulkarni n = sizeof(t5_up_cim_reg_array) / (5 * sizeof(u32)); 3610*7e6ad469SVishal Kulkarni else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6) 3611*7e6ad469SVishal Kulkarni n = sizeof(t6_up_cim_reg_array) / (5 * sizeof(u32)); 3612*7e6ad469SVishal Kulkarni 3613*7e6ad469SVishal Kulkarni for (i = 0; i < n; i++) { 3614*7e6ad469SVishal Kulkarni u32 *buff = up_cim_indr->outbuf; 3615*7e6ad469SVishal Kulkarni 3616*7e6ad469SVishal Kulkarni if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5) 3617*7e6ad469SVishal Kulkarni rc = dump_indirect_regs(t5_up_cim_reg_ptr[i], 3618*7e6ad469SVishal Kulkarni indirect_addr, 3619*7e6ad469SVishal Kulkarni (const u32 *)buff, 3620*7e6ad469SVishal Kulkarni cudbg_poutbuf); 3621*7e6ad469SVishal Kulkarni else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6) 3622*7e6ad469SVishal Kulkarni rc = dump_indirect_regs(t6_up_cim_reg_ptr[i], 3623*7e6ad469SVishal Kulkarni indirect_addr, 3624*7e6ad469SVishal Kulkarni (const u32 *)buff, 3625*7e6ad469SVishal Kulkarni cudbg_poutbuf); 3626*7e6ad469SVishal Kulkarni 3627*7e6ad469SVishal Kulkarni if (rc < 0) 3628*7e6ad469SVishal Kulkarni goto err1; 3629*7e6ad469SVishal Kulkarni up_cim_indr++; 3630*7e6ad469SVishal Kulkarni 3631*7e6ad469SVishal Kulkarni /* Prohibit accessing data beyond entity size. This helps 3632*7e6ad469SVishal Kulkarni * new app and old dump compatibily scenario 3633*7e6ad469SVishal Kulkarni */ 3634*7e6ad469SVishal Kulkarni if ((char *)up_cim_indr >= (dc_buff.data + dc_buff.size)) 3635*7e6ad469SVishal Kulkarni break; 3636*7e6ad469SVishal Kulkarni } 3637*7e6ad469SVishal Kulkarni 3638*7e6ad469SVishal Kulkarni err1: 3639*7e6ad469SVishal Kulkarni return rc; 3640*7e6ad469SVishal Kulkarni } 3641*7e6ad469SVishal Kulkarni 3642*7e6ad469SVishal Kulkarni static int 3643*7e6ad469SVishal Kulkarni print_pbt_addr_entry(struct cudbg_buffer *cudbg_poutbuf, u32 val) 3644*7e6ad469SVishal Kulkarni { 3645*7e6ad469SVishal Kulkarni char *fmts = "\n [%2u:%2u] %-10s "; 3646*7e6ad469SVishal Kulkarni u32 vld, alloc, pending, address; 3647*7e6ad469SVishal Kulkarni int rc = 0; 3648*7e6ad469SVishal Kulkarni 3649*7e6ad469SVishal Kulkarni vld = (val >> 28) & 1; 3650*7e6ad469SVishal Kulkarni printf(fmts, 28, 28, "vld"); 3651*7e6ad469SVishal Kulkarni printf("%d", vld); 3652*7e6ad469SVishal Kulkarni 3653*7e6ad469SVishal Kulkarni alloc = (val >> 27) & 1; 3654*7e6ad469SVishal Kulkarni printf(fmts, 27, 27, "alloc"); 3655*7e6ad469SVishal Kulkarni printf("%d", alloc); 3656*7e6ad469SVishal Kulkarni 3657*7e6ad469SVishal Kulkarni pending = (val >> 26) & 1; 3658*7e6ad469SVishal Kulkarni printf(fmts, 26, 26, "pending"); 3659*7e6ad469SVishal Kulkarni printf("%d", pending); 3660*7e6ad469SVishal Kulkarni 3661*7e6ad469SVishal Kulkarni address = val & 0x1FFFFFF; 3662*7e6ad469SVishal Kulkarni printf(fmts, 25, 0, "address<<6"); 3663*7e6ad469SVishal Kulkarni printf("0x%08x", address<<6); 3664*7e6ad469SVishal Kulkarni printf("\n"); 3665*7e6ad469SVishal Kulkarni 3666*7e6ad469SVishal Kulkarni 3667*7e6ad469SVishal Kulkarni return rc; 3668*7e6ad469SVishal Kulkarni } 3669*7e6ad469SVishal Kulkarni 3670*7e6ad469SVishal Kulkarni int 3671*7e6ad469SVishal Kulkarni view_mbox_log(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 3672*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 3673*7e6ad469SVishal Kulkarni { 3674*7e6ad469SVishal Kulkarni struct cudbg_mbox_log *mboxlog = NULL; 3675*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 3676*7e6ad469SVishal Kulkarni u16 mbox_cmds; 3677*7e6ad469SVishal Kulkarni int rc, i, k; 3678*7e6ad469SVishal Kulkarni 3679*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 3680*7e6ad469SVishal Kulkarni if (rc) 3681*7e6ad469SVishal Kulkarni return rc; 3682*7e6ad469SVishal Kulkarni 3683*7e6ad469SVishal Kulkarni mbox_cmds = (u16)dc_buff.size / sizeof(struct cudbg_mbox_log); 3684*7e6ad469SVishal Kulkarni mboxlog = (struct cudbg_mbox_log *)dc_buff.data; 3685*7e6ad469SVishal Kulkarni printf( 3686*7e6ad469SVishal Kulkarni "%10s %15s %5s %5s %s\n", "Seq", "Tstamp", "Atime", 3687*7e6ad469SVishal Kulkarni "Etime", "Command/Reply"); 3688*7e6ad469SVishal Kulkarni 3689*7e6ad469SVishal Kulkarni for (i = 0; i < mbox_cmds && mboxlog->entry.timestamp; i++) { 3690*7e6ad469SVishal Kulkarni printf("%10u %15llu %5d %5d", 3691*7e6ad469SVishal Kulkarni mboxlog->entry.seqno, mboxlog->entry.timestamp, 3692*7e6ad469SVishal Kulkarni mboxlog->entry.access, mboxlog->entry.execute); 3693*7e6ad469SVishal Kulkarni 3694*7e6ad469SVishal Kulkarni for (k = 0; k < MBOX_LEN / 8; k++) 3695*7e6ad469SVishal Kulkarni printf(" %08x %08x", 3696*7e6ad469SVishal Kulkarni mboxlog->hi[k], mboxlog->lo[k]); 3697*7e6ad469SVishal Kulkarni 3698*7e6ad469SVishal Kulkarni printf("\n"); 3699*7e6ad469SVishal Kulkarni mboxlog++; 3700*7e6ad469SVishal Kulkarni } 3701*7e6ad469SVishal Kulkarni 3702*7e6ad469SVishal Kulkarni return rc; 3703*7e6ad469SVishal Kulkarni } 3704*7e6ad469SVishal Kulkarni 3705*7e6ad469SVishal Kulkarni int 3706*7e6ad469SVishal Kulkarni view_pbt_tables(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 3707*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 3708*7e6ad469SVishal Kulkarni { 3709*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 3710*7e6ad469SVishal Kulkarni struct cudbg_pbt_tables *pbt; 3711*7e6ad469SVishal Kulkarni int rc = 0; 3712*7e6ad469SVishal Kulkarni int i = 0; 3713*7e6ad469SVishal Kulkarni u32 addr; 3714*7e6ad469SVishal Kulkarni 3715*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 3716*7e6ad469SVishal Kulkarni if (rc) 3717*7e6ad469SVishal Kulkarni return rc; 3718*7e6ad469SVishal Kulkarni 3719*7e6ad469SVishal Kulkarni pbt = (struct cudbg_pbt_tables *)dc_buff.data; 3720*7e6ad469SVishal Kulkarni /* PBT dynamic entries */ 3721*7e6ad469SVishal Kulkarni addr = CUDBG_CHAC_PBT_ADDR; 3722*7e6ad469SVishal Kulkarni for (i = 0; i < CUDBG_PBT_DYNAMIC_ENTRIES; i++) { 3723*7e6ad469SVishal Kulkarni printf("Dynamic "); 3724*7e6ad469SVishal Kulkarni printf("Addr Table [0x%03x]: 0x%08x", 3725*7e6ad469SVishal Kulkarni (addr + (i * 4) - CUDBG_CHAC_PBT_ADDR), 3726*7e6ad469SVishal Kulkarni pbt->pbt_dynamic[i]); 3727*7e6ad469SVishal Kulkarni rc = print_pbt_addr_entry(cudbg_poutbuf, pbt->pbt_dynamic[i]); 3728*7e6ad469SVishal Kulkarni if (rc < 0) 3729*7e6ad469SVishal Kulkarni goto err1; 3730*7e6ad469SVishal Kulkarni } 3731*7e6ad469SVishal Kulkarni 3732*7e6ad469SVishal Kulkarni /* PBT static entries */ 3733*7e6ad469SVishal Kulkarni addr = CUDBG_CHAC_PBT_ADDR + (1 << 6); 3734*7e6ad469SVishal Kulkarni for (i = 0; i < CUDBG_PBT_STATIC_ENTRIES; i++) { 3735*7e6ad469SVishal Kulkarni printf("Static "); 3736*7e6ad469SVishal Kulkarni printf("Addr Table [0x%03x]: 0x%08x", 3737*7e6ad469SVishal Kulkarni (addr + (i * 4) - CUDBG_CHAC_PBT_ADDR), 3738*7e6ad469SVishal Kulkarni pbt->pbt_static[i]); 3739*7e6ad469SVishal Kulkarni rc = print_pbt_addr_entry(cudbg_poutbuf, pbt->pbt_static[i]); 3740*7e6ad469SVishal Kulkarni if (rc < 0) 3741*7e6ad469SVishal Kulkarni goto err1; 3742*7e6ad469SVishal Kulkarni } 3743*7e6ad469SVishal Kulkarni 3744*7e6ad469SVishal Kulkarni /* PBT lrf entries */ 3745*7e6ad469SVishal Kulkarni addr = CUDBG_CHAC_PBT_LRF; 3746*7e6ad469SVishal Kulkarni for (i = 0; i < CUDBG_LRF_ENTRIES; i++) { 3747*7e6ad469SVishal Kulkarni printf( 3748*7e6ad469SVishal Kulkarni "LRF Table [0x%03x]: 0x%08x\n", 3749*7e6ad469SVishal Kulkarni (addr + (i * 4) - CUDBG_CHAC_PBT_LRF), 3750*7e6ad469SVishal Kulkarni pbt->lrf_table[i]); 3751*7e6ad469SVishal Kulkarni } 3752*7e6ad469SVishal Kulkarni 3753*7e6ad469SVishal Kulkarni /* PBT data entries */ 3754*7e6ad469SVishal Kulkarni addr = CUDBG_CHAC_PBT_DATA; 3755*7e6ad469SVishal Kulkarni for (i = 0; i < CUDBG_PBT_DATA_ENTRIES; i++) { 3756*7e6ad469SVishal Kulkarni printf( 3757*7e6ad469SVishal Kulkarni "DATA Table [0x%03x]: 0x%08x\n", 3758*7e6ad469SVishal Kulkarni (addr + (i * 4) - CUDBG_CHAC_PBT_DATA), 3759*7e6ad469SVishal Kulkarni pbt->pbt_data[i]); 3760*7e6ad469SVishal Kulkarni } 3761*7e6ad469SVishal Kulkarni 3762*7e6ad469SVishal Kulkarni err1: 3763*7e6ad469SVishal Kulkarni return rc; 3764*7e6ad469SVishal Kulkarni } 3765*7e6ad469SVishal Kulkarni 3766*7e6ad469SVishal Kulkarni int 3767*7e6ad469SVishal Kulkarni view_ma_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 3768*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 3769*7e6ad469SVishal Kulkarni { 3770*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 3771*7e6ad469SVishal Kulkarni struct ireg_buf *ma_indr; 3772*7e6ad469SVishal Kulkarni u32 indirect_addr; 3773*7e6ad469SVishal Kulkarni int rc = 0; 3774*7e6ad469SVishal Kulkarni int i = 0; 3775*7e6ad469SVishal Kulkarni int n; 3776*7e6ad469SVishal Kulkarni 3777*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 3778*7e6ad469SVishal Kulkarni if (rc) 3779*7e6ad469SVishal Kulkarni return rc; 3780*7e6ad469SVishal Kulkarni 3781*7e6ad469SVishal Kulkarni indirect_addr = A_MA_LOCAL_DEBUG_CFG; 3782*7e6ad469SVishal Kulkarni ma_indr = (struct ireg_buf *)dc_buff.data; 3783*7e6ad469SVishal Kulkarni n = sizeof(t6_ma_ireg_array) / (4 * sizeof(u32)); 3784*7e6ad469SVishal Kulkarni n += sizeof(t6_ma_ireg_array2) / (4 * sizeof(u32)); 3785*7e6ad469SVishal Kulkarni for (i = 0; i < n; i++) { 3786*7e6ad469SVishal Kulkarni u32 *buff = ma_indr->outbuf; 3787*7e6ad469SVishal Kulkarni 3788*7e6ad469SVishal Kulkarni rc = dump_indirect_regs(t6_ma_ptr[i], indirect_addr, 3789*7e6ad469SVishal Kulkarni (const u32 *) buff, cudbg_poutbuf); 3790*7e6ad469SVishal Kulkarni if (rc < 0) 3791*7e6ad469SVishal Kulkarni goto err1; 3792*7e6ad469SVishal Kulkarni ma_indr++; 3793*7e6ad469SVishal Kulkarni } 3794*7e6ad469SVishal Kulkarni 3795*7e6ad469SVishal Kulkarni err1: 3796*7e6ad469SVishal Kulkarni return rc; 3797*7e6ad469SVishal Kulkarni } 3798*7e6ad469SVishal Kulkarni 3799*7e6ad469SVishal Kulkarni int 3800*7e6ad469SVishal Kulkarni view_hma_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 3801*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 3802*7e6ad469SVishal Kulkarni { 3803*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 3804*7e6ad469SVishal Kulkarni struct ireg_buf *hma_indr; 3805*7e6ad469SVishal Kulkarni u32 indirect_addr; 3806*7e6ad469SVishal Kulkarni int rc = 0; 3807*7e6ad469SVishal Kulkarni int i = 0; 3808*7e6ad469SVishal Kulkarni int n; 3809*7e6ad469SVishal Kulkarni 3810*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 3811*7e6ad469SVishal Kulkarni if (rc) 3812*7e6ad469SVishal Kulkarni return rc; 3813*7e6ad469SVishal Kulkarni 3814*7e6ad469SVishal Kulkarni indirect_addr = A_HMA_LOCAL_DEBUG_CFG; 3815*7e6ad469SVishal Kulkarni hma_indr = (struct ireg_buf *)dc_buff.data; 3816*7e6ad469SVishal Kulkarni n = sizeof(t6_hma_ireg_array) / (4 * sizeof(u32)); 3817*7e6ad469SVishal Kulkarni for (i = 0; i < n; i++) { 3818*7e6ad469SVishal Kulkarni u32 *buff = hma_indr->outbuf; 3819*7e6ad469SVishal Kulkarni 3820*7e6ad469SVishal Kulkarni rc = dump_indirect_regs(t6_hma_ptr[i], indirect_addr, 3821*7e6ad469SVishal Kulkarni (const u32 *) buff, cudbg_poutbuf); 3822*7e6ad469SVishal Kulkarni if (rc < 0) 3823*7e6ad469SVishal Kulkarni goto err1; 3824*7e6ad469SVishal Kulkarni hma_indr++; 3825*7e6ad469SVishal Kulkarni } 3826*7e6ad469SVishal Kulkarni 3827*7e6ad469SVishal Kulkarni err1: 3828*7e6ad469SVishal Kulkarni return rc; 3829*7e6ad469SVishal Kulkarni } 3830*7e6ad469SVishal Kulkarni 3831*7e6ad469SVishal Kulkarni int 3832*7e6ad469SVishal Kulkarni view_pm_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 3833*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 3834*7e6ad469SVishal Kulkarni { 3835*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 3836*7e6ad469SVishal Kulkarni struct ireg_buf *ch_pm; 3837*7e6ad469SVishal Kulkarni u32 indirect_addr; 3838*7e6ad469SVishal Kulkarni int rc = 0; 3839*7e6ad469SVishal Kulkarni int i = 0; 3840*7e6ad469SVishal Kulkarni int n; 3841*7e6ad469SVishal Kulkarni 3842*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 3843*7e6ad469SVishal Kulkarni if (rc) 3844*7e6ad469SVishal Kulkarni return rc; 3845*7e6ad469SVishal Kulkarni 3846*7e6ad469SVishal Kulkarni ch_pm = (struct ireg_buf *)dc_buff.data; 3847*7e6ad469SVishal Kulkarni 3848*7e6ad469SVishal Kulkarni if (!cudbg_poutbuf->data) 3849*7e6ad469SVishal Kulkarni printf("\n\nPM_RX\n\n"); 3850*7e6ad469SVishal Kulkarni 3851*7e6ad469SVishal Kulkarni indirect_addr = PM_RX_INDIRECT; 3852*7e6ad469SVishal Kulkarni n = sizeof(t5_pm_rx_array)/(4 * sizeof(u32)); 3853*7e6ad469SVishal Kulkarni for (i = 0; i < n; i++) { 3854*7e6ad469SVishal Kulkarni u32 *buff = ch_pm->outbuf; 3855*7e6ad469SVishal Kulkarni 3856*7e6ad469SVishal Kulkarni rc = dump_indirect_regs(t5_pm_rx_ptr[i], indirect_addr, 3857*7e6ad469SVishal Kulkarni (const u32 *) buff, cudbg_poutbuf); 3858*7e6ad469SVishal Kulkarni if (rc < 0) 3859*7e6ad469SVishal Kulkarni goto err1; 3860*7e6ad469SVishal Kulkarni 3861*7e6ad469SVishal Kulkarni ch_pm++; 3862*7e6ad469SVishal Kulkarni } 3863*7e6ad469SVishal Kulkarni 3864*7e6ad469SVishal Kulkarni if (!cudbg_poutbuf->data) 3865*7e6ad469SVishal Kulkarni printf("\n\nPM_TX\n\n"); 3866*7e6ad469SVishal Kulkarni 3867*7e6ad469SVishal Kulkarni indirect_addr = PM_TX_INDIRECT; 3868*7e6ad469SVishal Kulkarni n = sizeof(t5_pm_tx_array)/(4 * sizeof(u32)); 3869*7e6ad469SVishal Kulkarni for (i = 0; i < n; i++) { 3870*7e6ad469SVishal Kulkarni u32 *buff = ch_pm->outbuf; 3871*7e6ad469SVishal Kulkarni 3872*7e6ad469SVishal Kulkarni rc = dump_indirect_regs(t5_pm_tx_ptr[i], indirect_addr, 3873*7e6ad469SVishal Kulkarni (const u32 *) buff, cudbg_poutbuf); 3874*7e6ad469SVishal Kulkarni if (rc < 0) 3875*7e6ad469SVishal Kulkarni goto err1; 3876*7e6ad469SVishal Kulkarni ch_pm++; 3877*7e6ad469SVishal Kulkarni } 3878*7e6ad469SVishal Kulkarni 3879*7e6ad469SVishal Kulkarni err1: 3880*7e6ad469SVishal Kulkarni return rc; 3881*7e6ad469SVishal Kulkarni } 3882*7e6ad469SVishal Kulkarni 3883*7e6ad469SVishal Kulkarni int 3884*7e6ad469SVishal Kulkarni view_tx_rate(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 3885*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 3886*7e6ad469SVishal Kulkarni { 3887*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 3888*7e6ad469SVishal Kulkarni struct tx_rate *tx_rate; 3889*7e6ad469SVishal Kulkarni int rc = 0; 3890*7e6ad469SVishal Kulkarni 3891*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 3892*7e6ad469SVishal Kulkarni if (rc) 3893*7e6ad469SVishal Kulkarni return rc; 3894*7e6ad469SVishal Kulkarni 3895*7e6ad469SVishal Kulkarni tx_rate = (struct tx_rate *)dc_buff.data; 3896*7e6ad469SVishal Kulkarni printf("\n\n\t\tTX_RATE\n\n"); 3897*7e6ad469SVishal Kulkarni if (tx_rate->nchan == NCHAN) { 3898*7e6ad469SVishal Kulkarni printf(" channel 0 channel 1 channel 2 channel 3\n"); 3899*7e6ad469SVishal Kulkarni printf("NIC B/s: %10llu %10llu"\ 3900*7e6ad469SVishal Kulkarni " %10llu %10llu\n", 3901*7e6ad469SVishal Kulkarni (unsigned long long)tx_rate->nrate[0], 3902*7e6ad469SVishal Kulkarni (unsigned long long)tx_rate->nrate[1], 3903*7e6ad469SVishal Kulkarni (unsigned long long)tx_rate->nrate[2], 3904*7e6ad469SVishal Kulkarni (unsigned long long)tx_rate->nrate[3]); 3905*7e6ad469SVishal Kulkarni printf("Offload B/s: %10llu %10llu"\ 3906*7e6ad469SVishal Kulkarni " %10llu %10llu\n", 3907*7e6ad469SVishal Kulkarni (unsigned long long)tx_rate->orate[0], 3908*7e6ad469SVishal Kulkarni (unsigned long long)tx_rate->orate[1], 3909*7e6ad469SVishal Kulkarni (unsigned long long)tx_rate->orate[2], 3910*7e6ad469SVishal Kulkarni (unsigned long long)tx_rate->orate[3]); 3911*7e6ad469SVishal Kulkarni } else { 3912*7e6ad469SVishal Kulkarni printf(" channel 0 "\ 3913*7e6ad469SVishal Kulkarni "channel 1\n"); 3914*7e6ad469SVishal Kulkarni printf("NIC B/s: %10llu "\ 3915*7e6ad469SVishal Kulkarni "%10llu\n", 3916*7e6ad469SVishal Kulkarni (unsigned long long)tx_rate->nrate[0], 3917*7e6ad469SVishal Kulkarni (unsigned long long)tx_rate->nrate[1]); 3918*7e6ad469SVishal Kulkarni printf("Offload B/s: %10llu "\ 3919*7e6ad469SVishal Kulkarni "%10llu\n", 3920*7e6ad469SVishal Kulkarni (unsigned long long)tx_rate->orate[0], 3921*7e6ad469SVishal Kulkarni (unsigned long long)tx_rate->orate[1]); 3922*7e6ad469SVishal Kulkarni } 3923*7e6ad469SVishal Kulkarni 3924*7e6ad469SVishal Kulkarni return rc; 3925*7e6ad469SVishal Kulkarni } 3926*7e6ad469SVishal Kulkarni 3927*7e6ad469SVishal Kulkarni int 3928*7e6ad469SVishal Kulkarni view_tid(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 3929*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 3930*7e6ad469SVishal Kulkarni { 3931*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 3932*7e6ad469SVishal Kulkarni struct tid_info_region_rev1 *tid1; 3933*7e6ad469SVishal Kulkarni struct tid_info_region *tid; 3934*7e6ad469SVishal Kulkarni u32 tid_start = 0; 3935*7e6ad469SVishal Kulkarni int rc = 0, rev; 3936*7e6ad469SVishal Kulkarni 3937*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 3938*7e6ad469SVishal Kulkarni if (rc) 3939*7e6ad469SVishal Kulkarni return rc; 3940*7e6ad469SVishal Kulkarni 3941*7e6ad469SVishal Kulkarni rev = get_entity_rev((struct cudbg_ver_hdr *)dc_buff.data); 3942*7e6ad469SVishal Kulkarni if (rev) { 3943*7e6ad469SVishal Kulkarni tid1 = (struct tid_info_region_rev1 *)(dc_buff.data); 3944*7e6ad469SVishal Kulkarni tid_start = tid1->tid_start; 3945*7e6ad469SVishal Kulkarni tid = &(tid1->tid); 3946*7e6ad469SVishal Kulkarni } else 3947*7e6ad469SVishal Kulkarni tid = (struct tid_info_region *)dc_buff.data; 3948*7e6ad469SVishal Kulkarni 3949*7e6ad469SVishal Kulkarni printf("\n\n\tTID INFO\n\n"); 3950*7e6ad469SVishal Kulkarni if (tid->le_db_conf & F_HASHEN) { 3951*7e6ad469SVishal Kulkarni if (tid->sb) { 3952*7e6ad469SVishal Kulkarni printf("TID range: "\ 3953*7e6ad469SVishal Kulkarni "%u..%u/%u..%u\n", tid_start, tid->sb - 1, 3954*7e6ad469SVishal Kulkarni tid->hash_base, tid->ntids - 1); 3955*7e6ad469SVishal Kulkarni } else if (tid->flags & FW_OFLD_CONN) { 3956*7e6ad469SVishal Kulkarni printf("TID range: "\ 3957*7e6ad469SVishal Kulkarni "%u..%u/%u..%u\n", tid->aftid_base, 3958*7e6ad469SVishal Kulkarni tid->aftid_end, tid->hash_base, 3959*7e6ad469SVishal Kulkarni tid->ntids - 1); 3960*7e6ad469SVishal Kulkarni 3961*7e6ad469SVishal Kulkarni } else { 3962*7e6ad469SVishal Kulkarni printf("TID range: "\ 3963*7e6ad469SVishal Kulkarni "%u..%u\n", tid->hash_base, 3964*7e6ad469SVishal Kulkarni tid->ntids - 1); 3965*7e6ad469SVishal Kulkarni } 3966*7e6ad469SVishal Kulkarni } else if (tid->ntids) { 3967*7e6ad469SVishal Kulkarni printf("TID range: %u..%u\n", 3968*7e6ad469SVishal Kulkarni tid_start, tid->ntids - 1); 3969*7e6ad469SVishal Kulkarni } 3970*7e6ad469SVishal Kulkarni 3971*7e6ad469SVishal Kulkarni if (tid->nstids) 3972*7e6ad469SVishal Kulkarni printf("STID range: %u..%u\n", 3973*7e6ad469SVishal Kulkarni tid->stid_base, tid->stid_base + tid->nstids - 1); 3974*7e6ad469SVishal Kulkarni 3975*7e6ad469SVishal Kulkarni #if 0 /*For T4 cards*/ 3976*7e6ad469SVishal Kulkarni if (tid->nsftids) 3977*7e6ad469SVishal Kulkarni printf("SFTID range: %u..%u\n", 3978*7e6ad469SVishal Kulkarni tid->sftid_base, 3979*7e6ad469SVishal Kulkarni tid->sftid_base + tid->nsftids - 2); 3980*7e6ad469SVishal Kulkarni #endif 3981*7e6ad469SVishal Kulkarni 3982*7e6ad469SVishal Kulkarni if (tid->nuotids) 3983*7e6ad469SVishal Kulkarni printf("UOTID range: %u..%u\n", 3984*7e6ad469SVishal Kulkarni tid->uotid_base, 3985*7e6ad469SVishal Kulkarni tid->uotid_base + tid->nuotids - 1); 3986*7e6ad469SVishal Kulkarni 3987*7e6ad469SVishal Kulkarni if (tid->nhpftids && is_t6(chip)) 3988*7e6ad469SVishal Kulkarni printf("HPFTID range: %u..%u\n", 3989*7e6ad469SVishal Kulkarni tid->hpftid_base, 3990*7e6ad469SVishal Kulkarni tid->hpftid_base + tid->nhpftids - 1); 3991*7e6ad469SVishal Kulkarni if (tid->ntids) 3992*7e6ad469SVishal Kulkarni printf("HW TID usage: %u IP users, "\ 3993*7e6ad469SVishal Kulkarni "%u IPv6 users\n", 3994*7e6ad469SVishal Kulkarni tid->IP_users, tid->IPv6_users); 3995*7e6ad469SVishal Kulkarni 3996*7e6ad469SVishal Kulkarni return rc; 3997*7e6ad469SVishal Kulkarni } 3998*7e6ad469SVishal Kulkarni 3999*7e6ad469SVishal Kulkarni static int 4000*7e6ad469SVishal Kulkarni show_cntxt(struct cudbg_ch_cntxt *context, 4001*7e6ad469SVishal Kulkarni struct cudbg_cntxt_field *field, 4002*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf) 4003*7e6ad469SVishal Kulkarni { 4004*7e6ad469SVishal Kulkarni char str[8]; 4005*7e6ad469SVishal Kulkarni int rc = 0; 4006*7e6ad469SVishal Kulkarni 4007*7e6ad469SVishal Kulkarni if (context->cntxt_type == CTXT_EGRESS) 4008*7e6ad469SVishal Kulkarni strcpy(str, "egress"); 4009*7e6ad469SVishal Kulkarni if (context->cntxt_type == CTXT_INGRESS) 4010*7e6ad469SVishal Kulkarni strcpy(str, "ingress"); 4011*7e6ad469SVishal Kulkarni if (context->cntxt_type == CTXT_FLM) 4012*7e6ad469SVishal Kulkarni strcpy(str, "fl"); 4013*7e6ad469SVishal Kulkarni if (context->cntxt_type == CTXT_CNM) 4014*7e6ad469SVishal Kulkarni strcpy(str, "cong"); 4015*7e6ad469SVishal Kulkarni printf("\n\nContext type: %-47s\nQueue ID: "\ 4016*7e6ad469SVishal Kulkarni "%-10d\n", str, context->cntxt_id); 4017*7e6ad469SVishal Kulkarni 4018*7e6ad469SVishal Kulkarni while (field->name) { 4019*7e6ad469SVishal Kulkarni unsigned long long data; 4020*7e6ad469SVishal Kulkarni 4021*7e6ad469SVishal Kulkarni u32 index = field->start_bit / 32; 4022*7e6ad469SVishal Kulkarni u32 bits = field->start_bit % 32; 4023*7e6ad469SVishal Kulkarni u32 width = field->end_bit - field->start_bit + 1; 4024*7e6ad469SVishal Kulkarni u32 mask = (1ULL << width) - 1; 4025*7e6ad469SVishal Kulkarni 4026*7e6ad469SVishal Kulkarni data = (unsigned long long)((context->data[index] >> bits) | 4027*7e6ad469SVishal Kulkarni ((u64)context->data[index + 1] << (32 - bits))); 4028*7e6ad469SVishal Kulkarni if (bits) 4029*7e6ad469SVishal Kulkarni data |= ((u64)context->data[index + 2] << (64 - bits)); 4030*7e6ad469SVishal Kulkarni data &= mask; 4031*7e6ad469SVishal Kulkarni 4032*7e6ad469SVishal Kulkarni if (field->islog2) 4033*7e6ad469SVishal Kulkarni data = (unsigned long long)1 << data; 4034*7e6ad469SVishal Kulkarni 4035*7e6ad469SVishal Kulkarni printf("%-47s %#-10llx\n", 4036*7e6ad469SVishal Kulkarni field->name, data << field->shift); 4037*7e6ad469SVishal Kulkarni field++; 4038*7e6ad469SVishal Kulkarni } 4039*7e6ad469SVishal Kulkarni 4040*7e6ad469SVishal Kulkarni return rc; 4041*7e6ad469SVishal Kulkarni } 4042*7e6ad469SVishal Kulkarni 4043*7e6ad469SVishal Kulkarni int 4044*7e6ad469SVishal Kulkarni view_mps_tcam(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 4045*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 4046*7e6ad469SVishal Kulkarni { 4047*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 4048*7e6ad469SVishal Kulkarni struct cudbg_mps_tcam *tcam; 4049*7e6ad469SVishal Kulkarni int rc = 0; 4050*7e6ad469SVishal Kulkarni int n, i; 4051*7e6ad469SVishal Kulkarni 4052*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 4053*7e6ad469SVishal Kulkarni if (rc) 4054*7e6ad469SVishal Kulkarni return rc; 4055*7e6ad469SVishal Kulkarni 4056*7e6ad469SVishal Kulkarni n = dc_buff.size / sizeof(struct cudbg_mps_tcam); 4057*7e6ad469SVishal Kulkarni tcam = (struct cudbg_mps_tcam *)dc_buff.data; 4058*7e6ad469SVishal Kulkarni if (is_t6(chip)) { 4059*7e6ad469SVishal Kulkarni printf("Idx Ethernet address "\ 4060*7e6ad469SVishal Kulkarni "Mask VNI Mask IVLAN Vld DIP_Hit "\ 4061*7e6ad469SVishal Kulkarni "Lookup Port Vld Ports PF VF "\ 4062*7e6ad469SVishal Kulkarni " Replication "\ 4063*7e6ad469SVishal Kulkarni " P0 P1 P2 P3 ML\n"); 4064*7e6ad469SVishal Kulkarni } else if (is_t5(chip)) { 4065*7e6ad469SVishal Kulkarni if (tcam->rplc_size > CUDBG_MAX_RPLC_SIZE) { 4066*7e6ad469SVishal Kulkarni printf("Idx Ethernet "\ 4067*7e6ad469SVishal Kulkarni "address Mask Vld Ports PF VF "\ 4068*7e6ad469SVishal Kulkarni " Replication "\ 4069*7e6ad469SVishal Kulkarni " P0 P1 "\ 4070*7e6ad469SVishal Kulkarni "P2 P3 ML\n"); 4071*7e6ad469SVishal Kulkarni } else { 4072*7e6ad469SVishal Kulkarni printf("Idx Ethernet "\ 4073*7e6ad469SVishal Kulkarni "address Mask Vld Ports PF VF "\ 4074*7e6ad469SVishal Kulkarni " Replication P0"\ 4075*7e6ad469SVishal Kulkarni " P1 P2 P3 ML\n"); 4076*7e6ad469SVishal Kulkarni } 4077*7e6ad469SVishal Kulkarni } 4078*7e6ad469SVishal Kulkarni 4079*7e6ad469SVishal Kulkarni for (i = 0; i < n; i++, tcam++) { 4080*7e6ad469SVishal Kulkarni /* Print only valid MPS TCAM entries */ 4081*7e6ad469SVishal Kulkarni if (i && !tcam->idx) 4082*7e6ad469SVishal Kulkarni continue; 4083*7e6ad469SVishal Kulkarni 4084*7e6ad469SVishal Kulkarni if (is_t6(chip)) { 4085*7e6ad469SVishal Kulkarni /* Inner header lookup */ 4086*7e6ad469SVishal Kulkarni if (tcam->lookup_type && (tcam->lookup_type != 4087*7e6ad469SVishal Kulkarni M_DATALKPTYPE)) { 4088*7e6ad469SVishal Kulkarni printf("%3u "\ 4089*7e6ad469SVishal Kulkarni "%02x:%02x:%02x:%02x:%02x:%02x "\ 4090*7e6ad469SVishal Kulkarni "%012llx %06x %06x - - "\ 4091*7e6ad469SVishal Kulkarni "%3c %3c %4x %3c "\ 4092*7e6ad469SVishal Kulkarni "%#x%4u%4d", 4093*7e6ad469SVishal Kulkarni tcam->idx, tcam->addr[0], 4094*7e6ad469SVishal Kulkarni tcam->addr[1], tcam->addr[2], 4095*7e6ad469SVishal Kulkarni tcam->addr[3], tcam->addr[4], 4096*7e6ad469SVishal Kulkarni tcam->addr[5], 4097*7e6ad469SVishal Kulkarni (unsigned long long)tcam->mask, 4098*7e6ad469SVishal Kulkarni tcam->vniy, (tcam->vnix | tcam->vniy), 4099*7e6ad469SVishal Kulkarni tcam->dip_hit ? 'Y' : 'N', 4100*7e6ad469SVishal Kulkarni tcam->lookup_type ? 'I' : 'O', 4101*7e6ad469SVishal Kulkarni tcam->port_num, 4102*7e6ad469SVishal Kulkarni (tcam->cls_lo & F_T6_SRAM_VLD) 4103*7e6ad469SVishal Kulkarni ? 'Y' : 'N', 4104*7e6ad469SVishal Kulkarni G_PORTMAP(tcam->cls_hi), 4105*7e6ad469SVishal Kulkarni G_T6_PF(tcam->cls_lo), 4106*7e6ad469SVishal Kulkarni (tcam->cls_lo & F_T6_VF_VALID) 4107*7e6ad469SVishal Kulkarni ? 4108*7e6ad469SVishal Kulkarni G_T6_VF(tcam->cls_lo) : -1); 4109*7e6ad469SVishal Kulkarni } else { 4110*7e6ad469SVishal Kulkarni printf("%3u "\ 4111*7e6ad469SVishal Kulkarni "%02x:%02x:%02x:%02x:%02x:%02x"\ 4112*7e6ad469SVishal Kulkarni " %012llx - - ", 4113*7e6ad469SVishal Kulkarni tcam->idx, tcam->addr[0], 4114*7e6ad469SVishal Kulkarni tcam->addr[1], tcam->addr[2], 4115*7e6ad469SVishal Kulkarni tcam->addr[3], tcam->addr[4], 4116*7e6ad469SVishal Kulkarni tcam->addr[5], 4117*7e6ad469SVishal Kulkarni (unsigned long long)tcam->mask); 4118*7e6ad469SVishal Kulkarni 4119*7e6ad469SVishal Kulkarni if (tcam->vlan_vld) { 4120*7e6ad469SVishal Kulkarni printf( 4121*7e6ad469SVishal Kulkarni "%4u Y ", 4122*7e6ad469SVishal Kulkarni tcam->ivlan); 4123*7e6ad469SVishal Kulkarni } else { 4124*7e6ad469SVishal Kulkarni printf( 4125*7e6ad469SVishal Kulkarni " - N "); 4126*7e6ad469SVishal Kulkarni } 4127*7e6ad469SVishal Kulkarni 4128*7e6ad469SVishal Kulkarni printf( 4129*7e6ad469SVishal Kulkarni "- %3c %4x %3c "\ 4130*7e6ad469SVishal Kulkarni "%#x%4u%4d", 4131*7e6ad469SVishal Kulkarni tcam->lookup_type ? 'I' : 'O', 4132*7e6ad469SVishal Kulkarni tcam->port_num, 4133*7e6ad469SVishal Kulkarni (tcam->cls_lo & F_T6_SRAM_VLD) 4134*7e6ad469SVishal Kulkarni ? 'Y' : 'N', 4135*7e6ad469SVishal Kulkarni G_PORTMAP(tcam->cls_hi), 4136*7e6ad469SVishal Kulkarni G_T6_PF(tcam->cls_lo), 4137*7e6ad469SVishal Kulkarni (tcam->cls_lo & F_T6_VF_VALID) 4138*7e6ad469SVishal Kulkarni ? 4139*7e6ad469SVishal Kulkarni G_T6_VF(tcam->cls_lo) : -1); 4140*7e6ad469SVishal Kulkarni } 4141*7e6ad469SVishal Kulkarni } else if (is_t5(chip)) { 4142*7e6ad469SVishal Kulkarni printf("%3u "\ 4143*7e6ad469SVishal Kulkarni "%02x:%02x:%02x:%02x:%02x:%02x %012llx%3c"\ 4144*7e6ad469SVishal Kulkarni " %#x%4u%4d", 4145*7e6ad469SVishal Kulkarni tcam->idx, tcam->addr[0], tcam->addr[1], 4146*7e6ad469SVishal Kulkarni tcam->addr[2], tcam->addr[3], 4147*7e6ad469SVishal Kulkarni tcam->addr[4], tcam->addr[5], 4148*7e6ad469SVishal Kulkarni (unsigned long long)tcam->mask, 4149*7e6ad469SVishal Kulkarni (tcam->cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 4150*7e6ad469SVishal Kulkarni G_PORTMAP(tcam->cls_hi), 4151*7e6ad469SVishal Kulkarni G_PF(tcam->cls_lo), 4152*7e6ad469SVishal Kulkarni (tcam->cls_lo & F_VF_VALID) ? 4153*7e6ad469SVishal Kulkarni G_VF(tcam->cls_lo) : -1); 4154*7e6ad469SVishal Kulkarni } 4155*7e6ad469SVishal Kulkarni 4156*7e6ad469SVishal Kulkarni if (tcam->repli) { 4157*7e6ad469SVishal Kulkarni if (tcam->rplc_size > CUDBG_MAX_RPLC_SIZE) { 4158*7e6ad469SVishal Kulkarni printf(" %08x %08x "\ 4159*7e6ad469SVishal Kulkarni "%08x %08x %08x %08x %08x %08x", 4160*7e6ad469SVishal Kulkarni tcam->rplc[7], tcam->rplc[6], 4161*7e6ad469SVishal Kulkarni tcam->rplc[5], tcam->rplc[4], 4162*7e6ad469SVishal Kulkarni tcam->rplc[3], tcam->rplc[2], 4163*7e6ad469SVishal Kulkarni tcam->rplc[1], tcam->rplc[0]); 4164*7e6ad469SVishal Kulkarni } else { 4165*7e6ad469SVishal Kulkarni printf(" %08x %08x "\ 4166*7e6ad469SVishal Kulkarni "%08x %08x", tcam->rplc[3], 4167*7e6ad469SVishal Kulkarni tcam->rplc[2], tcam->rplc[1], 4168*7e6ad469SVishal Kulkarni tcam->rplc[0]); 4169*7e6ad469SVishal Kulkarni } 4170*7e6ad469SVishal Kulkarni } else { 4171*7e6ad469SVishal Kulkarni if (tcam->rplc_size > CUDBG_MAX_RPLC_SIZE) 4172*7e6ad469SVishal Kulkarni printf("%72c", ' '); 4173*7e6ad469SVishal Kulkarni else 4174*7e6ad469SVishal Kulkarni printf("%36c", ' '); 4175*7e6ad469SVishal Kulkarni } 4176*7e6ad469SVishal Kulkarni if (is_t6(chip)) { 4177*7e6ad469SVishal Kulkarni printf( "%4u%3u%3u%3u %#x\n", 4178*7e6ad469SVishal Kulkarni G_T6_SRAM_PRIO0(tcam->cls_lo), 4179*7e6ad469SVishal Kulkarni G_T6_SRAM_PRIO1(tcam->cls_lo), 4180*7e6ad469SVishal Kulkarni G_T6_SRAM_PRIO2(tcam->cls_lo), 4181*7e6ad469SVishal Kulkarni G_T6_SRAM_PRIO3(tcam->cls_lo), 4182*7e6ad469SVishal Kulkarni (tcam->cls_lo >> S_T6_MULTILISTEN0) & 0xf); 4183*7e6ad469SVishal Kulkarni } else if (is_t5(chip)) { 4184*7e6ad469SVishal Kulkarni printf("%4u%3u%3u%3u %#x\n", 4185*7e6ad469SVishal Kulkarni G_SRAM_PRIO0(tcam->cls_lo), 4186*7e6ad469SVishal Kulkarni G_SRAM_PRIO1(tcam->cls_lo), 4187*7e6ad469SVishal Kulkarni G_SRAM_PRIO2(tcam->cls_lo), 4188*7e6ad469SVishal Kulkarni G_SRAM_PRIO3(tcam->cls_lo), 4189*7e6ad469SVishal Kulkarni (tcam->cls_lo >> S_MULTILISTEN0) & 0xf); 4190*7e6ad469SVishal Kulkarni } 4191*7e6ad469SVishal Kulkarni } 4192*7e6ad469SVishal Kulkarni 4193*7e6ad469SVishal Kulkarni return rc; 4194*7e6ad469SVishal Kulkarni } 4195*7e6ad469SVishal Kulkarni 4196*7e6ad469SVishal Kulkarni int 4197*7e6ad469SVishal Kulkarni view_dump_context(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 4198*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 4199*7e6ad469SVishal Kulkarni { 4200*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 4201*7e6ad469SVishal Kulkarni struct cudbg_ch_cntxt *context; 4202*7e6ad469SVishal Kulkarni int rc = 0; 4203*7e6ad469SVishal Kulkarni int n, i; 4204*7e6ad469SVishal Kulkarni 4205*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 4206*7e6ad469SVishal Kulkarni if (rc) 4207*7e6ad469SVishal Kulkarni return rc; 4208*7e6ad469SVishal Kulkarni 4209*7e6ad469SVishal Kulkarni n = dc_buff.size / sizeof(struct cudbg_ch_cntxt); 4210*7e6ad469SVishal Kulkarni context = (struct cudbg_ch_cntxt *)dc_buff.data; 4211*7e6ad469SVishal Kulkarni for (i = 0; i < n; i++, context++) { 4212*7e6ad469SVishal Kulkarni /* Only print valid contexts */ 4213*7e6ad469SVishal Kulkarni if (context->cntxt_type != CTXT_CNM) { 4214*7e6ad469SVishal Kulkarni rc = cudbg_sge_ctxt_check_valid(context->data, 4215*7e6ad469SVishal Kulkarni context->cntxt_type); 4216*7e6ad469SVishal Kulkarni if (!rc) 4217*7e6ad469SVishal Kulkarni continue; 4218*7e6ad469SVishal Kulkarni } 4219*7e6ad469SVishal Kulkarni 4220*7e6ad469SVishal Kulkarni if (context->cntxt_type == CTXT_EGRESS) { 4221*7e6ad469SVishal Kulkarni if (is_t5(chip)) 4222*7e6ad469SVishal Kulkarni rc = show_cntxt(context, t5_egress_cntxt, 4223*7e6ad469SVishal Kulkarni cudbg_poutbuf); 4224*7e6ad469SVishal Kulkarni else if (is_t6(chip)) 4225*7e6ad469SVishal Kulkarni rc = show_cntxt(context, t6_egress_cntxt, 4226*7e6ad469SVishal Kulkarni cudbg_poutbuf); 4227*7e6ad469SVishal Kulkarni } else if (context->cntxt_type == CTXT_INGRESS) { 4228*7e6ad469SVishal Kulkarni if (is_t5(chip)) 4229*7e6ad469SVishal Kulkarni rc = show_cntxt(context, t5_ingress_cntxt, 4230*7e6ad469SVishal Kulkarni cudbg_poutbuf); 4231*7e6ad469SVishal Kulkarni else if (is_t6(chip)) 4232*7e6ad469SVishal Kulkarni rc = show_cntxt(context, t6_ingress_cntxt, 4233*7e6ad469SVishal Kulkarni cudbg_poutbuf); 4234*7e6ad469SVishal Kulkarni } else if (context->cntxt_type == CTXT_CNM) 4235*7e6ad469SVishal Kulkarni rc = show_cntxt(context, t5_cnm_cntxt, cudbg_poutbuf); 4236*7e6ad469SVishal Kulkarni else if (context->cntxt_type == CTXT_FLM) { 4237*7e6ad469SVishal Kulkarni if (is_t5(chip)) 4238*7e6ad469SVishal Kulkarni rc = show_cntxt(context, t5_flm_cntxt, 4239*7e6ad469SVishal Kulkarni cudbg_poutbuf); 4240*7e6ad469SVishal Kulkarni else if (is_t6(chip)) 4241*7e6ad469SVishal Kulkarni rc = show_cntxt(context, t6_flm_cntxt, 4242*7e6ad469SVishal Kulkarni cudbg_poutbuf); 4243*7e6ad469SVishal Kulkarni } 4244*7e6ad469SVishal Kulkarni 4245*7e6ad469SVishal Kulkarni if (rc < 0) 4246*7e6ad469SVishal Kulkarni goto err1; 4247*7e6ad469SVishal Kulkarni } 4248*7e6ad469SVishal Kulkarni 4249*7e6ad469SVishal Kulkarni err1: 4250*7e6ad469SVishal Kulkarni return rc; 4251*7e6ad469SVishal Kulkarni } 4252*7e6ad469SVishal Kulkarni 4253*7e6ad469SVishal Kulkarni int 4254*7e6ad469SVishal Kulkarni view_le_tcam(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 4255*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 4256*7e6ad469SVishal Kulkarni { 4257*7e6ad469SVishal Kulkarni char *le_region[] = { 4258*7e6ad469SVishal Kulkarni "active", "server", "filter", "clip", "routing" 4259*7e6ad469SVishal Kulkarni }; 4260*7e6ad469SVishal Kulkarni struct cudbg_tid_data *tid_data = NULL; 4261*7e6ad469SVishal Kulkarni struct cudbg_tcam *tcam_region = NULL; 4262*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 4263*7e6ad469SVishal Kulkarni int rc = 0, j; 4264*7e6ad469SVishal Kulkarni u32 i; 4265*7e6ad469SVishal Kulkarni 4266*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 4267*7e6ad469SVishal Kulkarni if (rc) 4268*7e6ad469SVishal Kulkarni return rc; 4269*7e6ad469SVishal Kulkarni 4270*7e6ad469SVishal Kulkarni tcam_region = (struct cudbg_tcam *)dc_buff.data; 4271*7e6ad469SVishal Kulkarni tid_data = (struct cudbg_tid_data *)(tcam_region + 1); 4272*7e6ad469SVishal Kulkarni printf("\n\nRouting table index: 0x%X\n", 4273*7e6ad469SVishal Kulkarni tcam_region->routing_start); 4274*7e6ad469SVishal Kulkarni printf("Lip comp table index: 0x%X\n", 4275*7e6ad469SVishal Kulkarni tcam_region->clip_start); 4276*7e6ad469SVishal Kulkarni printf("Filter table index: 0x%X\n", 4277*7e6ad469SVishal Kulkarni tcam_region->filter_start); 4278*7e6ad469SVishal Kulkarni printf("Server index: 0x%X\n\n", 4279*7e6ad469SVishal Kulkarni tcam_region->server_start); 4280*7e6ad469SVishal Kulkarni 4281*7e6ad469SVishal Kulkarni printf("tid start: %d\n\n", 0); 4282*7e6ad469SVishal Kulkarni printf("tid end: %d\n\n", 4283*7e6ad469SVishal Kulkarni tcam_region->max_tid); 4284*7e6ad469SVishal Kulkarni 4285*7e6ad469SVishal Kulkarni for (i = 0; i < tcam_region->max_tid; i++) { 4286*7e6ad469SVishal Kulkarni printf( 4287*7e6ad469SVishal Kulkarni "======================================================================================\n"); 4288*7e6ad469SVishal Kulkarni printf("This is a LE_DB_DATA_READ "\ 4289*7e6ad469SVishal Kulkarni "command: on TID %d at index %d\n", i, i * 4); 4290*7e6ad469SVishal Kulkarni if (i < tcam_region->server_start / 4) { 4291*7e6ad469SVishal Kulkarni printf("Region: %s\n\n", 4292*7e6ad469SVishal Kulkarni le_region[0]); 4293*7e6ad469SVishal Kulkarni } else if ((i >= tcam_region->server_start / 4) && 4294*7e6ad469SVishal Kulkarni (i < tcam_region->filter_start / 4)) { 4295*7e6ad469SVishal Kulkarni printf("Region: %s\n\n", 4296*7e6ad469SVishal Kulkarni le_region[1]); 4297*7e6ad469SVishal Kulkarni } else if ((i >= tcam_region->filter_start / 4) && 4298*7e6ad469SVishal Kulkarni (i < tcam_region->clip_start / 4)) { 4299*7e6ad469SVishal Kulkarni printf("Region: %s\n\n", 4300*7e6ad469SVishal Kulkarni le_region[2]); 4301*7e6ad469SVishal Kulkarni } else if ((i >= tcam_region->clip_start / 4) && 4302*7e6ad469SVishal Kulkarni (i < tcam_region->routing_start / 4)) { 4303*7e6ad469SVishal Kulkarni printf("Region: %s\n\n", 4304*7e6ad469SVishal Kulkarni le_region[3]); 4305*7e6ad469SVishal Kulkarni } else if (i >= tcam_region->routing_start / 4) { 4306*7e6ad469SVishal Kulkarni printf("Region: %s\n\n", 4307*7e6ad469SVishal Kulkarni le_region[4]); 4308*7e6ad469SVishal Kulkarni } 4309*7e6ad469SVishal Kulkarni 4310*7e6ad469SVishal Kulkarni printf("READ:\n"); 4311*7e6ad469SVishal Kulkarni printf("DBGICMDMODE: %s\n", 4312*7e6ad469SVishal Kulkarni (tid_data->dbig_conf & 1) ? "LE" : "TCAM"); 4313*7e6ad469SVishal Kulkarni printf("READING TID: 0x%X\n", 4314*7e6ad469SVishal Kulkarni tid_data->tid); 4315*7e6ad469SVishal Kulkarni printf("Write: "\ 4316*7e6ad469SVishal Kulkarni "LE_DB_DBGI_REQ_TCAM_CMD: 0x%X\n", 4317*7e6ad469SVishal Kulkarni tid_data->dbig_cmd); 4318*7e6ad469SVishal Kulkarni printf("Write: LE_DB_DBGI_CONFIG "\ 4319*7e6ad469SVishal Kulkarni "0x%X\n", tid_data->dbig_conf); 4320*7e6ad469SVishal Kulkarni printf("Polling: LE_DB_DBGI_CONFIG:"\ 4321*7e6ad469SVishal Kulkarni " busy bit\n"); 4322*7e6ad469SVishal Kulkarni printf("Read: "\ 4323*7e6ad469SVishal Kulkarni "LE_DB_DBGI_RSP_STATUS: 0x%X [%d]\n", 4324*7e6ad469SVishal Kulkarni tid_data->dbig_rsp_stat & 1, 4325*7e6ad469SVishal Kulkarni tid_data->dbig_rsp_stat & 1); 4326*7e6ad469SVishal Kulkarni printf("Read: "\ 4327*7e6ad469SVishal Kulkarni "LE_DB_DBGI_RSP_DATA:\n"); 4328*7e6ad469SVishal Kulkarni printf("Response data for TID "\ 4329*7e6ad469SVishal Kulkarni "0x%X:\n", i); 4330*7e6ad469SVishal Kulkarni 4331*7e6ad469SVishal Kulkarni for (j = 0; j < CUDBG_NUM_REQ_REGS; j++) { 4332*7e6ad469SVishal Kulkarni printf("\t0x%X: 0x%08X\n", 4333*7e6ad469SVishal Kulkarni A_LE_DB_DBGI_RSP_DATA + (j << 2), 4334*7e6ad469SVishal Kulkarni tid_data->data[j]); 4335*7e6ad469SVishal Kulkarni } 4336*7e6ad469SVishal Kulkarni 4337*7e6ad469SVishal Kulkarni printf("DATA READ: "); 4338*7e6ad469SVishal Kulkarni for (j = CUDBG_NUM_REQ_REGS - 1; j >= 0; j--) { 4339*7e6ad469SVishal Kulkarni printf("%08X", 4340*7e6ad469SVishal Kulkarni tid_data->data[j]); 4341*7e6ad469SVishal Kulkarni } 4342*7e6ad469SVishal Kulkarni printf("\n\n"); 4343*7e6ad469SVishal Kulkarni 4344*7e6ad469SVishal Kulkarni tid_data++; 4345*7e6ad469SVishal Kulkarni } 4346*7e6ad469SVishal Kulkarni 4347*7e6ad469SVishal Kulkarni return rc; 4348*7e6ad469SVishal Kulkarni } 4349*7e6ad469SVishal Kulkarni 4350*7e6ad469SVishal Kulkarni int 4351*7e6ad469SVishal Kulkarni view_pcie_config(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 4352*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 4353*7e6ad469SVishal Kulkarni { 4354*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 4355*7e6ad469SVishal Kulkarni u32 *pcie_config; 4356*7e6ad469SVishal Kulkarni int rc = 0; 4357*7e6ad469SVishal Kulkarni 4358*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 4359*7e6ad469SVishal Kulkarni if (rc) 4360*7e6ad469SVishal Kulkarni return rc; 4361*7e6ad469SVishal Kulkarni 4362*7e6ad469SVishal Kulkarni if (!cudbg_poutbuf->data) 4363*7e6ad469SVishal Kulkarni printf("\n\t\t\tPCIE CONFIG\n\n"); 4364*7e6ad469SVishal Kulkarni 4365*7e6ad469SVishal Kulkarni pcie_config = (u32 *)dc_buff.data; 4366*7e6ad469SVishal Kulkarni rc = dump_indirect_regs(t5_pcie_config_ptr[0], 0, 4367*7e6ad469SVishal Kulkarni (const u32 *)pcie_config, cudbg_poutbuf); 4368*7e6ad469SVishal Kulkarni 4369*7e6ad469SVishal Kulkarni return rc; 4370*7e6ad469SVishal Kulkarni } 4371*7e6ad469SVishal Kulkarni 4372*7e6ad469SVishal Kulkarni int 4373*7e6ad469SVishal Kulkarni view_pcie_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 4374*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 4375*7e6ad469SVishal Kulkarni { 4376*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 4377*7e6ad469SVishal Kulkarni struct ireg_buf *ch_pcie; 4378*7e6ad469SVishal Kulkarni u32 indirect_addr; 4379*7e6ad469SVishal Kulkarni int rc = 0; 4380*7e6ad469SVishal Kulkarni int i = 0; 4381*7e6ad469SVishal Kulkarni int n; 4382*7e6ad469SVishal Kulkarni 4383*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 4384*7e6ad469SVishal Kulkarni if (rc) 4385*7e6ad469SVishal Kulkarni return rc; 4386*7e6ad469SVishal Kulkarni 4387*7e6ad469SVishal Kulkarni if (!cudbg_poutbuf->data) 4388*7e6ad469SVishal Kulkarni printf("\n\nPCIE_PDBG\n\n"); 4389*7e6ad469SVishal Kulkarni 4390*7e6ad469SVishal Kulkarni indirect_addr = PCIE_PDEBUG_INDIRECT; 4391*7e6ad469SVishal Kulkarni ch_pcie = (struct ireg_buf *)dc_buff.data; 4392*7e6ad469SVishal Kulkarni n = sizeof(t5_pcie_pdbg_array)/(4 * sizeof(u32)); 4393*7e6ad469SVishal Kulkarni for (i = 0; i < n; i++) { 4394*7e6ad469SVishal Kulkarni u32 *buff = ch_pcie->outbuf; 4395*7e6ad469SVishal Kulkarni 4396*7e6ad469SVishal Kulkarni rc = dump_indirect_regs(t5_pcie_pdbg_ptr[i], indirect_addr, 4397*7e6ad469SVishal Kulkarni (const u32 *) buff, cudbg_poutbuf); 4398*7e6ad469SVishal Kulkarni if (rc < 0) 4399*7e6ad469SVishal Kulkarni goto err1; 4400*7e6ad469SVishal Kulkarni ch_pcie++; 4401*7e6ad469SVishal Kulkarni } 4402*7e6ad469SVishal Kulkarni 4403*7e6ad469SVishal Kulkarni if (!cudbg_poutbuf->data) 4404*7e6ad469SVishal Kulkarni printf("\n\nPCIE_CDBG\n\n"); 4405*7e6ad469SVishal Kulkarni 4406*7e6ad469SVishal Kulkarni indirect_addr = PCIE_CDEBUG_INDIRECT; 4407*7e6ad469SVishal Kulkarni n = sizeof(t5_pcie_cdbg_array)/(4 * sizeof(u32)); 4408*7e6ad469SVishal Kulkarni for (i = 0; i < n; i++) { 4409*7e6ad469SVishal Kulkarni u32 *buff = ch_pcie->outbuf; 4410*7e6ad469SVishal Kulkarni 4411*7e6ad469SVishal Kulkarni rc = dump_indirect_regs(t5_pcie_cdbg_ptr[i], indirect_addr, 4412*7e6ad469SVishal Kulkarni (const u32 *) buff, cudbg_poutbuf); 4413*7e6ad469SVishal Kulkarni if (rc < 0) 4414*7e6ad469SVishal Kulkarni goto err1; 4415*7e6ad469SVishal Kulkarni ch_pcie++; 4416*7e6ad469SVishal Kulkarni } 4417*7e6ad469SVishal Kulkarni 4418*7e6ad469SVishal Kulkarni err1: 4419*7e6ad469SVishal Kulkarni return rc; 4420*7e6ad469SVishal Kulkarni } 4421*7e6ad469SVishal Kulkarni 4422*7e6ad469SVishal Kulkarni int 4423*7e6ad469SVishal Kulkarni view_tp_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 4424*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 4425*7e6ad469SVishal Kulkarni { 4426*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 4427*7e6ad469SVishal Kulkarni int j = 0, k, l, len, n = 0; 4428*7e6ad469SVishal Kulkarni struct ireg_buf *ch_tp_pio; 4429*7e6ad469SVishal Kulkarni u32 indirect_addr; 4430*7e6ad469SVishal Kulkarni u32 *pkey = NULL; 4431*7e6ad469SVishal Kulkarni int rc = 0; 4432*7e6ad469SVishal Kulkarni int i = 0; 4433*7e6ad469SVishal Kulkarni 4434*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 4435*7e6ad469SVishal Kulkarni if (rc) 4436*7e6ad469SVishal Kulkarni return rc; 4437*7e6ad469SVishal Kulkarni 4438*7e6ad469SVishal Kulkarni ch_tp_pio = (struct ireg_buf *)dc_buff.data; 4439*7e6ad469SVishal Kulkarni l = 0; 4440*7e6ad469SVishal Kulkarni 4441*7e6ad469SVishal Kulkarni indirect_addr = TP_PIO; 4442*7e6ad469SVishal Kulkarni if (!cudbg_poutbuf->data) 4443*7e6ad469SVishal Kulkarni printf("\n\nTP_PIO\n\n"); 4444*7e6ad469SVishal Kulkarni 4445*7e6ad469SVishal Kulkarni if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) 4446*7e6ad469SVishal Kulkarni n = sizeof(t5_tp_pio_array)/(4 * sizeof(u32)); 4447*7e6ad469SVishal Kulkarni else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6) 4448*7e6ad469SVishal Kulkarni n = sizeof(t6_tp_pio_array)/(4 * sizeof(u32)); 4449*7e6ad469SVishal Kulkarni 4450*7e6ad469SVishal Kulkarni for (i = 0; i < n; i++) { 4451*7e6ad469SVishal Kulkarni u32 *buff = ch_tp_pio->outbuf; 4452*7e6ad469SVishal Kulkarni 4453*7e6ad469SVishal Kulkarni if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) 4454*7e6ad469SVishal Kulkarni rc = dump_indirect_regs(t5_tp_pio_ptr[i], indirect_addr, 4455*7e6ad469SVishal Kulkarni (const u32 *) buff, 4456*7e6ad469SVishal Kulkarni cudbg_poutbuf); 4457*7e6ad469SVishal Kulkarni else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6) 4458*7e6ad469SVishal Kulkarni rc = dump_indirect_regs(t6_tp_pio_ptr[i], indirect_addr, 4459*7e6ad469SVishal Kulkarni (const u32 *) buff, 4460*7e6ad469SVishal Kulkarni cudbg_poutbuf); 4461*7e6ad469SVishal Kulkarni 4462*7e6ad469SVishal Kulkarni if (rc < 0) 4463*7e6ad469SVishal Kulkarni goto err1; 4464*7e6ad469SVishal Kulkarni 4465*7e6ad469SVishal Kulkarni ch_tp_pio++; 4466*7e6ad469SVishal Kulkarni } 4467*7e6ad469SVishal Kulkarni 4468*7e6ad469SVishal Kulkarni indirect_addr = TP_TM_PIO_ADDR; 4469*7e6ad469SVishal Kulkarni if (!cudbg_poutbuf->data) 4470*7e6ad469SVishal Kulkarni printf("\n\nTP_TM_PIO\n\n"); 4471*7e6ad469SVishal Kulkarni 4472*7e6ad469SVishal Kulkarni l = 0; 4473*7e6ad469SVishal Kulkarni if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) 4474*7e6ad469SVishal Kulkarni n = sizeof(t5_tp_tm_pio_array)/(4 * sizeof(u32)); 4475*7e6ad469SVishal Kulkarni else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6) 4476*7e6ad469SVishal Kulkarni n = sizeof(t6_tp_tm_pio_array)/(4 * sizeof(u32)); 4477*7e6ad469SVishal Kulkarni 4478*7e6ad469SVishal Kulkarni for (i = 0; i < n; i++) { 4479*7e6ad469SVishal Kulkarni u32 *buff = ch_tp_pio->outbuf; 4480*7e6ad469SVishal Kulkarni 4481*7e6ad469SVishal Kulkarni if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) 4482*7e6ad469SVishal Kulkarni rc = dump_indirect_regs(t5_tp_tm_regs, indirect_addr, 4483*7e6ad469SVishal Kulkarni (const u32 *)buff, 4484*7e6ad469SVishal Kulkarni cudbg_poutbuf); 4485*7e6ad469SVishal Kulkarni else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6) 4486*7e6ad469SVishal Kulkarni rc = dump_indirect_regs(t6_tp_tm_regs, indirect_addr, 4487*7e6ad469SVishal Kulkarni (const u32 *)buff, 4488*7e6ad469SVishal Kulkarni cudbg_poutbuf); 4489*7e6ad469SVishal Kulkarni 4490*7e6ad469SVishal Kulkarni if (rc < 0) 4491*7e6ad469SVishal Kulkarni goto err1; 4492*7e6ad469SVishal Kulkarni 4493*7e6ad469SVishal Kulkarni ch_tp_pio++; 4494*7e6ad469SVishal Kulkarni } 4495*7e6ad469SVishal Kulkarni indirect_addr = TP_MIB_INDEX; 4496*7e6ad469SVishal Kulkarni if (!cudbg_poutbuf->data) 4497*7e6ad469SVishal Kulkarni printf("\n\nTP_MIB_INDEX\n\n"); 4498*7e6ad469SVishal Kulkarni 4499*7e6ad469SVishal Kulkarni l = 0; 4500*7e6ad469SVishal Kulkarni if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) 4501*7e6ad469SVishal Kulkarni n = sizeof(t5_tp_mib_index_array)/(4 * sizeof(u32)); 4502*7e6ad469SVishal Kulkarni else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6) 4503*7e6ad469SVishal Kulkarni n = sizeof(t6_tp_mib_index_array)/(4 * sizeof(u32)); 4504*7e6ad469SVishal Kulkarni for (i = 0; i < n ; i++) { 4505*7e6ad469SVishal Kulkarni u32 *buff = ch_tp_pio->outbuf; 4506*7e6ad469SVishal Kulkarni 4507*7e6ad469SVishal Kulkarni pkey = (u32 *) buff; 4508*7e6ad469SVishal Kulkarni if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) 4509*7e6ad469SVishal Kulkarni j = l + t5_tp_mib_index_array[i][3]; 4510*7e6ad469SVishal Kulkarni else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6) 4511*7e6ad469SVishal Kulkarni j = l + t6_tp_mib_index_array[i][3]; 4512*7e6ad469SVishal Kulkarni 4513*7e6ad469SVishal Kulkarni len = 0; 4514*7e6ad469SVishal Kulkarni for (k = l; k < j; k++) { 4515*7e6ad469SVishal Kulkarni if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) { 4516*7e6ad469SVishal Kulkarni printf("[0x%x:%2s]"\ 4517*7e6ad469SVishal Kulkarni " %-47s %#-10x %u\n", 4518*7e6ad469SVishal Kulkarni indirect_addr, 4519*7e6ad469SVishal Kulkarni t5_tp_mib_index_reg_array[k].addr, 4520*7e6ad469SVishal Kulkarni t5_tp_mib_index_reg_array[k].name, 4521*7e6ad469SVishal Kulkarni pkey[len], pkey[len]); 4522*7e6ad469SVishal Kulkarni } else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6) { 4523*7e6ad469SVishal Kulkarni printf("[0x%x:%2s]"\ 4524*7e6ad469SVishal Kulkarni " %-47s %#-10x %u\n", 4525*7e6ad469SVishal Kulkarni indirect_addr, 4526*7e6ad469SVishal Kulkarni t6_tp_mib_index_reg_array[k].addr, 4527*7e6ad469SVishal Kulkarni t6_tp_mib_index_reg_array[k].name, 4528*7e6ad469SVishal Kulkarni pkey[len], pkey[len]); 4529*7e6ad469SVishal Kulkarni } 4530*7e6ad469SVishal Kulkarni len++; 4531*7e6ad469SVishal Kulkarni } 4532*7e6ad469SVishal Kulkarni l = k; 4533*7e6ad469SVishal Kulkarni ch_tp_pio++; 4534*7e6ad469SVishal Kulkarni } 4535*7e6ad469SVishal Kulkarni 4536*7e6ad469SVishal Kulkarni err1: 4537*7e6ad469SVishal Kulkarni return rc; 4538*7e6ad469SVishal Kulkarni } 4539*7e6ad469SVishal Kulkarni 4540*7e6ad469SVishal Kulkarni int 4541*7e6ad469SVishal Kulkarni find_index_in_t6_sge_regs(u32 addr) 4542*7e6ad469SVishal Kulkarni { 4543*7e6ad469SVishal Kulkarni u32 i = 0; 4544*7e6ad469SVishal Kulkarni 4545*7e6ad469SVishal Kulkarni while (t6_sge_regs[i].name) { 4546*7e6ad469SVishal Kulkarni if (t6_sge_regs[i].addr == addr) 4547*7e6ad469SVishal Kulkarni return i; 4548*7e6ad469SVishal Kulkarni i++; 4549*7e6ad469SVishal Kulkarni } 4550*7e6ad469SVishal Kulkarni 4551*7e6ad469SVishal Kulkarni return -1; 4552*7e6ad469SVishal Kulkarni } 4553*7e6ad469SVishal Kulkarni 4554*7e6ad469SVishal Kulkarni void 4555*7e6ad469SVishal Kulkarni print_t6_sge_reg_value(u32 reg_addr, u32 reg_data, u32 data_value, 4556*7e6ad469SVishal Kulkarni int idx_map, struct cudbg_buffer *cudbg_poutbuf) 4557*7e6ad469SVishal Kulkarni { 4558*7e6ad469SVishal Kulkarni struct reg_info *reg_array = &t6_sge_regs[idx_map]; 4559*7e6ad469SVishal Kulkarni u32 value; 4560*7e6ad469SVishal Kulkarni 4561*7e6ad469SVishal Kulkarni printf("[0x%x:0x%x] %-47s %#-10x %u\n", 4562*7e6ad469SVishal Kulkarni reg_addr, reg_data, reg_array->name, data_value, 4563*7e6ad469SVishal Kulkarni data_value); 4564*7e6ad469SVishal Kulkarni 4565*7e6ad469SVishal Kulkarni reg_array++; 4566*7e6ad469SVishal Kulkarni while (reg_array->len) { 4567*7e6ad469SVishal Kulkarni value = xtract(data_value, reg_array->addr, reg_array->len); 4568*7e6ad469SVishal Kulkarni 4569*7e6ad469SVishal Kulkarni printf(" %-3u:%3u %-47s "\ 4570*7e6ad469SVishal Kulkarni "%#-10x %u\n", 4571*7e6ad469SVishal Kulkarni reg_array->addr + reg_array->len - 1, 4572*7e6ad469SVishal Kulkarni reg_array->addr, reg_array->name, value, value); 4573*7e6ad469SVishal Kulkarni 4574*7e6ad469SVishal Kulkarni reg_array++; 4575*7e6ad469SVishal Kulkarni } 4576*7e6ad469SVishal Kulkarni 4577*7e6ad469SVishal Kulkarni 4578*7e6ad469SVishal Kulkarni return; 4579*7e6ad469SVishal Kulkarni } 4580*7e6ad469SVishal Kulkarni 4581*7e6ad469SVishal Kulkarni void 4582*7e6ad469SVishal Kulkarni print_sge_qbase(struct sge_qbase_reg_field *sge_qbase, u32 pf_vf_count, 4583*7e6ad469SVishal Kulkarni int isPF, struct cudbg_buffer *cudbg_poutbuf) 4584*7e6ad469SVishal Kulkarni { 4585*7e6ad469SVishal Kulkarni u32 *data_value; 4586*7e6ad469SVishal Kulkarni u32 f; 4587*7e6ad469SVishal Kulkarni int idx_map0, idx_map1, idx_map2, idx_map3; 4588*7e6ad469SVishal Kulkarni 4589*7e6ad469SVishal Kulkarni idx_map0 = find_index_in_t6_sge_regs(sge_qbase->reg_data[0]); 4590*7e6ad469SVishal Kulkarni idx_map1 = find_index_in_t6_sge_regs(sge_qbase->reg_data[1]); 4591*7e6ad469SVishal Kulkarni idx_map2 = find_index_in_t6_sge_regs(sge_qbase->reg_data[2]); 4592*7e6ad469SVishal Kulkarni idx_map3 = find_index_in_t6_sge_regs(sge_qbase->reg_data[3]); 4593*7e6ad469SVishal Kulkarni 4594*7e6ad469SVishal Kulkarni if (idx_map0 < 0 || idx_map1 < 0 || idx_map2 < 0 || idx_map3 < 0) { 4595*7e6ad469SVishal Kulkarni printf("Error: one of these addr is "\ 4596*7e6ad469SVishal Kulkarni "wrong: 0x%x 0x%x 0x%x 0x%x\n", sge_qbase->reg_data[0], 4597*7e6ad469SVishal Kulkarni sge_qbase->reg_data[1], sge_qbase->reg_data[2], 4598*7e6ad469SVishal Kulkarni sge_qbase->reg_data[3]); 4599*7e6ad469SVishal Kulkarni return; 4600*7e6ad469SVishal Kulkarni } 4601*7e6ad469SVishal Kulkarni 4602*7e6ad469SVishal Kulkarni for (f = 0; f < pf_vf_count; f++) { 4603*7e6ad469SVishal Kulkarni if (isPF) 4604*7e6ad469SVishal Kulkarni data_value = (u32 *)sge_qbase->pf_data_value[f]; 4605*7e6ad469SVishal Kulkarni else 4606*7e6ad469SVishal Kulkarni data_value = (u32 *)sge_qbase->vf_data_value[f]; 4607*7e6ad469SVishal Kulkarni printf("\nSGE_QBASE_INDEX for %s %d\n", 4608*7e6ad469SVishal Kulkarni isPF ? "pf" : "vf", f); 4609*7e6ad469SVishal Kulkarni print_t6_sge_reg_value(sge_qbase->reg_addr, sge_qbase->reg_data[0], 4610*7e6ad469SVishal Kulkarni data_value[0], idx_map0, cudbg_poutbuf); 4611*7e6ad469SVishal Kulkarni 4612*7e6ad469SVishal Kulkarni print_t6_sge_reg_value(sge_qbase->reg_addr, sge_qbase->reg_data[1], 4613*7e6ad469SVishal Kulkarni data_value[1], idx_map1, cudbg_poutbuf); 4614*7e6ad469SVishal Kulkarni 4615*7e6ad469SVishal Kulkarni print_t6_sge_reg_value(sge_qbase->reg_addr, sge_qbase->reg_data[2], 4616*7e6ad469SVishal Kulkarni data_value[2], idx_map2, cudbg_poutbuf); 4617*7e6ad469SVishal Kulkarni 4618*7e6ad469SVishal Kulkarni print_t6_sge_reg_value(sge_qbase->reg_addr, sge_qbase->reg_data[3], 4619*7e6ad469SVishal Kulkarni data_value[3], idx_map3, cudbg_poutbuf); 4620*7e6ad469SVishal Kulkarni } 4621*7e6ad469SVishal Kulkarni 4622*7e6ad469SVishal Kulkarni return; 4623*7e6ad469SVishal Kulkarni } 4624*7e6ad469SVishal Kulkarni 4625*7e6ad469SVishal Kulkarni int 4626*7e6ad469SVishal Kulkarni view_sge_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 4627*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 4628*7e6ad469SVishal Kulkarni { 4629*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 4630*7e6ad469SVishal Kulkarni struct sge_qbase_reg_field *sge_qbase; 4631*7e6ad469SVishal Kulkarni u32 indirect_addr; 4632*7e6ad469SVishal Kulkarni u32 *pkey = NULL; 4633*7e6ad469SVishal Kulkarni int j, k, len; 4634*7e6ad469SVishal Kulkarni int rc = 0; 4635*7e6ad469SVishal Kulkarni int i = 0; 4636*7e6ad469SVishal Kulkarni int l = 0; 4637*7e6ad469SVishal Kulkarni 4638*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 4639*7e6ad469SVishal Kulkarni if (rc) 4640*7e6ad469SVishal Kulkarni return rc; 4641*7e6ad469SVishal Kulkarni 4642*7e6ad469SVishal Kulkarni pkey = (u32 *) (dc_buff.data + sizeof(struct ireg_field)); 4643*7e6ad469SVishal Kulkarni indirect_addr = SGE_DEBUG_DATA_INDIRECT; 4644*7e6ad469SVishal Kulkarni for (i = 0; i < 2; i++) { 4645*7e6ad469SVishal Kulkarni printf("\n"); 4646*7e6ad469SVishal Kulkarni j = l + t5_sge_dbg_index_array[i][3]; 4647*7e6ad469SVishal Kulkarni len = 0; 4648*7e6ad469SVishal Kulkarni for (k = l; k < j; k++) { 4649*7e6ad469SVishal Kulkarni if (i == 0) { 4650*7e6ad469SVishal Kulkarni printf("[0x%x:0x%x]"\ 4651*7e6ad469SVishal Kulkarni " %-47s %#-10x %u\n", 4652*7e6ad469SVishal Kulkarni indirect_addr, 4653*7e6ad469SVishal Kulkarni sge_debug_data_high[k].addr, 4654*7e6ad469SVishal Kulkarni sge_debug_data_high[k].name, 4655*7e6ad469SVishal Kulkarni pkey[len], pkey[len]); 4656*7e6ad469SVishal Kulkarni } else { 4657*7e6ad469SVishal Kulkarni printf("[0x%x:0x%x]"\ 4658*7e6ad469SVishal Kulkarni " %-47s %#-10x %u\n", 4659*7e6ad469SVishal Kulkarni indirect_addr, 4660*7e6ad469SVishal Kulkarni sge_debug_data_low[k].addr, 4661*7e6ad469SVishal Kulkarni sge_debug_data_low[k].name, 4662*7e6ad469SVishal Kulkarni pkey[len], pkey[len]); 4663*7e6ad469SVishal Kulkarni } 4664*7e6ad469SVishal Kulkarni len++; 4665*7e6ad469SVishal Kulkarni } 4666*7e6ad469SVishal Kulkarni pkey = (u32 *)((char *)pkey + sizeof(struct ireg_buf)); 4667*7e6ad469SVishal Kulkarni } 4668*7e6ad469SVishal Kulkarni 4669*7e6ad469SVishal Kulkarni if (is_t6(chip)) { 4670*7e6ad469SVishal Kulkarni dc_buff.offset = 2 * sizeof(struct ireg_buf); 4671*7e6ad469SVishal Kulkarni 4672*7e6ad469SVishal Kulkarni if (dc_buff.size <= dc_buff.offset) 4673*7e6ad469SVishal Kulkarni goto err1; 4674*7e6ad469SVishal Kulkarni 4675*7e6ad469SVishal Kulkarni sge_qbase = (struct sge_qbase_reg_field *)(dc_buff.data + 4676*7e6ad469SVishal Kulkarni dc_buff.offset); 4677*7e6ad469SVishal Kulkarni print_sge_qbase(sge_qbase, 8, 1, cudbg_poutbuf); 4678*7e6ad469SVishal Kulkarni print_sge_qbase(sge_qbase, sge_qbase->vfcount, 0, 4679*7e6ad469SVishal Kulkarni cudbg_poutbuf); 4680*7e6ad469SVishal Kulkarni } 4681*7e6ad469SVishal Kulkarni 4682*7e6ad469SVishal Kulkarni err1: 4683*7e6ad469SVishal Kulkarni return rc; 4684*7e6ad469SVishal Kulkarni } 4685*7e6ad469SVishal Kulkarni 4686*7e6ad469SVishal Kulkarni static int 4687*7e6ad469SVishal Kulkarni view_full_t6(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 4688*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf) 4689*7e6ad469SVishal Kulkarni { 4690*7e6ad469SVishal Kulkarni u32 pcie_c0rd_full, pcie_c0wr_full, pcie_c0rsp_full; 4691*7e6ad469SVishal Kulkarni u32 pcie_c1rd_full, pcie_c1wr_full, pcie_c1rsp_full; 4692*7e6ad469SVishal Kulkarni u32 rx_fifo_cng, rx_pcmd_cng, rx_hdr_cng; 4693*7e6ad469SVishal Kulkarni u32 tx, rx, cs, es, pcie, pcie1, sge; 4694*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 4695*7e6ad469SVishal Kulkarni u32 sge_req_full = 0, sge_rx_full; 4696*7e6ad469SVishal Kulkarni u32 cng0, cng1; 4697*7e6ad469SVishal Kulkarni int rc = 0; 4698*7e6ad469SVishal Kulkarni u32 *sp; 4699*7e6ad469SVishal Kulkarni 4700*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 4701*7e6ad469SVishal Kulkarni if (rc) 4702*7e6ad469SVishal Kulkarni return rc; 4703*7e6ad469SVishal Kulkarni 4704*7e6ad469SVishal Kulkarni sp = (u32 *)dc_buff.data; 4705*7e6ad469SVishal Kulkarni 4706*7e6ad469SVishal Kulkarni /* Collect Registers: 4707*7e6ad469SVishal Kulkarni * TP_DBG_SCHED_TX (0x7e40 + 0x6a), 4708*7e6ad469SVishal Kulkarni * TP_DBG_SCHED_RX (0x7e40 + 0x6b), 4709*7e6ad469SVishal Kulkarni * TP_DBG_CSIDE_INT (0x7e40 + 0x23f), 4710*7e6ad469SVishal Kulkarni * TP_DBG_ESIDE_INT (0x7e40 + 0x148), 4711*7e6ad469SVishal Kulkarni * PCIE_CDEBUG_INDEX[AppData0] (0x5a10 + 2), 4712*7e6ad469SVishal Kulkarni * PCIE_CDEBUG_INDEX[AppData1] (0x5a10 + 3), 4713*7e6ad469SVishal Kulkarni * SGE_DEBUG_DATA_HIGH_INDEX_10 (0x12a8) 4714*7e6ad469SVishal Kulkarni **/ 4715*7e6ad469SVishal Kulkarni tx = *sp; 4716*7e6ad469SVishal Kulkarni rx = *(sp + 1); 4717*7e6ad469SVishal Kulkarni cs = *(sp + 2); 4718*7e6ad469SVishal Kulkarni es = *(sp + 3); 4719*7e6ad469SVishal Kulkarni pcie = *(sp + 4); 4720*7e6ad469SVishal Kulkarni pcie1 = *(sp + 5); 4721*7e6ad469SVishal Kulkarni sge = *(sp + 6); 4722*7e6ad469SVishal Kulkarni 4723*7e6ad469SVishal Kulkarni pcie_c0wr_full = pcie & 1; 4724*7e6ad469SVishal Kulkarni pcie_c0rd_full = (pcie >> 2) & 1; 4725*7e6ad469SVishal Kulkarni pcie_c0rsp_full = (pcie >> 4) & 1; 4726*7e6ad469SVishal Kulkarni 4727*7e6ad469SVishal Kulkarni pcie_c1wr_full = pcie1 & 1; 4728*7e6ad469SVishal Kulkarni pcie_c1rd_full = (pcie1 >> 2) & 1; 4729*7e6ad469SVishal Kulkarni pcie_c1rsp_full = (pcie1 >> 4) & 1; 4730*7e6ad469SVishal Kulkarni 4731*7e6ad469SVishal Kulkarni /* sge debug_PD_RdRspAFull_d for each channel */ 4732*7e6ad469SVishal Kulkarni sge_rx_full = (sge >> 30) & 0x3; 4733*7e6ad469SVishal Kulkarni 4734*7e6ad469SVishal Kulkarni rx_fifo_cng = (rx >> 20) & 0xf; 4735*7e6ad469SVishal Kulkarni rx_pcmd_cng = (rx >> 14) & 0x3; 4736*7e6ad469SVishal Kulkarni rx_hdr_cng = (rx >> 8) & 0xf; 4737*7e6ad469SVishal Kulkarni cng0 = (rx_fifo_cng & 1) | (rx_pcmd_cng & 1) | (rx_hdr_cng & 1); 4738*7e6ad469SVishal Kulkarni cng1 = ((rx_fifo_cng & 2) >> 1) | ((rx_pcmd_cng & 2) >> 1) | 4739*7e6ad469SVishal Kulkarni ((rx_hdr_cng & 2) >> 1); 4740*7e6ad469SVishal Kulkarni 4741*7e6ad469SVishal Kulkarni printf("\n"); 4742*7e6ad469SVishal Kulkarni /* TP resource reservation */ 4743*7e6ad469SVishal Kulkarni printf("Tx0 ==%1u=> T <=%1u= Rx0\n", 4744*7e6ad469SVishal Kulkarni ((tx >> 28) & 1), ((rx >> 28) & 1)); 4745*7e6ad469SVishal Kulkarni printf("Tx1 ==%1u=> P <=%1u= Rx1\n", 4746*7e6ad469SVishal Kulkarni ((tx >> 29) & 1), ((rx >> 29) & 1)); 4747*7e6ad469SVishal Kulkarni printf("\n"); 4748*7e6ad469SVishal Kulkarni 4749*7e6ad469SVishal Kulkarni /* TX path */ 4750*7e6ad469SVishal Kulkarni /* pcie bits 19:16 are D_RspAFull for each channel */ 4751*7e6ad469SVishal Kulkarni /* Tx is blocked when Responses from system cannot flow toward TP. */ 4752*7e6ad469SVishal Kulkarni printf("Tx0 P =%1u=> S ? U =>%1u=> T\n", 4753*7e6ad469SVishal Kulkarni pcie_c0rsp_full, ((cs >> 24) & 1)); 4754*7e6ad469SVishal Kulkarni printf("Tx1 C =%1u=> G ? T =>%1u=> P\n", 4755*7e6ad469SVishal Kulkarni pcie_c1rsp_full, ((cs >> 25) & 1)); 4756*7e6ad469SVishal Kulkarni 4757*7e6ad469SVishal Kulkarni /* RX path */ 4758*7e6ad469SVishal Kulkarni /* Rx is blocked when sge and/or pcie cannot send requests to system. 4759*7e6ad469SVishal Kulkarni * */ 4760*7e6ad469SVishal Kulkarni printf(" Rd Wr\n"); 4761*7e6ad469SVishal Kulkarni printf("RX0 P <=%1u=%1u=%1u S <=%1u= C "\ 4762*7e6ad469SVishal Kulkarni "<=%1u= T <=T <=%1u= T <=%1u= M\n", 4763*7e6ad469SVishal Kulkarni ((pcie_c0rd_full >> 0) & 1), ((pcie_c0wr_full >> 0) & 1), 4764*7e6ad469SVishal Kulkarni ((sge_req_full >> 0) & 1), ((sge_rx_full >> 0) & 1), 4765*7e6ad469SVishal Kulkarni cng0, ((cs >> 20) & 1), ((es >> 16) & 1)); 4766*7e6ad469SVishal Kulkarni #ifndef __CHECKER__ 4767*7e6ad469SVishal Kulkarni printf("RX1 C <=%1u=%1u=%1u G <=%1u= X "\ 4768*7e6ad469SVishal Kulkarni "<=%1u= C <=P <=%1u= E <=%1u= P\n", 4769*7e6ad469SVishal Kulkarni ((pcie_c1rd_full >> 1) & 1), ((pcie_c1wr_full >> 1) & 1), 4770*7e6ad469SVishal Kulkarni ((sge_req_full >> 1) & 1), ((sge_rx_full >> 1) & 1), 4771*7e6ad469SVishal Kulkarni cng1, ((cs >> 21) & 1), ((es >> 17) & 1)); 4772*7e6ad469SVishal Kulkarni #endif 4773*7e6ad469SVishal Kulkarni printf("\n"); 4774*7e6ad469SVishal Kulkarni 4775*7e6ad469SVishal Kulkarni 4776*7e6ad469SVishal Kulkarni return rc; 4777*7e6ad469SVishal Kulkarni } 4778*7e6ad469SVishal Kulkarni 4779*7e6ad469SVishal Kulkarni static int 4780*7e6ad469SVishal Kulkarni view_full_t5(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 4781*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf) 4782*7e6ad469SVishal Kulkarni { 4783*7e6ad469SVishal Kulkarni u32 sge_rsp_full, sge_req_full, sge_rx_full; 4784*7e6ad469SVishal Kulkarni u32 rx_fifo_cng, rx_pcmd_cng, rx_hdr_cng; 4785*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 4786*7e6ad469SVishal Kulkarni u32 pcie_rd_full, pcie_wr_full; 4787*7e6ad469SVishal Kulkarni u32 tx, rx, cs, es, pcie, sge; 4788*7e6ad469SVishal Kulkarni u32 cng0, cng1; 4789*7e6ad469SVishal Kulkarni int rc = 0; 4790*7e6ad469SVishal Kulkarni u32 *sp; 4791*7e6ad469SVishal Kulkarni 4792*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 4793*7e6ad469SVishal Kulkarni if (rc) 4794*7e6ad469SVishal Kulkarni return rc; 4795*7e6ad469SVishal Kulkarni 4796*7e6ad469SVishal Kulkarni sp = (u32 *)dc_buff.data; 4797*7e6ad469SVishal Kulkarni 4798*7e6ad469SVishal Kulkarni /* Collect Registers: 4799*7e6ad469SVishal Kulkarni * TP_DBG_SCHED_TX (0x7e40 + 0x6a), 4800*7e6ad469SVishal Kulkarni * TP_DBG_SCHED_RX (0x7e40 + 0x6b), 4801*7e6ad469SVishal Kulkarni * TP_DBG_CSIDE_INT (0x7e40 + 0x23f), 4802*7e6ad469SVishal Kulkarni * TP_DBG_ESIDE_INT (0x7e40 + 0x148), 4803*7e6ad469SVishal Kulkarni * PCIE_CDEBUG_INDEX[AppData0] (0x5a10 + 2), 4804*7e6ad469SVishal Kulkarni * SGE_DEBUG_DATA_HIGH_INDEX_10 (0x12a8) 4805*7e6ad469SVishal Kulkarni **/ 4806*7e6ad469SVishal Kulkarni tx = *sp; 4807*7e6ad469SVishal Kulkarni rx = *(sp + 1); 4808*7e6ad469SVishal Kulkarni cs = *(sp + 2); 4809*7e6ad469SVishal Kulkarni es = *(sp + 3); 4810*7e6ad469SVishal Kulkarni pcie = *(sp + 4); 4811*7e6ad469SVishal Kulkarni sge = *(sp + 5); 4812*7e6ad469SVishal Kulkarni 4813*7e6ad469SVishal Kulkarni pcie_rd_full = (pcie >> 8) & 0xf; 4814*7e6ad469SVishal Kulkarni pcie_wr_full = pcie & 0xf; 4815*7e6ad469SVishal Kulkarni 4816*7e6ad469SVishal Kulkarni /* OR together D_RdReqAFull and D_WrReqAFull for pcie */ 4817*7e6ad469SVishal Kulkarni 4818*7e6ad469SVishal Kulkarni /* sge debug_PD_RdRspAFull_d for each channel */ 4819*7e6ad469SVishal Kulkarni sge_rsp_full = ((sge >> 26) & 0xf); 4820*7e6ad469SVishal Kulkarni /* OR together sge debug_PD_RdReqAFull_d and debug PD_WrReqAFull_d */ 4821*7e6ad469SVishal Kulkarni sge_req_full = ((sge >> 22) & 0xf) | ((sge >> 18) & 0xf); 4822*7e6ad469SVishal Kulkarni sge_rx_full = (sge >> 30) & 0x3; 4823*7e6ad469SVishal Kulkarni 4824*7e6ad469SVishal Kulkarni rx_fifo_cng = (rx >> 20) & 0xf; 4825*7e6ad469SVishal Kulkarni rx_pcmd_cng = (rx >> 14) & 0x3; 4826*7e6ad469SVishal Kulkarni rx_hdr_cng = (rx >> 8) & 0xf; 4827*7e6ad469SVishal Kulkarni cng0 = (rx_fifo_cng & 1) | (rx_pcmd_cng & 1) | (rx_hdr_cng & 1); 4828*7e6ad469SVishal Kulkarni cng1 = ((rx_fifo_cng & 2) >> 1) | ((rx_pcmd_cng & 2) >> 1) | 4829*7e6ad469SVishal Kulkarni ((rx_hdr_cng & 2) >> 1); 4830*7e6ad469SVishal Kulkarni 4831*7e6ad469SVishal Kulkarni printf("\n"); 4832*7e6ad469SVishal Kulkarni /* TP resource reservation */ 4833*7e6ad469SVishal Kulkarni printf("Tx0 ==%1u=\\ /=%1u= Rx0\n", 4834*7e6ad469SVishal Kulkarni ((tx >> 28) & 1), ((rx >> 28) & 1)); 4835*7e6ad469SVishal Kulkarni printf("Tx1 ==%1u= | T | =%1u= Rx1\n", 4836*7e6ad469SVishal Kulkarni ((tx >> 29) & 1), ((rx >> 29) & 1)); 4837*7e6ad469SVishal Kulkarni printf("Tx2 ==%1u= | P | =%1u= Rx2\n", 4838*7e6ad469SVishal Kulkarni ((tx >> 30) & 1), ((rx >> 30) & 1)); 4839*7e6ad469SVishal Kulkarni printf("Tx3 ==%1u=/ \\=%1u= Rx3\n", 4840*7e6ad469SVishal Kulkarni ((tx >> 31) & 1), ((rx >> 31) & 1)); 4841*7e6ad469SVishal Kulkarni printf("\n"); 4842*7e6ad469SVishal Kulkarni 4843*7e6ad469SVishal Kulkarni /* TX path */ 4844*7e6ad469SVishal Kulkarni /* pcie bits 19:16 are D_RspAFull for each channel */ 4845*7e6ad469SVishal Kulkarni /* Tx is blocked when Responses from system cannot flow toward TP. */ 4846*7e6ad469SVishal Kulkarni printf("Tx0 P =%1u=%1u=\\ S ? U ==%1u=\\\n", 4847*7e6ad469SVishal Kulkarni ((pcie >> 16) & 1), (sge_rsp_full & 1), ((cs >> 24) & 1)); 4848*7e6ad469SVishal Kulkarni printf("Tx1 C =%1u=%1u= |G ? T ==%1u= | T\n", 4849*7e6ad469SVishal Kulkarni ((pcie >> 17) & 1), ((sge_rsp_full >> 1) & 1), 4850*7e6ad469SVishal Kulkarni ((cs >> 25) & 1)); 4851*7e6ad469SVishal Kulkarni printf("Tx2 I =%1u=%1u= |E ? X ==%1u= | P\n", 4852*7e6ad469SVishal Kulkarni ((pcie >> 18) & 1), ((sge_rsp_full >> 2) & 1), 4853*7e6ad469SVishal Kulkarni ((cs >> 26) & 1)); 4854*7e6ad469SVishal Kulkarni printf("Tx3 E =%1u=%1u=/ ? ==%1u=/\n", 4855*7e6ad469SVishal Kulkarni ((pcie >> 19) & 1), ((sge_rsp_full >> 3) & 1), 4856*7e6ad469SVishal Kulkarni ((cs >> 27) & 1)); 4857*7e6ad469SVishal Kulkarni printf("\n"); 4858*7e6ad469SVishal Kulkarni 4859*7e6ad469SVishal Kulkarni /* RX path */ 4860*7e6ad469SVishal Kulkarni /* Rx is blocked when sge and/or pcie cannot send requests to system. 4861*7e6ad469SVishal Kulkarni * */ 4862*7e6ad469SVishal Kulkarni printf(" Rd Wr\n"); 4863*7e6ad469SVishal Kulkarni printf("RX0 P /=%1u=%1u=%1u S <=%1u= C "\ 4864*7e6ad469SVishal Kulkarni "<=%1u= T <=T <=%1u= T /=%1u= M\n", 4865*7e6ad469SVishal Kulkarni ((pcie_rd_full >> 0) & 1), ((pcie_wr_full >> 0) & 1), 4866*7e6ad469SVishal Kulkarni ((sge_req_full >> 0) & 1), ((sge_rx_full >> 0) & 1), 4867*7e6ad469SVishal Kulkarni cng0, ((cs >> 20) & 1), ((es >> 16) & 1)); 4868*7e6ad469SVishal Kulkarni printf("RX1 C| =%1u=%1u=%1u G <=%1u= X "\ 4869*7e6ad469SVishal Kulkarni "<=%1u= C <=P <=%1u= E| =%1u= P\n", 4870*7e6ad469SVishal Kulkarni ((pcie_rd_full >> 1) & 1), ((pcie_wr_full >> 1) & 1), 4871*7e6ad469SVishal Kulkarni ((sge_req_full >> 1) & 1), ((sge_rx_full >> 1) & 1), 4872*7e6ad469SVishal Kulkarni cng1, ((cs >> 21) & 1), ((es >> 17) & 1)); 4873*7e6ad469SVishal Kulkarni printf("RX2 I| =%1u=%1u=%1u E "\ 4874*7e6ad469SVishal Kulkarni " | =%1u= S\n", 4875*7e6ad469SVishal Kulkarni ((pcie_rd_full >> 2) & 1), ((pcie_wr_full >> 2) & 1), 4876*7e6ad469SVishal Kulkarni ((sge_req_full >> 2) & 1), ((es >> 18) & 1)); 4877*7e6ad469SVishal Kulkarni printf("RX3 E \\=%1u=%1u=%1u "\ 4878*7e6ad469SVishal Kulkarni " \\=%1u=\n", 4879*7e6ad469SVishal Kulkarni ((pcie_rd_full >> 3) & 1), ((pcie_wr_full >> 3) & 1), 4880*7e6ad469SVishal Kulkarni ((sge_req_full >> 3) & 1), ((es >> 19) & 1)); 4881*7e6ad469SVishal Kulkarni printf("\n"); 4882*7e6ad469SVishal Kulkarni 4883*7e6ad469SVishal Kulkarni return rc; 4884*7e6ad469SVishal Kulkarni } 4885*7e6ad469SVishal Kulkarni 4886*7e6ad469SVishal Kulkarni int 4887*7e6ad469SVishal Kulkarni view_full(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 4888*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 4889*7e6ad469SVishal Kulkarni { 4890*7e6ad469SVishal Kulkarni int rc = -1; 4891*7e6ad469SVishal Kulkarni 4892*7e6ad469SVishal Kulkarni if (is_t5(chip)) 4893*7e6ad469SVishal Kulkarni rc = view_full_t5(pbuf, entity_hdr, cudbg_poutbuf); 4894*7e6ad469SVishal Kulkarni else if (is_t6(chip)) 4895*7e6ad469SVishal Kulkarni rc = view_full_t6(pbuf, entity_hdr, cudbg_poutbuf); 4896*7e6ad469SVishal Kulkarni 4897*7e6ad469SVishal Kulkarni return rc; 4898*7e6ad469SVishal Kulkarni } 4899*7e6ad469SVishal Kulkarni 4900*7e6ad469SVishal Kulkarni int 4901*7e6ad469SVishal Kulkarni view_vpd_data(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 4902*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 4903*7e6ad469SVishal Kulkarni { 4904*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 4905*7e6ad469SVishal Kulkarni struct struct_vpd_data *vpd_data; 4906*7e6ad469SVishal Kulkarni int rc = 0; 4907*7e6ad469SVishal Kulkarni 4908*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 4909*7e6ad469SVishal Kulkarni if (rc) 4910*7e6ad469SVishal Kulkarni return rc; 4911*7e6ad469SVishal Kulkarni 4912*7e6ad469SVishal Kulkarni vpd_data = (struct struct_vpd_data *) dc_buff.data; 4913*7e6ad469SVishal Kulkarni printf("MN %s\n", vpd_data->mn); 4914*7e6ad469SVishal Kulkarni printf("SN %s\n", vpd_data->sn); 4915*7e6ad469SVishal Kulkarni printf("BN %s\n", vpd_data->bn); 4916*7e6ad469SVishal Kulkarni printf("NA %s\n", vpd_data->na); 4917*7e6ad469SVishal Kulkarni printf("SCFG Version 0x%x\n", 4918*7e6ad469SVishal Kulkarni vpd_data->scfg_vers); 4919*7e6ad469SVishal Kulkarni printf("VPD Version 0x%x\n", 4920*7e6ad469SVishal Kulkarni vpd_data->vpd_vers); 4921*7e6ad469SVishal Kulkarni 4922*7e6ad469SVishal Kulkarni printf("Firmware Version: %d.%d.%d.%d\n", 4923*7e6ad469SVishal Kulkarni vpd_data->fw_major, vpd_data->fw_minor, vpd_data->fw_micro, 4924*7e6ad469SVishal Kulkarni vpd_data->fw_build); 4925*7e6ad469SVishal Kulkarni 4926*7e6ad469SVishal Kulkarni return rc; 4927*7e6ad469SVishal Kulkarni } 4928*7e6ad469SVishal Kulkarni 4929*7e6ad469SVishal Kulkarni int 4930*7e6ad469SVishal Kulkarni view_upload(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 4931*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 4932*7e6ad469SVishal Kulkarni { 4933*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 4934*7e6ad469SVishal Kulkarni int rc = 0; 4935*7e6ad469SVishal Kulkarni u32 *value; 4936*7e6ad469SVishal Kulkarni 4937*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 4938*7e6ad469SVishal Kulkarni if (rc) 4939*7e6ad469SVishal Kulkarni return rc; 4940*7e6ad469SVishal Kulkarni 4941*7e6ad469SVishal Kulkarni value = (u32 *) dc_buff.data; 4942*7e6ad469SVishal Kulkarni if (*value == 0xffffffff) { 4943*7e6ad469SVishal Kulkarni printf("uP load: <not available>\n"); 4944*7e6ad469SVishal Kulkarni goto err1; 4945*7e6ad469SVishal Kulkarni } 4946*7e6ad469SVishal Kulkarni 4947*7e6ad469SVishal Kulkarni printf("uP load: %d, %d, %d\n", 4948*7e6ad469SVishal Kulkarni (*value >> 0) & 0xff, 4949*7e6ad469SVishal Kulkarni (*value >> 8) & 0xff, 4950*7e6ad469SVishal Kulkarni (*value >> 16) & 0xff); 4951*7e6ad469SVishal Kulkarni 4952*7e6ad469SVishal Kulkarni err1: 4953*7e6ad469SVishal Kulkarni return rc; 4954*7e6ad469SVishal Kulkarni } 4955*7e6ad469SVishal Kulkarni 4956*7e6ad469SVishal Kulkarni static const char * 4957*7e6ad469SVishal Kulkarni cudbg_qdesc_qtype_to_str(enum cudbg_qdesc_qtype qtype) 4958*7e6ad469SVishal Kulkarni { 4959*7e6ad469SVishal Kulkarni switch (qtype) { 4960*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_NIC_TXQ: 4961*7e6ad469SVishal Kulkarni return "ETHERNET-TXQ"; 4962*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_NIC_RXQ: 4963*7e6ad469SVishal Kulkarni return "ETHERNET-RXQ"; 4964*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_NIC_FLQ: 4965*7e6ad469SVishal Kulkarni return "ETHERNET-FL"; 4966*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_CTRLQ: 4967*7e6ad469SVishal Kulkarni return "ETHERNET-CTRLQ"; 4968*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_FWEVTQ: 4969*7e6ad469SVishal Kulkarni return "FIRMWARE-EVENT-QUEUE"; 4970*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_INTRQ: 4971*7e6ad469SVishal Kulkarni return "NON-DATA-INTERRUPT-QUEUE"; 4972*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_PTP_TXQ: 4973*7e6ad469SVishal Kulkarni return "PTP-TXQ"; 4974*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_OFLD_TXQ: 4975*7e6ad469SVishal Kulkarni return "OFFLOAD-TXQ"; 4976*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_RDMA_RXQ: 4977*7e6ad469SVishal Kulkarni return "RDMA-RXQ"; 4978*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_RDMA_FLQ: 4979*7e6ad469SVishal Kulkarni return "RDMA-FL"; 4980*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_RDMA_CIQ: 4981*7e6ad469SVishal Kulkarni return "RDMA-CIQ"; 4982*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_ISCSI_RXQ: 4983*7e6ad469SVishal Kulkarni return "iSCSI-RXQ"; 4984*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_ISCSI_FLQ: 4985*7e6ad469SVishal Kulkarni return "iSCSI-FL"; 4986*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_ISCSIT_RXQ: 4987*7e6ad469SVishal Kulkarni return "iSCSIT-RXQ"; 4988*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_ISCSIT_FLQ: 4989*7e6ad469SVishal Kulkarni return "iSCSIT-FL"; 4990*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_CRYPTO_TXQ: 4991*7e6ad469SVishal Kulkarni return "CRYPTO-TXQ"; 4992*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_CRYPTO_RXQ: 4993*7e6ad469SVishal Kulkarni return "CRYPTO-RXQ"; 4994*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_CRYPTO_FLQ: 4995*7e6ad469SVishal Kulkarni return "CRYPTO-FL"; 4996*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_TLS_RXQ: 4997*7e6ad469SVishal Kulkarni return "TLS-RXQ"; 4998*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_TLS_FLQ: 4999*7e6ad469SVishal Kulkarni return "TLS-FL"; 5000*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_UNKNOWN: 5001*7e6ad469SVishal Kulkarni case CUDBG_QTYPE_MAX: 5002*7e6ad469SVishal Kulkarni return "UNKNOWN"; 5003*7e6ad469SVishal Kulkarni } 5004*7e6ad469SVishal Kulkarni 5005*7e6ad469SVishal Kulkarni return "UNKNOWN"; 5006*7e6ad469SVishal Kulkarni } 5007*7e6ad469SVishal Kulkarni 5008*7e6ad469SVishal Kulkarni static struct cudbg_qdesc_entry * 5009*7e6ad469SVishal Kulkarni cudbg_next_qdesc(struct cudbg_qdesc_entry *e) 5010*7e6ad469SVishal Kulkarni { 5011*7e6ad469SVishal Kulkarni return (struct cudbg_qdesc_entry *) 5012*7e6ad469SVishal Kulkarni ((u8 *)e + sizeof(*e) + e->data_size); 5013*7e6ad469SVishal Kulkarni } 5014*7e6ad469SVishal Kulkarni 5015*7e6ad469SVishal Kulkarni int 5016*7e6ad469SVishal Kulkarni view_qdesc(char *pbuf, struct cudbg_entity_hdr *entity_hdr, 5017*7e6ad469SVishal Kulkarni struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip) 5018*7e6ad469SVishal Kulkarni { 5019*7e6ad469SVishal Kulkarni struct cudbg_qdesc_entry *qdesc_entry; 5020*7e6ad469SVishal Kulkarni struct cudbg_qdesc_info *qdesc_info; 5021*7e6ad469SVishal Kulkarni struct cudbg_buffer c_buff, dc_buff; 5022*7e6ad469SVishal Kulkarni u8 zero_memory_128[128] = { 0 }; 5023*7e6ad469SVishal Kulkarni struct cudbg_ver_hdr *ver_hdr; 5024*7e6ad469SVishal Kulkarni u32 i, j, k, l, max_desc; 5025*7e6ad469SVishal Kulkarni u32 star_count = 0; 5026*7e6ad469SVishal Kulkarni int rc = 0; 5027*7e6ad469SVishal Kulkarni u8 *p; 5028*7e6ad469SVishal Kulkarni 5029*7e6ad469SVishal Kulkarni rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff); 5030*7e6ad469SVishal Kulkarni if (rc) 5031*7e6ad469SVishal Kulkarni return rc; 5032*7e6ad469SVishal Kulkarni 5033*7e6ad469SVishal Kulkarni ver_hdr = (struct cudbg_ver_hdr *)dc_buff.data; 5034*7e6ad469SVishal Kulkarni qdesc_info = (struct cudbg_qdesc_info *) 5035*7e6ad469SVishal Kulkarni (dc_buff.data + sizeof(*ver_hdr)); 5036*7e6ad469SVishal Kulkarni 5037*7e6ad469SVishal Kulkarni if (!qdesc_info->num_queues) { 5038*7e6ad469SVishal Kulkarni printf("No queues found\n"); 5039*7e6ad469SVishal Kulkarni goto err1; 5040*7e6ad469SVishal Kulkarni } 5041*7e6ad469SVishal Kulkarni 5042*7e6ad469SVishal Kulkarni qdesc_entry = (struct cudbg_qdesc_entry *) 5043*7e6ad469SVishal Kulkarni ((u8 *)qdesc_info + ver_hdr->size); 5044*7e6ad469SVishal Kulkarni 5045*7e6ad469SVishal Kulkarni for (i = 0; i < qdesc_info->num_queues; i++) { 5046*7e6ad469SVishal Kulkarni star_count = 0; 5047*7e6ad469SVishal Kulkarni printf( 5048*7e6ad469SVishal Kulkarni "\n\nQueue - %s, context-id: %u, desc-size: %u, desc-num: %u\n", 5049*7e6ad469SVishal Kulkarni cudbg_qdesc_qtype_to_str(qdesc_entry->qtype), 5050*7e6ad469SVishal Kulkarni qdesc_entry->qid, 5051*7e6ad469SVishal Kulkarni qdesc_entry->desc_size, 5052*7e6ad469SVishal Kulkarni qdesc_entry->num_desc); 5053*7e6ad469SVishal Kulkarni p = (u8 *)qdesc_entry + qdesc_info->qdesc_entry_size; 5054*7e6ad469SVishal Kulkarni 5055*7e6ad469SVishal Kulkarni for (j = 0; j < qdesc_entry->num_desc; j++) { 5056*7e6ad469SVishal Kulkarni k = 0; 5057*7e6ad469SVishal Kulkarni /* Below logic skips printing descriptors filled with 5058*7e6ad469SVishal Kulkarni * all zeros and replaces it with star 5059*7e6ad469SVishal Kulkarni */ 5060*7e6ad469SVishal Kulkarni if (!memcmp(p, zero_memory_128, qdesc_entry->desc_size)) { 5061*7e6ad469SVishal Kulkarni star_count++; 5062*7e6ad469SVishal Kulkarni if (star_count >= 2 && 5063*7e6ad469SVishal Kulkarni j != (qdesc_entry->num_desc - 1)) { 5064*7e6ad469SVishal Kulkarni /* Skip all consecutive descriptors 5065*7e6ad469SVishal Kulkarni * filled with zeros until the last 5066*7e6ad469SVishal Kulkarni * descriptor. 5067*7e6ad469SVishal Kulkarni */ 5068*7e6ad469SVishal Kulkarni p += qdesc_entry->desc_size; 5069*7e6ad469SVishal Kulkarni 5070*7e6ad469SVishal Kulkarni if (star_count == 2) { 5071*7e6ad469SVishal Kulkarni /* Print * for the second 5072*7e6ad469SVishal Kulkarni * consecutive descriptor 5073*7e6ad469SVishal Kulkarni * filled with zeros. 5074*7e6ad469SVishal Kulkarni */ 5075*7e6ad469SVishal Kulkarni printf("\n%-8s\n", "*"); 5076*7e6ad469SVishal Kulkarni } 5077*7e6ad469SVishal Kulkarni continue; 5078*7e6ad469SVishal Kulkarni } 5079*7e6ad469SVishal Kulkarni } else { 5080*7e6ad469SVishal Kulkarni /* Descriptor doesn't contain all zeros, so 5081*7e6ad469SVishal Kulkarni * restart skip logic. 5082*7e6ad469SVishal Kulkarni */ 5083*7e6ad469SVishal Kulkarni star_count = 0; 5084*7e6ad469SVishal Kulkarni } 5085*7e6ad469SVishal Kulkarni 5086*7e6ad469SVishal Kulkarni printf("\n%-8d:", j); 5087*7e6ad469SVishal Kulkarni while (k < qdesc_entry->desc_size) { 5088*7e6ad469SVishal Kulkarni max_desc = min(qdesc_entry->desc_size - k, 5089*7e6ad469SVishal Kulkarni sizeof(u32)); 5090*7e6ad469SVishal Kulkarni if (k && !(k % 32)) 5091*7e6ad469SVishal Kulkarni printf("\n%-9s", " "); 5092*7e6ad469SVishal Kulkarni if (!(k % 4)) 5093*7e6ad469SVishal Kulkarni printf(" "); 5094*7e6ad469SVishal Kulkarni for (l = 0; l < max_desc; l++, k++, p++) 5095*7e6ad469SVishal Kulkarni printf("%02x", *p); 5096*7e6ad469SVishal Kulkarni } 5097*7e6ad469SVishal Kulkarni } 5098*7e6ad469SVishal Kulkarni qdesc_entry = cudbg_next_qdesc(qdesc_entry); 5099*7e6ad469SVishal Kulkarni } 5100*7e6ad469SVishal Kulkarni 5101*7e6ad469SVishal Kulkarni err1: 5102*7e6ad469SVishal Kulkarni return rc; 5103*7e6ad469SVishal Kulkarni } 5104