1bf21cd93STycho Nightingale /*- 2*32640292SAndy Fiddaman * SPDX-License-Identifier: BSD-2-Clause 34c87aefeSPatrick Mooney * 4bf21cd93STycho Nightingale * Copyright (c) 2015 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> 5bf21cd93STycho Nightingale * All rights reserved. 6bf21cd93STycho Nightingale * 7bf21cd93STycho Nightingale * Redistribution and use in source and binary forms, with or without 8bf21cd93STycho Nightingale * modification, are permitted provided that the following conditions 9bf21cd93STycho Nightingale * are met: 10bf21cd93STycho Nightingale * 1. Redistributions of source code must retain the above copyright 11bf21cd93STycho Nightingale * notice, this list of conditions and the following disclaimer. 12bf21cd93STycho Nightingale * 2. Redistributions in binary form must reproduce the above copyright 13bf21cd93STycho Nightingale * notice, this list of conditions and the following disclaimer in the 14bf21cd93STycho Nightingale * documentation and/or other materials provided with the distribution. 15bf21cd93STycho Nightingale * 16bf21cd93STycho Nightingale * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 17bf21cd93STycho Nightingale * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18bf21cd93STycho Nightingale * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19bf21cd93STycho Nightingale * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20bf21cd93STycho Nightingale * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21bf21cd93STycho Nightingale * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22bf21cd93STycho Nightingale * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23bf21cd93STycho Nightingale * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24bf21cd93STycho Nightingale * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25bf21cd93STycho Nightingale * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26bf21cd93STycho Nightingale * SUCH DAMAGE. 27bf21cd93STycho Nightingale */ 28bf21cd93STycho Nightingale 29bf21cd93STycho Nightingale #ifndef _VGA_H_ 30bf21cd93STycho Nightingale #define _VGA_H_ 31bf21cd93STycho Nightingale 32bf21cd93STycho Nightingale #define VGA_IOPORT_START 0x3c0 33bf21cd93STycho Nightingale #define VGA_IOPORT_END 0x3df 34bf21cd93STycho Nightingale 35bf21cd93STycho Nightingale /* General registers */ 36bf21cd93STycho Nightingale #define GEN_INPUT_STS0_PORT 0x3c2 37bf21cd93STycho Nightingale #define GEN_FEATURE_CTRL_PORT 0x3ca 38bf21cd93STycho Nightingale #define GEN_MISC_OUTPUT_PORT 0x3cc 39bf21cd93STycho Nightingale #define GEN_INPUT_STS1_MONO_PORT 0x3ba 40bf21cd93STycho Nightingale #define GEN_INPUT_STS1_COLOR_PORT 0x3da 414c87aefeSPatrick Mooney #define GEN_IS1_VR 0x08 /* Vertical retrace */ 424c87aefeSPatrick Mooney #define GEN_IS1_DE 0x01 /* Display enable not */ 43bf21cd93STycho Nightingale 44bf21cd93STycho Nightingale /* Attribute controller registers. */ 45bf21cd93STycho Nightingale #define ATC_IDX_PORT 0x3c0 46bf21cd93STycho Nightingale #define ATC_DATA_PORT 0x3c1 47bf21cd93STycho Nightingale 48bf21cd93STycho Nightingale #define ATC_IDX_MASK 0x1f 49bf21cd93STycho Nightingale #define ATC_PALETTE0 0 50bf21cd93STycho Nightingale #define ATC_PALETTE15 15 51bf21cd93STycho Nightingale #define ATC_MODE_CONTROL 16 524c87aefeSPatrick Mooney #define ATC_MC_IPS 0x80 /* Internal palette size */ 534c87aefeSPatrick Mooney #define ATC_MC_GA 0x01 /* Graphics/alphanumeric */ 54bf21cd93STycho Nightingale #define ATC_OVERSCAN_COLOR 17 55bf21cd93STycho Nightingale #define ATC_COLOR_PLANE_ENABLE 18 56bf21cd93STycho Nightingale #define ATC_HORIZ_PIXEL_PANNING 19 57bf21cd93STycho Nightingale #define ATC_COLOR_SELECT 20 584c87aefeSPatrick Mooney #define ATC_CS_C67 0x0c /* Color select bits 6+7 */ 594c87aefeSPatrick Mooney #define ATC_CS_C45 0x03 /* Color select bits 4+5 */ 60bf21cd93STycho Nightingale 61bf21cd93STycho Nightingale /* Sequencer registers. */ 62bf21cd93STycho Nightingale #define SEQ_IDX_PORT 0x3c4 63bf21cd93STycho Nightingale #define SEQ_DATA_PORT 0x3c5 64bf21cd93STycho Nightingale 65bf21cd93STycho Nightingale #define SEQ_RESET 0 66bf21cd93STycho Nightingale #define SEQ_RESET_ASYNC 0x1 67bf21cd93STycho Nightingale #define SEQ_RESET_SYNC 0x2 68bf21cd93STycho Nightingale #define SEQ_CLOCKING_MODE 1 694c87aefeSPatrick Mooney #define SEQ_CM_SO 0x20 /* Screen off */ 704c87aefeSPatrick Mooney #define SEQ_CM_89 0x01 /* 8/9 dot clock */ 71bf21cd93STycho Nightingale #define SEQ_MAP_MASK 2 72bf21cd93STycho Nightingale #define SEQ_CHAR_MAP_SELECT 3 734c87aefeSPatrick Mooney #define SEQ_CMS_SAH 0x20 /* Char map A bit 2 */ 744c87aefeSPatrick Mooney #define SEQ_CMS_SAH_SHIFT 5 754c87aefeSPatrick Mooney #define SEQ_CMS_SA 0x0c /* Char map A bits 0+1 */ 764c87aefeSPatrick Mooney #define SEQ_CMS_SA_SHIFT 2 774c87aefeSPatrick Mooney #define SEQ_CMS_SBH 0x10 /* Char map B bit 2 */ 784c87aefeSPatrick Mooney #define SEQ_CMS_SBH_SHIFT 4 794c87aefeSPatrick Mooney #define SEQ_CMS_SB 0x03 /* Char map B bits 0+1 */ 804c87aefeSPatrick Mooney #define SEQ_CMS_SB_SHIFT 0 81bf21cd93STycho Nightingale #define SEQ_MEMORY_MODE 4 824c87aefeSPatrick Mooney #define SEQ_MM_C4 0x08 /* Chain 4 */ 834c87aefeSPatrick Mooney #define SEQ_MM_OE 0x04 /* Odd/even */ 844c87aefeSPatrick Mooney #define SEQ_MM_EM 0x02 /* Extended memory */ 85bf21cd93STycho Nightingale 86bf21cd93STycho Nightingale /* Graphics controller registers. */ 87bf21cd93STycho Nightingale #define GC_IDX_PORT 0x3ce 88bf21cd93STycho Nightingale #define GC_DATA_PORT 0x3cf 89bf21cd93STycho Nightingale 90bf21cd93STycho Nightingale #define GC_SET_RESET 0 91bf21cd93STycho Nightingale #define GC_ENABLE_SET_RESET 1 92bf21cd93STycho Nightingale #define GC_COLOR_COMPARE 2 93bf21cd93STycho Nightingale #define GC_DATA_ROTATE 3 94bf21cd93STycho Nightingale #define GC_READ_MAP_SELECT 4 95bf21cd93STycho Nightingale #define GC_MODE 5 964c87aefeSPatrick Mooney #define GC_MODE_OE 0x10 /* Odd/even */ 974c87aefeSPatrick Mooney #define GC_MODE_C4 0x04 /* Chain 4 */ 98bf21cd93STycho Nightingale 99bf21cd93STycho Nightingale #define GC_MISCELLANEOUS 6 1004c87aefeSPatrick Mooney #define GC_MISC_GM 0x01 /* Graphics/alphanumeric */ 1014c87aefeSPatrick Mooney #define GC_MISC_MM 0x0c /* memory map */ 1024c87aefeSPatrick Mooney #define GC_MISC_MM_SHIFT 2 103bf21cd93STycho Nightingale #define GC_COLOR_DONT_CARE 7 104bf21cd93STycho Nightingale #define GC_BIT_MASK 8 105bf21cd93STycho Nightingale 106bf21cd93STycho Nightingale /* CRT controller registers. */ 107bf21cd93STycho Nightingale #define CRTC_IDX_MONO_PORT 0x3b4 108bf21cd93STycho Nightingale #define CRTC_DATA_MONO_PORT 0x3b5 109bf21cd93STycho Nightingale #define CRTC_IDX_COLOR_PORT 0x3d4 110bf21cd93STycho Nightingale #define CRTC_DATA_COLOR_PORT 0x3d5 111bf21cd93STycho Nightingale 112bf21cd93STycho Nightingale #define CRTC_HORIZ_TOTAL 0 113bf21cd93STycho Nightingale #define CRTC_HORIZ_DISP_END 1 114bf21cd93STycho Nightingale #define CRTC_START_HORIZ_BLANK 2 115bf21cd93STycho Nightingale #define CRTC_END_HORIZ_BLANK 3 116bf21cd93STycho Nightingale #define CRTC_START_HORIZ_RETRACE 4 117bf21cd93STycho Nightingale #define CRTC_END_HORIZ_RETRACE 5 118bf21cd93STycho Nightingale #define CRTC_VERT_TOTAL 6 119bf21cd93STycho Nightingale #define CRTC_OVERFLOW 7 1204c87aefeSPatrick Mooney #define CRTC_OF_VRS9 0x80 /* VRS bit 9 */ 1214c87aefeSPatrick Mooney #define CRTC_OF_VRS9_SHIFT 7 1224c87aefeSPatrick Mooney #define CRTC_OF_VDE9 0x40 /* VDE bit 9 */ 1234c87aefeSPatrick Mooney #define CRTC_OF_VDE9_SHIFT 6 1244c87aefeSPatrick Mooney #define CRTC_OF_VRS8 0x04 /* VRS bit 8 */ 1254c87aefeSPatrick Mooney #define CRTC_OF_VRS8_SHIFT 2 1264c87aefeSPatrick Mooney #define CRTC_OF_VDE8 0x02 /* VDE bit 8 */ 1274c87aefeSPatrick Mooney #define CRTC_OF_VDE8_SHIFT 1 128bf21cd93STycho Nightingale #define CRTC_PRESET_ROW_SCAN 8 129bf21cd93STycho Nightingale #define CRTC_MAX_SCAN_LINE 9 1304c87aefeSPatrick Mooney #define CRTC_MSL_MSL 0x1f 131bf21cd93STycho Nightingale #define CRTC_CURSOR_START 10 1324c87aefeSPatrick Mooney #define CRTC_CS_CO 0x20 /* Cursor off */ 1334c87aefeSPatrick Mooney #define CRTC_CS_CS 0x1f /* Cursor start */ 134bf21cd93STycho Nightingale #define CRTC_CURSOR_END 11 1354c87aefeSPatrick Mooney #define CRTC_CE_CE 0x1f /* Cursor end */ 136bf21cd93STycho Nightingale #define CRTC_START_ADDR_HIGH 12 137bf21cd93STycho Nightingale #define CRTC_START_ADDR_LOW 13 138bf21cd93STycho Nightingale #define CRTC_CURSOR_LOC_HIGH 14 139bf21cd93STycho Nightingale #define CRTC_CURSOR_LOC_LOW 15 140bf21cd93STycho Nightingale #define CRTC_VERT_RETRACE_START 16 141bf21cd93STycho Nightingale #define CRTC_VERT_RETRACE_END 17 1424c87aefeSPatrick Mooney #define CRTC_VRE_MASK 0xf 143bf21cd93STycho Nightingale #define CRTC_VERT_DISP_END 18 144bf21cd93STycho Nightingale #define CRTC_OFFSET 19 145bf21cd93STycho Nightingale #define CRTC_UNDERLINE_LOC 20 146bf21cd93STycho Nightingale #define CRTC_START_VERT_BLANK 21 147bf21cd93STycho Nightingale #define CRTC_END_VERT_BLANK 22 148bf21cd93STycho Nightingale #define CRTC_MODE_CONTROL 23 1494c87aefeSPatrick Mooney #define CRTC_MC_TE 0x80 /* Timing enable */ 150bf21cd93STycho Nightingale #define CRTC_LINE_COMPARE 24 151bf21cd93STycho Nightingale 152bf21cd93STycho Nightingale /* DAC registers */ 153bf21cd93STycho Nightingale #define DAC_MASK 0x3c6 154bf21cd93STycho Nightingale #define DAC_IDX_RD_PORT 0x3c7 155bf21cd93STycho Nightingale #define DAC_IDX_WR_PORT 0x3c8 156bf21cd93STycho Nightingale #define DAC_DATA_PORT 0x3c9 157bf21cd93STycho Nightingale 1584c87aefeSPatrick Mooney void *vga_init(int io_only); 159bf21cd93STycho Nightingale 160bf21cd93STycho Nightingale #endif /* _VGA_H_ */ 161