1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Copyright (c) 2015-2016 Alexander Motin <mav@FreeBSD.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
34 #include <sys/stat.h>
35 #include <sys/uio.h>
36 #include <sys/ioctl.h>
37 #include <sys/disk.h>
38 #include <sys/ata.h>
39 #include <sys/endian.h>
40
41 #include <errno.h>
42 #include <fcntl.h>
43 #include <stdio.h>
44 #include <stdlib.h>
45 #include <stdint.h>
46 #include <string.h>
47 #include <strings.h>
48 #include <unistd.h>
49 #include <assert.h>
50 #include <pthread.h>
51 #include <pthread_np.h>
52 #include <inttypes.h>
53 #include <md5.h>
54
55 #include "bhyverun.h"
56 #include "config.h"
57 #include "debug.h"
58 #include "pci_emul.h"
59 #include "ahci.h"
60 #include "block_if.h"
61
62 #define DEF_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
63 #define MAX_PORTS 32 /* AHCI supports 32 ports */
64
65 #define PxSIG_ATA 0x00000101 /* ATA drive */
66 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
67
68 enum sata_fis_type {
69 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
70 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
71 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
72 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
73 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
74 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
75 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
76 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
77 };
78
79 /*
80 * SCSI opcodes
81 */
82 #define TEST_UNIT_READY 0x00
83 #define REQUEST_SENSE 0x03
84 #define INQUIRY 0x12
85 #define START_STOP_UNIT 0x1B
86 #define PREVENT_ALLOW 0x1E
87 #define READ_CAPACITY 0x25
88 #define READ_10 0x28
89 #define POSITION_TO_ELEMENT 0x2B
90 #define READ_TOC 0x43
91 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
92 #define MODE_SENSE_10 0x5A
93 #define REPORT_LUNS 0xA0
94 #define READ_12 0xA8
95 #define READ_CD 0xBE
96
97 /*
98 * SCSI mode page codes
99 */
100 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
101 #define MODEPAGE_CD_CAPABILITIES 0x2A
102
103 /*
104 * ATA commands
105 */
106 #define ATA_SF_ENAB_SATA_SF 0x10
107 #define ATA_SATA_SF_AN 0x05
108 #define ATA_SF_DIS_SATA_SF 0x90
109
110 /*
111 * Debug printf
112 */
113 #ifdef AHCI_DEBUG
114 static FILE *dbg;
115 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
116 #else
117 #define DPRINTF(format, arg...)
118 #endif
119 #define WPRINTF(format, arg...) printf(format, ##arg)
120
121 #define AHCI_PORT_IDENT 20 + 1
122
123 struct ahci_ioreq {
124 struct blockif_req io_req;
125 struct ahci_port *io_pr;
126 STAILQ_ENTRY(ahci_ioreq) io_flist;
127 TAILQ_ENTRY(ahci_ioreq) io_blist;
128 uint8_t *cfis;
129 uint32_t len;
130 uint32_t done;
131 int slot;
132 int more;
133 };
134
135 struct ahci_port {
136 struct blockif_ctxt *bctx;
137 struct pci_ahci_softc *pr_sc;
138 struct ata_params ata_ident;
139 uint8_t *cmd_lst;
140 uint8_t *rfis;
141 int port;
142 int atapi;
143 int reset;
144 int waitforclear;
145 int mult_sectors;
146 uint8_t xfermode;
147 uint8_t err_cfis[20];
148 uint8_t sense_key;
149 uint8_t asc;
150 u_int ccs;
151 uint32_t pending;
152
153 uint32_t clb;
154 uint32_t clbu;
155 uint32_t fb;
156 uint32_t fbu;
157 uint32_t is;
158 uint32_t ie;
159 uint32_t cmd;
160 uint32_t unused0;
161 uint32_t tfd;
162 uint32_t sig;
163 uint32_t ssts;
164 uint32_t sctl;
165 uint32_t serr;
166 uint32_t sact;
167 uint32_t ci;
168 uint32_t sntf;
169 uint32_t fbs;
170
171 /*
172 * i/o request info
173 */
174 struct ahci_ioreq *ioreq;
175 int ioqsz;
176 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
177 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
178 };
179
180 struct ahci_cmd_hdr {
181 uint16_t flags;
182 uint16_t prdtl;
183 uint32_t prdbc;
184 uint64_t ctba;
185 uint32_t reserved[4];
186 };
187
188 struct ahci_prdt_entry {
189 uint64_t dba;
190 uint32_t reserved;
191 #define DBCMASK 0x3fffff
192 uint32_t dbc;
193 };
194
195 struct pci_ahci_softc {
196 struct pci_devinst *asc_pi;
197 pthread_mutex_t mtx;
198 int ports;
199 uint32_t cap;
200 uint32_t ghc;
201 uint32_t is;
202 uint32_t pi;
203 uint32_t vs;
204 uint32_t ccc_ctl;
205 uint32_t ccc_pts;
206 uint32_t em_loc;
207 uint32_t em_ctl;
208 uint32_t cap2;
209 uint32_t bohc;
210 uint32_t lintr;
211 struct ahci_port port[MAX_PORTS];
212 };
213 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
214
215 static void ahci_handle_port(struct ahci_port *p);
216
lba_to_msf(uint8_t * buf,int lba)217 static inline void lba_to_msf(uint8_t *buf, int lba)
218 {
219 lba += 150;
220 buf[0] = (lba / 75) / 60;
221 buf[1] = (lba / 75) % 60;
222 buf[2] = lba % 75;
223 }
224
225 /*
226 * Generate HBA interrupts on global IS register write.
227 */
228 static void
ahci_generate_intr(struct pci_ahci_softc * sc,uint32_t mask)229 ahci_generate_intr(struct pci_ahci_softc *sc, uint32_t mask)
230 {
231 struct pci_devinst *pi = sc->asc_pi;
232 struct ahci_port *p;
233 int i, nmsg;
234 uint32_t mmask;
235
236 /* Update global IS from PxIS/PxIE. */
237 for (i = 0; i < sc->ports; i++) {
238 p = &sc->port[i];
239 if (p->is & p->ie)
240 sc->is |= (1 << i);
241 }
242 DPRINTF("%s(%08x) %08x", __func__, mask, sc->is);
243
244 /* If there is nothing enabled -- clear legacy interrupt and exit. */
245 if (sc->is == 0 || (sc->ghc & AHCI_GHC_IE) == 0) {
246 if (sc->lintr) {
247 pci_lintr_deassert(pi);
248 sc->lintr = 0;
249 }
250 return;
251 }
252
253 /* If there is anything and no MSI -- assert legacy interrupt. */
254 nmsg = pci_msi_maxmsgnum(pi);
255 if (nmsg == 0) {
256 if (!sc->lintr) {
257 sc->lintr = 1;
258 pci_lintr_assert(pi);
259 }
260 return;
261 }
262
263 /* Assert respective MSIs for ports that were touched. */
264 for (i = 0; i < nmsg; i++) {
265 if (sc->ports <= nmsg || i < nmsg - 1)
266 mmask = 1 << i;
267 else
268 mmask = 0xffffffff << i;
269 if (sc->is & mask && mmask & mask)
270 pci_generate_msi(pi, i);
271 }
272 }
273
274 /*
275 * Generate HBA interrupt on specific port event.
276 */
277 static void
ahci_port_intr(struct ahci_port * p)278 ahci_port_intr(struct ahci_port *p)
279 {
280 struct pci_ahci_softc *sc = p->pr_sc;
281 struct pci_devinst *pi = sc->asc_pi;
282 int nmsg;
283
284 DPRINTF("%s(%d) %08x/%08x %08x", __func__,
285 p->port, p->is, p->ie, sc->is);
286
287 /* If there is nothing enabled -- we are done. */
288 if ((p->is & p->ie) == 0)
289 return;
290
291 /* In case of non-shared MSI always generate interrupt. */
292 nmsg = pci_msi_maxmsgnum(pi);
293 if (sc->ports <= nmsg || p->port < nmsg - 1) {
294 sc->is |= (1 << p->port);
295 if ((sc->ghc & AHCI_GHC_IE) == 0)
296 return;
297 pci_generate_msi(pi, p->port);
298 return;
299 }
300
301 /* If IS for this port is already set -- do nothing. */
302 if (sc->is & (1 << p->port))
303 return;
304
305 sc->is |= (1 << p->port);
306
307 /* If interrupts are enabled -- generate one. */
308 if ((sc->ghc & AHCI_GHC_IE) == 0)
309 return;
310 if (nmsg > 0) {
311 pci_generate_msi(pi, nmsg - 1);
312 } else if (!sc->lintr) {
313 sc->lintr = 1;
314 pci_lintr_assert(pi);
315 }
316 }
317
318 static void
ahci_write_fis(struct ahci_port * p,enum sata_fis_type ft,uint8_t * fis)319 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
320 {
321 int offset, len, irq;
322
323 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
324 return;
325
326 switch (ft) {
327 case FIS_TYPE_REGD2H:
328 offset = 0x40;
329 len = 20;
330 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_DHR : 0;
331 break;
332 case FIS_TYPE_SETDEVBITS:
333 offset = 0x58;
334 len = 8;
335 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_SDB : 0;
336 break;
337 case FIS_TYPE_PIOSETUP:
338 offset = 0x20;
339 len = 20;
340 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_PS : 0;
341 break;
342 default:
343 WPRINTF("unsupported fis type %d", ft);
344 return;
345 }
346 if (fis[2] & ATA_S_ERROR) {
347 p->waitforclear = 1;
348 irq |= AHCI_P_IX_TFE;
349 }
350 memcpy(p->rfis + offset, fis, len);
351 if (irq) {
352 if (~p->is & irq) {
353 p->is |= irq;
354 ahci_port_intr(p);
355 }
356 }
357 }
358
359 static void
ahci_write_fis_piosetup(struct ahci_port * p)360 ahci_write_fis_piosetup(struct ahci_port *p)
361 {
362 uint8_t fis[20];
363
364 memset(fis, 0, sizeof(fis));
365 fis[0] = FIS_TYPE_PIOSETUP;
366 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
367 }
368
369 static void
ahci_write_fis_sdb(struct ahci_port * p,int slot,uint8_t * cfis,uint32_t tfd)370 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
371 {
372 uint8_t fis[8];
373 uint8_t error;
374
375 error = (tfd >> 8) & 0xff;
376 tfd &= 0x77;
377 memset(fis, 0, sizeof(fis));
378 fis[0] = FIS_TYPE_SETDEVBITS;
379 fis[1] = (1 << 6);
380 fis[2] = tfd;
381 fis[3] = error;
382 if (fis[2] & ATA_S_ERROR) {
383 p->err_cfis[0] = slot;
384 p->err_cfis[2] = tfd;
385 p->err_cfis[3] = error;
386 memcpy(&p->err_cfis[4], cfis + 4, 16);
387 } else {
388 *(uint32_t *)(fis + 4) = (1 << slot);
389 p->sact &= ~(1 << slot);
390 }
391 p->tfd &= ~0x77;
392 p->tfd |= tfd;
393 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
394 }
395
396 static void
ahci_write_fis_d2h(struct ahci_port * p,int slot,uint8_t * cfis,uint32_t tfd)397 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
398 {
399 uint8_t fis[20];
400 uint8_t error;
401
402 error = (tfd >> 8) & 0xff;
403 memset(fis, 0, sizeof(fis));
404 fis[0] = FIS_TYPE_REGD2H;
405 fis[1] = (1 << 6);
406 fis[2] = tfd & 0xff;
407 fis[3] = error;
408 fis[4] = cfis[4];
409 fis[5] = cfis[5];
410 fis[6] = cfis[6];
411 fis[7] = cfis[7];
412 fis[8] = cfis[8];
413 fis[9] = cfis[9];
414 fis[10] = cfis[10];
415 fis[11] = cfis[11];
416 fis[12] = cfis[12];
417 fis[13] = cfis[13];
418 if (fis[2] & ATA_S_ERROR) {
419 p->err_cfis[0] = 0x80;
420 p->err_cfis[2] = tfd & 0xff;
421 p->err_cfis[3] = error;
422 memcpy(&p->err_cfis[4], cfis + 4, 16);
423 } else
424 p->ci &= ~(1 << slot);
425 p->tfd = tfd;
426 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
427 }
428
429 static void
ahci_write_fis_d2h_ncq(struct ahci_port * p,int slot)430 ahci_write_fis_d2h_ncq(struct ahci_port *p, int slot)
431 {
432 uint8_t fis[20];
433
434 p->tfd = ATA_S_READY | ATA_S_DSC;
435 memset(fis, 0, sizeof(fis));
436 fis[0] = FIS_TYPE_REGD2H;
437 fis[1] = 0; /* No interrupt */
438 fis[2] = p->tfd; /* Status */
439 fis[3] = 0; /* No error */
440 p->ci &= ~(1 << slot);
441 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
442 }
443
444 static void
ahci_write_reset_fis_d2h(struct ahci_port * p)445 ahci_write_reset_fis_d2h(struct ahci_port *p)
446 {
447 uint8_t fis[20];
448
449 memset(fis, 0, sizeof(fis));
450 fis[0] = FIS_TYPE_REGD2H;
451 fis[3] = 1;
452 fis[4] = 1;
453 if (p->atapi) {
454 fis[5] = 0x14;
455 fis[6] = 0xeb;
456 }
457 fis[12] = 1;
458 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
459 }
460
461 static void
ahci_check_stopped(struct ahci_port * p)462 ahci_check_stopped(struct ahci_port *p)
463 {
464 /*
465 * If we are no longer processing the command list and nothing
466 * is in-flight, clear the running bit, the current command
467 * slot, the command issue and active bits.
468 */
469 if (!(p->cmd & AHCI_P_CMD_ST)) {
470 if (p->pending == 0) {
471 p->ccs = 0;
472 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
473 p->ci = 0;
474 p->sact = 0;
475 p->waitforclear = 0;
476 }
477 }
478 }
479
480 static void
ahci_port_stop(struct ahci_port * p)481 ahci_port_stop(struct ahci_port *p)
482 {
483 struct ahci_ioreq *aior;
484 uint8_t *cfis;
485 int slot;
486 int error;
487
488 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
489
490 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
491 /*
492 * Try to cancel the outstanding blockif request.
493 */
494 error = blockif_cancel(p->bctx, &aior->io_req);
495 if (error != 0)
496 continue;
497
498 slot = aior->slot;
499 cfis = aior->cfis;
500 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
501 cfis[2] == ATA_READ_FPDMA_QUEUED ||
502 cfis[2] == ATA_SEND_FPDMA_QUEUED)
503 p->sact &= ~(1 << slot); /* NCQ */
504 else
505 p->ci &= ~(1 << slot);
506
507 /*
508 * This command is now done.
509 */
510 p->pending &= ~(1 << slot);
511
512 /*
513 * Delete the blockif request from the busy list
514 */
515 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
516
517 /*
518 * Move the blockif request back to the free list
519 */
520 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
521 }
522
523 ahci_check_stopped(p);
524 }
525
526 static void
ahci_port_reset(struct ahci_port * pr)527 ahci_port_reset(struct ahci_port *pr)
528 {
529 pr->serr = 0;
530 pr->sact = 0;
531 pr->xfermode = ATA_UDMA6;
532 pr->mult_sectors = 128;
533
534 if (!pr->bctx) {
535 pr->ssts = ATA_SS_DET_NO_DEVICE;
536 pr->sig = 0xFFFFFFFF;
537 pr->tfd = 0x7F;
538 return;
539 }
540 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE;
541 if (pr->sctl & ATA_SC_SPD_MASK)
542 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK);
543 else
544 pr->ssts |= ATA_SS_SPD_GEN3;
545 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
546 if (!pr->atapi) {
547 pr->sig = PxSIG_ATA;
548 pr->tfd |= ATA_S_READY;
549 } else
550 pr->sig = PxSIG_ATAPI;
551 ahci_write_reset_fis_d2h(pr);
552 }
553
554 static void
ahci_reset(struct pci_ahci_softc * sc)555 ahci_reset(struct pci_ahci_softc *sc)
556 {
557 int i;
558
559 sc->ghc = AHCI_GHC_AE;
560 sc->is = 0;
561
562 if (sc->lintr) {
563 pci_lintr_deassert(sc->asc_pi);
564 sc->lintr = 0;
565 }
566
567 for (i = 0; i < sc->ports; i++) {
568 sc->port[i].ie = 0;
569 sc->port[i].is = 0;
570 sc->port[i].cmd = (AHCI_P_CMD_SUD | AHCI_P_CMD_POD);
571 if (sc->port[i].bctx)
572 sc->port[i].cmd |= AHCI_P_CMD_CPS;
573 sc->port[i].sctl = 0;
574 ahci_port_reset(&sc->port[i]);
575 }
576 }
577
578 static void
ata_string(uint8_t * dest,const char * src,int len)579 ata_string(uint8_t *dest, const char *src, int len)
580 {
581 int i;
582
583 for (i = 0; i < len; i++) {
584 if (*src)
585 dest[i ^ 1] = *src++;
586 else
587 dest[i ^ 1] = ' ';
588 }
589 }
590
591 static void
atapi_string(uint8_t * dest,const char * src,int len)592 atapi_string(uint8_t *dest, const char *src, int len)
593 {
594 int i;
595
596 for (i = 0; i < len; i++) {
597 if (*src)
598 dest[i] = *src++;
599 else
600 dest[i] = ' ';
601 }
602 }
603
604 /*
605 * Build up the iovec based on the PRDT, 'done' and 'len'.
606 */
607 static void
ahci_build_iov(struct ahci_port * p,struct ahci_ioreq * aior,struct ahci_prdt_entry * prdt,uint16_t prdtl)608 ahci_build_iov(struct ahci_port *p, struct ahci_ioreq *aior,
609 struct ahci_prdt_entry *prdt, uint16_t prdtl)
610 {
611 struct blockif_req *breq = &aior->io_req;
612 uint32_t dbcsz, extra, left, skip, todo;
613 int i, j;
614
615 assert(aior->len >= aior->done);
616
617 /* Copy part of PRDT between 'done' and 'len' bytes into the iov. */
618 skip = aior->done;
619 left = aior->len - aior->done;
620 todo = 0;
621 for (i = 0, j = 0; i < prdtl && j < BLOCKIF_IOV_MAX && left > 0;
622 i++, prdt++) {
623 dbcsz = (prdt->dbc & DBCMASK) + 1;
624 /* Skip already done part of the PRDT */
625 if (dbcsz <= skip) {
626 skip -= dbcsz;
627 continue;
628 }
629 dbcsz -= skip;
630 if (dbcsz > left)
631 dbcsz = left;
632 breq->br_iov[j].iov_base = paddr_guest2host(ahci_ctx(p->pr_sc),
633 prdt->dba + skip, dbcsz);
634 breq->br_iov[j].iov_len = dbcsz;
635 todo += dbcsz;
636 left -= dbcsz;
637 skip = 0;
638 j++;
639 }
640
641 /* If we got limited by IOV length, round I/O down to sector size. */
642 if (j == BLOCKIF_IOV_MAX) {
643 extra = todo % blockif_sectsz(p->bctx);
644 todo -= extra;
645 assert(todo > 0);
646 while (extra > 0) {
647 if (breq->br_iov[j - 1].iov_len > extra) {
648 breq->br_iov[j - 1].iov_len -= extra;
649 break;
650 }
651 extra -= breq->br_iov[j - 1].iov_len;
652 j--;
653 }
654 }
655
656 breq->br_iovcnt = j;
657 breq->br_resid = todo;
658 aior->done += todo;
659 aior->more = (aior->done < aior->len && i < prdtl);
660 }
661
662 static void
ahci_handle_rw(struct ahci_port * p,int slot,uint8_t * cfis,uint32_t done)663 ahci_handle_rw(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
664 {
665 struct ahci_ioreq *aior;
666 struct blockif_req *breq;
667 struct ahci_prdt_entry *prdt;
668 struct ahci_cmd_hdr *hdr;
669 uint64_t lba;
670 uint32_t len;
671 int err, first, ncq, readop;
672
673 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
674 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
675 ncq = 0;
676 readop = 1;
677 first = (done == 0);
678
679 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 ||
680 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 ||
681 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
682 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
683 readop = 0;
684
685 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
686 cfis[2] == ATA_READ_FPDMA_QUEUED) {
687 lba = ((uint64_t)cfis[10] << 40) |
688 ((uint64_t)cfis[9] << 32) |
689 ((uint64_t)cfis[8] << 24) |
690 ((uint64_t)cfis[6] << 16) |
691 ((uint64_t)cfis[5] << 8) |
692 cfis[4];
693 len = cfis[11] << 8 | cfis[3];
694 if (!len)
695 len = 65536;
696 ncq = 1;
697 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 ||
698 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 ||
699 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
700 lba = ((uint64_t)cfis[10] << 40) |
701 ((uint64_t)cfis[9] << 32) |
702 ((uint64_t)cfis[8] << 24) |
703 ((uint64_t)cfis[6] << 16) |
704 ((uint64_t)cfis[5] << 8) |
705 cfis[4];
706 len = cfis[13] << 8 | cfis[12];
707 if (!len)
708 len = 65536;
709 } else {
710 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
711 (cfis[5] << 8) | cfis[4];
712 len = cfis[12];
713 if (!len)
714 len = 256;
715 }
716 lba *= blockif_sectsz(p->bctx);
717 len *= blockif_sectsz(p->bctx);
718
719 /* Pull request off free list */
720 aior = STAILQ_FIRST(&p->iofhd);
721 assert(aior != NULL);
722 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
723
724 aior->cfis = cfis;
725 aior->slot = slot;
726 aior->len = len;
727 aior->done = done;
728 breq = &aior->io_req;
729 breq->br_offset = lba + done;
730 ahci_build_iov(p, aior, prdt, hdr->prdtl);
731
732 /* Mark this command in-flight. */
733 p->pending |= 1 << slot;
734
735 /* Stuff request onto busy list. */
736 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
737
738 if (ncq && first)
739 ahci_write_fis_d2h_ncq(p, slot);
740
741 if (readop)
742 err = blockif_read(p->bctx, breq);
743 else
744 err = blockif_write(p->bctx, breq);
745 assert(err == 0);
746 }
747
748 static void
ahci_handle_flush(struct ahci_port * p,int slot,uint8_t * cfis)749 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
750 {
751 struct ahci_ioreq *aior;
752 struct blockif_req *breq;
753 int err;
754
755 /*
756 * Pull request off free list
757 */
758 aior = STAILQ_FIRST(&p->iofhd);
759 assert(aior != NULL);
760 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
761 aior->cfis = cfis;
762 aior->slot = slot;
763 aior->len = 0;
764 aior->done = 0;
765 aior->more = 0;
766 breq = &aior->io_req;
767
768 /*
769 * Mark this command in-flight.
770 */
771 p->pending |= 1 << slot;
772
773 /*
774 * Stuff request onto busy list
775 */
776 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
777
778 err = blockif_flush(p->bctx, breq);
779 assert(err == 0);
780 }
781
782 static inline void
read_prdt(struct ahci_port * p,int slot,uint8_t * cfis,void * buf,unsigned int size)783 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis, void *buf,
784 unsigned int size)
785 {
786 struct ahci_cmd_hdr *hdr;
787 struct ahci_prdt_entry *prdt;
788 uint8_t *to;
789 unsigned int len;
790 int i;
791
792 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
793 len = size;
794 to = buf;
795 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
796 for (i = 0; i < hdr->prdtl && len; i++) {
797 uint8_t *ptr;
798 uint32_t dbcsz;
799 unsigned int sublen;
800
801 dbcsz = (prdt->dbc & DBCMASK) + 1;
802 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
803 sublen = MIN(len, dbcsz);
804 memcpy(to, ptr, sublen);
805 len -= sublen;
806 to += sublen;
807 prdt++;
808 }
809 }
810
811 static void
ahci_handle_dsm_trim(struct ahci_port * p,int slot,uint8_t * cfis,uint32_t done)812 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
813 {
814 struct ahci_ioreq *aior;
815 struct blockif_req *breq;
816 uint8_t *entry;
817 uint64_t elba;
818 uint32_t len, elen;
819 int err, first, ncq;
820 uint8_t buf[512];
821
822 first = (done == 0);
823 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) {
824 len = (uint16_t)cfis[13] << 8 | cfis[12];
825 len *= 512;
826 ncq = 0;
827 } else { /* ATA_SEND_FPDMA_QUEUED */
828 len = (uint16_t)cfis[11] << 8 | cfis[3];
829 len *= 512;
830 ncq = 1;
831 }
832 read_prdt(p, slot, cfis, buf, sizeof(buf));
833
834 next:
835 entry = &buf[done];
836 elba = ((uint64_t)entry[5] << 40) |
837 ((uint64_t)entry[4] << 32) |
838 ((uint64_t)entry[3] << 24) |
839 ((uint64_t)entry[2] << 16) |
840 ((uint64_t)entry[1] << 8) |
841 entry[0];
842 elen = (uint16_t)entry[7] << 8 | entry[6];
843 done += 8;
844 if (elen == 0) {
845 if (done >= len) {
846 if (ncq) {
847 if (first)
848 ahci_write_fis_d2h_ncq(p, slot);
849 ahci_write_fis_sdb(p, slot, cfis,
850 ATA_S_READY | ATA_S_DSC);
851 } else {
852 ahci_write_fis_d2h(p, slot, cfis,
853 ATA_S_READY | ATA_S_DSC);
854 }
855 p->pending &= ~(1 << slot);
856 ahci_check_stopped(p);
857 if (!first)
858 ahci_handle_port(p);
859 return;
860 }
861 goto next;
862 }
863
864 /*
865 * Pull request off free list
866 */
867 aior = STAILQ_FIRST(&p->iofhd);
868 assert(aior != NULL);
869 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
870 aior->cfis = cfis;
871 aior->slot = slot;
872 aior->len = len;
873 aior->done = done;
874 aior->more = (len != done);
875
876 breq = &aior->io_req;
877 breq->br_offset = elba * blockif_sectsz(p->bctx);
878 breq->br_resid = elen * blockif_sectsz(p->bctx);
879
880 /*
881 * Mark this command in-flight.
882 */
883 p->pending |= 1 << slot;
884
885 /*
886 * Stuff request onto busy list
887 */
888 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
889
890 if (ncq && first)
891 ahci_write_fis_d2h_ncq(p, slot);
892
893 err = blockif_delete(p->bctx, breq);
894 assert(err == 0);
895 }
896
897 static inline void
write_prdt(struct ahci_port * p,int slot,uint8_t * cfis,void * buf,unsigned int size)898 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis, void *buf,
899 unsigned int size)
900 {
901 struct ahci_cmd_hdr *hdr;
902 struct ahci_prdt_entry *prdt;
903 uint8_t *from;
904 unsigned int len;
905 int i;
906
907 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
908 len = size;
909 from = buf;
910 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
911 for (i = 0; i < hdr->prdtl && len; i++) {
912 uint8_t *ptr;
913 uint32_t dbcsz;
914 int sublen;
915
916 dbcsz = (prdt->dbc & DBCMASK) + 1;
917 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
918 sublen = MIN(len, dbcsz);
919 memcpy(ptr, from, sublen);
920 len -= sublen;
921 from += sublen;
922 prdt++;
923 }
924 hdr->prdbc = size - len;
925 }
926
927 static void
ahci_checksum(uint8_t * buf,int size)928 ahci_checksum(uint8_t *buf, int size)
929 {
930 int i;
931 uint8_t sum = 0;
932
933 for (i = 0; i < size - 1; i++)
934 sum += buf[i];
935 buf[size - 1] = 0x100 - sum;
936 }
937
938 static void
ahci_handle_read_log(struct ahci_port * p,int slot,uint8_t * cfis)939 ahci_handle_read_log(struct ahci_port *p, int slot, uint8_t *cfis)
940 {
941 struct ahci_cmd_hdr *hdr;
942 uint32_t buf[128];
943 uint8_t *buf8 = (uint8_t *)buf;
944 uint16_t *buf16 = (uint16_t *)buf;
945
946 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
947 if (p->atapi || hdr->prdtl == 0 || cfis[5] != 0 ||
948 cfis[9] != 0 || cfis[12] != 1 || cfis[13] != 0) {
949 ahci_write_fis_d2h(p, slot, cfis,
950 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
951 return;
952 }
953
954 memset(buf, 0, sizeof(buf));
955 if (cfis[4] == 0x00) { /* Log directory */
956 buf16[0x00] = 1; /* Version -- 1 */
957 buf16[0x10] = 1; /* NCQ Command Error Log -- 1 page */
958 buf16[0x13] = 1; /* SATA NCQ Send and Receive Log -- 1 page */
959 } else if (cfis[4] == 0x10) { /* NCQ Command Error Log */
960 memcpy(buf8, p->err_cfis, sizeof(p->err_cfis));
961 ahci_checksum(buf8, sizeof(buf));
962 } else if (cfis[4] == 0x13) { /* SATA NCQ Send and Receive Log */
963 if (blockif_candelete(p->bctx) && !blockif_is_ro(p->bctx)) {
964 buf[0x00] = 1; /* SFQ DSM supported */
965 buf[0x01] = 1; /* SFQ DSM TRIM supported */
966 }
967 } else {
968 ahci_write_fis_d2h(p, slot, cfis,
969 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
970 return;
971 }
972
973 if (cfis[2] == ATA_READ_LOG_EXT)
974 ahci_write_fis_piosetup(p);
975 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
976 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
977 }
978
979 static void
handle_identify(struct ahci_port * p,int slot,uint8_t * cfis)980 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
981 {
982 struct ahci_cmd_hdr *hdr;
983
984 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
985 if (p->atapi || hdr->prdtl == 0) {
986 ahci_write_fis_d2h(p, slot, cfis,
987 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
988 } else {
989 ahci_write_fis_piosetup(p);
990 write_prdt(p, slot, cfis, (void*)&p->ata_ident, sizeof(struct ata_params));
991 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
992 }
993 }
994
995 static void
ata_identify_init(struct ahci_port * p,int atapi)996 ata_identify_init(struct ahci_port* p, int atapi)
997 {
998 struct ata_params* ata_ident = &p->ata_ident;
999
1000 if (atapi) {
1001 ata_ident->config = ATA_PROTO_ATAPI | ATA_ATAPI_TYPE_CDROM |
1002 ATA_ATAPI_REMOVABLE | ATA_DRQ_FAST;
1003 ata_ident->capabilities1 = ATA_SUPPORT_LBA |
1004 ATA_SUPPORT_DMA;
1005 ata_ident->capabilities2 = (1 << 14 | 1);
1006 ata_ident->atavalid = ATA_FLAG_64_70 | ATA_FLAG_88;
1007 ata_ident->obsolete62 = 0x3f;
1008 ata_ident->mwdmamodes = 7;
1009 if (p->xfermode & ATA_WDMA0)
1010 ata_ident->mwdmamodes |= (1 << ((p->xfermode & 7) + 8));
1011 ata_ident->apiomodes = 3;
1012 ata_ident->mwdmamin = 0x0078;
1013 ata_ident->mwdmarec = 0x0078;
1014 ata_ident->pioblind = 0x0078;
1015 ata_ident->pioiordy = 0x0078;
1016 ata_ident->satacapabilities = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3);
1017 ata_ident->satacapabilities2 = ((p->ssts & ATA_SS_SPD_MASK) >> 3);
1018 ata_ident->satasupport = ATA_SUPPORT_NCQ_STREAM;
1019 ata_ident->version_major = 0x3f0;
1020 ata_ident->support.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1021 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1022 ata_ident->support.command2 = (1 << 14);
1023 ata_ident->support.extension = (1 << 14);
1024 ata_ident->enabled.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET |
1025 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP);
1026 ata_ident->enabled.extension = (1 << 14);
1027 ata_ident->udmamodes = 0x7f;
1028 if (p->xfermode & ATA_UDMA0)
1029 ata_ident->udmamodes |= (1 << ((p->xfermode & 7) + 8));
1030 ata_ident->transport_major = 0x1020;
1031 ata_ident->integrity = 0x00a5;
1032 } else {
1033 uint64_t sectors;
1034 int sectsz, psectsz, psectoff, candelete, ro;
1035 uint16_t cyl;
1036 uint8_t sech, heads;
1037
1038 ro = blockif_is_ro(p->bctx);
1039 candelete = blockif_candelete(p->bctx);
1040 sectsz = blockif_sectsz(p->bctx);
1041 sectors = blockif_size(p->bctx) / sectsz;
1042 blockif_chs(p->bctx, &cyl, &heads, &sech);
1043 blockif_psectsz(p->bctx, &psectsz, &psectoff);
1044 ata_ident->config = ATA_DRQ_FAST;
1045 ata_ident->cylinders = cyl;
1046 ata_ident->heads = heads;
1047 ata_ident->sectors = sech;
1048
1049 ata_ident->sectors_intr = (0x8000 | 128);
1050 ata_ident->tcg = 0;
1051
1052 ata_ident->capabilities1 = ATA_SUPPORT_DMA |
1053 ATA_SUPPORT_LBA | ATA_SUPPORT_IORDY;
1054 ata_ident->capabilities2 = (1 << 14);
1055 ata_ident->atavalid = ATA_FLAG_64_70 | ATA_FLAG_88;
1056 if (p->mult_sectors)
1057 ata_ident->multi = (ATA_MULTI_VALID | p->mult_sectors);
1058 if (sectors <= 0x0fffffff) {
1059 ata_ident->lba_size_1 = sectors;
1060 ata_ident->lba_size_2 = (sectors >> 16);
1061 } else {
1062 ata_ident->lba_size_1 = 0xffff;
1063 ata_ident->lba_size_2 = 0x0fff;
1064 }
1065 ata_ident->mwdmamodes = 0x7;
1066 if (p->xfermode & ATA_WDMA0)
1067 ata_ident->mwdmamodes |= (1 << ((p->xfermode & 7) + 8));
1068 ata_ident->apiomodes = 0x3;
1069 ata_ident->mwdmamin = 0x0078;
1070 ata_ident->mwdmarec = 0x0078;
1071 ata_ident->pioblind = 0x0078;
1072 ata_ident->pioiordy = 0x0078;
1073 ata_ident->support3 = 0;
1074 ata_ident->queue = 31;
1075 ata_ident->satacapabilities = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 |
1076 ATA_SUPPORT_NCQ);
1077 ata_ident->satacapabilities2 = (ATA_SUPPORT_RCVSND_FPDMA_QUEUED |
1078 (p->ssts & ATA_SS_SPD_MASK) >> 3);
1079 ata_ident->version_major = 0x3f0;
1080 ata_ident->version_minor = 0x28;
1081 ata_ident->support.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE |
1082 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1083 ata_ident->support.command2 = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1084 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14);
1085 ata_ident->support.extension = (1 << 14);
1086 ata_ident->enabled.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE |
1087 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
1088 ata_ident->enabled.command2 = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
1089 ATA_SUPPORT_FLUSHCACHE48 | 1 << 15);
1090 ata_ident->enabled.extension = (1 << 14);
1091 ata_ident->udmamodes = 0x7f;
1092 if (p->xfermode & ATA_UDMA0)
1093 ata_ident->udmamodes |= (1 << ((p->xfermode & 7) + 8));
1094 ata_ident->lba_size48_1 = sectors;
1095 ata_ident->lba_size48_2 = (sectors >> 16);
1096 ata_ident->lba_size48_3 = (sectors >> 32);
1097 ata_ident->lba_size48_4 = (sectors >> 48);
1098
1099 if (candelete && !ro) {
1100 ata_ident->support3 |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT;
1101 ata_ident->max_dsm_blocks = 1;
1102 ata_ident->support_dsm = ATA_SUPPORT_DSM_TRIM;
1103 }
1104 ata_ident->pss = ATA_PSS_VALID_VALUE;
1105 ata_ident->lsalign = 0x4000;
1106 if (psectsz > sectsz) {
1107 ata_ident->pss |= ATA_PSS_MULTLS;
1108 ata_ident->pss |= ffsl(psectsz / sectsz) - 1;
1109 ata_ident->lsalign |= (psectoff / sectsz);
1110 }
1111 if (sectsz > 512) {
1112 ata_ident->pss |= ATA_PSS_LSSABOVE512;
1113 ata_ident->lss_1 = sectsz / 2;
1114 ata_ident->lss_2 = ((sectsz / 2) >> 16);
1115 }
1116 ata_ident->support2 = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1117 ata_ident->enabled2 = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
1118 ata_ident->transport_major = 0x1020;
1119 ata_ident->integrity = 0x00a5;
1120 }
1121 ahci_checksum((uint8_t*)ata_ident, sizeof(struct ata_params));
1122 }
1123
1124 static void
handle_atapi_identify(struct ahci_port * p,int slot,uint8_t * cfis)1125 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
1126 {
1127 if (!p->atapi) {
1128 ahci_write_fis_d2h(p, slot, cfis,
1129 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1130 } else {
1131 ahci_write_fis_piosetup(p);
1132 write_prdt(p, slot, cfis, (void *)&p->ata_ident, sizeof(struct ata_params));
1133 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
1134 }
1135 }
1136
1137 static void
atapi_inquiry(struct ahci_port * p,int slot,uint8_t * cfis)1138 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
1139 {
1140 uint8_t buf[36];
1141 uint8_t *acmd;
1142 unsigned int len;
1143 uint32_t tfd;
1144
1145 acmd = cfis + 0x40;
1146
1147 if (acmd[1] & 1) { /* VPD */
1148 if (acmd[2] == 0) { /* Supported VPD pages */
1149 buf[0] = 0x05;
1150 buf[1] = 0;
1151 buf[2] = 0;
1152 buf[3] = 1;
1153 buf[4] = 0;
1154 len = 4 + buf[3];
1155 } else {
1156 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1157 p->asc = 0x24;
1158 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1159 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1160 ahci_write_fis_d2h(p, slot, cfis, tfd);
1161 return;
1162 }
1163 } else {
1164 buf[0] = 0x05;
1165 buf[1] = 0x80;
1166 buf[2] = 0x00;
1167 buf[3] = 0x21;
1168 buf[4] = 31;
1169 buf[5] = 0;
1170 buf[6] = 0;
1171 buf[7] = 0;
1172 atapi_string(buf + 8, "BHYVE", 8);
1173 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
1174 atapi_string(buf + 32, "001", 4);
1175 len = sizeof(buf);
1176 }
1177
1178 if (len > acmd[4])
1179 len = acmd[4];
1180 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1181 write_prdt(p, slot, cfis, buf, len);
1182 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1183 }
1184
1185 static void
atapi_read_capacity(struct ahci_port * p,int slot,uint8_t * cfis)1186 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
1187 {
1188 uint8_t buf[8];
1189 uint64_t sectors;
1190
1191 sectors = blockif_size(p->bctx) / 2048;
1192 be32enc(buf, sectors - 1);
1193 be32enc(buf + 4, 2048);
1194 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1195 write_prdt(p, slot, cfis, buf, sizeof(buf));
1196 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1197 }
1198
1199 static void
atapi_read_toc(struct ahci_port * p,int slot,uint8_t * cfis)1200 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
1201 {
1202 uint8_t *acmd;
1203 uint8_t format;
1204 unsigned int len;
1205
1206 acmd = cfis + 0x40;
1207
1208 len = be16dec(acmd + 7);
1209 format = acmd[9] >> 6;
1210 switch (format) {
1211 case 0:
1212 {
1213 size_t size;
1214 int msf;
1215 uint64_t sectors;
1216 uint8_t start_track, buf[20], *bp;
1217
1218 msf = (acmd[1] >> 1) & 1;
1219 start_track = acmd[6];
1220 if (start_track > 1 && start_track != 0xaa) {
1221 uint32_t tfd;
1222 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1223 p->asc = 0x24;
1224 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1225 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1226 ahci_write_fis_d2h(p, slot, cfis, tfd);
1227 return;
1228 }
1229 bp = buf + 2;
1230 *bp++ = 1;
1231 *bp++ = 1;
1232 if (start_track <= 1) {
1233 *bp++ = 0;
1234 *bp++ = 0x14;
1235 *bp++ = 1;
1236 *bp++ = 0;
1237 if (msf) {
1238 *bp++ = 0;
1239 lba_to_msf(bp, 0);
1240 bp += 3;
1241 } else {
1242 *bp++ = 0;
1243 *bp++ = 0;
1244 *bp++ = 0;
1245 *bp++ = 0;
1246 }
1247 }
1248 *bp++ = 0;
1249 *bp++ = 0x14;
1250 *bp++ = 0xaa;
1251 *bp++ = 0;
1252 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1253 sectors >>= 2;
1254 if (msf) {
1255 *bp++ = 0;
1256 lba_to_msf(bp, sectors);
1257 bp += 3;
1258 } else {
1259 be32enc(bp, sectors);
1260 bp += 4;
1261 }
1262 size = bp - buf;
1263 be16enc(buf, size - 2);
1264 if (len > size)
1265 len = size;
1266 write_prdt(p, slot, cfis, buf, len);
1267 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1268 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1269 break;
1270 }
1271 case 1:
1272 {
1273 uint8_t buf[12];
1274
1275 memset(buf, 0, sizeof(buf));
1276 buf[1] = 0xa;
1277 buf[2] = 0x1;
1278 buf[3] = 0x1;
1279 if (len > sizeof(buf))
1280 len = sizeof(buf);
1281 write_prdt(p, slot, cfis, buf, len);
1282 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1283 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1284 break;
1285 }
1286 case 2:
1287 {
1288 size_t size;
1289 int msf;
1290 uint64_t sectors;
1291 uint8_t *bp, buf[50];
1292
1293 msf = (acmd[1] >> 1) & 1;
1294 bp = buf + 2;
1295 *bp++ = 1;
1296 *bp++ = 1;
1297
1298 *bp++ = 1;
1299 *bp++ = 0x14;
1300 *bp++ = 0;
1301 *bp++ = 0xa0;
1302 *bp++ = 0;
1303 *bp++ = 0;
1304 *bp++ = 0;
1305 *bp++ = 0;
1306 *bp++ = 1;
1307 *bp++ = 0;
1308 *bp++ = 0;
1309
1310 *bp++ = 1;
1311 *bp++ = 0x14;
1312 *bp++ = 0;
1313 *bp++ = 0xa1;
1314 *bp++ = 0;
1315 *bp++ = 0;
1316 *bp++ = 0;
1317 *bp++ = 0;
1318 *bp++ = 1;
1319 *bp++ = 0;
1320 *bp++ = 0;
1321
1322 *bp++ = 1;
1323 *bp++ = 0x14;
1324 *bp++ = 0;
1325 *bp++ = 0xa2;
1326 *bp++ = 0;
1327 *bp++ = 0;
1328 *bp++ = 0;
1329 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1330 sectors >>= 2;
1331 if (msf) {
1332 *bp++ = 0;
1333 lba_to_msf(bp, sectors);
1334 bp += 3;
1335 } else {
1336 be32enc(bp, sectors);
1337 bp += 4;
1338 }
1339
1340 *bp++ = 1;
1341 *bp++ = 0x14;
1342 *bp++ = 0;
1343 *bp++ = 1;
1344 *bp++ = 0;
1345 *bp++ = 0;
1346 *bp++ = 0;
1347 if (msf) {
1348 *bp++ = 0;
1349 lba_to_msf(bp, 0);
1350 bp += 3;
1351 } else {
1352 *bp++ = 0;
1353 *bp++ = 0;
1354 *bp++ = 0;
1355 *bp++ = 0;
1356 }
1357
1358 size = bp - buf;
1359 be16enc(buf, size - 2);
1360 if (len > size)
1361 len = size;
1362 write_prdt(p, slot, cfis, buf, len);
1363 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1364 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1365 break;
1366 }
1367 default:
1368 {
1369 uint32_t tfd;
1370
1371 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1372 p->asc = 0x24;
1373 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1374 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1375 ahci_write_fis_d2h(p, slot, cfis, tfd);
1376 break;
1377 }
1378 }
1379 }
1380
1381 static void
atapi_report_luns(struct ahci_port * p,int slot,uint8_t * cfis)1382 atapi_report_luns(struct ahci_port *p, int slot, uint8_t *cfis)
1383 {
1384 uint8_t buf[16];
1385
1386 memset(buf, 0, sizeof(buf));
1387 buf[3] = 8;
1388
1389 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1390 write_prdt(p, slot, cfis, buf, sizeof(buf));
1391 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1392 }
1393
1394 static void
atapi_read(struct ahci_port * p,int slot,uint8_t * cfis,uint32_t done)1395 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
1396 {
1397 struct ahci_ioreq *aior;
1398 struct ahci_cmd_hdr *hdr;
1399 struct ahci_prdt_entry *prdt;
1400 struct blockif_req *breq;
1401 uint8_t *acmd;
1402 uint64_t lba;
1403 uint32_t len;
1404 int err;
1405
1406 acmd = cfis + 0x40;
1407 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1408 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1409
1410 lba = be32dec(acmd + 2);
1411 if (acmd[0] == READ_10)
1412 len = be16dec(acmd + 7);
1413 else
1414 len = be32dec(acmd + 6);
1415 if (len == 0) {
1416 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1417 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1418 }
1419 lba *= 2048;
1420 len *= 2048;
1421
1422 /*
1423 * Pull request off free list
1424 */
1425 aior = STAILQ_FIRST(&p->iofhd);
1426 assert(aior != NULL);
1427 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1428 aior->cfis = cfis;
1429 aior->slot = slot;
1430 aior->len = len;
1431 aior->done = done;
1432 breq = &aior->io_req;
1433 breq->br_offset = lba + done;
1434 ahci_build_iov(p, aior, prdt, hdr->prdtl);
1435
1436 /* Mark this command in-flight. */
1437 p->pending |= 1 << slot;
1438
1439 /* Stuff request onto busy list. */
1440 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1441
1442 err = blockif_read(p->bctx, breq);
1443 assert(err == 0);
1444 }
1445
1446 static void
atapi_request_sense(struct ahci_port * p,int slot,uint8_t * cfis)1447 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1448 {
1449 uint8_t buf[64];
1450 uint8_t *acmd;
1451 unsigned int len;
1452
1453 acmd = cfis + 0x40;
1454 len = acmd[4];
1455 if (len > sizeof(buf))
1456 len = sizeof(buf);
1457 memset(buf, 0, len);
1458 buf[0] = 0x70 | (1 << 7);
1459 buf[2] = p->sense_key;
1460 buf[7] = 10;
1461 buf[12] = p->asc;
1462 write_prdt(p, slot, cfis, buf, len);
1463 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1464 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1465 }
1466
1467 static void
atapi_start_stop_unit(struct ahci_port * p,int slot,uint8_t * cfis)1468 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1469 {
1470 uint8_t *acmd = cfis + 0x40;
1471 uint32_t tfd;
1472
1473 switch (acmd[4] & 3) {
1474 case 0:
1475 case 1:
1476 case 3:
1477 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1478 tfd = ATA_S_READY | ATA_S_DSC;
1479 break;
1480 case 2:
1481 /* TODO eject media */
1482 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1483 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1484 p->asc = 0x53;
1485 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1486 break;
1487 }
1488 ahci_write_fis_d2h(p, slot, cfis, tfd);
1489 }
1490
1491 static void
atapi_mode_sense(struct ahci_port * p,int slot,uint8_t * cfis)1492 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1493 {
1494 uint8_t *acmd;
1495 uint32_t tfd = 0;
1496 uint8_t pc, code;
1497 unsigned int len;
1498
1499 acmd = cfis + 0x40;
1500 len = be16dec(acmd + 7);
1501 pc = acmd[2] >> 6;
1502 code = acmd[2] & 0x3f;
1503
1504 switch (pc) {
1505 case 0:
1506 switch (code) {
1507 case MODEPAGE_RW_ERROR_RECOVERY:
1508 {
1509 uint8_t buf[16];
1510
1511 if (len > sizeof(buf))
1512 len = sizeof(buf);
1513
1514 memset(buf, 0, sizeof(buf));
1515 be16enc(buf, 16 - 2);
1516 buf[2] = 0x70;
1517 buf[8] = 0x01;
1518 buf[9] = 16 - 10;
1519 buf[11] = 0x05;
1520 write_prdt(p, slot, cfis, buf, len);
1521 tfd = ATA_S_READY | ATA_S_DSC;
1522 break;
1523 }
1524 case MODEPAGE_CD_CAPABILITIES:
1525 {
1526 uint8_t buf[30];
1527
1528 if (len > sizeof(buf))
1529 len = sizeof(buf);
1530
1531 memset(buf, 0, sizeof(buf));
1532 be16enc(buf, 30 - 2);
1533 buf[2] = 0x70;
1534 buf[8] = 0x2A;
1535 buf[9] = 30 - 10;
1536 buf[10] = 0x08;
1537 buf[12] = 0x71;
1538 be16enc(&buf[18], 2);
1539 be16enc(&buf[20], 512);
1540 write_prdt(p, slot, cfis, buf, len);
1541 tfd = ATA_S_READY | ATA_S_DSC;
1542 break;
1543 }
1544 default:
1545 goto error;
1546 break;
1547 }
1548 break;
1549 case 3:
1550 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1551 p->asc = 0x39;
1552 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1553 break;
1554 error:
1555 case 1:
1556 case 2:
1557 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1558 p->asc = 0x24;
1559 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1560 break;
1561 }
1562 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1563 ahci_write_fis_d2h(p, slot, cfis, tfd);
1564 }
1565
1566 static void
atapi_get_event_status_notification(struct ahci_port * p,int slot,uint8_t * cfis)1567 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1568 uint8_t *cfis)
1569 {
1570 uint8_t *acmd;
1571 uint32_t tfd;
1572
1573 acmd = cfis + 0x40;
1574
1575 /* we don't support asynchronous operation */
1576 if (!(acmd[1] & 1)) {
1577 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1578 p->asc = 0x24;
1579 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1580 } else {
1581 uint8_t buf[8];
1582 unsigned int len;
1583
1584 len = be16dec(acmd + 7);
1585 if (len > sizeof(buf))
1586 len = sizeof(buf);
1587
1588 memset(buf, 0, sizeof(buf));
1589 be16enc(buf, 8 - 2);
1590 buf[2] = 0x04;
1591 buf[3] = 0x10;
1592 buf[5] = 0x02;
1593 write_prdt(p, slot, cfis, buf, len);
1594 tfd = ATA_S_READY | ATA_S_DSC;
1595 }
1596 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1597 ahci_write_fis_d2h(p, slot, cfis, tfd);
1598 }
1599
1600 static void
handle_packet_cmd(struct ahci_port * p,int slot,uint8_t * cfis)1601 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1602 {
1603 uint8_t *acmd;
1604
1605 acmd = cfis + 0x40;
1606
1607 #ifdef AHCI_DEBUG
1608 {
1609 int i;
1610 DPRINTF("ACMD:");
1611 for (i = 0; i < 16; i++)
1612 DPRINTF("%02x ", acmd[i]);
1613 DPRINTF("");
1614 }
1615 #endif
1616
1617 switch (acmd[0]) {
1618 case TEST_UNIT_READY:
1619 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1620 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1621 break;
1622 case INQUIRY:
1623 atapi_inquiry(p, slot, cfis);
1624 break;
1625 case READ_CAPACITY:
1626 atapi_read_capacity(p, slot, cfis);
1627 break;
1628 case PREVENT_ALLOW:
1629 /* TODO */
1630 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1631 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1632 break;
1633 case READ_TOC:
1634 atapi_read_toc(p, slot, cfis);
1635 break;
1636 case REPORT_LUNS:
1637 atapi_report_luns(p, slot, cfis);
1638 break;
1639 case READ_10:
1640 case READ_12:
1641 atapi_read(p, slot, cfis, 0);
1642 break;
1643 case REQUEST_SENSE:
1644 atapi_request_sense(p, slot, cfis);
1645 break;
1646 case START_STOP_UNIT:
1647 atapi_start_stop_unit(p, slot, cfis);
1648 break;
1649 case MODE_SENSE_10:
1650 atapi_mode_sense(p, slot, cfis);
1651 break;
1652 case GET_EVENT_STATUS_NOTIFICATION:
1653 atapi_get_event_status_notification(p, slot, cfis);
1654 break;
1655 default:
1656 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1657 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1658 p->asc = 0x20;
1659 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1660 ATA_S_READY | ATA_S_ERROR);
1661 break;
1662 }
1663 }
1664
1665 static void
ahci_handle_cmd(struct ahci_port * p,int slot,uint8_t * cfis)1666 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1667 {
1668
1669 p->tfd |= ATA_S_BUSY;
1670 switch (cfis[2]) {
1671 case ATA_ATA_IDENTIFY:
1672 handle_identify(p, slot, cfis);
1673 break;
1674 case ATA_SETFEATURES:
1675 {
1676 switch (cfis[3]) {
1677 case ATA_SF_ENAB_SATA_SF:
1678 switch (cfis[12]) {
1679 case ATA_SATA_SF_AN:
1680 p->tfd = ATA_S_DSC | ATA_S_READY;
1681 break;
1682 default:
1683 p->tfd = ATA_S_ERROR | ATA_S_READY;
1684 p->tfd |= (ATA_ERROR_ABORT << 8);
1685 break;
1686 }
1687 break;
1688 case ATA_SF_ENAB_WCACHE:
1689 case ATA_SF_DIS_WCACHE:
1690 case ATA_SF_ENAB_RCACHE:
1691 case ATA_SF_DIS_RCACHE:
1692 p->tfd = ATA_S_DSC | ATA_S_READY;
1693 break;
1694 case ATA_SF_SETXFER:
1695 {
1696 switch (cfis[12] & 0xf8) {
1697 case ATA_PIO:
1698 case ATA_PIO0:
1699 break;
1700 case ATA_WDMA0:
1701 case ATA_UDMA0:
1702 p->xfermode = (cfis[12] & 0x7);
1703 break;
1704 }
1705 p->tfd = ATA_S_DSC | ATA_S_READY;
1706 break;
1707 }
1708 default:
1709 p->tfd = ATA_S_ERROR | ATA_S_READY;
1710 p->tfd |= (ATA_ERROR_ABORT << 8);
1711 break;
1712 }
1713 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1714 break;
1715 }
1716 case ATA_SET_MULTI:
1717 if (cfis[12] != 0 &&
1718 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1719 p->tfd = ATA_S_ERROR | ATA_S_READY;
1720 p->tfd |= (ATA_ERROR_ABORT << 8);
1721 } else {
1722 p->mult_sectors = cfis[12];
1723 p->tfd = ATA_S_DSC | ATA_S_READY;
1724 }
1725 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1726 break;
1727 case ATA_READ:
1728 case ATA_WRITE:
1729 case ATA_READ48:
1730 case ATA_WRITE48:
1731 case ATA_READ_MUL:
1732 case ATA_WRITE_MUL:
1733 case ATA_READ_MUL48:
1734 case ATA_WRITE_MUL48:
1735 case ATA_READ_DMA:
1736 case ATA_WRITE_DMA:
1737 case ATA_READ_DMA48:
1738 case ATA_WRITE_DMA48:
1739 case ATA_READ_FPDMA_QUEUED:
1740 case ATA_WRITE_FPDMA_QUEUED:
1741 ahci_handle_rw(p, slot, cfis, 0);
1742 break;
1743 case ATA_FLUSHCACHE:
1744 case ATA_FLUSHCACHE48:
1745 ahci_handle_flush(p, slot, cfis);
1746 break;
1747 case ATA_DATA_SET_MANAGEMENT:
1748 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM &&
1749 cfis[13] == 0 && cfis[12] == 1) {
1750 ahci_handle_dsm_trim(p, slot, cfis, 0);
1751 break;
1752 }
1753 ahci_write_fis_d2h(p, slot, cfis,
1754 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1755 break;
1756 case ATA_SEND_FPDMA_QUEUED:
1757 if ((cfis[13] & 0x1f) == ATA_SFPDMA_DSM &&
1758 cfis[17] == 0 && cfis[16] == ATA_DSM_TRIM &&
1759 cfis[11] == 0 && cfis[3] == 1) {
1760 ahci_handle_dsm_trim(p, slot, cfis, 0);
1761 break;
1762 }
1763 ahci_write_fis_d2h(p, slot, cfis,
1764 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1765 break;
1766 case ATA_READ_LOG_EXT:
1767 case ATA_READ_LOG_DMA_EXT:
1768 ahci_handle_read_log(p, slot, cfis);
1769 break;
1770 case ATA_SECURITY_FREEZE_LOCK:
1771 case ATA_SMART_CMD:
1772 case ATA_NOP:
1773 ahci_write_fis_d2h(p, slot, cfis,
1774 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1775 break;
1776 case ATA_CHECK_POWER_MODE:
1777 cfis[12] = 0xff; /* always on */
1778 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1779 break;
1780 case ATA_STANDBY_CMD:
1781 case ATA_STANDBY_IMMEDIATE:
1782 case ATA_IDLE_CMD:
1783 case ATA_IDLE_IMMEDIATE:
1784 case ATA_SLEEP:
1785 case ATA_READ_VERIFY:
1786 case ATA_READ_VERIFY48:
1787 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1788 break;
1789 case ATA_ATAPI_IDENTIFY:
1790 handle_atapi_identify(p, slot, cfis);
1791 break;
1792 case ATA_PACKET_CMD:
1793 if (!p->atapi) {
1794 ahci_write_fis_d2h(p, slot, cfis,
1795 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1796 } else
1797 handle_packet_cmd(p, slot, cfis);
1798 break;
1799 default:
1800 WPRINTF("Unsupported cmd:%02x", cfis[2]);
1801 ahci_write_fis_d2h(p, slot, cfis,
1802 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1803 break;
1804 }
1805 }
1806
1807 static void
ahci_handle_slot(struct ahci_port * p,int slot)1808 ahci_handle_slot(struct ahci_port *p, int slot)
1809 {
1810 struct ahci_cmd_hdr *hdr;
1811 #ifdef AHCI_DEBUG
1812 struct ahci_prdt_entry *prdt;
1813 #endif
1814 struct pci_ahci_softc *sc;
1815 uint8_t *cfis;
1816 #ifdef AHCI_DEBUG
1817 int cfl, i;
1818 #endif
1819
1820 sc = p->pr_sc;
1821 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1822 #ifdef AHCI_DEBUG
1823 cfl = (hdr->flags & 0x1f) * 4;
1824 #endif
1825 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1826 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1827 #ifdef AHCI_DEBUG
1828 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1829
1830 DPRINTF("cfis:");
1831 for (i = 0; i < cfl; i++) {
1832 if (i % 10 == 0)
1833 DPRINTF("");
1834 DPRINTF("%02x ", cfis[i]);
1835 }
1836 DPRINTF("");
1837
1838 for (i = 0; i < hdr->prdtl; i++) {
1839 DPRINTF("%d@%08"PRIx64"", prdt->dbc & 0x3fffff, prdt->dba);
1840 prdt++;
1841 }
1842 #endif
1843
1844 if (cfis[0] != FIS_TYPE_REGH2D) {
1845 WPRINTF("Not a H2D FIS:%02x", cfis[0]);
1846 return;
1847 }
1848
1849 if (cfis[1] & 0x80) {
1850 ahci_handle_cmd(p, slot, cfis);
1851 } else {
1852 if (cfis[15] & (1 << 2))
1853 p->reset = 1;
1854 else if (p->reset) {
1855 p->reset = 0;
1856 ahci_port_reset(p);
1857 }
1858 p->ci &= ~(1 << slot);
1859 }
1860 }
1861
1862 static void
ahci_handle_port(struct ahci_port * p)1863 ahci_handle_port(struct ahci_port *p)
1864 {
1865
1866 if (!(p->cmd & AHCI_P_CMD_ST))
1867 return;
1868
1869 /*
1870 * Search for any new commands to issue ignoring those that
1871 * are already in-flight. Stop if device is busy or in error.
1872 */
1873 for (; (p->ci & ~p->pending) != 0; p->ccs = ((p->ccs + 1) & 31)) {
1874 if ((p->tfd & (ATA_S_BUSY | ATA_S_DRQ)) != 0)
1875 break;
1876 if (p->waitforclear)
1877 break;
1878 if ((p->ci & ~p->pending & (1 << p->ccs)) != 0) {
1879 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1880 p->cmd |= p->ccs << AHCI_P_CMD_CCS_SHIFT;
1881 ahci_handle_slot(p, p->ccs);
1882 }
1883 }
1884 }
1885
1886 /*
1887 * blockif callback routine - this runs in the context of the blockif
1888 * i/o thread, so the mutex needs to be acquired.
1889 */
1890 static void
ata_ioreq_cb(struct blockif_req * br,int err)1891 ata_ioreq_cb(struct blockif_req *br, int err)
1892 {
1893 struct ahci_cmd_hdr *hdr;
1894 struct ahci_ioreq *aior;
1895 struct ahci_port *p;
1896 struct pci_ahci_softc *sc;
1897 uint32_t tfd;
1898 uint8_t *cfis;
1899 int slot, ncq, dsm;
1900
1901 DPRINTF("%s %d", __func__, err);
1902
1903 ncq = dsm = 0;
1904 aior = br->br_param;
1905 p = aior->io_pr;
1906 cfis = aior->cfis;
1907 slot = aior->slot;
1908 sc = p->pr_sc;
1909 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1910
1911 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1912 cfis[2] == ATA_READ_FPDMA_QUEUED ||
1913 cfis[2] == ATA_SEND_FPDMA_QUEUED)
1914 ncq = 1;
1915 if (cfis[2] == ATA_DATA_SET_MANAGEMENT ||
1916 (cfis[2] == ATA_SEND_FPDMA_QUEUED &&
1917 (cfis[13] & 0x1f) == ATA_SFPDMA_DSM))
1918 dsm = 1;
1919
1920 pthread_mutex_lock(&sc->mtx);
1921
1922 /*
1923 * Delete the blockif request from the busy list
1924 */
1925 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1926
1927 /*
1928 * Move the blockif request back to the free list
1929 */
1930 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1931
1932 if (!err)
1933 hdr->prdbc = aior->done;
1934
1935 if (!err && aior->more) {
1936 if (dsm)
1937 ahci_handle_dsm_trim(p, slot, cfis, aior->done);
1938 else
1939 ahci_handle_rw(p, slot, cfis, aior->done);
1940 goto out;
1941 }
1942
1943 if (!err)
1944 tfd = ATA_S_READY | ATA_S_DSC;
1945 else
1946 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1947 if (ncq)
1948 ahci_write_fis_sdb(p, slot, cfis, tfd);
1949 else
1950 ahci_write_fis_d2h(p, slot, cfis, tfd);
1951
1952 /*
1953 * This command is now complete.
1954 */
1955 p->pending &= ~(1 << slot);
1956
1957 ahci_check_stopped(p);
1958 ahci_handle_port(p);
1959 out:
1960 pthread_mutex_unlock(&sc->mtx);
1961 DPRINTF("%s exit", __func__);
1962 }
1963
1964 static void
atapi_ioreq_cb(struct blockif_req * br,int err)1965 atapi_ioreq_cb(struct blockif_req *br, int err)
1966 {
1967 struct ahci_cmd_hdr *hdr;
1968 struct ahci_ioreq *aior;
1969 struct ahci_port *p;
1970 struct pci_ahci_softc *sc;
1971 uint8_t *cfis;
1972 uint32_t tfd;
1973 int slot;
1974
1975 DPRINTF("%s %d", __func__, err);
1976
1977 aior = br->br_param;
1978 p = aior->io_pr;
1979 cfis = aior->cfis;
1980 slot = aior->slot;
1981 sc = p->pr_sc;
1982 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1983
1984 pthread_mutex_lock(&sc->mtx);
1985
1986 /*
1987 * Delete the blockif request from the busy list
1988 */
1989 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1990
1991 /*
1992 * Move the blockif request back to the free list
1993 */
1994 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1995
1996 if (!err)
1997 hdr->prdbc = aior->done;
1998
1999 if (!err && aior->more) {
2000 atapi_read(p, slot, cfis, aior->done);
2001 goto out;
2002 }
2003
2004 if (!err) {
2005 tfd = ATA_S_READY | ATA_S_DSC;
2006 } else {
2007 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
2008 p->asc = 0x21;
2009 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
2010 }
2011 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
2012 ahci_write_fis_d2h(p, slot, cfis, tfd);
2013
2014 /*
2015 * This command is now complete.
2016 */
2017 p->pending &= ~(1 << slot);
2018
2019 ahci_check_stopped(p);
2020 ahci_handle_port(p);
2021 out:
2022 pthread_mutex_unlock(&sc->mtx);
2023 DPRINTF("%s exit", __func__);
2024 }
2025
2026 static void
pci_ahci_ioreq_init(struct ahci_port * pr)2027 pci_ahci_ioreq_init(struct ahci_port *pr)
2028 {
2029 struct ahci_ioreq *vr;
2030 int i;
2031
2032 pr->ioqsz = blockif_queuesz(pr->bctx);
2033 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
2034 STAILQ_INIT(&pr->iofhd);
2035
2036 /*
2037 * Add all i/o request entries to the free queue
2038 */
2039 for (i = 0; i < pr->ioqsz; i++) {
2040 vr = &pr->ioreq[i];
2041 vr->io_pr = pr;
2042 if (!pr->atapi)
2043 vr->io_req.br_callback = ata_ioreq_cb;
2044 else
2045 vr->io_req.br_callback = atapi_ioreq_cb;
2046 vr->io_req.br_param = vr;
2047 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
2048 }
2049
2050 TAILQ_INIT(&pr->iobhd);
2051 }
2052
2053 static void
pci_ahci_port_write(struct pci_ahci_softc * sc,uint64_t offset,uint64_t value)2054 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2055 {
2056 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2057 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2058 struct ahci_port *p = &sc->port[port];
2059
2060 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"",
2061 port, offset, value);
2062
2063 switch (offset) {
2064 case AHCI_P_CLB:
2065 p->clb = value;
2066 break;
2067 case AHCI_P_CLBU:
2068 p->clbu = value;
2069 break;
2070 case AHCI_P_FB:
2071 p->fb = value;
2072 break;
2073 case AHCI_P_FBU:
2074 p->fbu = value;
2075 break;
2076 case AHCI_P_IS:
2077 p->is &= ~value;
2078 ahci_port_intr(p);
2079 break;
2080 case AHCI_P_IE:
2081 p->ie = value & 0xFDC000FF;
2082 ahci_port_intr(p);
2083 break;
2084 case AHCI_P_CMD:
2085 {
2086 p->cmd &= ~(AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2087 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2088 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2089 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK);
2090 p->cmd |= (AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD |
2091 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE |
2092 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE |
2093 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK) & value;
2094
2095 if (!(value & AHCI_P_CMD_ST)) {
2096 ahci_port_stop(p);
2097 } else {
2098 uint64_t clb;
2099
2100 p->cmd |= AHCI_P_CMD_CR;
2101 clb = (uint64_t)p->clbu << 32 | p->clb;
2102 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
2103 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
2104 }
2105
2106 if (value & AHCI_P_CMD_FRE) {
2107 uint64_t fb;
2108
2109 p->cmd |= AHCI_P_CMD_FR;
2110 fb = (uint64_t)p->fbu << 32 | p->fb;
2111 /* we don't support FBSCP, so rfis size is 256Bytes */
2112 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
2113 } else {
2114 p->cmd &= ~AHCI_P_CMD_FR;
2115 }
2116
2117 if (value & AHCI_P_CMD_CLO) {
2118 p->tfd &= ~(ATA_S_BUSY | ATA_S_DRQ);
2119 p->cmd &= ~AHCI_P_CMD_CLO;
2120 }
2121
2122 if (value & AHCI_P_CMD_ICC_MASK) {
2123 p->cmd &= ~AHCI_P_CMD_ICC_MASK;
2124 }
2125
2126 ahci_handle_port(p);
2127 break;
2128 }
2129 case AHCI_P_TFD:
2130 case AHCI_P_SIG:
2131 case AHCI_P_SSTS:
2132 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"", offset);
2133 break;
2134 case AHCI_P_SCTL:
2135 p->sctl = value;
2136 if (!(p->cmd & AHCI_P_CMD_ST)) {
2137 if (value & ATA_SC_DET_RESET)
2138 ahci_port_reset(p);
2139 }
2140 break;
2141 case AHCI_P_SERR:
2142 p->serr &= ~value;
2143 break;
2144 case AHCI_P_SACT:
2145 p->sact |= value;
2146 break;
2147 case AHCI_P_CI:
2148 p->ci |= value;
2149 ahci_handle_port(p);
2150 break;
2151 case AHCI_P_SNTF:
2152 case AHCI_P_FBS:
2153 default:
2154 break;
2155 }
2156 }
2157
2158 static void
pci_ahci_host_write(struct pci_ahci_softc * sc,uint64_t offset,uint64_t value)2159 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
2160 {
2161 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"",
2162 offset, value);
2163
2164 switch (offset) {
2165 case AHCI_CAP:
2166 case AHCI_PI:
2167 case AHCI_VS:
2168 case AHCI_CAP2:
2169 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"", offset);
2170 break;
2171 case AHCI_GHC:
2172 if (value & AHCI_GHC_HR) {
2173 ahci_reset(sc);
2174 break;
2175 }
2176 if (value & AHCI_GHC_IE)
2177 sc->ghc |= AHCI_GHC_IE;
2178 else
2179 sc->ghc &= ~AHCI_GHC_IE;
2180 ahci_generate_intr(sc, 0xffffffff);
2181 break;
2182 case AHCI_IS:
2183 sc->is &= ~value;
2184 ahci_generate_intr(sc, value);
2185 break;
2186 default:
2187 break;
2188 }
2189 }
2190
2191 static void
pci_ahci_write(struct pci_devinst * pi,int baridx,uint64_t offset,int size,uint64_t value)2192 pci_ahci_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
2193 uint64_t value)
2194 {
2195 struct pci_ahci_softc *sc = pi->pi_arg;
2196
2197 assert(baridx == 5);
2198 assert((offset % 4) == 0 && size == 4);
2199
2200 pthread_mutex_lock(&sc->mtx);
2201
2202 if (offset < AHCI_OFFSET)
2203 pci_ahci_host_write(sc, offset, value);
2204 else if (offset < (uint64_t)AHCI_OFFSET + sc->ports * AHCI_STEP)
2205 pci_ahci_port_write(sc, offset, value);
2206 else
2207 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"", offset);
2208
2209 pthread_mutex_unlock(&sc->mtx);
2210 }
2211
2212 static uint64_t
pci_ahci_host_read(struct pci_ahci_softc * sc,uint64_t offset)2213 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
2214 {
2215 uint32_t value;
2216
2217 switch (offset) {
2218 case AHCI_CAP:
2219 case AHCI_GHC:
2220 case AHCI_IS:
2221 case AHCI_PI:
2222 case AHCI_VS:
2223 case AHCI_CCCC:
2224 case AHCI_CCCP:
2225 case AHCI_EM_LOC:
2226 case AHCI_EM_CTL:
2227 case AHCI_CAP2:
2228 {
2229 uint32_t *p = &sc->cap;
2230 p += (offset - AHCI_CAP) / sizeof(uint32_t);
2231 value = *p;
2232 break;
2233 }
2234 default:
2235 value = 0;
2236 break;
2237 }
2238 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x",
2239 offset, value);
2240
2241 return (value);
2242 }
2243
2244 static uint64_t
pci_ahci_port_read(struct pci_ahci_softc * sc,uint64_t offset)2245 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
2246 {
2247 uint32_t value;
2248 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2249 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2250
2251 switch (offset) {
2252 case AHCI_P_CLB:
2253 case AHCI_P_CLBU:
2254 case AHCI_P_FB:
2255 case AHCI_P_FBU:
2256 case AHCI_P_IS:
2257 case AHCI_P_IE:
2258 case AHCI_P_CMD:
2259 case AHCI_P_TFD:
2260 case AHCI_P_SIG:
2261 case AHCI_P_SSTS:
2262 case AHCI_P_SCTL:
2263 case AHCI_P_SERR:
2264 case AHCI_P_SACT:
2265 case AHCI_P_CI:
2266 case AHCI_P_SNTF:
2267 case AHCI_P_FBS:
2268 {
2269 uint32_t *p= &sc->port[port].clb;
2270 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
2271 value = *p;
2272 break;
2273 }
2274 default:
2275 value = 0;
2276 break;
2277 }
2278
2279 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x",
2280 port, offset, value);
2281
2282 return value;
2283 }
2284
2285 static uint64_t
pci_ahci_read(struct pci_devinst * pi,int baridx,uint64_t regoff,int size)2286 pci_ahci_read(struct pci_devinst *pi, int baridx, uint64_t regoff, int size)
2287 {
2288 struct pci_ahci_softc *sc = pi->pi_arg;
2289 uint64_t offset;
2290 uint32_t value;
2291
2292 assert(baridx == 5);
2293 assert(size == 1 || size == 2 || size == 4);
2294 assert((regoff & (size - 1)) == 0);
2295
2296 pthread_mutex_lock(&sc->mtx);
2297
2298 offset = regoff & ~0x3; /* round down to a multiple of 4 bytes */
2299 if (offset < AHCI_OFFSET)
2300 value = pci_ahci_host_read(sc, offset);
2301 else if (offset < (uint64_t)AHCI_OFFSET + sc->ports * AHCI_STEP)
2302 value = pci_ahci_port_read(sc, offset);
2303 else {
2304 value = 0;
2305 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"",
2306 regoff);
2307 }
2308 value >>= 8 * (regoff & 0x3);
2309
2310 pthread_mutex_unlock(&sc->mtx);
2311
2312 return (value);
2313 }
2314
2315 /*
2316 * Each AHCI controller has a "port" node which contains nodes for
2317 * each port named after the decimal number of the port (no leading
2318 * zeroes). Port nodes contain a "type" ("hd" or "cd"), as well as
2319 * options for blockif. For example:
2320 *
2321 * pci.0.1.0
2322 * .device="ahci"
2323 * .port
2324 * .0
2325 * .type="hd"
2326 * .path="/path/to/image"
2327 */
2328 static int
pci_ahci_legacy_config_port(nvlist_t * nvl,int port,const char * type,const char * opts)2329 pci_ahci_legacy_config_port(nvlist_t *nvl, int port, const char *type,
2330 const char *opts)
2331 {
2332 char node_name[sizeof("XX")];
2333 nvlist_t *port_nvl;
2334
2335 snprintf(node_name, sizeof(node_name), "%d", port);
2336 port_nvl = create_relative_config_node(nvl, node_name);
2337 set_config_value_node(port_nvl, "type", type);
2338 return (blockif_legacy_config(port_nvl, opts));
2339 }
2340
2341 static int
pci_ahci_legacy_config(nvlist_t * nvl,const char * opts)2342 pci_ahci_legacy_config(nvlist_t *nvl, const char *opts)
2343 {
2344 nvlist_t *ports_nvl;
2345 const char *type;
2346 char *next, *next2, *str, *tofree;
2347 int p, ret;
2348
2349 if (opts == NULL)
2350 return (0);
2351
2352 ports_nvl = create_relative_config_node(nvl, "port");
2353 ret = 1;
2354 tofree = str = strdup(opts);
2355 for (p = 0; p < MAX_PORTS && str != NULL; p++, str = next) {
2356 /* Identify and cut off type of present port. */
2357 if (strncmp(str, "hd:", 3) == 0) {
2358 type = "hd";
2359 str += 3;
2360 } else if (strncmp(str, "cd:", 3) == 0) {
2361 type = "cd";
2362 str += 3;
2363 } else
2364 type = NULL;
2365
2366 /* Find and cut off the next port options. */
2367 next = strstr(str, ",hd:");
2368 next2 = strstr(str, ",cd:");
2369 if (next == NULL || (next2 != NULL && next2 < next))
2370 next = next2;
2371 if (next != NULL) {
2372 next[0] = 0;
2373 next++;
2374 }
2375
2376 if (str[0] == 0)
2377 continue;
2378
2379 if (type == NULL) {
2380 EPRINTLN("Missing or invalid type for port %d: \"%s\"",
2381 p, str);
2382 goto out;
2383 }
2384
2385 if (pci_ahci_legacy_config_port(ports_nvl, p, type, str) != 0)
2386 goto out;
2387 }
2388 ret = 0;
2389 out:
2390 free(tofree);
2391 return (ret);
2392 }
2393
2394 static int
pci_ahci_cd_legacy_config(nvlist_t * nvl,const char * opts)2395 pci_ahci_cd_legacy_config(nvlist_t *nvl, const char *opts)
2396 {
2397 nvlist_t *ports_nvl;
2398
2399 ports_nvl = create_relative_config_node(nvl, "port");
2400 return (pci_ahci_legacy_config_port(ports_nvl, 0, "cd", opts));
2401 }
2402
2403 static int
pci_ahci_hd_legacy_config(nvlist_t * nvl,const char * opts)2404 pci_ahci_hd_legacy_config(nvlist_t *nvl, const char *opts)
2405 {
2406 nvlist_t *ports_nvl;
2407
2408 ports_nvl = create_relative_config_node(nvl, "port");
2409 return (pci_ahci_legacy_config_port(ports_nvl, 0, "hd", opts));
2410 }
2411
2412 static int
pci_ahci_init(struct pci_devinst * pi,nvlist_t * nvl)2413 pci_ahci_init(struct pci_devinst *pi, nvlist_t *nvl)
2414 {
2415 char bident[sizeof("XXX:XXX:XXX")];
2416 char node_name[sizeof("XX")];
2417 struct blockif_ctxt *bctxt;
2418 struct pci_ahci_softc *sc;
2419 int atapi, ret, slots, p;
2420 MD5_CTX mdctx;
2421 u_char digest[16];
2422 const char *path, *type, *value;
2423 nvlist_t *ports_nvl, *port_nvl;
2424
2425 ret = 0;
2426
2427 #ifdef AHCI_DEBUG
2428 dbg = fopen("/tmp/log", "w+");
2429 #endif
2430
2431 sc = calloc(1, sizeof(struct pci_ahci_softc));
2432 pi->pi_arg = sc;
2433 sc->asc_pi = pi;
2434 pthread_mutex_init(&sc->mtx, NULL);
2435 sc->ports = 0;
2436 sc->pi = 0;
2437 slots = 32;
2438
2439 ports_nvl = find_relative_config_node(nvl, "port");
2440 for (p = 0; ports_nvl != NULL && p < MAX_PORTS; p++) {
2441 struct ata_params *ata_ident = &sc->port[p].ata_ident;
2442 char ident[AHCI_PORT_IDENT];
2443
2444 snprintf(node_name, sizeof(node_name), "%d", p);
2445 port_nvl = find_relative_config_node(ports_nvl, node_name);
2446 if (port_nvl == NULL)
2447 continue;
2448
2449 type = get_config_value_node(port_nvl, "type");
2450 if (type == NULL)
2451 continue;
2452
2453 if (strcmp(type, "hd") == 0)
2454 atapi = 0;
2455 else
2456 atapi = 1;
2457
2458 /*
2459 * Attempt to open the backing image. Use the PCI slot/func
2460 * and the port number for the identifier string.
2461 */
2462 snprintf(bident, sizeof(bident), "%u:%u:%u", pi->pi_slot,
2463 pi->pi_func, p);
2464
2465 bctxt = blockif_open(port_nvl, bident);
2466 if (bctxt == NULL) {
2467 sc->ports = p;
2468 ret = 1;
2469 goto open_fail;
2470 }
2471
2472 ret = blockif_add_boot_device(pi, bctxt);
2473 if (ret) {
2474 sc->ports = p;
2475 goto open_fail;
2476 }
2477
2478 sc->port[p].bctx = bctxt;
2479 sc->port[p].pr_sc = sc;
2480 sc->port[p].port = p;
2481 sc->port[p].atapi = atapi;
2482
2483 /*
2484 * Create an identifier for the backing file.
2485 * Use parts of the md5 sum of the filename
2486 */
2487 path = get_config_value_node(port_nvl, "path");
2488 MD5Init(&mdctx);
2489 MD5Update(&mdctx, path, strlen(path));
2490 MD5Final(digest, &mdctx);
2491 snprintf(ident, AHCI_PORT_IDENT,
2492 "BHYVE-%02X%02X-%02X%02X-%02X%02X",
2493 digest[0], digest[1], digest[2], digest[3], digest[4],
2494 digest[5]);
2495
2496 memset(ata_ident, 0, sizeof(struct ata_params));
2497 ata_string((uint8_t*)&ata_ident->serial, ident, 20);
2498 ata_string((uint8_t*)&ata_ident->revision, "001", 8);
2499 if (atapi)
2500 ata_string((uint8_t*)&ata_ident->model, "BHYVE SATA DVD ROM", 40);
2501 else
2502 ata_string((uint8_t*)&ata_ident->model, "BHYVE SATA DISK", 40);
2503 value = get_config_value_node(port_nvl, "nmrr");
2504 if (value != NULL)
2505 ata_ident->media_rotation_rate = atoi(value);
2506 value = get_config_value_node(port_nvl, "ser");
2507 if (value != NULL)
2508 ata_string((uint8_t*)(&ata_ident->serial), value, 20);
2509 value = get_config_value_node(port_nvl, "rev");
2510 if (value != NULL)
2511 ata_string((uint8_t*)(&ata_ident->revision), value, 8);
2512 value = get_config_value_node(port_nvl, "model");
2513 if (value != NULL)
2514 ata_string((uint8_t*)(&ata_ident->model), value, 40);
2515 ata_identify_init(&sc->port[p], atapi);
2516
2517 #ifndef __FreeBSD__
2518 /*
2519 * Attempt to enable the write cache for this device, as the
2520 * guest will issue FLUSH commands when it requires durability.
2521 *
2522 * Failure here is fine, since an always-sync device will not
2523 * have an impact on correctness.
2524 */
2525 (void) blockif_set_wce(bctxt, 1);
2526 #endif
2527
2528 /*
2529 * Allocate blockif request structures and add them
2530 * to the free list
2531 */
2532 pci_ahci_ioreq_init(&sc->port[p]);
2533
2534 sc->pi |= (1 << p);
2535 if (sc->port[p].ioqsz < slots)
2536 slots = sc->port[p].ioqsz;
2537 }
2538 sc->ports = p;
2539
2540 /* Intel ICH8 AHCI */
2541 --slots;
2542 if (sc->ports < DEF_PORTS)
2543 sc->ports = DEF_PORTS;
2544 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
2545 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
2546 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
2547 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
2548 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
2549
2550 sc->vs = 0x10300;
2551 sc->cap2 = AHCI_CAP2_APST;
2552 ahci_reset(sc);
2553
2554 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
2555 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2556 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
2557 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
2558 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
2559 p = MIN(sc->ports, 16);
2560 p = flsl(p) - ((p & (p - 1)) ? 0 : 1);
2561 pci_emul_add_msicap(pi, 1 << p);
2562 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
2563 AHCI_OFFSET + sc->ports * AHCI_STEP);
2564
2565 pci_lintr_request(pi);
2566
2567 open_fail:
2568 if (ret) {
2569 for (p = 0; p < sc->ports; p++) {
2570 if (sc->port[p].bctx != NULL)
2571 blockif_close(sc->port[p].bctx);
2572 }
2573 free(sc);
2574 }
2575
2576 return (ret);
2577 }
2578
2579 /*
2580 * Use separate emulation names to distinguish drive and atapi devices
2581 */
2582 static const struct pci_devemu pci_de_ahci = {
2583 .pe_emu = "ahci",
2584 .pe_init = pci_ahci_init,
2585 .pe_legacy_config = pci_ahci_legacy_config,
2586 .pe_barwrite = pci_ahci_write,
2587 .pe_barread = pci_ahci_read,
2588 };
2589 PCI_EMUL_SET(pci_de_ahci);
2590
2591 static const struct pci_devemu pci_de_ahci_hd = {
2592 .pe_emu = "ahci-hd",
2593 .pe_legacy_config = pci_ahci_hd_legacy_config,
2594 .pe_alias = "ahci",
2595 };
2596 PCI_EMUL_SET(pci_de_ahci_hd);
2597
2598 static const struct pci_devemu pci_de_ahci_cd = {
2599 .pe_emu = "ahci-cd",
2600 .pe_legacy_config = pci_ahci_cd_legacy_config,
2601 .pe_alias = "ahci",
2602 };
2603 PCI_EMUL_SET(pci_de_ahci_cd);
2604