184659b24SMichael Zeller /*- 2*32640292SAndy Fiddaman * SPDX-License-Identifier: BSD-2-Clause 384659b24SMichael Zeller * 484659b24SMichael Zeller * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 584659b24SMichael Zeller * All rights reserved. 684659b24SMichael Zeller * 784659b24SMichael Zeller * Redistribution and use in source and binary forms, with or without 884659b24SMichael Zeller * modification, are permitted provided that the following conditions 984659b24SMichael Zeller * are met: 1084659b24SMichael Zeller * 1. Redistributions of source code must retain the above copyright 1184659b24SMichael Zeller * notice, this list of conditions and the following disclaimer. 1284659b24SMichael Zeller * 2. Redistributions in binary form must reproduce the above copyright 1384659b24SMichael Zeller * notice, this list of conditions and the following disclaimer in the 1484659b24SMichael Zeller * documentation and/or other materials provided with the distribution. 1584659b24SMichael Zeller * 1684659b24SMichael Zeller * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1784659b24SMichael Zeller * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1884659b24SMichael Zeller * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1984659b24SMichael Zeller * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2084659b24SMichael Zeller * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2184659b24SMichael Zeller * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2284659b24SMichael Zeller * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2384659b24SMichael Zeller * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2484659b24SMichael Zeller * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2584659b24SMichael Zeller * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2684659b24SMichael Zeller * SUCH DAMAGE. 2784659b24SMichael Zeller */ 2884659b24SMichael Zeller 2984659b24SMichael Zeller #ifndef _HDAC_REG_H_ 3084659b24SMichael Zeller #define _HDAC_REG_H_ 3184659b24SMichael Zeller 3284659b24SMichael Zeller /**************************************************************************** 3384659b24SMichael Zeller * HDA Controller Register Set 3484659b24SMichael Zeller ****************************************************************************/ 3584659b24SMichael Zeller #define HDAC_GCAP 0x00 /* 2 - Global Capabilities*/ 3684659b24SMichael Zeller #define HDAC_VMIN 0x02 /* 1 - Minor Version */ 3784659b24SMichael Zeller #define HDAC_VMAJ 0x03 /* 1 - Major Version */ 3884659b24SMichael Zeller #define HDAC_OUTPAY 0x04 /* 2 - Output Payload Capability */ 3984659b24SMichael Zeller #define HDAC_INPAY 0x06 /* 2 - Input Payload Capability */ 4084659b24SMichael Zeller #define HDAC_GCTL 0x08 /* 4 - Global Control */ 4184659b24SMichael Zeller #define HDAC_WAKEEN 0x0c /* 2 - Wake Enable */ 4284659b24SMichael Zeller #define HDAC_STATESTS 0x0e /* 2 - State Change Status */ 4384659b24SMichael Zeller #define HDAC_GSTS 0x10 /* 2 - Global Status */ 4484659b24SMichael Zeller #define HDAC_OUTSTRMPAY 0x18 /* 2 - Output Stream Payload Capability */ 4584659b24SMichael Zeller #define HDAC_INSTRMPAY 0x1a /* 2 - Input Stream Payload Capability */ 4684659b24SMichael Zeller #define HDAC_INTCTL 0x20 /* 4 - Interrupt Control */ 4784659b24SMichael Zeller #define HDAC_INTSTS 0x24 /* 4 - Interrupt Status */ 4884659b24SMichael Zeller #define HDAC_WALCLK 0x30 /* 4 - Wall Clock Counter */ 4984659b24SMichael Zeller #define HDAC_SSYNC 0x38 /* 4 - Stream Synchronization */ 5084659b24SMichael Zeller #define HDAC_CORBLBASE 0x40 /* 4 - CORB Lower Base Address */ 5184659b24SMichael Zeller #define HDAC_CORBUBASE 0x44 /* 4 - CORB Upper Base Address */ 5284659b24SMichael Zeller #define HDAC_CORBWP 0x48 /* 2 - CORB Write Pointer */ 5384659b24SMichael Zeller #define HDAC_CORBRP 0x4a /* 2 - CORB Read Pointer */ 5484659b24SMichael Zeller #define HDAC_CORBCTL 0x4c /* 1 - CORB Control */ 5584659b24SMichael Zeller #define HDAC_CORBSTS 0x4d /* 1 - CORB Status */ 5684659b24SMichael Zeller #define HDAC_CORBSIZE 0x4e /* 1 - CORB Size */ 5784659b24SMichael Zeller #define HDAC_RIRBLBASE 0x50 /* 4 - RIRB Lower Base Address */ 5884659b24SMichael Zeller #define HDAC_RIRBUBASE 0x54 /* 4 - RIRB Upper Base Address */ 5984659b24SMichael Zeller #define HDAC_RIRBWP 0x58 /* 2 - RIRB Write Pointer */ 6084659b24SMichael Zeller #define HDAC_RINTCNT 0x5a /* 2 - Response Interrupt Count */ 6184659b24SMichael Zeller #define HDAC_RIRBCTL 0x5c /* 1 - RIRB Control */ 6284659b24SMichael Zeller #define HDAC_RIRBSTS 0x5d /* 1 - RIRB Status */ 6384659b24SMichael Zeller #define HDAC_RIRBSIZE 0x5e /* 1 - RIRB Size */ 6484659b24SMichael Zeller #define HDAC_ICOI 0x60 /* 4 - Immediate Command Output Interface */ 6584659b24SMichael Zeller #define HDAC_ICII 0x64 /* 4 - Immediate Command Input Interface */ 6684659b24SMichael Zeller #define HDAC_ICIS 0x68 /* 2 - Immediate Command Status */ 6784659b24SMichael Zeller #define HDAC_DPIBLBASE 0x70 /* 4 - DMA Position Buffer Lower Base */ 6884659b24SMichael Zeller #define HDAC_DPIBUBASE 0x74 /* 4 - DMA Position Buffer Upper Base */ 6984659b24SMichael Zeller #define HDAC_SDCTL0 0x80 /* 3 - Stream Descriptor Control */ 7084659b24SMichael Zeller #define HDAC_SDCTL1 0x81 /* 3 - Stream Descriptor Control */ 7184659b24SMichael Zeller #define HDAC_SDCTL2 0x82 /* 3 - Stream Descriptor Control */ 7284659b24SMichael Zeller #define HDAC_SDSTS 0x83 /* 1 - Stream Descriptor Status */ 7384659b24SMichael Zeller #define HDAC_SDLPIB 0x84 /* 4 - Link Position in Buffer */ 7484659b24SMichael Zeller #define HDAC_SDCBL 0x88 /* 4 - Cyclic Buffer Length */ 7584659b24SMichael Zeller #define HDAC_SDLVI 0x8C /* 2 - Last Valid Index */ 7684659b24SMichael Zeller #define HDAC_SDFIFOS 0x90 /* 2 - FIFOS */ 7784659b24SMichael Zeller #define HDAC_SDFMT 0x92 /* 2 - fmt */ 7884659b24SMichael Zeller #define HDAC_SDBDPL 0x98 /* 4 - Buffer Descriptor Pointer Lower Base */ 7984659b24SMichael Zeller #define HDAC_SDBDPU 0x9C /* 4 - Buffer Descriptor Pointer Upper Base */ 8084659b24SMichael Zeller 8184659b24SMichael Zeller #define _HDAC_ISDOFFSET(n, iss, oss) (0x80 + ((n) * 0x20)) 8284659b24SMichael Zeller #define _HDAC_ISDCTL(n, iss, oss) (0x00 + _HDAC_ISDOFFSET(n, iss, oss)) 8384659b24SMichael Zeller #define _HDAC_ISDSTS(n, iss, oss) (0x03 + _HDAC_ISDOFFSET(n, iss, oss)) 8484659b24SMichael Zeller #define _HDAC_ISDPICB(n, iss, oss) (0x04 + _HDAC_ISDOFFSET(n, iss, oss)) 8584659b24SMichael Zeller #define _HDAC_ISDCBL(n, iss, oss) (0x08 + _HDAC_ISDOFFSET(n, iss, oss)) 8684659b24SMichael Zeller #define _HDAC_ISDLVI(n, iss, oss) (0x0c + _HDAC_ISDOFFSET(n, iss, oss)) 8784659b24SMichael Zeller #define _HDAC_ISDFIFOD(n, iss, oss) (0x10 + _HDAC_ISDOFFSET(n, iss, oss)) 8884659b24SMichael Zeller #define _HDAC_ISDFMT(n, iss, oss) (0x12 + _HDAC_ISDOFFSET(n, iss, oss)) 8984659b24SMichael Zeller #define _HDAC_ISDBDPL(n, iss, oss) (0x18 + _HDAC_ISDOFFSET(n, iss, oss)) 9084659b24SMichael Zeller #define _HDAC_ISDBDPU(n, iss, oss) (0x1c + _HDAC_ISDOFFSET(n, iss, oss)) 9184659b24SMichael Zeller 9284659b24SMichael Zeller #define _HDAC_OSDOFFSET(n, iss, oss) (0x80 + ((iss) * 0x20) + ((n) * 0x20)) 9384659b24SMichael Zeller #define _HDAC_OSDCTL(n, iss, oss) (0x00 + _HDAC_OSDOFFSET(n, iss, oss)) 9484659b24SMichael Zeller #define _HDAC_OSDSTS(n, iss, oss) (0x03 + _HDAC_OSDOFFSET(n, iss, oss)) 9584659b24SMichael Zeller #define _HDAC_OSDPICB(n, iss, oss) (0x04 + _HDAC_OSDOFFSET(n, iss, oss)) 9684659b24SMichael Zeller #define _HDAC_OSDCBL(n, iss, oss) (0x08 + _HDAC_OSDOFFSET(n, iss, oss)) 9784659b24SMichael Zeller #define _HDAC_OSDLVI(n, iss, oss) (0x0c + _HDAC_OSDOFFSET(n, iss, oss)) 9884659b24SMichael Zeller #define _HDAC_OSDFIFOD(n, iss, oss) (0x10 + _HDAC_OSDOFFSET(n, iss, oss)) 9984659b24SMichael Zeller #define _HDAC_OSDFMT(n, iss, oss) (0x12 + _HDAC_OSDOFFSET(n, iss, oss)) 10084659b24SMichael Zeller #define _HDAC_OSDBDPL(n, iss, oss) (0x18 + _HDAC_OSDOFFSET(n, iss, oss)) 10184659b24SMichael Zeller #define _HDAC_OSDBDPU(n, iss, oss) (0x1c + _HDAC_OSDOFFSET(n, iss, oss)) 10284659b24SMichael Zeller 10384659b24SMichael Zeller #define _HDAC_BSDOFFSET(n, iss, oss) \ 10484659b24SMichael Zeller (0x80 + ((iss) * 0x20) + ((oss) * 0x20) + ((n) * 0x20)) 10584659b24SMichael Zeller #define _HDAC_BSDCTL(n, iss, oss) (0x00 + _HDAC_BSDOFFSET(n, iss, oss)) 10684659b24SMichael Zeller #define _HDAC_BSDSTS(n, iss, oss) (0x03 + _HDAC_BSDOFFSET(n, iss, oss)) 10784659b24SMichael Zeller #define _HDAC_BSDPICB(n, iss, oss) (0x04 + _HDAC_BSDOFFSET(n, iss, oss)) 10884659b24SMichael Zeller #define _HDAC_BSDCBL(n, iss, oss) (0x08 + _HDAC_BSDOFFSET(n, iss, oss)) 10984659b24SMichael Zeller #define _HDAC_BSDLVI(n, iss, oss) (0x0c + _HDAC_BSDOFFSET(n, iss, oss)) 11084659b24SMichael Zeller #define _HDAC_BSDFIFOD(n, iss, oss) (0x10 + _HDAC_BSDOFFSET(n, iss, oss)) 11184659b24SMichael Zeller #define _HDAC_BSDFMT(n, iss, oss) (0x12 + _HDAC_BSDOFFSET(n, iss, oss)) 11284659b24SMichael Zeller #define _HDAC_BSDBDPL(n, iss, oss) (0x18 + _HDAC_BSDOFFSET(n, iss, oss)) 11384659b24SMichael Zeller #define _HDAC_BSDBDBU(n, iss, oss) (0x1c + _HDAC_BSDOFFSET(n, iss, oss)) 11484659b24SMichael Zeller 11584659b24SMichael Zeller /**************************************************************************** 11684659b24SMichael Zeller * HDA Controller Register Fields 11784659b24SMichael Zeller ****************************************************************************/ 11884659b24SMichael Zeller 11984659b24SMichael Zeller /* GCAP - Global Capabilities */ 12084659b24SMichael Zeller #define HDAC_GCAP_64OK 0x0001 12184659b24SMichael Zeller #define HDAC_GCAP_NSDO_MASK 0x0006 12284659b24SMichael Zeller #define HDAC_GCAP_NSDO_SHIFT 1 12384659b24SMichael Zeller #define HDAC_GCAP_BSS_MASK 0x00f8 12484659b24SMichael Zeller #define HDAC_GCAP_BSS_SHIFT 3 12584659b24SMichael Zeller #define HDAC_GCAP_ISS_MASK 0x0f00 12684659b24SMichael Zeller #define HDAC_GCAP_ISS_SHIFT 8 12784659b24SMichael Zeller #define HDAC_GCAP_OSS_MASK 0xf000 12884659b24SMichael Zeller #define HDAC_GCAP_OSS_SHIFT 12 12984659b24SMichael Zeller 13084659b24SMichael Zeller #define HDAC_GCAP_NSDO_1SDO 0x00 13184659b24SMichael Zeller #define HDAC_GCAP_NSDO_2SDO 0x02 13284659b24SMichael Zeller #define HDAC_GCAP_NSDO_4SDO 0x04 13384659b24SMichael Zeller 13484659b24SMichael Zeller #define HDAC_GCAP_BSS(gcap) \ 13584659b24SMichael Zeller (((gcap) & HDAC_GCAP_BSS_MASK) >> HDAC_GCAP_BSS_SHIFT) 13684659b24SMichael Zeller #define HDAC_GCAP_ISS(gcap) \ 13784659b24SMichael Zeller (((gcap) & HDAC_GCAP_ISS_MASK) >> HDAC_GCAP_ISS_SHIFT) 13884659b24SMichael Zeller #define HDAC_GCAP_OSS(gcap) \ 13984659b24SMichael Zeller (((gcap) & HDAC_GCAP_OSS_MASK) >> HDAC_GCAP_OSS_SHIFT) 14084659b24SMichael Zeller #define HDAC_GCAP_NSDO(gcap) \ 14184659b24SMichael Zeller (((gcap) & HDAC_GCAP_NSDO_MASK) >> HDAC_GCAP_NSDO_SHIFT) 14284659b24SMichael Zeller 14384659b24SMichael Zeller /* GCTL - Global Control */ 14484659b24SMichael Zeller #define HDAC_GCTL_CRST 0x00000001 14584659b24SMichael Zeller #define HDAC_GCTL_FCNTRL 0x00000002 14684659b24SMichael Zeller #define HDAC_GCTL_UNSOL 0x00000100 14784659b24SMichael Zeller 14884659b24SMichael Zeller /* WAKEEN - Wake Enable */ 14984659b24SMichael Zeller #define HDAC_WAKEEN_SDIWEN_MASK 0x7fff 15084659b24SMichael Zeller #define HDAC_WAKEEN_SDIWEN_SHIFT 0 15184659b24SMichael Zeller 15284659b24SMichael Zeller /* STATESTS - State Change Status */ 15384659b24SMichael Zeller #define HDAC_STATESTS_SDIWAKE_MASK 0x7fff 15484659b24SMichael Zeller #define HDAC_STATESTS_SDIWAKE_SHIFT 0 15584659b24SMichael Zeller 15684659b24SMichael Zeller #define HDAC_STATESTS_SDIWAKE(statests, n) \ 15784659b24SMichael Zeller (((((statests) & HDAC_STATESTS_SDIWAKE_MASK) >> \ 15884659b24SMichael Zeller HDAC_STATESTS_SDIWAKE_SHIFT) >> (n)) & 0x0001) 15984659b24SMichael Zeller 16084659b24SMichael Zeller /* GSTS - Global Status */ 16184659b24SMichael Zeller #define HDAC_GSTS_FSTS 0x0002 16284659b24SMichael Zeller 16384659b24SMichael Zeller /* INTCTL - Interrut Control */ 16484659b24SMichael Zeller #define HDAC_INTCTL_SIE_MASK 0x3fffffff 16584659b24SMichael Zeller #define HDAC_INTCTL_SIE_SHIFT 0 16684659b24SMichael Zeller #define HDAC_INTCTL_CIE 0x40000000 16784659b24SMichael Zeller #define HDAC_INTCTL_GIE 0x80000000 16884659b24SMichael Zeller 16984659b24SMichael Zeller /* INTSTS - Interrupt Status */ 17084659b24SMichael Zeller #define HDAC_INTSTS_SIS_MASK 0x3fffffff 17184659b24SMichael Zeller #define HDAC_INTSTS_SIS_SHIFT 0 17284659b24SMichael Zeller #define HDAC_INTSTS_CIS 0x40000000 17384659b24SMichael Zeller #define HDAC_INTSTS_GIS 0x80000000 17484659b24SMichael Zeller 17584659b24SMichael Zeller /* SSYNC - Stream Synchronization */ 17684659b24SMichael Zeller #define HDAC_SSYNC_SSYNC_MASK 0x3fffffff 17784659b24SMichael Zeller #define HDAC_SSYNC_SSYNC_SHIFT 0 17884659b24SMichael Zeller 17984659b24SMichael Zeller /* CORBWP - CORB Write Pointer */ 18084659b24SMichael Zeller #define HDAC_CORBWP_CORBWP_MASK 0x00ff 18184659b24SMichael Zeller #define HDAC_CORBWP_CORBWP_SHIFT 0 18284659b24SMichael Zeller 18384659b24SMichael Zeller /* CORBRP - CORB Read Pointer */ 18484659b24SMichael Zeller #define HDAC_CORBRP_CORBRP_MASK 0x00ff 18584659b24SMichael Zeller #define HDAC_CORBRP_CORBRP_SHIFT 0 18684659b24SMichael Zeller #define HDAC_CORBRP_CORBRPRST 0x8000 18784659b24SMichael Zeller 18884659b24SMichael Zeller /* CORBCTL - CORB Control */ 18984659b24SMichael Zeller #define HDAC_CORBCTL_CMEIE 0x01 19084659b24SMichael Zeller #define HDAC_CORBCTL_CORBRUN 0x02 19184659b24SMichael Zeller 19284659b24SMichael Zeller /* CORBSTS - CORB Status */ 19384659b24SMichael Zeller #define HDAC_CORBSTS_CMEI 0x01 19484659b24SMichael Zeller 19584659b24SMichael Zeller /* CORBSIZE - CORB Size */ 19684659b24SMichael Zeller #define HDAC_CORBSIZE_CORBSIZE_MASK 0x03 19784659b24SMichael Zeller #define HDAC_CORBSIZE_CORBSIZE_SHIFT 0 19884659b24SMichael Zeller #define HDAC_CORBSIZE_CORBSZCAP_MASK 0xf0 19984659b24SMichael Zeller #define HDAC_CORBSIZE_CORBSZCAP_SHIFT 4 20084659b24SMichael Zeller 20184659b24SMichael Zeller #define HDAC_CORBSIZE_CORBSIZE_2 0x00 20284659b24SMichael Zeller #define HDAC_CORBSIZE_CORBSIZE_16 0x01 20384659b24SMichael Zeller #define HDAC_CORBSIZE_CORBSIZE_256 0x02 20484659b24SMichael Zeller 20584659b24SMichael Zeller #define HDAC_CORBSIZE_CORBSZCAP_2 0x10 20684659b24SMichael Zeller #define HDAC_CORBSIZE_CORBSZCAP_16 0x20 20784659b24SMichael Zeller #define HDAC_CORBSIZE_CORBSZCAP_256 0x40 20884659b24SMichael Zeller 20984659b24SMichael Zeller #define HDAC_CORBSIZE_CORBSIZE(corbsize) \ 21084659b24SMichael Zeller (((corbsize) & HDAC_CORBSIZE_CORBSIZE_MASK) >> HDAC_CORBSIZE_CORBSIZE_SHIFT) 21184659b24SMichael Zeller 21284659b24SMichael Zeller /* RIRBWP - RIRB Write Pointer */ 21384659b24SMichael Zeller #define HDAC_RIRBWP_RIRBWP_MASK 0x00ff 21484659b24SMichael Zeller #define HDAC_RIRBWP_RIRBWP_SHIFT 0 21584659b24SMichael Zeller #define HDAC_RIRBWP_RIRBWPRST 0x8000 21684659b24SMichael Zeller 21784659b24SMichael Zeller /* RINTCTN - Response Interrupt Count */ 21884659b24SMichael Zeller #define HDAC_RINTCNT_MASK 0x00ff 21984659b24SMichael Zeller #define HDAC_RINTCNT_SHIFT 0 22084659b24SMichael Zeller 22184659b24SMichael Zeller /* RIRBCTL - RIRB Control */ 22284659b24SMichael Zeller #define HDAC_RIRBCTL_RINTCTL 0x01 22384659b24SMichael Zeller #define HDAC_RIRBCTL_RIRBDMAEN 0x02 22484659b24SMichael Zeller #define HDAC_RIRBCTL_RIRBOIC 0x04 22584659b24SMichael Zeller 22684659b24SMichael Zeller /* RIRBSTS - RIRB Status */ 22784659b24SMichael Zeller #define HDAC_RIRBSTS_RINTFL 0x01 22884659b24SMichael Zeller #define HDAC_RIRBSTS_RIRBOIS 0x04 22984659b24SMichael Zeller 23084659b24SMichael Zeller /* RIRBSIZE - RIRB Size */ 23184659b24SMichael Zeller #define HDAC_RIRBSIZE_RIRBSIZE_MASK 0x03 23284659b24SMichael Zeller #define HDAC_RIRBSIZE_RIRBSIZE_SHIFT 0 23384659b24SMichael Zeller #define HDAC_RIRBSIZE_RIRBSZCAP_MASK 0xf0 23484659b24SMichael Zeller #define HDAC_RIRBSIZE_RIRBSZCAP_SHIFT 4 23584659b24SMichael Zeller 23684659b24SMichael Zeller #define HDAC_RIRBSIZE_RIRBSIZE_2 0x00 23784659b24SMichael Zeller #define HDAC_RIRBSIZE_RIRBSIZE_16 0x01 23884659b24SMichael Zeller #define HDAC_RIRBSIZE_RIRBSIZE_256 0x02 23984659b24SMichael Zeller 24084659b24SMichael Zeller #define HDAC_RIRBSIZE_RIRBSZCAP_2 0x10 24184659b24SMichael Zeller #define HDAC_RIRBSIZE_RIRBSZCAP_16 0x20 24284659b24SMichael Zeller #define HDAC_RIRBSIZE_RIRBSZCAP_256 0x40 24384659b24SMichael Zeller 24484659b24SMichael Zeller #define HDAC_RIRBSIZE_RIRBSIZE(rirbsize) \ 24584659b24SMichael Zeller (((rirbsize) & HDAC_RIRBSIZE_RIRBSIZE_MASK) >> HDAC_RIRBSIZE_RIRBSIZE_SHIFT) 24684659b24SMichael Zeller 24784659b24SMichael Zeller /* DPLBASE - DMA Position Lower Base Address */ 24884659b24SMichael Zeller #define HDAC_DPLBASE_DPLBASE_MASK 0xffffff80 24984659b24SMichael Zeller #define HDAC_DPLBASE_DPLBASE_SHIFT 7 25084659b24SMichael Zeller #define HDAC_DPLBASE_DPLBASE_DMAPBE 0x00000001 25184659b24SMichael Zeller 25284659b24SMichael Zeller /* SDCTL - Stream Descriptor Control */ 25384659b24SMichael Zeller #define HDAC_SDCTL_SRST 0x000001 25484659b24SMichael Zeller #define HDAC_SDCTL_RUN 0x000002 25584659b24SMichael Zeller #define HDAC_SDCTL_IOCE 0x000004 25684659b24SMichael Zeller #define HDAC_SDCTL_FEIE 0x000008 25784659b24SMichael Zeller #define HDAC_SDCTL_DEIE 0x000010 25884659b24SMichael Zeller #define HDAC_SDCTL2_STRIPE_MASK 0x03 25984659b24SMichael Zeller #define HDAC_SDCTL2_STRIPE_SHIFT 0 26084659b24SMichael Zeller #define HDAC_SDCTL2_TP 0x04 26184659b24SMichael Zeller #define HDAC_SDCTL2_DIR 0x08 26284659b24SMichael Zeller #define HDAC_SDCTL2_STRM_MASK 0xf0 26384659b24SMichael Zeller #define HDAC_SDCTL2_STRM_SHIFT 4 26484659b24SMichael Zeller 26584659b24SMichael Zeller #define HDAC_SDSTS_DESE (1 << 4) 26684659b24SMichael Zeller #define HDAC_SDSTS_FIFOE (1 << 3) 26784659b24SMichael Zeller #define HDAC_SDSTS_BCIS (1 << 2) 26884659b24SMichael Zeller 26984659b24SMichael Zeller #endif /* _HDAC_REG_H_ */ 270