184659b24SMichael Zeller /*- 2*32640292SAndy Fiddaman * SPDX-License-Identifier: BSD-2-Clause 384659b24SMichael Zeller * 484659b24SMichael Zeller * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 584659b24SMichael Zeller * All rights reserved. 684659b24SMichael Zeller * 784659b24SMichael Zeller * Redistribution and use in source and binary forms, with or without 884659b24SMichael Zeller * modification, are permitted provided that the following conditions 984659b24SMichael Zeller * are met: 1084659b24SMichael Zeller * 1. Redistributions of source code must retain the above copyright 1184659b24SMichael Zeller * notice, this list of conditions and the following disclaimer. 1284659b24SMichael Zeller * 2. Redistributions in binary form must reproduce the above copyright 1384659b24SMichael Zeller * notice, this list of conditions and the following disclaimer in the 1484659b24SMichael Zeller * documentation and/or other materials provided with the distribution. 1584659b24SMichael Zeller * 1684659b24SMichael Zeller * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1784659b24SMichael Zeller * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1884659b24SMichael Zeller * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1984659b24SMichael Zeller * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2084659b24SMichael Zeller * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2184659b24SMichael Zeller * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2284659b24SMichael Zeller * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2384659b24SMichael Zeller * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2484659b24SMichael Zeller * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2584659b24SMichael Zeller * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2684659b24SMichael Zeller * SUCH DAMAGE. 2784659b24SMichael Zeller */ 2884659b24SMichael Zeller 2984659b24SMichael Zeller #ifndef _HDA_REG_H_ 3084659b24SMichael Zeller #define _HDA_REG_H_ 3184659b24SMichael Zeller 3284659b24SMichael Zeller /**************************************************************************** 3384659b24SMichael Zeller * HDA Device Verbs 3484659b24SMichael Zeller ****************************************************************************/ 3584659b24SMichael Zeller 3684659b24SMichael Zeller /* HDA Command */ 3784659b24SMichael Zeller #define HDA_CMD_VERB_MASK 0x000fffff 3884659b24SMichael Zeller #define HDA_CMD_VERB_SHIFT 0 3984659b24SMichael Zeller #define HDA_CMD_NID_MASK 0x0ff00000 4084659b24SMichael Zeller #define HDA_CMD_NID_SHIFT 20 4184659b24SMichael Zeller #define HDA_CMD_CAD_MASK 0xf0000000 4284659b24SMichael Zeller #define HDA_CMD_CAD_SHIFT 28 4384659b24SMichael Zeller 4484659b24SMichael Zeller #define HDA_CMD_VERB_4BIT_SHIFT 16 4584659b24SMichael Zeller #define HDA_CMD_VERB_12BIT_SHIFT 8 4684659b24SMichael Zeller 4784659b24SMichael Zeller #define HDA_CMD_VERB_4BIT(verb, payload) \ 4884659b24SMichael Zeller (((verb) << HDA_CMD_VERB_4BIT_SHIFT) | (payload)) 4984659b24SMichael Zeller #define HDA_CMD_4BIT(cad, nid, verb, payload) \ 5084659b24SMichael Zeller (((cad) << HDA_CMD_CAD_SHIFT) | \ 5184659b24SMichael Zeller ((nid) << HDA_CMD_NID_SHIFT) | \ 5284659b24SMichael Zeller (HDA_CMD_VERB_4BIT((verb), (payload)))) 5384659b24SMichael Zeller 5484659b24SMichael Zeller #define HDA_CMD_VERB_12BIT(verb, payload) \ 5584659b24SMichael Zeller (((verb) << HDA_CMD_VERB_12BIT_SHIFT) | (payload)) 5684659b24SMichael Zeller #define HDA_CMD_12BIT(cad, nid, verb, payload) \ 5784659b24SMichael Zeller (((cad) << HDA_CMD_CAD_SHIFT) | \ 5884659b24SMichael Zeller ((nid) << HDA_CMD_NID_SHIFT) | \ 5984659b24SMichael Zeller (HDA_CMD_VERB_12BIT((verb), (payload)))) 6084659b24SMichael Zeller 6184659b24SMichael Zeller /* Get Parameter */ 6284659b24SMichael Zeller #define HDA_CMD_VERB_GET_PARAMETER 0xf00 6384659b24SMichael Zeller 6484659b24SMichael Zeller #define HDA_CMD_GET_PARAMETER(cad, nid, payload) \ 6584659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 6684659b24SMichael Zeller HDA_CMD_VERB_GET_PARAMETER, (payload))) 6784659b24SMichael Zeller 6884659b24SMichael Zeller /* Connection Select Control */ 6984659b24SMichael Zeller #define HDA_CMD_VERB_GET_CONN_SELECT_CONTROL 0xf01 7084659b24SMichael Zeller #define HDA_CMD_VERB_SET_CONN_SELECT_CONTROL 0x701 7184659b24SMichael Zeller 7284659b24SMichael Zeller #define HDA_CMD_GET_CONN_SELECT_CONTROL(cad, nid) \ 7384659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 7484659b24SMichael Zeller HDA_CMD_VERB_GET_CONN_SELECT_CONTROL, 0x0)) 7584659b24SMichael Zeller #define HDA_CMD_SET_CONNECTION_SELECT_CONTROL(cad, nid, payload) \ 7684659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 7784659b24SMichael Zeller HDA_CMD_VERB_SET_CONN_SELECT_CONTROL, (payload))) 7884659b24SMichael Zeller 7984659b24SMichael Zeller /* Connection List Entry */ 8084659b24SMichael Zeller #define HDA_CMD_VERB_GET_CONN_LIST_ENTRY 0xf02 8184659b24SMichael Zeller 8284659b24SMichael Zeller #define HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, payload) \ 8384659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 8484659b24SMichael Zeller HDA_CMD_VERB_GET_CONN_LIST_ENTRY, (payload))) 8584659b24SMichael Zeller 8684659b24SMichael Zeller #define HDA_CMD_GET_CONN_LIST_ENTRY_SIZE_SHORT 1 8784659b24SMichael Zeller #define HDA_CMD_GET_CONN_LIST_ENTRY_SIZE_LONG 2 8884659b24SMichael Zeller 8984659b24SMichael Zeller /* Processing State */ 9084659b24SMichael Zeller #define HDA_CMD_VERB_GET_PROCESSING_STATE 0xf03 9184659b24SMichael Zeller #define HDA_CMD_VERB_SET_PROCESSING_STATE 0x703 9284659b24SMichael Zeller 9384659b24SMichael Zeller #define HDA_CMD_GET_PROCESSING_STATE(cad, nid) \ 9484659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 9584659b24SMichael Zeller HDA_CMD_VERB_GET_PROCESSING_STATE, 0x0)) 9684659b24SMichael Zeller #define HDA_CMD_SET_PROCESSING_STATE(cad, nid, payload) \ 9784659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 9884659b24SMichael Zeller HDA_CMD_VERB_SET_PROCESSING_STATE, (payload))) 9984659b24SMichael Zeller 10084659b24SMichael Zeller #define HDA_CMD_GET_PROCESSING_STATE_STATE_OFF 0x00 10184659b24SMichael Zeller #define HDA_CMD_GET_PROCESSING_STATE_STATE_ON 0x01 10284659b24SMichael Zeller #define HDA_CMD_GET_PROCESSING_STATE_STATE_BENIGN 0x02 10384659b24SMichael Zeller 10484659b24SMichael Zeller /* Coefficient Index */ 10584659b24SMichael Zeller #define HDA_CMD_VERB_GET_COEFF_INDEX 0xd 10684659b24SMichael Zeller #define HDA_CMD_VERB_SET_COEFF_INDEX 0x5 10784659b24SMichael Zeller 10884659b24SMichael Zeller #define HDA_CMD_GET_COEFF_INDEX(cad, nid) \ 10984659b24SMichael Zeller (HDA_CMD_4BIT((cad), (nid), \ 11084659b24SMichael Zeller HDA_CMD_VERB_GET_COEFF_INDEX, 0x0)) 11184659b24SMichael Zeller #define HDA_CMD_SET_COEFF_INDEX(cad, nid, payload) \ 11284659b24SMichael Zeller (HDA_CMD_4BIT((cad), (nid), \ 11384659b24SMichael Zeller HDA_CMD_VERB_SET_COEFF_INDEX, (payload))) 11484659b24SMichael Zeller 11584659b24SMichael Zeller /* Processing Coefficient */ 11684659b24SMichael Zeller #define HDA_CMD_VERB_GET_PROCESSING_COEFF 0xc 11784659b24SMichael Zeller #define HDA_CMD_VERB_SET_PROCESSING_COEFF 0x4 11884659b24SMichael Zeller 11984659b24SMichael Zeller #define HDA_CMD_GET_PROCESSING_COEFF(cad, nid) \ 12084659b24SMichael Zeller (HDA_CMD_4BIT((cad), (nid), \ 12184659b24SMichael Zeller HDA_CMD_VERB_GET_PROCESSING_COEFF, 0x0)) 12284659b24SMichael Zeller #define HDA_CMD_SET_PROCESSING_COEFF(cad, nid, payload) \ 12384659b24SMichael Zeller (HDA_CMD_4BIT((cad), (nid), \ 12484659b24SMichael Zeller HDA_CMD_VERB_SET_PROCESSING_COEFF, (payload))) 12584659b24SMichael Zeller 12684659b24SMichael Zeller /* Amplifier Gain/Mute */ 12784659b24SMichael Zeller #define HDA_CMD_VERB_GET_AMP_GAIN_MUTE 0xb 12884659b24SMichael Zeller #define HDA_CMD_VERB_SET_AMP_GAIN_MUTE 0x3 12984659b24SMichael Zeller 13084659b24SMichael Zeller #define HDA_CMD_GET_AMP_GAIN_MUTE(cad, nid, payload) \ 13184659b24SMichael Zeller (HDA_CMD_4BIT((cad), (nid), \ 13284659b24SMichael Zeller HDA_CMD_VERB_GET_AMP_GAIN_MUTE, (payload))) 13384659b24SMichael Zeller #define HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, payload) \ 13484659b24SMichael Zeller (HDA_CMD_4BIT((cad), (nid), \ 13584659b24SMichael Zeller HDA_CMD_VERB_SET_AMP_GAIN_MUTE, (payload))) 13684659b24SMichael Zeller 13784659b24SMichael Zeller #define HDA_CMD_GET_AMP_GAIN_MUTE_INPUT 0x0000 13884659b24SMichael Zeller #define HDA_CMD_GET_AMP_GAIN_MUTE_OUTPUT 0x8000 13984659b24SMichael Zeller #define HDA_CMD_GET_AMP_GAIN_MUTE_RIGHT 0x0000 14084659b24SMichael Zeller #define HDA_CMD_GET_AMP_GAIN_MUTE_LEFT 0x2000 14184659b24SMichael Zeller 14284659b24SMichael Zeller #define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_MASK 0x00000008 14384659b24SMichael Zeller #define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_SHIFT 7 14484659b24SMichael Zeller #define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_MASK 0x00000007 14584659b24SMichael Zeller #define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_SHIFT 0 14684659b24SMichael Zeller 14784659b24SMichael Zeller #define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE(rsp) \ 14884659b24SMichael Zeller (((rsp) & HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_MASK) >> \ 14984659b24SMichael Zeller HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_SHIFT) 15084659b24SMichael Zeller #define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN(rsp) \ 15184659b24SMichael Zeller (((rsp) & HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_MASK) >> \ 15284659b24SMichael Zeller HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_SHIFT) 15384659b24SMichael Zeller 15484659b24SMichael Zeller #define HDA_CMD_SET_AMP_GAIN_MUTE_OUTPUT 0x8000 15584659b24SMichael Zeller #define HDA_CMD_SET_AMP_GAIN_MUTE_INPUT 0x4000 15684659b24SMichael Zeller #define HDA_CMD_SET_AMP_GAIN_MUTE_LEFT 0x2000 15784659b24SMichael Zeller #define HDA_CMD_SET_AMP_GAIN_MUTE_RIGHT 0x1000 15884659b24SMichael Zeller #define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_MASK 0x0f00 15984659b24SMichael Zeller #define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_SHIFT 8 16084659b24SMichael Zeller #define HDA_CMD_SET_AMP_GAIN_MUTE_MUTE 0x0080 16184659b24SMichael Zeller #define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_MASK 0x0007 16284659b24SMichael Zeller #define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_SHIFT 0 16384659b24SMichael Zeller 16484659b24SMichael Zeller #define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX(index) \ 16584659b24SMichael Zeller (((index) << HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_SHIFT) & \ 16684659b24SMichael Zeller HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_MASK) 16784659b24SMichael Zeller #define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN(index) \ 16884659b24SMichael Zeller (((index) << HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_SHIFT) & \ 16984659b24SMichael Zeller HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_MASK) 17084659b24SMichael Zeller 17184659b24SMichael Zeller /* Converter format */ 17284659b24SMichael Zeller #define HDA_CMD_VERB_GET_CONV_FMT 0xa 17384659b24SMichael Zeller #define HDA_CMD_VERB_SET_CONV_FMT 0x2 17484659b24SMichael Zeller 17584659b24SMichael Zeller #define HDA_CMD_GET_CONV_FMT(cad, nid) \ 17684659b24SMichael Zeller (HDA_CMD_4BIT((cad), (nid), \ 17784659b24SMichael Zeller HDA_CMD_VERB_GET_CONV_FMT, 0x0)) 17884659b24SMichael Zeller #define HDA_CMD_SET_CONV_FMT(cad, nid, payload) \ 17984659b24SMichael Zeller (HDA_CMD_4BIT((cad), (nid), \ 18084659b24SMichael Zeller HDA_CMD_VERB_SET_CONV_FMT, (payload))) 18184659b24SMichael Zeller 18284659b24SMichael Zeller /* Digital Converter Control */ 18384659b24SMichael Zeller #define HDA_CMD_VERB_GET_DIGITAL_CONV_FMT1 0xf0d 18484659b24SMichael Zeller #define HDA_CMD_VERB_GET_DIGITAL_CONV_FMT2 0xf0e 18584659b24SMichael Zeller #define HDA_CMD_VERB_SET_DIGITAL_CONV_FMT1 0x70d 18684659b24SMichael Zeller #define HDA_CMD_VERB_SET_DIGITAL_CONV_FMT2 0x70e 18784659b24SMichael Zeller 18884659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT(cad, nid) \ 18984659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 19084659b24SMichael Zeller HDA_CMD_VERB_GET_DIGITAL_CONV_FMT1, 0x0)) 19184659b24SMichael Zeller #define HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, nid, payload) \ 19284659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 19384659b24SMichael Zeller HDA_CMD_VERB_SET_DIGITAL_CONV_FMT1, (payload))) 19484659b24SMichael Zeller #define HDA_CMD_SET_DIGITAL_CONV_FMT2(cad, nid, payload) \ 19584659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 19684659b24SMichael Zeller HDA_CMD_VERB_SET_DIGITAL_CONV_FMT2, (payload))) 19784659b24SMichael Zeller 19884659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_CC_MASK 0x7f00 19984659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_CC_SHIFT 8 20084659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_L_MASK 0x0080 20184659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_L_SHIFT 7 20284659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_MASK 0x0040 20384659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_SHIFT 6 20484659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_MASK 0x0020 20584659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_SHIFT 5 20684659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_MASK 0x0010 20784659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_SHIFT 4 20884659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_MASK 0x0008 20984659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_SHIFT 3 21084659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_MASK 0x0004 21184659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_SHIFT 2 21284659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_V_MASK 0x0002 21384659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_V_SHIFT 1 21484659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_MASK 0x0001 21584659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_SHIFT 0 21684659b24SMichael Zeller 21784659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_CC(rsp) \ 21884659b24SMichael Zeller (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_CC_MASK) >> \ 21984659b24SMichael Zeller HDA_CMD_GET_DIGITAL_CONV_FMT_CC_SHIFT) 22084659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_L(rsp) \ 22184659b24SMichael Zeller (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_L_MASK) >> \ 22284659b24SMichael Zeller HDA_CMD_GET_DIGITAL_CONV_FMT_L_SHIFT) 22384659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO(rsp) \ 22484659b24SMichael Zeller (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_MASK) >> \ 22584659b24SMichael Zeller HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_SHIFT) 22684659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO(rsp) \ 22784659b24SMichael Zeller (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_MASK) >> \ 22884659b24SMichael Zeller HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_SHIFT) 22984659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY(rsp) \ 23084659b24SMichael Zeller (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_MASK) >> \ 23184659b24SMichael Zeller HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_SHIFT) 23284659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE(rsp) \ 23384659b24SMichael Zeller (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_MASK) >> \ 23484659b24SMichael Zeller HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_SHIFT) 23584659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG(rsp) \ 23684659b24SMichael Zeller (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_MASK) >> \ 23784659b24SMichael Zeller HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_SHIFT) 23884659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_V(rsp) \ 23984659b24SMichael Zeller (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_V_MASK) >> \ 24084659b24SMichael Zeller HDA_CMD_GET_DIGITAL_CONV_FMT_V_SHIFT) 24184659b24SMichael Zeller #define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN(rsp) \ 24284659b24SMichael Zeller (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_MASK) >> \ 24384659b24SMichael Zeller HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_SHIFT) 24484659b24SMichael Zeller 24584659b24SMichael Zeller #define HDA_CMD_SET_DIGITAL_CONV_FMT1_L 0x80 24684659b24SMichael Zeller #define HDA_CMD_SET_DIGITAL_CONV_FMT1_PRO 0x40 24784659b24SMichael Zeller #define HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO 0x20 24884659b24SMichael Zeller #define HDA_CMD_SET_DIGITAL_CONV_FMT1_COPY 0x10 24984659b24SMichael Zeller #define HDA_CMD_SET_DIGITAL_CONV_FMT1_PRE 0x08 25084659b24SMichael Zeller #define HDA_CMD_SET_DIGITAL_CONV_FMT1_VCFG 0x04 25184659b24SMichael Zeller #define HDA_CMD_SET_DIGITAL_CONV_FMT1_V 0x02 25284659b24SMichael Zeller #define HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN 0x01 25384659b24SMichael Zeller 25484659b24SMichael Zeller /* Power State */ 25584659b24SMichael Zeller #define HDA_CMD_VERB_GET_POWER_STATE 0xf05 25684659b24SMichael Zeller #define HDA_CMD_VERB_SET_POWER_STATE 0x705 25784659b24SMichael Zeller 25884659b24SMichael Zeller #define HDA_CMD_GET_POWER_STATE(cad, nid) \ 25984659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 26084659b24SMichael Zeller HDA_CMD_VERB_GET_POWER_STATE, 0x0)) 26184659b24SMichael Zeller #define HDA_CMD_SET_POWER_STATE(cad, nid, payload) \ 26284659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 26384659b24SMichael Zeller HDA_CMD_VERB_SET_POWER_STATE, (payload))) 26484659b24SMichael Zeller 26584659b24SMichael Zeller #define HDA_CMD_POWER_STATE_D0 0x00 26684659b24SMichael Zeller #define HDA_CMD_POWER_STATE_D1 0x01 26784659b24SMichael Zeller #define HDA_CMD_POWER_STATE_D2 0x02 26884659b24SMichael Zeller #define HDA_CMD_POWER_STATE_D3 0x03 26984659b24SMichael Zeller 27084659b24SMichael Zeller #define HDA_CMD_POWER_STATE_ACT_MASK 0x000000f0 27184659b24SMichael Zeller #define HDA_CMD_POWER_STATE_ACT_SHIFT 4 27284659b24SMichael Zeller #define HDA_CMD_POWER_STATE_SET_MASK 0x0000000f 27384659b24SMichael Zeller #define HDA_CMD_POWER_STATE_SET_SHIFT 0 27484659b24SMichael Zeller 27584659b24SMichael Zeller #define HDA_CMD_GET_POWER_STATE_ACT(rsp) \ 27684659b24SMichael Zeller (((rsp) & HDA_CMD_POWER_STATE_ACT_MASK) >> \ 27784659b24SMichael Zeller HDA_CMD_POWER_STATE_ACT_SHIFT) 27884659b24SMichael Zeller #define HDA_CMD_GET_POWER_STATE_SET(rsp) \ 27984659b24SMichael Zeller (((rsp) & HDA_CMD_POWER_STATE_SET_MASK) >> \ 28084659b24SMichael Zeller HDA_CMD_POWER_STATE_SET_SHIFT) 28184659b24SMichael Zeller 28284659b24SMichael Zeller #define HDA_CMD_SET_POWER_STATE_ACT(ps) \ 28384659b24SMichael Zeller (((ps) << HDA_CMD_POWER_STATE_ACT_SHIFT) & \ 28484659b24SMichael Zeller HDA_CMD_POWER_STATE_ACT_MASK) 28584659b24SMichael Zeller #define HDA_CMD_SET_POWER_STATE_SET(ps) \ 28684659b24SMichael Zeller (((ps) << HDA_CMD_POWER_STATE_SET_SHIFT) & \ 28784659b24SMichael Zeller HDA_CMD_POWER_STATE_ACT_MASK) 28884659b24SMichael Zeller 28984659b24SMichael Zeller /* Converter Stream, Channel */ 29084659b24SMichael Zeller #define HDA_CMD_VERB_GET_CONV_STREAM_CHAN 0xf06 29184659b24SMichael Zeller #define HDA_CMD_VERB_SET_CONV_STREAM_CHAN 0x706 29284659b24SMichael Zeller 29384659b24SMichael Zeller #define HDA_CMD_GET_CONV_STREAM_CHAN(cad, nid) \ 29484659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 29584659b24SMichael Zeller HDA_CMD_VERB_GET_CONV_STREAM_CHAN, 0x0)) 29684659b24SMichael Zeller #define HDA_CMD_SET_CONV_STREAM_CHAN(cad, nid, payload) \ 29784659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 29884659b24SMichael Zeller HDA_CMD_VERB_SET_CONV_STREAM_CHAN, (payload))) 29984659b24SMichael Zeller 30084659b24SMichael Zeller #define HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK 0x000000f0 30184659b24SMichael Zeller #define HDA_CMD_CONV_STREAM_CHAN_STREAM_SHIFT 4 30284659b24SMichael Zeller #define HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK 0x0000000f 30384659b24SMichael Zeller #define HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT 0 30484659b24SMichael Zeller 30584659b24SMichael Zeller #define HDA_CMD_GET_CONV_STREAM_CHAN_STREAM(rsp) \ 30684659b24SMichael Zeller (((rsp) & HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK) >> \ 30784659b24SMichael Zeller HDA_CMD_CONV_STREAM_CHAN_STREAM_SHIFT) 30884659b24SMichael Zeller #define HDA_CMD_GET_CONV_STREAM_CHAN_CHAN(rsp) \ 30984659b24SMichael Zeller (((rsp) & HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK) >> \ 31084659b24SMichael Zeller HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT) 31184659b24SMichael Zeller 31284659b24SMichael Zeller #define HDA_CMD_SET_CONV_STREAM_CHAN_STREAM(param) \ 31384659b24SMichael Zeller (((param) << HDA_CMD_CONV_STREAM_CHAN_STREAM_SHIFT) & \ 31484659b24SMichael Zeller HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK) 31584659b24SMichael Zeller #define HDA_CMD_SET_CONV_STREAM_CHAN_CHAN(param) \ 31684659b24SMichael Zeller (((param) << HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT) & \ 31784659b24SMichael Zeller HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK) 31884659b24SMichael Zeller 31984659b24SMichael Zeller /* Input Converter SDI Select */ 32084659b24SMichael Zeller #define HDA_CMD_VERB_GET_INPUT_CONVERTER_SDI_SELECT 0xf04 32184659b24SMichael Zeller #define HDA_CMD_VERB_SET_INPUT_CONVERTER_SDI_SELECT 0x704 32284659b24SMichael Zeller 32384659b24SMichael Zeller #define HDA_CMD_GET_INPUT_CONVERTER_SDI_SELECT(cad, nid) \ 32484659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 32584659b24SMichael Zeller HDA_CMD_VERB_GET_INPUT_CONVERTER_SDI_SELECT, 0x0)) 32684659b24SMichael Zeller #define HDA_CMD_SET_INPUT_CONVERTER_SDI_SELECT(cad, nid, payload) \ 32784659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 32884659b24SMichael Zeller HDA_CMD_VERB_SET_INPUT_CONVERTER_SDI_SELECT, (payload))) 32984659b24SMichael Zeller 33084659b24SMichael Zeller /* Pin Widget Control */ 33184659b24SMichael Zeller #define HDA_CMD_VERB_GET_PIN_WIDGET_CTRL 0xf07 33284659b24SMichael Zeller #define HDA_CMD_VERB_SET_PIN_WIDGET_CTRL 0x707 33384659b24SMichael Zeller 33484659b24SMichael Zeller #define HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid) \ 33584659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 33684659b24SMichael Zeller HDA_CMD_VERB_GET_PIN_WIDGET_CTRL, 0x0)) 33784659b24SMichael Zeller #define HDA_CMD_SET_PIN_WIDGET_CTRL(cad, nid, payload) \ 33884659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 33984659b24SMichael Zeller HDA_CMD_VERB_SET_PIN_WIDGET_CTRL, (payload))) 34084659b24SMichael Zeller 34184659b24SMichael Zeller #define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_MASK 0x00000080 34284659b24SMichael Zeller #define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_SHIFT 7 34384659b24SMichael Zeller #define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_MASK 0x00000040 34484659b24SMichael Zeller #define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_SHIFT 6 34584659b24SMichael Zeller #define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_MASK 0x00000020 34684659b24SMichael Zeller #define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_SHIFT 5 34784659b24SMichael Zeller #define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK 0x00000007 34884659b24SMichael Zeller #define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT 0 34984659b24SMichael Zeller 35084659b24SMichael Zeller #define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE(rsp) \ 35184659b24SMichael Zeller (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_MASK) >> \ 35284659b24SMichael Zeller HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_SHIFT) 35384659b24SMichael Zeller #define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE(rsp) \ 35484659b24SMichael Zeller (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_MASK) >> \ 35584659b24SMichael Zeller HDA_GET_CMD_PIN_WIDGET_CTRL_OUT_ENABLE_SHIFT) 35684659b24SMichael Zeller #define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE(rsp) \ 35784659b24SMichael Zeller (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_MASK) >> \ 35884659b24SMichael Zeller HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_SHIFT) 35984659b24SMichael Zeller #define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE(rsp) \ 36084659b24SMichael Zeller (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) >> \ 36184659b24SMichael Zeller HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT) 36284659b24SMichael Zeller 36384659b24SMichael Zeller #define HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE 0x80 36484659b24SMichael Zeller #define HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE 0x40 36584659b24SMichael Zeller #define HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE 0x20 36684659b24SMichael Zeller #define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK 0x07 36784659b24SMichael Zeller #define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT 0 36884659b24SMichael Zeller 36984659b24SMichael Zeller #define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(param) \ 37084659b24SMichael Zeller (((param) << HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT) & \ 37184659b24SMichael Zeller HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 37284659b24SMichael Zeller 37384659b24SMichael Zeller #define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_HIZ 0 37484659b24SMichael Zeller #define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 1 37584659b24SMichael Zeller #define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_GROUND 2 37684659b24SMichael Zeller #define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4 37784659b24SMichael Zeller #define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 5 37884659b24SMichael Zeller 37984659b24SMichael Zeller /* Unsolicited Response */ 38084659b24SMichael Zeller #define HDA_CMD_VERB_GET_UNSOLICITED_RESPONSE 0xf08 38184659b24SMichael Zeller #define HDA_CMD_VERB_SET_UNSOLICITED_RESPONSE 0x708 38284659b24SMichael Zeller 38384659b24SMichael Zeller #define HDA_CMD_GET_UNSOLICITED_RESPONSE(cad, nid) \ 38484659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 38584659b24SMichael Zeller HDA_CMD_VERB_GET_UNSOLICITED_RESPONSE, 0x0)) 38684659b24SMichael Zeller #define HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, nid, payload) \ 38784659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 38884659b24SMichael Zeller HDA_CMD_VERB_SET_UNSOLICITED_RESPONSE, (payload))) 38984659b24SMichael Zeller 39084659b24SMichael Zeller #define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_MASK 0x00000080 39184659b24SMichael Zeller #define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_SHIFT 7 39284659b24SMichael Zeller #define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_MASK 0x0000001f 39384659b24SMichael Zeller #define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_SHIFT 0 39484659b24SMichael Zeller 39584659b24SMichael Zeller #define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE(rsp) \ 39684659b24SMichael Zeller (((rsp) & HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_MASK) >> \ 39784659b24SMichael Zeller HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_SHIFT) 39884659b24SMichael Zeller #define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG(rsp) \ 39984659b24SMichael Zeller (((rsp) & HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_MASK) >> \ 40084659b24SMichael Zeller HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_SHIFT) 40184659b24SMichael Zeller 40284659b24SMichael Zeller #define HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE 0x80 40384659b24SMichael Zeller #define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_MASK 0x3f 40484659b24SMichael Zeller #define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_SHIFT 0 40584659b24SMichael Zeller 40684659b24SMichael Zeller #define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG(param) \ 40784659b24SMichael Zeller (((param) << HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_SHIFT) & \ 40884659b24SMichael Zeller HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_MASK) 40984659b24SMichael Zeller 41084659b24SMichael Zeller /* Pin Sense */ 41184659b24SMichael Zeller #define HDA_CMD_VERB_GET_PIN_SENSE 0xf09 41284659b24SMichael Zeller #define HDA_CMD_VERB_SET_PIN_SENSE 0x709 41384659b24SMichael Zeller 41484659b24SMichael Zeller #define HDA_CMD_GET_PIN_SENSE(cad, nid) \ 41584659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 41684659b24SMichael Zeller HDA_CMD_VERB_GET_PIN_SENSE, 0x0)) 41784659b24SMichael Zeller #define HDA_CMD_SET_PIN_SENSE(cad, nid, payload) \ 41884659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 41984659b24SMichael Zeller HDA_CMD_VERB_SET_PIN_SENSE, (payload))) 42084659b24SMichael Zeller 42184659b24SMichael Zeller #define HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT 0x80000000 42284659b24SMichael Zeller #define HDA_CMD_GET_PIN_SENSE_ELD_VALID 0x40000000 42384659b24SMichael Zeller #define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_MASK 0x7fffffff 42484659b24SMichael Zeller #define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_SHIFT 0 42584659b24SMichael Zeller 42684659b24SMichael Zeller #define HDA_CMD_GET_PIN_SENSE_IMP_SENSE(rsp) \ 42784659b24SMichael Zeller (((rsp) & HDA_CMD_GET_PIN_SENSE_IMP_SENSE_MASK) >> \ 42884659b24SMichael Zeller HDA_CMD_GET_PIN_SENSE_IMP_SENSE_SHIFT) 42984659b24SMichael Zeller 43084659b24SMichael Zeller #define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_INVALID 0x7fffffff 43184659b24SMichael Zeller 43284659b24SMichael Zeller #define HDA_CMD_SET_PIN_SENSE_LEFT_CHANNEL 0x00 43384659b24SMichael Zeller #define HDA_CMD_SET_PIN_SENSE_RIGHT_CHANNEL 0x01 43484659b24SMichael Zeller 43584659b24SMichael Zeller /* EAPD/BTL Enable */ 43684659b24SMichael Zeller #define HDA_CMD_VERB_GET_EAPD_BTL_ENABLE 0xf0c 43784659b24SMichael Zeller #define HDA_CMD_VERB_SET_EAPD_BTL_ENABLE 0x70c 43884659b24SMichael Zeller 43984659b24SMichael Zeller #define HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid) \ 44084659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 44184659b24SMichael Zeller HDA_CMD_VERB_GET_EAPD_BTL_ENABLE, 0x0)) 44284659b24SMichael Zeller #define HDA_CMD_SET_EAPD_BTL_ENABLE(cad, nid, payload) \ 44384659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 44484659b24SMichael Zeller HDA_CMD_VERB_SET_EAPD_BTL_ENABLE, (payload))) 44584659b24SMichael Zeller 44684659b24SMichael Zeller #define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_MASK 0x00000004 44784659b24SMichael Zeller #define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_SHIFT 2 44884659b24SMichael Zeller #define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_MASK 0x00000002 44984659b24SMichael Zeller #define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_SHIFT 1 45084659b24SMichael Zeller #define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_MASK 0x00000001 45184659b24SMichael Zeller #define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_SHIFT 0 45284659b24SMichael Zeller 45384659b24SMichael Zeller #define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP(rsp) \ 45484659b24SMichael Zeller (((rsp) & HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_MASK) >> \ 45584659b24SMichael Zeller HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_SHIFT) 45684659b24SMichael Zeller #define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD(rsp) \ 45784659b24SMichael Zeller (((rsp) & HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_MASK) >> \ 45884659b24SMichael Zeller HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_SHIFT) 45984659b24SMichael Zeller #define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL(rsp) \ 46084659b24SMichael Zeller (((rsp) & HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_MASK) >> \ 46184659b24SMichael Zeller HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_SHIFT) 46284659b24SMichael Zeller 46384659b24SMichael Zeller #define HDA_CMD_SET_EAPD_BTL_ENABLE_LR_SWAP 0x04 46484659b24SMichael Zeller #define HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD 0x02 46584659b24SMichael Zeller #define HDA_CMD_SET_EAPD_BTL_ENABLE_BTL 0x01 46684659b24SMichael Zeller 46784659b24SMichael Zeller /* GPI Data */ 46884659b24SMichael Zeller #define HDA_CMD_VERB_GET_GPI_DATA 0xf10 46984659b24SMichael Zeller #define HDA_CMD_VERB_SET_GPI_DATA 0x710 47084659b24SMichael Zeller 47184659b24SMichael Zeller #define HDA_CMD_GET_GPI_DATA(cad, nid) \ 47284659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 47384659b24SMichael Zeller HDA_CMD_VERB_GET_GPI_DATA, 0x0)) 47484659b24SMichael Zeller #define HDA_CMD_SET_GPI_DATA(cad, nid) \ 47584659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 47684659b24SMichael Zeller HDA_CMD_VERB_SET_GPI_DATA, (payload))) 47784659b24SMichael Zeller 47884659b24SMichael Zeller /* GPI Wake Enable Mask */ 47984659b24SMichael Zeller #define HDA_CMD_VERB_GET_GPI_WAKE_ENABLE_MASK 0xf11 48084659b24SMichael Zeller #define HDA_CMD_VERB_SET_GPI_WAKE_ENABLE_MASK 0x711 48184659b24SMichael Zeller 48284659b24SMichael Zeller #define HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, nid) \ 48384659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 48484659b24SMichael Zeller HDA_CMD_VERB_GET_GPI_WAKE_ENABLE_MASK, 0x0)) 48584659b24SMichael Zeller #define HDA_CMD_SET_GPI_WAKE_ENABLE_MASK(cad, nid, payload) \ 48684659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 48784659b24SMichael Zeller HDA_CMD_VERB_SET_GPI_WAKE_ENABLE_MASK, (payload))) 48884659b24SMichael Zeller 48984659b24SMichael Zeller /* GPI Unsolicited Enable Mask */ 49084659b24SMichael Zeller #define HDA_CMD_VERB_GET_GPI_UNSOLICITED_ENABLE_MASK 0xf12 49184659b24SMichael Zeller #define HDA_CMD_VERB_SET_GPI_UNSOLICITED_ENABLE_MASK 0x712 49284659b24SMichael Zeller 49384659b24SMichael Zeller #define HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, nid) \ 49484659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 49584659b24SMichael Zeller HDA_CMD_VERB_GET_GPI_UNSOLICITED_ENABLE_MASK, 0x0)) 49684659b24SMichael Zeller #define HDA_CMD_SET_GPI_UNSOLICITED_ENABLE_MASK(cad, nid, payload) \ 49784659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 49884659b24SMichael Zeller HDA_CMD_VERB_SET_GPI_UNSOLICITED_ENABLE_MASK, (payload))) 49984659b24SMichael Zeller 50084659b24SMichael Zeller /* GPI Sticky Mask */ 50184659b24SMichael Zeller #define HDA_CMD_VERB_GET_GPI_STICKY_MASK 0xf13 50284659b24SMichael Zeller #define HDA_CMD_VERB_SET_GPI_STICKY_MASK 0x713 50384659b24SMichael Zeller 50484659b24SMichael Zeller #define HDA_CMD_GET_GPI_STICKY_MASK(cad, nid) \ 50584659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 50684659b24SMichael Zeller HDA_CMD_VERB_GET_GPI_STICKY_MASK, 0x0)) 50784659b24SMichael Zeller #define HDA_CMD_SET_GPI_STICKY_MASK(cad, nid, payload) \ 50884659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 50984659b24SMichael Zeller HDA_CMD_VERB_SET_GPI_STICKY_MASK, (payload))) 51084659b24SMichael Zeller 51184659b24SMichael Zeller /* GPO Data */ 51284659b24SMichael Zeller #define HDA_CMD_VERB_GET_GPO_DATA 0xf14 51384659b24SMichael Zeller #define HDA_CMD_VERB_SET_GPO_DATA 0x714 51484659b24SMichael Zeller 51584659b24SMichael Zeller #define HDA_CMD_GET_GPO_DATA(cad, nid) \ 51684659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 51784659b24SMichael Zeller HDA_CMD_VERB_GET_GPO_DATA, 0x0)) 51884659b24SMichael Zeller #define HDA_CMD_SET_GPO_DATA(cad, nid, payload) \ 51984659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 52084659b24SMichael Zeller HDA_CMD_VERB_SET_GPO_DATA, (payload))) 52184659b24SMichael Zeller 52284659b24SMichael Zeller /* GPIO Data */ 52384659b24SMichael Zeller #define HDA_CMD_VERB_GET_GPIO_DATA 0xf15 52484659b24SMichael Zeller #define HDA_CMD_VERB_SET_GPIO_DATA 0x715 52584659b24SMichael Zeller 52684659b24SMichael Zeller #define HDA_CMD_GET_GPIO_DATA(cad, nid) \ 52784659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 52884659b24SMichael Zeller HDA_CMD_VERB_GET_GPIO_DATA, 0x0)) 52984659b24SMichael Zeller #define HDA_CMD_SET_GPIO_DATA(cad, nid, payload) \ 53084659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 53184659b24SMichael Zeller HDA_CMD_VERB_SET_GPIO_DATA, (payload))) 53284659b24SMichael Zeller 53384659b24SMichael Zeller /* GPIO Enable Mask */ 53484659b24SMichael Zeller #define HDA_CMD_VERB_GET_GPIO_ENABLE_MASK 0xf16 53584659b24SMichael Zeller #define HDA_CMD_VERB_SET_GPIO_ENABLE_MASK 0x716 53684659b24SMichael Zeller 53784659b24SMichael Zeller #define HDA_CMD_GET_GPIO_ENABLE_MASK(cad, nid) \ 53884659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 53984659b24SMichael Zeller HDA_CMD_VERB_GET_GPIO_ENABLE_MASK, 0x0)) 54084659b24SMichael Zeller #define HDA_CMD_SET_GPIO_ENABLE_MASK(cad, nid, payload) \ 54184659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 54284659b24SMichael Zeller HDA_CMD_VERB_SET_GPIO_ENABLE_MASK, (payload))) 54384659b24SMichael Zeller 54484659b24SMichael Zeller /* GPIO Direction */ 54584659b24SMichael Zeller #define HDA_CMD_VERB_GET_GPIO_DIRECTION 0xf17 54684659b24SMichael Zeller #define HDA_CMD_VERB_SET_GPIO_DIRECTION 0x717 54784659b24SMichael Zeller 54884659b24SMichael Zeller #define HDA_CMD_GET_GPIO_DIRECTION(cad, nid) \ 54984659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 55084659b24SMichael Zeller HDA_CMD_VERB_GET_GPIO_DIRECTION, 0x0)) 55184659b24SMichael Zeller #define HDA_CMD_SET_GPIO_DIRECTION(cad, nid, payload) \ 55284659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 55384659b24SMichael Zeller HDA_CMD_VERB_SET_GPIO_DIRECTION, (payload))) 55484659b24SMichael Zeller 55584659b24SMichael Zeller /* GPIO Wake Enable Mask */ 55684659b24SMichael Zeller #define HDA_CMD_VERB_GET_GPIO_WAKE_ENABLE_MASK 0xf18 55784659b24SMichael Zeller #define HDA_CMD_VERB_SET_GPIO_WAKE_ENABLE_MASK 0x718 55884659b24SMichael Zeller 55984659b24SMichael Zeller #define HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, nid) \ 56084659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 56184659b24SMichael Zeller HDA_CMD_VERB_GET_GPIO_WAKE_ENABLE_MASK, 0x0)) 56284659b24SMichael Zeller #define HDA_CMD_SET_GPIO_WAKE_ENABLE_MASK(cad, nid, payload) \ 56384659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 56484659b24SMichael Zeller HDA_CMD_VERB_SET_GPIO_WAKE_ENABLE_MASK, (payload))) 56584659b24SMichael Zeller 56684659b24SMichael Zeller /* GPIO Unsolicited Enable Mask */ 56784659b24SMichael Zeller #define HDA_CMD_VERB_GET_GPIO_UNSOLICITED_ENABLE_MASK 0xf19 56884659b24SMichael Zeller #define HDA_CMD_VERB_SET_GPIO_UNSOLICITED_ENABLE_MASK 0x719 56984659b24SMichael Zeller 57084659b24SMichael Zeller #define HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, nid) \ 57184659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 57284659b24SMichael Zeller HDA_CMD_VERB_GET_GPIO_UNSOLICITED_ENABLE_MASK, 0x0)) 57384659b24SMichael Zeller #define HDA_CMD_SET_GPIO_UNSOLICITED_ENABLE_MASK(cad, nid, payload) \ 57484659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 57584659b24SMichael Zeller HDA_CMD_VERB_SET_GPIO_UNSOLICITED_ENABLE_MASK, (payload))) 57684659b24SMichael Zeller 57784659b24SMichael Zeller /* GPIO_STICKY_MASK */ 57884659b24SMichael Zeller #define HDA_CMD_VERB_GET_GPIO_STICKY_MASK 0xf1a 57984659b24SMichael Zeller #define HDA_CMD_VERB_SET_GPIO_STICKY_MASK 0x71a 58084659b24SMichael Zeller 58184659b24SMichael Zeller #define HDA_CMD_GET_GPIO_STICKY_MASK(cad, nid) \ 58284659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 58384659b24SMichael Zeller HDA_CMD_VERB_GET_GPIO_STICKY_MASK, 0x0)) 58484659b24SMichael Zeller #define HDA_CMD_SET_GPIO_STICKY_MASK(cad, nid, payload) \ 58584659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 58684659b24SMichael Zeller HDA_CMD_VERB_SET_GPIO_STICKY_MASK, (payload))) 58784659b24SMichael Zeller 58884659b24SMichael Zeller /* Beep Generation */ 58984659b24SMichael Zeller #define HDA_CMD_VERB_GET_BEEP_GENERATION 0xf0a 59084659b24SMichael Zeller #define HDA_CMD_VERB_SET_BEEP_GENERATION 0x70a 59184659b24SMichael Zeller 59284659b24SMichael Zeller #define HDA_CMD_GET_BEEP_GENERATION(cad, nid) \ 59384659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 59484659b24SMichael Zeller HDA_CMD_VERB_GET_BEEP_GENERATION, 0x0)) 59584659b24SMichael Zeller #define HDA_CMD_SET_BEEP_GENERATION(cad, nid, payload) \ 59684659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 59784659b24SMichael Zeller HDA_CMD_VERB_SET_BEEP_GENERATION, (payload))) 59884659b24SMichael Zeller 59984659b24SMichael Zeller /* Volume Knob */ 60084659b24SMichael Zeller #define HDA_CMD_VERB_GET_VOLUME_KNOB 0xf0f 60184659b24SMichael Zeller #define HDA_CMD_VERB_SET_VOLUME_KNOB 0x70f 60284659b24SMichael Zeller 60384659b24SMichael Zeller #define HDA_CMD_GET_VOLUME_KNOB(cad, nid) \ 60484659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 60584659b24SMichael Zeller HDA_CMD_VERB_GET_VOLUME_KNOB, 0x0)) 60684659b24SMichael Zeller #define HDA_CMD_SET_VOLUME_KNOB(cad, nid, payload) \ 60784659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 60884659b24SMichael Zeller HDA_CMD_VERB_SET_VOLUME_KNOB, (payload))) 60984659b24SMichael Zeller 61084659b24SMichael Zeller /* Subsystem ID */ 61184659b24SMichael Zeller #define HDA_CMD_VERB_GET_SUBSYSTEM_ID 0xf20 61284659b24SMichael Zeller #define HDA_CMD_VERB_SET_SUSBYSTEM_ID1 0x720 61384659b24SMichael Zeller #define HDA_CMD_VERB_SET_SUBSYSTEM_ID2 0x721 61484659b24SMichael Zeller #define HDA_CMD_VERB_SET_SUBSYSTEM_ID3 0x722 61584659b24SMichael Zeller #define HDA_CMD_VERB_SET_SUBSYSTEM_ID4 0x723 61684659b24SMichael Zeller 61784659b24SMichael Zeller #define HDA_CMD_GET_SUBSYSTEM_ID(cad, nid) \ 61884659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 61984659b24SMichael Zeller HDA_CMD_VERB_GET_SUBSYSTEM_ID, 0x0)) 62084659b24SMichael Zeller #define HDA_CMD_SET_SUBSYSTEM_ID1(cad, nid, payload) \ 62184659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 62284659b24SMichael Zeller HDA_CMD_VERB_SET_SUSBYSTEM_ID1, (payload))) 62384659b24SMichael Zeller #define HDA_CMD_SET_SUBSYSTEM_ID2(cad, nid, payload) \ 62484659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 62584659b24SMichael Zeller HDA_CMD_VERB_SET_SUSBYSTEM_ID2, (payload))) 62684659b24SMichael Zeller #define HDA_CMD_SET_SUBSYSTEM_ID3(cad, nid, payload) \ 62784659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 62884659b24SMichael Zeller HDA_CMD_VERB_SET_SUSBYSTEM_ID3, (payload))) 62984659b24SMichael Zeller #define HDA_CMD_SET_SUBSYSTEM_ID4(cad, nid, payload) \ 63084659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 63184659b24SMichael Zeller HDA_CMD_VERB_SET_SUSBYSTEM_ID4, (payload))) 63284659b24SMichael Zeller 63384659b24SMichael Zeller /* Configuration Default */ 63484659b24SMichael Zeller #define HDA_CMD_VERB_GET_CONFIGURATION_DEFAULT 0xf1c 63584659b24SMichael Zeller #define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT1 0x71c 63684659b24SMichael Zeller #define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT2 0x71d 63784659b24SMichael Zeller #define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT3 0x71e 63884659b24SMichael Zeller #define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT4 0x71f 63984659b24SMichael Zeller 64084659b24SMichael Zeller #define HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid) \ 64184659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 64284659b24SMichael Zeller HDA_CMD_VERB_GET_CONFIGURATION_DEFAULT, 0x0)) 64384659b24SMichael Zeller #define HDA_CMD_SET_CONFIGURATION_DEFAULT1(cad, nid, payload) \ 64484659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 64584659b24SMichael Zeller HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT1, (payload))) 64684659b24SMichael Zeller #define HDA_CMD_SET_CONFIGURATION_DEFAULT2(cad, nid, payload) \ 64784659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 64884659b24SMichael Zeller HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT2, (payload))) 64984659b24SMichael Zeller #define HDA_CMD_SET_CONFIGURATION_DEFAULT3(cad, nid, payload) \ 65084659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 65184659b24SMichael Zeller HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT3, (payload))) 65284659b24SMichael Zeller #define HDA_CMD_SET_CONFIGURATION_DEFAULT4(cad, nid, payload) \ 65384659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 65484659b24SMichael Zeller HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT4, (payload))) 65584659b24SMichael Zeller 65684659b24SMichael Zeller /* Stripe Control */ 65784659b24SMichael Zeller #define HDA_CMD_VERB_GET_STRIPE_CONTROL 0xf24 65884659b24SMichael Zeller #define HDA_CMD_VERB_SET_STRIPE_CONTROL 0x724 65984659b24SMichael Zeller 66084659b24SMichael Zeller #define HDA_CMD_GET_STRIPE_CONTROL(cad, nid) \ 66184659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 66284659b24SMichael Zeller HDA_CMD_VERB_GET_STRIPE_CONTROL, 0x0)) 66384659b24SMichael Zeller #define HDA_CMD_SET_STRIPE_CONTROL(cad, nid, payload) \ 66484659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 66584659b24SMichael Zeller HDA_CMD_VERB_SET_STRIPE_CONTROL, (payload))) 66684659b24SMichael Zeller 66784659b24SMichael Zeller /* Channel Count Control */ 66884659b24SMichael Zeller #define HDA_CMD_VERB_GET_CONV_CHAN_COUNT 0xf2d 6696dc98349SAndy Fiddaman #define HDA_CMD_VERB_SET_CONV_CHAN_COUNT 0x72d 67084659b24SMichael Zeller 67184659b24SMichael Zeller #define HDA_CMD_GET_CONV_CHAN_COUNT(cad, nid) \ 67284659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 67384659b24SMichael Zeller HDA_CMD_VERB_GET_CONV_CHAN_COUNT, 0x0)) 67484659b24SMichael Zeller #define HDA_CMD_SET_CONV_CHAN_COUNT(cad, nid, payload) \ 67584659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 67684659b24SMichael Zeller HDA_CMD_VERB_SET_CONV_CHAN_COUNT, (payload))) 67784659b24SMichael Zeller 6786dc98349SAndy Fiddaman #define HDA_CMD_VERB_GET_HDMI_DIP_SIZE 0xf2e 67984659b24SMichael Zeller 68084659b24SMichael Zeller #define HDA_CMD_GET_HDMI_DIP_SIZE(cad, nid, arg) \ 68184659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 68284659b24SMichael Zeller HDA_CMD_VERB_GET_HDMI_DIP_SIZE, (arg))) 68384659b24SMichael Zeller 6846dc98349SAndy Fiddaman #define HDA_CMD_VERB_GET_HDMI_ELDD 0xf2f 68584659b24SMichael Zeller 68684659b24SMichael Zeller #define HDA_CMD_GET_HDMI_ELDD(cad, nid, off) \ 68784659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 68884659b24SMichael Zeller HDA_CMD_VERB_GET_HDMI_ELDD, (off))) 68984659b24SMichael Zeller 6906dc98349SAndy Fiddaman #define HDA_CMD_VERB_GET_HDMI_DIP_INDEX 0xf30 6916dc98349SAndy Fiddaman #define HDA_CMD_VERB_SET_HDMI_DIP_INDEX 0x730 69284659b24SMichael Zeller 69384659b24SMichael Zeller #define HDA_CMD_GET_HDMI_DIP_INDEX(cad, nid) \ 69484659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 69584659b24SMichael Zeller HDA_CMD_VERB_GET_HDMI_DIP_INDEX, 0x0)) 69684659b24SMichael Zeller #define HDA_CMD_SET_HDMI_DIP_INDEX(cad, nid, payload) \ 69784659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 69884659b24SMichael Zeller HDA_CMD_VERB_SET_HDMI_DIP_INDEX, (payload))) 69984659b24SMichael Zeller 7006dc98349SAndy Fiddaman #define HDA_CMD_VERB_GET_HDMI_DIP_DATA 0xf31 7016dc98349SAndy Fiddaman #define HDA_CMD_VERB_SET_HDMI_DIP_DATA 0x731 70284659b24SMichael Zeller 70384659b24SMichael Zeller #define HDA_CMD_GET_HDMI_DIP_DATA(cad, nid) \ 70484659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 70584659b24SMichael Zeller HDA_CMD_VERB_GET_HDMI_DIP_DATA, 0x0)) 70684659b24SMichael Zeller #define HDA_CMD_SET_HDMI_DIP_DATA(cad, nid, payload) \ 70784659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 70884659b24SMichael Zeller HDA_CMD_VERB_SET_HDMI_DIP_DATA, (payload))) 70984659b24SMichael Zeller 7106dc98349SAndy Fiddaman #define HDA_CMD_VERB_GET_HDMI_DIP_XMIT 0xf32 7116dc98349SAndy Fiddaman #define HDA_CMD_VERB_SET_HDMI_DIP_XMIT 0x732 71284659b24SMichael Zeller 71384659b24SMichael Zeller #define HDA_CMD_GET_HDMI_DIP_XMIT(cad, nid) \ 71484659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 71584659b24SMichael Zeller HDA_CMD_VERB_GET_HDMI_DIP_XMIT, 0x0)) 71684659b24SMichael Zeller #define HDA_CMD_SET_HDMI_DIP_XMIT(cad, nid, payload) \ 71784659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 71884659b24SMichael Zeller HDA_CMD_VERB_SET_HDMI_DIP_XMIT, (payload))) 71984659b24SMichael Zeller 7206dc98349SAndy Fiddaman #define HDA_CMD_VERB_GET_HDMI_CP_CTRL 0xf33 7216dc98349SAndy Fiddaman #define HDA_CMD_VERB_SET_HDMI_CP_CTRL 0x733 72284659b24SMichael Zeller 7236dc98349SAndy Fiddaman #define HDA_CMD_VERB_GET_HDMI_CHAN_SLOT 0xf34 7246dc98349SAndy Fiddaman #define HDA_CMD_VERB_SET_HDMI_CHAN_SLOT 0x734 72584659b24SMichael Zeller 72684659b24SMichael Zeller #define HDA_CMD_GET_HDMI_CHAN_SLOT(cad, nid) \ 72784659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 72884659b24SMichael Zeller HDA_CMD_VERB_GET_HDMI_CHAN_SLOT, 0x0)) 72984659b24SMichael Zeller #define HDA_CMD_SET_HDMI_CHAN_SLOT(cad, nid, payload) \ 73084659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 73184659b24SMichael Zeller HDA_CMD_VERB_SET_HDMI_CHAN_SLOT, (payload))) 73284659b24SMichael Zeller 73384659b24SMichael Zeller #define HDA_HDMI_CODING_TYPE_REF_STREAM_HEADER 0 73484659b24SMichael Zeller #define HDA_HDMI_CODING_TYPE_LPCM 1 73584659b24SMichael Zeller #define HDA_HDMI_CODING_TYPE_AC3 2 73684659b24SMichael Zeller #define HDA_HDMI_CODING_TYPE_MPEG1 3 73784659b24SMichael Zeller #define HDA_HDMI_CODING_TYPE_MP3 4 73884659b24SMichael Zeller #define HDA_HDMI_CODING_TYPE_MPEG2 5 73984659b24SMichael Zeller #define HDA_HDMI_CODING_TYPE_AACLC 6 74084659b24SMichael Zeller #define HDA_HDMI_CODING_TYPE_DTS 7 74184659b24SMichael Zeller #define HDA_HDMI_CODING_TYPE_ATRAC 8 74284659b24SMichael Zeller #define HDA_HDMI_CODING_TYPE_SACD 9 74384659b24SMichael Zeller #define HDA_HDMI_CODING_TYPE_EAC3 10 74484659b24SMichael Zeller #define HDA_HDMI_CODING_TYPE_DTS_HD 11 74584659b24SMichael Zeller #define HDA_HDMI_CODING_TYPE_MLP 12 74684659b24SMichael Zeller #define HDA_HDMI_CODING_TYPE_DST 13 74784659b24SMichael Zeller #define HDA_HDMI_CODING_TYPE_WMAPRO 14 74884659b24SMichael Zeller #define HDA_HDMI_CODING_TYPE_REF_CTX 15 74984659b24SMichael Zeller 75084659b24SMichael Zeller /* Function Reset */ 75184659b24SMichael Zeller #define HDA_CMD_VERB_FUNCTION_RESET 0x7ff 75284659b24SMichael Zeller 75384659b24SMichael Zeller #define HDA_CMD_FUNCTION_RESET(cad, nid) \ 75484659b24SMichael Zeller (HDA_CMD_12BIT((cad), (nid), \ 75584659b24SMichael Zeller HDA_CMD_VERB_FUNCTION_RESET, 0x0)) 75684659b24SMichael Zeller 75784659b24SMichael Zeller 75884659b24SMichael Zeller /**************************************************************************** 75984659b24SMichael Zeller * HDA Device Parameters 76084659b24SMichael Zeller ****************************************************************************/ 76184659b24SMichael Zeller 76284659b24SMichael Zeller /* Vendor ID */ 76384659b24SMichael Zeller #define HDA_PARAM_VENDOR_ID 0x00 76484659b24SMichael Zeller 76584659b24SMichael Zeller #define HDA_PARAM_VENDOR_ID_VENDOR_ID_MASK 0xffff0000 76684659b24SMichael Zeller #define HDA_PARAM_VENDOR_ID_VENDOR_ID_SHIFT 16 76784659b24SMichael Zeller #define HDA_PARAM_VENDOR_ID_DEVICE_ID_MASK 0x0000ffff 76884659b24SMichael Zeller #define HDA_PARAM_VENDOR_ID_DEVICE_ID_SHIFT 0 76984659b24SMichael Zeller 77084659b24SMichael Zeller #define HDA_PARAM_VENDOR_ID_VENDOR_ID(param) \ 77184659b24SMichael Zeller (((param) & HDA_PARAM_VENDOR_ID_VENDOR_ID_MASK) >> \ 77284659b24SMichael Zeller HDA_PARAM_VENDOR_ID_VENDOR_ID_SHIFT) 77384659b24SMichael Zeller #define HDA_PARAM_VENDOR_ID_DEVICE_ID(param) \ 77484659b24SMichael Zeller (((param) & HDA_PARAM_VENDOR_ID_DEVICE_ID_MASK) >> \ 77584659b24SMichael Zeller HDA_PARAM_VENDOR_ID_DEVICE_ID_SHIFT) 77684659b24SMichael Zeller 77784659b24SMichael Zeller /* Revision ID */ 77884659b24SMichael Zeller #define HDA_PARAM_REVISION_ID 0x02 77984659b24SMichael Zeller 78084659b24SMichael Zeller #define HDA_PARAM_REVISION_ID_MAJREV_MASK 0x00f00000 78184659b24SMichael Zeller #define HDA_PARAM_REVISION_ID_MAJREV_SHIFT 20 78284659b24SMichael Zeller #define HDA_PARAM_REVISION_ID_MINREV_MASK 0x000f0000 78384659b24SMichael Zeller #define HDA_PARAM_REVISION_ID_MINREV_SHIFT 16 78484659b24SMichael Zeller #define HDA_PARAM_REVISION_ID_REVISION_ID_MASK 0x0000ff00 78584659b24SMichael Zeller #define HDA_PARAM_REVISION_ID_REVISION_ID_SHIFT 8 78684659b24SMichael Zeller #define HDA_PARAM_REVISION_ID_STEPPING_ID_MASK 0x000000ff 78784659b24SMichael Zeller #define HDA_PARAM_REVISION_ID_STEPPING_ID_SHIFT 0 78884659b24SMichael Zeller 78984659b24SMichael Zeller #define HDA_PARAM_REVISION_ID_MAJREV(param) \ 79084659b24SMichael Zeller (((param) & HDA_PARAM_REVISION_ID_MAJREV_MASK) >> \ 79184659b24SMichael Zeller HDA_PARAM_REVISION_ID_MAJREV_SHIFT) 79284659b24SMichael Zeller #define HDA_PARAM_REVISION_ID_MINREV(param) \ 79384659b24SMichael Zeller (((param) & HDA_PARAM_REVISION_ID_MINREV_MASK) >> \ 79484659b24SMichael Zeller HDA_PARAM_REVISION_ID_MINREV_SHIFT) 79584659b24SMichael Zeller #define HDA_PARAM_REVISION_ID_REVISION_ID(param) \ 79684659b24SMichael Zeller (((param) & HDA_PARAM_REVISION_ID_REVISION_ID_MASK) >> \ 79784659b24SMichael Zeller HDA_PARAM_REVISION_ID_REVISION_ID_SHIFT) 79884659b24SMichael Zeller #define HDA_PARAM_REVISION_ID_STEPPING_ID(param) \ 79984659b24SMichael Zeller (((param) & HDA_PARAM_REVISION_ID_STEPPING_ID_MASK) >> \ 80084659b24SMichael Zeller HDA_PARAM_REVISION_ID_STEPPING_ID_SHIFT) 80184659b24SMichael Zeller 80284659b24SMichael Zeller /* Subordinate Node Cound */ 80384659b24SMichael Zeller #define HDA_PARAM_SUB_NODE_COUNT 0x04 80484659b24SMichael Zeller 80584659b24SMichael Zeller #define HDA_PARAM_SUB_NODE_COUNT_START_MASK 0x00ff0000 80684659b24SMichael Zeller #define HDA_PARAM_SUB_NODE_COUNT_START_SHIFT 16 80784659b24SMichael Zeller #define HDA_PARAM_SUB_NODE_COUNT_TOTAL_MASK 0x000000ff 80884659b24SMichael Zeller #define HDA_PARAM_SUB_NODE_COUNT_TOTAL_SHIFT 0 80984659b24SMichael Zeller 81084659b24SMichael Zeller #define HDA_PARAM_SUB_NODE_COUNT_START(param) \ 81184659b24SMichael Zeller (((param) & HDA_PARAM_SUB_NODE_COUNT_START_MASK) >> \ 81284659b24SMichael Zeller HDA_PARAM_SUB_NODE_COUNT_START_SHIFT) 81384659b24SMichael Zeller #define HDA_PARAM_SUB_NODE_COUNT_TOTAL(param) \ 81484659b24SMichael Zeller (((param) & HDA_PARAM_SUB_NODE_COUNT_TOTAL_MASK) >> \ 81584659b24SMichael Zeller HDA_PARAM_SUB_NODE_COUNT_TOTAL_SHIFT) 81684659b24SMichael Zeller 81784659b24SMichael Zeller /* Function Group Type */ 81884659b24SMichael Zeller #define HDA_PARAM_FCT_GRP_TYPE 0x05 81984659b24SMichael Zeller 82084659b24SMichael Zeller #define HDA_PARAM_FCT_GRP_TYPE_UNSOL_MASK 0x00000100 82184659b24SMichael Zeller #define HDA_PARAM_FCT_GRP_TYPE_UNSOL_SHIFT 8 82284659b24SMichael Zeller #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MASK 0x000000ff 82384659b24SMichael Zeller #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_SHIFT 0 82484659b24SMichael Zeller 82584659b24SMichael Zeller #define HDA_PARAM_FCT_GRP_TYPE_UNSOL(param) \ 82684659b24SMichael Zeller (((param) & HDA_PARAM_FCT_GRP_TYPE_UNSOL_MASK) >> \ 82784659b24SMichael Zeller HDA_PARAM_FCT_GROUP_TYPE_UNSOL_SHIFT) 82884659b24SMichael Zeller #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(param) \ 82984659b24SMichael Zeller (((param) & HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MASK) >> \ 83084659b24SMichael Zeller HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_SHIFT) 83184659b24SMichael Zeller 83284659b24SMichael Zeller #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO 0x01 83384659b24SMichael Zeller #define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM 0x02 83484659b24SMichael Zeller 83584659b24SMichael Zeller /* Audio Function Group Capabilities */ 83684659b24SMichael Zeller #define HDA_PARAM_AUDIO_FCT_GRP_CAP 0x08 83784659b24SMichael Zeller 83884659b24SMichael Zeller #define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_MASK 0x00010000 83984659b24SMichael Zeller #define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_SHIFT 16 84084659b24SMichael Zeller #define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_MASK 0x00000f00 84184659b24SMichael Zeller #define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_SHIFT 8 84284659b24SMichael Zeller #define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_MASK 0x0000000f 84384659b24SMichael Zeller #define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_SHIFT 0 84484659b24SMichael Zeller 84584659b24SMichael Zeller #define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN(param) \ 84684659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_MASK) >> \ 84784659b24SMichael Zeller HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_SHIFT) 84884659b24SMichael Zeller #define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY(param) \ 84984659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_MASK) >> \ 85084659b24SMichael Zeller HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_SHIFT) 85184659b24SMichael Zeller #define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY(param) \ 85284659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_MASK) >> \ 85384659b24SMichael Zeller HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_SHIFT) 85484659b24SMichael Zeller 85584659b24SMichael Zeller /* Audio Widget Capabilities */ 85684659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP 0x09 85784659b24SMichael Zeller 85884659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK 0x00f00000 85984659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT 20 86084659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_MASK 0x000f0000 86184659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_SHIFT 16 86284659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_MASK 0x0000e000 86384659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_SHIFT 13 86484659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_CP_MASK 0x00001000 86584659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_CP_SHIFT 12 86684659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_MASK 0x00000800 86784659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_SHIFT 11 86884659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_MASK 0x00000400 86984659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_SHIFT 10 87084659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_MASK 0x00000200 87184659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_SHIFT 9 87284659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_MASK 0x00000100 87384659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_SHIFT 8 87484659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_MASK 0x00000080 87584659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_SHIFT 7 87684659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_MASK 0x00000040 87784659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_SHIFT 6 87884659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_MASK 0x00000020 87984659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_SHIFT 5 88084659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_MASK 0x00000010 88184659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_SHIFT 4 88284659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_MASK 0x00000008 88384659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_SHIFT 3 88484659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_MASK 0x00000004 88584659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_SHIFT 2 88684659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_MASK 0x00000002 88784659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_SHIFT 1 88884659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_MASK 0x00000001 88984659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT 0 89084659b24SMichael Zeller 89184659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(param) \ 89284659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK) >> \ 89384659b24SMichael Zeller HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT) 89484659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY(param) \ 89584659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_MASK) >> \ 89684659b24SMichael Zeller HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_SHIFT) 89784659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_CC(param) \ 89884659b24SMichael Zeller ((((param) & HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_MASK) >> \ 89984659b24SMichael Zeller (HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_SHIFT - 1)) | \ 90084659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_MASK) >> \ 90184659b24SMichael Zeller HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT)) 90284659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_CP(param) \ 90384659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_CP_MASK) >> \ 90484659b24SMichael Zeller HDA_PARAM_AUDIO_WIDGET_CAP_CP_SHIFT) 90584659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(param) \ 90684659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_MASK) >> \ 90784659b24SMichael Zeller HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_SHIFT) 90884659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(param) \ 90984659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_MASK) >> \ 91084659b24SMichael Zeller HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_SHIFT) 91184659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(param) \ 91284659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_MASK) >> \ 91384659b24SMichael Zeller HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_SHIFT) 91484659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST(param) \ 91584659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_MASK) >> \ 91684659b24SMichael Zeller HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_SHIFT) 91784659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(param) \ 91884659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_MASK) >> \ 91984659b24SMichael Zeller HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_SHIFT) 92084659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(param) \ 92184659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_MASK) >> \ 92284659b24SMichael Zeller HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_SHIFT) 92384659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(param) \ 92484659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_MASK) >> \ 92584659b24SMichael Zeller HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_SHIFT) 92684659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(param) \ 92784659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_MASK) >> \ 92884659b24SMichael Zeller HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_SHIFT) 92984659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(param) \ 93084659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_MASK) >> \ 93184659b24SMichael Zeller HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_SHIFT) 93284659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(param) \ 93384659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_MASK) >> \ 93484659b24SMichael Zeller HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_SHIFT) 93584659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(param) \ 93684659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_MASK) >> \ 93784659b24SMichael Zeller HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_SHIFT) 93884659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(param) \ 93984659b24SMichael Zeller (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_MASK) >> \ 94084659b24SMichael Zeller HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT) 94184659b24SMichael Zeller 94284659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT 0x0 94384659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT 0x1 94484659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 0x2 94584659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR 0x3 94684659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX 0x4 94784659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET 0x5 94884659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET 0x6 94984659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET 0x7 95084659b24SMichael Zeller #define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET 0xf 95184659b24SMichael Zeller 95284659b24SMichael Zeller /* Supported PCM Size, Rates */ 95384659b24SMichael Zeller 95484659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE 0x0a 95584659b24SMichael Zeller 95684659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_MASK 0x00100000 95784659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_SHIFT 20 95884659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_MASK 0x00080000 95984659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_SHIFT 19 96084659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_MASK 0x00040000 96184659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_SHIFT 18 96284659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_MASK 0x00020000 96384659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_SHIFT 17 96484659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_MASK 0x00010000 96584659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_SHIFT 16 96684659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_MASK 0x00000001 96784659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_SHIFT 0 96884659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_MASK 0x00000002 96984659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_SHIFT 1 97084659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_MASK 0x00000004 97184659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_SHIFT 2 97284659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_MASK 0x00000008 97384659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_SHIFT 3 97484659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_MASK 0x00000010 97584659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_SHIFT 4 97684659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_MASK 0x00000020 97784659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_SHIFT 5 97884659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_MASK 0x00000040 97984659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_SHIFT 6 98084659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_MASK 0x00000080 98184659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_SHIFT 7 98284659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_MASK 0x00000100 98384659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_SHIFT 8 98484659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_MASK 0x00000200 98584659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_SHIFT 9 98684659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_MASK 0x00000400 98784659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_SHIFT 10 98884659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_MASK 0x00000800 98984659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_SHIFT 11 99084659b24SMichael Zeller 99184659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(param) \ 99284659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_MASK) >> \ 99384659b24SMichael Zeller HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_SHIFT) 99484659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(param) \ 99584659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_MASK) >> \ 99684659b24SMichael Zeller HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_SHIFT) 99784659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(param) \ 99884659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_MASK) >> \ 99984659b24SMichael Zeller HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_SHIFT) 100084659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(param) \ 100184659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_MASK) >> \ 100284659b24SMichael Zeller HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_SHIFT) 100384659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(param) \ 100484659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_MASK) >> \ 100584659b24SMichael Zeller HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_SHIFT) 100684659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(param) \ 100784659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_MASK) >> \ 100884659b24SMichael Zeller HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_SHIFT) 100984659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(param) \ 101084659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_MASK) >> \ 101184659b24SMichael Zeller HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_SHIFT) 101284659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(param) \ 101384659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_MASK) >> \ 101484659b24SMichael Zeller HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_SHIFT) 101584659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(param) \ 101684659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_MASK) >> \ 101784659b24SMichael Zeller HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_SHIFT) 101884659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(param) \ 101984659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_MASK) >> \ 102084659b24SMichael Zeller HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_SHIFT) 102184659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(param) \ 102284659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_MASK) >> \ 102384659b24SMichael Zeller HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_SHIFT) 102484659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(param) \ 102584659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_MASK) >> \ 102684659b24SMichael Zeller HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_SHIFT) 102784659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(param) \ 102884659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_MASK) >> \ 102984659b24SMichael Zeller HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_SHIFT) 103084659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(param) \ 103184659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_MASK) >> \ 103284659b24SMichael Zeller HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_SHIFT) 103384659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(param) \ 103484659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_MASK) >> \ 103584659b24SMichael Zeller HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_SHIFT) 103684659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(param) \ 103784659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_MASK) >> \ 103884659b24SMichael Zeller HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_SHIFT) 103984659b24SMichael Zeller #define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(param) \ 104084659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_MASK) >> \ 104184659b24SMichael Zeller HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_SHIFT) 104284659b24SMichael Zeller 104384659b24SMichael Zeller /* Supported Stream Formats */ 104484659b24SMichael Zeller #define HDA_PARAM_SUPP_STREAM_FORMATS 0x0b 104584659b24SMichael Zeller 104684659b24SMichael Zeller #define HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK 0x00000004 104784659b24SMichael Zeller #define HDA_PARAM_SUPP_STREAM_FORMATS_AC3_SHIFT 2 104884659b24SMichael Zeller #define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_MASK 0x00000002 104984659b24SMichael Zeller #define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_SHIFT 1 105084659b24SMichael Zeller #define HDA_PARAM_SUPP_STREAM_FORMATS_PCM_MASK 0x00000001 105184659b24SMichael Zeller #define HDA_PARAM_SUPP_STREAM_FORMATS_PCM_SHIFT 0 105284659b24SMichael Zeller 105384659b24SMichael Zeller #define HDA_PARAM_SUPP_STREAM_FORMATS_AC3(param) \ 105484659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK) >> \ 105584659b24SMichael Zeller HDA_PARAM_SUPP_STREAM_FORMATS_AC3_SHIFT) 105684659b24SMichael Zeller #define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(param) \ 105784659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_MASK) >> \ 105884659b24SMichael Zeller HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_SHIFT) 105984659b24SMichael Zeller #define HDA_PARAM_SUPP_STREAM_FORMATS_PCM(param) \ 106084659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_STREAM_FORMATS_PCM_MASK) >> \ 106184659b24SMichael Zeller HDA_PARAM_SUPP_STREAM_FORMATS_PCM_SHIFT) 106284659b24SMichael Zeller 106384659b24SMichael Zeller /* Pin Capabilities */ 106484659b24SMichael Zeller #define HDA_PARAM_PIN_CAP 0x0c 106584659b24SMichael Zeller 106684659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_HBR_MASK 0x08000000 106784659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_HBR_SHIFT 27 106884659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_DP_MASK 0x01000000 106984659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_DP_SHIFT 24 107084659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_EAPD_CAP_MASK 0x00010000 107184659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_EAPD_CAP_SHIFT 16 107284659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_VREF_CTRL_MASK 0x0000ff00 107384659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_VREF_CTRL_SHIFT 8 107484659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK 0x00002000 107584659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_VREF_CTRL_100_SHIFT 13 107684659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK 0x00001000 107784659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_VREF_CTRL_80_SHIFT 12 107884659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_MASK 0x00000400 107984659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_SHIFT 10 108084659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK 0x00000200 108184659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_VREF_CTRL_50_SHIFT 9 108284659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_MASK 0x00000100 108384659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_SHIFT 8 108484659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_HDMI_MASK 0x00000080 108584659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_HDMI_SHIFT 7 108684659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_MASK 0x00000040 108784659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_SHIFT 6 108884659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_INPUT_CAP_MASK 0x00000020 108984659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_INPUT_CAP_SHIFT 5 109084659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_OUTPUT_CAP_MASK 0x00000010 109184659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_OUTPUT_CAP_SHIFT 4 109284659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_HEADPHONE_CAP_MASK 0x00000008 109384659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_HEADPHONE_CAP_SHIFT 3 109484659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_MASK 0x00000004 109584659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_SHIFT 2 109684659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_TRIGGER_REQD_MASK 0x00000002 109784659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_TRIGGER_REQD_SHIFT 1 109884659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_MASK 0x00000001 109984659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_SHIFT 0 110084659b24SMichael Zeller 110184659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_HBR(param) \ 110284659b24SMichael Zeller (((param) & HDA_PARAM_PIN_CAP_HBR_MASK) >> \ 110384659b24SMichael Zeller HDA_PARAM_PIN_CAP_HBR_SHIFT) 110484659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_DP(param) \ 110584659b24SMichael Zeller (((param) & HDA_PARAM_PIN_CAP_DP_MASK) >> \ 110684659b24SMichael Zeller HDA_PARAM_PIN_CAP_DP_SHIFT) 110784659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_EAPD_CAP(param) \ 110884659b24SMichael Zeller (((param) & HDA_PARAM_PIN_CAP_EAPD_CAP_MASK) >> \ 110984659b24SMichael Zeller HDA_PARAM_PIN_CAP_EAPD_CAP_SHIFT) 111084659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_VREF_CTRL(param) \ 111184659b24SMichael Zeller (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_MASK) >> \ 111284659b24SMichael Zeller HDA_PARAM_PIN_CAP_VREF_CTRL_SHIFT) 111384659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_VREF_CTRL_100(param) \ 111484659b24SMichael Zeller (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK) >> \ 111584659b24SMichael Zeller HDA_PARAM_PIN_CAP_VREF_CTRL_100_SHIFT) 111684659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_VREF_CTRL_80(param) \ 111784659b24SMichael Zeller (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK) >> \ 111884659b24SMichael Zeller HDA_PARAM_PIN_CAP_VREF_CTRL_80_SHIFT) 111984659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(param) \ 112084659b24SMichael Zeller (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_MASK) >> \ 112184659b24SMichael Zeller HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_SHIFT) 112284659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_VREF_CTRL_50(param) \ 112384659b24SMichael Zeller (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK) >> \ 112484659b24SMichael Zeller HDA_PARAM_PIN_CAP_VREF_CTRL_50_SHIFT) 112584659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(param) \ 112684659b24SMichael Zeller (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_MASK) >> \ 112784659b24SMichael Zeller HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_SHIFT) 112884659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_HDMI(param) \ 112984659b24SMichael Zeller (((param) & HDA_PARAM_PIN_CAP_HDMI_MASK) >> \ 113084659b24SMichael Zeller HDA_PARAM_PIN_CAP_HDMI_SHIFT) 113184659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(param) \ 113284659b24SMichael Zeller (((param) & HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_MASK) >> \ 113384659b24SMichael Zeller HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_SHIFT) 113484659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_INPUT_CAP(param) \ 113584659b24SMichael Zeller (((param) & HDA_PARAM_PIN_CAP_INPUT_CAP_MASK) >> \ 113684659b24SMichael Zeller HDA_PARAM_PIN_CAP_INPUT_CAP_SHIFT) 113784659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_OUTPUT_CAP(param) \ 113884659b24SMichael Zeller (((param) & HDA_PARAM_PIN_CAP_OUTPUT_CAP_MASK) >> \ 113984659b24SMichael Zeller HDA_PARAM_PIN_CAP_OUTPUT_CAP_SHIFT) 114084659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_HEADPHONE_CAP(param) \ 114184659b24SMichael Zeller (((param) & HDA_PARAM_PIN_CAP_HEADPHONE_CAP_MASK) >> \ 114284659b24SMichael Zeller HDA_PARAM_PIN_CAP_HEADPHONE_CAP_SHIFT) 114384659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(param) \ 114484659b24SMichael Zeller (((param) & HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_MASK) >> \ 114584659b24SMichael Zeller HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_SHIFT) 114684659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_TRIGGER_REQD(param) \ 114784659b24SMichael Zeller (((param) & HDA_PARAM_PIN_CAP_TRIGGER_REQD_MASK) >> \ 114884659b24SMichael Zeller HDA_PARAM_PIN_CAP_TRIGGER_REQD_SHIFT) 114984659b24SMichael Zeller #define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(param) \ 115084659b24SMichael Zeller (((param) & HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_MASK) >> \ 115184659b24SMichael Zeller HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_SHIFT) 115284659b24SMichael Zeller 115384659b24SMichael Zeller /* Input Amplifier Capabilities */ 115484659b24SMichael Zeller #define HDA_PARAM_INPUT_AMP_CAP 0x0d 115584659b24SMichael Zeller 115684659b24SMichael Zeller #define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_MASK 0x80000000 115784659b24SMichael Zeller #define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_SHIFT 31 115884659b24SMichael Zeller #define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_MASK 0x007f0000 115984659b24SMichael Zeller #define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_SHIFT 16 116084659b24SMichael Zeller #define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_MASK 0x00007f00 116184659b24SMichael Zeller #define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_SHIFT 8 116284659b24SMichael Zeller #define HDA_PARAM_INPUT_AMP_CAP_OFFSET_MASK 0x0000007f 116384659b24SMichael Zeller #define HDA_PARAM_INPUT_AMP_CAP_OFFSET_SHIFT 0 116484659b24SMichael Zeller 116584659b24SMichael Zeller #define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP(param) \ 116684659b24SMichael Zeller (((param) & HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_MASK) >> \ 116784659b24SMichael Zeller HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_SHIFT) 116884659b24SMichael Zeller #define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE(param) \ 116984659b24SMichael Zeller (((param) & HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_MASK) >> \ 117084659b24SMichael Zeller HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_SHIFT) 117184659b24SMichael Zeller #define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS(param) \ 117284659b24SMichael Zeller (((param) & HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_MASK) >> \ 117384659b24SMichael Zeller HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_SHIFT) 117484659b24SMichael Zeller #define HDA_PARAM_INPUT_AMP_CAP_OFFSET(param) \ 117584659b24SMichael Zeller (((param) & HDA_PARAM_INPUT_AMP_CAP_OFFSET_MASK) >> \ 117684659b24SMichael Zeller HDA_PARAM_INPUT_AMP_CAP_OFFSET_SHIFT) 117784659b24SMichael Zeller 117884659b24SMichael Zeller /* Output Amplifier Capabilities */ 117984659b24SMichael Zeller #define HDA_PARAM_OUTPUT_AMP_CAP 0x12 118084659b24SMichael Zeller 118184659b24SMichael Zeller #define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_MASK 0x80000000 118284659b24SMichael Zeller #define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_SHIFT 31 118384659b24SMichael Zeller #define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_MASK 0x007f0000 118484659b24SMichael Zeller #define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_SHIFT 16 118584659b24SMichael Zeller #define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_MASK 0x00007f00 118684659b24SMichael Zeller #define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_SHIFT 8 118784659b24SMichael Zeller #define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_MASK 0x0000007f 118884659b24SMichael Zeller #define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_SHIFT 0 118984659b24SMichael Zeller 119084659b24SMichael Zeller #define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(param) \ 119184659b24SMichael Zeller (((param) & HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_MASK) >> \ 119284659b24SMichael Zeller HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_SHIFT) 119384659b24SMichael Zeller #define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(param) \ 119484659b24SMichael Zeller (((param) & HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_MASK) >> \ 119584659b24SMichael Zeller HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_SHIFT) 119684659b24SMichael Zeller #define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(param) \ 119784659b24SMichael Zeller (((param) & HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_MASK) >> \ 119884659b24SMichael Zeller HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_SHIFT) 119984659b24SMichael Zeller #define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(param) \ 120084659b24SMichael Zeller (((param) & HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_MASK) >> \ 120184659b24SMichael Zeller HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_SHIFT) 120284659b24SMichael Zeller 120384659b24SMichael Zeller /* Connection List Length */ 120484659b24SMichael Zeller #define HDA_PARAM_CONN_LIST_LENGTH 0x0e 120584659b24SMichael Zeller 120684659b24SMichael Zeller #define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_MASK 0x00000080 120784659b24SMichael Zeller #define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_SHIFT 7 120884659b24SMichael Zeller #define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_MASK 0x0000007f 120984659b24SMichael Zeller #define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_SHIFT 0 121084659b24SMichael Zeller 121184659b24SMichael Zeller #define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(param) \ 121284659b24SMichael Zeller (((param) & HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_MASK) >> \ 121384659b24SMichael Zeller HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_SHIFT) 121484659b24SMichael Zeller #define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(param) \ 121584659b24SMichael Zeller (((param) & HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_MASK) >> \ 121684659b24SMichael Zeller HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_SHIFT) 121784659b24SMichael Zeller 121884659b24SMichael Zeller /* Supported Power States */ 121984659b24SMichael Zeller #define HDA_PARAM_SUPP_POWER_STATES 0x0f 122084659b24SMichael Zeller 122184659b24SMichael Zeller #define HDA_PARAM_SUPP_POWER_STATES_D3_MASK 0x00000008 122284659b24SMichael Zeller #define HDA_PARAM_SUPP_POWER_STATES_D3_SHIFT 3 122384659b24SMichael Zeller #define HDA_PARAM_SUPP_POWER_STATES_D2_MASK 0x00000004 122484659b24SMichael Zeller #define HDA_PARAM_SUPP_POWER_STATES_D2_SHIFT 2 122584659b24SMichael Zeller #define HDA_PARAM_SUPP_POWER_STATES_D1_MASK 0x00000002 122684659b24SMichael Zeller #define HDA_PARAM_SUPP_POWER_STATES_D1_SHIFT 1 122784659b24SMichael Zeller #define HDA_PARAM_SUPP_POWER_STATES_D0_MASK 0x00000001 122884659b24SMichael Zeller #define HDA_PARAM_SUPP_POWER_STATES_D0_SHIFT 0 122984659b24SMichael Zeller 123084659b24SMichael Zeller #define HDA_PARAM_SUPP_POWER_STATES_D3(param) \ 123184659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_POWER_STATES_D3_MASK) >> \ 123284659b24SMichael Zeller HDA_PARAM_SUPP_POWER_STATES_D3_SHIFT) 123384659b24SMichael Zeller #define HDA_PARAM_SUPP_POWER_STATES_D2(param) \ 123484659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_POWER_STATES_D2_MASK) >> \ 123584659b24SMichael Zeller HDA_PARAM_SUPP_POWER_STATES_D2_SHIFT) 123684659b24SMichael Zeller #define HDA_PARAM_SUPP_POWER_STATES_D1(param) \ 123784659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_POWER_STATES_D1_MASK) >> \ 123884659b24SMichael Zeller HDA_PARAM_SUPP_POWER_STATES_D1_SHIFT) 123984659b24SMichael Zeller #define HDA_PARAM_SUPP_POWER_STATES_D0(param) \ 124084659b24SMichael Zeller (((param) & HDA_PARAM_SUPP_POWER_STATES_D0_MASK) >> \ 124184659b24SMichael Zeller HDA_PARAM_SUPP_POWER_STATES_D0_SHIFT) 124284659b24SMichael Zeller 124384659b24SMichael Zeller /* Processing Capabilities */ 124484659b24SMichael Zeller #define HDA_PARAM_PROCESSING_CAP 0x10 124584659b24SMichael Zeller 124684659b24SMichael Zeller #define HDA_PARAM_PROCESSING_CAP_NUMCOEFF_MASK 0x0000ff00 124784659b24SMichael Zeller #define HDA_PARAM_PROCESSING_CAP_NUMCOEFF_SHIFT 8 124884659b24SMichael Zeller #define HDA_PARAM_PROCESSING_CAP_BENIGN_MASK 0x00000001 124984659b24SMichael Zeller #define HDA_PARAM_PROCESSING_CAP_BENIGN_SHIFT 0 125084659b24SMichael Zeller 125184659b24SMichael Zeller #define HDA_PARAM_PROCESSING_CAP_NUMCOEFF(param) \ 125284659b24SMichael Zeller (((param) & HDA_PARAM_PROCESSING_CAP_NUMCOEFF_MASK) >> \ 125384659b24SMichael Zeller HDA_PARAM_PROCESSING_CAP_NUMCOEFF_SHIFT) 125484659b24SMichael Zeller #define HDA_PARAM_PROCESSING_CAP_BENIGN(param) \ 125584659b24SMichael Zeller (((param) & HDA_PARAM_PROCESSING_CAP_BENIGN_MASK) >> \ 125684659b24SMichael Zeller HDA_PARAM_PROCESSING_CAP_BENIGN_SHIFT) 125784659b24SMichael Zeller 125884659b24SMichael Zeller /* GPIO Count */ 125984659b24SMichael Zeller #define HDA_PARAM_GPIO_COUNT 0x11 126084659b24SMichael Zeller 126184659b24SMichael Zeller #define HDA_PARAM_GPIO_COUNT_GPI_WAKE_MASK 0x80000000 126284659b24SMichael Zeller #define HDA_PARAM_GPIO_COUNT_GPI_WAKE_SHIFT 31 126384659b24SMichael Zeller #define HDA_PARAM_GPIO_COUNT_GPI_UNSOL_MASK 0x40000000 126484659b24SMichael Zeller #define HDA_PARAM_GPIO_COUNT_GPI_UNSOL_SHIFT 30 126584659b24SMichael Zeller #define HDA_PARAM_GPIO_COUNT_NUM_GPI_MASK 0x00ff0000 126684659b24SMichael Zeller #define HDA_PARAM_GPIO_COUNT_NUM_GPI_SHIFT 16 126784659b24SMichael Zeller #define HDA_PARAM_GPIO_COUNT_NUM_GPO_MASK 0x0000ff00 126884659b24SMichael Zeller #define HDA_PARAM_GPIO_COUNT_NUM_GPO_SHIFT 8 126984659b24SMichael Zeller #define HDA_PARAM_GPIO_COUNT_NUM_GPIO_MASK 0x000000ff 127084659b24SMichael Zeller #define HDA_PARAM_GPIO_COUNT_NUM_GPIO_SHIFT 0 127184659b24SMichael Zeller 127284659b24SMichael Zeller #define HDA_PARAM_GPIO_COUNT_GPI_WAKE(param) \ 127384659b24SMichael Zeller (((param) & HDA_PARAM_GPIO_COUNT_GPI_WAKE_MASK) >> \ 127484659b24SMichael Zeller HDA_PARAM_GPIO_COUNT_GPI_WAKE_SHIFT) 127584659b24SMichael Zeller #define HDA_PARAM_GPIO_COUNT_GPI_UNSOL(param) \ 127684659b24SMichael Zeller (((param) & HDA_PARAM_GPIO_COUNT_GPI_UNSOL_MASK) >> \ 127784659b24SMichael Zeller HDA_PARAM_GPIO_COUNT_GPI_UNSOL_SHIFT) 127884659b24SMichael Zeller #define HDA_PARAM_GPIO_COUNT_NUM_GPI(param) \ 127984659b24SMichael Zeller (((param) & HDA_PARAM_GPIO_COUNT_NUM_GPI_MASK) >> \ 128084659b24SMichael Zeller HDA_PARAM_GPIO_COUNT_NUM_GPI_SHIFT) 128184659b24SMichael Zeller #define HDA_PARAM_GPIO_COUNT_NUM_GPO(param) \ 128284659b24SMichael Zeller (((param) & HDA_PARAM_GPIO_COUNT_NUM_GPO_MASK) >> \ 128384659b24SMichael Zeller HDA_PARAM_GPIO_COUNT_NUM_GPO_SHIFT) 128484659b24SMichael Zeller #define HDA_PARAM_GPIO_COUNT_NUM_GPIO(param) \ 128584659b24SMichael Zeller (((param) & HDA_PARAM_GPIO_COUNT_NUM_GPIO_MASK) >> \ 128684659b24SMichael Zeller HDA_PARAM_GPIO_COUNT_NUM_GPIO_SHIFT) 128784659b24SMichael Zeller 128884659b24SMichael Zeller /* Volume Knob Capabilities */ 128984659b24SMichael Zeller #define HDA_PARAM_VOLUME_KNOB_CAP 0x13 129084659b24SMichael Zeller 129184659b24SMichael Zeller #define HDA_PARAM_VOLUME_KNOB_CAP_DELTA_MASK 0x00000080 129284659b24SMichael Zeller #define HDA_PARAM_VOLUME_KNOB_CAP_DELTA_SHIFT 7 129384659b24SMichael Zeller #define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_MASK 0x0000007f 129484659b24SMichael Zeller #define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_SHIFT 0 129584659b24SMichael Zeller 129684659b24SMichael Zeller #define HDA_PARAM_VOLUME_KNOB_CAP_DELTA(param) \ 129784659b24SMichael Zeller (((param) & HDA_PARAM_VOLUME_KNOB_CAP_DELTA_MASK) >> \ 129884659b24SMichael Zeller HDA_PARAM_VOLUME_KNOB_CAP_DELTA_SHIFT) 129984659b24SMichael Zeller #define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS(param) \ 130084659b24SMichael Zeller (((param) & HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_MASK) >> \ 130184659b24SMichael Zeller HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_SHIFT) 130284659b24SMichael Zeller 130384659b24SMichael Zeller 130484659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK 0x0000000f 130584659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT 0 130684659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK 0x000000f0 130784659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT 4 130884659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_MISC_MASK 0x00000f00 130984659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_MISC_SHIFT 8 131084659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_COLOR_MASK 0x0000f000 131184659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT 12 131284659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK 0x000f0000 131384659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT 16 131484659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_DEVICE_MASK 0x00f00000 131584659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT 20 131684659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_LOCATION_MASK 0x3f000000 131784659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT 24 131884659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK 0xc0000000 131984659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT 30 132084659b24SMichael Zeller 132184659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf) \ 132284659b24SMichael Zeller (((conf) & HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK) >> \ 132384659b24SMichael Zeller HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) 132484659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf) \ 132584659b24SMichael Zeller (((conf) & HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) >> \ 132684659b24SMichael Zeller HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) 132784659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_MISC(conf) \ 132884659b24SMichael Zeller (((conf) & HDA_CONFIG_DEFAULTCONF_MISC_MASK) >> \ 132984659b24SMichael Zeller HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) 133084659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_COLOR(conf) \ 133184659b24SMichael Zeller (((conf) & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> \ 133284659b24SMichael Zeller HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) 133384659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf) \ 133484659b24SMichael Zeller (((conf) & HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK) >> \ 133584659b24SMichael Zeller HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) 133684659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_DEVICE(conf) \ 133784659b24SMichael Zeller (((conf) & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> \ 133884659b24SMichael Zeller HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) 133984659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_LOCATION(conf) \ 134084659b24SMichael Zeller (((conf) & HDA_CONFIG_DEFAULTCONF_LOCATION_MASK) >> \ 134184659b24SMichael Zeller HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) 134284659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf) \ 134384659b24SMichael Zeller (((conf) & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> \ 134484659b24SMichael Zeller HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) 134584659b24SMichael Zeller 134684659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK (0<<30) 134784659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE (1<<30) 134884659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED (2<<30) 134984659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH (3<<30) 135084659b24SMichael Zeller 135184659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT (0<<20) 135284659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER (1<<20) 135384659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT (2<<20) 135484659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_DEVICE_CD (3<<20) 135584659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT (4<<20) 135684659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT (5<<20) 135784659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE (6<<20) 135884659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET (7<<20) 135984659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN (8<<20) 136084659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_DEVICE_AUX (9<<20) 136184659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN (10<<20) 136284659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY (11<<20) 136384659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN (12<<20) 136484659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN (13<<20) 136584659b24SMichael Zeller #define HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER (15<<20) 136684659b24SMichael Zeller 136784659b24SMichael Zeller #endif /* _HDA_REG_H_ */ 1368