1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 4. Neither the name of the University nor the names of its contributors
14 *    may be used to endorse or promote products derived from this software
15 *    without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 *	from: @(#)specialreg.h	7.1 (Berkeley) 5/9/91
30 * $FreeBSD$
31 */
32
33#ifndef _MACHINE_SPECIALREG_H_
34#define	_MACHINE_SPECIALREG_H_
35
36/*
37 * Bits in 386 special registers:
38 */
39#define	CR0_PE	0x00000001	/* Protected mode Enable */
40#define	CR0_MP	0x00000002	/* "Math" (fpu) Present */
41#define	CR0_EM	0x00000004	/* EMulate FPU instructions. (trap ESC only) */
42#define	CR0_TS	0x00000008	/* Task Switched (if MP, trap ESC and WAIT) */
43#define	CR0_PG	0x80000000	/* PaGing enable */
44
45/*
46 * Bits in 486 special registers:
47 */
48#define	CR0_NE	0x00000020	/* Numeric Error enable (EX16 vs IRQ13) */
49#define	CR0_WP	0x00010000	/* Write Protect (honor page protect in
50							   all modes) */
51#define	CR0_AM	0x00040000	/* Alignment Mask (set to enable AC flag) */
52#define	CR0_NW  0x20000000	/* Not Write-through */
53#define	CR0_CD  0x40000000	/* Cache Disable */
54
55#define	CR3_PCID_SAVE 0x8000000000000000
56#define	CR3_PCID_MASK 0xfff
57
58/*
59 * Bits in PPro special registers
60 */
61#define	CR4_VME	0x00000001	/* Virtual 8086 mode extensions */
62#define	CR4_PVI	0x00000002	/* Protected-mode virtual interrupts */
63#define	CR4_TSD	0x00000004	/* Time stamp disable */
64#define	CR4_DE	0x00000008	/* Debugging extensions */
65#define	CR4_PSE	0x00000010	/* Page size extensions */
66#define	CR4_PAE	0x00000020	/* Physical address extension */
67#define	CR4_MCE	0x00000040	/* Machine check enable */
68#define	CR4_PGE	0x00000080	/* Page global enable */
69#define	CR4_PCE	0x00000100	/* Performance monitoring counter enable */
70#define	CR4_FXSR 0x00000200	/* Fast FPU save/restore used by OS */
71#define	CR4_XMM	0x00000400	/* enable SIMD/MMX2 to use except 16 */
72#define	CR4_VMXE 0x00002000	/* enable VMX operation (Intel-specific) */
73#define	CR4_FSGSBASE 0x00010000	/* Enable FS/GS BASE accessing instructions */
74#define	CR4_PCIDE 0x00020000	/* Enable Context ID */
75#define	CR4_XSAVE 0x00040000	/* XSETBV/XGETBV */
76#define	CR4_SMEP 0x00100000	/* Supervisor-Mode Execution Prevention */
77
78/*
79 * Bits in AMD64 special registers.  EFER is 64 bits wide.
80 */
81#define	EFER_SCE 0x000000001	/* System Call Extensions (R/W) */
82#define	EFER_LME 0x000000100	/* Long mode enable (R/W) */
83#define	EFER_LMA 0x000000400	/* Long mode active (R) */
84#define	EFER_NXE 0x000000800	/* PTE No-Execute bit enable (R/W) */
85#define	EFER_SVM 0x000001000	/* SVM enable bit for AMD, reserved for Intel */
86#define	EFER_LMSLE 0x000002000	/* Long Mode Segment Limit Enable */
87#define	EFER_FFXSR 0x000004000	/* Fast FXSAVE/FSRSTOR */
88#define	EFER_TCE   0x000008000	/* Translation Cache Extension */
89
90/*
91 * Intel Extended Features registers
92 */
93#define	XCR0	0		/* XFEATURE_ENABLED_MASK register */
94
95#define	XFEATURE_ENABLED_X87		0x00000001
96#define	XFEATURE_ENABLED_SSE		0x00000002
97#define	XFEATURE_ENABLED_YMM_HI128	0x00000004
98#define	XFEATURE_ENABLED_AVX		XFEATURE_ENABLED_YMM_HI128
99#define	XFEATURE_ENABLED_BNDREGS	0x00000008
100#define	XFEATURE_ENABLED_BNDCSR		0x00000010
101#define	XFEATURE_ENABLED_OPMASK		0x00000020
102#define	XFEATURE_ENABLED_ZMM_HI256	0x00000040
103#define	XFEATURE_ENABLED_HI16_ZMM	0x00000080
104
105#define	XFEATURE_AVX					\
106    (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX)
107#define	XFEATURE_AVX512						\
108    (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 |	\
109    XFEATURE_ENABLED_HI16_ZMM)
110#define	XFEATURE_MPX					\
111    (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR)
112
113/*
114 * CPUID instruction features register
115 */
116#define	CPUID_FPU	0x00000001
117#define	CPUID_VME	0x00000002
118#define	CPUID_DE	0x00000004
119#define	CPUID_PSE	0x00000008
120#define	CPUID_TSC	0x00000010
121#define	CPUID_MSR	0x00000020
122#define	CPUID_PAE	0x00000040
123#define	CPUID_MCE	0x00000080
124#define	CPUID_CX8	0x00000100
125#define	CPUID_APIC	0x00000200
126#define	CPUID_B10	0x00000400
127#define	CPUID_SEP	0x00000800
128#define	CPUID_MTRR	0x00001000
129#define	CPUID_PGE	0x00002000
130#define	CPUID_MCA	0x00004000
131#define	CPUID_CMOV	0x00008000
132#define	CPUID_PAT	0x00010000
133#define	CPUID_PSE36	0x00020000
134#define	CPUID_PSN	0x00040000
135#define	CPUID_CLFSH	0x00080000
136#define	CPUID_B20	0x00100000
137#define	CPUID_DS	0x00200000
138#define	CPUID_ACPI	0x00400000
139#define	CPUID_MMX	0x00800000
140#define	CPUID_FXSR	0x01000000
141#define	CPUID_SSE	0x02000000
142#define	CPUID_XMM	0x02000000
143#define	CPUID_SSE2	0x04000000
144#define	CPUID_SS	0x08000000
145#define	CPUID_HTT	0x10000000
146#define	CPUID_TM	0x20000000
147#define	CPUID_IA64	0x40000000
148#define	CPUID_PBE	0x80000000
149
150#define	CPUID2_SSE3	0x00000001
151#define	CPUID2_PCLMULQDQ 0x00000002
152#define	CPUID2_DTES64	0x00000004
153#define	CPUID2_MON	0x00000008
154#define	CPUID2_DS_CPL	0x00000010
155#define	CPUID2_VMX	0x00000020
156#define	CPUID2_SMX	0x00000040
157#define	CPUID2_EST	0x00000080
158#define	CPUID2_TM2	0x00000100
159#define	CPUID2_SSSE3	0x00000200
160#define	CPUID2_CNXTID	0x00000400
161#define	CPUID2_SDBG	0x00000800
162#define	CPUID2_FMA	0x00001000
163#define	CPUID2_CX16	0x00002000
164#define	CPUID2_XTPR	0x00004000
165#define	CPUID2_PDCM	0x00008000
166#define	CPUID2_PCID	0x00020000
167#define	CPUID2_DCA	0x00040000
168#define	CPUID2_SSE41	0x00080000
169#define	CPUID2_SSE42	0x00100000
170#define	CPUID2_X2APIC	0x00200000
171#define	CPUID2_MOVBE	0x00400000
172#define	CPUID2_POPCNT	0x00800000
173#define	CPUID2_TSCDLT	0x01000000
174#define	CPUID2_AESNI	0x02000000
175#define	CPUID2_XSAVE	0x04000000
176#define	CPUID2_OSXSAVE	0x08000000
177#define	CPUID2_AVX	0x10000000
178#define	CPUID2_F16C	0x20000000
179#define	CPUID2_RDRAND	0x40000000
180#define	CPUID2_HV	0x80000000
181
182/*
183 * Important bits in the Thermal and Power Management flags
184 * CPUID.6 EAX and ECX.
185 */
186#define	CPUTPM1_SENSOR	0x00000001
187#define	CPUTPM1_TURBO	0x00000002
188#define	CPUTPM1_ARAT	0x00000004
189#define	CPUTPM2_EFFREQ	0x00000001
190
191/*
192 * Important bits in the AMD extended cpuid flags
193 */
194#define	AMDID_SYSCALL	0x00000800
195#define	AMDID_MP	0x00080000
196#define	AMDID_NX	0x00100000
197#define	AMDID_EXT_MMX	0x00400000
198#define	AMDID_FFXSR	0x02000000
199#define	AMDID_PAGE1GB	0x04000000
200#define	AMDID_RDTSCP	0x08000000
201#define	AMDID_LM	0x20000000
202#define	AMDID_EXT_3DNOW	0x40000000
203#define	AMDID_3DNOW	0x80000000
204
205#define	AMDID2_LAHF	0x00000001
206#define	AMDID2_CMP	0x00000002
207#define	AMDID2_SVM	0x00000004
208#define	AMDID2_EXT_APIC	0x00000008
209#define	AMDID2_CR8	0x00000010
210#define	AMDID2_ABM	0x00000020
211#define	AMDID2_SSE4A	0x00000040
212#define	AMDID2_MAS	0x00000080
213#define	AMDID2_PREFETCH	0x00000100
214#define	AMDID2_OSVW	0x00000200
215#define	AMDID2_IBS	0x00000400
216#define	AMDID2_XOP	0x00000800
217#define	AMDID2_SKINIT	0x00001000
218#define	AMDID2_WDT	0x00002000
219#define	AMDID2_LWP	0x00008000
220#define	AMDID2_FMA4	0x00010000
221#define	AMDID2_TCE	0x00020000
222#define	AMDID2_NODE_ID	0x00080000
223#define	AMDID2_TBM	0x00200000
224#define	AMDID2_TOPOLOGY	0x00400000
225#define	AMDID2_PCXC	0x00800000
226#define	AMDID2_PNXC	0x01000000
227#define	AMDID2_DBE	0x04000000
228#define	AMDID2_PTSC	0x08000000
229#define	AMDID2_PTSCEL2I	0x10000000
230
231/*
232 * CPUID instruction 1 eax info
233 */
234#define	CPUID_STEPPING		0x0000000f
235#define	CPUID_MODEL		0x000000f0
236#define	CPUID_FAMILY		0x00000f00
237#define	CPUID_EXT_MODEL		0x000f0000
238#define	CPUID_EXT_FAMILY	0x0ff00000
239#ifdef __i386__
240#define	CPUID_TO_MODEL(id) \
241    ((((id) & CPUID_MODEL) >> 4) | \
242    ((((id) & CPUID_FAMILY) >= 0x600) ? \
243    (((id) & CPUID_EXT_MODEL) >> 12) : 0))
244#define	CPUID_TO_FAMILY(id) \
245    ((((id) & CPUID_FAMILY) >> 8) + \
246    ((((id) & CPUID_FAMILY) == 0xf00) ? \
247    (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
248#else
249#define	CPUID_TO_MODEL(id) \
250    ((((id) & CPUID_MODEL) >> 4) | \
251    (((id) & CPUID_EXT_MODEL) >> 12))
252#define	CPUID_TO_FAMILY(id) \
253    ((((id) & CPUID_FAMILY) >> 8) + \
254    (((id) & CPUID_EXT_FAMILY) >> 20))
255#endif
256
257/*
258 * CPUID instruction 1 ebx info
259 */
260#define	CPUID_BRAND_INDEX	0x000000ff
261#define	CPUID_CLFUSH_SIZE	0x0000ff00
262#define	CPUID_HTT_CORES		0x00ff0000
263#define	CPUID_LOCAL_APIC_ID	0xff000000
264
265/*
266 * CPUID instruction 5 info
267 */
268#define	CPUID5_MON_MIN_SIZE	0x0000ffff	/* eax */
269#define	CPUID5_MON_MAX_SIZE	0x0000ffff	/* ebx */
270#define	CPUID5_MON_MWAIT_EXT	0x00000001	/* ecx */
271#define	CPUID5_MWAIT_INTRBREAK	0x00000002	/* ecx */
272
273/*
274 * MWAIT cpu power states.  Lower 4 bits are sub-states.
275 */
276#define	MWAIT_C0	0xf0
277#define	MWAIT_C1	0x00
278#define	MWAIT_C2	0x10
279#define	MWAIT_C3	0x20
280#define	MWAIT_C4	0x30
281
282/*
283 * MWAIT extensions.
284 */
285/* Interrupt breaks MWAIT even when masked. */
286#define	MWAIT_INTRBREAK		0x00000001
287
288/*
289 * CPUID instruction 6 ecx info
290 */
291#define	CPUID_PERF_STAT		0x00000001
292#define	CPUID_PERF_BIAS		0x00000008
293
294/*
295 * CPUID instruction 0xb ebx info.
296 */
297#define	CPUID_TYPE_INVAL	0
298#define	CPUID_TYPE_SMT		1
299#define	CPUID_TYPE_CORE		2
300
301/*
302 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1
303 */
304#define	CPUID_EXTSTATE_XSAVEOPT	0x00000001
305#define	CPUID_EXTSTATE_XSAVEC	0x00000002
306#define	CPUID_EXTSTATE_XINUSE	0x00000004
307#define	CPUID_EXTSTATE_XSAVES	0x00000008
308
309/*
310 * AMD extended function 8000_0007h edx info
311 */
312#define	AMDPM_TS		0x00000001
313#define	AMDPM_FID		0x00000002
314#define	AMDPM_VID		0x00000004
315#define	AMDPM_TTP		0x00000008
316#define	AMDPM_TM		0x00000010
317#define	AMDPM_STC		0x00000020
318#define	AMDPM_100MHZ_STEPS	0x00000040
319#define	AMDPM_HW_PSTATE		0x00000080
320#define	AMDPM_TSC_INVARIANT	0x00000100
321#define	AMDPM_CPB		0x00000200
322
323/*
324 * AMD extended function 8000_0008h ecx info
325 */
326#define	AMDID_CMP_CORES		0x000000ff
327#define	AMDID_COREID_SIZE	0x0000f000
328#define	AMDID_COREID_SIZE_SHIFT	12
329
330/*
331 * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info
332 */
333#define	CPUID_STDEXT_FSGSBASE	0x00000001
334#define	CPUID_STDEXT_TSC_ADJUST	0x00000002
335#define	CPUID_STDEXT_BMI1	0x00000008
336#define	CPUID_STDEXT_HLE	0x00000010
337#define	CPUID_STDEXT_AVX2	0x00000020
338#define	CPUID_STDEXT_FDP_EXC	0x00000040
339#define	CPUID_STDEXT_SMEP	0x00000080
340#define	CPUID_STDEXT_BMI2	0x00000100
341#define	CPUID_STDEXT_ERMS	0x00000200
342#define	CPUID_STDEXT_INVPCID	0x00000400
343#define	CPUID_STDEXT_RTM	0x00000800
344#define	CPUID_STDEXT_MPX	0x00004000
345#define	CPUID_STDEXT_AVX512F	0x00010000
346#define	CPUID_STDEXT_AVX512DQ	0x00020000
347#define	CPUID_STDEXT_RDSEED	0x00040000
348#define	CPUID_STDEXT_ADX	0x00080000
349#define	CPUID_STDEXT_SMAP	0x00100000
350#define	CPUID_STDEXT_AVX512IFMA	0x00200000
351#define	CPUID_STDEXT_PCOMMIT	0x00400000
352#define	CPUID_STDEXT_CLFLUSHOPT	0x00800000
353#define	CPUID_STDEXT_CLWB	0x01000000
354#define	CPUID_STDEXT_PROCTRACE	0x02000000
355#define	CPUID_STDEXT_AVX512PF	0x04000000
356#define	CPUID_STDEXT_AVX512ER	0x08000000
357#define	CPUID_STDEXT_AVX512CD	0x10000000
358#define	CPUID_STDEXT_SHA	0x20000000
359#define	CPUID_STDEXT_AVX512BW	0x40000000
360
361/*
362 * CPUID manufacturers identifiers
363 */
364#define	AMD_VENDOR_ID		"AuthenticAMD"
365#define	CENTAUR_VENDOR_ID	"CentaurHauls"
366#define	CYRIX_VENDOR_ID		"CyrixInstead"
367#define	INTEL_VENDOR_ID		"GenuineIntel"
368#define	NEXGEN_VENDOR_ID	"NexGenDriven"
369#define	NSC_VENDOR_ID		"Geode by NSC"
370#define	RISE_VENDOR_ID		"RiseRiseRise"
371#define	SIS_VENDOR_ID		"SiS SiS SiS "
372#define	TRANSMETA_VENDOR_ID	"GenuineTMx86"
373#define	UMC_VENDOR_ID		"UMC UMC UMC "
374
375/*
376 * Model-specific registers for the i386 family
377 */
378#define	MSR_P5_MC_ADDR		0x000
379#define	MSR_P5_MC_TYPE		0x001
380#define	MSR_TSC			0x010
381#define	MSR_P5_CESR		0x011
382#define	MSR_P5_CTR0		0x012
383#define	MSR_P5_CTR1		0x013
384#define	MSR_IA32_PLATFORM_ID	0x017
385#define	MSR_APICBASE		0x01b
386#define	MSR_EBL_CR_POWERON	0x02a
387#define	MSR_TEST_CTL		0x033
388#define	MSR_IA32_FEATURE_CONTROL 0x03a
389#define	MSR_BIOS_UPDT_TRIG	0x079
390#define	MSR_BBL_CR_D0		0x088
391#define	MSR_BBL_CR_D1		0x089
392#define	MSR_BBL_CR_D2		0x08a
393#define	MSR_BIOS_SIGN		0x08b
394#define	MSR_PERFCTR0		0x0c1
395#define	MSR_PERFCTR1		0x0c2
396#define	MSR_PLATFORM_INFO	0x0ce
397#define	MSR_MPERF		0x0e7
398#define	MSR_APERF		0x0e8
399#define	MSR_IA32_EXT_CONFIG	0x0ee	/* Undocumented. Core Solo/Duo only */
400#define	MSR_MTRRcap		0x0fe
401#define	MSR_BBL_CR_ADDR		0x116
402#define	MSR_BBL_CR_DECC		0x118
403#define	MSR_BBL_CR_CTL		0x119
404#define	MSR_BBL_CR_TRIG		0x11a
405#define	MSR_BBL_CR_BUSY		0x11b
406#define	MSR_BBL_CR_CTL3		0x11e
407#define	MSR_SYSENTER_CS_MSR	0x174
408#define	MSR_SYSENTER_ESP_MSR	0x175
409#define	MSR_SYSENTER_EIP_MSR	0x176
410#define	MSR_MCG_CAP		0x179
411#define	MSR_MCG_STATUS		0x17a
412#define	MSR_MCG_CTL		0x17b
413#define	MSR_EVNTSEL0		0x186
414#define	MSR_EVNTSEL1		0x187
415#define	MSR_THERM_CONTROL	0x19a
416#define	MSR_THERM_INTERRUPT	0x19b
417#define	MSR_THERM_STATUS	0x19c
418#define	MSR_IA32_MISC_ENABLE	0x1a0
419#define	MSR_IA32_TEMPERATURE_TARGET	0x1a2
420#define	MSR_TURBO_RATIO_LIMIT	0x1ad
421#define	MSR_TURBO_RATIO_LIMIT1	0x1ae
422#define	MSR_DEBUGCTLMSR		0x1d9
423#define	MSR_LASTBRANCHFROMIP	0x1db
424#define	MSR_LASTBRANCHTOIP	0x1dc
425#define	MSR_LASTINTFROMIP	0x1dd
426#define	MSR_LASTINTTOIP		0x1de
427#define	MSR_ROB_CR_BKUPTMPDR6	0x1e0
428#define	MSR_MTRRVarBase		0x200
429#define	MSR_MTRR64kBase		0x250
430#define	MSR_MTRR16kBase		0x258
431#define	MSR_MTRR4kBase		0x268
432#define	MSR_PAT			0x277
433#define	MSR_MC0_CTL2		0x280
434#define	MSR_MTRRdefType		0x2ff
435#define	MSR_MC0_CTL		0x400
436#define	MSR_MC0_STATUS		0x401
437#define	MSR_MC0_ADDR		0x402
438#define	MSR_MC0_MISC		0x403
439#define	MSR_MC1_CTL		0x404
440#define	MSR_MC1_STATUS		0x405
441#define	MSR_MC1_ADDR		0x406
442#define	MSR_MC1_MISC		0x407
443#define	MSR_MC2_CTL		0x408
444#define	MSR_MC2_STATUS		0x409
445#define	MSR_MC2_ADDR		0x40a
446#define	MSR_MC2_MISC		0x40b
447#define	MSR_MC3_CTL		0x40c
448#define	MSR_MC3_STATUS		0x40d
449#define	MSR_MC3_ADDR		0x40e
450#define	MSR_MC3_MISC		0x40f
451#define	MSR_MC4_CTL		0x410
452#define	MSR_MC4_STATUS		0x411
453#define	MSR_MC4_ADDR		0x412
454#define	MSR_MC4_MISC		0x413
455#define	MSR_RAPL_POWER_UNIT	0x606
456#define	MSR_PKG_ENERGY_STATUS	0x611
457#define	MSR_DRAM_ENERGY_STATUS	0x619
458#define	MSR_PP0_ENERGY_STATUS	0x639
459#define	MSR_PP1_ENERGY_STATUS	0x641
460
461/*
462 * VMX MSRs
463 */
464#define	MSR_VMX_BASIC		0x480
465#define	MSR_VMX_PINBASED_CTLS	0x481
466#define	MSR_VMX_PROCBASED_CTLS	0x482
467#define	MSR_VMX_EXIT_CTLS	0x483
468#define	MSR_VMX_ENTRY_CTLS	0x484
469#define	MSR_VMX_CR0_FIXED0	0x486
470#define	MSR_VMX_CR0_FIXED1	0x487
471#define	MSR_VMX_CR4_FIXED0	0x488
472#define	MSR_VMX_CR4_FIXED1	0x489
473#define	MSR_VMX_PROCBASED_CTLS2	0x48b
474#define	MSR_VMX_EPT_VPID_CAP	0x48c
475#define	MSR_VMX_TRUE_PINBASED_CTLS	0x48d
476#define	MSR_VMX_TRUE_PROCBASED_CTLS	0x48e
477#define	MSR_VMX_TRUE_EXIT_CTLS	0x48f
478#define	MSR_VMX_TRUE_ENTRY_CTLS	0x490
479
480/*
481 * X2APIC MSRs
482 */
483#define	MSR_APIC_000		0x800
484#define	MSR_APIC_ID		0x802
485#define	MSR_APIC_VERSION	0x803
486#define	MSR_APIC_TPR		0x808
487#define	MSR_APIC_EOI		0x80b
488#define	MSR_APIC_LDR		0x80d
489#define	MSR_APIC_SVR		0x80f
490#define	MSR_APIC_ISR0		0x810
491#define	MSR_APIC_ISR1		0x811
492#define	MSR_APIC_ISR2		0x812
493#define	MSR_APIC_ISR3		0x813
494#define	MSR_APIC_ISR4		0x814
495#define	MSR_APIC_ISR5		0x815
496#define	MSR_APIC_ISR6		0x816
497#define	MSR_APIC_ISR7		0x817
498#define	MSR_APIC_TMR0		0x818
499#define	MSR_APIC_IRR0		0x820
500#define	MSR_APIC_ESR		0x828
501#define	MSR_APIC_LVT_CMCI	0x82F
502#define	MSR_APIC_ICR		0x830
503#define	MSR_APIC_LVT_TIMER	0x832
504#define	MSR_APIC_LVT_THERMAL	0x833
505#define	MSR_APIC_LVT_PCINT	0x834
506#define	MSR_APIC_LVT_LINT0	0x835
507#define	MSR_APIC_LVT_LINT1	0x836
508#define	MSR_APIC_LVT_ERROR	0x837
509#define	MSR_APIC_ICR_TIMER	0x838
510#define	MSR_APIC_CCR_TIMER	0x839
511#define	MSR_APIC_DCR_TIMER	0x83e
512#define	MSR_APIC_SELF_IPI	0x83f
513
514#define	MSR_IA32_XSS		0xda0
515
516/*
517 * Constants related to MSR's.
518 */
519#define	APICBASE_RESERVED	0x000002ff
520#define	APICBASE_BSP		0x00000100
521#define	APICBASE_X2APIC		0x00000400
522#define	APICBASE_ENABLED	0x00000800
523#define	APICBASE_ADDRESS	0xfffff000
524
525/* MSR_IA32_FEATURE_CONTROL related */
526#define	IA32_FEATURE_CONTROL_LOCK	0x01	/* lock bit */
527#define	IA32_FEATURE_CONTROL_SMX_EN	0x02	/* enable VMX inside SMX */
528#define	IA32_FEATURE_CONTROL_VMX_EN	0x04	/* enable VMX outside SMX */
529
530/* MSR IA32_MISC_ENABLE */
531#define	IA32_MISC_EN_FASTSTR	0x0000000000000001ULL
532#define	IA32_MISC_EN_ATCCE	0x0000000000000008ULL
533#define	IA32_MISC_EN_PERFMON	0x0000000000000080ULL
534#define	IA32_MISC_EN_PEBSU	0x0000000000001000ULL
535#define	IA32_MISC_EN_ESSTE	0x0000000000010000ULL
536#define	IA32_MISC_EN_MONE	0x0000000000040000ULL
537#define	IA32_MISC_EN_LIMCPUID	0x0000000000400000ULL
538#define	IA32_MISC_EN_xTPRD	0x0000000000800000ULL
539#define	IA32_MISC_EN_XDD	0x0000000400000000ULL
540
541/*
542 * PAT modes.
543 */
544#define	PAT_UNCACHEABLE		0x00
545#define	PAT_WRITE_COMBINING	0x01
546#define	PAT_WRITE_THROUGH	0x04
547#define	PAT_WRITE_PROTECTED	0x05
548#define	PAT_WRITE_BACK		0x06
549#define	PAT_UNCACHED		0x07
550#define	PAT_VALUE(i, m)		((long long)(m) << (8 * (i)))
551#define	PAT_MASK(i)		PAT_VALUE(i, 0xff)
552
553/*
554 * Constants related to MTRRs
555 */
556#define	MTRR_UNCACHEABLE	0x00
557#define	MTRR_WRITE_COMBINING	0x01
558#define	MTRR_WRITE_THROUGH	0x04
559#define	MTRR_WRITE_PROTECTED	0x05
560#define	MTRR_WRITE_BACK		0x06
561#define	MTRR_N64K		8	/* numbers of fixed-size entries */
562#define	MTRR_N16K		16
563#define	MTRR_N4K		64
564#define	MTRR_CAP_WC		0x0000000000000400
565#define	MTRR_CAP_FIXED		0x0000000000000100
566#define	MTRR_CAP_VCNT		0x00000000000000ff
567#define	MTRR_DEF_ENABLE		0x0000000000000800
568#define	MTRR_DEF_FIXED_ENABLE	0x0000000000000400
569#define	MTRR_DEF_TYPE		0x00000000000000ff
570#define	MTRR_PHYSBASE_PHYSBASE	0x000ffffffffff000
571#define	MTRR_PHYSBASE_TYPE	0x00000000000000ff
572#define	MTRR_PHYSMASK_PHYSMASK	0x000ffffffffff000
573#define	MTRR_PHYSMASK_VALID	0x0000000000000800
574
575/*
576 * Cyrix configuration registers, accessible as IO ports.
577 */
578#define	CCR0			0xc0	/* Configuration control register 0 */
579#define	CCR0_NC0		0x01	/* First 64K of each 1M memory region is
580								   non-cacheable */
581#define	CCR0_NC1		0x02	/* 640K-1M region is non-cacheable */
582#define	CCR0_A20M		0x04	/* Enables A20M# input pin */
583#define	CCR0_KEN		0x08	/* Enables KEN# input pin */
584#define	CCR0_FLUSH		0x10	/* Enables FLUSH# input pin */
585#define	CCR0_BARB		0x20	/* Flushes internal cache when entering hold
586								   state */
587#define	CCR0_CO			0x40	/* Cache org: 1=direct mapped, 0=2x set
588								   assoc */
589#define	CCR0_SUSPEND	0x80	/* Enables SUSP# and SUSPA# pins */
590
591#define	CCR1			0xc1	/* Configuration control register 1 */
592#define	CCR1_RPL		0x01	/* Enables RPLSET and RPLVAL# pins */
593#define	CCR1_SMI		0x02	/* Enables SMM pins */
594#define	CCR1_SMAC		0x04	/* System management memory access */
595#define	CCR1_MMAC		0x08	/* Main memory access */
596#define	CCR1_NO_LOCK	0x10	/* Negate LOCK# */
597#define	CCR1_SM3		0x80	/* SMM address space address region 3 */
598
599#define	CCR2			0xc2
600#define	CCR2_WB			0x02	/* Enables WB cache interface pins */
601#define	CCR2_SADS		0x02	/* Slow ADS */
602#define	CCR2_LOCK_NW	0x04	/* LOCK NW Bit */
603#define	CCR2_SUSP_HLT	0x08	/* Suspend on HALT */
604#define	CCR2_WT1		0x10	/* WT region 1 */
605#define	CCR2_WPR1		0x10	/* Write-protect region 1 */
606#define	CCR2_BARB		0x20	/* Flushes write-back cache when entering
607								   hold state. */
608#define	CCR2_BWRT		0x40	/* Enables burst write cycles */
609#define	CCR2_USE_SUSP	0x80	/* Enables suspend pins */
610
611#define	CCR3			0xc3
612#define	CCR3_SMILOCK	0x01	/* SMM register lock */
613#define	CCR3_NMI		0x02	/* Enables NMI during SMM */
614#define	CCR3_LINBRST	0x04	/* Linear address burst cycles */
615#define	CCR3_SMMMODE	0x08	/* SMM Mode */
616#define	CCR3_MAPEN0		0x10	/* Enables Map0 */
617#define	CCR3_MAPEN1		0x20	/* Enables Map1 */
618#define	CCR3_MAPEN2		0x40	/* Enables Map2 */
619#define	CCR3_MAPEN3		0x80	/* Enables Map3 */
620
621#define	CCR4			0xe8
622#define	CCR4_IOMASK		0x07
623#define	CCR4_MEM		0x08	/* Enables momory bypassing */
624#define	CCR4_DTE		0x10	/* Enables directory table entry cache */
625#define	CCR4_FASTFPE	0x20	/* Fast FPU exception */
626#define	CCR4_CPUID		0x80	/* Enables CPUID instruction */
627
628#define	CCR5			0xe9
629#define	CCR5_WT_ALLOC	0x01	/* Write-through allocate */
630#define	CCR5_SLOP		0x02	/* LOOP instruction slowed down */
631#define	CCR5_LBR1		0x10	/* Local bus region 1 */
632#define	CCR5_ARREN		0x20	/* Enables ARR region */
633
634#define	CCR6			0xea
635
636#define	CCR7			0xeb
637
638/* Performance Control Register (5x86 only). */
639#define	PCR0			0x20
640#define	PCR0_RSTK		0x01	/* Enables return stack */
641#define	PCR0_BTB		0x02	/* Enables branch target buffer */
642#define	PCR0_LOOP		0x04	/* Enables loop */
643#define	PCR0_AIS		0x08	/* Enables all instrcutions stalled to
644								   serialize pipe. */
645#define	PCR0_MLR		0x10	/* Enables reordering of misaligned loads */
646#define	PCR0_BTBRT		0x40	/* Enables BTB test register. */
647#define	PCR0_LSSER		0x80	/* Disable reorder */
648
649/* Device Identification Registers */
650#define	DIR0			0xfe
651#define	DIR1			0xff
652
653/*
654 * Machine Check register constants.
655 */
656#define	MCG_CAP_COUNT		0x000000ff
657#define	MCG_CAP_CTL_P		0x00000100
658#define	MCG_CAP_EXT_P		0x00000200
659#define	MCG_CAP_CMCI_P		0x00000400
660#define	MCG_CAP_TES_P		0x00000800
661#define	MCG_CAP_EXT_CNT		0x00ff0000
662#define	MCG_CAP_SER_P		0x01000000
663#define	MCG_STATUS_RIPV		0x00000001
664#define	MCG_STATUS_EIPV		0x00000002
665#define	MCG_STATUS_MCIP		0x00000004
666#define	MCG_CTL_ENABLE		0xffffffffffffffff
667#define	MCG_CTL_DISABLE		0x0000000000000000
668#define	MSR_MC_CTL(x)		(MSR_MC0_CTL + (x) * 4)
669#define	MSR_MC_STATUS(x)	(MSR_MC0_STATUS + (x) * 4)
670#define	MSR_MC_ADDR(x)		(MSR_MC0_ADDR + (x) * 4)
671#define	MSR_MC_MISC(x)		(MSR_MC0_MISC + (x) * 4)
672#define	MSR_MC_CTL2(x)		(MSR_MC0_CTL2 + (x))	/* If MCG_CAP_CMCI_P */
673#define	MC_STATUS_MCA_ERROR	0x000000000000ffff
674#define	MC_STATUS_MODEL_ERROR	0x00000000ffff0000
675#define	MC_STATUS_OTHER_INFO	0x01ffffff00000000
676#define	MC_STATUS_COR_COUNT	0x001fffc000000000	/* If MCG_CAP_CMCI_P */
677#define	MC_STATUS_TES_STATUS	0x0060000000000000	/* If MCG_CAP_TES_P */
678#define	MC_STATUS_AR		0x0080000000000000	/* If MCG_CAP_TES_P */
679#define	MC_STATUS_S		0x0100000000000000	/* If MCG_CAP_TES_P */
680#define	MC_STATUS_PCC		0x0200000000000000
681#define	MC_STATUS_ADDRV		0x0400000000000000
682#define	MC_STATUS_MISCV		0x0800000000000000
683#define	MC_STATUS_EN		0x1000000000000000
684#define	MC_STATUS_UC		0x2000000000000000
685#define	MC_STATUS_OVER		0x4000000000000000
686#define	MC_STATUS_VAL		0x8000000000000000
687#define	MC_MISC_RA_LSB		0x000000000000003f	/* If MCG_CAP_SER_P */
688#define	MC_MISC_ADDRESS_MODE	0x00000000000001c0	/* If MCG_CAP_SER_P */
689#define	MC_CTL2_THRESHOLD	0x0000000000007fff
690#define	MC_CTL2_CMCI_EN		0x0000000040000000
691
692/*
693 * The following four 3-byte registers control the non-cacheable regions.
694 * These registers must be written as three separate bytes.
695 *
696 * NCRx+0: A31-A24 of starting address
697 * NCRx+1: A23-A16 of starting address
698 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
699 *
700 * The non-cacheable region's starting address must be aligned to the
701 * size indicated by the NCR_SIZE_xx field.
702 */
703#define	NCR1	0xc4
704#define	NCR2	0xc7
705#define	NCR3	0xca
706#define	NCR4	0xcd
707
708#define	NCR_SIZE_0K	0
709#define	NCR_SIZE_4K	1
710#define	NCR_SIZE_8K	2
711#define	NCR_SIZE_16K	3
712#define	NCR_SIZE_32K	4
713#define	NCR_SIZE_64K	5
714#define	NCR_SIZE_128K	6
715#define	NCR_SIZE_256K	7
716#define	NCR_SIZE_512K	8
717#define	NCR_SIZE_1M	9
718#define	NCR_SIZE_2M	10
719#define	NCR_SIZE_4M	11
720#define	NCR_SIZE_8M	12
721#define	NCR_SIZE_16M	13
722#define	NCR_SIZE_32M	14
723#define	NCR_SIZE_4G	15
724
725/*
726 * The address region registers are used to specify the location and
727 * size for the eight address regions.
728 *
729 * ARRx + 0: A31-A24 of start address
730 * ARRx + 1: A23-A16 of start address
731 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
732 */
733#define	ARR0	0xc4
734#define	ARR1	0xc7
735#define	ARR2	0xca
736#define	ARR3	0xcd
737#define	ARR4	0xd0
738#define	ARR5	0xd3
739#define	ARR6	0xd6
740#define	ARR7	0xd9
741
742#define	ARR_SIZE_0K		0
743#define	ARR_SIZE_4K		1
744#define	ARR_SIZE_8K		2
745#define	ARR_SIZE_16K	3
746#define	ARR_SIZE_32K	4
747#define	ARR_SIZE_64K	5
748#define	ARR_SIZE_128K	6
749#define	ARR_SIZE_256K	7
750#define	ARR_SIZE_512K	8
751#define	ARR_SIZE_1M		9
752#define	ARR_SIZE_2M		10
753#define	ARR_SIZE_4M		11
754#define	ARR_SIZE_8M		12
755#define	ARR_SIZE_16M	13
756#define	ARR_SIZE_32M	14
757#define	ARR_SIZE_4G		15
758
759/*
760 * The region control registers specify the attributes associated with
761 * the ARRx addres regions.
762 */
763#define	RCR0	0xdc
764#define	RCR1	0xdd
765#define	RCR2	0xde
766#define	RCR3	0xdf
767#define	RCR4	0xe0
768#define	RCR5	0xe1
769#define	RCR6	0xe2
770#define	RCR7	0xe3
771
772#define	RCR_RCD	0x01	/* Disables caching for ARRx (x = 0-6). */
773#define	RCR_RCE	0x01	/* Enables caching for ARR7. */
774#define	RCR_WWO	0x02	/* Weak write ordering. */
775#define	RCR_WL	0x04	/* Weak locking. */
776#define	RCR_WG	0x08	/* Write gathering. */
777#define	RCR_WT	0x10	/* Write-through. */
778#define	RCR_NLB	0x20	/* LBA# pin is not asserted. */
779
780/* AMD Write Allocate Top-Of-Memory and Control Register */
781#define	AMD_WT_ALLOC_TME	0x40000	/* top-of-memory enable */
782#define	AMD_WT_ALLOC_PRE	0x20000	/* programmable range enable */
783#define	AMD_WT_ALLOC_FRE	0x10000	/* fixed (A0000-FFFFF) range enable */
784
785/* AMD64 MSR's */
786#define	MSR_EFER	0xc0000080	/* extended features */
787#define	MSR_STAR	0xc0000081	/* legacy mode SYSCALL target/cs/ss */
788#define	MSR_LSTAR	0xc0000082	/* long mode SYSCALL target rip */
789#define	MSR_CSTAR	0xc0000083	/* compat mode SYSCALL target rip */
790#define	MSR_SF_MASK	0xc0000084	/* syscall flags mask */
791#define	MSR_FSBASE	0xc0000100	/* base address of the %fs "segment" */
792#define	MSR_GSBASE	0xc0000101	/* base address of the %gs "segment" */
793#define	MSR_KGSBASE	0xc0000102	/* base address of the kernel %gs */
794#define	MSR_PERFEVSEL0	0xc0010000
795#define	MSR_PERFEVSEL1	0xc0010001
796#define	MSR_PERFEVSEL2	0xc0010002
797#define	MSR_PERFEVSEL3	0xc0010003
798#define	MSR_K7_PERFCTR0	0xc0010004
799#define	MSR_K7_PERFCTR1	0xc0010005
800#define	MSR_K7_PERFCTR2	0xc0010006
801#define	MSR_K7_PERFCTR3	0xc0010007
802#define	MSR_SYSCFG	0xc0010010
803#define	MSR_HWCR	0xc0010015
804#define	MSR_IORRBASE0	0xc0010016
805#define	MSR_IORRMASK0	0xc0010017
806#define	MSR_IORRBASE1	0xc0010018
807#define	MSR_IORRMASK1	0xc0010019
808#define	MSR_TOP_MEM	0xc001001a	/* boundary for ram below 4G */
809#define	MSR_TOP_MEM2	0xc001001d	/* boundary for ram above 4G */
810#define	MSR_NB_CFG1	0xc001001f	/* NB configuration 1 */
811#define	MSR_P_STATE_LIMIT 0xc0010061	/* P-state Current Limit Register */
812#define	MSR_P_STATE_CONTROL 0xc0010062	/* P-state Control Register */
813#define	MSR_P_STATE_STATUS 0xc0010063	/* P-state Status Register */
814#define	MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */
815#define	MSR_SMM_ADDR	0xc0010112	/* SMM TSEG base address */
816#define	MSR_SMM_MASK	0xc0010113	/* SMM TSEG address mask */
817#define	MSR_IC_CFG	0xc0011021	/* Instruction Cache Configuration */
818#define	MSR_K8_UCODE_UPDATE	0xc0010020	/* update microcode */
819#define	MSR_MC0_CTL_MASK	0xc0010044
820#define	MSR_VM_CR		0xc0010114 /* SVM: feature control */
821#define	MSR_VM_HSAVE_PA		0xc0010117 /* SVM: host save area address */
822
823/* MSR_VM_CR related */
824#define	VM_CR_SVMDIS		0x10	/* SVM: disabled by BIOS */
825
826/* VIA ACE crypto featureset: for via_feature_rng */
827#define	VIA_HAS_RNG		1	/* cpu has RNG */
828
829/* VIA ACE crypto featureset: for via_feature_xcrypt */
830#define	VIA_HAS_AES		1	/* cpu has AES */
831#define	VIA_HAS_SHA		2	/* cpu has SHA1 & SHA256 */
832#define	VIA_HAS_MM		4	/* cpu has RSA instructions */
833#define	VIA_HAS_AESCTR		8	/* cpu has AES-CTR instructions */
834
835/* Centaur Extended Feature flags */
836#define	VIA_CPUID_HAS_RNG	0x000004
837#define	VIA_CPUID_DO_RNG	0x000008
838#define	VIA_CPUID_HAS_ACE	0x000040
839#define	VIA_CPUID_DO_ACE	0x000080
840#define	VIA_CPUID_HAS_ACE2	0x000100
841#define	VIA_CPUID_DO_ACE2	0x000200
842#define	VIA_CPUID_HAS_PHE	0x000400
843#define	VIA_CPUID_DO_PHE	0x000800
844#define	VIA_CPUID_HAS_PMM	0x001000
845#define	VIA_CPUID_DO_PMM	0x002000
846
847/* VIA ACE xcrypt-* instruction context control options */
848#define	VIA_CRYPT_CWLO_ROUND_M		0x0000000f
849#define	VIA_CRYPT_CWLO_ALG_M		0x00000070
850#define	VIA_CRYPT_CWLO_ALG_AES		0x00000000
851#define	VIA_CRYPT_CWLO_KEYGEN_M		0x00000080
852#define	VIA_CRYPT_CWLO_KEYGEN_HW	0x00000000
853#define	VIA_CRYPT_CWLO_KEYGEN_SW	0x00000080
854#define	VIA_CRYPT_CWLO_NORMAL		0x00000000
855#define	VIA_CRYPT_CWLO_INTERMEDIATE	0x00000100
856#define	VIA_CRYPT_CWLO_ENCRYPT		0x00000000
857#define	VIA_CRYPT_CWLO_DECRYPT		0x00000200
858#define	VIA_CRYPT_CWLO_KEY128		0x0000000a	/* 128bit, 10 rds */
859#define	VIA_CRYPT_CWLO_KEY192		0x0000040c	/* 192bit, 12 rds */
860#define	VIA_CRYPT_CWLO_KEY256		0x0000080e	/* 256bit, 15 rds */
861
862#endif /* !_MACHINE_SPECIALREG_H_ */
863