1*199767f8SToomas Soome /*- 2*199767f8SToomas Soome * Copyright (c) 1991 The Regents of the University of California. 3*199767f8SToomas Soome * All rights reserved. 4*199767f8SToomas Soome * 5*199767f8SToomas Soome * Redistribution and use in source and binary forms, with or without 6*199767f8SToomas Soome * modification, are permitted provided that the following conditions 7*199767f8SToomas Soome * are met: 8*199767f8SToomas Soome * 1. Redistributions of source code must retain the above copyright 9*199767f8SToomas Soome * notice, this list of conditions and the following disclaimer. 10*199767f8SToomas Soome * 2. Redistributions in binary form must reproduce the above copyright 11*199767f8SToomas Soome * notice, this list of conditions and the following disclaimer in the 12*199767f8SToomas Soome * documentation and/or other materials provided with the distribution. 13*199767f8SToomas Soome * 4. Neither the name of the University nor the names of its contributors 14*199767f8SToomas Soome * may be used to endorse or promote products derived from this software 15*199767f8SToomas Soome * without specific prior written permission. 16*199767f8SToomas Soome * 17*199767f8SToomas Soome * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18*199767f8SToomas Soome * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19*199767f8SToomas Soome * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20*199767f8SToomas Soome * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21*199767f8SToomas Soome * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22*199767f8SToomas Soome * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23*199767f8SToomas Soome * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24*199767f8SToomas Soome * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25*199767f8SToomas Soome * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26*199767f8SToomas Soome * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27*199767f8SToomas Soome * SUCH DAMAGE. 28*199767f8SToomas Soome * 29*199767f8SToomas Soome * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 30*199767f8SToomas Soome * $FreeBSD$ 31*199767f8SToomas Soome */ 32*199767f8SToomas Soome 33*199767f8SToomas Soome /* 34*199767f8SToomas Soome * NS8250... UART registers. 35*199767f8SToomas Soome */ 36*199767f8SToomas Soome 37*199767f8SToomas Soome /* 8250 registers #[0-6]. */ 38*199767f8SToomas Soome 39*199767f8SToomas Soome #define com_data 0 /* data register (R/W) */ 40*199767f8SToomas Soome #define REG_DATA com_data 41*199767f8SToomas Soome 42*199767f8SToomas Soome #define com_ier 1 /* interrupt enable register (W) */ 43*199767f8SToomas Soome #define REG_IER com_ier 44*199767f8SToomas Soome #define IER_ERXRDY 0x1 45*199767f8SToomas Soome #define IER_ETXRDY 0x2 46*199767f8SToomas Soome #define IER_ERLS 0x4 47*199767f8SToomas Soome #define IER_EMSC 0x8 48*199767f8SToomas Soome 49*199767f8SToomas Soome #define IER_BITS "\20\1ERXRDY\2ETXRDY\3ERLS\4EMSC" 50*199767f8SToomas Soome 51*199767f8SToomas Soome #define com_iir 2 /* interrupt identification register (R) */ 52*199767f8SToomas Soome #define REG_IIR com_iir 53*199767f8SToomas Soome #define IIR_IMASK 0xf 54*199767f8SToomas Soome #define IIR_RXTOUT 0xc 55*199767f8SToomas Soome #define IIR_BUSY 0x7 56*199767f8SToomas Soome #define IIR_RLS 0x6 57*199767f8SToomas Soome #define IIR_RXRDY 0x4 58*199767f8SToomas Soome #define IIR_TXRDY 0x2 59*199767f8SToomas Soome #define IIR_NOPEND 0x1 60*199767f8SToomas Soome #define IIR_MLSC 0x0 61*199767f8SToomas Soome #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 62*199767f8SToomas Soome 63*199767f8SToomas Soome #define IIR_BITS "\20\1NOPEND\2TXRDY\3RXRDY" 64*199767f8SToomas Soome 65*199767f8SToomas Soome #define com_lcr 3 /* line control register (R/W) */ 66*199767f8SToomas Soome #define com_cfcr com_lcr /* character format control register (R/W) */ 67*199767f8SToomas Soome #define REG_LCR com_lcr 68*199767f8SToomas Soome #define LCR_DLAB 0x80 69*199767f8SToomas Soome #define CFCR_DLAB LCR_DLAB 70*199767f8SToomas Soome #define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ 71*199767f8SToomas Soome #define CFCR_EFR_ENABLE LCR_EFR_ENABLE 72*199767f8SToomas Soome #define LCR_SBREAK 0x40 73*199767f8SToomas Soome #define CFCR_SBREAK LCR_SBREAK 74*199767f8SToomas Soome #define LCR_PZERO 0x30 75*199767f8SToomas Soome #define CFCR_PZERO LCR_PZERO 76*199767f8SToomas Soome #define LCR_PONE 0x20 77*199767f8SToomas Soome #define CFCR_PONE LCR_PONE 78*199767f8SToomas Soome #define LCR_PEVEN 0x10 79*199767f8SToomas Soome #define CFCR_PEVEN LCR_PEVEN 80*199767f8SToomas Soome #define LCR_PODD 0x00 81*199767f8SToomas Soome #define CFCR_PODD LCR_PODD 82*199767f8SToomas Soome #define LCR_PENAB 0x08 83*199767f8SToomas Soome #define CFCR_PENAB LCR_PENAB 84*199767f8SToomas Soome #define LCR_STOPB 0x04 85*199767f8SToomas Soome #define CFCR_STOPB LCR_STOPB 86*199767f8SToomas Soome #define LCR_8BITS 0x03 87*199767f8SToomas Soome #define CFCR_8BITS LCR_8BITS 88*199767f8SToomas Soome #define LCR_7BITS 0x02 89*199767f8SToomas Soome #define CFCR_7BITS LCR_7BITS 90*199767f8SToomas Soome #define LCR_6BITS 0x01 91*199767f8SToomas Soome #define CFCR_6BITS LCR_6BITS 92*199767f8SToomas Soome #define LCR_5BITS 0x00 93*199767f8SToomas Soome #define CFCR_5BITS LCR_5BITS 94*199767f8SToomas Soome 95*199767f8SToomas Soome #define com_mcr 4 /* modem control register (R/W) */ 96*199767f8SToomas Soome #define REG_MCR com_mcr 97*199767f8SToomas Soome #define MCR_PRESCALE 0x80 /* only available on 16650 up */ 98*199767f8SToomas Soome #define MCR_LOOPBACK 0x10 99*199767f8SToomas Soome #define MCR_IE 0x08 100*199767f8SToomas Soome #define MCR_IENABLE MCR_IE 101*199767f8SToomas Soome #define MCR_DRS 0x04 102*199767f8SToomas Soome #define MCR_RTS 0x02 103*199767f8SToomas Soome #define MCR_DTR 0x01 104*199767f8SToomas Soome 105*199767f8SToomas Soome #define MCR_BITS "\20\1DTR\2RTS\3DRS\4IE\5LOOPBACK\10PRESCALE" 106*199767f8SToomas Soome 107*199767f8SToomas Soome #define com_lsr 5 /* line status register (R/W) */ 108*199767f8SToomas Soome #define REG_LSR com_lsr 109*199767f8SToomas Soome #define LSR_RCV_FIFO 0x80 110*199767f8SToomas Soome #define LSR_TEMT 0x40 111*199767f8SToomas Soome #define LSR_TSRE LSR_TEMT 112*199767f8SToomas Soome #define LSR_THRE 0x20 113*199767f8SToomas Soome #define LSR_TXRDY LSR_THRE 114*199767f8SToomas Soome #define LSR_BI 0x10 115*199767f8SToomas Soome #define LSR_FE 0x08 116*199767f8SToomas Soome #define LSR_PE 0x04 117*199767f8SToomas Soome #define LSR_OE 0x02 118*199767f8SToomas Soome #define LSR_RXRDY 0x01 119*199767f8SToomas Soome #define LSR_RCV_MASK 0x1f 120*199767f8SToomas Soome 121*199767f8SToomas Soome #define LSR_BITS "\20\1RXRDY\2OE\3PE\4FE\5BI\6THRE\7TEMT\10RCV_FIFO" 122*199767f8SToomas Soome 123*199767f8SToomas Soome #define com_msr 6 /* modem status register (R/W) */ 124*199767f8SToomas Soome #define REG_MSR com_msr 125*199767f8SToomas Soome #define MSR_DCD 0x80 126*199767f8SToomas Soome #define MSR_RI 0x40 127*199767f8SToomas Soome #define MSR_DSR 0x20 128*199767f8SToomas Soome #define MSR_CTS 0x10 129*199767f8SToomas Soome #define MSR_DDCD 0x08 130*199767f8SToomas Soome #define MSR_TERI 0x04 131*199767f8SToomas Soome #define MSR_DDSR 0x02 132*199767f8SToomas Soome #define MSR_DCTS 0x01 133*199767f8SToomas Soome 134*199767f8SToomas Soome #define MSR_BITS "\20\1DCTS\2DDSR\3TERI\4DDCD\5CTS\6DSR\7RI\10DCD" 135*199767f8SToomas Soome 136*199767f8SToomas Soome /* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */ 137*199767f8SToomas Soome #define com_dll 0 /* divisor latch low (R/W) */ 138*199767f8SToomas Soome #define com_dlbl com_dll 139*199767f8SToomas Soome #define com_dlm 1 /* divisor latch high (R/W) */ 140*199767f8SToomas Soome #define com_dlbh com_dlm 141*199767f8SToomas Soome #define REG_DLL com_dll 142*199767f8SToomas Soome #define REG_DLH com_dlm 143*199767f8SToomas Soome 144*199767f8SToomas Soome /* 16450 register #7. Not multiplexed. */ 145*199767f8SToomas Soome #define com_scr 7 /* scratch register (R/W) */ 146*199767f8SToomas Soome 147*199767f8SToomas Soome /* 16550 register #2. Not multiplexed. */ 148*199767f8SToomas Soome #define com_fcr 2 /* FIFO control register (W) */ 149*199767f8SToomas Soome #define com_fifo com_fcr 150*199767f8SToomas Soome #define REG_FCR com_fcr 151*199767f8SToomas Soome #define FCR_ENABLE 0x01 152*199767f8SToomas Soome #define FIFO_ENABLE FCR_ENABLE 153*199767f8SToomas Soome #define FCR_RCV_RST 0x02 154*199767f8SToomas Soome #define FIFO_RCV_RST FCR_RCV_RST 155*199767f8SToomas Soome #define FCR_XMT_RST 0x04 156*199767f8SToomas Soome #define FIFO_XMT_RST FCR_XMT_RST 157*199767f8SToomas Soome #define FCR_DMA 0x08 158*199767f8SToomas Soome #define FIFO_DMA_MODE FCR_DMA 159*199767f8SToomas Soome #define FCR_RX_LOW 0x00 160*199767f8SToomas Soome #define FIFO_RX_LOW FCR_RX_LOW 161*199767f8SToomas Soome #define FCR_RX_MEDL 0x40 162*199767f8SToomas Soome #define FIFO_RX_MEDL FCR_RX_MEDL 163*199767f8SToomas Soome #define FCR_RX_MEDH 0x80 164*199767f8SToomas Soome #define FIFO_RX_MEDH FCR_RX_MEDH 165*199767f8SToomas Soome #define FCR_RX_HIGH 0xc0 166*199767f8SToomas Soome #define FIFO_RX_HIGH FCR_RX_HIGH 167*199767f8SToomas Soome 168*199767f8SToomas Soome #define FCR_BITS "\20\1ENABLE\2RCV_RST\3XMT_RST\4DMA" 169*199767f8SToomas Soome 170*199767f8SToomas Soome /* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */ 171*199767f8SToomas Soome 172*199767f8SToomas Soome #define com_efr 2 /* enhanced features register (R/W) */ 173*199767f8SToomas Soome #define REG_EFR com_efr 174*199767f8SToomas Soome #define EFR_CTS 0x80 175*199767f8SToomas Soome #define EFR_AUTOCTS EFR_CTS 176*199767f8SToomas Soome #define EFR_RTS 0x40 177*199767f8SToomas Soome #define EFR_AUTORTS EFR_RTS 178*199767f8SToomas Soome #define EFR_EFE 0x10 /* enhanced functions enable */ 179*199767f8SToomas Soome 180*199767f8SToomas Soome #define com_xon1 4 /* XON 1 character (R/W) */ 181*199767f8SToomas Soome #define com_xon2 5 /* XON 2 character (R/W) */ 182*199767f8SToomas Soome #define com_xoff1 6 /* XOFF 1 character (R/W) */ 183*199767f8SToomas Soome #define com_xoff2 7 /* XOFF 2 character (R/W) */ 184*199767f8SToomas Soome 185*199767f8SToomas Soome #define DW_REG_USR 31 /* DesignWare derived Uart Status Reg */ 186*199767f8SToomas Soome #define com_usr 39 /* Octeon 16750/16550 Uart Status Reg */ 187*199767f8SToomas Soome #define REG_USR com_usr 188*199767f8SToomas Soome #define USR_BUSY 1 /* Uart Busy. Serial transfer in progress */ 189*199767f8SToomas Soome #define USR_TXFIFO_NOTFULL 2 /* Uart TX FIFO Not full */ 190*199767f8SToomas Soome 191*199767f8SToomas Soome /* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */ 192*199767f8SToomas Soome #define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */ 193*199767f8SToomas Soome 194*199767f8SToomas Soome /* 16950 register #3. R/W access enabled by ACR[7]. */ 195*199767f8SToomas Soome #define com_rfl 3 /* receiver fifo level (R) */ 196*199767f8SToomas Soome 197*199767f8SToomas Soome /* 198*199767f8SToomas Soome * 16950 register #4. Access enabled by ACR[7]. Also requires 199*199767f8SToomas Soome * !LCR_EFR_ENABLE. 200*199767f8SToomas Soome */ 201*199767f8SToomas Soome #define com_tfl 4 /* transmitter fifo level (R) */ 202*199767f8SToomas Soome 203*199767f8SToomas Soome /* 204*199767f8SToomas Soome * 16950 register #5. Accessible if !LCR_EFR_ENABLE. Read access also 205*199767f8SToomas Soome * requires ACR[6]. 206*199767f8SToomas Soome */ 207*199767f8SToomas Soome #define com_icr 5 /* index control register (R/W) */ 208*199767f8SToomas Soome 209*199767f8SToomas Soome /* 210*199767f8SToomas Soome * 16950 register #7. It is the same as com_scr except it has a different 211*199767f8SToomas Soome * abbreviation in the manufacturer's data sheet and it also serves as an 212*199767f8SToomas Soome * index into the Indexed Control register set. 213*199767f8SToomas Soome */ 214*199767f8SToomas Soome #define com_spr com_scr /* scratch pad (and index) register (R/W) */ 215*199767f8SToomas Soome #define REG_SPR com_scr 216*199767f8SToomas Soome 217*199767f8SToomas Soome /* 218*199767f8SToomas Soome * 16950 indexed control registers #[0-0x13]. Access is via index in SPR, 219*199767f8SToomas Soome * data in ICR (if ICR is accessible). 220*199767f8SToomas Soome */ 221*199767f8SToomas Soome 222*199767f8SToomas Soome #define com_acr 0 /* additional control register (R/W) */ 223*199767f8SToomas Soome #define ACR_ASE 0x80 /* ASR/RFL/TFL enable */ 224*199767f8SToomas Soome #define ACR_ICRE 0x40 /* ICR enable */ 225*199767f8SToomas Soome #define ACR_TLE 0x20 /* TTL/RTL enable */ 226*199767f8SToomas Soome 227*199767f8SToomas Soome #define com_cpr 1 /* clock prescaler register (R/W) */ 228*199767f8SToomas Soome #define com_tcr 2 /* times clock register (R/W) */ 229*199767f8SToomas Soome #define com_ttl 4 /* transmitter trigger level (R/W) */ 230*199767f8SToomas Soome #define com_rtl 5 /* receiver trigger level (R/W) */ 231*199767f8SToomas Soome /* ... */ 232*199767f8SToomas Soome 233*199767f8SToomas Soome /* Hardware extension mode register for RSB-2000/3000. */ 234*199767f8SToomas Soome #define com_emr com_msr 235*199767f8SToomas Soome #define EMR_EXBUFF 0x04 236*199767f8SToomas Soome #define EMR_CTSFLW 0x08 237*199767f8SToomas Soome #define EMR_DSRFLW 0x10 238*199767f8SToomas Soome #define EMR_RTSFLW 0x20 239*199767f8SToomas Soome #define EMR_DTRFLW 0x40 240*199767f8SToomas Soome #define EMR_EFMODE 0x80 241