1829150b0SGordon Ross
2829150b0SGordon Ross /*
3829150b0SGordon Ross * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
4829150b0SGordon Ross * Use is subject to license terms.
5829150b0SGordon Ross */
6829150b0SGordon Ross /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
7829150b0SGordon Ross /*
8829150b0SGordon Ross * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
9829150b0SGordon Ross *
10829150b0SGordon Ross * The Weather Channel (TM) funded Tungsten Graphics to develop the
11829150b0SGordon Ross * initial release of the Radeon 8500 driver under the XFree86 license.
12829150b0SGordon Ross * This notice must be preserved.
13829150b0SGordon Ross *
14829150b0SGordon Ross * Permission is hereby granted, free of charge, to any person obtaining a
15829150b0SGordon Ross * copy of this software and associated documentation files (the "Software"),
16829150b0SGordon Ross * to deal in the Software without restriction, including without limitation
17829150b0SGordon Ross * the rights to use, copy, modify, merge, publish, distribute, sublicense,
18829150b0SGordon Ross * and/or sell copies of the Software, and to permit persons to whom the
19829150b0SGordon Ross * Software is furnished to do so, subject to the following conditions:
20829150b0SGordon Ross *
21829150b0SGordon Ross * The above copyright notice and this permission notice (including the next
22829150b0SGordon Ross * paragraph) shall be included in all copies or substantial portions of the
23829150b0SGordon Ross * Software.
24829150b0SGordon Ross *
25829150b0SGordon Ross * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
26829150b0SGordon Ross * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
27829150b0SGordon Ross * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
28829150b0SGordon Ross * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
29829150b0SGordon Ross * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
30829150b0SGordon Ross * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
31829150b0SGordon Ross * DEALINGS IN THE SOFTWARE.
32829150b0SGordon Ross *
33829150b0SGordon Ross * Authors:
34829150b0SGordon Ross * Keith Whitwell <keith@tungstengraphics.com>
35829150b0SGordon Ross * Michel D�zer <michel@daenzer.net>
36829150b0SGordon Ross */
37829150b0SGordon Ross
38829150b0SGordon Ross #include "drmP.h"
39829150b0SGordon Ross #include "radeon_drm.h"
40829150b0SGordon Ross #include "radeon_drv.h"
41829150b0SGordon Ross #include "radeon_io32.h"
42829150b0SGordon Ross
43829150b0SGordon Ross static inline u32
radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv,u32 mask)44829150b0SGordon Ross radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 mask)
45829150b0SGordon Ross {
46829150b0SGordon Ross uint32_t irqs = RADEON_READ(RADEON_GEN_INT_STATUS) & mask;
47829150b0SGordon Ross if (irqs)
48829150b0SGordon Ross RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
49829150b0SGordon Ross return (irqs);
50829150b0SGordon Ross }
51829150b0SGordon Ross
52829150b0SGordon Ross /*
53829150b0SGordon Ross * Interrupts - Used for device synchronization and flushing in the
54829150b0SGordon Ross * following circumstances:
55829150b0SGordon Ross *
56829150b0SGordon Ross * - Exclusive FB access with hw idle:
57829150b0SGordon Ross * - Wait for GUI Idle (?) interrupt, then do normal flush.
58829150b0SGordon Ross *
59829150b0SGordon Ross * - Frame throttling, NV_fence:
60829150b0SGordon Ross * - Drop marker irq's into command stream ahead of time.
61829150b0SGordon Ross * - Wait on irq's with lock *not held*
62829150b0SGordon Ross * - Check each for termination condition
63829150b0SGordon Ross *
64829150b0SGordon Ross * - Internally in cp_getbuffer, etc:
65829150b0SGordon Ross * - as above, but wait with lock held???
66829150b0SGordon Ross *
67829150b0SGordon Ross * NOTE: These functions are misleadingly named -- the irq's aren't
68829150b0SGordon Ross * tied to dma at all, this is just a hangover from dri prehistory.
69829150b0SGordon Ross */
70829150b0SGordon Ross
71829150b0SGordon Ross irqreturn_t
radeon_driver_irq_handler(DRM_IRQ_ARGS)72829150b0SGordon Ross radeon_driver_irq_handler(DRM_IRQ_ARGS)
73829150b0SGordon Ross {
74829150b0SGordon Ross drm_device_t *dev = (drm_device_t *)(uintptr_t)arg;
75829150b0SGordon Ross drm_radeon_private_t *dev_priv =
76829150b0SGordon Ross (drm_radeon_private_t *)dev->dev_private;
77829150b0SGordon Ross u32 stat;
78829150b0SGordon Ross
79829150b0SGordon Ross /*
80829150b0SGordon Ross * Only consider the bits we're interested in - others could be used
81829150b0SGordon Ross * outside the DRM
82829150b0SGordon Ross */
83829150b0SGordon Ross stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
84829150b0SGordon Ross RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT));
85829150b0SGordon Ross if (!stat)
86829150b0SGordon Ross return (IRQ_NONE);
87829150b0SGordon Ross
88829150b0SGordon Ross stat &= dev_priv->irq_enable_reg;
89829150b0SGordon Ross
90829150b0SGordon Ross /* SW interrupt */
91829150b0SGordon Ross if (stat & RADEON_SW_INT_TEST) {
92829150b0SGordon Ross DRM_WAKEUP(&dev_priv->swi_queue);
93829150b0SGordon Ross }
94829150b0SGordon Ross
95829150b0SGordon Ross /* VBLANK interrupt */
96829150b0SGordon Ross if (stat & (RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT)) {
97829150b0SGordon Ross int vblank_crtc = dev_priv->vblank_crtc;
98829150b0SGordon Ross
99829150b0SGordon Ross if ((vblank_crtc &
100829150b0SGordon Ross (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) ==
101829150b0SGordon Ross (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
102829150b0SGordon Ross if (stat & RADEON_CRTC_VBLANK_STAT)
103829150b0SGordon Ross atomic_inc(&dev->vbl_received);
104829150b0SGordon Ross if (stat & RADEON_CRTC2_VBLANK_STAT)
105829150b0SGordon Ross atomic_inc(&dev->vbl_received2);
106829150b0SGordon Ross } else if (((stat & RADEON_CRTC_VBLANK_STAT) &&
107829150b0SGordon Ross (vblank_crtc & DRM_RADEON_VBLANK_CRTC1)) ||
108829150b0SGordon Ross ((stat & RADEON_CRTC2_VBLANK_STAT) &&
109829150b0SGordon Ross (vblank_crtc & DRM_RADEON_VBLANK_CRTC2)))
110829150b0SGordon Ross atomic_inc(&dev->vbl_received);
111829150b0SGordon Ross
112829150b0SGordon Ross DRM_WAKEUP(&dev->vbl_queue);
113829150b0SGordon Ross drm_vbl_send_signals(dev);
114829150b0SGordon Ross }
115829150b0SGordon Ross
116829150b0SGordon Ross return (IRQ_HANDLED);
117829150b0SGordon Ross }
118829150b0SGordon Ross
radeon_emit_irq(drm_device_t * dev)119829150b0SGordon Ross static int radeon_emit_irq(drm_device_t *dev)
120829150b0SGordon Ross {
121829150b0SGordon Ross drm_radeon_private_t *dev_priv = dev->dev_private;
122829150b0SGordon Ross unsigned int ret;
123829150b0SGordon Ross RING_LOCALS;
124829150b0SGordon Ross
125829150b0SGordon Ross atomic_inc(&dev_priv->swi_emitted);
126829150b0SGordon Ross ret = atomic_read(&dev_priv->swi_emitted);
127829150b0SGordon Ross
128829150b0SGordon Ross BEGIN_RING(4);
129829150b0SGordon Ross OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
130829150b0SGordon Ross OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
131829150b0SGordon Ross ADVANCE_RING();
132829150b0SGordon Ross COMMIT_RING();
133829150b0SGordon Ross
134829150b0SGordon Ross return (ret);
135829150b0SGordon Ross }
136829150b0SGordon Ross
radeon_wait_irq(drm_device_t * dev,int swi_nr)137829150b0SGordon Ross static int radeon_wait_irq(drm_device_t *dev, int swi_nr)
138829150b0SGordon Ross {
139829150b0SGordon Ross drm_radeon_private_t *dev_priv =
140829150b0SGordon Ross (drm_radeon_private_t *)dev->dev_private;
141829150b0SGordon Ross int ret = 0;
142829150b0SGordon Ross
143829150b0SGordon Ross if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
144829150b0SGordon Ross return (0);
145829150b0SGordon Ross
146829150b0SGordon Ross dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
147829150b0SGordon Ross
148829150b0SGordon Ross DRM_WAIT_ON(ret, &dev_priv->swi_queue, 3 * DRM_HZ,
149829150b0SGordon Ross RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
150829150b0SGordon Ross
151829150b0SGordon Ross return (ret);
152829150b0SGordon Ross }
153829150b0SGordon Ross
radeon_driver_vblank_do_wait(struct drm_device * dev,unsigned int * sequence,int crtc)154829150b0SGordon Ross static int radeon_driver_vblank_do_wait(struct drm_device *dev,
155829150b0SGordon Ross unsigned int *sequence, int crtc)
156829150b0SGordon Ross {
157829150b0SGordon Ross drm_radeon_private_t *dev_priv =
158829150b0SGordon Ross (drm_radeon_private_t *)dev->dev_private;
159829150b0SGordon Ross unsigned int cur_vblank;
160829150b0SGordon Ross int ret = 0;
161829150b0SGordon Ross atomic_t *counter;
162829150b0SGordon Ross if (!dev_priv) {
163829150b0SGordon Ross DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
164829150b0SGordon Ross return (EINVAL);
165829150b0SGordon Ross }
166829150b0SGordon Ross
167829150b0SGordon Ross /*
168829150b0SGordon Ross * I don't know why reset Intr Status Register here,
169829150b0SGordon Ross * it might miss intr. So, I remove the code which
170829150b0SGordon Ross * exists in open source, and changes as follows:
171829150b0SGordon Ross */
172829150b0SGordon Ross
173829150b0SGordon Ross if (crtc == DRM_RADEON_VBLANK_CRTC1) {
174829150b0SGordon Ross counter = &dev->vbl_received;
175829150b0SGordon Ross } else if (crtc == DRM_RADEON_VBLANK_CRTC2) {
176829150b0SGordon Ross counter = &dev->vbl_received2;
177829150b0SGordon Ross } else
178829150b0SGordon Ross return (EINVAL);
179829150b0SGordon Ross
180829150b0SGordon Ross dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
181829150b0SGordon Ross
182829150b0SGordon Ross /*
183829150b0SGordon Ross * Assume that the user has missed the current sequence number
184829150b0SGordon Ross * by about a day rather than she wants to wait for years
185829150b0SGordon Ross * using vertical blanks...
186829150b0SGordon Ross */
187829150b0SGordon Ross DRM_WAIT_ON(ret, &dev->vbl_queue, 3 * DRM_HZ,
188829150b0SGordon Ross (((cur_vblank = atomic_read(counter)) - *sequence) <= (1 << 23)));
189829150b0SGordon Ross
190829150b0SGordon Ross *sequence = cur_vblank;
191829150b0SGordon Ross
192829150b0SGordon Ross return (ret);
193829150b0SGordon Ross }
194829150b0SGordon Ross
195829150b0SGordon Ross int
radeon_driver_vblank_wait(struct drm_device * dev,unsigned int * sequence)196829150b0SGordon Ross radeon_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence)
197829150b0SGordon Ross {
198829150b0SGordon Ross return (radeon_driver_vblank_do_wait(dev, sequence,
199829150b0SGordon Ross DRM_RADEON_VBLANK_CRTC1));
200829150b0SGordon Ross }
201829150b0SGordon Ross
202829150b0SGordon Ross int
radeon_driver_vblank_wait2(struct drm_device * dev,unsigned int * sequence)203829150b0SGordon Ross radeon_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence)
204829150b0SGordon Ross {
205829150b0SGordon Ross return (radeon_driver_vblank_do_wait(dev, sequence,
206829150b0SGordon Ross DRM_RADEON_VBLANK_CRTC2));
207829150b0SGordon Ross }
208829150b0SGordon Ross
209829150b0SGordon Ross /*
210829150b0SGordon Ross * Needs the lock as it touches the ring.
211829150b0SGordon Ross */
212829150b0SGordon Ross /*ARGSUSED*/
213829150b0SGordon Ross int
radeon_irq_emit(DRM_IOCTL_ARGS)214829150b0SGordon Ross radeon_irq_emit(DRM_IOCTL_ARGS)
215829150b0SGordon Ross {
216829150b0SGordon Ross DRM_DEVICE;
217829150b0SGordon Ross drm_radeon_private_t *dev_priv = dev->dev_private;
218829150b0SGordon Ross drm_radeon_irq_emit_t emit;
219829150b0SGordon Ross int result;
220829150b0SGordon Ross
221829150b0SGordon Ross LOCK_TEST_WITH_RETURN(dev, fpriv);
222829150b0SGordon Ross
223829150b0SGordon Ross if (!dev_priv) {
224829150b0SGordon Ross DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
225829150b0SGordon Ross return (EINVAL);
226829150b0SGordon Ross }
227829150b0SGordon Ross
228829150b0SGordon Ross #ifdef _MULTI_DATAMODEL
229829150b0SGordon Ross if (ddi_model_convert_from(mode & FMODELS) == DDI_MODEL_ILP32) {
230829150b0SGordon Ross drm_radeon_irq_emit_32_t emit32;
231829150b0SGordon Ross
232829150b0SGordon Ross DRM_COPYFROM_WITH_RETURN(&emit32, (void *) data,
233829150b0SGordon Ross sizeof (emit32));
234829150b0SGordon Ross emit.irq_seq = (void *)(uintptr_t)(emit32.irq_seq);
235829150b0SGordon Ross } else {
236829150b0SGordon Ross #endif
237829150b0SGordon Ross
238829150b0SGordon Ross DRM_COPYFROM_WITH_RETURN(&emit, (void *) data, sizeof (emit));
239829150b0SGordon Ross #ifdef _MULTI_DATAMODEL
240829150b0SGordon Ross }
241829150b0SGordon Ross #endif
242829150b0SGordon Ross
243829150b0SGordon Ross result = radeon_emit_irq(dev);
244829150b0SGordon Ross
245829150b0SGordon Ross if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof (int))) {
246829150b0SGordon Ross DRM_ERROR("copy_to_user\n");
247829150b0SGordon Ross return (EFAULT);
248829150b0SGordon Ross }
249829150b0SGordon Ross
250829150b0SGordon Ross return (0);
251829150b0SGordon Ross }
252829150b0SGordon Ross
253829150b0SGordon Ross /*
254829150b0SGordon Ross * Doesn't need the hardware lock.
255829150b0SGordon Ross */
256829150b0SGordon Ross /*ARGSUSED*/
257829150b0SGordon Ross int
radeon_irq_wait(DRM_IOCTL_ARGS)258829150b0SGordon Ross radeon_irq_wait(DRM_IOCTL_ARGS)
259829150b0SGordon Ross {
260829150b0SGordon Ross DRM_DEVICE;
261829150b0SGordon Ross drm_radeon_private_t *dev_priv = dev->dev_private;
262829150b0SGordon Ross drm_radeon_irq_wait_t irqwait;
263829150b0SGordon Ross
264829150b0SGordon Ross if (!dev_priv) {
265829150b0SGordon Ross DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
266829150b0SGordon Ross return (EINVAL);
267829150b0SGordon Ross }
268829150b0SGordon Ross
269829150b0SGordon Ross DRM_COPYFROM_WITH_RETURN(&irqwait, (void *) data, sizeof (irqwait));
270829150b0SGordon Ross
271829150b0SGordon Ross return (radeon_wait_irq(dev, irqwait.irq_seq));
272829150b0SGordon Ross }
273829150b0SGordon Ross
radeon_enable_interrupt(struct drm_device * dev)274829150b0SGordon Ross static void radeon_enable_interrupt(struct drm_device *dev)
275829150b0SGordon Ross {
276829150b0SGordon Ross drm_radeon_private_t *dev_priv;
277829150b0SGordon Ross
278829150b0SGordon Ross dev_priv = (drm_radeon_private_t *)dev->dev_private;
279829150b0SGordon Ross dev_priv->irq_enable_reg = RADEON_SW_INT_ENABLE;
280829150b0SGordon Ross
281829150b0SGordon Ross if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC1) {
282829150b0SGordon Ross dev_priv->irq_enable_reg |= RADEON_CRTC_VBLANK_MASK;
283829150b0SGordon Ross }
284829150b0SGordon Ross
285829150b0SGordon Ross if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC2) {
286829150b0SGordon Ross dev_priv->irq_enable_reg |= RADEON_CRTC2_VBLANK_MASK;
287829150b0SGordon Ross }
288829150b0SGordon Ross
289829150b0SGordon Ross RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
290829150b0SGordon Ross dev_priv->irq_enabled = 1;
291829150b0SGordon Ross }
292829150b0SGordon Ross
293829150b0SGordon Ross
294829150b0SGordon Ross /*
295829150b0SGordon Ross * drm_dma.h hooks
296829150b0SGordon Ross */
297829150b0SGordon Ross int
radeon_driver_irq_preinstall(drm_device_t * dev)298829150b0SGordon Ross radeon_driver_irq_preinstall(drm_device_t *dev)
299829150b0SGordon Ross {
300829150b0SGordon Ross drm_radeon_private_t *dev_priv =
301829150b0SGordon Ross (drm_radeon_private_t *)dev->dev_private;
302829150b0SGordon Ross
303829150b0SGordon Ross if (!dev_priv->mmio)
304829150b0SGordon Ross return (EINVAL);
305829150b0SGordon Ross
306829150b0SGordon Ross /* Disable *all* interrupts */
307829150b0SGordon Ross RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
308829150b0SGordon Ross
309829150b0SGordon Ross /* Clear bits if they're already high */
310829150b0SGordon Ross (void) radeon_acknowledge_irqs(dev_priv,
311829150b0SGordon Ross (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT |
312829150b0SGordon Ross RADEON_CRTC2_VBLANK_STAT));
313829150b0SGordon Ross
314829150b0SGordon Ross return (0);
315829150b0SGordon Ross }
316829150b0SGordon Ross
317829150b0SGordon Ross void
radeon_driver_irq_postinstall(drm_device_t * dev)318829150b0SGordon Ross radeon_driver_irq_postinstall(drm_device_t *dev)
319829150b0SGordon Ross {
320829150b0SGordon Ross drm_radeon_private_t *dev_priv =
321829150b0SGordon Ross (drm_radeon_private_t *)dev->dev_private;
322829150b0SGordon Ross
323829150b0SGordon Ross atomic_set(&dev_priv->swi_emitted, 0);
324829150b0SGordon Ross DRM_INIT_WAITQUEUE(&dev_priv->swi_queue, DRM_INTR_PRI(dev));
325829150b0SGordon Ross
326829150b0SGordon Ross radeon_enable_interrupt(dev);
327829150b0SGordon Ross }
328829150b0SGordon Ross
329829150b0SGordon Ross void
radeon_driver_irq_uninstall(drm_device_t * dev)330829150b0SGordon Ross radeon_driver_irq_uninstall(drm_device_t *dev)
331829150b0SGordon Ross {
332829150b0SGordon Ross drm_radeon_private_t *dev_priv =
333829150b0SGordon Ross (drm_radeon_private_t *)dev->dev_private;
334829150b0SGordon Ross if (!dev_priv)
335829150b0SGordon Ross return;
336829150b0SGordon Ross
337829150b0SGordon Ross /* Disable *all* interrupts */
338829150b0SGordon Ross RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
339829150b0SGordon Ross DRM_FINI_WAITQUEUE(&dev_priv->swi_queue);
340829150b0SGordon Ross }
341829150b0SGordon Ross
342829150b0SGordon Ross int
radeon_vblank_crtc_get(drm_device_t * dev)343829150b0SGordon Ross radeon_vblank_crtc_get(drm_device_t *dev)
344829150b0SGordon Ross {
345829150b0SGordon Ross drm_radeon_private_t *dev_priv;
346829150b0SGordon Ross u32 flag;
347829150b0SGordon Ross u32 value;
348829150b0SGordon Ross
349829150b0SGordon Ross dev_priv = (drm_radeon_private_t *)dev->dev_private;
350829150b0SGordon Ross flag = RADEON_READ(RADEON_GEN_INT_CNTL);
351829150b0SGordon Ross value = 0;
352829150b0SGordon Ross
353829150b0SGordon Ross if (flag & RADEON_CRTC_VBLANK_MASK)
354829150b0SGordon Ross value |= DRM_RADEON_VBLANK_CRTC1;
355829150b0SGordon Ross
356829150b0SGordon Ross if (flag & RADEON_CRTC2_VBLANK_MASK)
357829150b0SGordon Ross value |= DRM_RADEON_VBLANK_CRTC2;
358829150b0SGordon Ross return (value);
359829150b0SGordon Ross }
360829150b0SGordon Ross
361829150b0SGordon Ross int
radeon_vblank_crtc_set(drm_device_t * dev,int64_t value)362829150b0SGordon Ross radeon_vblank_crtc_set(drm_device_t *dev, int64_t value)
363829150b0SGordon Ross {
364829150b0SGordon Ross drm_radeon_private_t *dev_priv;
365829150b0SGordon Ross
366829150b0SGordon Ross dev_priv = (drm_radeon_private_t *)dev->dev_private;
367829150b0SGordon Ross if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
368829150b0SGordon Ross DRM_ERROR("called with invalid crtc 0x%x\n",
369829150b0SGordon Ross (unsigned int)value);
370829150b0SGordon Ross return (EINVAL);
371829150b0SGordon Ross }
372829150b0SGordon Ross dev_priv->vblank_crtc = (unsigned int)value;
373829150b0SGordon Ross radeon_enable_interrupt(dev);
374829150b0SGordon Ross return (0);
375829150b0SGordon Ross }
376