1/*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 *    must display the following acknowledgement:
20 *	This product includes software developed by the University of
21 *	California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 *    may be used to endorse or promote products derived from this software
24 *    without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 *	from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39 */
40
41#include <sys/cdefs.h>
42__FBSDID("$FreeBSD$");
43
44#include "opt_cpu.h"
45
46#include <sys/param.h>
47#include <sys/bus.h>
48#include <sys/cpu.h>
49#include <sys/eventhandler.h>
50#include <sys/limits.h>
51#include <sys/systm.h>
52#include <sys/kernel.h>
53#include <sys/sysctl.h>
54#include <sys/power.h>
55
56#include <vm/vm.h>
57#include <vm/pmap.h>
58
59#include <machine/asmacros.h>
60#include <machine/clock.h>
61#include <machine/cputypes.h>
62#include <machine/frame.h>
63#include <machine/intr_machdep.h>
64#include <machine/md_var.h>
65#include <machine/segments.h>
66#include <machine/specialreg.h>
67
68#include <amd64/vmm/intel/vmx_controls.h>
69#include <x86/isa/icu.h>
70#include <x86/vmware.h>
71
72#ifdef __i386__
73#define	IDENTBLUE_CYRIX486	0
74#define	IDENTBLUE_IBMCPU	1
75#define	IDENTBLUE_CYRIXM2	2
76
77static void identifycyrix(void);
78static void print_transmeta_info(void);
79#endif
80static u_int find_cpu_vendor_id(void);
81static void print_AMD_info(void);
82static void print_INTEL_info(void);
83static void print_INTEL_TLB(u_int data);
84static void print_hypervisor_info(void);
85static void print_svm_info(void);
86static void print_via_padlock_info(void);
87static void print_vmx_info(void);
88
89#ifdef __i386__
90int	cpu;			/* Are we 386, 386sx, 486, etc? */
91int	cpu_class;
92#endif
93u_int	cpu_feature;		/* Feature flags */
94u_int	cpu_feature2;		/* Feature flags */
95u_int	amd_feature;		/* AMD feature flags */
96u_int	amd_feature2;		/* AMD feature flags */
97u_int	amd_rascap;		/* AMD RAS capabilities */
98u_int	amd_pminfo;		/* AMD advanced power management info */
99u_int	amd_extended_feature_extensions;
100u_int	via_feature_rng;	/* VIA RNG features */
101u_int	via_feature_xcrypt;	/* VIA ACE features */
102u_int	cpu_high;		/* Highest arg to CPUID */
103u_int	cpu_exthigh;		/* Highest arg to extended CPUID */
104u_int	cpu_id;			/* Stepping ID */
105u_int	cpu_procinfo;		/* HyperThreading Info / Brand Index / CLFUSH */
106u_int	cpu_procinfo2;		/* Multicore info */
107char	cpu_vendor[20];		/* CPU Origin code */
108u_int	cpu_vendor_id;		/* CPU vendor ID */
109u_int	cpu_fxsr;		/* SSE enabled */
110u_int	cpu_mxcsr_mask;		/* Valid bits in mxcsr */
111u_int	cpu_clflush_line_size = 32;
112u_int	cpu_stdext_feature;	/* %ebx */
113u_int	cpu_stdext_feature2;	/* %ecx */
114u_int	cpu_stdext_feature3;	/* %edx */
115uint64_t cpu_ia32_arch_caps;
116u_int	cpu_max_ext_state_size;
117u_int	cpu_mon_mwait_flags;	/* MONITOR/MWAIT flags (CPUID.05H.ECX) */
118u_int	cpu_mon_min_size;	/* MONITOR minimum range size, bytes */
119u_int	cpu_mon_max_size;	/* MONITOR minimum range size, bytes */
120u_int	cpu_maxphyaddr;		/* Max phys addr width in bits */
121u_int	cpu_power_eax;		/* 06H: Power management leaf, %eax */
122u_int	cpu_power_ebx;		/* 06H: Power management leaf, %ebx */
123u_int	cpu_power_ecx;		/* 06H: Power management leaf, %ecx */
124u_int	cpu_power_edx;		/* 06H: Power management leaf, %edx */
125char machine[] = MACHINE;
126
127SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
128    &via_feature_rng, 0,
129    "VIA RNG feature available in CPU");
130SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
131    &via_feature_xcrypt, 0,
132    "VIA xcrypt feature available in CPU");
133
134#ifdef __amd64__
135#ifdef SCTL_MASK32
136extern int adaptive_machine_arch;
137#endif
138
139static int
140sysctl_hw_machine(SYSCTL_HANDLER_ARGS)
141{
142#ifdef SCTL_MASK32
143	static const char machine32[] = "i386";
144#endif
145	int error;
146
147#ifdef SCTL_MASK32
148	if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch)
149		error = SYSCTL_OUT(req, machine32, sizeof(machine32));
150	else
151#endif
152		error = SYSCTL_OUT(req, machine, sizeof(machine));
153	return (error);
154
155}
156SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD |
157    CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class");
158#else
159SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
160    machine, 0, "Machine class");
161#endif
162
163static char cpu_model[128];
164SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE,
165    cpu_model, 0, "Machine model");
166
167static int hw_clockrate;
168SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
169    &hw_clockrate, 0, "CPU instruction clock rate");
170
171u_int hv_base;
172u_int hv_high;
173char hv_vendor[16];
174SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor,
175    0, "Hypervisor vendor");
176
177static eventhandler_tag tsc_post_tag;
178
179static char cpu_brand[48];
180
181#ifdef __i386__
182#define	MAX_BRAND_INDEX	8
183
184static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
185	NULL,			/* No brand */
186	"Intel Celeron",
187	"Intel Pentium III",
188	"Intel Pentium III Xeon",
189	NULL,
190	NULL,
191	NULL,
192	NULL,
193	"Intel Pentium 4"
194};
195
196static struct {
197	char	*cpu_name;
198	int	cpu_class;
199} cpus[] = {
200	{ "Intel 80286",	CPUCLASS_286 },		/* CPU_286   */
201	{ "i386SX",		CPUCLASS_386 },		/* CPU_386SX */
202	{ "i386DX",		CPUCLASS_386 },		/* CPU_386   */
203	{ "i486SX",		CPUCLASS_486 },		/* CPU_486SX */
204	{ "i486DX",		CPUCLASS_486 },		/* CPU_486   */
205	{ "Pentium",		CPUCLASS_586 },		/* CPU_586   */
206	{ "Cyrix 486",		CPUCLASS_486 },		/* CPU_486DLC */
207	{ "Pentium Pro",	CPUCLASS_686 },		/* CPU_686 */
208	{ "Cyrix 5x86",		CPUCLASS_486 },		/* CPU_M1SC */
209	{ "Cyrix 6x86",		CPUCLASS_486 },		/* CPU_M1 */
210	{ "Blue Lightning",	CPUCLASS_486 },		/* CPU_BLUE */
211	{ "Cyrix 6x86MX",	CPUCLASS_686 },		/* CPU_M2 */
212	{ "NexGen 586",		CPUCLASS_386 },		/* CPU_NX586 (XXX) */
213	{ "Cyrix 486S/DX",	CPUCLASS_486 },		/* CPU_CY486DX */
214	{ "Pentium II",		CPUCLASS_686 },		/* CPU_PII */
215	{ "Pentium III",	CPUCLASS_686 },		/* CPU_PIII */
216	{ "Pentium 4",		CPUCLASS_686 },		/* CPU_P4 */
217};
218#endif
219
220static struct {
221	char	*vendor;
222	u_int	vendor_id;
223} cpu_vendors[] = {
224	{ INTEL_VENDOR_ID,	CPU_VENDOR_INTEL },	/* GenuineIntel */
225	{ AMD_VENDOR_ID,	CPU_VENDOR_AMD },	/* AuthenticAMD */
226	{ HYGON_VENDOR_ID,	CPU_VENDOR_HYGON },	/* HygonGenuine*/
227	{ CENTAUR_VENDOR_ID,	CPU_VENDOR_CENTAUR },	/* CentaurHauls */
228#ifdef __i386__
229	{ NSC_VENDOR_ID,	CPU_VENDOR_NSC },	/* Geode by NSC */
230	{ CYRIX_VENDOR_ID,	CPU_VENDOR_CYRIX },	/* CyrixInstead */
231	{ TRANSMETA_VENDOR_ID,	CPU_VENDOR_TRANSMETA },	/* GenuineTMx86 */
232	{ SIS_VENDOR_ID,	CPU_VENDOR_SIS },	/* SiS SiS SiS  */
233	{ UMC_VENDOR_ID,	CPU_VENDOR_UMC },	/* UMC UMC UMC  */
234	{ NEXGEN_VENDOR_ID,	CPU_VENDOR_NEXGEN },	/* NexGenDriven */
235	{ RISE_VENDOR_ID,	CPU_VENDOR_RISE },	/* RiseRiseRise */
236#if 0
237	/* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
238	{ "TransmetaCPU",	CPU_VENDOR_TRANSMETA },
239#endif
240#endif
241};
242
243void
244printcpuinfo(void)
245{
246	u_int regs[4], i;
247	char *brand;
248
249	printf("CPU: ");
250#ifdef __i386__
251	cpu_class = cpus[cpu].cpu_class;
252	strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model));
253#else
254	strncpy(cpu_model, "Hammer", sizeof (cpu_model));
255#endif
256
257	/* Check for extended CPUID information and a processor name. */
258	if (cpu_exthigh >= 0x80000004) {
259		brand = cpu_brand;
260		for (i = 0x80000002; i < 0x80000005; i++) {
261			do_cpuid(i, regs);
262			memcpy(brand, regs, sizeof(regs));
263			brand += sizeof(regs);
264		}
265	}
266
267	switch (cpu_vendor_id) {
268	case CPU_VENDOR_INTEL:
269#ifdef __i386__
270		if ((cpu_id & 0xf00) > 0x300) {
271			u_int brand_index;
272
273			cpu_model[0] = '\0';
274
275			switch (cpu_id & 0x3000) {
276			case 0x1000:
277				strcpy(cpu_model, "Overdrive ");
278				break;
279			case 0x2000:
280				strcpy(cpu_model, "Dual ");
281				break;
282			}
283
284			switch (cpu_id & 0xf00) {
285			case 0x400:
286				strcat(cpu_model, "i486 ");
287				/* Check the particular flavor of 486 */
288				switch (cpu_id & 0xf0) {
289				case 0x00:
290				case 0x10:
291					strcat(cpu_model, "DX");
292					break;
293				case 0x20:
294					strcat(cpu_model, "SX");
295					break;
296				case 0x30:
297					strcat(cpu_model, "DX2");
298					break;
299				case 0x40:
300					strcat(cpu_model, "SL");
301					break;
302				case 0x50:
303					strcat(cpu_model, "SX2");
304					break;
305				case 0x70:
306					strcat(cpu_model,
307					    "DX2 Write-Back Enhanced");
308					break;
309				case 0x80:
310					strcat(cpu_model, "DX4");
311					break;
312				}
313				break;
314			case 0x500:
315				/* Check the particular flavor of 586 */
316				strcat(cpu_model, "Pentium");
317				switch (cpu_id & 0xf0) {
318				case 0x00:
319					strcat(cpu_model, " A-step");
320					break;
321				case 0x10:
322					strcat(cpu_model, "/P5");
323					break;
324				case 0x20:
325					strcat(cpu_model, "/P54C");
326					break;
327				case 0x30:
328					strcat(cpu_model, "/P24T");
329					break;
330				case 0x40:
331					strcat(cpu_model, "/P55C");
332					break;
333				case 0x70:
334					strcat(cpu_model, "/P54C");
335					break;
336				case 0x80:
337					strcat(cpu_model, "/P55C (quarter-micron)");
338					break;
339				default:
340					/* nothing */
341					break;
342				}
343#if defined(I586_CPU) && !defined(NO_F00F_HACK)
344				/*
345				 * XXX - If/when Intel fixes the bug, this
346				 * should also check the version of the
347				 * CPU, not just that it's a Pentium.
348				 */
349				has_f00f_bug = 1;
350#endif
351				break;
352			case 0x600:
353				/* Check the particular flavor of 686 */
354				switch (cpu_id & 0xf0) {
355				case 0x00:
356					strcat(cpu_model, "Pentium Pro A-step");
357					break;
358				case 0x10:
359					strcat(cpu_model, "Pentium Pro");
360					break;
361				case 0x30:
362				case 0x50:
363				case 0x60:
364					strcat(cpu_model,
365				"Pentium II/Pentium II Xeon/Celeron");
366					cpu = CPU_PII;
367					break;
368				case 0x70:
369				case 0x80:
370				case 0xa0:
371				case 0xb0:
372					strcat(cpu_model,
373					"Pentium III/Pentium III Xeon/Celeron");
374					cpu = CPU_PIII;
375					break;
376				default:
377					strcat(cpu_model, "Unknown 80686");
378					break;
379				}
380				break;
381			case 0xf00:
382				strcat(cpu_model, "Pentium 4");
383				cpu = CPU_P4;
384				break;
385			default:
386				strcat(cpu_model, "unknown");
387				break;
388			}
389
390			/*
391			 * If we didn't get a brand name from the extended
392			 * CPUID, try to look it up in the brand table.
393			 */
394			if (cpu_high > 0 && *cpu_brand == '\0') {
395				brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
396				if (brand_index <= MAX_BRAND_INDEX &&
397				    cpu_brandtable[brand_index] != NULL)
398					strcpy(cpu_brand,
399					    cpu_brandtable[brand_index]);
400			}
401		}
402#else
403		/* Please make up your mind folks! */
404		strcat(cpu_model, "EM64T");
405#endif
406		break;
407	case CPU_VENDOR_AMD:
408		/*
409		 * Values taken from AMD Processor Recognition
410		 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
411		 * (also describes ``Features'' encodings.
412		 */
413		strcpy(cpu_model, "AMD ");
414#ifdef __i386__
415		switch (cpu_id & 0xFF0) {
416		case 0x410:
417			strcat(cpu_model, "Standard Am486DX");
418			break;
419		case 0x430:
420			strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
421			break;
422		case 0x470:
423			strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
424			break;
425		case 0x480:
426			strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
427			break;
428		case 0x490:
429			strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
430			break;
431		case 0x4E0:
432			strcat(cpu_model, "Am5x86 Write-Through");
433			break;
434		case 0x4F0:
435			strcat(cpu_model, "Am5x86 Write-Back");
436			break;
437		case 0x500:
438			strcat(cpu_model, "K5 model 0");
439			break;
440		case 0x510:
441			strcat(cpu_model, "K5 model 1");
442			break;
443		case 0x520:
444			strcat(cpu_model, "K5 PR166 (model 2)");
445			break;
446		case 0x530:
447			strcat(cpu_model, "K5 PR200 (model 3)");
448			break;
449		case 0x560:
450			strcat(cpu_model, "K6");
451			break;
452		case 0x570:
453			strcat(cpu_model, "K6 266 (model 1)");
454			break;
455		case 0x580:
456			strcat(cpu_model, "K6-2");
457			break;
458		case 0x590:
459			strcat(cpu_model, "K6-III");
460			break;
461		case 0x5a0:
462			strcat(cpu_model, "Geode LX");
463			break;
464		default:
465			strcat(cpu_model, "Unknown");
466			break;
467		}
468#else
469		if ((cpu_id & 0xf00) == 0xf00)
470			strcat(cpu_model, "AMD64 Processor");
471		else
472			strcat(cpu_model, "Unknown");
473#endif
474		break;
475#ifdef __i386__
476	case CPU_VENDOR_CYRIX:
477		strcpy(cpu_model, "Cyrix ");
478		switch (cpu_id & 0xff0) {
479		case 0x440:
480			strcat(cpu_model, "MediaGX");
481			break;
482		case 0x520:
483			strcat(cpu_model, "6x86");
484			break;
485		case 0x540:
486			cpu_class = CPUCLASS_586;
487			strcat(cpu_model, "GXm");
488			break;
489		case 0x600:
490			strcat(cpu_model, "6x86MX");
491			break;
492		default:
493			/*
494			 * Even though CPU supports the cpuid
495			 * instruction, it can be disabled.
496			 * Therefore, this routine supports all Cyrix
497			 * CPUs.
498			 */
499			switch (cyrix_did & 0xf0) {
500			case 0x00:
501				switch (cyrix_did & 0x0f) {
502				case 0x00:
503					strcat(cpu_model, "486SLC");
504					break;
505				case 0x01:
506					strcat(cpu_model, "486DLC");
507					break;
508				case 0x02:
509					strcat(cpu_model, "486SLC2");
510					break;
511				case 0x03:
512					strcat(cpu_model, "486DLC2");
513					break;
514				case 0x04:
515					strcat(cpu_model, "486SRx");
516					break;
517				case 0x05:
518					strcat(cpu_model, "486DRx");
519					break;
520				case 0x06:
521					strcat(cpu_model, "486SRx2");
522					break;
523				case 0x07:
524					strcat(cpu_model, "486DRx2");
525					break;
526				case 0x08:
527					strcat(cpu_model, "486SRu");
528					break;
529				case 0x09:
530					strcat(cpu_model, "486DRu");
531					break;
532				case 0x0a:
533					strcat(cpu_model, "486SRu2");
534					break;
535				case 0x0b:
536					strcat(cpu_model, "486DRu2");
537					break;
538				default:
539					strcat(cpu_model, "Unknown");
540					break;
541				}
542				break;
543			case 0x10:
544				switch (cyrix_did & 0x0f) {
545				case 0x00:
546					strcat(cpu_model, "486S");
547					break;
548				case 0x01:
549					strcat(cpu_model, "486S2");
550					break;
551				case 0x02:
552					strcat(cpu_model, "486Se");
553					break;
554				case 0x03:
555					strcat(cpu_model, "486S2e");
556					break;
557				case 0x0a:
558					strcat(cpu_model, "486DX");
559					break;
560				case 0x0b:
561					strcat(cpu_model, "486DX2");
562					break;
563				case 0x0f:
564					strcat(cpu_model, "486DX4");
565					break;
566				default:
567					strcat(cpu_model, "Unknown");
568					break;
569				}
570				break;
571			case 0x20:
572				if ((cyrix_did & 0x0f) < 8)
573					strcat(cpu_model, "6x86");	/* Where did you get it? */
574				else
575					strcat(cpu_model, "5x86");
576				break;
577			case 0x30:
578				strcat(cpu_model, "6x86");
579				break;
580			case 0x40:
581				if ((cyrix_did & 0xf000) == 0x3000) {
582					cpu_class = CPUCLASS_586;
583					strcat(cpu_model, "GXm");
584				} else
585					strcat(cpu_model, "MediaGX");
586				break;
587			case 0x50:
588				strcat(cpu_model, "6x86MX");
589				break;
590			case 0xf0:
591				switch (cyrix_did & 0x0f) {
592				case 0x0d:
593					strcat(cpu_model, "Overdrive CPU");
594					break;
595				case 0x0e:
596					strcpy(cpu_model, "Texas Instruments 486SXL");
597					break;
598				case 0x0f:
599					strcat(cpu_model, "486SLC/DLC");
600					break;
601				default:
602					strcat(cpu_model, "Unknown");
603					break;
604				}
605				break;
606			default:
607				strcat(cpu_model, "Unknown");
608				break;
609			}
610			break;
611		}
612		break;
613	case CPU_VENDOR_RISE:
614		strcpy(cpu_model, "Rise ");
615		switch (cpu_id & 0xff0) {
616		case 0x500:	/* 6401 and 6441 (Kirin) */
617		case 0x520:	/* 6510 (Lynx) */
618			strcat(cpu_model, "mP6");
619			break;
620		default:
621			strcat(cpu_model, "Unknown");
622		}
623		break;
624#endif
625	case CPU_VENDOR_CENTAUR:
626#ifdef __i386__
627		switch (cpu_id & 0xff0) {
628		case 0x540:
629			strcpy(cpu_model, "IDT WinChip C6");
630			break;
631		case 0x580:
632			strcpy(cpu_model, "IDT WinChip 2");
633			break;
634		case 0x590:
635			strcpy(cpu_model, "IDT WinChip 3");
636			break;
637		case 0x660:
638			strcpy(cpu_model, "VIA C3 Samuel");
639			break;
640		case 0x670:
641			if (cpu_id & 0x8)
642				strcpy(cpu_model, "VIA C3 Ezra");
643			else
644				strcpy(cpu_model, "VIA C3 Samuel 2");
645			break;
646		case 0x680:
647			strcpy(cpu_model, "VIA C3 Ezra-T");
648			break;
649		case 0x690:
650			strcpy(cpu_model, "VIA C3 Nehemiah");
651			break;
652		case 0x6a0:
653		case 0x6d0:
654			strcpy(cpu_model, "VIA C7 Esther");
655			break;
656		case 0x6f0:
657			strcpy(cpu_model, "VIA Nano");
658			break;
659		default:
660			strcpy(cpu_model, "VIA/IDT Unknown");
661		}
662#else
663		strcpy(cpu_model, "VIA ");
664		if ((cpu_id & 0xff0) == 0x6f0)
665			strcat(cpu_model, "Nano Processor");
666		else
667			strcat(cpu_model, "Unknown");
668#endif
669		break;
670#ifdef __i386__
671	case CPU_VENDOR_IBM:
672		strcpy(cpu_model, "Blue Lightning CPU");
673		break;
674	case CPU_VENDOR_NSC:
675		switch (cpu_id & 0xff0) {
676		case 0x540:
677			strcpy(cpu_model, "Geode SC1100");
678			cpu = CPU_GEODE1100;
679			break;
680		default:
681			strcpy(cpu_model, "Geode/NSC unknown");
682			break;
683		}
684		break;
685#endif
686	case CPU_VENDOR_HYGON:
687		strcpy(cpu_model, "Hygon ");
688#ifdef __i386__
689		strcat(cpu_model, "Unknown");
690#else
691		if ((cpu_id & 0xf00) == 0xf00)
692			strcat(cpu_model, "AMD64 Processor");
693		else
694			strcat(cpu_model, "Unknown");
695#endif
696		break;
697
698	default:
699		strcat(cpu_model, "Unknown");
700		break;
701	}
702
703	/*
704	 * Replace cpu_model with cpu_brand minus leading spaces if
705	 * we have one.
706	 */
707	brand = cpu_brand;
708	while (*brand == ' ')
709		++brand;
710	if (*brand != '\0')
711		strcpy(cpu_model, brand);
712
713	printf("%s (", cpu_model);
714	if (tsc_freq != 0) {
715		hw_clockrate = (tsc_freq + 5000) / 1000000;
716		printf("%jd.%02d-MHz ",
717		    (intmax_t)(tsc_freq + 4999) / 1000000,
718		    (u_int)((tsc_freq + 4999) / 10000) % 100);
719	}
720#ifdef __i386__
721	switch(cpu_class) {
722	case CPUCLASS_286:
723		printf("286");
724		break;
725	case CPUCLASS_386:
726		printf("386");
727		break;
728#if defined(I486_CPU)
729	case CPUCLASS_486:
730		printf("486");
731		break;
732#endif
733#if defined(I586_CPU)
734	case CPUCLASS_586:
735		printf("586");
736		break;
737#endif
738#if defined(I686_CPU)
739	case CPUCLASS_686:
740		printf("686");
741		break;
742#endif
743	default:
744		printf("Unknown");	/* will panic below... */
745	}
746#else
747	printf("K8");
748#endif
749	printf("-class CPU)\n");
750	if (*cpu_vendor)
751		printf("  Origin=\"%s\"", cpu_vendor);
752	if (cpu_id)
753		printf("  Id=0x%x", cpu_id);
754
755	if (cpu_vendor_id == CPU_VENDOR_INTEL ||
756	    cpu_vendor_id == CPU_VENDOR_AMD ||
757	    cpu_vendor_id == CPU_VENDOR_HYGON ||
758	    cpu_vendor_id == CPU_VENDOR_CENTAUR ||
759#ifdef __i386__
760	    cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
761	    cpu_vendor_id == CPU_VENDOR_RISE ||
762	    cpu_vendor_id == CPU_VENDOR_NSC ||
763	    (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) ||
764#endif
765	    0) {
766		printf("  Family=0x%x", CPUID_TO_FAMILY(cpu_id));
767		printf("  Model=0x%x", CPUID_TO_MODEL(cpu_id));
768		printf("  Stepping=%u", cpu_id & CPUID_STEPPING);
769#ifdef __i386__
770		if (cpu_vendor_id == CPU_VENDOR_CYRIX)
771			printf("\n  DIR=0x%04x", cyrix_did);
772#endif
773
774		/*
775		 * AMD CPUID Specification
776		 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf
777		 *
778		 * Intel Processor Identification and CPUID Instruction
779		 * http://www.intel.com/assets/pdf/appnote/241618.pdf
780		 */
781		if (cpu_high > 0) {
782
783			/*
784			 * Here we should probably set up flags indicating
785			 * whether or not various features are available.
786			 * The interesting ones are probably VME, PSE, PAE,
787			 * and PGE.  The code already assumes without bothering
788			 * to check that all CPUs >= Pentium have a TSC and
789			 * MSRs.
790			 */
791			printf("\n  Features=0x%b", cpu_feature,
792			"\020"
793			"\001FPU"	/* Integral FPU */
794			"\002VME"	/* Extended VM86 mode support */
795			"\003DE"	/* Debugging Extensions (CR4.DE) */
796			"\004PSE"	/* 4MByte page tables */
797			"\005TSC"	/* Timestamp counter */
798			"\006MSR"	/* Machine specific registers */
799			"\007PAE"	/* Physical address extension */
800			"\010MCE"	/* Machine Check support */
801			"\011CX8"	/* CMPEXCH8 instruction */
802			"\012APIC"	/* SMP local APIC */
803			"\013oldMTRR"	/* Previous implementation of MTRR */
804			"\014SEP"	/* Fast System Call */
805			"\015MTRR"	/* Memory Type Range Registers */
806			"\016PGE"	/* PG_G (global bit) support */
807			"\017MCA"	/* Machine Check Architecture */
808			"\020CMOV"	/* CMOV instruction */
809			"\021PAT"	/* Page attributes table */
810			"\022PSE36"	/* 36 bit address space support */
811			"\023PN"	/* Processor Serial number */
812			"\024CLFLUSH"	/* Has the CLFLUSH instruction */
813			"\025<b20>"
814			"\026DTS"	/* Debug Trace Store */
815			"\027ACPI"	/* ACPI support */
816			"\030MMX"	/* MMX instructions */
817			"\031FXSR"	/* FXSAVE/FXRSTOR */
818			"\032SSE"	/* Streaming SIMD Extensions */
819			"\033SSE2"	/* Streaming SIMD Extensions #2 */
820			"\034SS"	/* Self snoop */
821			"\035HTT"	/* Hyperthreading (see EBX bit 16-23) */
822			"\036TM"	/* Thermal Monitor clock slowdown */
823			"\037IA64"	/* CPU can execute IA64 instructions */
824			"\040PBE"	/* Pending Break Enable */
825			);
826
827			if (cpu_feature2 != 0) {
828				printf("\n  Features2=0x%b", cpu_feature2,
829				"\020"
830				"\001SSE3"	/* SSE3 */
831				"\002PCLMULQDQ"	/* Carry-Less Mul Quadword */
832				"\003DTES64"	/* 64-bit Debug Trace */
833				"\004MON"	/* MONITOR/MWAIT Instructions */
834				"\005DS_CPL"	/* CPL Qualified Debug Store */
835				"\006VMX"	/* Virtual Machine Extensions */
836				"\007SMX"	/* Safer Mode Extensions */
837				"\010EST"	/* Enhanced SpeedStep */
838				"\011TM2"	/* Thermal Monitor 2 */
839				"\012SSSE3"	/* SSSE3 */
840				"\013CNXT-ID"	/* L1 context ID available */
841				"\014SDBG"	/* IA32 silicon debug */
842				"\015FMA"	/* Fused Multiply Add */
843				"\016CX16"	/* CMPXCHG16B Instruction */
844				"\017xTPR"	/* Send Task Priority Messages*/
845				"\020PDCM"	/* Perf/Debug Capability MSR */
846				"\021<b16>"
847				"\022PCID"	/* Process-context Identifiers*/
848				"\023DCA"	/* Direct Cache Access */
849				"\024SSE4.1"	/* SSE 4.1 */
850				"\025SSE4.2"	/* SSE 4.2 */
851				"\026x2APIC"	/* xAPIC Extensions */
852				"\027MOVBE"	/* MOVBE Instruction */
853				"\030POPCNT"	/* POPCNT Instruction */
854				"\031TSCDLT"	/* TSC-Deadline Timer */
855				"\032AESNI"	/* AES Crypto */
856				"\033XSAVE"	/* XSAVE/XRSTOR States */
857				"\034OSXSAVE"	/* OS-Enabled State Management*/
858				"\035AVX"	/* Advanced Vector Extensions */
859				"\036F16C"	/* Half-precision conversions */
860				"\037RDRAND"	/* RDRAND Instruction */
861				"\040HV"	/* Hypervisor */
862				);
863			}
864
865			if (amd_feature != 0) {
866				printf("\n  AMD Features=0x%b", amd_feature,
867				"\020"		/* in hex */
868				"\001<s0>"	/* Same */
869				"\002<s1>"	/* Same */
870				"\003<s2>"	/* Same */
871				"\004<s3>"	/* Same */
872				"\005<s4>"	/* Same */
873				"\006<s5>"	/* Same */
874				"\007<s6>"	/* Same */
875				"\010<s7>"	/* Same */
876				"\011<s8>"	/* Same */
877				"\012<s9>"	/* Same */
878				"\013<b10>"	/* Undefined */
879				"\014SYSCALL"	/* Have SYSCALL/SYSRET */
880				"\015<s12>"	/* Same */
881				"\016<s13>"	/* Same */
882				"\017<s14>"	/* Same */
883				"\020<s15>"	/* Same */
884				"\021<s16>"	/* Same */
885				"\022<s17>"	/* Same */
886				"\023<b18>"	/* Reserved, unknown */
887				"\024MP"	/* Multiprocessor Capable */
888				"\025NX"	/* Has EFER.NXE, NX */
889				"\026<b21>"	/* Undefined */
890				"\027MMX+"	/* AMD MMX Extensions */
891				"\030<s23>"	/* Same */
892				"\031<s24>"	/* Same */
893				"\032FFXSR"	/* Fast FXSAVE/FXRSTOR */
894				"\033Page1GB"	/* 1-GB large page support */
895				"\034RDTSCP"	/* RDTSCP */
896				"\035<b28>"	/* Undefined */
897				"\036LM"	/* 64 bit long mode */
898				"\0373DNow!+"	/* AMD 3DNow! Extensions */
899				"\0403DNow!"	/* AMD 3DNow! */
900				);
901			}
902
903			if (amd_feature2 != 0) {
904				printf("\n  AMD Features2=0x%b", amd_feature2,
905				"\020"
906				"\001LAHF"	/* LAHF/SAHF in long mode */
907				"\002CMP"	/* CMP legacy */
908				"\003SVM"	/* Secure Virtual Mode */
909				"\004ExtAPIC"	/* Extended APIC register */
910				"\005CR8"	/* CR8 in legacy mode */
911				"\006ABM"	/* LZCNT instruction */
912				"\007SSE4A"	/* SSE4A */
913				"\010MAS"	/* Misaligned SSE mode */
914				"\011Prefetch"	/* 3DNow! Prefetch/PrefetchW */
915				"\012OSVW"	/* OS visible workaround */
916				"\013IBS"	/* Instruction based sampling */
917				"\014XOP"	/* XOP extended instructions */
918				"\015SKINIT"	/* SKINIT/STGI */
919				"\016WDT"	/* Watchdog timer */
920				"\017<b14>"
921				"\020LWP"	/* Lightweight Profiling */
922				"\021FMA4"	/* 4-operand FMA instructions */
923				"\022TCE"	/* Translation Cache Extension */
924				"\023<b18>"
925				"\024NodeId"	/* NodeId MSR support */
926				"\025<b20>"
927				"\026TBM"	/* Trailing Bit Manipulation */
928				"\027Topology"	/* Topology Extensions */
929				"\030PCXC"	/* Core perf count */
930				"\031PNXC"	/* NB perf count */
931				"\032<b25>"
932				"\033DBE"	/* Data Breakpoint extension */
933				"\034PTSC"	/* Performance TSC */
934				"\035PL2I"	/* L2I perf count */
935				"\036MWAITX"	/* MONITORX/MWAITX instructions */
936				"\037ADMSKX"	/* Address mask extension */
937				"\040<b31>"
938				);
939			}
940
941			if (cpu_stdext_feature != 0) {
942				printf("\n  Structured Extended Features=0x%b",
943				    cpu_stdext_feature,
944				       "\020"
945				       /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
946				       "\001FSGSBASE"
947				       "\002TSCADJ"
948				       "\003SGX"
949				       /* Bit Manipulation Instructions */
950				       "\004BMI1"
951				       /* Hardware Lock Elision */
952				       "\005HLE"
953				       /* Advanced Vector Instructions 2 */
954				       "\006AVX2"
955				       /* FDP_EXCPTN_ONLY */
956				       "\007FDPEXC"
957				       /* Supervisor Mode Execution Prot. */
958				       "\010SMEP"
959				       /* Bit Manipulation Instructions */
960				       "\011BMI2"
961				       "\012ERMS"
962				       /* Invalidate Processor Context ID */
963				       "\013INVPCID"
964				       /* Restricted Transactional Memory */
965				       "\014RTM"
966				       "\015PQM"
967				       "\016NFPUSG"
968				       /* Intel Memory Protection Extensions */
969				       "\017MPX"
970				       "\020PQE"
971				       /* AVX512 Foundation */
972				       "\021AVX512F"
973				       "\022AVX512DQ"
974				       /* Enhanced NRBG */
975				       "\023RDSEED"
976				       /* ADCX + ADOX */
977				       "\024ADX"
978				       /* Supervisor Mode Access Prevention */
979				       "\025SMAP"
980				       "\026AVX512IFMA"
981				       /* Formerly PCOMMIT */
982				       "\027<b22>"
983				       "\030CLFLUSHOPT"
984				       "\031CLWB"
985				       "\032PROCTRACE"
986				       "\033AVX512PF"
987				       "\034AVX512ER"
988				       "\035AVX512CD"
989				       "\036SHA"
990				       "\037AVX512BW"
991				       "\040AVX512VL"
992				       );
993			}
994
995			if (cpu_stdext_feature2 != 0) {
996				printf("\n  Structured Extended Features2=0x%b",
997				    cpu_stdext_feature2,
998				       "\020"
999				       "\001PREFETCHWT1"
1000				       "\002AVX512VBMI"
1001				       "\003UMIP"
1002				       "\004PKU"
1003				       "\005OSPKE"
1004				       "\006WAITPKG"
1005				       "\007AVX512VBMI2"
1006				       "\011GFNI"
1007				       "\012VAES"
1008				       "\013VPCLMULQDQ"
1009				       "\014AVX512VNNI"
1010				       "\015AVX512BITALG"
1011				       "\016AVX512VPOPCNTDQ"
1012				       "\027RDPID"
1013				       "\032CLDEMOTE"
1014				       "\034MOVDIRI"
1015				       "\035MOVDIR64B"
1016				       "\036ENQCMD"
1017				       "\037SGXLC"
1018				       );
1019			}
1020
1021			if (cpu_stdext_feature3 != 0) {
1022				printf("\n  Structured Extended Features3=0x%b",
1023				    cpu_stdext_feature3,
1024				       "\020"
1025				       "\003AVX512_4VNNIW"
1026				       "\004AVX512_4FMAPS"
1027				       "\005FSRM"
1028				       "\011AVX512VP2INTERSECT"
1029				       "\013MD_CLEAR"
1030				       "\016TSXFA"
1031				       "\023PCONFIG"
1032				       "\025IBT"
1033				       "\033IBPB"
1034				       "\034STIBP"
1035				       "\035L1DFL"
1036				       "\036ARCH_CAP"
1037				       "\037CORE_CAP"
1038				       "\040SSBD"
1039				       );
1040			}
1041
1042			if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
1043				cpuid_count(0xd, 0x1, regs);
1044				if (regs[0] != 0) {
1045					printf("\n  XSAVE Features=0x%b",
1046					    regs[0],
1047					    "\020"
1048					    "\001XSAVEOPT"
1049					    "\002XSAVEC"
1050					    "\003XINUSE"
1051					    "\004XSAVES");
1052				}
1053			}
1054
1055			if (cpu_ia32_arch_caps != 0) {
1056				printf("\n  IA32_ARCH_CAPS=0x%b",
1057				    (u_int)cpu_ia32_arch_caps,
1058				       "\020"
1059				       "\001RDCL_NO"
1060				       "\002IBRS_ALL"
1061				       "\003RSBA"
1062				       "\004SKIP_L1DFL_VME"
1063				       "\005SSB_NO"
1064				       "\006MDS_NO"
1065				       "\010TSX_CTRL"
1066				       "\011TAA_NO"
1067				       );
1068			}
1069
1070			if (amd_extended_feature_extensions != 0) {
1071				u_int amd_fe_masked;
1072
1073				amd_fe_masked = amd_extended_feature_extensions;
1074				if ((amd_fe_masked & AMDFEID_IBRS) == 0)
1075					amd_fe_masked &=
1076					    ~(AMDFEID_IBRS_ALWAYSON |
1077						AMDFEID_PREFER_IBRS);
1078				if ((amd_fe_masked & AMDFEID_STIBP) == 0)
1079					amd_fe_masked &=
1080					    ~AMDFEID_STIBP_ALWAYSON;
1081
1082				printf("\n  "
1083				    "AMD Extended Feature Extensions ID EBX="
1084				    "0x%b", amd_fe_masked,
1085				    "\020"
1086				    "\001CLZERO"
1087				    "\002IRPerf"
1088				    "\003XSaveErPtr"
1089				    "\005RDPRU"
1090				    "\011MCOMMIT"
1091				    "\012WBNOINVD"
1092				    "\015IBPB"
1093				    "\017IBRS"
1094				    "\020STIBP"
1095				    "\021IBRS_ALWAYSON"
1096				    "\022STIBP_ALWAYSON"
1097				    "\023PREFER_IBRS"
1098				    "\031SSBD"
1099				    "\032VIRT_SSBD"
1100				    "\033SSB_NO"
1101				    );
1102			}
1103
1104			if (via_feature_rng != 0 || via_feature_xcrypt != 0)
1105				print_via_padlock_info();
1106
1107			if (cpu_feature2 & CPUID2_VMX)
1108				print_vmx_info();
1109
1110			if (amd_feature2 & AMDID2_SVM)
1111				print_svm_info();
1112
1113			if ((cpu_feature & CPUID_HTT) &&
1114			    (cpu_vendor_id == CPU_VENDOR_AMD ||
1115			     cpu_vendor_id == CPU_VENDOR_HYGON))
1116				cpu_feature &= ~CPUID_HTT;
1117
1118			/*
1119			 * If this CPU supports P-state invariant TSC then
1120			 * mention the capability.
1121			 */
1122			if (tsc_is_invariant) {
1123				printf("\n  TSC: P-state invariant");
1124				if (tsc_perf_stat)
1125					printf(", performance statistics");
1126			}
1127		}
1128#ifdef __i386__
1129	} else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1130		printf("  DIR=0x%04x", cyrix_did);
1131		printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
1132		printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
1133#ifndef CYRIX_CACHE_REALLY_WORKS
1134		if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
1135			printf("\n  CPU cache: write-through mode");
1136#endif
1137#endif
1138	}
1139
1140	/* Avoid ugly blank lines: only print newline when we have to. */
1141	if (*cpu_vendor || cpu_id)
1142		printf("\n");
1143
1144	if (bootverbose) {
1145		if (cpu_vendor_id == CPU_VENDOR_AMD ||
1146		    cpu_vendor_id == CPU_VENDOR_HYGON)
1147			print_AMD_info();
1148		else if (cpu_vendor_id == CPU_VENDOR_INTEL)
1149			print_INTEL_info();
1150#ifdef __i386__
1151		else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
1152			print_transmeta_info();
1153#endif
1154	}
1155
1156	print_hypervisor_info();
1157}
1158
1159#ifdef __i386__
1160void
1161panicifcpuunsupported(void)
1162{
1163
1164#if !defined(lint)
1165#if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
1166#error This kernel is not configured for one of the supported CPUs
1167#endif
1168#else /* lint */
1169#endif /* lint */
1170	/*
1171	 * Now that we have told the user what they have,
1172	 * let them know if that machine type isn't configured.
1173	 */
1174	switch (cpu_class) {
1175	case CPUCLASS_286:	/* a 286 should not make it this far, anyway */
1176	case CPUCLASS_386:
1177#if !defined(I486_CPU)
1178	case CPUCLASS_486:
1179#endif
1180#if !defined(I586_CPU)
1181	case CPUCLASS_586:
1182#endif
1183#if !defined(I686_CPU)
1184	case CPUCLASS_686:
1185#endif
1186		panic("CPU class not configured");
1187	default:
1188		break;
1189	}
1190}
1191
1192static	volatile u_int trap_by_rdmsr;
1193
1194/*
1195 * Special exception 6 handler.
1196 * The rdmsr instruction generates invalid opcodes fault on 486-class
1197 * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
1198 * function identblue() when this handler is called.  Stacked eip should
1199 * be advanced.
1200 */
1201inthand_t	bluetrap6;
1202#ifdef __GNUCLIKE_ASM
1203__asm
1204("									\n\
1205	.text								\n\
1206	.p2align 2,0x90							\n\
1207	.type	" __XSTRING(CNAME(bluetrap6)) ",@function		\n\
1208" __XSTRING(CNAME(bluetrap6)) ":					\n\
1209	ss								\n\
1210	movl	$0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "		\n\
1211	addl	$2, (%esp)	/* rdmsr is a 2-byte instruction */	\n\
1212	iret								\n\
1213");
1214#endif
1215
1216/*
1217 * Special exception 13 handler.
1218 * Accessing non-existent MSR generates general protection fault.
1219 */
1220inthand_t	bluetrap13;
1221#ifdef __GNUCLIKE_ASM
1222__asm
1223("									\n\
1224	.text								\n\
1225	.p2align 2,0x90							\n\
1226	.type	" __XSTRING(CNAME(bluetrap13)) ",@function		\n\
1227" __XSTRING(CNAME(bluetrap13)) ":					\n\
1228	ss								\n\
1229	movl	$0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "		\n\
1230	popl	%eax		/* discard error code */		\n\
1231	addl	$2, (%esp)	/* rdmsr is a 2-byte instruction */	\n\
1232	iret								\n\
1233");
1234#endif
1235
1236/*
1237 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1238 * support cpuid instruction.  This function should be called after
1239 * loading interrupt descriptor table register.
1240 *
1241 * I don't like this method that handles fault, but I couldn't get
1242 * information for any other methods.  Does blue giant know?
1243 */
1244static int
1245identblue(void)
1246{
1247
1248	trap_by_rdmsr = 0;
1249
1250	/*
1251	 * Cyrix 486-class CPU does not support rdmsr instruction.
1252	 * The rdmsr instruction generates invalid opcode fault, and exception
1253	 * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1254	 * bluetrap6() set the magic number to trap_by_rdmsr.
1255	 */
1256	setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1257	    GSEL(GCODE_SEL, SEL_KPL));
1258
1259	/*
1260	 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1261	 * In this case, rdmsr generates general protection fault, and
1262	 * exception will be trapped by bluetrap13().
1263	 */
1264	setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1265	    GSEL(GCODE_SEL, SEL_KPL));
1266
1267	rdmsr(0x1002);		/* Cyrix CPU generates fault. */
1268
1269	if (trap_by_rdmsr == 0xa8c1d)
1270		return IDENTBLUE_CYRIX486;
1271	else if (trap_by_rdmsr == 0xa89c4)
1272		return IDENTBLUE_CYRIXM2;
1273	return IDENTBLUE_IBMCPU;
1274}
1275
1276
1277/*
1278 * identifycyrix() set lower 16 bits of cyrix_did as follows:
1279 *
1280 *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1281 * +-------+-------+---------------+
1282 * |  SID  |  RID  |   Device ID   |
1283 * |    (DIR 1)    |    (DIR 0)    |
1284 * +-------+-------+---------------+
1285 */
1286static void
1287identifycyrix(void)
1288{
1289	register_t saveintr;
1290	int	ccr2_test = 0, dir_test = 0;
1291	u_char	ccr2, ccr3;
1292
1293	saveintr = intr_disable();
1294
1295	ccr2 = read_cyrix_reg(CCR2);
1296	write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1297	read_cyrix_reg(CCR2);
1298	if (read_cyrix_reg(CCR2) != ccr2)
1299		ccr2_test = 1;
1300	write_cyrix_reg(CCR2, ccr2);
1301
1302	ccr3 = read_cyrix_reg(CCR3);
1303	write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1304	read_cyrix_reg(CCR3);
1305	if (read_cyrix_reg(CCR3) != ccr3)
1306		dir_test = 1;					/* CPU supports DIRs. */
1307	write_cyrix_reg(CCR3, ccr3);
1308
1309	if (dir_test) {
1310		/* Device ID registers are available. */
1311		cyrix_did = read_cyrix_reg(DIR1) << 8;
1312		cyrix_did += read_cyrix_reg(DIR0);
1313	} else if (ccr2_test)
1314		cyrix_did = 0x0010;		/* 486S A-step */
1315	else
1316		cyrix_did = 0x00ff;		/* Old 486SLC/DLC and TI486SXLC/SXL */
1317
1318	intr_restore(saveintr);
1319}
1320#endif
1321
1322/* Update TSC freq with the value indicated by the caller. */
1323static void
1324tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status)
1325{
1326
1327	/* If there was an error during the transition, don't do anything. */
1328	if (status != 0)
1329		return;
1330
1331	/* Total setting for this level gives the new frequency in MHz. */
1332	hw_clockrate = level->total_set.freq;
1333}
1334
1335static void
1336hook_tsc_freq(void *arg __unused)
1337{
1338
1339	if (tsc_is_invariant)
1340		return;
1341
1342	tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change,
1343	    tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY);
1344}
1345
1346SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL);
1347
1348static const struct {
1349	const char *	vm_bname;
1350	int		vm_guest;
1351} vm_bnames[] = {
1352	{ "QEMU",	VM_GUEST_VM },		/* QEMU */
1353	{ "Plex86",	VM_GUEST_VM },		/* Plex86 */
1354	{ "Bochs",	VM_GUEST_VM },		/* Bochs */
1355	{ "Xen",	VM_GUEST_XEN },		/* Xen */
1356	{ "BHYVE",	VM_GUEST_BHYVE },	/* bhyve */
1357	{ "Seabios",	VM_GUEST_KVM },		/* KVM */
1358};
1359
1360static const struct {
1361	const char *	vm_pname;
1362	int		vm_guest;
1363} vm_pnames[] = {
1364	{ "VMware Virtual Platform",	VM_GUEST_VMWARE },
1365	{ "Virtual Machine",		VM_GUEST_VM }, /* Microsoft VirtualPC */
1366	{ "VirtualBox",			VM_GUEST_VBOX },
1367	{ "Parallels Virtual Platform",	VM_GUEST_PARALLELS },
1368	{ "KVM",			VM_GUEST_KVM },
1369};
1370
1371static struct {
1372	const char	*vm_cpuid;
1373	int		vm_guest;
1374} vm_cpuids[] = {
1375	{ "XENXENXEN",		VM_GUEST_XEN },		/* XEN */
1376	{ "Microsoft Hv",	VM_GUEST_HV },		/* Microsoft Hyper-V */
1377	{ "VMwareVMware",	VM_GUEST_VMWARE },	/* VMware VM */
1378	{ "KVMKVMKVM",		VM_GUEST_KVM },		/* KVM */
1379	{ "bhyve bhyve ",	VM_GUEST_BHYVE },	/* bhyve */
1380	{ "VBoxVBoxVBox",	VM_GUEST_VBOX },	/* VirtualBox */
1381};
1382
1383static void
1384identify_hypervisor_cpuid_base(void)
1385{
1386	u_int leaf, regs[4];
1387	int i;
1388
1389	/*
1390	 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
1391	 * http://lkml.org/lkml/2008/10/1/246
1392	 *
1393	 * KB1009458: Mechanisms to determine if software is running in
1394	 * a VMware virtual machine
1395	 * http://kb.vmware.com/kb/1009458
1396	 *
1397	 * Search for a hypervisor that we recognize. If we cannot find
1398	 * a specific hypervisor, return the first information about the
1399	 * hypervisor that we found, as others may be able to use.
1400	 */
1401	for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1402		do_cpuid(leaf, regs);
1403
1404		/*
1405		 * KVM from Linux kernels prior to commit
1406		 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax
1407		 * to 0 rather than a valid hv_high value.  Check for
1408		 * the KVM signature bytes and fixup %eax to the
1409		 * highest supported leaf in that case.
1410		 */
1411		if (regs[0] == 0 && regs[1] == 0x4b4d564b &&
1412		    regs[2] == 0x564b4d56 && regs[3] == 0x0000004d)
1413			regs[0] = leaf + 1;
1414
1415		if (regs[0] >= leaf) {
1416			for (i = 0; i < nitems(vm_cpuids); i++)
1417				if (strncmp((const char *)&regs[1],
1418				    vm_cpuids[i].vm_cpuid, 12) == 0) {
1419					vm_guest = vm_cpuids[i].vm_guest;
1420					break;
1421				}
1422
1423			/*
1424			 * If this is the first entry or we found a
1425			 * specific hypervisor, record the base, high value,
1426			 * and vendor identifier.
1427			 */
1428			if (vm_guest != VM_GUEST_VM || leaf == 0x40000000) {
1429				hv_base = leaf;
1430				hv_high = regs[0];
1431				((u_int *)&hv_vendor)[0] = regs[1];
1432				((u_int *)&hv_vendor)[1] = regs[2];
1433				((u_int *)&hv_vendor)[2] = regs[3];
1434				hv_vendor[12] = '\0';
1435
1436				/*
1437				 * If we found a specific hypervisor, then
1438				 * we are finished.
1439				 */
1440				if (vm_guest != VM_GUEST_VM)
1441					return;
1442			}
1443		}
1444	}
1445}
1446
1447void
1448identify_hypervisor(void)
1449{
1450	u_int regs[4];
1451	char *p;
1452	int i;
1453
1454	/*
1455	 * If CPUID2_HV is set, we are running in a hypervisor environment.
1456	 */
1457	if (cpu_feature2 & CPUID2_HV) {
1458		vm_guest = VM_GUEST_VM;
1459		identify_hypervisor_cpuid_base();
1460
1461		/* If we have a definitive vendor, we can return now. */
1462		if (*hv_vendor != '\0')
1463			return;
1464	}
1465
1466	/*
1467	 * Examine SMBIOS strings for older hypervisors.
1468	 */
1469	p = kern_getenv("smbios.system.serial");
1470	if (p != NULL) {
1471		if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) {
1472			vmware_hvcall(VMW_HVCMD_GETVERSION, regs);
1473			if (regs[1] == VMW_HVMAGIC) {
1474				vm_guest = VM_GUEST_VMWARE;
1475				freeenv(p);
1476				return;
1477			}
1478		}
1479		freeenv(p);
1480	}
1481
1482	/*
1483	 * XXX: Some of these entries may not be needed since they were
1484	 * added to FreeBSD before the checks above.
1485	 */
1486	p = kern_getenv("smbios.bios.vendor");
1487	if (p != NULL) {
1488		for (i = 0; i < nitems(vm_bnames); i++)
1489			if (strcmp(p, vm_bnames[i].vm_bname) == 0) {
1490				vm_guest = vm_bnames[i].vm_guest;
1491				/* If we have a specific match, return */
1492				if (vm_guest != VM_GUEST_VM) {
1493					freeenv(p);
1494					return;
1495				}
1496				/*
1497				 * We are done with bnames, but there might be
1498				 * a more specific match in the pnames
1499				 */
1500				break;
1501			}
1502		freeenv(p);
1503	}
1504	p = kern_getenv("smbios.system.product");
1505	if (p != NULL) {
1506		for (i = 0; i < nitems(vm_pnames); i++)
1507			if (strcmp(p, vm_pnames[i].vm_pname) == 0) {
1508				vm_guest = vm_pnames[i].vm_guest;
1509				freeenv(p);
1510				return;
1511			}
1512		freeenv(p);
1513	}
1514}
1515
1516bool
1517fix_cpuid(void)
1518{
1519	uint64_t msr;
1520
1521	/*
1522	 * Clear "Limit CPUID Maxval" bit and return true if the caller should
1523	 * get the largest standard CPUID function number again if it is set
1524	 * from BIOS.  It is necessary for probing correct CPU topology later
1525	 * and for the correct operation of the AVX-aware userspace.
1526	 */
1527	if (cpu_vendor_id == CPU_VENDOR_INTEL &&
1528	    ((CPUID_TO_FAMILY(cpu_id) == 0xf &&
1529	    CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1530	    (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1531	    CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1532		msr = rdmsr(MSR_IA32_MISC_ENABLE);
1533		if ((msr & IA32_MISC_EN_LIMCPUID) != 0) {
1534			msr &= ~IA32_MISC_EN_LIMCPUID;
1535			wrmsr(MSR_IA32_MISC_ENABLE, msr);
1536			return (true);
1537		}
1538	}
1539
1540	/*
1541	 * Re-enable AMD Topology Extension that could be disabled by BIOS
1542	 * on some notebook processors.  Without the extension it's really
1543	 * hard to determine the correct CPU cache topology.
1544	 * See BIOS and Kernel Developer���s Guide (BKDG) for AMD Family 15h
1545	 * Models 60h-6Fh Processors, Publication # 50742.
1546	 */
1547	if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&
1548	    CPUID_TO_FAMILY(cpu_id) == 0x15) {
1549		msr = rdmsr(MSR_EXTFEATURES);
1550		if ((msr & ((uint64_t)1 << 54)) == 0) {
1551			msr |= (uint64_t)1 << 54;
1552			wrmsr(MSR_EXTFEATURES, msr);
1553			return (true);
1554		}
1555	}
1556	return (false);
1557}
1558
1559void
1560identify_cpu1(void)
1561{
1562	u_int regs[4];
1563
1564	do_cpuid(0, regs);
1565	cpu_high = regs[0];
1566	((u_int *)&cpu_vendor)[0] = regs[1];
1567	((u_int *)&cpu_vendor)[1] = regs[3];
1568	((u_int *)&cpu_vendor)[2] = regs[2];
1569	cpu_vendor[12] = '\0';
1570
1571	do_cpuid(1, regs);
1572	cpu_id = regs[0];
1573	cpu_procinfo = regs[1];
1574	cpu_feature = regs[3];
1575	cpu_feature2 = regs[2];
1576}
1577
1578void
1579identify_cpu2(void)
1580{
1581	u_int regs[4], cpu_stdext_disable;
1582
1583	if (cpu_high >= 6) {
1584		cpuid_count(6, 0, regs);
1585		cpu_power_eax = regs[0];
1586		cpu_power_ebx = regs[1];
1587		cpu_power_ecx = regs[2];
1588		cpu_power_edx = regs[3];
1589	}
1590
1591	if (cpu_high >= 7) {
1592		cpuid_count(7, 0, regs);
1593		cpu_stdext_feature = regs[1];
1594
1595		/*
1596		 * Some hypervisors failed to filter out unsupported
1597		 * extended features.  Allow to disable the
1598		 * extensions, activation of which requires setting a
1599		 * bit in CR4, and which VM monitors do not support.
1600		 */
1601		cpu_stdext_disable = 0;
1602		TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable);
1603		cpu_stdext_feature &= ~cpu_stdext_disable;
1604
1605		cpu_stdext_feature2 = regs[2];
1606		cpu_stdext_feature3 = regs[3];
1607
1608		if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
1609			cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
1610	}
1611}
1612
1613void
1614identify_cpu_fixup_bsp(void)
1615{
1616	u_int regs[4];
1617
1618	cpu_vendor_id = find_cpu_vendor_id();
1619
1620	if (fix_cpuid()) {
1621		do_cpuid(0, regs);
1622		cpu_high = regs[0];
1623	}
1624}
1625
1626/*
1627 * Final stage of CPU identification.
1628 */
1629void
1630finishidentcpu(void)
1631{
1632	u_int regs[4];
1633#ifdef __i386__
1634	u_char ccr3;
1635#endif
1636
1637	identify_cpu_fixup_bsp();
1638
1639	if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
1640		do_cpuid(5, regs);
1641		cpu_mon_mwait_flags = regs[2];
1642		cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
1643		cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
1644	}
1645
1646	identify_cpu2();
1647
1648#ifdef __i386__
1649	if (cpu_high > 0 &&
1650	    (cpu_vendor_id == CPU_VENDOR_INTEL ||
1651	     cpu_vendor_id == CPU_VENDOR_AMD ||
1652	     cpu_vendor_id == CPU_VENDOR_HYGON ||
1653	     cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
1654	     cpu_vendor_id == CPU_VENDOR_CENTAUR ||
1655	     cpu_vendor_id == CPU_VENDOR_NSC)) {
1656		do_cpuid(0x80000000, regs);
1657		if (regs[0] >= 0x80000000)
1658			cpu_exthigh = regs[0];
1659	}
1660#else
1661	if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1662	    cpu_vendor_id == CPU_VENDOR_AMD ||
1663	    cpu_vendor_id == CPU_VENDOR_HYGON ||
1664	    cpu_vendor_id == CPU_VENDOR_CENTAUR) {
1665		do_cpuid(0x80000000, regs);
1666		cpu_exthigh = regs[0];
1667	}
1668#endif
1669	if (cpu_exthigh >= 0x80000001) {
1670		do_cpuid(0x80000001, regs);
1671		amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1672		amd_feature2 = regs[2];
1673	}
1674	if (cpu_exthigh >= 0x80000007) {
1675		do_cpuid(0x80000007, regs);
1676		amd_rascap = regs[1];
1677		amd_pminfo = regs[3];
1678	}
1679	if (cpu_exthigh >= 0x80000008) {
1680		do_cpuid(0x80000008, regs);
1681		cpu_maxphyaddr = regs[0] & 0xff;
1682		amd_extended_feature_extensions = regs[1];
1683		cpu_procinfo2 = regs[2];
1684	} else {
1685		cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32;
1686	}
1687
1688#ifdef __i386__
1689	if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1690		if (cpu == CPU_486) {
1691			/*
1692			 * These conditions are equivalent to:
1693			 *     - CPU does not support cpuid instruction.
1694			 *     - Cyrix/IBM CPU is detected.
1695			 */
1696			if (identblue() == IDENTBLUE_IBMCPU) {
1697				strcpy(cpu_vendor, "IBM");
1698				cpu_vendor_id = CPU_VENDOR_IBM;
1699				cpu = CPU_BLUE;
1700				return;
1701			}
1702		}
1703		switch (cpu_id & 0xf00) {
1704		case 0x600:
1705			/*
1706			 * Cyrix's datasheet does not describe DIRs.
1707			 * Therefor, I assume it does not have them
1708			 * and use the result of the cpuid instruction.
1709			 * XXX they seem to have it for now at least. -Peter
1710			 */
1711			identifycyrix();
1712			cpu = CPU_M2;
1713			break;
1714		default:
1715			identifycyrix();
1716			/*
1717			 * This routine contains a trick.
1718			 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1719			 */
1720			switch (cyrix_did & 0x00f0) {
1721			case 0x00:
1722			case 0xf0:
1723				cpu = CPU_486DLC;
1724				break;
1725			case 0x10:
1726				cpu = CPU_CY486DX;
1727				break;
1728			case 0x20:
1729				if ((cyrix_did & 0x000f) < 8)
1730					cpu = CPU_M1;
1731				else
1732					cpu = CPU_M1SC;
1733				break;
1734			case 0x30:
1735				cpu = CPU_M1;
1736				break;
1737			case 0x40:
1738				/* MediaGX CPU */
1739				cpu = CPU_M1SC;
1740				break;
1741			default:
1742				/* M2 and later CPUs are treated as M2. */
1743				cpu = CPU_M2;
1744
1745				/*
1746				 * enable cpuid instruction.
1747				 */
1748				ccr3 = read_cyrix_reg(CCR3);
1749				write_cyrix_reg(CCR3, CCR3_MAPEN0);
1750				write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1751				write_cyrix_reg(CCR3, ccr3);
1752
1753				do_cpuid(0, regs);
1754				cpu_high = regs[0];	/* eax */
1755				do_cpuid(1, regs);
1756				cpu_id = regs[0];	/* eax */
1757				cpu_feature = regs[3];	/* edx */
1758				break;
1759			}
1760		}
1761	} else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1762		/*
1763		 * There are BlueLightning CPUs that do not change
1764		 * undefined flags by dividing 5 by 2.  In this case,
1765		 * the CPU identification routine in locore.s leaves
1766		 * cpu_vendor null string and puts CPU_486 into the
1767		 * cpu.
1768		 */
1769		if (identblue() == IDENTBLUE_IBMCPU) {
1770			strcpy(cpu_vendor, "IBM");
1771			cpu_vendor_id = CPU_VENDOR_IBM;
1772			cpu = CPU_BLUE;
1773			return;
1774		}
1775	}
1776#endif
1777}
1778
1779int
1780pti_get_default(void)
1781{
1782
1783	if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 ||
1784	    strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0)
1785		return (0);
1786	if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0)
1787		return (0);
1788	return (1);
1789}
1790
1791static u_int
1792find_cpu_vendor_id(void)
1793{
1794	int	i;
1795
1796	for (i = 0; i < nitems(cpu_vendors); i++)
1797		if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1798			return (cpu_vendors[i].vendor_id);
1799	return (0);
1800}
1801
1802static void
1803print_AMD_assoc(int i)
1804{
1805	if (i == 255)
1806		printf(", fully associative\n");
1807	else
1808		printf(", %d-way associative\n", i);
1809}
1810
1811static void
1812print_AMD_l2_assoc(int i)
1813{
1814	switch (i & 0x0f) {
1815	case 0: printf(", disabled/not present\n"); break;
1816	case 1: printf(", direct mapped\n"); break;
1817	case 2: printf(", 2-way associative\n"); break;
1818	case 4: printf(", 4-way associative\n"); break;
1819	case 6: printf(", 8-way associative\n"); break;
1820	case 8: printf(", 16-way associative\n"); break;
1821	case 15: printf(", fully associative\n"); break;
1822	default: printf(", reserved configuration\n"); break;
1823	}
1824}
1825
1826static void
1827print_AMD_info(void)
1828{
1829#ifdef __i386__
1830	uint64_t amd_whcr;
1831#endif
1832	u_int regs[4];
1833
1834	if (cpu_exthigh >= 0x80000005) {
1835		do_cpuid(0x80000005, regs);
1836		printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
1837		print_AMD_assoc(regs[0] >> 24);
1838
1839		printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
1840		print_AMD_assoc((regs[0] >> 8) & 0xff);
1841
1842		printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
1843		print_AMD_assoc(regs[1] >> 24);
1844
1845		printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
1846		print_AMD_assoc((regs[1] >> 8) & 0xff);
1847
1848		printf("L1 data cache: %d kbytes", regs[2] >> 24);
1849		printf(", %d bytes/line", regs[2] & 0xff);
1850		printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1851		print_AMD_assoc((regs[2] >> 16) & 0xff);
1852
1853		printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1854		printf(", %d bytes/line", regs[3] & 0xff);
1855		printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1856		print_AMD_assoc((regs[3] >> 16) & 0xff);
1857	}
1858
1859	if (cpu_exthigh >= 0x80000006) {
1860		do_cpuid(0x80000006, regs);
1861		if ((regs[0] >> 16) != 0) {
1862			printf("L2 2MB data TLB: %d entries",
1863			    (regs[0] >> 16) & 0xfff);
1864			print_AMD_l2_assoc(regs[0] >> 28);
1865			printf("L2 2MB instruction TLB: %d entries",
1866			    regs[0] & 0xfff);
1867			print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1868		} else {
1869			printf("L2 2MB unified TLB: %d entries",
1870			    regs[0] & 0xfff);
1871			print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
1872		}
1873		if ((regs[1] >> 16) != 0) {
1874			printf("L2 4KB data TLB: %d entries",
1875			    (regs[1] >> 16) & 0xfff);
1876			print_AMD_l2_assoc(regs[1] >> 28);
1877
1878			printf("L2 4KB instruction TLB: %d entries",
1879			    (regs[1] >> 16) & 0xfff);
1880			print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1881		} else {
1882			printf("L2 4KB unified TLB: %d entries",
1883			    (regs[1] >> 16) & 0xfff);
1884			print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
1885		}
1886		printf("L2 unified cache: %d kbytes", regs[2] >> 16);
1887		printf(", %d bytes/line", regs[2] & 0xff);
1888		printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1889		print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
1890	}
1891
1892#ifdef __i386__
1893	if (((cpu_id & 0xf00) == 0x500)
1894	    && (((cpu_id & 0x0f0) > 0x80)
1895		|| (((cpu_id & 0x0f0) == 0x80)
1896		    && (cpu_id & 0x00f) > 0x07))) {
1897		/* K6-2(new core [Stepping 8-F]), K6-III or later */
1898		amd_whcr = rdmsr(0xc0000082);
1899		if (!(amd_whcr & (0x3ff << 22))) {
1900			printf("Write Allocate Disable\n");
1901		} else {
1902			printf("Write Allocate Enable Limit: %dM bytes\n",
1903			    (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1904			printf("Write Allocate 15-16M bytes: %s\n",
1905			    (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1906		}
1907	} else if (((cpu_id & 0xf00) == 0x500)
1908		   && ((cpu_id & 0x0f0) > 0x50)) {
1909		/* K6, K6-2(old core) */
1910		amd_whcr = rdmsr(0xc0000082);
1911		if (!(amd_whcr & (0x7f << 1))) {
1912			printf("Write Allocate Disable\n");
1913		} else {
1914			printf("Write Allocate Enable Limit: %dM bytes\n",
1915			    (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1916			printf("Write Allocate 15-16M bytes: %s\n",
1917			    (amd_whcr & 0x0001) ? "Enable" : "Disable");
1918			printf("Hardware Write Allocate Control: %s\n",
1919			    (amd_whcr & 0x0100) ? "Enable" : "Disable");
1920		}
1921	}
1922#endif
1923	/*
1924	 * Opteron Rev E shows a bug as in very rare occasions a read memory
1925	 * barrier is not performed as expected if it is followed by a
1926	 * non-atomic read-modify-write instruction.
1927	 * As long as that bug pops up very rarely (intensive machine usage
1928	 * on other operating systems generally generates one unexplainable
1929	 * crash any 2 months) and as long as a model specific fix would be
1930	 * impractical at this stage, print out a warning string if the broken
1931	 * model and family are identified.
1932	 */
1933	if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1934	    CPUID_TO_MODEL(cpu_id) <= 0x3f)
1935		printf("WARNING: This architecture revision has known SMP "
1936		    "hardware bugs which may cause random instability\n");
1937}
1938
1939static void
1940print_INTEL_info(void)
1941{
1942	u_int regs[4];
1943	u_int rounds, regnum;
1944	u_int nwaycode, nway;
1945
1946	if (cpu_high >= 2) {
1947		rounds = 0;
1948		do {
1949			do_cpuid(0x2, regs);
1950			if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1951				break;	/* we have a buggy CPU */
1952
1953			for (regnum = 0; regnum <= 3; ++regnum) {
1954				if (regs[regnum] & (1<<31))
1955					continue;
1956				if (regnum != 0)
1957					print_INTEL_TLB(regs[regnum] & 0xff);
1958				print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1959				print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1960				print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1961			}
1962		} while (--rounds > 0);
1963	}
1964
1965	if (cpu_exthigh >= 0x80000006) {
1966		do_cpuid(0x80000006, regs);
1967		nwaycode = (regs[2] >> 12) & 0x0f;
1968		if (nwaycode >= 0x02 && nwaycode <= 0x08)
1969			nway = 1 << (nwaycode / 2);
1970		else
1971			nway = 0;
1972		printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n",
1973		    (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1974	}
1975}
1976
1977static void
1978print_INTEL_TLB(u_int data)
1979{
1980	switch (data) {
1981	case 0x0:
1982	case 0x40:
1983	default:
1984		break;
1985	case 0x1:
1986		printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n");
1987		break;
1988	case 0x2:
1989		printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n");
1990		break;
1991	case 0x3:
1992		printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n");
1993		break;
1994	case 0x4:
1995		printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n");
1996		break;
1997	case 0x6:
1998		printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n");
1999		break;
2000	case 0x8:
2001		printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n");
2002		break;
2003	case 0x9:
2004		printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n");
2005		break;
2006	case 0xa:
2007		printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n");
2008		break;
2009	case 0xb:
2010		printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n");
2011		break;
2012	case 0xc:
2013		printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n");
2014		break;
2015	case 0xd:
2016		printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size");
2017		break;
2018	case 0xe:
2019		printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n");
2020		break;
2021	case 0x1d:
2022		printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n");
2023		break;
2024	case 0x21:
2025		printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n");
2026		break;
2027	case 0x22:
2028		printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2029		break;
2030	case 0x23:
2031		printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2032		break;
2033	case 0x24:
2034		printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n");
2035		break;
2036	case 0x25:
2037		printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2038		break;
2039	case 0x29:
2040		printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2041		break;
2042	case 0x2c:
2043		printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n");
2044		break;
2045	case 0x30:
2046		printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n");
2047		break;
2048	case 0x39: /* De-listed in SDM rev. 54 */
2049		printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2050		break;
2051	case 0x3b: /* De-listed in SDM rev. 54 */
2052		printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n");
2053		break;
2054	case 0x3c: /* De-listed in SDM rev. 54 */
2055		printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2056		break;
2057	case 0x41:
2058		printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n");
2059		break;
2060	case 0x42:
2061		printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n");
2062		break;
2063	case 0x43:
2064		printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n");
2065		break;
2066	case 0x44:
2067		printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n");
2068		break;
2069	case 0x45:
2070		printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n");
2071		break;
2072	case 0x46:
2073		printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n");
2074		break;
2075	case 0x47:
2076		printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n");
2077		break;
2078	case 0x48:
2079		printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n");
2080		break;
2081	case 0x49:
2082		if (CPUID_TO_FAMILY(cpu_id) == 0xf &&
2083		    CPUID_TO_MODEL(cpu_id) == 0x6)
2084			printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
2085		else
2086			printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size");
2087		break;
2088	case 0x4a:
2089		printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n");
2090		break;
2091	case 0x4b:
2092		printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n");
2093		break;
2094	case 0x4c:
2095		printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n");
2096		break;
2097	case 0x4d:
2098		printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n");
2099		break;
2100	case 0x4e:
2101		printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n");
2102		break;
2103	case 0x4f:
2104		printf("Instruction TLB: 4 KByte pages, 32 entries\n");
2105		break;
2106	case 0x50:
2107		printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n");
2108		break;
2109	case 0x51:
2110		printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n");
2111		break;
2112	case 0x52:
2113		printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n");
2114		break;
2115	case 0x55:
2116		printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n");
2117		break;
2118	case 0x56:
2119		printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n");
2120		break;
2121	case 0x57:
2122		printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n");
2123		break;
2124	case 0x59:
2125		printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n");
2126		break;
2127	case 0x5a:
2128		printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n");
2129		break;
2130	case 0x5b:
2131		printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n");
2132		break;
2133	case 0x5c:
2134		printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n");
2135		break;
2136	case 0x5d:
2137		printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n");
2138		break;
2139	case 0x60:
2140		printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2141		break;
2142	case 0x61:
2143		printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n");
2144		break;
2145	case 0x63:
2146		printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n");
2147		break;
2148	case 0x64:
2149		printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n");
2150		break;
2151	case 0x66:
2152		printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2153		break;
2154	case 0x67:
2155		printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n");
2156		break;
2157	case 0x68:
2158		printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
2159		break;
2160	case 0x6a:
2161		printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
2162		break;
2163	case 0x6b:
2164		printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
2165		break;
2166	case 0x6c:
2167		printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n");
2168		break;
2169	case 0x6d:
2170		printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
2171		break;
2172	case 0x70:
2173		printf("Trace cache: 12K-uops, 8-way set associative\n");
2174		break;
2175	case 0x71:
2176		printf("Trace cache: 16K-uops, 8-way set associative\n");
2177		break;
2178	case 0x72:
2179		printf("Trace cache: 32K-uops, 8-way set associative\n");
2180		break;
2181	case 0x76:
2182		printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n");
2183		break;
2184	case 0x78:
2185		printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n");
2186		break;
2187	case 0x79:
2188		printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2189		break;
2190	case 0x7a:
2191		printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2192		break;
2193	case 0x7b:
2194		printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n");
2195		break;
2196	case 0x7c:
2197		printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n");
2198		break;
2199	case 0x7d:
2200		printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
2201		break;
2202	case 0x7f:
2203		printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n");
2204		break;
2205	case 0x80:
2206		printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n");
2207		break;
2208	case 0x82:
2209		printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n");
2210		break;
2211	case 0x83:
2212		printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n");
2213		break;
2214	case 0x84:
2215		printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n");
2216		break;
2217	case 0x85:
2218		printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n");
2219		break;
2220	case 0x86:
2221		printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n");
2222		break;
2223	case 0x87:
2224		printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n");
2225		break;
2226	case 0xa0:
2227		printf("DTLB: 4k pages, fully associative, 32 entries\n");
2228		break;
2229	case 0xb0:
2230		printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2231		break;
2232	case 0xb1:
2233		printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n");
2234		break;
2235	case 0xb2:
2236		printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n");
2237		break;
2238	case 0xb3:
2239		printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n");
2240		break;
2241	case 0xb4:
2242		printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n");
2243		break;
2244	case 0xb5:
2245		printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n");
2246		break;
2247	case 0xb6:
2248		printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n");
2249		break;
2250	case 0xba:
2251		printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n");
2252		break;
2253	case 0xc0:
2254		printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n");
2255		break;
2256	case 0xc1:
2257		printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n");
2258		break;
2259	case 0xc2:
2260		printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n");
2261		break;
2262	case 0xc3:
2263		printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n");
2264		break;
2265	case 0xc4:
2266		printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n");
2267		break;
2268	case 0xca:
2269		printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n");
2270		break;
2271	case 0xd0:
2272		printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n");
2273		break;
2274	case 0xd1:
2275		printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n");
2276		break;
2277	case 0xd2:
2278		printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n");
2279		break;
2280	case 0xd6:
2281		printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n");
2282		break;
2283	case 0xd7:
2284		printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n");
2285		break;
2286	case 0xd8:
2287		printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n");
2288		break;
2289	case 0xdc:
2290		printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n");
2291		break;
2292	case 0xdd:
2293		printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n");
2294		break;
2295	case 0xde:
2296		printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n");
2297		break;
2298	case 0xe2:
2299		printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n");
2300		break;
2301	case 0xe3:
2302		printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n");
2303		break;
2304	case 0xe4:
2305		printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n");
2306		break;
2307	case 0xea:
2308		printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n");
2309		break;
2310	case 0xeb:
2311		printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n");
2312		break;
2313	case 0xec:
2314		printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n");
2315		break;
2316	case 0xf0:
2317		printf("64-Byte prefetching\n");
2318		break;
2319	case 0xf1:
2320		printf("128-Byte prefetching\n");
2321		break;
2322	}
2323}
2324
2325static void
2326print_svm_info(void)
2327{
2328	u_int features, regs[4];
2329	uint64_t msr;
2330	int comma;
2331
2332	printf("\n  SVM: ");
2333	do_cpuid(0x8000000A, regs);
2334	features = regs[3];
2335
2336	msr = rdmsr(MSR_VM_CR);
2337	if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS)
2338		printf("(disabled in BIOS) ");
2339
2340	if (!bootverbose) {
2341		comma = 0;
2342		if (features & (1 << 0)) {
2343			printf("%sNP", comma ? "," : "");
2344			comma = 1;
2345		}
2346		if (features & (1 << 3)) {
2347			printf("%sNRIP", comma ? "," : "");
2348			comma = 1;
2349		}
2350		if (features & (1 << 5)) {
2351			printf("%sVClean", comma ? "," : "");
2352			comma = 1;
2353		}
2354		if (features & (1 << 6)) {
2355			printf("%sAFlush", comma ? "," : "");
2356			comma = 1;
2357		}
2358		if (features & (1 << 7)) {
2359			printf("%sDAssist", comma ? "," : "");
2360			comma = 1;
2361		}
2362		printf("%sNAsids=%d", comma ? "," : "", regs[1]);
2363		return;
2364	}
2365
2366	printf("Features=0x%b", features,
2367	       "\020"
2368	       "\001NP"			/* Nested paging */
2369	       "\002LbrVirt"		/* LBR virtualization */
2370	       "\003SVML"		/* SVM lock */
2371	       "\004NRIPS"		/* NRIP save */
2372	       "\005TscRateMsr"		/* MSR based TSC rate control */
2373	       "\006VmcbClean"		/* VMCB clean bits */
2374	       "\007FlushByAsid"	/* Flush by ASID */
2375	       "\010DecodeAssist"	/* Decode assist */
2376	       "\011<b8>"
2377	       "\012<b9>"
2378	       "\013PauseFilter"	/* PAUSE intercept filter */
2379	       "\014EncryptedMcodePatch"
2380	       "\015PauseFilterThreshold" /* PAUSE filter threshold */
2381	       "\016AVIC"		/* virtual interrupt controller */
2382	       "\017<b14>"
2383	       "\020V_VMSAVE_VMLOAD"
2384	       "\021vGIF"
2385	       "\022GMET"		/* Guest Mode Execute Trap */
2386	       "\023<b18>"
2387	       "\024<b19>"
2388	       "\025GuesSpecCtl"	/* Guest Spec_ctl */
2389	       "\026<b21>"
2390	       "\027<b22>"
2391	       "\030<b23>"
2392	       "\031<b24>"
2393	       "\032<b25>"
2394	       "\033<b26>"
2395	       "\034<b27>"
2396	       "\035<b28>"
2397	       "\036<b29>"
2398	       "\037<b30>"
2399	       "\040<b31>"
2400	       );
2401	printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]);
2402}
2403
2404#ifdef __i386__
2405static void
2406print_transmeta_info(void)
2407{
2408	u_int regs[4], nreg = 0;
2409
2410	do_cpuid(0x80860000, regs);
2411	nreg = regs[0];
2412	if (nreg >= 0x80860001) {
2413		do_cpuid(0x80860001, regs);
2414		printf("  Processor revision %u.%u.%u.%u\n",
2415		       (regs[1] >> 24) & 0xff,
2416		       (regs[1] >> 16) & 0xff,
2417		       (regs[1] >> 8) & 0xff,
2418		       regs[1] & 0xff);
2419	}
2420	if (nreg >= 0x80860002) {
2421		do_cpuid(0x80860002, regs);
2422		printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
2423		       (regs[1] >> 24) & 0xff,
2424		       (regs[1] >> 16) & 0xff,
2425		       (regs[1] >> 8) & 0xff,
2426		       regs[1] & 0xff,
2427		       regs[2]);
2428	}
2429	if (nreg >= 0x80860006) {
2430		char info[65];
2431		do_cpuid(0x80860003, (u_int*) &info[0]);
2432		do_cpuid(0x80860004, (u_int*) &info[16]);
2433		do_cpuid(0x80860005, (u_int*) &info[32]);
2434		do_cpuid(0x80860006, (u_int*) &info[48]);
2435		info[64] = 0;
2436		printf("  %s\n", info);
2437	}
2438}
2439#endif
2440
2441static void
2442print_via_padlock_info(void)
2443{
2444	u_int regs[4];
2445
2446	do_cpuid(0xc0000001, regs);
2447	printf("\n  VIA Padlock Features=0x%b", regs[3],
2448	"\020"
2449	"\003RNG"		/* RNG */
2450	"\007AES"		/* ACE */
2451	"\011AES-CTR"		/* ACE2 */
2452	"\013SHA1,SHA256"	/* PHE */
2453	"\015RSA"		/* PMM */
2454	);
2455}
2456
2457static uint32_t
2458vmx_settable(uint64_t basic, int msr, int true_msr)
2459{
2460	uint64_t val;
2461
2462	if (basic & (1ULL << 55))
2463		val = rdmsr(true_msr);
2464	else
2465		val = rdmsr(msr);
2466
2467	/* Just report the controls that can be set to 1. */
2468	return (val >> 32);
2469}
2470
2471static void
2472print_vmx_info(void)
2473{
2474	uint64_t basic, msr;
2475	uint32_t entry, exit, mask, pin, proc, proc2;
2476	int comma;
2477
2478	printf("\n  VT-x: ");
2479	msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
2480	if (!(msr & IA32_FEATURE_CONTROL_VMX_EN))
2481		printf("(disabled in BIOS) ");
2482	basic = rdmsr(MSR_VMX_BASIC);
2483	pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS,
2484	    MSR_VMX_TRUE_PINBASED_CTLS);
2485	proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS,
2486	    MSR_VMX_TRUE_PROCBASED_CTLS);
2487	if (proc & PROCBASED_SECONDARY_CONTROLS)
2488		proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2,
2489		    MSR_VMX_PROCBASED_CTLS2);
2490	else
2491		proc2 = 0;
2492	exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS);
2493	entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS);
2494
2495	if (!bootverbose) {
2496		comma = 0;
2497		if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT &&
2498		    entry & VM_ENTRY_LOAD_PAT) {
2499			printf("%sPAT", comma ? "," : "");
2500			comma = 1;
2501		}
2502		if (proc & PROCBASED_HLT_EXITING) {
2503			printf("%sHLT", comma ? "," : "");
2504			comma = 1;
2505		}
2506		if (proc & PROCBASED_MTF) {
2507			printf("%sMTF", comma ? "," : "");
2508			comma = 1;
2509		}
2510		if (proc & PROCBASED_PAUSE_EXITING) {
2511			printf("%sPAUSE", comma ? "," : "");
2512			comma = 1;
2513		}
2514		if (proc2 & PROCBASED2_ENABLE_EPT) {
2515			printf("%sEPT", comma ? "," : "");
2516			comma = 1;
2517		}
2518		if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) {
2519			printf("%sUG", comma ? "," : "");
2520			comma = 1;
2521		}
2522		if (proc2 & PROCBASED2_ENABLE_VPID) {
2523			printf("%sVPID", comma ? "," : "");
2524			comma = 1;
2525		}
2526		if (proc & PROCBASED_USE_TPR_SHADOW &&
2527		    proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES &&
2528		    proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE &&
2529		    proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION &&
2530		    proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) {
2531			printf("%sVID", comma ? "," : "");
2532			comma = 1;
2533			if (pin & PINBASED_POSTED_INTERRUPT)
2534				printf(",PostIntr");
2535		}
2536		return;
2537	}
2538
2539	mask = basic >> 32;
2540	printf("Basic Features=0x%b", mask,
2541	"\020"
2542	"\02132PA"		/* 32-bit physical addresses */
2543	"\022SMM"		/* SMM dual-monitor */
2544	"\027INS/OUTS"		/* VM-exit info for INS and OUTS */
2545	"\030TRUE"		/* TRUE_CTLS MSRs */
2546	);
2547	printf("\n        Pin-Based Controls=0x%b", pin,
2548	"\020"
2549	"\001ExtINT"		/* External-interrupt exiting */
2550	"\004NMI"		/* NMI exiting */
2551	"\006VNMI"		/* Virtual NMIs */
2552	"\007PreTmr"		/* Activate VMX-preemption timer */
2553	"\010PostIntr"		/* Process posted interrupts */
2554	);
2555	printf("\n        Primary Processor Controls=0x%b", proc,
2556	"\020"
2557	"\003INTWIN"		/* Interrupt-window exiting */
2558	"\004TSCOff"		/* Use TSC offsetting */
2559	"\010HLT"		/* HLT exiting */
2560	"\012INVLPG"		/* INVLPG exiting */
2561	"\013MWAIT"		/* MWAIT exiting */
2562	"\014RDPMC"		/* RDPMC exiting */
2563	"\015RDTSC"		/* RDTSC exiting */
2564	"\020CR3-LD"		/* CR3-load exiting */
2565	"\021CR3-ST"		/* CR3-store exiting */
2566	"\024CR8-LD"		/* CR8-load exiting */
2567	"\025CR8-ST"		/* CR8-store exiting */
2568	"\026TPR"		/* Use TPR shadow */
2569	"\027NMIWIN"		/* NMI-window exiting */
2570	"\030MOV-DR"		/* MOV-DR exiting */
2571	"\031IO"		/* Unconditional I/O exiting */
2572	"\032IOmap"		/* Use I/O bitmaps */
2573	"\034MTF"		/* Monitor trap flag */
2574	"\035MSRmap"		/* Use MSR bitmaps */
2575	"\036MONITOR"		/* MONITOR exiting */
2576	"\037PAUSE"		/* PAUSE exiting */
2577	);
2578	if (proc & PROCBASED_SECONDARY_CONTROLS)
2579		printf("\n        Secondary Processor Controls=0x%b", proc2,
2580		"\020"
2581		"\001APIC"		/* Virtualize APIC accesses */
2582		"\002EPT"		/* Enable EPT */
2583		"\003DT"		/* Descriptor-table exiting */
2584		"\004RDTSCP"		/* Enable RDTSCP */
2585		"\005x2APIC"		/* Virtualize x2APIC mode */
2586		"\006VPID"		/* Enable VPID */
2587		"\007WBINVD"		/* WBINVD exiting */
2588		"\010UG"		/* Unrestricted guest */
2589		"\011APIC-reg"		/* APIC-register virtualization */
2590		"\012VID"		/* Virtual-interrupt delivery */
2591		"\013PAUSE-loop"	/* PAUSE-loop exiting */
2592		"\014RDRAND"		/* RDRAND exiting */
2593		"\015INVPCID"		/* Enable INVPCID */
2594		"\016VMFUNC"		/* Enable VM functions */
2595		"\017VMCS"		/* VMCS shadowing */
2596		"\020EPT#VE"		/* EPT-violation #VE */
2597		"\021XSAVES"		/* Enable XSAVES/XRSTORS */
2598		);
2599	printf("\n        Exit Controls=0x%b", mask,
2600	"\020"
2601	"\003DR"		/* Save debug controls */
2602				/* Ignore Host address-space size */
2603	"\015PERF"		/* Load MSR_PERF_GLOBAL_CTRL */
2604	"\020AckInt"		/* Acknowledge interrupt on exit */
2605	"\023PAT-SV"		/* Save MSR_PAT */
2606	"\024PAT-LD"		/* Load MSR_PAT */
2607	"\025EFER-SV"		/* Save MSR_EFER */
2608	"\026EFER-LD"		/* Load MSR_EFER */
2609	"\027PTMR-SV"		/* Save VMX-preemption timer value */
2610	);
2611	printf("\n        Entry Controls=0x%b", mask,
2612	"\020"
2613	"\003DR"		/* Save debug controls */
2614				/* Ignore IA-32e mode guest */
2615				/* Ignore Entry to SMM */
2616				/* Ignore Deactivate dual-monitor treatment */
2617	"\016PERF"		/* Load MSR_PERF_GLOBAL_CTRL */
2618	"\017PAT"		/* Load MSR_PAT */
2619	"\020EFER"		/* Load MSR_EFER */
2620	);
2621	if (proc & PROCBASED_SECONDARY_CONTROLS &&
2622	    (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) {
2623		msr = rdmsr(MSR_VMX_EPT_VPID_CAP);
2624		mask = msr;
2625		printf("\n        EPT Features=0x%b", mask,
2626		"\020"
2627		"\001XO"		/* Execute-only translations */
2628		"\007PW4"		/* Page-walk length of 4 */
2629		"\011UC"		/* EPT paging-structure mem can be UC */
2630		"\017WB"		/* EPT paging-structure mem can be WB */
2631		"\0212M"		/* EPT PDE can map a 2-Mbyte page */
2632		"\0221G"		/* EPT PDPTE can map a 1-Gbyte page */
2633		"\025INVEPT"		/* INVEPT is supported */
2634		"\026AD"		/* Accessed and dirty flags for EPT */
2635		"\032single"		/* INVEPT single-context type */
2636		"\033all"		/* INVEPT all-context type */
2637		);
2638		mask = msr >> 32;
2639		printf("\n        VPID Features=0x%b", mask,
2640		"\020"
2641		"\001INVVPID"		/* INVVPID is supported */
2642		"\011individual"	/* INVVPID individual-address type */
2643		"\012single"		/* INVVPID single-context type */
2644		"\013all"		/* INVVPID all-context type */
2645		 /* INVVPID single-context-retaining-globals type */
2646		"\014single-globals"
2647		);
2648	}
2649}
2650
2651static void
2652print_hypervisor_info(void)
2653{
2654
2655	if (*hv_vendor != '\0')
2656		printf("Hypervisor: Origin = \"%s\"\n", hv_vendor);
2657}
2658
2659/*
2660 * Returns the maximum physical address that can be used with the
2661 * current system.
2662 */
2663vm_paddr_t
2664cpu_getmaxphyaddr(void)
2665{
2666
2667#if defined(__i386__)
2668	if (!pae_mode)
2669		return (0xffffffff);
2670#endif
2671	return ((1ULL << cpu_maxphyaddr) - 1);
2672}
2673