1b571d13hselasky/* $FreeBSD$ */
2b571d13hselasky
3b571d13hselasky/*-
41537078pfg * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
51537078pfg *
6b571d13hselasky * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
7b571d13hselasky *
8b571d13hselasky * Redistribution and use in source and binary forms, with or without
9b571d13hselasky * modification, are permitted provided that the following conditions
10b571d13hselasky * are met:
11b571d13hselasky * 1. Redistributions of source code must retain the above copyright
12b571d13hselasky *    notice, this list of conditions and the following disclaimer.
13b571d13hselasky * 2. Redistributions in binary form must reproduce the above copyright
14b571d13hselasky *    notice, this list of conditions and the following disclaimer in the
15b571d13hselasky *    documentation and/or other materials provided with the distribution.
16b571d13hselasky *
17b571d13hselasky * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18b571d13hselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19b571d13hselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20b571d13hselasky * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21b571d13hselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22b571d13hselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23b571d13hselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24b571d13hselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25b571d13hselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26b571d13hselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27b571d13hselasky * SUCH DAMAGE.
28b571d13hselasky */
29b571d13hselasky
30b571d13hselasky#ifndef _XHCI_H_
31b571d13hselasky#define	_XHCI_H_
32b571d13hselasky
33b571d13hselasky#define	XHCI_MAX_DEVICES	MIN(USB_MAX_DEVICES, 128)
34b571d13hselasky#define	XHCI_MAX_ENDPOINTS	32	/* hardcoded - do not change */
356716d2fhselasky#define	XHCI_MAX_SCRATCHPADS	256	/* theoretical max is 1023 */
36b571d13hselasky#define	XHCI_MAX_EVENTS		(16 * 13)
37b571d13hselasky#define	XHCI_MAX_COMMANDS	(16 * 1)
38b571d13hselasky#define	XHCI_MAX_RSEG		1
39b571d13hselasky#define	XHCI_MAX_TRANSFERS	4
40ce0da37hselasky#if USB_MAX_EP_STREAMS == 8
41ce0da37hselasky#define	XHCI_MAX_STREAMS	8
42ce0da37hselasky#define	XHCI_MAX_STREAMS_LOG	3
43ce0da37hselasky#elif USB_MAX_EP_STREAMS == 1
44ce0da37hselasky#define	XHCI_MAX_STREAMS	1
45ce0da37hselasky#define	XHCI_MAX_STREAMS_LOG	0
46ce0da37hselasky#else
47ce0da37hselasky#error "The USB_MAX_EP_STREAMS value is not supported."
48ce0da37hselasky#endif
49b571d13hselasky#define	XHCI_DEV_CTX_ADDR_ALIGN		64	/* bytes */
50b571d13hselasky#define	XHCI_DEV_CTX_ALIGN		64	/* bytes */
51b571d13hselasky#define	XHCI_INPUT_CTX_ALIGN		64	/* bytes */
52b571d13hselasky#define	XHCI_SLOT_CTX_ALIGN		32	/* bytes */
53b571d13hselasky#define	XHCI_ENDP_CTX_ALIGN		32	/* bytes */
54b571d13hselasky#define	XHCI_STREAM_CTX_ALIGN		16	/* bytes */
55b571d13hselasky#define	XHCI_TRANS_RING_SEG_ALIGN	16	/* bytes */
56b571d13hselasky#define	XHCI_CMD_RING_SEG_ALIGN		64	/* bytes */
57b571d13hselasky#define	XHCI_EVENT_RING_SEG_ALIGN	64	/* bytes */
58b571d13hselasky#define	XHCI_SCRATCH_BUF_ARRAY_ALIGN	64	/* bytes */
59b571d13hselasky#define	XHCI_SCRATCH_BUFFER_ALIGN	USB_PAGE_SIZE
60b571d13hselasky#define	XHCI_TRB_ALIGN			16	/* bytes */
61b571d13hselasky#define	XHCI_TD_ALIGN			64	/* bytes */
62b571d13hselasky#define	XHCI_PAGE_SIZE			4096	/* bytes */
63b571d13hselasky
64b571d13hselaskystruct xhci_dev_ctx_addr {
65b571d13hselasky	volatile uint64_t	qwBaaDevCtxAddr[USB_MAX_DEVICES + 1];
66b571d13hselasky	struct {
67b571d13hselasky		volatile uint64_t dummy;
68b571d13hselasky	} __aligned(64) padding;
69b571d13hselasky	volatile uint64_t	qwSpBufPtr[XHCI_MAX_SCRATCHPADS];
70b571d13hselasky};
71b571d13hselasky
72b571d13hselasky#define	XHCI_EPNO2EPID(x) \
73b571d13hselasky    ((((x) & UE_DIR_IN) ? 1 : 0) | (2 * ((x) & UE_ADDR)))
74b571d13hselasky
75b571d13hselaskystruct xhci_slot_ctx {
76b571d13hselasky	volatile uint32_t	dwSctx0;
77b571d13hselasky#define	XHCI_SCTX_0_ROUTE_SET(x)		((x) & 0xFFFFF)
78b571d13hselasky#define	XHCI_SCTX_0_ROUTE_GET(x)		((x) & 0xFFFFF)
79b571d13hselasky#define	XHCI_SCTX_0_SPEED_SET(x)		(((x) & 0xF) << 20)
80b571d13hselasky#define	XHCI_SCTX_0_SPEED_GET(x)		(((x) >> 20) & 0xF)
81b571d13hselasky#define	XHCI_SCTX_0_MTT_SET(x)			(((x) & 0x1) << 25)
82b571d13hselasky#define	XHCI_SCTX_0_MTT_GET(x)			(((x) >> 25) & 0x1)
83b571d13hselasky#define	XHCI_SCTX_0_HUB_SET(x)			(((x) & 0x1) << 26)
84b571d13hselasky#define	XHCI_SCTX_0_HUB_GET(x)			(((x) >> 26) & 0x1)
85b571d13hselasky#define	XHCI_SCTX_0_CTX_NUM_SET(x)		(((x) & 0x1F) << 27)
86b571d13hselasky#define	XHCI_SCTX_0_CTX_NUM_GET(x)		(((x) >> 27) & 0x1F)
87b571d13hselasky	volatile uint32_t	dwSctx1;
88b571d13hselasky#define	XHCI_SCTX_1_MAX_EL_SET(x)		((x) & 0xFFFF)
89b571d13hselasky#define	XHCI_SCTX_1_MAX_EL_GET(x)		((x) & 0xFFFF)
90b571d13hselasky#define	XHCI_SCTX_1_RH_PORT_SET(x)		(((x) & 0xFF) << 16)
91b571d13hselasky#define	XHCI_SCTX_1_RH_PORT_GET(x)		(((x) >> 16) & 0xFF)
92b571d13hselasky#define	XHCI_SCTX_1_NUM_PORTS_SET(x)		(((x) & 0xFF) << 24)
93b571d13hselasky#define	XHCI_SCTX_1_NUM_PORTS_GET(x)		(((x) >> 24) & 0xFF)
94b571d13hselasky	volatile uint32_t	dwSctx2;
95b571d13hselasky#define	XHCI_SCTX_2_TT_HUB_SID_SET(x)		((x) & 0xFF)
96b571d13hselasky#define	XHCI_SCTX_2_TT_HUB_SID_GET(x)		((x) & 0xFF)
97b571d13hselasky#define	XHCI_SCTX_2_TT_PORT_NUM_SET(x)		(((x) & 0xFF) << 8)
98b571d13hselasky#define	XHCI_SCTX_2_TT_PORT_NUM_GET(x)		(((x) >> 8) & 0xFF)
99b571d13hselasky#define	XHCI_SCTX_2_TT_THINK_TIME_SET(x)	(((x) & 0x3) << 16)
100b571d13hselasky#define	XHCI_SCTX_2_TT_THINK_TIME_GET(x)	(((x) >> 16) & 0x3)
101b571d13hselasky#define	XHCI_SCTX_2_IRQ_TARGET_SET(x)		(((x) & 0x3FF) << 22)
102b571d13hselasky#define	XHCI_SCTX_2_IRQ_TARGET_GET(x)		(((x) >> 22) & 0x3FF)
103b571d13hselasky	volatile uint32_t	dwSctx3;
104b571d13hselasky#define	XHCI_SCTX_3_DEV_ADDR_SET(x)		((x) & 0xFF)
105b571d13hselasky#define	XHCI_SCTX_3_DEV_ADDR_GET(x)		((x) & 0xFF)
106b571d13hselasky#define	XHCI_SCTX_3_SLOT_STATE_SET(x)		(((x) & 0x1F) << 27)
107b571d13hselasky#define	XHCI_SCTX_3_SLOT_STATE_GET(x)		(((x) >> 27) & 0x1F)
108b571d13hselasky	volatile uint32_t	dwSctx4;
109b571d13hselasky	volatile uint32_t	dwSctx5;
110b571d13hselasky	volatile uint32_t	dwSctx6;
111b571d13hselasky	volatile uint32_t	dwSctx7;
112b571d13hselasky};
113b571d13hselasky
114b571d13hselaskystruct xhci_endp_ctx {
115b571d13hselasky	volatile uint32_t	dwEpCtx0;
116b571d13hselasky#define	XHCI_EPCTX_0_EPSTATE_SET(x)		((x) & 0x7)
117b571d13hselasky#define	XHCI_EPCTX_0_EPSTATE_GET(x)		((x) & 0x7)
1183b97ae3hselasky#define	XHCI_EPCTX_0_EPSTATE_DISABLED		0
1193b97ae3hselasky#define	XHCI_EPCTX_0_EPSTATE_RUNNING		1
1203b97ae3hselasky#define	XHCI_EPCTX_0_EPSTATE_HALTED		2
1213b97ae3hselasky#define	XHCI_EPCTX_0_EPSTATE_STOPPED		3
1223b97ae3hselasky#define	XHCI_EPCTX_0_EPSTATE_ERROR		4
1233b97ae3hselasky#define	XHCI_EPCTX_0_EPSTATE_RESERVED_5		5
1243b97ae3hselasky#define	XHCI_EPCTX_0_EPSTATE_RESERVED_6		6
1253b97ae3hselasky#define	XHCI_EPCTX_0_EPSTATE_RESERVED_7		7
126b571d13hselasky#define	XHCI_EPCTX_0_MULT_SET(x)		(((x) & 0x3) << 8)
127b571d13hselasky#define	XHCI_EPCTX_0_MULT_GET(x)		(((x) >> 8) & 0x3)
128b571d13hselasky#define	XHCI_EPCTX_0_MAXP_STREAMS_SET(x)	(((x) & 0x1F) << 10)
129b571d13hselasky#define	XHCI_EPCTX_0_MAXP_STREAMS_GET(x)	(((x) >> 10) & 0x1F)
130b571d13hselasky#define	XHCI_EPCTX_0_LSA_SET(x)			(((x) & 0x1) << 15)
131b571d13hselasky#define	XHCI_EPCTX_0_LSA_GET(x)			(((x) >> 15) & 0x1)
132b571d13hselasky#define	XHCI_EPCTX_0_IVAL_SET(x)		(((x) & 0xFF) << 16)
133b571d13hselasky#define	XHCI_EPCTX_0_IVAL_GET(x)		(((x) >> 16) & 0xFF)
134b571d13hselasky	volatile uint32_t	dwEpCtx1;
135b571d13hselasky#define	XHCI_EPCTX_1_CERR_SET(x)		(((x) & 0x3) << 1)
136b571d13hselasky#define	XHCI_EPCTX_1_CERR_GET(x)		(((x) >> 1) & 0x3)
137b571d13hselasky#define	XHCI_EPCTX_1_EPTYPE_SET(x)		(((x) & 0x7) << 3)
138b571d13hselasky#define	XHCI_EPCTX_1_EPTYPE_GET(x)		(((x) >> 3) & 0x7)
139b571d13hselasky#define	XHCI_EPCTX_1_HID_SET(x)			(((x) & 0x1) << 7)
140b571d13hselasky#define	XHCI_EPCTX_1_HID_GET(x)			(((x) >> 7) & 0x1)
141b571d13hselasky#define	XHCI_EPCTX_1_MAXB_SET(x)		(((x) & 0xFF) << 8)
142b571d13hselasky#define	XHCI_EPCTX_1_MAXB_GET(x)		(((x) >> 8) & 0xFF)
143b571d13hselasky#define	XHCI_EPCTX_1_MAXP_SIZE_SET(x)		(((x) & 0xFFFF) << 16)
144b571d13hselasky#define	XHCI_EPCTX_1_MAXP_SIZE_GET(x)		(((x) >> 16) & 0xFFFF)
145b571d13hselasky	volatile uint64_t	qwEpCtx2;
146b571d13hselasky#define	XHCI_EPCTX_2_DCS_SET(x)			((x) & 0x1)
147b571d13hselasky#define	XHCI_EPCTX_2_DCS_GET(x)			((x) & 0x1)
148b571d13hselasky#define	XHCI_EPCTX_2_TR_DQ_PTR_MASK		0xFFFFFFFFFFFFFFF0U
149b571d13hselasky	volatile uint32_t	dwEpCtx4;
150b571d13hselasky#define	XHCI_EPCTX_4_AVG_TRB_LEN_SET(x)		((x) & 0xFFFF)
151b571d13hselasky#define	XHCI_EPCTX_4_AVG_TRB_LEN_GET(x)		((x) & 0xFFFF)
152b571d13hselasky#define	XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x)	(((x) & 0xFFFF) << 16)
153b571d13hselasky#define	XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x)	(((x) >> 16) & 0xFFFF)
154b571d13hselasky	volatile uint32_t	dwEpCtx5;
155b571d13hselasky	volatile uint32_t	dwEpCtx6;
156b571d13hselasky	volatile uint32_t	dwEpCtx7;
157b571d13hselasky};
158b571d13hselasky
159b571d13hselaskystruct xhci_input_ctx {
160b571d13hselasky#define	XHCI_INCTX_NON_CTRL_MASK	0xFFFFFFFCU
161b571d13hselasky	volatile uint32_t	dwInCtx0;
162b571d13hselasky#define	XHCI_INCTX_0_DROP_MASK(n)	(1U << (n))
163b571d13hselasky	volatile uint32_t	dwInCtx1;
164b571d13hselasky#define	XHCI_INCTX_1_ADD_MASK(n)	(1U << (n))
165b571d13hselasky	volatile uint32_t	dwInCtx2;
166b571d13hselasky	volatile uint32_t	dwInCtx3;
167b571d13hselasky	volatile uint32_t	dwInCtx4;
168b571d13hselasky	volatile uint32_t	dwInCtx5;
169b571d13hselasky	volatile uint32_t	dwInCtx6;
170b571d13hselasky	volatile uint32_t	dwInCtx7;
171b571d13hselasky};
172b571d13hselasky
173b571d13hselaskystruct xhci_input_dev_ctx {
174b571d13hselasky	struct xhci_input_ctx	ctx_input;
175b571d13hselasky	struct xhci_slot_ctx	ctx_slot;
176b571d13hselasky	struct xhci_endp_ctx	ctx_ep[XHCI_MAX_ENDPOINTS - 1];
177b571d13hselasky};
178b571d13hselasky
179b571d13hselaskystruct xhci_dev_ctx {
180b571d13hselasky	struct xhci_slot_ctx	ctx_slot;
181b571d13hselasky	struct xhci_endp_ctx	ctx_ep[XHCI_MAX_ENDPOINTS - 1];
182b571d13hselasky} __aligned(XHCI_DEV_CTX_ALIGN);
183b571d13hselasky
184b571d13hselaskystruct xhci_stream_ctx {
185b571d13hselasky	volatile uint64_t	qwSctx0;
186b571d13hselasky#define	XHCI_SCTX_0_DCS_GET(x)		((x) & 0x1)
187b571d13hselasky#define	XHCI_SCTX_0_DCS_SET(x)		((x) & 0x1)
188b571d13hselasky#define	XHCI_SCTX_0_SCT_SET(x)		(((x) & 0x7) << 1)
189b571d13hselasky#define	XHCI_SCTX_0_SCT_GET(x)		(((x) >> 1) & 0x7)
190b571d13hselasky#define	XHCI_SCTX_0_SCT_SEC_TR_RING	0x0
191b571d13hselasky#define	XHCI_SCTX_0_SCT_PRIM_TR_RING	0x1
192b571d13hselasky#define	XHCI_SCTX_0_SCT_PRIM_SSA_8	0x2
193b571d13hselasky#define	XHCI_SCTX_0_SCT_PRIM_SSA_16	0x3
194b571d13hselasky#define	XHCI_SCTX_0_SCT_PRIM_SSA_32	0x4
195b571d13hselasky#define	XHCI_SCTX_0_SCT_PRIM_SSA_64	0x5
196b571d13hselasky#define	XHCI_SCTX_0_SCT_PRIM_SSA_128	0x6
197b571d13hselasky#define	XHCI_SCTX_0_SCT_PRIM_SSA_256	0x7
198b571d13hselasky#define	XHCI_SCTX_0_TR_DQ_PTR_MASK	0xFFFFFFFFFFFFFFF0U
199b571d13hselasky	volatile uint32_t	dwSctx2;
200b571d13hselasky	volatile uint32_t	dwSctx3;
201b571d13hselasky};
202b571d13hselasky
203b571d13hselaskystruct xhci_trb {
204b571d13hselasky	volatile uint64_t	qwTrb0;
20580800behselasky#define	XHCI_TRB_0_DIR_IN_MASK		(0x80ULL << 0)
206b571d13hselasky#define	XHCI_TRB_0_WLENGTH_MASK		(0xFFFFULL << 48)
207b571d13hselasky	volatile uint32_t	dwTrb2;
208b571d13hselasky#define	XHCI_TRB_2_ERROR_GET(x)		(((x) >> 24) & 0xFF)
209b571d13hselasky#define	XHCI_TRB_2_ERROR_SET(x)		(((x) & 0xFF) << 24)
210b571d13hselasky#define	XHCI_TRB_2_TDSZ_GET(x)		(((x) >> 17) & 0x1F)
211b571d13hselasky#define	XHCI_TRB_2_TDSZ_SET(x)		(((x) & 0x1F) << 17)
212b571d13hselasky#define	XHCI_TRB_2_REM_GET(x)		((x) & 0xFFFFFF)
213b571d13hselasky#define	XHCI_TRB_2_REM_SET(x)		((x) & 0xFFFFFF)
214b571d13hselasky#define	XHCI_TRB_2_BYTES_GET(x)		((x) & 0x1FFFF)
215b571d13hselasky#define	XHCI_TRB_2_BYTES_SET(x)		((x) & 0x1FFFF)
216b571d13hselasky#define	XHCI_TRB_2_IRQ_GET(x)		(((x) >> 22) & 0x3FF)
217b571d13hselasky#define	XHCI_TRB_2_IRQ_SET(x)		(((x) & 0x3FF) << 22)
218b571d13hselasky#define	XHCI_TRB_2_STREAM_GET(x)	(((x) >> 16) & 0xFFFF)
219b571d13hselasky#define	XHCI_TRB_2_STREAM_SET(x)	(((x) & 0xFFFF) << 16)
220b571d13hselasky
221b571d13hselasky	volatile uint32_t	dwTrb3;
222b571d13hselasky#define	XHCI_TRB_3_TYPE_GET(x)		(((x) >> 10) & 0x3F)
223b571d13hselasky#define	XHCI_TRB_3_TYPE_SET(x)		(((x) & 0x3F) << 10)
224b571d13hselasky#define	XHCI_TRB_3_CYCLE_BIT		(1U << 0)
225b571d13hselasky#define	XHCI_TRB_3_TC_BIT		(1U << 1)	/* command ring only */
226b571d13hselasky#define	XHCI_TRB_3_ENT_BIT		(1U << 1)	/* transfer ring only */
227b571d13hselasky#define	XHCI_TRB_3_ISP_BIT		(1U << 2)
228b571d13hselasky#define	XHCI_TRB_3_NSNOOP_BIT		(1U << 3)
229b571d13hselasky#define	XHCI_TRB_3_CHAIN_BIT		(1U << 4)
230b571d13hselasky#define	XHCI_TRB_3_IOC_BIT		(1U << 5)
231b571d13hselasky#define	XHCI_TRB_3_IDT_BIT		(1U << 6)
232b571d13hselasky#define	XHCI_TRB_3_TBC_GET(x)		(((x) >> 7) & 3)
233b571d13hselasky#define	XHCI_TRB_3_TBC_SET(x)		(((x) & 3) << 7)
234b571d13hselasky#define	XHCI_TRB_3_BEI_BIT		(1U << 9)
235b571d13hselasky#define	XHCI_TRB_3_DCEP_BIT		(1U << 9)
236b571d13hselasky#define	XHCI_TRB_3_PRSV_BIT		(1U << 9)
237b571d13hselasky#define	XHCI_TRB_3_BSR_BIT		(1U << 9)
238b571d13hselasky#define	XHCI_TRB_3_TRT_MASK		(3U << 16)
239b571d13hselasky#define	XHCI_TRB_3_TRT_NONE		(0U << 16)
240b571d13hselasky#define	XHCI_TRB_3_TRT_OUT		(2U << 16)
241b571d13hselasky#define	XHCI_TRB_3_TRT_IN		(3U << 16)
242b571d13hselasky#define	XHCI_TRB_3_DIR_IN		(1U << 16)
243b571d13hselasky#define	XHCI_TRB_3_TLBPC_GET(x)		(((x) >> 16) & 0xF)
244b571d13hselasky#define	XHCI_TRB_3_TLBPC_SET(x)		(((x) & 0xF) << 16)
245b571d13hselasky#define	XHCI_TRB_3_EP_GET(x)		(((x) >> 16) & 0x1F)
246b571d13hselasky#define	XHCI_TRB_3_EP_SET(x)		(((x) & 0x1F) << 16)
247b571d13hselasky#define	XHCI_TRB_3_FRID_GET(x)		(((x) >> 20) & 0x7FF)
248b571d13hselasky#define	XHCI_TRB_3_FRID_SET(x)		(((x) & 0x7FF) << 20)
249b571d13hselasky#define	XHCI_TRB_3_ISO_SIA_BIT		(1U << 31)
250b571d13hselasky#define	XHCI_TRB_3_SUSP_EP_BIT		(1U << 23)
251b571d13hselasky#define	XHCI_TRB_3_SLOT_GET(x)		(((x) >> 24) & 0xFF)
252b571d13hselasky#define	XHCI_TRB_3_SLOT_SET(x)		(((x) & 0xFF) << 24)
253b571d13hselasky
254b571d13hselasky/* Commands */
255b571d13hselasky#define	XHCI_TRB_TYPE_RESERVED		0x00
256b571d13hselasky#define	XHCI_TRB_TYPE_NORMAL		0x01
257b571d13hselasky#define	XHCI_TRB_TYPE_SETUP_STAGE	0x02
258b571d13hselasky#define	XHCI_TRB_TYPE_DATA_STAGE	0x03
259b571d13hselasky#define	XHCI_TRB_TYPE_STATUS_STAGE	0x04
260b571d13hselasky#define	XHCI_TRB_TYPE_ISOCH		0x05
261b571d13hselasky#define	XHCI_TRB_TYPE_LINK		0x06
262b571d13hselasky#define	XHCI_TRB_TYPE_EVENT_DATA	0x07
263b571d13hselasky#define	XHCI_TRB_TYPE_NOOP		0x08
264b571d13hselasky#define	XHCI_TRB_TYPE_ENABLE_SLOT	0x09
265b571d13hselasky#define	XHCI_TRB_TYPE_DISABLE_SLOT	0x0A
266b571d13hselasky#define	XHCI_TRB_TYPE_ADDRESS_DEVICE	0x0B
267b571d13hselasky#define	XHCI_TRB_TYPE_CONFIGURE_EP	0x0C
268b571d13hselasky#define	XHCI_TRB_TYPE_EVALUATE_CTX	0x0D
269b571d13hselasky#define	XHCI_TRB_TYPE_RESET_EP		0x0E
270b571d13hselasky#define	XHCI_TRB_TYPE_STOP_EP		0x0F
271b571d13hselasky#define	XHCI_TRB_TYPE_SET_TR_DEQUEUE	0x10
272b571d13hselasky#define	XHCI_TRB_TYPE_RESET_DEVICE	0x11
273b571d13hselasky#define	XHCI_TRB_TYPE_FORCE_EVENT	0x12
274b571d13hselasky#define	XHCI_TRB_TYPE_NEGOTIATE_BW	0x13
275b571d13hselasky#define	XHCI_TRB_TYPE_SET_LATENCY_TOL  	0x14
276b571d13hselasky#define	XHCI_TRB_TYPE_GET_PORT_BW	0x15
277b571d13hselasky#define	XHCI_TRB_TYPE_FORCE_HEADER	0x16
278b571d13hselasky#define	XHCI_TRB_TYPE_NOOP_CMD		0x17
279b571d13hselasky
280b571d13hselasky/* Events */
281b571d13hselasky#define	XHCI_TRB_EVENT_TRANSFER		0x20
282b571d13hselasky#define	XHCI_TRB_EVENT_CMD_COMPLETE	0x21
283b571d13hselasky#define	XHCI_TRB_EVENT_PORT_STS_CHANGE  0x22
284b571d13hselasky#define	XHCI_TRB_EVENT_BW_REQUEST      	0x23
285b571d13hselasky#define	XHCI_TRB_EVENT_DOORBELL		0x24
286b571d13hselasky#define	XHCI_TRB_EVENT_HOST_CTRL	0x25
287b571d13hselasky#define	XHCI_TRB_EVENT_DEVICE_NOTIFY	0x26
288b571d13hselasky#define	XHCI_TRB_EVENT_MFINDEX_WRAP	0x27
289b571d13hselasky
290b571d13hselasky/* Error codes */
291b571d13hselasky#define	XHCI_TRB_ERROR_INVALID		0x00
292b571d13hselasky#define	XHCI_TRB_ERROR_SUCCESS		0x01
293b571d13hselasky#define	XHCI_TRB_ERROR_DATA_BUF		0x02
294b571d13hselasky#define	XHCI_TRB_ERROR_BABBLE		0x03
295b571d13hselasky#define	XHCI_TRB_ERROR_XACT		0x04
296b571d13hselasky#define	XHCI_TRB_ERROR_TRB		0x05
297b571d13hselasky#define	XHCI_TRB_ERROR_STALL		0x06
298b571d13hselasky#define	XHCI_TRB_ERROR_RESOURCE		0x07
299b571d13hselasky#define	XHCI_TRB_ERROR_BANDWIDTH	0x08
300b571d13hselasky#define	XHCI_TRB_ERROR_NO_SLOTS		0x09
301b571d13hselasky#define	XHCI_TRB_ERROR_STREAM_TYPE	0x0A
302b571d13hselasky#define	XHCI_TRB_ERROR_SLOT_NOT_ON	0x0B
303b571d13hselasky#define	XHCI_TRB_ERROR_ENDP_NOT_ON	0x0C
304b571d13hselasky#define	XHCI_TRB_ERROR_SHORT_PKT	0x0D
305b571d13hselasky#define	XHCI_TRB_ERROR_RING_UNDERRUN	0x0E
306b571d13hselasky#define	XHCI_TRB_ERROR_RING_OVERRUN	0x0F
307b571d13hselasky#define	XHCI_TRB_ERROR_VF_RING_FULL	0x10
308b571d13hselasky#define	XHCI_TRB_ERROR_PARAMETER	0x11
309b571d13hselasky#define	XHCI_TRB_ERROR_BW_OVERRUN	0x12
310b571d13hselasky#define	XHCI_TRB_ERROR_CONTEXT_STATE	0x13
311b571d13hselasky#define	XHCI_TRB_ERROR_NO_PING_RESP	0x14
312b571d13hselasky#define	XHCI_TRB_ERROR_EV_RING_FULL	0x15
313b571d13hselasky#define	XHCI_TRB_ERROR_INCOMPAT_DEV	0x16
314b571d13hselasky#define	XHCI_TRB_ERROR_MISSED_SERVICE	0x17
315b571d13hselasky#define	XHCI_TRB_ERROR_CMD_RING_STOP	0x18
316b571d13hselasky#define	XHCI_TRB_ERROR_CMD_ABORTED	0x19
317b571d13hselasky#define	XHCI_TRB_ERROR_STOPPED		0x1A
318b571d13hselasky#define	XHCI_TRB_ERROR_LENGTH		0x1B
319b571d13hselasky#define	XHCI_TRB_ERROR_BAD_MELAT	0x1D
320b571d13hselasky#define	XHCI_TRB_ERROR_ISOC_OVERRUN	0x1F
321b571d13hselasky#define	XHCI_TRB_ERROR_EVENT_LOST	0x20
322b571d13hselasky#define	XHCI_TRB_ERROR_UNDEFINED	0x21
323b571d13hselasky#define	XHCI_TRB_ERROR_INVALID_SID	0x22
324b571d13hselasky#define	XHCI_TRB_ERROR_SEC_BW		0x23
325b571d13hselasky#define	XHCI_TRB_ERROR_SPLIT_XACT	0x24
326b571d13hselasky} __aligned(4);
327b571d13hselasky
328b571d13hselaskystruct xhci_dev_endpoint_trbs {
329ed9fc36hselasky	struct xhci_trb		trb[(XHCI_MAX_STREAMS *
330ed9fc36hselasky	    XHCI_MAX_TRANSFERS) + XHCI_MAX_STREAMS];
331b571d13hselasky};
332b571d13hselasky
333fb3916chselasky#if (USB_PAGE_SIZE < 4096)
334e4c6cd0hselasky#error "The XHCI driver needs a pagesize above or equal to 4K"
335fb3916chselasky#endif
336fb3916chselasky
337fb3916chselasky/* Define the maximum payload which we will handle in a single TRB */
338fb3916chselasky#define	XHCI_TD_PAYLOAD_MAX	65536	/* bytes */
339fb3916chselasky
340fb3916chselasky/* Define the maximum payload of a single scatter-gather list element */
341fb3916chselasky#define	XHCI_TD_PAGE_SIZE \
342fb3916chselasky  ((USB_PAGE_SIZE < XHCI_TD_PAYLOAD_MAX) ? USB_PAGE_SIZE : XHCI_TD_PAYLOAD_MAX)
343fb3916chselasky
344fb3916chselasky/* Define the maximum length of the scatter-gather list */
345fb3916chselasky#define	XHCI_TD_PAGE_NBUF \
346fb3916chselasky  (((XHCI_TD_PAYLOAD_MAX + XHCI_TD_PAGE_SIZE - 1) / XHCI_TD_PAGE_SIZE) + 1)
347b571d13hselasky
348b571d13hselaskystruct xhci_td {
349fb3916chselasky	/* one LINK TRB has been added to the TRB array */
350b571d13hselasky	struct xhci_trb		td_trb[XHCI_TD_PAGE_NBUF + 1];
351b571d13hselasky
352b571d13hselasky/*
353b571d13hselasky * Extra information needed:
354b571d13hselasky */
355b571d13hselasky	uint64_t		td_self;
356b571d13hselasky	struct xhci_td		*next;
357b571d13hselasky	struct xhci_td		*alt_next;
358b571d13hselasky	struct xhci_td		*obj_next;
359b571d13hselasky	struct usb_page_cache	*page_cache;
360b571d13hselasky	uint32_t		len;
361b571d13hselasky	uint32_t		remainder;
362b571d13hselasky	uint8_t			ntrb;
363b571d13hselasky	uint8_t			status;
364b571d13hselasky} __aligned(XHCI_TRB_ALIGN);
365b571d13hselasky
366b571d13hselaskystruct xhci_command {
367b571d13hselasky	struct xhci_trb		trb;
368b571d13hselasky	TAILQ_ENTRY(xhci_command) entry;
369b571d13hselasky};
370b571d13hselasky
371b571d13hselaskystruct xhci_event_ring_seg {
372b571d13hselasky	volatile uint64_t	qwEvrsTablePtr;
373b571d13hselasky	volatile uint32_t	dwEvrsTableSize;
374b571d13hselasky	volatile uint32_t	dwEvrsReserved;
375b571d13hselasky};
376b571d13hselasky
377b571d13hselaskystruct xhci_hw_root {
378b571d13hselasky	struct xhci_event_ring_seg	hwr_ring_seg[XHCI_MAX_RSEG];
379b571d13hselasky	struct {
380b571d13hselasky		volatile uint64_t dummy;
381b571d13hselasky	} __aligned(64)			padding;
382b571d13hselasky	struct xhci_trb			hwr_events[XHCI_MAX_EVENTS];
383b571d13hselasky	struct xhci_trb			hwr_commands[XHCI_MAX_COMMANDS];
384b571d13hselasky};
385b571d13hselasky
386b571d13hselaskystruct xhci_endpoint_ext {
387b571d13hselasky	struct xhci_trb		*trb;
388ce0da37hselasky	struct usb_xfer		*xfer[XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS];
389b571d13hselasky	struct usb_page_cache	*page_cache;
390b571d13hselasky	uint64_t		physaddr;
391ce0da37hselasky	uint8_t			trb_used[XHCI_MAX_STREAMS];
392ce0da37hselasky	uint8_t			trb_index[XHCI_MAX_STREAMS];
393b571d13hselasky	uint8_t			trb_halted;
394b571d13hselasky	uint8_t			trb_running;
3957b42f3fhselasky	uint8_t			trb_ep_mode;
3968f9526chselasky	uint8_t			trb_ep_maxp;
397b571d13hselasky};
398b571d13hselasky
399b571d13hselaskyenum {
400b571d13hselasky	XHCI_ST_DISABLED,
401b571d13hselasky	XHCI_ST_ENABLED,
402b571d13hselasky	XHCI_ST_DEFAULT,
403b571d13hselasky	XHCI_ST_ADDRESSED,
404b571d13hselasky	XHCI_ST_CONFIGURED,
405b571d13hselasky	XHCI_ST_MAX
406b571d13hselasky};
407b571d13hselasky
408b571d13hselaskystruct xhci_hw_dev {
409b571d13hselasky	struct usb_page_cache	device_pc;
410b571d13hselasky	struct usb_page_cache	input_pc;
411ed9fc36hselasky	struct usb_page_cache	endpoint_pc[XHCI_MAX_ENDPOINTS];
412b571d13hselasky
413b571d13hselasky	struct usb_page		device_pg;
414b571d13hselasky	struct usb_page		input_pg;
415ed9fc36hselasky	struct usb_page		endpoint_pg[XHCI_MAX_ENDPOINTS];
416b571d13hselasky
417b571d13hselasky	struct xhci_endpoint_ext endp[XHCI_MAX_ENDPOINTS];
418b571d13hselasky
419a3c9c18hselasky	uint32_t		ep_configured;
420a3c9c18hselasky
421b571d13hselasky	uint8_t			state;
422b571d13hselasky	uint8_t			nports;
423b571d13hselasky	uint8_t			tt;
424fd7b9e3hselasky	uint8_t			context_num;
425b571d13hselasky};
426b571d13hselasky
427b571d13hselaskystruct xhci_hw_softc {
428b571d13hselasky	struct usb_page_cache	root_pc;
429b571d13hselasky	struct usb_page_cache	ctx_pc;
430b571d13hselasky	struct usb_page_cache	scratch_pc[XHCI_MAX_SCRATCHPADS];
431b571d13hselasky
432b571d13hselasky	struct usb_page		root_pg;
433b571d13hselasky	struct usb_page		ctx_pg;
434b571d13hselasky	struct usb_page		scratch_pg[XHCI_MAX_SCRATCHPADS];
435b571d13hselasky
436b571d13hselasky	struct xhci_hw_dev	devs[XHCI_MAX_DEVICES + 1];
437b571d13hselasky};
438b571d13hselasky
439b571d13hselaskystruct xhci_config_desc {
440b571d13hselasky	struct usb_config_descriptor		confd;
441b571d13hselasky	struct usb_interface_descriptor		ifcd;
442b571d13hselasky	struct usb_endpoint_descriptor		endpd;
443b571d13hselasky	struct usb_endpoint_ss_comp_descriptor	endpcd;
444b571d13hselasky} __packed;
445b571d13hselasky
446b571d13hselaskystruct xhci_bos_desc {
447b571d13hselasky	struct usb_bos_descriptor		bosd;
448b571d13hselasky	struct usb_devcap_usb2ext_descriptor	usb2extd;
449b571d13hselasky	struct usb_devcap_ss_descriptor		usbdcd;
450b571d13hselasky	struct usb_devcap_container_id_descriptor cidd;
451b571d13hselasky} __packed;
452b571d13hselasky
453b571d13hselaskyunion xhci_hub_desc {
454b571d13hselasky	struct usb_status		stat;
455b571d13hselasky	struct usb_port_status		ps;
456b571d13hselasky	struct usb_hub_ss_descriptor	hubd;
457b571d13hselasky	uint8_t				temp[128];
458b571d13hselasky};
459b571d13hselasky
460eaecb3dhselaskytypedef int (xhci_port_route_t)(device_t, uint32_t, uint32_t);
461eaecb3dhselasky
462b571d13hselaskystruct xhci_softc {
463b571d13hselasky	struct xhci_hw_softc	sc_hw;
464b571d13hselasky	/* base device */
465b571d13hselasky	struct usb_bus		sc_bus;
4662e6231fhselasky	/* configure message */
467b571d13hselasky	struct usb_bus_msg	sc_config_msg[2];
468b571d13hselasky
4695311e12hselasky	struct usb_callout	sc_callout;
4705311e12hselasky
471eaecb3dhselasky	xhci_port_route_t	*sc_port_route;
472eaecb3dhselasky
473b571d13hselasky	union xhci_hub_desc	sc_hub_desc;
474b571d13hselasky
475b571d13hselasky	struct cv		sc_cmd_cv;
476b571d13hselasky	struct sx		sc_cmd_sx;
477b571d13hselasky
478b571d13hselasky	struct usb_device	*sc_devices[XHCI_MAX_DEVICES];
479b571d13hselasky	struct resource		*sc_io_res;
480b571d13hselasky	struct resource		*sc_irq_res;
4815badcaaandrew	struct resource		*sc_msix_res;
482b571d13hselasky
483b571d13hselasky	void			*sc_intr_hdl;
484b571d13hselasky	bus_size_t		sc_io_size;
485b571d13hselasky	bus_space_tag_t		sc_io_tag;
486b571d13hselasky	bus_space_handle_t	sc_io_hdl;
487b571d13hselasky	/* last pending command address */
488b571d13hselasky	uint64_t		sc_cmd_addr;
489b571d13hselasky	/* result of command */
490b571d13hselasky	uint32_t		sc_cmd_result[2];
491b571d13hselasky 	/* copy of cmd register */
492b571d13hselasky	uint32_t		sc_cmd;
493b571d13hselasky	/* worst case exit latency */
494b571d13hselasky	uint32_t		sc_exit_lat_max;
495b571d13hselasky
496b571d13hselasky	/* offset to operational registers */
497b571d13hselasky	uint32_t		sc_oper_off;
498b571d13hselasky	/* offset to capability registers */
499b571d13hselasky	uint32_t		sc_capa_off;
500b571d13hselasky	/* offset to runtime registers */
501b571d13hselasky	uint32_t		sc_runt_off;
502b571d13hselasky	/* offset to doorbell registers */
503b571d13hselasky	uint32_t		sc_door_off;
504b571d13hselasky
505b571d13hselasky	/* chip specific */
506b571d13hselasky	uint16_t		sc_erst_max;
507b571d13hselasky	uint16_t		sc_event_idx;
508b571d13hselasky	uint16_t		sc_command_idx;
509d2748c8hselasky	uint16_t		sc_imod_default;
510b571d13hselasky
51115bbf75hselasky	/* number of scratch pages */
51215bbf75hselasky	uint16_t		sc_noscratch;
51315bbf75hselasky
514b571d13hselasky	uint8_t			sc_event_ccs;
515b571d13hselasky	uint8_t			sc_command_ccs;
516b571d13hselasky	/* number of XHCI device slots */
517b571d13hselasky	uint8_t			sc_noslot;
518b571d13hselasky	/* number of ports on root HUB */
519b571d13hselasky	uint8_t			sc_noport;
520b571d13hselasky	/* root HUB device configuration */
521b571d13hselasky	uint8_t			sc_conf;
5220ec6a6bhselasky	/* step status stage of all control transfers */
5230ec6a6bhselasky	uint8_t			sc_ctlstep;
524de588echselasky	/* root HUB port event bitmap, max 256 ports */
525de588echselasky	uint8_t			sc_hub_idata[32];
526b571d13hselasky
5272709677hselasky	/* size of context */
5282709677hselasky	uint8_t			sc_ctx_is_64_byte;
5292709677hselasky
530b571d13hselasky	/* vendor string for root HUB */
531b571d13hselasky	char			sc_vendor[16];
532b571d13hselasky};
533b571d13hselasky
534b571d13hselasky#define	XHCI_CMD_LOCK(sc)	sx_xlock(&(sc)->sc_cmd_sx)
535b571d13hselasky#define	XHCI_CMD_UNLOCK(sc)	sx_xunlock(&(sc)->sc_cmd_sx)
536b571d13hselasky#define	XHCI_CMD_ASSERT_LOCKED(sc) sx_assert(&(sc)->sc_cmd_sx, SA_LOCKED)
537b571d13hselasky
538b571d13hselasky/* prototypes */
539b571d13hselasky
5405311e12hselaskyuint8_t 	xhci_use_polling(void);
541b571d13hselaskyusb_error_t xhci_halt_controller(struct xhci_softc *);
54269cdfebhselaskyusb_error_t xhci_reset_controller(struct xhci_softc *);
5438dc95f1hselaskyusb_error_t xhci_init(struct xhci_softc *, device_t, uint8_t);
544b571d13hselaskyusb_error_t xhci_start_controller(struct xhci_softc *);
545b571d13hselaskyvoid	xhci_interrupt(struct xhci_softc *);
546b571d13hselaskyvoid	xhci_uninit(struct xhci_softc *);
5478c64fedandrewint	xhci_pci_attach(device_t);
5488c64fedandrew
5498c64fedandrewDECLARE_CLASS(xhci_pci_driver);
550b571d13hselasky
551b571d13hselasky#endif					/* _XHCI_H_ */
552