1/*-
2 * Copyright (c) 2015-2016 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD$");
33
34#include "efx.h"
35#include "efx_impl.h"
36
37
38#if EFSYS_OPT_MEDFORD
39
40static	__checkReturn	efx_rc_t
41medford_nic_get_required_pcie_bandwidth(
42	__in		efx_nic_t *enp,
43	__out		uint32_t *bandwidth_mbpsp)
44{
45	uint32_t bandwidth;
46	efx_rc_t rc;
47
48	if ((rc = ef10_nic_get_port_mode_bandwidth(enp,
49						    &bandwidth)) != 0)
50		goto fail1;
51
52	*bandwidth_mbpsp = bandwidth;
53
54	return (0);
55
56fail1:
57	EFSYS_PROBE1(fail1, efx_rc_t, rc);
58
59	return (rc);
60}
61
62	__checkReturn	efx_rc_t
63medford_board_cfg(
64	__in		efx_nic_t *enp)
65{
66	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
67	uint32_t sysclk, dpcpu_clk;
68	uint32_t end_padding;
69	uint32_t bandwidth;
70	efx_rc_t rc;
71
72	/*
73	 * Enable firmware workarounds for hardware errata.
74	 * Expected responses are:
75	 *  - 0 (zero):
76	 *	Success: workaround enabled or disabled as requested.
77	 *  - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
78	 *	Firmware does not support the MC_CMD_WORKAROUND request.
79	 *	(assume that the workaround is not supported).
80	 *  - MC_CMD_ERR_ENOENT (reported as ENOENT):
81	 *	Firmware does not support the requested workaround.
82	 *  - MC_CMD_ERR_EPERM  (reported as EACCES):
83	 *	Unprivileged function cannot enable/disable workarounds.
84	 *
85	 * See efx_mcdi_request_errcode() for MCDI error translations.
86	 */
87
88
89	if (EFX_PCI_FUNCTION_IS_VF(encp)) {
90		/*
91		 * Interrupt testing does not work for VFs. See bug50084 and
92		 * bug71432 comment 21.
93		 */
94		encp->enc_bug41750_workaround = B_TRUE;
95	}
96
97	/* Chained multicast is always enabled on Medford */
98	encp->enc_bug26807_workaround = B_TRUE;
99
100	/*
101	 * If the bug61265 workaround is enabled, then interrupt holdoff timers
102	 * cannot be controlled by timer table writes, so MCDI must be used
103	 * (timer table writes can still be used for wakeup timers).
104	 */
105	rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
106	    NULL);
107	if ((rc == 0) || (rc == EACCES))
108		encp->enc_bug61265_workaround = B_TRUE;
109	else if ((rc == ENOTSUP) || (rc == ENOENT))
110		encp->enc_bug61265_workaround = B_FALSE;
111	else
112		goto fail1;
113
114	/* Checksums for TSO sends can be incorrect on Medford. */
115	encp->enc_bug61297_workaround = B_TRUE;
116
117	/* Get clock frequencies (in MHz). */
118	if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
119		goto fail2;
120
121	/*
122	 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
123	 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
124	 */
125	encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
126	encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
127		    FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
128
129	/* Alignment for receive packet DMA buffers */
130	encp->enc_rx_buf_align_start = 1;
131
132	/* Get the RX DMA end padding alignment configuration */
133	if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
134		if (rc != EACCES)
135			goto fail3;
136
137		/* Assume largest tail padding size supported by hardware */
138		end_padding = 256;
139	}
140	encp->enc_rx_buf_align_end = end_padding;
141
142	/*
143	 * The maximum supported transmit queue size is 2048. TXQs with 4096
144	 * descriptors are not supported as the top bit is used for vfifo
145	 * stuffing.
146	 */
147	encp->enc_txq_max_ndescs = 2048;
148
149	EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
150	encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
151	encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
152	encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
153
154	/*
155	 * Medford stores a single global copy of VPD, not per-PF as on
156	 * Huntington.
157	 */
158	encp->enc_vpd_is_global = B_TRUE;
159
160	rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
161	if (rc != 0)
162		goto fail4;
163	encp->enc_required_pcie_bandwidth_mbps = bandwidth;
164	encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
165
166	return (0);
167
168fail4:
169	EFSYS_PROBE(fail4);
170fail3:
171	EFSYS_PROBE(fail3);
172fail2:
173	EFSYS_PROBE(fail2);
174fail1:
175	EFSYS_PROBE1(fail1, efx_rc_t, rc);
176
177	return (rc);
178}
179
180#endif	/* EFSYS_OPT_MEDFORD */
181