1/*-
2 * Copyright (c) 2015-2016 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD$
31 */
32
33#ifndef	_SYS_EF10_IMPL_H
34#define	_SYS_EF10_IMPL_H
35
36#ifdef	__cplusplus
37extern "C" {
38#endif
39
40
41/* Number of hardware PIO buffers (for compile-time resource dimensions) */
42#define	EF10_MAX_PIOBUF_NBUFS	(16)
43
44#if EFSYS_OPT_HUNTINGTON
45# if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS)
46#  error "EF10_MAX_PIOBUF_NBUFS too small"
47# endif
48#endif /* EFSYS_OPT_HUNTINGTON */
49#if EFSYS_OPT_MEDFORD
50# if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS)
51#  error "EF10_MAX_PIOBUF_NBUFS too small"
52# endif
53#endif /* EFSYS_OPT_MEDFORD */
54#if EFSYS_OPT_MEDFORD2
55# if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS)
56#  error "EF10_MAX_PIOBUF_NBUFS too small"
57# endif
58#endif /* EFSYS_OPT_MEDFORD2 */
59
60
61
62/*
63 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
64 * possibly be increased, or the write size reported by newer firmware used
65 * instead.
66 */
67#define	EF10_NVRAM_CHUNK 0x80
68
69/*
70 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
71 * to an 8 descriptor boundary.
72 */
73#define	EF10_RX_WPTR_ALIGN 8
74
75/*
76 * Max byte offset into the packet the TCP header must start for the hardware
77 * to be able to parse the packet correctly.
78 */
79#define	EF10_TCP_HEADER_OFFSET_LIMIT	208
80
81/* Invalid RSS context handle */
82#define	EF10_RSS_CONTEXT_INVALID	(0xffffffff)
83
84
85/* EV */
86
87	__checkReturn	efx_rc_t
88ef10_ev_init(
89	__in		efx_nic_t *enp);
90
91			void
92ef10_ev_fini(
93	__in		efx_nic_t *enp);
94
95	__checkReturn	efx_rc_t
96ef10_ev_qcreate(
97	__in		efx_nic_t *enp,
98	__in		unsigned int index,
99	__in		efsys_mem_t *esmp,
100	__in		size_t ndescs,
101	__in		uint32_t id,
102	__in		uint32_t us,
103	__in		uint32_t flags,
104	__in		efx_evq_t *eep);
105
106			void
107ef10_ev_qdestroy(
108	__in		efx_evq_t *eep);
109
110	__checkReturn	efx_rc_t
111ef10_ev_qprime(
112	__in		efx_evq_t *eep,
113	__in		unsigned int count);
114
115			void
116ef10_ev_qpost(
117	__in	efx_evq_t *eep,
118	__in	uint16_t data);
119
120	__checkReturn	efx_rc_t
121ef10_ev_qmoderate(
122	__in		efx_evq_t *eep,
123	__in		unsigned int us);
124
125#if EFSYS_OPT_QSTATS
126			void
127ef10_ev_qstats_update(
128	__in				efx_evq_t *eep,
129	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat);
130#endif /* EFSYS_OPT_QSTATS */
131
132		void
133ef10_ev_rxlabel_init(
134	__in		efx_evq_t *eep,
135	__in		efx_rxq_t *erp,
136	__in		unsigned int label,
137	__in		efx_rxq_type_t type);
138
139		void
140ef10_ev_rxlabel_fini(
141	__in		efx_evq_t *eep,
142	__in		unsigned int label);
143
144/* INTR */
145
146	__checkReturn	efx_rc_t
147ef10_intr_init(
148	__in		efx_nic_t *enp,
149	__in		efx_intr_type_t type,
150	__in		efsys_mem_t *esmp);
151
152			void
153ef10_intr_enable(
154	__in		efx_nic_t *enp);
155
156			void
157ef10_intr_disable(
158	__in		efx_nic_t *enp);
159
160			void
161ef10_intr_disable_unlocked(
162	__in		efx_nic_t *enp);
163
164	__checkReturn	efx_rc_t
165ef10_intr_trigger(
166	__in		efx_nic_t *enp,
167	__in		unsigned int level);
168
169			void
170ef10_intr_status_line(
171	__in		efx_nic_t *enp,
172	__out		boolean_t *fatalp,
173	__out		uint32_t *qmaskp);
174
175			void
176ef10_intr_status_message(
177	__in		efx_nic_t *enp,
178	__in		unsigned int message,
179	__out		boolean_t *fatalp);
180
181			void
182ef10_intr_fatal(
183	__in		efx_nic_t *enp);
184			void
185ef10_intr_fini(
186	__in		efx_nic_t *enp);
187
188/* NIC */
189
190extern	__checkReturn	efx_rc_t
191ef10_nic_probe(
192	__in		efx_nic_t *enp);
193
194extern	__checkReturn	efx_rc_t
195ef10_nic_set_drv_limits(
196	__inout		efx_nic_t *enp,
197	__in		efx_drv_limits_t *edlp);
198
199extern	__checkReturn	efx_rc_t
200ef10_nic_get_vi_pool(
201	__in		efx_nic_t *enp,
202	__out		uint32_t *vi_countp);
203
204extern	__checkReturn	efx_rc_t
205ef10_nic_get_bar_region(
206	__in		efx_nic_t *enp,
207	__in		efx_nic_region_t region,
208	__out		uint32_t *offsetp,
209	__out		size_t *sizep);
210
211extern	__checkReturn	efx_rc_t
212ef10_nic_reset(
213	__in		efx_nic_t *enp);
214
215extern	__checkReturn	efx_rc_t
216ef10_nic_init(
217	__in		efx_nic_t *enp);
218
219extern	__checkReturn	boolean_t
220ef10_nic_hw_unavailable(
221	__in		efx_nic_t *enp);
222
223extern			void
224ef10_nic_set_hw_unavailable(
225	__in		efx_nic_t *enp);
226
227#if EFSYS_OPT_DIAG
228
229extern	__checkReturn	efx_rc_t
230ef10_nic_register_test(
231	__in		efx_nic_t *enp);
232
233#endif	/* EFSYS_OPT_DIAG */
234
235extern			void
236ef10_nic_fini(
237	__in		efx_nic_t *enp);
238
239extern			void
240ef10_nic_unprobe(
241	__in		efx_nic_t *enp);
242
243
244/* MAC */
245
246extern	__checkReturn	efx_rc_t
247ef10_mac_poll(
248	__in		efx_nic_t *enp,
249	__out		efx_link_mode_t *link_modep);
250
251extern	__checkReturn	efx_rc_t
252ef10_mac_up(
253	__in		efx_nic_t *enp,
254	__out		boolean_t *mac_upp);
255
256extern	__checkReturn	efx_rc_t
257ef10_mac_addr_set(
258	__in	efx_nic_t *enp);
259
260extern	__checkReturn	efx_rc_t
261ef10_mac_pdu_set(
262	__in	efx_nic_t *enp);
263
264extern	__checkReturn	efx_rc_t
265ef10_mac_pdu_get(
266	__in	efx_nic_t *enp,
267	__out	size_t *pdu);
268
269extern	__checkReturn	efx_rc_t
270ef10_mac_reconfigure(
271	__in	efx_nic_t *enp);
272
273extern	__checkReturn	efx_rc_t
274ef10_mac_multicast_list_set(
275	__in				efx_nic_t *enp);
276
277extern	__checkReturn	efx_rc_t
278ef10_mac_filter_default_rxq_set(
279	__in		efx_nic_t *enp,
280	__in		efx_rxq_t *erp,
281	__in		boolean_t using_rss);
282
283extern			void
284ef10_mac_filter_default_rxq_clear(
285	__in		efx_nic_t *enp);
286
287#if EFSYS_OPT_LOOPBACK
288
289extern	__checkReturn	efx_rc_t
290ef10_mac_loopback_set(
291	__in		efx_nic_t *enp,
292	__in		efx_link_mode_t link_mode,
293	__in		efx_loopback_type_t loopback_type);
294
295#endif	/* EFSYS_OPT_LOOPBACK */
296
297#if EFSYS_OPT_MAC_STATS
298
299extern	__checkReturn			efx_rc_t
300ef10_mac_stats_get_mask(
301	__in				efx_nic_t *enp,
302	__inout_bcount(mask_size)	uint32_t *maskp,
303	__in				size_t mask_size);
304
305extern	__checkReturn			efx_rc_t
306ef10_mac_stats_update(
307	__in				efx_nic_t *enp,
308	__in				efsys_mem_t *esmp,
309	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stat,
310	__inout_opt			uint32_t *generationp);
311
312#endif	/* EFSYS_OPT_MAC_STATS */
313
314
315/* MCDI */
316
317#if EFSYS_OPT_MCDI
318
319extern	__checkReturn	efx_rc_t
320ef10_mcdi_init(
321	__in		efx_nic_t *enp,
322	__in		const efx_mcdi_transport_t *mtp);
323
324extern			void
325ef10_mcdi_fini(
326	__in		efx_nic_t *enp);
327
328extern			void
329ef10_mcdi_send_request(
330	__in			efx_nic_t *enp,
331	__in_bcount(hdr_len)	void *hdrp,
332	__in			size_t hdr_len,
333	__in_bcount(sdu_len)	void *sdup,
334	__in			size_t sdu_len);
335
336extern	__checkReturn	boolean_t
337ef10_mcdi_poll_response(
338	__in		efx_nic_t *enp);
339
340extern			void
341ef10_mcdi_read_response(
342	__in			efx_nic_t *enp,
343	__out_bcount(length)	void *bufferp,
344	__in			size_t offset,
345	__in			size_t length);
346
347extern			efx_rc_t
348ef10_mcdi_poll_reboot(
349	__in		efx_nic_t *enp);
350
351extern	__checkReturn	efx_rc_t
352ef10_mcdi_feature_supported(
353	__in		efx_nic_t *enp,
354	__in		efx_mcdi_feature_id_t id,
355	__out		boolean_t *supportedp);
356
357extern			void
358ef10_mcdi_get_timeout(
359	__in		efx_nic_t *enp,
360	__in		efx_mcdi_req_t *emrp,
361	__out		uint32_t *timeoutp);
362
363#endif /* EFSYS_OPT_MCDI */
364
365/* NVRAM */
366
367#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
368
369extern	__checkReturn		efx_rc_t
370ef10_nvram_buf_read_tlv(
371	__in				efx_nic_t *enp,
372	__in_bcount(max_seg_size)	caddr_t seg_data,
373	__in				size_t max_seg_size,
374	__in				uint32_t tag,
375	__deref_out_bcount_opt(*sizep)	caddr_t *datap,
376	__out				size_t *sizep);
377
378extern	__checkReturn		efx_rc_t
379ef10_nvram_buf_write_tlv(
380	__inout_bcount(partn_size)	caddr_t partn_data,
381	__in				size_t partn_size,
382	__in				uint32_t tag,
383	__in_bcount(tag_size)		caddr_t tag_data,
384	__in				size_t tag_size,
385	__out				size_t *total_lengthp);
386
387extern	__checkReturn		efx_rc_t
388ef10_nvram_partn_read_tlv(
389	__in				efx_nic_t *enp,
390	__in				uint32_t partn,
391	__in				uint32_t tag,
392	__deref_out_bcount_opt(*sizep)	caddr_t *datap,
393	__out				size_t *sizep);
394
395extern	__checkReturn		efx_rc_t
396ef10_nvram_partn_write_tlv(
397	__in			efx_nic_t *enp,
398	__in			uint32_t partn,
399	__in			uint32_t tag,
400	__in_bcount(size)	caddr_t data,
401	__in			size_t size);
402
403extern	__checkReturn		efx_rc_t
404ef10_nvram_partn_write_segment_tlv(
405	__in			efx_nic_t *enp,
406	__in			uint32_t partn,
407	__in			uint32_t tag,
408	__in_bcount(size)	caddr_t data,
409	__in			size_t size,
410	__in			boolean_t all_segments);
411
412extern	__checkReturn		efx_rc_t
413ef10_nvram_partn_lock(
414	__in			efx_nic_t *enp,
415	__in			uint32_t partn);
416
417extern	__checkReturn		efx_rc_t
418ef10_nvram_partn_unlock(
419	__in			efx_nic_t *enp,
420	__in			uint32_t partn,
421	__out_opt		uint32_t *resultp);
422
423#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
424
425#if EFSYS_OPT_NVRAM
426
427#if EFSYS_OPT_DIAG
428
429extern	__checkReturn		efx_rc_t
430ef10_nvram_test(
431	__in			efx_nic_t *enp);
432
433#endif	/* EFSYS_OPT_DIAG */
434
435extern	__checkReturn		efx_rc_t
436ef10_nvram_type_to_partn(
437	__in			efx_nic_t *enp,
438	__in			efx_nvram_type_t type,
439	__out			uint32_t *partnp);
440
441extern	__checkReturn		efx_rc_t
442ef10_nvram_partn_size(
443	__in			efx_nic_t *enp,
444	__in			uint32_t partn,
445	__out			size_t *sizep);
446
447extern	__checkReturn		efx_rc_t
448ef10_nvram_partn_rw_start(
449	__in			efx_nic_t *enp,
450	__in			uint32_t partn,
451	__out			size_t *chunk_sizep);
452
453extern	__checkReturn		efx_rc_t
454ef10_nvram_partn_read_mode(
455	__in			efx_nic_t *enp,
456	__in			uint32_t partn,
457	__in			unsigned int offset,
458	__out_bcount(size)	caddr_t data,
459	__in			size_t size,
460	__in			uint32_t mode);
461
462extern	__checkReturn		efx_rc_t
463ef10_nvram_partn_read(
464	__in			efx_nic_t *enp,
465	__in			uint32_t partn,
466	__in			unsigned int offset,
467	__in_bcount(size)	caddr_t data,
468	__in			size_t size);
469
470extern	__checkReturn		efx_rc_t
471ef10_nvram_partn_read_backup(
472	__in			efx_nic_t *enp,
473	__in			uint32_t partn,
474	__in			unsigned int offset,
475	__out_bcount(size)	caddr_t data,
476	__in			size_t size);
477
478extern	__checkReturn		efx_rc_t
479ef10_nvram_partn_erase(
480	__in			efx_nic_t *enp,
481	__in			uint32_t partn,
482	__in			unsigned int offset,
483	__in			size_t size);
484
485extern	__checkReturn		efx_rc_t
486ef10_nvram_partn_write(
487	__in			efx_nic_t *enp,
488	__in			uint32_t partn,
489	__in			unsigned int offset,
490	__out_bcount(size)	caddr_t data,
491	__in			size_t size);
492
493extern	__checkReturn		efx_rc_t
494ef10_nvram_partn_rw_finish(
495	__in			efx_nic_t *enp,
496	__in			uint32_t partn,
497	__out_opt		uint32_t *verify_resultp);
498
499extern	__checkReturn		efx_rc_t
500ef10_nvram_partn_get_version(
501	__in			efx_nic_t *enp,
502	__in			uint32_t partn,
503	__out			uint32_t *subtypep,
504	__out_ecount(4)		uint16_t version[4]);
505
506extern	__checkReturn		efx_rc_t
507ef10_nvram_partn_set_version(
508	__in			efx_nic_t *enp,
509	__in			uint32_t partn,
510	__in_ecount(4)		uint16_t version[4]);
511
512extern	__checkReturn		efx_rc_t
513ef10_nvram_buffer_validate(
514	__in			uint32_t partn,
515	__in_bcount(buffer_size)
516				caddr_t bufferp,
517	__in			size_t buffer_size);
518
519extern			void
520ef10_nvram_buffer_init(
521	__out_bcount(buffer_size)
522				caddr_t bufferp,
523	__in			size_t buffer_size);
524
525extern	__checkReturn		efx_rc_t
526ef10_nvram_buffer_create(
527	__in			uint32_t partn_type,
528	__out_bcount(buffer_size)
529				caddr_t bufferp,
530	__in			size_t buffer_size);
531
532extern	__checkReturn		efx_rc_t
533ef10_nvram_buffer_find_item_start(
534	__in_bcount(buffer_size)
535				caddr_t bufferp,
536	__in			size_t buffer_size,
537	__out			uint32_t *startp);
538
539extern	__checkReturn		efx_rc_t
540ef10_nvram_buffer_find_end(
541	__in_bcount(buffer_size)
542				caddr_t bufferp,
543	__in			size_t buffer_size,
544	__in			uint32_t offset,
545	__out			uint32_t *endp);
546
547extern	__checkReturn	__success(return != B_FALSE)	boolean_t
548ef10_nvram_buffer_find_item(
549	__in_bcount(buffer_size)
550				caddr_t bufferp,
551	__in			size_t buffer_size,
552	__in			uint32_t offset,
553	__out			uint32_t *startp,
554	__out			uint32_t *lengthp);
555
556extern	__checkReturn		efx_rc_t
557ef10_nvram_buffer_peek_item(
558	__in_bcount(buffer_size)
559				caddr_t bufferp,
560	__in			size_t buffer_size,
561	__in			uint32_t offset,
562	__out			uint32_t *tagp,
563	__out			uint32_t *lengthp,
564	__out			uint32_t *value_offsetp);
565
566extern	__checkReturn		efx_rc_t
567ef10_nvram_buffer_get_item(
568	__in_bcount(buffer_size)
569				caddr_t bufferp,
570	__in			size_t buffer_size,
571	__in			uint32_t offset,
572	__in			uint32_t length,
573	__out			uint32_t *tagp,
574	__out_bcount_part(value_max_size, *lengthp)
575				caddr_t valuep,
576	__in			size_t value_max_size,
577	__out			uint32_t *lengthp);
578
579extern	__checkReturn		efx_rc_t
580ef10_nvram_buffer_insert_item(
581	__in_bcount(buffer_size)
582				caddr_t bufferp,
583	__in			size_t buffer_size,
584	__in			uint32_t offset,
585	__in			uint32_t tag,
586	__in_bcount(length)	caddr_t valuep,
587	__in			uint32_t length,
588	__out			uint32_t *lengthp);
589
590extern	__checkReturn		efx_rc_t
591ef10_nvram_buffer_modify_item(
592	__in_bcount(buffer_size)
593				caddr_t bufferp,
594	__in			size_t buffer_size,
595	__in			uint32_t offset,
596	__in			uint32_t tag,
597	__in_bcount(length)	caddr_t valuep,
598	__in			uint32_t length,
599	__out			uint32_t *lengthp);
600
601extern	__checkReturn		efx_rc_t
602ef10_nvram_buffer_delete_item(
603	__in_bcount(buffer_size)
604				caddr_t bufferp,
605	__in			size_t buffer_size,
606	__in			uint32_t offset,
607	__in			uint32_t length,
608	__in			uint32_t end);
609
610extern	__checkReturn		efx_rc_t
611ef10_nvram_buffer_finish(
612	__in_bcount(buffer_size)
613				caddr_t bufferp,
614	__in			size_t buffer_size);
615
616#endif	/* EFSYS_OPT_NVRAM */
617
618
619/* PHY */
620
621typedef struct ef10_link_state_s {
622	efx_phy_link_state_t	epls;
623#if EFSYS_OPT_LOOPBACK
624	efx_loopback_type_t	els_loopback;
625#endif
626	boolean_t		els_mac_up;
627} ef10_link_state_t;
628
629extern			void
630ef10_phy_link_ev(
631	__in		efx_nic_t *enp,
632	__in		efx_qword_t *eqp,
633	__out		efx_link_mode_t *link_modep);
634
635extern	__checkReturn	efx_rc_t
636ef10_phy_get_link(
637	__in		efx_nic_t *enp,
638	__out		ef10_link_state_t *elsp);
639
640extern	__checkReturn	efx_rc_t
641ef10_phy_power(
642	__in		efx_nic_t *enp,
643	__in		boolean_t on);
644
645extern	__checkReturn	efx_rc_t
646ef10_phy_reconfigure(
647	__in		efx_nic_t *enp);
648
649extern	__checkReturn	efx_rc_t
650ef10_phy_verify(
651	__in		efx_nic_t *enp);
652
653extern	__checkReturn	efx_rc_t
654ef10_phy_oui_get(
655	__in		efx_nic_t *enp,
656	__out		uint32_t *ouip);
657
658extern	__checkReturn	efx_rc_t
659ef10_phy_link_state_get(
660	__in		efx_nic_t *enp,
661	__out		efx_phy_link_state_t *eplsp);
662
663#if EFSYS_OPT_PHY_STATS
664
665extern	__checkReturn			efx_rc_t
666ef10_phy_stats_update(
667	__in				efx_nic_t *enp,
668	__in				efsys_mem_t *esmp,
669	__inout_ecount(EFX_PHY_NSTATS)	uint32_t *stat);
670
671#endif	/* EFSYS_OPT_PHY_STATS */
672
673#if EFSYS_OPT_BIST
674
675extern	__checkReturn		efx_rc_t
676ef10_bist_enable_offline(
677	__in			efx_nic_t *enp);
678
679extern	__checkReturn		efx_rc_t
680ef10_bist_start(
681	__in			efx_nic_t *enp,
682	__in			efx_bist_type_t type);
683
684extern	__checkReturn		efx_rc_t
685ef10_bist_poll(
686	__in			efx_nic_t *enp,
687	__in			efx_bist_type_t type,
688	__out			efx_bist_result_t *resultp,
689	__out_opt __drv_when(count > 0, __notnull)
690	uint32_t	*value_maskp,
691	__out_ecount_opt(count)	__drv_when(count > 0, __notnull)
692	unsigned long	*valuesp,
693	__in			size_t count);
694
695extern				void
696ef10_bist_stop(
697	__in			efx_nic_t *enp,
698	__in			efx_bist_type_t type);
699
700#endif	/* EFSYS_OPT_BIST */
701
702/* TX */
703
704extern	__checkReturn	efx_rc_t
705ef10_tx_init(
706	__in		efx_nic_t *enp);
707
708extern			void
709ef10_tx_fini(
710	__in		efx_nic_t *enp);
711
712extern	__checkReturn	efx_rc_t
713ef10_tx_qcreate(
714	__in		efx_nic_t *enp,
715	__in		unsigned int index,
716	__in		unsigned int label,
717	__in		efsys_mem_t *esmp,
718	__in		size_t ndescs,
719	__in		uint32_t id,
720	__in		uint16_t flags,
721	__in		efx_evq_t *eep,
722	__in		efx_txq_t *etp,
723	__out		unsigned int *addedp);
724
725extern		void
726ef10_tx_qdestroy(
727	__in		efx_txq_t *etp);
728
729extern	__checkReturn		efx_rc_t
730ef10_tx_qpost(
731	__in			efx_txq_t *etp,
732	__in_ecount(ndescs)	efx_buffer_t *ebp,
733	__in			unsigned int ndescs,
734	__in			unsigned int completed,
735	__inout			unsigned int *addedp);
736
737extern			void
738ef10_tx_qpush(
739	__in		efx_txq_t *etp,
740	__in		unsigned int added,
741	__in		unsigned int pushed);
742
743#if EFSYS_OPT_RX_PACKED_STREAM
744extern			void
745ef10_rx_qpush_ps_credits(
746	__in		efx_rxq_t *erp);
747
748extern	__checkReturn	uint8_t *
749ef10_rx_qps_packet_info(
750	__in		efx_rxq_t *erp,
751	__in		uint8_t *buffer,
752	__in		uint32_t buffer_length,
753	__in		uint32_t current_offset,
754	__out		uint16_t *lengthp,
755	__out		uint32_t *next_offsetp,
756	__out		uint32_t *timestamp);
757#endif
758
759extern	__checkReturn	efx_rc_t
760ef10_tx_qpace(
761	__in		efx_txq_t *etp,
762	__in		unsigned int ns);
763
764extern	__checkReturn	efx_rc_t
765ef10_tx_qflush(
766	__in		efx_txq_t *etp);
767
768extern			void
769ef10_tx_qenable(
770	__in		efx_txq_t *etp);
771
772extern	__checkReturn	efx_rc_t
773ef10_tx_qpio_enable(
774	__in		efx_txq_t *etp);
775
776extern			void
777ef10_tx_qpio_disable(
778	__in		efx_txq_t *etp);
779
780extern	__checkReturn	efx_rc_t
781ef10_tx_qpio_write(
782	__in			efx_txq_t *etp,
783	__in_ecount(buf_length)	uint8_t *buffer,
784	__in			size_t buf_length,
785	__in			size_t pio_buf_offset);
786
787extern	__checkReturn	efx_rc_t
788ef10_tx_qpio_post(
789	__in			efx_txq_t *etp,
790	__in			size_t pkt_length,
791	__in			unsigned int completed,
792	__inout			unsigned int *addedp);
793
794extern	__checkReturn	efx_rc_t
795ef10_tx_qdesc_post(
796	__in		efx_txq_t *etp,
797	__in_ecount(n)	efx_desc_t *ed,
798	__in		unsigned int n,
799	__in		unsigned int completed,
800	__inout		unsigned int *addedp);
801
802extern	void
803ef10_tx_qdesc_dma_create(
804	__in	efx_txq_t *etp,
805	__in	efsys_dma_addr_t addr,
806	__in	size_t size,
807	__in	boolean_t eop,
808	__out	efx_desc_t *edp);
809
810extern	void
811ef10_tx_qdesc_tso_create(
812	__in	efx_txq_t *etp,
813	__in	uint16_t ipv4_id,
814	__in	uint32_t tcp_seq,
815	__in	uint8_t	 tcp_flags,
816	__out	efx_desc_t *edp);
817
818extern	void
819ef10_tx_qdesc_tso2_create(
820	__in			efx_txq_t *etp,
821	__in			uint16_t ipv4_id,
822	__in			uint16_t outer_ipv4_id,
823	__in			uint32_t tcp_seq,
824	__in			uint16_t tcp_mss,
825	__out_ecount(count)	efx_desc_t *edp,
826	__in			int count);
827
828extern	void
829ef10_tx_qdesc_vlantci_create(
830	__in	efx_txq_t *etp,
831	__in	uint16_t vlan_tci,
832	__out	efx_desc_t *edp);
833
834extern	void
835ef10_tx_qdesc_checksum_create(
836	__in	efx_txq_t *etp,
837	__in	uint16_t flags,
838	__out	efx_desc_t *edp);
839
840#if EFSYS_OPT_QSTATS
841
842extern			void
843ef10_tx_qstats_update(
844	__in				efx_txq_t *etp,
845	__inout_ecount(TX_NQSTATS)	efsys_stat_t *stat);
846
847#endif /* EFSYS_OPT_QSTATS */
848
849typedef uint32_t	efx_piobuf_handle_t;
850
851#define	EFX_PIOBUF_HANDLE_INVALID	((efx_piobuf_handle_t)-1)
852
853extern	__checkReturn	efx_rc_t
854ef10_nic_pio_alloc(
855	__inout		efx_nic_t *enp,
856	__out		uint32_t *bufnump,
857	__out		efx_piobuf_handle_t *handlep,
858	__out		uint32_t *blknump,
859	__out		uint32_t *offsetp,
860	__out		size_t *sizep);
861
862extern	__checkReturn	efx_rc_t
863ef10_nic_pio_free(
864	__inout		efx_nic_t *enp,
865	__in		uint32_t bufnum,
866	__in		uint32_t blknum);
867
868extern	__checkReturn	efx_rc_t
869ef10_nic_pio_link(
870	__inout		efx_nic_t *enp,
871	__in		uint32_t vi_index,
872	__in		efx_piobuf_handle_t handle);
873
874extern	__checkReturn	efx_rc_t
875ef10_nic_pio_unlink(
876	__inout		efx_nic_t *enp,
877	__in		uint32_t vi_index);
878
879
880/* VPD */
881
882#if EFSYS_OPT_VPD
883
884extern	__checkReturn		efx_rc_t
885ef10_vpd_init(
886	__in			efx_nic_t *enp);
887
888extern	__checkReturn		efx_rc_t
889ef10_vpd_size(
890	__in			efx_nic_t *enp,
891	__out			size_t *sizep);
892
893extern	__checkReturn		efx_rc_t
894ef10_vpd_read(
895	__in			efx_nic_t *enp,
896	__out_bcount(size)	caddr_t data,
897	__in			size_t size);
898
899extern	__checkReturn		efx_rc_t
900ef10_vpd_verify(
901	__in			efx_nic_t *enp,
902	__in_bcount(size)	caddr_t data,
903	__in			size_t size);
904
905extern	__checkReturn		efx_rc_t
906ef10_vpd_reinit(
907	__in			efx_nic_t *enp,
908	__in_bcount(size)	caddr_t data,
909	__in			size_t size);
910
911extern	__checkReturn		efx_rc_t
912ef10_vpd_get(
913	__in			efx_nic_t *enp,
914	__in_bcount(size)	caddr_t data,
915	__in			size_t size,
916	__inout			efx_vpd_value_t *evvp);
917
918extern	__checkReturn		efx_rc_t
919ef10_vpd_set(
920	__in			efx_nic_t *enp,
921	__in_bcount(size)	caddr_t data,
922	__in			size_t size,
923	__in			efx_vpd_value_t *evvp);
924
925extern	__checkReturn		efx_rc_t
926ef10_vpd_next(
927	__in			efx_nic_t *enp,
928	__in_bcount(size)	caddr_t data,
929	__in			size_t size,
930	__out			efx_vpd_value_t *evvp,
931	__inout			unsigned int *contp);
932
933extern __checkReturn		efx_rc_t
934ef10_vpd_write(
935	__in			efx_nic_t *enp,
936	__in_bcount(size)	caddr_t data,
937	__in			size_t size);
938
939extern				void
940ef10_vpd_fini(
941	__in			efx_nic_t *enp);
942
943#endif	/* EFSYS_OPT_VPD */
944
945
946/* RX */
947
948extern	__checkReturn	efx_rc_t
949ef10_rx_init(
950	__in		efx_nic_t *enp);
951
952#if EFSYS_OPT_RX_SCATTER
953extern	__checkReturn	efx_rc_t
954ef10_rx_scatter_enable(
955	__in		efx_nic_t *enp,
956	__in		unsigned int buf_size);
957#endif	/* EFSYS_OPT_RX_SCATTER */
958
959
960#if EFSYS_OPT_RX_SCALE
961
962extern	__checkReturn	efx_rc_t
963ef10_rx_scale_context_alloc(
964	__in		efx_nic_t *enp,
965	__in		efx_rx_scale_context_type_t type,
966	__in		uint32_t num_queues,
967	__out		uint32_t *rss_contextp);
968
969extern	__checkReturn	efx_rc_t
970ef10_rx_scale_context_free(
971	__in		efx_nic_t *enp,
972	__in		uint32_t rss_context);
973
974extern	__checkReturn	efx_rc_t
975ef10_rx_scale_mode_set(
976	__in		efx_nic_t *enp,
977	__in		uint32_t rss_context,
978	__in		efx_rx_hash_alg_t alg,
979	__in		efx_rx_hash_type_t type,
980	__in		boolean_t insert);
981
982extern	__checkReturn	efx_rc_t
983ef10_rx_scale_key_set(
984	__in		efx_nic_t *enp,
985	__in		uint32_t rss_context,
986	__in_ecount(n)	uint8_t *key,
987	__in		size_t n);
988
989extern	__checkReturn	efx_rc_t
990ef10_rx_scale_tbl_set(
991	__in		efx_nic_t *enp,
992	__in		uint32_t rss_context,
993	__in_ecount(n)	unsigned int *table,
994	__in		size_t n);
995
996extern	__checkReturn	uint32_t
997ef10_rx_prefix_hash(
998	__in		efx_nic_t *enp,
999	__in		efx_rx_hash_alg_t func,
1000	__in		uint8_t *buffer);
1001
1002#endif /* EFSYS_OPT_RX_SCALE */
1003
1004extern	__checkReturn	efx_rc_t
1005ef10_rx_prefix_pktlen(
1006	__in		efx_nic_t *enp,
1007	__in		uint8_t *buffer,
1008	__out		uint16_t *lengthp);
1009
1010extern				void
1011ef10_rx_qpost(
1012	__in			efx_rxq_t *erp,
1013	__in_ecount(ndescs)	efsys_dma_addr_t *addrp,
1014	__in			size_t size,
1015	__in			unsigned int ndescs,
1016	__in			unsigned int completed,
1017	__in			unsigned int added);
1018
1019extern			void
1020ef10_rx_qpush(
1021	__in		efx_rxq_t *erp,
1022	__in		unsigned int added,
1023	__inout		unsigned int *pushedp);
1024
1025extern	__checkReturn	efx_rc_t
1026ef10_rx_qflush(
1027	__in		efx_rxq_t *erp);
1028
1029extern		void
1030ef10_rx_qenable(
1031	__in		efx_rxq_t *erp);
1032
1033union efx_rxq_type_data_u;
1034
1035extern	__checkReturn	efx_rc_t
1036ef10_rx_qcreate(
1037	__in		efx_nic_t *enp,
1038	__in		unsigned int index,
1039	__in		unsigned int label,
1040	__in		efx_rxq_type_t type,
1041	__in_opt	const union efx_rxq_type_data_u *type_data,
1042	__in		efsys_mem_t *esmp,
1043	__in		size_t ndescs,
1044	__in		uint32_t id,
1045	__in		unsigned int flags,
1046	__in		efx_evq_t *eep,
1047	__in		efx_rxq_t *erp);
1048
1049extern			void
1050ef10_rx_qdestroy(
1051	__in		efx_rxq_t *erp);
1052
1053extern			void
1054ef10_rx_fini(
1055	__in		efx_nic_t *enp);
1056
1057#if EFSYS_OPT_FILTER
1058
1059typedef struct ef10_filter_handle_s {
1060	uint32_t	efh_lo;
1061	uint32_t	efh_hi;
1062} ef10_filter_handle_t;
1063
1064typedef struct ef10_filter_entry_s {
1065	uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1066	ef10_filter_handle_t efe_handle;
1067} ef10_filter_entry_t;
1068
1069/*
1070 * BUSY flag indicates that an update is in progress.
1071 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1072 */
1073#define	EFX_EF10_FILTER_FLAG_BUSY	1U
1074#define	EFX_EF10_FILTER_FLAG_AUTO_OLD	2U
1075#define	EFX_EF10_FILTER_FLAGS		3U
1076
1077/*
1078 * Size of the hash table used by the driver. Doesn't need to be the
1079 * same size as the hardware's table.
1080 */
1081#define	EFX_EF10_FILTER_TBL_ROWS 8192
1082
1083/* Only need to allow for one directed and one unknown unicast filter */
1084#define	EFX_EF10_FILTER_UNICAST_FILTERS_MAX	2
1085
1086/* Allow for the broadcast address to be added to the multicast list */
1087#define	EFX_EF10_FILTER_MULTICAST_FILTERS_MAX	(EFX_MAC_MULTICAST_LIST_MAX + 1)
1088
1089/*
1090 * For encapsulated packets, there is one filter each for each combination of
1091 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1092 * multicast inner frames.
1093 */
1094#define	EFX_EF10_FILTER_ENCAP_FILTERS_MAX	12
1095
1096typedef struct ef10_filter_table_s {
1097	ef10_filter_entry_t	eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1098	efx_rxq_t		*eft_default_rxq;
1099	boolean_t		eft_using_rss;
1100	uint32_t		eft_unicst_filter_indexes[
1101	    EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1102	uint32_t		eft_unicst_filter_count;
1103	uint32_t		eft_mulcst_filter_indexes[
1104	    EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1105	uint32_t		eft_mulcst_filter_count;
1106	boolean_t		eft_using_all_mulcst;
1107	uint32_t		eft_encap_filter_indexes[
1108	    EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1109	uint32_t		eft_encap_filter_count;
1110} ef10_filter_table_t;
1111
1112	__checkReturn	efx_rc_t
1113ef10_filter_init(
1114	__in		efx_nic_t *enp);
1115
1116			void
1117ef10_filter_fini(
1118	__in		efx_nic_t *enp);
1119
1120	__checkReturn	efx_rc_t
1121ef10_filter_restore(
1122	__in		efx_nic_t *enp);
1123
1124	__checkReturn	efx_rc_t
1125ef10_filter_add(
1126	__in		efx_nic_t *enp,
1127	__inout		efx_filter_spec_t *spec,
1128	__in		boolean_t may_replace);
1129
1130	__checkReturn	efx_rc_t
1131ef10_filter_delete(
1132	__in		efx_nic_t *enp,
1133	__inout		efx_filter_spec_t *spec);
1134
1135extern	__checkReturn	efx_rc_t
1136ef10_filter_supported_filters(
1137	__in				efx_nic_t *enp,
1138	__out_ecount(buffer_length)	uint32_t *buffer,
1139	__in				size_t buffer_length,
1140	__out				size_t *list_lengthp);
1141
1142extern	__checkReturn	efx_rc_t
1143ef10_filter_reconfigure(
1144	__in				efx_nic_t *enp,
1145	__in_ecount(6)			uint8_t const *mac_addr,
1146	__in				boolean_t all_unicst,
1147	__in				boolean_t mulcst,
1148	__in				boolean_t all_mulcst,
1149	__in				boolean_t brdcst,
1150	__in_ecount(6*count)		uint8_t const *addrs,
1151	__in				uint32_t count);
1152
1153extern		void
1154ef10_filter_get_default_rxq(
1155	__in		efx_nic_t *enp,
1156	__out		efx_rxq_t **erpp,
1157	__out		boolean_t *using_rss);
1158
1159extern		void
1160ef10_filter_default_rxq_set(
1161	__in		efx_nic_t *enp,
1162	__in		efx_rxq_t *erp,
1163	__in		boolean_t using_rss);
1164
1165extern		void
1166ef10_filter_default_rxq_clear(
1167	__in		efx_nic_t *enp);
1168
1169
1170#endif /* EFSYS_OPT_FILTER */
1171
1172extern	__checkReturn			efx_rc_t
1173efx_mcdi_get_function_info(
1174	__in				efx_nic_t *enp,
1175	__out				uint32_t *pfp,
1176	__out_opt			uint32_t *vfp);
1177
1178extern	__checkReturn		efx_rc_t
1179efx_mcdi_privilege_mask(
1180	__in			efx_nic_t *enp,
1181	__in			uint32_t pf,
1182	__in			uint32_t vf,
1183	__out			uint32_t *maskp);
1184
1185extern	__checkReturn	efx_rc_t
1186efx_mcdi_get_port_assignment(
1187	__in		efx_nic_t *enp,
1188	__out		uint32_t *portp);
1189
1190extern	__checkReturn	efx_rc_t
1191efx_mcdi_get_port_modes(
1192	__in		efx_nic_t *enp,
1193	__out		uint32_t *modesp,
1194	__out_opt	uint32_t *current_modep,
1195	__out_opt	uint32_t *default_modep);
1196
1197extern	__checkReturn	efx_rc_t
1198ef10_nic_get_port_mode_bandwidth(
1199	__in		efx_nic_t *enp,
1200	__out		uint32_t *bandwidth_mbpsp);
1201
1202extern	__checkReturn	efx_rc_t
1203efx_mcdi_get_mac_address_pf(
1204	__in			efx_nic_t *enp,
1205	__out_ecount_opt(6)	uint8_t mac_addrp[6]);
1206
1207extern	__checkReturn	efx_rc_t
1208efx_mcdi_get_mac_address_vf(
1209	__in			efx_nic_t *enp,
1210	__out_ecount_opt(6)	uint8_t mac_addrp[6]);
1211
1212extern	__checkReturn	efx_rc_t
1213efx_mcdi_get_clock(
1214	__in		efx_nic_t *enp,
1215	__out		uint32_t *sys_freqp,
1216	__out		uint32_t *dpcpu_freqp);
1217
1218
1219extern	__checkReturn	efx_rc_t
1220efx_mcdi_get_rxdp_config(
1221	__in		efx_nic_t *enp,
1222	__out		uint32_t *end_paddingp);
1223
1224extern	__checkReturn	efx_rc_t
1225efx_mcdi_get_vector_cfg(
1226	__in		efx_nic_t *enp,
1227	__out_opt	uint32_t *vec_basep,
1228	__out_opt	uint32_t *pf_nvecp,
1229	__out_opt	uint32_t *vf_nvecp);
1230
1231extern	__checkReturn		efx_rc_t
1232ef10_get_privilege_mask(
1233	__in			efx_nic_t *enp,
1234	__out			uint32_t *maskp);
1235
1236#if EFSYS_OPT_FW_SUBVARIANT_AWARE
1237
1238extern	__checkReturn	efx_rc_t
1239efx_mcdi_get_nic_global(
1240	__in		efx_nic_t *enp,
1241	__in		uint32_t key,
1242	__out		uint32_t *valuep);
1243
1244extern	__checkReturn	efx_rc_t
1245efx_mcdi_set_nic_global(
1246	__in		efx_nic_t *enp,
1247	__in		uint32_t key,
1248	__in		uint32_t value);
1249
1250#endif	/* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1251
1252
1253#if EFSYS_OPT_RX_PACKED_STREAM
1254
1255/* Data space per credit in packed stream mode */
1256#define	EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1257
1258/*
1259 * Received packets are always aligned at this boundary. Also there always
1260 * exists a gap of this size between packets.
1261 * (see SF-112241-TC, 4.5)
1262 */
1263#define	EFX_RX_PACKED_STREAM_ALIGNMENT 64
1264
1265/*
1266 * Size of a pseudo-header prepended to received packets
1267 * in packed stream mode
1268 */
1269#define	EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1270
1271/* Minimum space for packet in packed stream mode */
1272#define	EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE		\
1273	EFX_P2ROUNDUP(size_t,				\
1274	    EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE +	\
1275	    EFX_MAC_PDU_MIN +				\
1276	    EFX_RX_PACKED_STREAM_ALIGNMENT,		\
1277	    EFX_RX_PACKED_STREAM_ALIGNMENT)
1278
1279/* Maximum number of credits */
1280#define	EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1281
1282#endif /* EFSYS_OPT_RX_PACKED_STREAM */
1283
1284#if EFSYS_OPT_RX_ES_SUPER_BUFFER
1285
1286/*
1287 * Maximum DMA length and buffer stride alignment.
1288 * (see SF-119419-TC, 3.2)
1289 */
1290#define	EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT	64
1291
1292#endif
1293
1294#ifdef	__cplusplus
1295}
1296#endif
1297
1298#endif	/* _SYS_EF10_IMPL_H */
1299