1/*******************************************************************************
2SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3
4Copyright (c) 2006-2009, Myricom Inc.
5All rights reserved.
6
7Redistribution and use in source and binary forms, with or without
8modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11    this list of conditions and the following disclaimer.
12
13 2. Neither the name of the Myricom Inc, nor the names of its
14    contributors may be used to endorse or promote products derived from
15    this software without specific prior written permission.
16
17THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27POSSIBILITY OF SUCH DAMAGE.
28
29$FreeBSD$
30***************************************************************************/
31
32#ifndef _myri10ge_mcp_h
33#define _myri10ge_mcp_h
34
35#define MXGEFW_VERSION_MAJOR	1
36#define MXGEFW_VERSION_MINOR	4
37
38#if defined MXGEFW && !defined _stdint_h_
39typedef signed char          int8_t;
40typedef signed short        int16_t;
41typedef signed int          int32_t;
42typedef signed long long    int64_t;
43typedef unsigned char       uint8_t;
44typedef unsigned short     uint16_t;
45typedef unsigned int       uint32_t;
46typedef unsigned long long uint64_t;
47#endif
48
49/* 8 Bytes */
50struct mcp_dma_addr {
51  uint32_t high;
52  uint32_t low;
53};
54typedef struct mcp_dma_addr mcp_dma_addr_t;
55
56/* 4 Bytes */
57struct mcp_slot {
58  uint16_t checksum;
59  uint16_t length;
60};
61typedef struct mcp_slot mcp_slot_t;
62
63#ifdef MXGEFW_NDIS
64/* 8-byte descriptor, exclusively used by NDIS drivers. */
65struct mcp_slot_8 {
66  /* Place hash value at the top so it gets written before length.
67   * The driver polls length.
68   */
69  uint32_t hash;
70  uint16_t checksum;
71  uint16_t length;
72};
73typedef struct mcp_slot_8 mcp_slot_8_t;
74
75/* Two bits of length in mcp_slot are used to indicate hash type. */
76#define MXGEFW_RSS_HASH_NULL (0 << 14) /* bit 15:14 = 00 */
77#define MXGEFW_RSS_HASH_IPV4 (1 << 14) /* bit 15:14 = 01 */
78#define MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) /* bit 15:14 = 10 */
79#define MXGEFW_RSS_HASH_MASK (3 << 14) /* bit 15:14 = 11 */
80#endif
81
82/* 64 Bytes */
83struct mcp_cmd {
84  uint32_t cmd;
85  uint32_t data0;	/* will be low portion if data > 32 bits */
86  /* 8 */
87  uint32_t data1;	/* will be high portion if data > 32 bits */
88  uint32_t data2;	/* currently unused.. */
89  /* 16 */
90  struct mcp_dma_addr response_addr;
91  /* 24 */
92  uint8_t pad[40];
93};
94typedef struct mcp_cmd mcp_cmd_t;
95
96/* 8 Bytes */
97struct mcp_cmd_response {
98  uint32_t data;
99  uint32_t result;
100};
101typedef struct mcp_cmd_response mcp_cmd_response_t;
102
103
104
105/*
106   flags used in mcp_kreq_ether_send_t:
107
108   The SMALL flag is only needed in the first segment. It is raised
109   for packets that are total less or equal 512 bytes.
110
111   The CKSUM flag must be set in all segments.
112
113   The PADDED flags is set if the packet needs to be padded, and it
114   must be set for all segments.
115
116   The  MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative
117   length of all previous segments was odd.
118*/
119
120
121#define MXGEFW_FLAGS_SMALL      0x1
122#define MXGEFW_FLAGS_TSO_HDR    0x1
123#define MXGEFW_FLAGS_FIRST      0x2
124#define MXGEFW_FLAGS_ALIGN_ODD  0x4
125#define MXGEFW_FLAGS_CKSUM      0x8
126#define MXGEFW_FLAGS_TSO_LAST   0x8
127#define MXGEFW_FLAGS_NO_TSO     0x10
128#define MXGEFW_FLAGS_TSO_CHOP   0x10
129#define MXGEFW_FLAGS_TSO_PLD    0x20
130
131#define MXGEFW_SEND_SMALL_SIZE  1520
132#define MXGEFW_MAX_MTU          9400
133
134union mcp_pso_or_cumlen {
135  uint16_t pseudo_hdr_offset;
136  uint16_t cum_len;
137};
138typedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t;
139
140#define	MXGEFW_MAX_SEND_DESC 12
141#define MXGEFW_PAD	    2
142
143/* 16 Bytes */
144struct mcp_kreq_ether_send {
145  uint32_t addr_high;
146  uint32_t addr_low;
147  uint16_t pseudo_hdr_offset;
148  uint16_t length;
149  uint8_t  pad;
150  uint8_t  rdma_count;
151  uint8_t  cksum_offset; 	/* where to start computing cksum */
152  uint8_t  flags;	       	/* as defined above */
153};
154typedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t;
155
156/* 8 Bytes */
157struct mcp_kreq_ether_recv {
158  uint32_t addr_high;
159  uint32_t addr_low;
160};
161typedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t;
162
163
164/* Commands */
165
166#define	MXGEFW_BOOT_HANDOFF	0xfc0000
167#define	MXGEFW_BOOT_DUMMY_RDMA	0xfc01c0
168
169#define	MXGEFW_ETH_CMD		0xf80000
170#define	MXGEFW_ETH_SEND_4	0x200000
171#define	MXGEFW_ETH_SEND_1	0x240000
172#define	MXGEFW_ETH_SEND_2	0x280000
173#define	MXGEFW_ETH_SEND_3	0x2c0000
174#define	MXGEFW_ETH_RECV_SMALL	0x300000
175#define	MXGEFW_ETH_RECV_BIG	0x340000
176#define	MXGEFW_ETH_SEND_GO	0x380000
177#define	MXGEFW_ETH_SEND_STOP	0x3C0000
178
179#define	MXGEFW_ETH_SEND(n)		(0x200000 + (((n) & 0x03) * 0x40000))
180#define	MXGEFW_ETH_SEND_OFFSET(n)	(MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4)
181
182enum myri10ge_mcp_cmd_type {
183  MXGEFW_CMD_NONE = 0,
184  /* Reset the mcp, it is left in a safe state, waiting
185     for the driver to set all its parameters */
186  MXGEFW_CMD_RESET = 1,
187
188  /* get the version number of the current firmware..
189     (may be available in the eeprom strings..? */
190  MXGEFW_GET_MCP_VERSION = 2,
191
192
193  /* Parameters which must be set by the driver before it can
194     issue MXGEFW_CMD_ETHERNET_UP. They persist until the next
195     MXGEFW_CMD_RESET is issued */
196
197  MXGEFW_CMD_SET_INTRQ_DMA = 3,
198  /* data0 = LSW of the host address
199   * data1 = MSW of the host address
200   * data2 = slice number if multiple slices are used
201   */
202
203  MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4,	/* in bytes, power of 2 */
204  MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5,	/* in bytes */
205
206
207  /* Parameters which refer to lanai SRAM addresses where the
208     driver must issue PIO writes for various things */
209
210  MXGEFW_CMD_GET_SEND_OFFSET = 6,
211  MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7,
212  MXGEFW_CMD_GET_BIG_RX_OFFSET = 8,
213  /* data0 = slice number if multiple slices are used */
214
215  MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9,
216  MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10,
217
218  /* Parameters which refer to rings stored on the MCP,
219     and whose size is controlled by the mcp */
220
221  MXGEFW_CMD_GET_SEND_RING_SIZE = 11,	/* in bytes */
222  MXGEFW_CMD_GET_RX_RING_SIZE = 12,	/* in bytes */
223
224  /* Parameters which refer to rings stored in the host,
225     and whose size is controlled by the host.  Note that
226     all must be physically contiguous and must contain
227     a power of 2 number of entries.  */
228
229  MXGEFW_CMD_SET_INTRQ_SIZE = 13, 	/* in bytes */
230#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK  (1U << 31)
231
232  /* command to bring ethernet interface up.  Above parameters
233     (plus mtu & mac address) must have been exchanged prior
234     to issuing this command  */
235  MXGEFW_CMD_ETHERNET_UP = 14,
236
237  /* command to bring ethernet interface down.  No further sends
238     or receives may be processed until an MXGEFW_CMD_ETHERNET_UP
239     is issued, and all interrupt queues must be flushed prior
240     to ack'ing this command */
241
242  MXGEFW_CMD_ETHERNET_DOWN = 15,
243
244  /* commands the driver may issue live, without resetting
245     the nic.  Note that increasing the mtu "live" should
246     only be done if the driver has already supplied buffers
247     sufficiently large to handle the new mtu.  Decreasing
248     the mtu live is safe */
249
250  MXGEFW_CMD_SET_MTU = 16,
251  MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17,  /* in microseconds */
252  MXGEFW_CMD_SET_STATS_INTERVAL = 18,   /* in microseconds */
253  MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */
254
255  MXGEFW_ENABLE_PROMISC = 20,
256  MXGEFW_DISABLE_PROMISC = 21,
257  MXGEFW_SET_MAC_ADDRESS = 22,
258
259  MXGEFW_ENABLE_FLOW_CONTROL = 23,
260  MXGEFW_DISABLE_FLOW_CONTROL = 24,
261
262  /* do a DMA test
263     data0,data1 = DMA address
264     data2       = RDMA length (MSH), WDMA length (LSH)
265     command return data = repetitions (MSH), 0.5-ms ticks (LSH)
266  */
267  MXGEFW_DMA_TEST = 25,
268
269  MXGEFW_ENABLE_ALLMULTI = 26,
270  MXGEFW_DISABLE_ALLMULTI = 27,
271
272  /* returns MXGEFW_CMD_ERROR_MULTICAST
273     if there is no room in the cache
274     data0,MSH(data1) = multicast group address */
275  MXGEFW_JOIN_MULTICAST_GROUP = 28,
276  /* returns MXGEFW_CMD_ERROR_MULTICAST
277     if the address is not in the cache,
278     or is equal to FF-FF-FF-FF-FF-FF
279     data0,MSH(data1) = multicast group address */
280  MXGEFW_LEAVE_MULTICAST_GROUP = 29,
281  MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30,
282
283  MXGEFW_CMD_SET_STATS_DMA_V2 = 31,
284  /* data0, data1 = bus addr,
285   * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows
286   * adding new stuff to mcp_irq_data without changing the ABI
287   *
288   * If multiple slices are used, data2 contains both the size of the
289   * structure (in the lower 16 bits) and the slice number
290   * (in the upper 16 bits).
291   */
292
293  MXGEFW_CMD_UNALIGNED_TEST = 32,
294  /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned
295     chipset */
296
297  MXGEFW_CMD_UNALIGNED_STATUS = 33,
298  /* return data = boolean, true if the chipset is known to be unaligned */
299
300  MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34,
301  /* data0 = number of big buffers to use.  It must be 0 or a power of 2.
302   * 0 indicates that the NIC consumes as many buffers as they are required
303   * for packet. This is the default behavior.
304   * A power of 2 number indicates that the NIC always uses the specified
305   * number of buffers for each big receive packet.
306   * It is up to the driver to ensure that this value is big enough for
307   * the NIC to be able to receive maximum-sized packets.
308   */
309
310  MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35,
311  MXGEFW_CMD_ENABLE_RSS_QUEUES = 36,
312  /* data0 = number of slices n (0, 1, ..., n-1) to enable
313   * data1 = interrupt mode | use of multiple transmit queues.
314   * 0=share one INTx/MSI.
315   * 1=use one MSI-X per queue.
316   * If all queues share one interrupt, the driver must have set
317   * RSS_SHARED_INTERRUPT_DMA before enabling queues.
318   * 2=enable both receive and send queues.
319   * Without this bit set, only one send queue (slice 0's send queue)
320   * is enabled.  The receive queues are always enabled.
321   */
322#define MXGEFW_SLICE_INTR_MODE_SHARED          0x0
323#define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE   0x1
324#define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2
325
326  MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37,
327  MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38,
328  /* data0, data1 = bus address lsw, msw */
329  MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39,
330  /* get the offset of the indirection table */
331  MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40,
332  /* set the size of the indirection table */
333  MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41,
334  /* get the offset of the secret key */
335  MXGEFW_CMD_RSS_KEY_UPDATED = 42,
336  /* tell nic that the secret key's been updated */
337  MXGEFW_CMD_SET_RSS_ENABLE = 43,
338  /* data0 = enable/disable rss
339   * 0: disable rss.  nic does not distribute receive packets.
340   * 1: enable rss.  nic distributes receive packets among queues.
341   * data1 = hash type
342   * 1: IPV4            (required by RSS)
343   * 2: TCP_IPV4        (required by RSS)
344   * 3: IPV4 | TCP_IPV4 (required by RSS)
345   * 4: source port
346   * 5: source port + destination port
347   */
348#define MXGEFW_RSS_HASH_TYPE_IPV4      0x1
349#define MXGEFW_RSS_HASH_TYPE_TCP_IPV4  0x2
350#define MXGEFW_RSS_HASH_TYPE_SRC_PORT  0x4
351#define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5
352#define MXGEFW_RSS_HASH_TYPE_MAX 0x5
353
354  MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44,
355  /* Return data = the max. size of the entire headers of a IPv6 TSO packet.
356   * If the header size of a IPv6 TSO packet is larger than the specified
357   * value, then the driver must not use TSO.
358   * This size restriction only applies to IPv6 TSO.
359   * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC
360   * always has enough header buffer to store maximum-sized headers.
361   */
362
363  MXGEFW_CMD_SET_TSO_MODE = 45,
364  /* data0 = TSO mode.
365   * 0: Linux/FreeBSD style (NIC default)
366   * 1: NDIS/NetBSD style
367   */
368#define MXGEFW_TSO_MODE_LINUX  0
369#define MXGEFW_TSO_MODE_NDIS   1
370
371  MXGEFW_CMD_MDIO_READ = 46,
372  /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */
373  MXGEFW_CMD_MDIO_WRITE = 47,
374  /* data0 = dev_addr,  data1 = register/addr, data2 = value  */
375
376  MXGEFW_CMD_I2C_READ = 48,
377  /* Starts to get a fresh copy of one byte or of the module i2c table, the
378   * obtained data is cached inside the xaui-xfi chip :
379   *   data0 :  0 => get one byte, 1=> get 256 bytes
380   *   data1 :  If data0 == 0: location to refresh
381   *               bit 7:0  register location
382   *               bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1)
383   *               bit 23:16 is the i2c bus number (for multi-port NICs)
384   *            If data0 == 1: unused
385   * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes
386   * During the i2c operation,  MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts
387   *  will return MXGEFW_CMD_ERROR_BUSY
388   */
389  MXGEFW_CMD_I2C_BYTE = 49,
390  /* Return the last obtained copy of a given byte in the xfp i2c table
391   * (copy cached during the last relevant MXGEFW_CMD_I2C_READ)
392   *   data0 : index of the desired table entry
393   *  Return data = the byte stored at the requested index in the table
394   */
395
396  MXGEFW_CMD_GET_VPUMP_OFFSET = 50,
397  /* Return data = NIC memory offset of mcp_vpump_public_global */
398  MXGEFW_CMD_RESET_VPUMP = 51,
399  /* Resets the VPUMP state */
400
401  MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52,
402  /* data0 = mcp_slot type to use.
403   * 0 = the default 4B mcp_slot
404   * 1 = 8B mcp_slot_8
405   */
406#define MXGEFW_RSS_MCP_SLOT_TYPE_MIN        0
407#define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH  1
408
409  MXGEFW_CMD_SET_THROTTLE_FACTOR = 53,
410  /* set the throttle factor for ethp_z8e
411     data0 = throttle_factor
412     throttle_factor = 256 * pcie-raw-speed / tx_speed
413     tx_speed = 256 * pcie-raw-speed / throttle_factor
414
415     For PCI-E x8: pcie-raw-speed == 16Gb/s
416     For PCI-E x4: pcie-raw-speed == 8Gb/s
417
418     ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s
419     ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s
420
421     with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s
422     with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s
423  */
424
425  MXGEFW_CMD_VPUMP_UP = 54,
426  /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */
427  MXGEFW_CMD_GET_VPUMP_CLK = 55,
428  /* Get the lanai clock */
429
430  MXGEFW_CMD_GET_DCA_OFFSET = 56,
431  /* offset of dca control for WDMAs */
432
433  /* VMWare NetQueue commands */
434  MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57,
435  MXGEFW_CMD_NETQ_ADD_FILTER = 58,
436  /* data0 = filter_id << 16 | queue << 8 | type */
437  /* data1 = MS4 of MAC Addr */
438  /* data2 = LS2_MAC << 16 | VLAN_tag */
439  MXGEFW_CMD_NETQ_DEL_FILTER = 59,
440  /* data0 = filter_id */
441  MXGEFW_CMD_NETQ_QUERY1 = 60,
442  MXGEFW_CMD_NETQ_QUERY2 = 61,
443  MXGEFW_CMD_NETQ_QUERY3 = 62,
444  MXGEFW_CMD_NETQ_QUERY4 = 63,
445
446  MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64,
447  /* When set, small receive buffers can cross page boundaries.
448   * Both small and big receive buffers may start at any address.
449   * This option has performance implications, so use with caution.
450   */
451};
452typedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t;
453
454
455enum myri10ge_mcp_cmd_status {
456  MXGEFW_CMD_OK = 0,
457  MXGEFW_CMD_UNKNOWN = 1,
458  MXGEFW_CMD_ERROR_RANGE = 2,
459  MXGEFW_CMD_ERROR_BUSY = 3,
460  MXGEFW_CMD_ERROR_EMPTY = 4,
461  MXGEFW_CMD_ERROR_CLOSED = 5,
462  MXGEFW_CMD_ERROR_HASH_ERROR = 6,
463  MXGEFW_CMD_ERROR_BAD_PORT = 7,
464  MXGEFW_CMD_ERROR_RESOURCES = 8,
465  MXGEFW_CMD_ERROR_MULTICAST = 9,
466  MXGEFW_CMD_ERROR_UNALIGNED = 10,
467  MXGEFW_CMD_ERROR_NO_MDIO = 11,
468  MXGEFW_CMD_ERROR_I2C_FAILURE = 12,
469  MXGEFW_CMD_ERROR_I2C_ABSENT = 13,
470  MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14
471};
472typedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t;
473
474
475#define MXGEFW_OLD_IRQ_DATA_LEN 40
476
477struct mcp_irq_data {
478  /* add new counters at the beginning */
479  uint32_t future_use[1];
480  uint32_t dropped_pause;
481  uint32_t dropped_unicast_filtered;
482  uint32_t dropped_bad_crc32;
483  uint32_t dropped_bad_phy;
484  uint32_t dropped_multicast_filtered;
485/* 40 Bytes */
486  uint32_t send_done_count;
487
488#define MXGEFW_LINK_DOWN 0
489#define MXGEFW_LINK_UP 1
490#define MXGEFW_LINK_MYRINET 2
491#define MXGEFW_LINK_UNKNOWN 3
492  uint32_t link_up;
493  uint32_t dropped_link_overflow;
494  uint32_t dropped_link_error_or_filtered;
495  uint32_t dropped_runt;
496  uint32_t dropped_overrun;
497  uint32_t dropped_no_small_buffer;
498  uint32_t dropped_no_big_buffer;
499  uint32_t rdma_tags_available;
500
501  uint8_t tx_stopped;
502  uint8_t link_down;
503  uint8_t stats_updated;
504  uint8_t valid;
505};
506typedef struct mcp_irq_data mcp_irq_data_t;
507
508#ifdef MXGEFW_NDIS
509/* Exclusively used by NDIS drivers */
510struct mcp_rss_shared_interrupt {
511  uint8_t pad[2];
512  uint8_t queue;
513  uint8_t valid;
514};
515#endif
516
517/* definitions for NETQ filter type */
518#define MXGEFW_NETQ_FILTERTYPE_NONE 0
519#define MXGEFW_NETQ_FILTERTYPE_MACADDR 1
520#define MXGEFW_NETQ_FILTERTYPE_VLAN 2
521#define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3
522
523#endif /* _myri10ge_mcp_h */
524