1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2010 George V. Neville-Neil <gnn@freebsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD$");
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/pmc.h>
36#include <sys/pmckern.h>
37
38#include <machine/cpu.h>
39#include <machine/cpufunc.h>
40#include <machine/pmc_mdep.h>
41
42#define	MIPS24K_PMC_CAPS	(PMC_CAP_INTERRUPT | PMC_CAP_USER |     \
43				 PMC_CAP_SYSTEM | PMC_CAP_EDGE |	\
44				 PMC_CAP_THRESHOLD | PMC_CAP_READ |	\
45				 PMC_CAP_WRITE | PMC_CAP_INVERT |	\
46				 PMC_CAP_QUALIFIER)
47
48#define MIPS24K_PMC_INTERRUPT_ENABLE      0x10 /* Enable interrupts */
49#define MIPS24K_PMC_USER_ENABLE           0x08 /* Count in USER mode */
50#define MIPS24K_PMC_SUPER_ENABLE          0x04 /* Count in SUPERVISOR mode */
51#define MIPS24K_PMC_KERNEL_ENABLE         0x02 /* Count in KERNEL mode */
52#define MIPS24K_PMC_ENABLE (MIPS24K_PMC_USER_ENABLE |	   \
53			    MIPS24K_PMC_SUPER_ENABLE |	   \
54			    MIPS24K_PMC_KERNEL_ENABLE)
55
56#define MIPS24K_PMC_SELECT 5 /* Which bit position the event starts at. */
57
58const struct mips_event_code_map mips_event_codes[] = {
59	{ PMC_EV_MIPS24K_CYCLE, MIPS_CTR_ALL, 0},
60	{ PMC_EV_MIPS24K_INSTR_EXECUTED, MIPS_CTR_ALL, 1},
61	{ PMC_EV_MIPS24K_BRANCH_COMPLETED, MIPS_CTR_0, 2},
62	{ PMC_EV_MIPS24K_BRANCH_MISPRED, MIPS_CTR_1, 2},
63	{ PMC_EV_MIPS24K_RETURN, MIPS_CTR_0, 3},
64	{ PMC_EV_MIPS24K_RETURN_MISPRED, MIPS_CTR_1, 3},
65	{ PMC_EV_MIPS24K_RETURN_NOT_31, MIPS_CTR_0, 4},
66	{ PMC_EV_MIPS24K_RETURN_NOTPRED, MIPS_CTR_1, 4},
67	{ PMC_EV_MIPS24K_ITLB_ACCESS, MIPS_CTR_0, 5},
68	{ PMC_EV_MIPS24K_ITLB_MISS, MIPS_CTR_1, 5},
69	{ PMC_EV_MIPS24K_DTLB_ACCESS, MIPS_CTR_0, 6},
70	{ PMC_EV_MIPS24K_DTLB_MISS, MIPS_CTR_1, 6},
71	{ PMC_EV_MIPS24K_JTLB_IACCESS, MIPS_CTR_0, 7},
72	{ PMC_EV_MIPS24K_JTLB_IMISS, MIPS_CTR_1, 7},
73	{ PMC_EV_MIPS24K_JTLB_DACCESS, MIPS_CTR_0, 8},
74	{ PMC_EV_MIPS24K_JTLB_DMISS, MIPS_CTR_1, 8},
75	{ PMC_EV_MIPS24K_IC_FETCH, MIPS_CTR_0, 9},
76	{ PMC_EV_MIPS24K_IC_MISS, MIPS_CTR_1, 9},
77	{ PMC_EV_MIPS24K_DC_LOADSTORE, MIPS_CTR_0, 10},
78	{ PMC_EV_MIPS24K_DC_WRITEBACK, MIPS_CTR_1, 10},
79	{ PMC_EV_MIPS24K_DC_MISS, MIPS_CTR_ALL, 11},
80	/* 12 reserved */
81	{ PMC_EV_MIPS24K_STORE_MISS, MIPS_CTR_0, 13},
82	{ PMC_EV_MIPS24K_LOAD_MISS, MIPS_CTR_1, 13},
83	{ PMC_EV_MIPS24K_INTEGER_COMPLETED, MIPS_CTR_0, 14},
84	{ PMC_EV_MIPS24K_FP_COMPLETED, MIPS_CTR_1, 14},
85	{ PMC_EV_MIPS24K_LOAD_COMPLETED, MIPS_CTR_0, 15},
86	{ PMC_EV_MIPS24K_STORE_COMPLETED, MIPS_CTR_1, 15},
87	{ PMC_EV_MIPS24K_BARRIER_COMPLETED, MIPS_CTR_0, 16},
88	{ PMC_EV_MIPS24K_MIPS16_COMPLETED, MIPS_CTR_1, 16},
89	{ PMC_EV_MIPS24K_NOP_COMPLETED, MIPS_CTR_0, 17},
90	{ PMC_EV_MIPS24K_INTEGER_MULDIV_COMPLETED, MIPS_CTR_1, 17},
91	{ PMC_EV_MIPS24K_RF_STALL, MIPS_CTR_0, 18},
92	{ PMC_EV_MIPS24K_INSTR_REFETCH, MIPS_CTR_1, 18},
93	{ PMC_EV_MIPS24K_STORE_COND_COMPLETED, MIPS_CTR_0, 19},
94	{ PMC_EV_MIPS24K_STORE_COND_FAILED, MIPS_CTR_1, 19},
95	{ PMC_EV_MIPS24K_ICACHE_REQUESTS, MIPS_CTR_0, 20},
96	{ PMC_EV_MIPS24K_ICACHE_HIT, MIPS_CTR_1, 20},
97	{ PMC_EV_MIPS24K_L2_WRITEBACK, MIPS_CTR_0, 21},
98	{ PMC_EV_MIPS24K_L2_ACCESS, MIPS_CTR_1, 21},
99	{ PMC_EV_MIPS24K_L2_MISS, MIPS_CTR_0, 22},
100	{ PMC_EV_MIPS24K_L2_ERR_CORRECTED, MIPS_CTR_1, 22},
101	{ PMC_EV_MIPS24K_EXCEPTIONS, MIPS_CTR_0, 23},
102	/* Event 23 on COP0 1/3 is undefined */
103	{ PMC_EV_MIPS24K_RF_CYCLES_STALLED, MIPS_CTR_0, 24},
104	{ PMC_EV_MIPS24K_IFU_CYCLES_STALLED, MIPS_CTR_0, 25},
105	{ PMC_EV_MIPS24K_ALU_CYCLES_STALLED, MIPS_CTR_1, 25},
106	/* Events 26 through 32 undefined or reserved to customers */
107	{ PMC_EV_MIPS24K_UNCACHED_LOAD, MIPS_CTR_0, 33},
108	{ PMC_EV_MIPS24K_UNCACHED_STORE, MIPS_CTR_1, 33},
109	{ PMC_EV_MIPS24K_CP2_REG_TO_REG_COMPLETED, MIPS_CTR_0, 35},
110	{ PMC_EV_MIPS24K_MFTC_COMPLETED, MIPS_CTR_1, 35},
111	/* Event 36 reserved */
112	{ PMC_EV_MIPS24K_IC_BLOCKED_CYCLES, MIPS_CTR_0, 37},
113	{ PMC_EV_MIPS24K_DC_BLOCKED_CYCLES, MIPS_CTR_1, 37},
114	{ PMC_EV_MIPS24K_L2_IMISS_STALL_CYCLES, MIPS_CTR_0, 38},
115	{ PMC_EV_MIPS24K_L2_DMISS_STALL_CYCLES, MIPS_CTR_1, 38},
116	{ PMC_EV_MIPS24K_DMISS_CYCLES, MIPS_CTR_0, 39},
117	{ PMC_EV_MIPS24K_L2_MISS_CYCLES, MIPS_CTR_1, 39},
118	{ PMC_EV_MIPS24K_UNCACHED_BLOCK_CYCLES, MIPS_CTR_0, 40},
119	{ PMC_EV_MIPS24K_MDU_STALL_CYCLES, MIPS_CTR_0, 41},
120	{ PMC_EV_MIPS24K_FPU_STALL_CYCLES, MIPS_CTR_1, 41},
121	{ PMC_EV_MIPS24K_CP2_STALL_CYCLES, MIPS_CTR_0, 42},
122	{ PMC_EV_MIPS24K_COREXTEND_STALL_CYCLES, MIPS_CTR_1, 42},
123	{ PMC_EV_MIPS24K_ISPRAM_STALL_CYCLES, MIPS_CTR_0, 43},
124	{ PMC_EV_MIPS24K_DSPRAM_STALL_CYCLES, MIPS_CTR_1, 43},
125	{ PMC_EV_MIPS24K_CACHE_STALL_CYCLES, MIPS_CTR_0, 44},
126	/* Event 44 undefined on 1/3 */
127	{ PMC_EV_MIPS24K_LOAD_TO_USE_STALLS, MIPS_CTR_0, 45},
128	{ PMC_EV_MIPS24K_BASE_MISPRED_STALLS, MIPS_CTR_1, 45},
129	{ PMC_EV_MIPS24K_CPO_READ_STALLS, MIPS_CTR_0, 46},
130	{ PMC_EV_MIPS24K_BRANCH_MISPRED_CYCLES, MIPS_CTR_1, 46},
131	/* Event 47 reserved */
132	{ PMC_EV_MIPS24K_IFETCH_BUFFER_FULL, MIPS_CTR_0, 48},
133	{ PMC_EV_MIPS24K_FETCH_BUFFER_ALLOCATED, MIPS_CTR_1, 48},
134	{ PMC_EV_MIPS24K_EJTAG_ITRIGGER, MIPS_CTR_0, 49},
135	{ PMC_EV_MIPS24K_EJTAG_DTRIGGER, MIPS_CTR_1, 49},
136	{ PMC_EV_MIPS24K_FSB_LT_QUARTER, MIPS_CTR_0, 50},
137	{ PMC_EV_MIPS24K_FSB_QUARTER_TO_HALF, MIPS_CTR_1, 50},
138	{ PMC_EV_MIPS24K_FSB_GT_HALF, MIPS_CTR_0, 51},
139	{ PMC_EV_MIPS24K_FSB_FULL_PIPELINE_STALLS, MIPS_CTR_1, 51},
140	{ PMC_EV_MIPS24K_LDQ_LT_QUARTER, MIPS_CTR_0, 52},
141	{ PMC_EV_MIPS24K_LDQ_QUARTER_TO_HALF, MIPS_CTR_1, 52},
142	{ PMC_EV_MIPS24K_LDQ_GT_HALF, MIPS_CTR_0, 53},
143	{ PMC_EV_MIPS24K_LDQ_FULL_PIPELINE_STALLS, MIPS_CTR_1, 53},
144	{ PMC_EV_MIPS24K_WBB_LT_QUARTER, MIPS_CTR_0, 54},
145	{ PMC_EV_MIPS24K_WBB_QUARTER_TO_HALF, MIPS_CTR_1, 54},
146	{ PMC_EV_MIPS24K_WBB_GT_HALF, MIPS_CTR_0, 55},
147	{ PMC_EV_MIPS24K_WBB_FULL_PIPELINE_STALLS, MIPS_CTR_1, 55},
148	/* Events 56-63 reserved */
149	{ PMC_EV_MIPS24K_REQUEST_LATENCY, MIPS_CTR_0, 61},
150	{ PMC_EV_MIPS24K_REQUEST_COUNT, MIPS_CTR_1, 61}
151
152};
153
154const int mips_event_codes_size = nitems(mips_event_codes);
155
156struct mips_pmc_spec mips_pmc_spec = {
157	.ps_cpuclass = PMC_CLASS_MIPS24K,
158	.ps_cputype = PMC_CPU_MIPS_24K,
159	.ps_capabilities = MIPS24K_PMC_CAPS,
160	.ps_counter_width = 32
161};
162
163/*
164 * Performance Count Register N
165 */
166uint64_t
167mips_pmcn_read(unsigned int pmc)
168{
169	uint32_t reg = 0;
170
171	KASSERT(pmc < mips_npmcs, ("[mips24k,%d] illegal PMC number %d",
172				   __LINE__, pmc));
173
174	/* The counter value is the next value after the control register. */
175	switch (pmc) {
176	case 0:
177		reg = mips_rd_perfcnt1();
178		break;
179	case 1:
180		reg = mips_rd_perfcnt3();
181		break;
182	default:
183		return 0;
184	}
185	return (reg);
186}
187
188uint64_t
189mips_pmcn_write(unsigned int pmc, uint64_t reg)
190{
191
192	KASSERT(pmc < mips_npmcs, ("[mips24k,%d] illegal PMC number %d",
193				   __LINE__, pmc));
194
195	switch (pmc) {
196	case 0:
197		mips_wr_perfcnt1(reg);
198		break;
199	case 1:
200		mips_wr_perfcnt3(reg);
201		break;
202	default:
203		return 0;
204	}
205	return (reg);
206}
207
208uint32_t
209mips_get_perfctl(int cpu, int ri, uint32_t event, uint32_t caps)
210{
211	uint32_t config;
212
213	config = event;
214
215	config <<= MIPS24K_PMC_SELECT;
216
217	if (caps & PMC_CAP_SYSTEM)
218		config |= (MIPS24K_PMC_SUPER_ENABLE |
219			   MIPS24K_PMC_KERNEL_ENABLE);
220	if (caps & PMC_CAP_USER)
221		config |= MIPS24K_PMC_USER_ENABLE;
222	if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
223		config |= MIPS24K_PMC_ENABLE;
224	if (caps & PMC_CAP_INTERRUPT)
225		config |= MIPS24K_PMC_INTERRUPT_ENABLE;
226
227	PMCDBG2(MDP,ALL,2,"mips24k-get_perfctl ri=%d -> config=0x%x", ri, config);
228
229	return (config);
230}
231