1/*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2006-2014 QLogic Corporation 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 25 * THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30#ifndef _BCEREG_H_DEFINED 31#define _BCEREG_H_DEFINED 32 33/****************************************************************************/ 34/* Conversion to FreeBSD type definitions. */ 35/****************************************************************************/ 36#define u64 uint64_t 37#define u32 uint32_t 38#define u16 uint16_t 39#define u8 uint8_t 40 41#if BYTE_ORDER == BIG_ENDIAN 42#define __BIG_ENDIAN 1 43#undef __LITTLE_ENDIAN 44#else 45#undef __BIG_ENDIAN 46#define __LITTLE_ENDIAN 1 47#endif 48 49#define BCE_DWORD_PRINTFB \ 50 "\020" \ 51 "\40b31" \ 52 "\37b30" \ 53 "\36b29" \ 54 "\35b28" \ 55 "\34b27" \ 56 "\33b26" \ 57 "\32b25" \ 58 "\31b24" \ 59 "\30b23" \ 60 "\27b22" \ 61 "\26b21" \ 62 "\25b20" \ 63 "\24b19" \ 64 "\23b18" \ 65 "\22b17" \ 66 "\21b16" \ 67 "\20b15" \ 68 "\17b14" \ 69 "\16b13" \ 70 "\15b12" \ 71 "\14b11" \ 72 "\13b10" \ 73 "\12b9" \ 74 "\11b8" \ 75 "\10b7" \ 76 "\07b6" \ 77 "\06b5" \ 78 "\05b4" \ 79 "\04b3" \ 80 "\03b2" \ 81 "\02b1" \ 82 "\01b0" 83 84/* MII Control Register 0x0 */ 85#define BCE_BMCR_PRINTFB \ 86 "\020" \ 87 "\20Reset" \ 88 "\17Loopback" \ 89 "\16Spd0" \ 90 "\15AnegEna" \ 91 "\14PwrDn" \ 92 "\13Isolate" \ 93 "\12RstrtAneg" \ 94 "\11FD" \ 95 "\10CollTst" \ 96 "\07Spd1" \ 97 "\06Rsrvd" \ 98 "\05Rsrvd" \ 99 "\04Rsrvd" \ 100 "\03Rsrvd" \ 101 "\02Rsrvd" \ 102 "\01Rsrvd" 103 104/* MII Status Register 0x1 */ 105#define BCE_BMSR_PRINTFB \ 106 "\020" \ 107 "\20Cap100T4" \ 108 "\17Cap100XFD" \ 109 "\16Cap100XHD" \ 110 "\15Cap10FD" \ 111 "\14Cap10HD" \ 112 "\13Cap100T2FD" \ 113 "\12Cap100T2HD" \ 114 "\11ExtStsPrsnt" \ 115 "\10Rsrvd" \ 116 "\07PrmblSupp" \ 117 "\06AnegCmpl" \ 118 "\05RemFaultDet" \ 119 "\04AnegCap" \ 120 "\03LnkUp" \ 121 "\02JabberDet" \ 122 "\01ExtCapSupp" 123 124/* MII Autoneg Advertisement Register 0x4 */ 125#define BCE_ANAR_PRINTFB \ 126 "\020" \ 127 "\20AdvNxtPg" \ 128 "\17Rsrvd" \ 129 "\16AdvRemFault" \ 130 "\15Rsrvd" \ 131 "\14AdvAsymPause" \ 132 "\13AdvPause" \ 133 "\12Adv100T4" \ 134 "\11Adv100FD" \ 135 "\10Adv100HD" \ 136 "\07Adv10FD" \ 137 "\06Adv10HD" \ 138 "\05Rsrvd" \ 139 "\04Rsrvd" \ 140 "\03Rsrvd" \ 141 "\02Rsrvd" \ 142 "\01Adv802.3" 143 144/* MII Autoneg Link Partner Ability Register 0x5 */ 145#define BCE_ANLPAR_PRINTFB \ 146 "\020" \ 147 "\20CapNxtPg" \ 148 "\17Ack" \ 149 "\16CapRemFault" \ 150 "\15Rsrvd" \ 151 "\14CapAsymPause" \ 152 "\13CapPause" \ 153 "\12Cap100T4" \ 154 "\11Cap100FD" \ 155 "\10Cap100HD" \ 156 "\07Cap10FD" \ 157 "\06Cap10HD" \ 158 "\05Rsrvd" \ 159 "\04Rsrvd" \ 160 "\03Rsrvd" \ 161 "\02Rsrvd" \ 162 "\01Cap802.3" 163 164/* 1000Base-T Control Register 0x09 */ 165#define BCE_1000CTL_PRINTFB \ 166 "\020" \ 167 "\20Test3" \ 168 "\17Test2" \ 169 "\16Test1" \ 170 "\15MasterSlave" \ 171 "\14ForceMaster" \ 172 "\13SwitchDev" \ 173 "\12Adv1000TFD" \ 174 "\11Adv1000THD" \ 175 "\10Rsrvd" \ 176 "\07Rsrvd" \ 177 "\06Rsrvd" \ 178 "\05Rsrvd" \ 179 "\04Rsrvd" \ 180 "\03Rsrvd" \ 181 "\02Rsrvd" \ 182 "\01Rsrvd" 183 184/* MII 1000Base-T Status Register 0x0a */ 185#define BCE_1000STS_PRINTFB \ 186 "\020" \ 187 "\20MstrSlvFault" \ 188 "\17Master" \ 189 "\16LclRcvrOk" \ 190 "\15RemRcvrOk" \ 191 "\14Cap1000FD" \ 192 "\13Cpa1000HD" \ 193 "\12Rsrvd" \ 194 "\11Rsrvd" 195 196/* MII Extended Status Register 0x0f */ 197#define BCE_EXTSTS_PRINTFB \ 198 "\020" \ 199 "\20b15" \ 200 "\17b14" \ 201 "\16b13" \ 202 "\15b12" \ 203 "\14Rsrvd" \ 204 "\13Rsrvd" \ 205 "\12Rsrvd" \ 206 "\11Rsrvd" \ 207 "\10Rsrvd" \ 208 "\07Rsrvd" \ 209 "\06Rsrvd" \ 210 "\05Rsrvd" \ 211 "\04Rsrvd" \ 212 "\03Rsrvd" \ 213 "\02Rsrvd" \ 214 "\01Rsrvd" 215 216/* MII Autoneg Link Partner Ability Register 0x19 */ 217#define BCE_AUXSTS_PRINTFB \ 218 "\020" \ 219 "\20AnegCmpl" \ 220 "\17AnegCmplAck" \ 221 "\16AnegAckDet" \ 222 "\15AnegAblDet" \ 223 "\14AnegNextPgWait" \ 224 "\13HCD" \ 225 "\12HCD" \ 226 "\11HCD" \ 227 "\10PrlDetFault" \ 228 "\07RemFault" \ 229 "\06PgRcvd" \ 230 "\05LnkPrtnrAnegAbl" \ 231 "\04LnkPrtnrNPAbl" \ 232 "\03LnkUp" \ 233 "\02EnaPauseRcv" \ 234 "\01EnaPausXmit" 235 236/* 237 * Remove before release: 238 * 239 * #define BCE_DEBUG 240 * #define BCE_NVRAM_WRITE_SUPPORT 241 */ 242 243/****************************************************************************/ 244/* Debugging macros and definitions. */ 245/****************************************************************************/ 246 247#define BCE_CP_LOAD 0x00000001 248#define BCE_CP_SEND 0x00000002 249#define BCE_CP_RECV 0x00000004 250#define BCE_CP_INTR 0x00000008 251#define BCE_CP_UNLOAD 0x00000010 252#define BCE_CP_RESET 0x00000020 253#define BCE_CP_PHY 0x00000040 254#define BCE_CP_NVRAM 0x00000080 255#define BCE_CP_FIRMWARE 0x00000100 256#define BCE_CP_CTX 0x00000200 257#define BCE_CP_REG 0x00000400 258#define BCE_CP_MISC 0x00400000 259#define BCE_CP_SPECIAL 0x00800000 260#define BCE_CP_ALL 0x00FFFFFF 261 262#define BCE_CP_MASK 0x00FFFFFF 263 264#define BCE_LEVEL_FATAL 0x00000000 265#define BCE_LEVEL_WARN 0x01000000 266#define BCE_LEVEL_INFO 0x02000000 267#define BCE_LEVEL_VERBOSE 0x03000000 268#define BCE_LEVEL_EXTREME 0x04000000 269#define BCE_LEVEL_INSANE 0x05000000 270 271#define BCE_LEVEL_MASK 0xFF000000 272 273#define BCE_WARN_LOAD (BCE_CP_LOAD | BCE_LEVEL_WARN) 274#define BCE_INFO_LOAD (BCE_CP_LOAD | BCE_LEVEL_INFO) 275#define BCE_VERBOSE_LOAD (BCE_CP_LOAD | BCE_LEVEL_VERBOSE) 276#define BCE_EXTREME_LOAD (BCE_CP_LOAD | BCE_LEVEL_EXTREME) 277#define BCE_INSANE_LOAD (BCE_CP_LOAD | BCE_LEVEL_INSANE) 278 279#define BCE_WARN_SEND (BCE_CP_SEND | BCE_LEVEL_WARN) 280#define BCE_INFO_SEND (BCE_CP_SEND | BCE_LEVEL_INFO) 281#define BCE_VERBOSE_SEND (BCE_CP_SEND | BCE_LEVEL_VERBOSE) 282#define BCE_EXTREME_SEND (BCE_CP_SEND | BCE_LEVEL_EXTREME) 283#define BCE_INSANE_SEND (BCE_CP_SEND | BCE_LEVEL_INSANE) 284 285#define BCE_WARN_RECV (BCE_CP_RECV | BCE_LEVEL_WARN) 286#define BCE_INFO_RECV (BCE_CP_RECV | BCE_LEVEL_INFO) 287#define BCE_VERBOSE_RECV (BCE_CP_RECV | BCE_LEVEL_VERBOSE) 288#define BCE_EXTREME_RECV (BCE_CP_RECV | BCE_LEVEL_EXTREME) 289#define BCE_INSANE_RECV (BCE_CP_RECV | BCE_LEVEL_INSANE) 290 291#define BCE_WARN_INTR (BCE_CP_INTR | BCE_LEVEL_WARN) 292#define BCE_INFO_INTR (BCE_CP_INTR | BCE_LEVEL_INFO) 293#define BCE_VERBOSE_INTR (BCE_CP_INTR | BCE_LEVEL_VERBOSE) 294#define BCE_EXTREME_INTR (BCE_CP_INTR | BCE_LEVEL_EXTREME) 295#define BCE_INSANE_INTR (BCE_CP_INTR | BCE_LEVEL_INSANE) 296 297#define BCE_WARN_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_WARN) 298#define BCE_INFO_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_INFO) 299#define BCE_VERBOSE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_VERBOSE) 300#define BCE_EXTREME_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_EXTREME) 301#define BCE_INSANE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_INSANE) 302 303#define BCE_WARN_RESET (BCE_CP_RESET | BCE_LEVEL_WARN) 304#define BCE_INFO_RESET (BCE_CP_RESET | BCE_LEVEL_INFO) 305#define BCE_VERBOSE_RESET (BCE_CP_RESET | BCE_LEVEL_VERBOSE) 306#define BCE_EXTREME_RESET (BCE_CP_RESET | BCE_LEVEL_EXTREME) 307#define BCE_INSANE_RESET (BCE_CP_RESET | BCE_LEVEL_INSANE) 308 309#define BCE_WARN_PHY (BCE_CP_PHY | BCE_LEVEL_WARN) 310#define BCE_INFO_PHY (BCE_CP_PHY | BCE_LEVEL_INFO) 311#define BCE_VERBOSE_PHY (BCE_CP_PHY | BCE_LEVEL_VERBOSE) 312#define BCE_EXTREME_PHY (BCE_CP_PHY | BCE_LEVEL_EXTREME) 313#define BCE_INSANE_PHY (BCE_CP_PHY | BCE_LEVEL_INSANE) 314 315#define BCE_WARN_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_WARN) 316#define BCE_INFO_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_INFO) 317#define BCE_VERBOSE_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_VERBOSE) 318#define BCE_EXTREME_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_EXTREME) 319#define BCE_INSANE_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_INSANE) 320 321#define BCE_WARN_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_WARN) 322#define BCE_INFO_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_INFO) 323#define BCE_VERBOSE_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_VERBOSE) 324#define BCE_EXTREME_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_EXTREME) 325#define BCE_INSANE_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_INSANE) 326 327#define BCE_WARN_CTX (BCE_CP_CTX | BCE_LEVEL_WARN) 328#define BCE_INFO_CTX (BCE_CP_CTX | BCE_LEVEL_INFO) 329#define BCE_VERBOSE_CTX (BCE_CP_CTX | BCE_LEVEL_VERBOSE) 330#define BCE_EXTREME_CTX (BCE_CP_CTX | BCE_LEVEL_EXTREME) 331#define BCE_INSANE_CTX (BCE_CP_CTX | BCE_LEVEL_INSANE) 332 333#define BCE_WARN_REG (BCE_CP_REG | BCE_LEVEL_WARN) 334#define BCE_INFO_REG (BCE_CP_REG | BCE_LEVEL_INFO) 335#define BCE_VERBOSE_REG (BCE_CP_REG | BCE_LEVEL_VERBOSE) 336#define BCE_EXTREME_REG (BCE_CP_REG | BCE_LEVEL_EXTREME) 337#define BCE_INSANE_REG (BCE_CP_REG | BCE_LEVEL_INSANE) 338 339#define BCE_WARN_MISC (BCE_CP_MISC | BCE_LEVEL_WARN) 340#define BCE_INFO_MISC (BCE_CP_MISC | BCE_LEVEL_INFO) 341#define BCE_VERBOSE_MISC (BCE_CP_MISC | BCE_LEVEL_VERBOSE) 342#define BCE_EXTREME_MISC (BCE_CP_MISC | BCE_LEVEL_EXTREME) 343#define BCE_INSANE_MISC (BCE_CP_MISC | BCE_LEVEL_INSANE) 344 345#define BCE_WARN_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_WARN) 346#define BCE_INFO_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_INFO) 347#define BCE_VERBOSE_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_VERBOSE) 348#define BCE_EXTREME_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_EXTREME) 349#define BCE_INSANE_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_INSANE) 350 351#define BCE_FATAL (BCE_CP_ALL | BCE_LEVEL_FATAL) 352#define BCE_WARN (BCE_CP_ALL | BCE_LEVEL_WARN) 353#define BCE_INFO (BCE_CP_ALL | BCE_LEVEL_INFO) 354#define BCE_VERBOSE (BCE_CP_ALL | BCE_LEVEL_VERBOSE) 355#define BCE_EXTREME (BCE_CP_ALL | BCE_LEVEL_EXTREME) 356#define BCE_INSANE (BCE_CP_ALL | BCE_LEVEL_INSANE) 357 358#define BCE_CODE_PATH(cp) ((cp & BCE_CP_MASK) & bce_debug) 359#define BCE_MSG_LEVEL(lv) \ 360 ((lv & BCE_LEVEL_MASK) <= (bce_debug & BCE_LEVEL_MASK)) 361#define BCE_LOG_MSG(m) (BCE_CODE_PATH(m) && BCE_MSG_LEVEL(m)) 362 363#ifdef BCE_DEBUG 364 365/* Print a message based on the logging level and code path. */ 366#define DBPRINT(sc, level, format, args...) \ 367 if (BCE_LOG_MSG(level)) { \ 368 device_printf(sc->bce_dev, format, ## args); \ 369 } 370 371/* Runs a particular command when debugging is enabled. */ 372#define DBRUN(args...) \ 373 do { \ 374 args; \ 375 } while (0) 376 377/* Runs a particular command based on the logging level and code path. */ 378#define DBRUNMSG(msg, args...) \ 379 if (BCE_LOG_MSG(msg)) { \ 380 args; \ 381 } 382 383/* Runs a particular command based on the logging level. */ 384#define DBRUNLV(level, args...) \ 385 if (BCE_MSG_LEVEL(level)) { \ 386 args; \ 387 } 388 389/* Runs a particular command based on the code path. */ 390#define DBRUNCP(cp, args...) \ 391 if (BCE_CODE_PATH(cp)) { \ 392 args; \ 393 } 394 395/* Runs a particular command based on a condition. */ 396#define DBRUNIF(cond, args...) \ 397 if (cond) { \ 398 args; \ 399 } 400 401/* Announces function entry. */ 402#define DBENTER(cond) \ 403 DBPRINT(sc, (cond), "%s(enter)\n", __FUNCTION__) 404 405/* Announces function exit. */ 406#define DBEXIT(cond) \ 407 DBPRINT(sc, (cond), "%s(exit)\n", __FUNCTION__) 408 409/* Temporarily override the debug level. */ 410#define DBPUSH(cond) \ 411 u32 bce_debug_temp = bce_debug; \ 412 bce_debug |= cond; 413 414/* Restore the previously overriden debug level. */ 415#define DBPOP() \ 416 bce_debug = bce_debug_temp; 417 418/* Needed for random() function which is only used in debugging. */ 419#include <sys/random.h> 420 421/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */ 422#define DB_RANDOMFALSE(defects) (random() > defects) 423#define DB_OR_RANDOMFALSE(defects) || (random() > defects) 424#define DB_AND_RANDOMFALSE(defects) && (random() > defects) 425 426/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */ 427#define DB_RANDOMTRUE(defects) (random() < defects) 428#define DB_OR_RANDOMTRUE(defects) || (random() < defects) 429#define DB_AND_RANDOMTRUE(defects) && (random() < defects) 430 431#define DB_PRINT_PHY_REG(reg, val) \ 432switch(reg) { \ 433case 0x00: DBPRINT(sc, BCE_INSANE_PHY, \ 434 "%s(): phy = %d, reg = 0x%04X (BMCR ), val = 0x%b\n", \ 435 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 436 BCE_BMCR_PRINTFB); break; \ 437case 0x01: DBPRINT(sc, BCE_INSANE_PHY, \ 438 "%s(): phy = %d, reg = 0x%04X (BMSR ), val = 0x%b\n", \ 439 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 440 BCE_BMSR_PRINTFB); break; \ 441case 0x04: DBPRINT(sc, BCE_INSANE_PHY, \ 442 "%s(): phy = %d, reg = 0x%04X (ANAR ), val = 0x%b\n", \ 443 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 444 BCE_ANAR_PRINTFB); break; \ 445case 0x05: DBPRINT(sc, BCE_INSANE_PHY, \ 446 "%s(): phy = %d, reg = 0x%04X (ANLPAR ), val = 0x%b\n", \ 447 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 448 BCE_ANLPAR_PRINTFB); break; \ 449case 0x09: DBPRINT(sc, BCE_INSANE_PHY, \ 450 "%s(): phy = %d, reg = 0x%04X (1000CTL), val = 0x%b\n", \ 451 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 452 BCE_1000CTL_PRINTFB); break; \ 453case 0x0a: DBPRINT(sc, BCE_INSANE_PHY, \ 454 "%s(): phy = %d, reg = 0x%04X (1000STS), val = 0x%b\n", \ 455 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 456 BCE_1000STS_PRINTFB); break; \ 457case 0x0f: DBPRINT(sc, BCE_INSANE_PHY, \ 458 "%s(): phy = %d, reg = 0x%04X (EXTSTS ), val = 0x%b\n", \ 459 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 460 BCE_EXTSTS_PRINTFB); break; \ 461case 0x19: DBPRINT(sc, BCE_INSANE_PHY, \ 462 "%s(): phy = %d, reg = 0x%04X (AUXSTS ), val = 0x%b\n", \ 463 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \ 464 BCE_AUXSTS_PRINTFB); break; \ 465default: DBPRINT(sc, BCE_INSANE_PHY, \ 466 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", \ 467 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff); \ 468 } 469 470#else 471 472#define DBPRINT(level, format, args...) 473#define DBRUN(args...) 474#define DBRUNMSG(msg, args...) 475#define DBRUNLV(level, args...) 476#define DBRUNCP(cp, args...) 477#define DBRUNIF(cond, args...) 478#define DBENTER(cond) 479#define DBEXIT(cond) 480#define DBPUSH(cond) 481#define DBPOP() 482#define DB_RANDOMFALSE(defects) 483#define DB_OR_RANDOMFALSE(percent) 484#define DB_AND_RANDOMFALSE(percent) 485#define DB_RANDOMTRUE(defects) 486#define DB_OR_RANDOMTRUE(percent) 487#define DB_AND_RANDOMTRUE(percent) 488#define DB_PRINT_PHY_REG(reg, val) 489 490#endif /* BCE_DEBUG */ 491 492/****************************************************************************/ 493/* Device identification definitions. */ 494/****************************************************************************/ 495#define BRCM_VENDORID 0x14E4 496#define BRCM_DEVICEID_BCM5706 0x164A 497#define BRCM_DEVICEID_BCM5706S 0x16AA 498#define BRCM_DEVICEID_BCM5708 0x164C 499#define BRCM_DEVICEID_BCM5708S 0x16AC 500#define BRCM_DEVICEID_BCM5709 0x1639 501#define BRCM_DEVICEID_BCM5709S 0x163A 502#define BRCM_DEVICEID_BCM5716 0x163B 503 504#define HP_VENDORID 0x103C 505 506#define PCI_ANY_ID (u_int16_t) (~0U) 507 508/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 509 510#define BCE_CHIP_NUM(sc) (((sc)->bce_chipid) & 0xffff0000) 511#define BCE_CHIP_NUM_5706 0x57060000 512#define BCE_CHIP_NUM_5708 0x57080000 513#define BCE_CHIP_NUM_5709 0x57090000 514 515#define BCE_CHIP_REV(sc) (((sc)->bce_chipid) & 0x0000f000) 516#define BCE_CHIP_REV_Ax 0x00000000 517#define BCE_CHIP_REV_Bx 0x00001000 518#define BCE_CHIP_REV_Cx 0x00002000 519 520#define BCE_CHIP_METAL(sc) (((sc)->bce_chipid) & 0x00000ff0) 521#define BCE_CHIP_BOND(bp) (((sc)->bce_chipid) & 0x0000000f) 522 523#define BCE_CHIP_ID(sc) (((sc)->bce_chipid) & 0xfffffff0) 524#define BCE_CHIP_ID_5706_A0 0x57060000 525#define BCE_CHIP_ID_5706_A1 0x57060010 526#define BCE_CHIP_ID_5706_A2 0x57060020 527#define BCE_CHIP_ID_5706_A3 0x57060030 528#define BCE_CHIP_ID_5708_A0 0x57080000 529#define BCE_CHIP_ID_5708_B0 0x57081000 530#define BCE_CHIP_ID_5708_B1 0x57081010 531#define BCE_CHIP_ID_5708_B2 0x57081020 532#define BCE_CHIP_ID_5709_A0 0x57090000 533#define BCE_CHIP_ID_5709_A1 0x57090010 534#define BCE_CHIP_ID_5709_B0 0x57091000 535#define BCE_CHIP_ID_5709_B1 0x57091010 536#define BCE_CHIP_ID_5709_B2 0x57091020 537#define BCE_CHIP_ID_5709_C0 0x57092000 538 539#define BCE_CHIP_BOND_ID(sc) (((sc)->bce_chipid) & 0xf) 540 541/* A serdes chip will have the first bit of the bond id set. */ 542#define BCE_CHIP_BOND_ID_SERDES_BIT 0x01 543 544/* shorthand one */ 545#define BCE_ASICREV(x) ((x) >> 28) 546#define BCE_ASICREV_BCM5700 0x06 547 548/* chip revisions */ 549#define BCE_CHIPREV(x) ((x) >> 24) 550#define BCE_CHIPREV_5700_AX 0x70 551#define BCE_CHIPREV_5700_BX 0x71 552#define BCE_CHIPREV_5700_CX 0x72 553#define BCE_CHIPREV_5701_AX 0x00 554 555struct bce_type { 556 u_int16_t bce_vid; 557 u_int16_t bce_did; 558 u_int16_t bce_svid; 559 u_int16_t bce_sdid; 560 const char *bce_name; 561}; 562 563/****************************************************************************/ 564/* Byte order conversions. */ 565/****************************************************************************/ 566#define bce_htobe16(x) htobe16(x) 567#define bce_htobe32(x) htobe32(x) 568#define bce_htobe64(x) htobe64(x) 569#define bce_htole16(x) htole16(x) 570#define bce_htole32(x) htole32(x) 571#define bce_htole64(x) htole64(x) 572 573#define bce_be16toh(x) be16toh(x) 574#define bce_be32toh(x) be32toh(x) 575#define bce_be64toh(x) be64toh(x) 576#define bce_le16toh(x) le16toh(x) 577#define bce_le32toh(x) le32toh(x) 578#define bce_le64toh(x) le64toh(x) 579 580/****************************************************************************/ 581/* NVRAM Access */ 582/****************************************************************************/ 583 584/* Buffered flash (Atmel: AT45DB011B) specific information */ 585#define SEEPROM_PAGE_BITS 2 586#define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS) 587#define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1) 588#define SEEPROM_PAGE_SIZE 4 589#define SEEPROM_TOTAL_SIZE 65536 590 591#define BUFFERED_FLASH_PAGE_BITS 9 592#define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS) 593#define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1) 594#define BUFFERED_FLASH_PAGE_SIZE 264 595#define BUFFERED_FLASH_TOTAL_SIZE 0x21000 596 597#define SAIFUN_FLASH_PAGE_BITS 8 598#define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS) 599#define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1) 600#define SAIFUN_FLASH_PAGE_SIZE 256 601#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536 602 603#define ST_MICRO_FLASH_PAGE_BITS 8 604#define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS) 605#define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1) 606#define ST_MICRO_FLASH_PAGE_SIZE 256 607#define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536 608 609#define BCM5709_FLASH_PAGE_BITS 8 610#define BCM5709_FLASH_PHY_PAGE_SIZE (1 << BCM5709_FLASH_PAGE_BITS) 611#define BCM5709_FLASH_BYTE_ADDR_MASK (BCM5709_FLASH_PHY_PAGE_SIZE-1) 612#define BCM5709_FLASH_PAGE_SIZE 256 613 614#define NVRAM_TIMEOUT_COUNT 30000 615#define BCE_FLASHDESC_MAX 64 616 617#define FLASH_STRAP_MASK (BCE_NVM_CFG1_FLASH_MODE | \ 618 BCE_NVM_CFG1_BUFFER_MODE | BCE_NVM_CFG1_PROTECT_MODE | \ 619 BCE_NVM_CFG1_FLASH_SIZE) 620 621#define FLASH_BACKUP_STRAP_MASK (0xf << 26) 622 623struct flash_spec { 624 u32 strapping; 625 u32 config1; 626 u32 config2; 627 u32 config3; 628 u32 write1; 629#define BCE_NV_BUFFERED 0x00000001 630#define BCE_NV_TRANSLATE 0x00000002 631#define BCE_NV_WREN 0x00000004 632 u32 flags; 633 u32 page_bits; 634 u32 page_size; 635 u32 addr_mask; 636 u32 total_size; 637 const u8 *name; 638}; 639 640/****************************************************************************/ 641/* Shared Memory layout */ 642/* The BCE bootcode will initialize this data area with port configurtion */ 643/* information which can be accessed by the driver. */ 644/****************************************************************************/ 645 646/* 647 * This value (in milliseconds) determines the frequency of the driver 648 * issuing the PULSE message code. The firmware monitors this periodic 649 * pulse to determine when to switch to an OS-absent mode. 650 */ 651#define DRV_PULSE_PERIOD_MS 250 652 653/* 654 * This value (in milliseconds) determines how long the driver should 655 * wait for an acknowledgement from the firmware before timing out. Once 656 * the firmware has timed out, the driver will assume there is no firmware 657 * running and there won't be any firmware-driver synchronization during a 658 * driver reset. 659 */ 660#define FW_ACK_TIME_OUT_MS 1000 661 662#define BCE_DRV_RESET_SIGNATURE 0x00000000 663#define BCE_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */ 664 665#define BCE_DRV_MB 0x00000004 666#define BCE_DRV_MSG_CODE 0xff000000 667#define BCE_DRV_MSG_CODE_RESET 0x01000000 668#define BCE_DRV_MSG_CODE_UNLOAD 0x02000000 669#define BCE_DRV_MSG_CODE_SHUTDOWN 0x03000000 670#define BCE_DRV_MSG_CODE_SUSPEND_WOL 0x04000000 671#define BCE_DRV_MSG_CODE_FW_TIMEOUT 0x05000000 672#define BCE_DRV_MSG_CODE_PULSE 0x06000000 673#define BCE_DRV_MSG_CODE_DIAG 0x07000000 674#define BCE_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 675#define BCE_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000 676#define BCE_DRV_MSG_CODE_CMD_SET_LINK 0x10000000 677 678#define BCE_DRV_MSG_DATA 0x00ff0000 679#define BCE_DRV_MSG_DATA_WAIT0 0x00010000 680#define BCE_DRV_MSG_DATA_WAIT1 0x00020000 681#define BCE_DRV_MSG_DATA_WAIT2 0x00030000 682#define BCE_DRV_MSG_DATA_WAIT3 0x00040000 683 684#define BCE_DRV_MSG_SEQ 0x0000ffff 685 686#define BCE_FW_MB 0x00000008 687#define BCE_FW_MSG_ACK 0x0000ffff 688#define BCE_FW_MSG_STATUS_MASK 0x00ff0000 689#define BCE_FW_MSG_STATUS_OK 0x00000000 690#define BCE_FW_MSG_STATUS_INVALID_ARGS 0x00010000 691#define BCE_FW_MSG_STATUS_DRV_PRSNT 0x00020000 692#define BCE_FW_MSG_STATUS_FAILURE 0x00ff0000 693 694#define BCE_LINK_STATUS 0x0000000c 695#define BCE_LINK_STATUS_INIT_VALUE 0xffffffff 696#define BCE_LINK_STATUS_LINK_UP 0x1 697#define BCE_LINK_STATUS_LINK_DOWN 0x0 698#define BCE_LINK_STATUS_SPEED_MASK 0x1e 699#define BCE_LINK_STATUS_AN_INCOMPLETE (0<<1) 700#define BCE_LINK_STATUS_10HALF (1<<1) 701#define BCE_LINK_STATUS_10FULL (2<<1) 702#define BCE_LINK_STATUS_100HALF (3<<1) 703#define BCE_LINK_STATUS_100BASE_T4 (4<<1) 704#define BCE_LINK_STATUS_100FULL (5<<1) 705#define BCE_LINK_STATUS_1000HALF (6<<1) 706#define BCE_LINK_STATUS_1000FULL (7<<1) 707#define BCE_LINK_STATUS_2500HALF (8<<1) 708#define BCE_LINK_STATUS_2500FULL (9<<1) 709#define BCE_LINK_STATUS_AN_ENABLED (1<<5) 710#define BCE_LINK_STATUS_AN_COMPLETE (1<<6) 711#define BCE_LINK_STATUS_PARALLEL_DET (1<<7) 712#define BCE_LINK_STATUS_RESERVED (1<<8) 713#define BCE_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) 714#define BCE_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) 715#define BCE_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) 716#define BCE_LINK_STATUS_PARTNER_AD_100FULL (1<<12) 717#define BCE_LINK_STATUS_PARTNER_AD_100HALF (1<<13) 718#define BCE_LINK_STATUS_PARTNER_AD_10FULL (1<<14) 719#define BCE_LINK_STATUS_PARTNER_AD_10HALF (1<<15) 720#define BCE_LINK_STATUS_TX_FC_ENABLED (1<<16) 721#define BCE_LINK_STATUS_RX_FC_ENABLED (1<<17) 722#define BCE_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) 723#define BCE_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) 724#define BCE_LINK_STATUS_SERDES_LINK (1<<20) 725#define BCE_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) 726#define BCE_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) 727 728#define BCE_DRV_PULSE_MB 0x00000010 729#define BCE_DRV_PULSE_SEQ_MASK 0x00007fff 730 731#define BCE_MB_ARGS_0 0x00000014 732#define BCE_NETLINK_SPEED_10HALF (1<<0) 733#define BCE_NETLINK_SPEED_10FULL (1<<1) 734#define BCE_NETLINK_SPEED_100HALF (1<<2) 735#define BCE_NETLINK_SPEED_100FULL (1<<3) 736#define BCE_NETLINK_SPEED_1000HALF (1<<4) 737#define BCE_NETLINK_SPEED_1000FULL (1<<5) 738#define BCE_NETLINK_SPEED_2500HALF (1<<6) 739#define BCE_NETLINK_SPEED_2500FULL (1<<7) 740#define BCE_NETLINK_SPEED_10GHALF (1<<8) 741#define BCE_NETLINK_SPEED_10GFULL (1<<9) 742#define BCE_NETLINK_ANEG_ENB (1<<10) 743#define BCE_NETLINK_PHY_APP_REMOTE (1<<11) 744#define BCE_NETLINK_FC_PAUSE_SYM (1<<12) 745#define BCE_NETLINK_FC_PAUSE_ASYM (1<<13) 746#define BCE_NETLINK_ETH_AT_WIRESPEED (1<<14) 747#define BCE_NETLINK_PHY_RESET (1<<15) 748 749#define BCE_MB_ARGS_1 0x00000018 750 751/* Indicate to the firmware not to go into the 752 * OS absent when it is not getting driver pulse. 753 * This is used for debugging. */ 754#define BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000 755 756#define BCE_DEV_INFO_SIGNATURE 0x00000020 757#define BCE_DEV_INFO_SIGNATURE_MAGIC 0x44564900 758#define BCE_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00 759#define BCE_DEV_INFO_FEATURE_CFG_VALID 0x01 760#define BCE_DEV_INFO_SECONDARY_PORT 0x80 761#define BCE_DEV_INFO_DRV_ALWAYS_ALIVE 0x40 762 763#define BCE_SHARED_HW_CFG_PART_NUM 0x00000024 764 765#define BCE_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034 766#define BCE_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000 767#define BCE_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000 768#define BCE_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00 769#define BCE_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff 770 771#define BCE_SHARED_HW_CFG_POWER_CONSUMED 0x00000038 772#define BCE_SHARED_HW_CFG_CONFIG 0x0000003c 773#define BCE_SHARED_HW_CFG_DESIGN_NIC 0 774#define BCE_SHARED_HW_CFG_DESIGN_LOM 0x1 775#define BCE_SHARED_HW_CFG_PHY_COPPER 0 776#define BCE_SHARED_HW_CFG_PHY_FIBER 0x2 777#define BCE_SHARED_HW_CFG_PHY_2_5G 0x20 778#define BCE_SHARED_HW_CFG_PHY_BACKPLANE 0x40 779#define BCE_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 780#define BCE_SHARED_HW_CFG_LED_MODE_MASK 0x300 781#define BCE_SHARED_HW_CFG_LED_MODE_MAC 0 782#define BCE_SHARED_HW_CFG_LED_MODE_GPHY1 0x100 783#define BCE_SHARED_HW_CFG_LED_MODE_GPHY2 0x200 784 785#define BCE_SHARED_HW_CFG_CONFIG2 0x00000040 786#define BCE_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000 787 788#define BCE_DEV_INFO_BC_REV 0x0000004c 789 790#define BCE_PORT_HW_CFG_MAC_UPPER 0x00000050 791#define BCE_PORT_HW_CFG_UPPERMAC_MASK 0xffff 792 793#define BCE_PORT_HW_CFG_MAC_LOWER 0x00000054 794#define BCE_PORT_HW_CFG_CONFIG 0x00000058 795#define BCE_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff 796#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000 797#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000 798#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000 799#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000 800 801#define BCE_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068 802#define BCE_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c 803#define BCE_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070 804#define BCE_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074 805#define BCE_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078 806#define BCE_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c 807 808#define BCE_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4 809 810#define BCE_DEV_INFO_FORMAT_REV 0x000000c4 811#define BCE_DEV_INFO_FORMAT_REV_MASK 0xff000000 812#define BCE_DEV_INFO_FORMAT_REV_ID ('A' << 24) 813 814#define BCE_SHARED_FEATURE 0x000000c8 815#define BCE_SHARED_FEATURE_MASK 0xffffffff 816 817#define BCE_PORT_FEATURE 0x000000d8 818#define BCE_PORT2_FEATURE 0x00000014c 819#define BCE_PORT_FEATURE_WOL_ENABLED 0x01000000 820#define BCE_PORT_FEATURE_MBA_ENABLED 0x02000000 821#define BCE_PORT_FEATURE_ASF_ENABLED 0x04000000 822#define BCE_PORT_FEATURE_IMD_ENABLED 0x08000000 823#define BCE_PORT_FEATURE_BAR1_SIZE_MASK 0xf 824#define BCE_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0 825#define BCE_PORT_FEATURE_BAR1_SIZE_64K 0x1 826#define BCE_PORT_FEATURE_BAR1_SIZE_128K 0x2 827#define BCE_PORT_FEATURE_BAR1_SIZE_256K 0x3 828#define BCE_PORT_FEATURE_BAR1_SIZE_512K 0x4 829#define BCE_PORT_FEATURE_BAR1_SIZE_1M 0x5 830#define BCE_PORT_FEATURE_BAR1_SIZE_2M 0x6 831#define BCE_PORT_FEATURE_BAR1_SIZE_4M 0x7 832#define BCE_PORT_FEATURE_BAR1_SIZE_8M 0x8 833#define BCE_PORT_FEATURE_BAR1_SIZE_16M 0x9 834#define BCE_PORT_FEATURE_BAR1_SIZE_32M 0xa 835#define BCE_PORT_FEATURE_BAR1_SIZE_64M 0xb 836#define BCE_PORT_FEATURE_BAR1_SIZE_128M 0xc 837#define BCE_PORT_FEATURE_BAR1_SIZE_256M 0xd 838#define BCE_PORT_FEATURE_BAR1_SIZE_512M 0xe 839#define BCE_PORT_FEATURE_BAR1_SIZE_1G 0xf 840 841#define BCE_PORT_FEATURE_WOL 0xdc 842#define BCE_PORT2_FEATURE_WOL 0x150 843#define BCE_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4 844#define BCE_PORT_FEATURE_WOL_DEFAULT_MASK 0x30 845#define BCE_PORT_FEATURE_WOL_DEFAULT_DISABLE 0 846#define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10 847#define BCE_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20 848#define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30 849#define BCE_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf 850#define BCE_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0 851#define BCE_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1 852#define BCE_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2 853#define BCE_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3 854#define BCE_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4 855#define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5 856#define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6 857#define BCE_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40 858#define BCE_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400 859#define BCE_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800 860 861#define BCE_PORT_FEATURE_MBA 0xe0 862#define BCE_PORT2_FEATURE_MBA 0x154 863#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0 864#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3 865#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0 866#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1 867#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2 868#define BCE_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2 869#define BCE_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c 870#define BCE_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0 871#define BCE_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4 872#define BCE_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8 873#define BCE_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc 874#define BCE_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10 875#define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14 876#define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18 877#define BCE_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40 878#define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0 879#define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80 880#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8 881#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00 882#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0 883#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100 884#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200 885#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300 886#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400 887#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500 888#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600 889#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700 890#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800 891#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900 892#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00 893#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00 894#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00 895#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00 896#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00 897#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00 898#define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16 899#define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000 900#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20 901#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000 902#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0 903#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000 904#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000 905#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000 906 907#define BCE_PORT_FEATURE_IMD 0xe4 908#define BCE_PORT2_FEATURE_IMD 0x158 909#define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0 910#define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1 911 912#define BCE_PORT_FEATURE_VLAN 0xe8 913#define BCE_PORT2_FEATURE_VLAN 0x15c 914#define BCE_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff 915#define BCE_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000 916 917#define BCE_MFW_VER_PTR 0x00000014c 918 919#define BCE_BC_STATE_RESET_TYPE 0x000001c0 920#define BCE_BC_STATE_RESET_TYPE_SIG 0x00005254 921#define BCE_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff 922 923#define BCE_BC_STATE_RESET_TYPE_NONE \ 924 (BCE_BC_STATE_RESET_TYPE_SIG | 0x00010000) 925#define BCE_BC_STATE_RESET_TYPE_PCI \ 926 (BCE_BC_STATE_RESET_TYPE_SIG | 0x00020000) 927#define BCE_BC_STATE_RESET_TYPE_VAUX \ 928 (BCE_BC_STATE_RESET_TYPE_SIG | 0x00030000) 929#define BCE_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE 930#define BCE_BC_STATE_RESET_TYPE_DRV_RESET \ 931 (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_RESET) 932#define BCE_BC_STATE_RESET_TYPE_DRV_UNLOAD \ 933 (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_UNLOAD) 934#define BCE_BC_STATE_RESET_TYPE_DRV_SHUTDOWN \ 935 (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_SHUTDOWN) 936#define BCE_BC_STATE_RESET_TYPE_DRV_WOL \ 937 (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_WOL) 938#define BCE_BC_STATE_RESET_TYPE_DRV_DIAG \ 939 (BCE_BC_STATE_RESET_TYPE_SIG | DRV_MSG_CODE_DIAG) 940#define BCE_BC_STATE_RESET_TYPE_VALUE(msg) \ 941 (BCE_BC_STATE_RESET_TYPE_SIG | (msg)) 942 943#define BCE_BC_RESET_TYPE 0x000001c0 944 945#define BCE_BC_STATE 0x000001c4 946#define BCE_BC_STATE_ERR_MASK 0x0000ff00 947#define BCE_BC_STATE_SIGN 0x42530000 948#define BCE_BC_STATE_SIGN_MASK 0xffff0000 949#define BCE_BC_STATE_BC1_START (BCE_BC_STATE_SIGN | 0x1) 950#define BCE_BC_STATE_GET_NVM_CFG1 (BCE_BC_STATE_SIGN | 0x2) 951#define BCE_BC_STATE_PROG_BAR (BCE_BC_STATE_SIGN | 0x3) 952#define BCE_BC_STATE_INIT_VID (BCE_BC_STATE_SIGN | 0x4) 953#define BCE_BC_STATE_GET_NVM_CFG2 (BCE_BC_STATE_SIGN | 0x5) 954#define BCE_BC_STATE_APPLY_WKARND (BCE_BC_STATE_SIGN | 0x6) 955#define BCE_BC_STATE_LOAD_BC2 (BCE_BC_STATE_SIGN | 0x7) 956#define BCE_BC_STATE_GOING_BC2 (BCE_BC_STATE_SIGN | 0x8) 957#define BCE_BC_STATE_GOING_DIAG (BCE_BC_STATE_SIGN | 0x9) 958#define BCE_BC_STATE_RT_FINAL_INIT (BCE_BC_STATE_SIGN | 0x81) 959#define BCE_BC_STATE_RT_WKARND (BCE_BC_STATE_SIGN | 0x82) 960#define BCE_BC_STATE_RT_DRV_PULSE (BCE_BC_STATE_SIGN | 0x83) 961#define BCE_BC_STATE_RT_FIOEVTS (BCE_BC_STATE_SIGN | 0x84) 962#define BCE_BC_STATE_RT_DRV_CMD (BCE_BC_STATE_SIGN | 0x85) 963#define BCE_BC_STATE_RT_LOW_POWER (BCE_BC_STATE_SIGN | 0x86) 964#define BCE_BC_STATE_RT_SET_WOL (BCE_BC_STATE_SIGN | 0x87) 965#define BCE_BC_STATE_RT_OTHER_FW (BCE_BC_STATE_SIGN | 0x88) 966#define BCE_BC_STATE_RT_GOING_D3 (BCE_BC_STATE_SIGN | 0x89) 967#define BCE_BC_STATE_ERR_BAD_VERSION (BCE_BC_STATE_SIGN | 0x0100) 968#define BCE_BC_STATE_ERR_BAD_BC2_CRC (BCE_BC_STATE_SIGN | 0x0200) 969#define BCE_BC_STATE_ERR_BC1_LOOP (BCE_BC_STATE_SIGN | 0x0300) 970#define BCE_BC_STATE_ERR_UNKNOWN_CMD (BCE_BC_STATE_SIGN | 0x0400) 971#define BCE_BC_STATE_ERR_DRV_DEAD (BCE_BC_STATE_SIGN | 0x0500) 972#define BCE_BC_STATE_ERR_NO_RXP (BCE_BC_STATE_SIGN | 0x0600) 973#define BCE_BC_STATE_ERR_TOO_MANY_RBUF (BCE_BC_STATE_SIGN | 0x0700) 974 975#define BCE_BC_STATE_CONDITION 0x000001c8 976#define BCE_CONDITION_INIT_POR 0x00000001 977#define BCE_CONDITION_INIT_VAUX_AVAIL 0x00000002 978#define BCE_CONDITION_INIT_PCI_AVAIL 0x00000004 979#define BCE_CONDITION_INIT_PCI_RESET 0x00000008 980#define BCE_CONDITION_INIT_HD_RESET 0x00000010 /* 5709/16 only */ 981#define BCE_CONDITION_DRV_PRESENT 0x00000100 982#define BCE_CONDITION_LOW_POWER_LINK 0x00000200 983#define BCE_CONDITION_CORE_RST_OCCURRED 0x00000400 /* 5709/16 only */ 984#define BCE_CONDITION_UNUSED 0x00000800 985#define BCE_CONDITION_BUSY_EXPROM 0x00001000 /* 5706/08 only */ 986 987#define BCE_CONDITION_MFW_RUN_UNKNOWN 0x00000000 988#define BCE_CONDITION_MFW_RUN_IPMI 0x00002000 989#define BCE_CONDITION_MFW_RUN_UMP 0x00004000 990#define BCE_CONDITION_MFW_RUN_NCSI 0x00006000 991#define BCE_CONDITION_MFW_RUN_NONE 0x0000e000 992#define BCE_CONDITION_MFW_RUN_MASK 0x0000e000 993 994/* 5709/16 only */ 995#define BCE_CONDITION_PM_STATE_MASK 0x00030000 996#define BCE_CONDITION_PM_STATE_FULL 0x00030000 997#define BCE_CONDITION_PM_STATE_PREP 0x00020000 998#define BCE_CONDITION_PM_STATE_UNPREP 0x00010000 999#define BCE_CONDITION_PM_RESERVED 0x00000000 1000 1001/* 5709/16 only */ 1002#define BCE_CONDITION_RXMODE_KEEP_VLAN 0x00040000 1003#define BCE_CONDITION_DRV_WOL_ENABLED 0x00080000 1004#define BCE_CONDITION_PORT_DISABLED 0x00100000 1005#define BCE_CONDITION_DRV_MAYBE_OUT 0x00200000 1006#define BCE_CONDITION_DPFW_DEAD 0x00400000 1007 1008#define BCE_BC_STATE_DEBUG_CMD 0x000001dc 1009#define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 1010#define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 1011#define BCE_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff 1012#define BCE_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff 1013 1014#define BCE_FW_EVT_CODE_MB 0x00000354 1015#define BCE_FW_EVT_CODE_SW_TIMER_EXPIRE_EVENT 0x00000000 1016#define BCE_FW_EVT_CODE_LINK_EVENT 0x00000001 1017 1018#define BCE_DRV_ACK_CAP_MB 0x00000364 1019#define BCE_DRV_ACK_CAP_SIGNATURE_MAGIC 0x35450000 1020 1021#define BCE_FW_CAP_MB 0x00000368 1022#define BCE_FW_CAP_SIGNATURE_MAGIC 0xaa550000 1023#define BCE_FW_ACK_SIGNATURE_MAGIC 0x52500000 1024#define BCE_FW_CAP_SIGNATURE_MAGIC_MASK 0xffff0000 1025#define BCE_FW_CAP_REMOTE_PHY_CAP 0x00000001 1026#define BCE_FW_CAP_REMOTE_PHY_PRESENT 0x00000002 1027#define BCE_FW_CAP_MFW_KEEP_VLAN 0x00000008 1028#define BCE_FW_CAP_BC_KEEP_VLAN 0x00000010 1029 1030#define BCE_RPHY_SERDES_LINK 0x00000374 1031 1032#define BCE_RPHY_COPPER_LINK 0x00000378 1033 1034#define HOST_VIEW_SHMEM_BASE 0x167c00 1035 1036/* 1037 * PCI registers defined in the PCI 2.2 spec. 1038 */ 1039#define BCE_PCI_PCIX_CMD 0x42 1040 1041/****************************************************************************/ 1042/* Convenience definitions. */ 1043/****************************************************************************/ 1044#define BCE_PRINTF(fmt, args...) \ 1045 device_printf(sc->bce_dev, fmt, ##args) 1046 1047#define BCE_LOCK_INIT(_sc, _name) \ 1048 mtx_init(&(_sc)->bce_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 1049#define BCE_LOCK(_sc) mtx_lock(&(_sc)->bce_mtx) 1050#define BCE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bce_mtx, MA_OWNED) 1051#define BCE_UNLOCK(_sc) mtx_unlock(&(_sc)->bce_mtx) 1052#define BCE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bce_mtx) 1053 1054#ifdef BCE_DEBUG 1055#define REG_WR(sc, offset, val) bce_reg_wr(sc, offset, val) 1056#define REG_WR16(sc, offset, val) bce_reg_wr16(sc, offset, val) 1057#define REG_RD(sc, offset) bce_reg_rd(sc, offset) 1058#else 1059#define REG_WR(sc, offset, val) \ 1060 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val) 1061#define REG_WR16(sc, offset, val) \ 1062 bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val) 1063#define REG_RD(sc, offset) \ 1064 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset) 1065#endif 1066 1067#define REG_RD_IND(sc, offset) bce_reg_rd_ind(sc, offset) 1068#define REG_WR_IND(sc, offset, val) bce_reg_wr_ind(sc, offset, val) 1069#define CTX_WR(sc, cid_addr, offset, val)bce_ctx_wr(sc, cid_addr, offset, val) 1070#define CTX_RD(sc, cid_addr, offset) bce_ctx_rd(sc, cid_addr, offset) 1071 1072#define BCE_SETBIT(sc, reg, x) \ 1073 REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) 1074#define BCE_CLRBIT(sc, reg, x) \ 1075 REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x))) 1076#define PCI_SETBIT(dev, reg, x, s) \ 1077 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 1078#define PCI_CLRBIT(dev, reg, x, s) \ 1079 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 1080 1081#define BCE_STATS(x) (u_long) stats->stat_ ## x ## _lo 1082 1083#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 1084#define BCE_ADDR_LO(y) ((u64) (y) & 0xFFFFFFFF) 1085#define BCE_ADDR_HI(y) ((u64) (y) >> 32) 1086#else 1087#define BCE_ADDR_LO(y) ((u32)y) 1088#define BCE_ADDR_HI(y) (0) 1089#endif 1090 1091/****************************************************************************/ 1092/* Do not modify any of the following data structures, they are generated */ 1093/* from RTL code. */ 1094/* */ 1095/* Begin machine generated definitions. */ 1096/****************************************************************************/ 1097 1098/* 1099 * tx_bd definition 1100 */ 1101struct tx_bd { 1102 u32 tx_bd_haddr_hi; 1103 u32 tx_bd_haddr_lo; 1104 u32 tx_bd_mss_nbytes; 1105 u16 tx_bd_flags; 1106#define TX_BD_FLAGS_CONN_FAULT (1<<0) 1107#define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) 1108#define TX_BD_FLAGS_IP_CKSUM (1<<2) 1109#define TX_BD_FLAGS_VLAN_TAG (1<<3) 1110#define TX_BD_FLAGS_COAL_NOW (1<<4) 1111#define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) 1112#define TX_BD_FLAGS_END (1<<6) 1113#define TX_BD_FLAGS_START (1<<7) 1114#define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) 1115#define TX_BD_FLAGS_SW_FLAGS (1<<13) 1116#define TX_BD_FLAGS_SW_SNAP (1<<14) 1117#define TX_BD_FLAGS_SW_LSO (1<<15) 1118 u16 tx_bd_vlan_tag; 1119}; 1120 1121/* 1122 * rx_bd definition 1123 */ 1124struct rx_bd { 1125 u32 rx_bd_haddr_hi; 1126 u32 rx_bd_haddr_lo; 1127 u32 rx_bd_len; 1128 u32 rx_bd_flags; 1129#define RX_BD_FLAGS_NOPUSH (1<<0) 1130#define RX_BD_FLAGS_DUMMY (1<<1) 1131#define RX_BD_FLAGS_END (1<<2) 1132#define RX_BD_FLAGS_START (1<<3) 1133}; 1134 1135/* 1136 * status_block definition 1137 */ 1138struct status_block { 1139 u32 status_attn_bits; 1140 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0) 1141 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1) 1142 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2) 1143 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3) 1144 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4) 1145 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5) 1146 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6) 1147 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7) 1148 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8) 1149 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9) 1150 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10) 1151 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11) 1152 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12) 1153 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13) 1154 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14) 1155 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15) 1156 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16) 1157 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17) 1158 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18) 1159 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19) 1160 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20) 1161 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21) 1162 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22) 1163 #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23) 1164 #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24) 1165 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) 1166 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) 1167 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) 1168 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) 1169 1170 u32 status_attn_bits_ack; 1171#if defined(__BIG_ENDIAN) 1172 u16 status_tx_quick_consumer_index0; 1173 u16 status_tx_quick_consumer_index1; 1174 u16 status_tx_quick_consumer_index2; 1175 u16 status_tx_quick_consumer_index3; 1176 u16 status_rx_quick_consumer_index0; 1177 u16 status_rx_quick_consumer_index1; 1178 u16 status_rx_quick_consumer_index2; 1179 u16 status_rx_quick_consumer_index3; 1180 u16 status_rx_quick_consumer_index4; 1181 u16 status_rx_quick_consumer_index5; 1182 u16 status_rx_quick_consumer_index6; 1183 u16 status_rx_quick_consumer_index7; 1184 u16 status_rx_quick_consumer_index8; 1185 u16 status_rx_quick_consumer_index9; 1186 u16 status_rx_quick_consumer_index10; 1187 u16 status_rx_quick_consumer_index11; 1188 u16 status_rx_quick_consumer_index12; 1189 u16 status_rx_quick_consumer_index13; 1190 u16 status_rx_quick_consumer_index14; 1191 u16 status_rx_quick_consumer_index15; 1192 u16 status_completion_producer_index; 1193 u16 status_cmd_consumer_index; 1194 u16 status_idx; 1195 u16 status_unused; 1196#elif defined(__LITTLE_ENDIAN) 1197 u16 status_tx_quick_consumer_index1; 1198 u16 status_tx_quick_consumer_index0; 1199 u16 status_tx_quick_consumer_index3; 1200 u16 status_tx_quick_consumer_index2; 1201 u16 status_rx_quick_consumer_index1; 1202 u16 status_rx_quick_consumer_index0; 1203 u16 status_rx_quick_consumer_index3; 1204 u16 status_rx_quick_consumer_index2; 1205 u16 status_rx_quick_consumer_index5; 1206 u16 status_rx_quick_consumer_index4; 1207 u16 status_rx_quick_consumer_index7; 1208 u16 status_rx_quick_consumer_index6; 1209 u16 status_rx_quick_consumer_index9; 1210 u16 status_rx_quick_consumer_index8; 1211 u16 status_rx_quick_consumer_index11; 1212 u16 status_rx_quick_consumer_index10; 1213 u16 status_rx_quick_consumer_index13; 1214 u16 status_rx_quick_consumer_index12; 1215 u16 status_rx_quick_consumer_index15; 1216 u16 status_rx_quick_consumer_index14; 1217 u16 status_cmd_consumer_index; 1218 u16 status_completion_producer_index; 1219 u16 status_unused; 1220 u16 status_idx; 1221#endif 1222}; 1223 1224/* 1225 * statistics_block definition 1226 */ 1227struct statistics_block { 1228 u32 stat_IfHCInOctets_hi; 1229 u32 stat_IfHCInOctets_lo; 1230 u32 stat_IfHCInBadOctets_hi; 1231 u32 stat_IfHCInBadOctets_lo; 1232 u32 stat_IfHCOutOctets_hi; 1233 u32 stat_IfHCOutOctets_lo; 1234 u32 stat_IfHCOutBadOctets_hi; 1235 u32 stat_IfHCOutBadOctets_lo; 1236 u32 stat_IfHCInUcastPkts_hi; 1237 u32 stat_IfHCInUcastPkts_lo; 1238 u32 stat_IfHCInMulticastPkts_hi; 1239 u32 stat_IfHCInMulticastPkts_lo; 1240 u32 stat_IfHCInBroadcastPkts_hi; 1241 u32 stat_IfHCInBroadcastPkts_lo; 1242 u32 stat_IfHCOutUcastPkts_hi; 1243 u32 stat_IfHCOutUcastPkts_lo; 1244 u32 stat_IfHCOutMulticastPkts_hi; 1245 u32 stat_IfHCOutMulticastPkts_lo; 1246 u32 stat_IfHCOutBroadcastPkts_hi; 1247 u32 stat_IfHCOutBroadcastPkts_lo; 1248 u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 1249 u32 stat_Dot3StatsCarrierSenseErrors; 1250 u32 stat_Dot3StatsFCSErrors; 1251 u32 stat_Dot3StatsAlignmentErrors; 1252 u32 stat_Dot3StatsSingleCollisionFrames; 1253 u32 stat_Dot3StatsMultipleCollisionFrames; 1254 u32 stat_Dot3StatsDeferredTransmissions; 1255 u32 stat_Dot3StatsExcessiveCollisions; 1256 u32 stat_Dot3StatsLateCollisions; 1257 u32 stat_EtherStatsCollisions; 1258 u32 stat_EtherStatsFragments; 1259 u32 stat_EtherStatsJabbers; 1260 u32 stat_EtherStatsUndersizePkts; 1261 u32 stat_EtherStatsOversizePkts; 1262 u32 stat_EtherStatsPktsRx64Octets; 1263 u32 stat_EtherStatsPktsRx65Octetsto127Octets; 1264 u32 stat_EtherStatsPktsRx128Octetsto255Octets; 1265 u32 stat_EtherStatsPktsRx256Octetsto511Octets; 1266 u32 stat_EtherStatsPktsRx512Octetsto1023Octets; 1267 u32 stat_EtherStatsPktsRx1024Octetsto1522Octets; 1268 u32 stat_EtherStatsPktsRx1523Octetsto9022Octets; 1269 u32 stat_EtherStatsPktsTx64Octets; 1270 u32 stat_EtherStatsPktsTx65Octetsto127Octets; 1271 u32 stat_EtherStatsPktsTx128Octetsto255Octets; 1272 u32 stat_EtherStatsPktsTx256Octetsto511Octets; 1273 u32 stat_EtherStatsPktsTx512Octetsto1023Octets; 1274 u32 stat_EtherStatsPktsTx1024Octetsto1522Octets; 1275 u32 stat_EtherStatsPktsTx1523Octetsto9022Octets; 1276 u32 stat_XonPauseFramesReceived; 1277 u32 stat_XoffPauseFramesReceived; 1278 u32 stat_OutXonSent; 1279 u32 stat_OutXoffSent; 1280 u32 stat_FlowControlDone; 1281 u32 stat_MacControlFramesReceived; 1282 u32 stat_XoffStateEntered; 1283 u32 stat_IfInFramesL2FilterDiscards; 1284 u32 stat_IfInRuleCheckerDiscards; 1285 u32 stat_IfInFTQDiscards; 1286 u32 stat_IfInMBUFDiscards; 1287 u32 stat_IfInRuleCheckerP4Hit; 1288 u32 stat_CatchupInRuleCheckerDiscards; 1289 u32 stat_CatchupInFTQDiscards; 1290 u32 stat_CatchupInMBUFDiscards; 1291 u32 stat_CatchupInRuleCheckerP4Hit; 1292 u32 stat_GenStat00; 1293 u32 stat_GenStat01; 1294 u32 stat_GenStat02; 1295 u32 stat_GenStat03; 1296 u32 stat_GenStat04; 1297 u32 stat_GenStat05; 1298 u32 stat_GenStat06; 1299 u32 stat_GenStat07; 1300 u32 stat_GenStat08; 1301 u32 stat_GenStat09; 1302 u32 stat_GenStat10; 1303 u32 stat_GenStat11; 1304 u32 stat_GenStat12; 1305 u32 stat_GenStat13; 1306 u32 stat_GenStat14; 1307 u32 stat_GenStat15; 1308}; 1309 1310/* 1311 * l2_fhdr definition 1312 */ 1313struct l2_fhdr { 1314 u32 l2_fhdr_status; 1315 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) 1316 #define L2_FHDR_STATUS_RULE_P2 (1<<3) 1317 #define L2_FHDR_STATUS_RULE_P3 (1<<4) 1318 #define L2_FHDR_STATUS_RULE_P4 (1<<5) 1319 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) 1320 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) 1321 #define L2_FHDR_STATUS_RSS_HASH (1<<8) 1322 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) 1323 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) 1324 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) 1325 1326 #define L2_FHDR_STATUS_SPLIT (1<<16) 1327 #define L2_FHDR_ERRORS_BAD_CRC (1<<17) 1328 #define L2_FHDR_ERRORS_PHY_DECODE (1<<18) 1329 #define L2_FHDR_ERRORS_ALIGNMENT (1<<19) 1330 #define L2_FHDR_ERRORS_TOO_SHORT (1<<20) 1331 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21) 1332 #define L2_FHDR_ERRORS_IPV4_BAD_LEN (1<<22) 1333 #define L2_FHDR_ERRORS_TCP_XSUM (1<<28) 1334 #define L2_FHDR_ERRORS_UDP_XSUM (1<<31) 1335 1336 u32 l2_fhdr_hash; 1337#if defined(__BIG_ENDIAN) 1338 u16 l2_fhdr_pkt_len; 1339 u16 l2_fhdr_vlan_tag; 1340 u16 l2_fhdr_ip_xsum; 1341 u16 l2_fhdr_tcp_udp_xsum; 1342#elif defined(__LITTLE_ENDIAN) 1343 u16 l2_fhdr_vlan_tag; 1344 u16 l2_fhdr_pkt_len; 1345 u16 l2_fhdr_tcp_udp_xsum; 1346 u16 l2_fhdr_ip_xsum; 1347#endif 1348}; 1349 1350#define BCE_L2FHDR_PRINTFB \ 1351 "\20" \ 1352 "\40UDP_XSUM_ERR" \ 1353 "\37b30" \ 1354 "\36b29" \ 1355 "\35TCP_XSUM_ERR" \ 1356 "\34b27" \ 1357 "\33b26" \ 1358 "\32b25" \ 1359 "\31b24" \ 1360 "\30b23" \ 1361 "\27IPv4_BAL_LEN" \ 1362 "\26GIANT_ERR" \ 1363 "\25SHORT_ERR" \ 1364 "\24ALIGN_ERR" \ 1365 "\23PHY_ERR" \ 1366 "\22CRC_ERR" \ 1367 "\21SPLIT" \ 1368 "\20UDP" \ 1369 "\17TCP" \ 1370 "\16IP" \ 1371 "\15SORT_b3" \ 1372 "\14SORT_b2" \ 1373 "\13SORT_b1" \ 1374 "\12SORT_b0" \ 1375 "\11RSS" \ 1376 "\10SNAP" \ 1377 "\07VLAN" \ 1378 "\06P4" \ 1379 "\05P3" \ 1380 "\04P2" \ 1381 "\03RULE_b2" \ 1382 "\02RULE_b1" \ 1383 "\01RULE_b0" 1384 1385/* 1386 * l2_tx_context definition (5706 and 5708) 1387 */ 1388#define BCE_L2CTX_TX_TYPE 0x00000000 1389#define BCE_L2CTX_TX_TYPE_SIZE_L2 ((0xc0/0x20)<<16) 1390#define BCE_L2CTX_TX_TYPE_TYPE (0xf<<28) 1391#define BCE_L2CTX_TX_TYPE_TYPE_EMPTY (0<<28) 1392#define BCE_L2CTX_TX_TYPE_TYPE_L2 (1<<28) 1393 1394#define BCE_L2CTX_TX_HOST_BIDX 0x00000088 1395#define BCE_L2CTX_TX_EST_NBD 0x00000088 1396#define BCE_L2CTX_TX_CMD_TYPE 0x00000088 1397#define BCE_L2CTX_TX_CMD_TYPE_TYPE (0xf<<24) 1398#define BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 (0<<24) 1399#define BCE_L2CTX_TX_CMD_TYPE_TYPE_TCP (1<<24) 1400 1401#define BCE_L2CTX_TX_HOST_BSEQ 0x00000090 1402#define BCE_L2CTX_TX_TSCH_BSEQ 0x00000094 1403#define BCE_L2CTX_TX_TBDR_BSEQ 0x00000098 1404#define BCE_L2CTX_TX_TBDR_BOFF 0x0000009c 1405#define BCE_L2CTX_TX_TBDR_BIDX 0x0000009c 1406#define BCE_L2CTX_TX_TBDR_BHADDR_HI 0x000000a0 1407#define BCE_L2CTX_TX_TBDR_BHADDR_LO 0x000000a4 1408#define BCE_L2CTX_TX_TXP_BOFF 0x000000a8 1409#define BCE_L2CTX_TX_TXP_BIDX 0x000000a8 1410#define BCE_L2CTX_TX_TXP_BSEQ 0x000000ac 1411 1412/* 1413 * l2_tx_context definition (5709 and 5716) 1414 */ 1415#define BCE_L2CTX_TX_TYPE_XI 0x00000080 1416#define BCE_L2CTX_TX_TYPE_SIZE_L2_XI ((0xc0/0x20)<<16) 1417#define BCE_L2CTX_TX_TYPE_TYPE_XI (0xf<<28) 1418#define BCE_L2CTX_TX_TYPE_TYPE_EMPTY_XI (0<<28) 1419#define BCE_L2CTX_TX_TYPE_TYPE_L2_XI (1<<28) 1420 1421#define BCE_L2CTX_TX_CMD_TYPE_XI 0x00000240 1422#define BCE_L2CTX_TX_CMD_TYPE_TYPE_XI (0xf<<24) 1423#define BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI (0<<24) 1424#define BCE_L2CTX_TX_CMD_TYPE_TYPE_TCP_XI (1<<24) 1425 1426#define BCE_L2CTX_TX_HOST_BIDX_XI 0x00000240 1427#define BCE_L2CTX_TX_HOST_BSEQ_XI 0x00000248 1428#define BCE_L2CTX_TX_TBDR_BHADDR_HI_XI 0x00000258 1429#define BCE_L2CTX_TX_TBDR_BHADDR_LO_XI 0x0000025c 1430 1431/* 1432 * l2_rx_context definition (5706, 5708, 5709, and 5716) 1433 */ 1434#define BCE_L2CTX_RX_WATER_MARK 0x00000000 1435#define BCE_L2CTX_RX_LO_WATER_MARK_SHIFT 0 1436#define BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT 32 1437#define BCE_L2CTX_RX_LO_WATER_MARK_SCALE 4 1438#define BCE_L2CTX_RX_LO_WATER_MARK_DIS 0 1439#define BCE_L2CTX_RX_HI_WATER_MARK_SHIFT 4 1440#define BCE_L2CTX_RX_HI_WATER_MARK_SCALE 16 1441#define BCE_L2CTX_RX_WATER_MARKS_MSK 0x000000ff 1442 1443#define BCE_L2CTX_RX_BD_PRE_READ 0x00000000 1444#define BCE_L2CTX_RX_BD_PRE_READ_SHIFT 8 1445 1446#define BCE_L2CTX_RX_CTX_SIZE 0x00000000 1447#define BCE_L2CTX_RX_CTX_SIZE_SHIFT 16 1448#define BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 \ 1449 ((0x20/20)<<BCE_L2CTX_RX_CTX_SIZE_SHIFT) 1450 1451#define BCE_L2CTX_RX_CTX_TYPE 0x00000000 1452#define BCE_L2CTX_RX_CTX_TYPE_SHIFT 24 1453 1454#define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) 1455#define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) 1456#define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28) 1457 1458#define BCE_L2CTX_RX_HOST_BDIDX 0x00000004 1459#define BCE_L2CTX_RX_HOST_BSEQ 0x00000008 1460#define BCE_L2CTX_RX_NX_BSEQ 0x0000000c 1461#define BCE_L2CTX_RX_NX_BDHADDR_HI 0x00000010 1462#define BCE_L2CTX_RX_NX_BDHADDR_LO 0x00000014 1463#define BCE_L2CTX_RX_NX_BDIDX 0x00000018 1464 1465#define BCE_L2CTX_RX_HOST_PG_BDIDX 0x00000044 1466#define BCE_L2CTX_RX_PG_BUF_SIZE 0x00000048 1467#define BCE_L2CTX_RX_RBDC_KEY 0x0000004c 1468#define BCE_L2CTX_RX_RBDC_JUMBO_KEY 0x3ffe 1469#define BCE_L2CTX_RX_NX_PG_BDHADDR_HI 0x00000050 1470#define BCE_L2CTX_RX_NX_PG_BDHADDR_LO 0x00000054 1471#define BCE_L2CTX_RX_NX_PG_BDIDX 0x00000058 1472 1473/* 1474 * l2_mq definitions (5706, 5708, 5709, and 5716) 1475 */ 1476 1477#define BCE_L2MQ_RX_HOST_BDIDX 0x00000004 1478#define BCE_L2MQ_RX_HOST_BSEQ 0x00000008 1479#define BCE_L2MQ_RX_HOST_PG_BDIDX 0x00000044 1480 1481#define BCE_L2MQ_TX_HOST_BIDX 0x00000088 1482#define BCE_L2MQ_TX_HOST_BSEQ 0x00000090 1483 1484/* 1485 * pci_config_l definition 1486 * offset: 0000 1487 */ 1488#define BCE_PCICFG_MISC_CONFIG 0x00000068 1489#define BCE_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) 1490#define BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) 1491#define BCE_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5) 1492#define BCE_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6) 1493#define BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7) 1494#define BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8) 1495#define BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9) 1496#define BCE_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16) 1497#define BCE_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24) 1498#define BCE_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28) 1499#define BCE_PCICFG_MISC_CONFIG_ASIC_REV (0xffffL<<16) 1500 1501#define BCE_PCICFG_MISC_STATUS 0x0000006c 1502#define BCE_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0) 1503#define BCE_PCICFG_MISC_STATUS_32BIT_DET (1L<<1) 1504#define BCE_PCICFG_MISC_STATUS_M66EN (1L<<2) 1505#define BCE_PCICFG_MISC_STATUS_PCIX_DET (1L<<3) 1506#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4) 1507#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4) 1508#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4) 1509#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4) 1510#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4) 1511 1512#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070 1513#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1514#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1515#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1516#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1517#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1518#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1519#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1520#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1521#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1522#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1523#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1524#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1525#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1526#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1527#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1528#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1529#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1530#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 1531#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1532#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1533#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1534#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1535#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1536#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1537#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1538#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 1539#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 1540#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 1541#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 1542 1543#define BCE_PCICFG_REG_WINDOW_ADDRESS 0x00000078 1544#define BCE_PCICFG_REG_WINDOW 0x00000080 1545#define BCE_PCICFG_INT_ACK_CMD 0x00000084 1546#define BCE_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0) 1547#define BCE_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16) 1548#define BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17) 1549#define BCE_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18) 1550 1551#define BCE_PCICFG_STATUS_BIT_SET_CMD 0x00000088 1552#define BCE_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c 1553#define BCE_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090 1554#define BCE_PCICFG_MAILBOX_QUEUE_DATA 0x00000094 1555 1556/* 1557 * pci_reg definition 1558 * offset: 0x400 1559 */ 1560#define BCE_PCI_GRC_WINDOW_ADDR 0x00000400 1561#define BCE_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8) 1562 1563#define BCE_PCI_CONFIG_1 0x00000404 1564#define BCE_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8) 1565#define BCE_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8) 1566#define BCE_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8) 1567#define BCE_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8) 1568#define BCE_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8) 1569#define BCE_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8) 1570#define BCE_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8) 1571#define BCE_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8) 1572#define BCE_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8) 1573#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11) 1574#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11) 1575#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11) 1576#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11) 1577#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11) 1578#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11) 1579#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11) 1580#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11) 1581#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11) 1582 1583#define BCE_PCI_CONFIG_2 0x00000408 1584#define BCE_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 1585#define BCE_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 1586#define BCE_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 1587#define BCE_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 1588#define BCE_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 1589#define BCE_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 1590#define BCE_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 1591#define BCE_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 1592#define BCE_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 1593#define BCE_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 1594#define BCE_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 1595#define BCE_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 1596#define BCE_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 1597#define BCE_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 1598#define BCE_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 1599#define BCE_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 1600#define BCE_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 1601#define BCE_PCI_CONFIG_2_BAR1_64ENA (1L<<4) 1602#define BCE_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 1603#define BCE_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 1604#define BCE_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 1605#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 1606#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 1607#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8) 1608#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8) 1609#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8) 1610#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8) 1611#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8) 1612#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8) 1613#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8) 1614#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8) 1615#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8) 1616#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8) 1617#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8) 1618#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8) 1619#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8) 1620#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8) 1621#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8) 1622#define BCE_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16) 1623#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21) 1624#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21) 1625#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21) 1626#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21) 1627#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21) 1628#define BCE_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23) 1629#define BCE_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24) 1630#define BCE_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25) 1631 1632#define BCE_PCI_CONFIG_3 0x0000040c 1633#define BCE_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 1634#define BCE_PCI_CONFIG_3_FORCE_PME (1L<<24) 1635#define BCE_PCI_CONFIG_3_PME_STATUS (1L<<25) 1636#define BCE_PCI_CONFIG_3_PME_ENABLE (1L<<26) 1637#define BCE_PCI_CONFIG_3_PM_STATE (0x3L<<27) 1638#define BCE_PCI_CONFIG_3_VAUX_PRESET (1L<<30) 1639#define BCE_PCI_CONFIG_3_PCI_POWER (1L<<31) 1640 1641#define BCE_PCI_PM_DATA_A 0x00000410 1642#define BCE_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0) 1643#define BCE_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8) 1644#define BCE_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16) 1645#define BCE_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24) 1646 1647#define BCE_PCI_PM_DATA_B 0x00000414 1648#define BCE_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0) 1649#define BCE_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8) 1650#define BCE_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16) 1651#define BCE_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24) 1652 1653#define BCE_PCI_SWAP_DIAG0 0x00000418 1654#define BCE_PCI_SWAP_DIAG1 0x0000041c 1655#define BCE_PCI_EXP_ROM_ADDR 0x00000420 1656#define BCE_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2) 1657#define BCE_PCI_EXP_ROM_ADDR_REQ (1L<<31) 1658 1659#define BCE_PCI_EXP_ROM_DATA 0x00000424 1660#define BCE_PCI_VPD_INTF 0x00000428 1661#define BCE_PCI_VPD_INTF_INTF_REQ (1L<<0) 1662 1663#define BCE_PCI_VPD_ADDR_FLAG 0x0000042c 1664#define BCE_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) 1665#define BCE_PCI_VPD_ADDR_FLAG_WR (1<<15) 1666 1667#define BCE_PCI_VPD_DATA 0x00000430 1668#define BCE_PCI_ID_VAL1 0x00000434 1669#define BCE_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0) 1670#define BCE_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16) 1671 1672#define BCE_PCI_ID_VAL2 0x00000438 1673#define BCE_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0) 1674#define BCE_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16) 1675 1676#define BCE_PCI_ID_VAL3 0x0000043c 1677#define BCE_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0) 1678#define BCE_PCI_ID_VAL3_REVISION_ID (0xffL<<24) 1679 1680#define BCE_PCI_ID_VAL4 0x00000440 1681#define BCE_PCI_ID_VAL4_CAP_ENA (0xfL<<0) 1682#define BCE_PCI_ID_VAL4_CAP_ENA_0 (0L<<0) 1683#define BCE_PCI_ID_VAL4_CAP_ENA_1 (1L<<0) 1684#define BCE_PCI_ID_VAL4_CAP_ENA_2 (2L<<0) 1685#define BCE_PCI_ID_VAL4_CAP_ENA_3 (3L<<0) 1686#define BCE_PCI_ID_VAL4_CAP_ENA_4 (4L<<0) 1687#define BCE_PCI_ID_VAL4_CAP_ENA_5 (5L<<0) 1688#define BCE_PCI_ID_VAL4_CAP_ENA_6 (6L<<0) 1689#define BCE_PCI_ID_VAL4_CAP_ENA_7 (7L<<0) 1690#define BCE_PCI_ID_VAL4_CAP_ENA_8 (8L<<0) 1691#define BCE_PCI_ID_VAL4_CAP_ENA_9 (9L<<0) 1692#define BCE_PCI_ID_VAL4_CAP_ENA_10 (10L<<0) 1693#define BCE_PCI_ID_VAL4_CAP_ENA_11 (11L<<0) 1694#define BCE_PCI_ID_VAL4_CAP_ENA_12 (12L<<0) 1695#define BCE_PCI_ID_VAL4_CAP_ENA_13 (13L<<0) 1696#define BCE_PCI_ID_VAL4_CAP_ENA_14 (14L<<0) 1697#define BCE_PCI_ID_VAL4_CAP_ENA_15 (15L<<0) 1698#define BCE_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6) 1699#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6) 1700#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6) 1701#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6) 1702#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6) 1703#define BCE_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9) 1704#define BCE_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12) 1705#define BCE_PCI_ID_VAL4_MSI_ENABLE (1L<<15) 1706#define BCE_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16) 1707#define BCE_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17) 1708#define BCE_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21) 1709#define BCE_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23) 1710#define BCE_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26) 1711 1712#define BCE_PCI_ID_VAL5 0x00000444 1713#define BCE_PCI_ID_VAL5_D1_SUPPORT (1L<<0) 1714#define BCE_PCI_ID_VAL5_D2_SUPPORT (1L<<1) 1715#define BCE_PCI_ID_VAL5_PME_IN_D0 (1L<<2) 1716#define BCE_PCI_ID_VAL5_PME_IN_D1 (1L<<3) 1717#define BCE_PCI_ID_VAL5_PME_IN_D2 (1L<<4) 1718#define BCE_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5) 1719 1720#define BCE_PCI_PCIX_EXTENDED_STATUS 0x00000448 1721#define BCE_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8) 1722#define BCE_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9) 1723#define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16) 1724#define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24) 1725 1726#define BCE_PCI_ID_VAL6 0x0000044c 1727#define BCE_PCI_ID_VAL6_MAX_LAT (0xffL<<0) 1728#define BCE_PCI_ID_VAL6_MIN_GNT (0xffL<<8) 1729#define BCE_PCI_ID_VAL6_BIST (0xffL<<16) 1730 1731#define BCE_PCI_MSI_DATA 0x00000450 1732#define BCE_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0) 1733 1734#define BCE_PCI_MSI_ADDR_H 0x00000454 1735#define BCE_PCI_MSI_ADDR_L 0x00000458 1736 1737/* 1738 * misc_reg definition 1739 * offset: 0x800 1740 */ 1741#define BCE_MISC_COMMAND 0x00000800 1742#define BCE_MISC_COMMAND_ENABLE_ALL (1L<<0) 1743#define BCE_MISC_COMMAND_DISABLE_ALL (1L<<1) 1744#define BCE_MISC_COMMAND_SW_RESET (1L<<4) 1745#define BCE_MISC_COMMAND_POR_RESET (1L<<5) 1746#define BCE_MISC_COMMAND_HD_RESET (1L<<6) 1747#define BCE_MISC_COMMAND_CMN_SW_RESET (1L<<7) 1748#define BCE_MISC_COMMAND_PAR_ERROR (1L<<8) 1749#define BCE_MISC_COMMAND_CS16_ERR (1L<<9) 1750#define BCE_MISC_COMMAND_CS16_ERR_LOC (0xfL<<12) 1751#define BCE_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16) 1752#define BCE_MISC_COMMAND_POWERDOWN_EVENT (1L<<23) 1753#define BCE_MISC_COMMAND_SW_SHUTDOWN (1L<<24) 1754#define BCE_MISC_COMMAND_SHUTDOWN_EN (1L<<25) 1755#define BCE_MISC_COMMAND_DINTEG_ATTN_EN (1L<<26) 1756#define BCE_MISC_COMMAND_PCIE_LINK_IN_L23 (1L<<27) 1757#define BCE_MISC_COMMAND_PCIE_DIS (1L<<28) 1758 1759#define BCE_MISC_CFG 0x00000804 1760#define BCE_MISC_CFG_GRC_TMOUT (1L<<0) 1761#define BCE_MISC_CFG_NVM_WR_EN (0x3L<<1) 1762#define BCE_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1) 1763#define BCE_MISC_CFG_NVM_WR_EN_PCI (1L<<1) 1764#define BCE_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1) 1765#define BCE_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1) 1766#define BCE_MISC_CFG_BIST_EN (1L<<3) 1767#define BCE_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4) 1768#define BCE_MISC_CFG_RESERVED5_TE (1L<<5) 1769#define BCE_MISC_CFG_RESERVED6_TE (1L<<6) 1770#define BCE_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7) 1771#define BCE_MISC_CFG_LEDMODE (0x7L<<8) 1772#define BCE_MISC_CFG_LEDMODE_MAC (0L<<8) 1773#define BCE_MISC_CFG_LEDMODE_PHY1_TE (1L<<8) 1774#define BCE_MISC_CFG_LEDMODE_PHY2_TE (2L<<8) 1775#define BCE_MISC_CFG_LEDMODE_PHY3_TE (3L<<8) 1776#define BCE_MISC_CFG_LEDMODE_PHY4_TE (4L<<8) 1777#define BCE_MISC_CFG_LEDMODE_PHY5_TE (5L<<8) 1778#define BCE_MISC_CFG_LEDMODE_PHY6_TE (6L<<8) 1779#define BCE_MISC_CFG_LEDMODE_PHY7_TE (7L<<8) 1780#define BCE_MISC_CFG_MCP_GRC_TMOUT_TE (1L<<11) 1781#define BCE_MISC_CFG_DBU_GRC_TMOUT_TE (1L<<12) 1782#define BCE_MISC_CFG_LEDMODE_XI (0xfL<<8) 1783#define BCE_MISC_CFG_LEDMODE_MAC_XI (0L<<8) 1784#define BCE_MISC_CFG_LEDMODE_PHY1_XI (1L<<8) 1785#define BCE_MISC_CFG_LEDMODE_PHY2_XI (2L<<8) 1786#define BCE_MISC_CFG_LEDMODE_PHY3_XI (3L<<8) 1787#define BCE_MISC_CFG_LEDMODE_MAC2_XI (4L<<8) 1788#define BCE_MISC_CFG_LEDMODE_PHY4_XI (5L<<8) 1789#define BCE_MISC_CFG_LEDMODE_PHY5_XI (6L<<8) 1790#define BCE_MISC_CFG_LEDMODE_PHY6_XI (7L<<8) 1791#define BCE_MISC_CFG_LEDMODE_MAC3_XI (8L<<8) 1792#define BCE_MISC_CFG_LEDMODE_PHY7_XI (9L<<8) 1793#define BCE_MISC_CFG_LEDMODE_PHY8_XI (10L<<8) 1794#define BCE_MISC_CFG_LEDMODE_PHY9_XI (11L<<8) 1795#define BCE_MISC_CFG_LEDMODE_MAC4_XI (12L<<8) 1796#define BCE_MISC_CFG_LEDMODE_PHY10_XI (13L<<8) 1797#define BCE_MISC_CFG_LEDMODE_PHY11_XI (14L<<8) 1798#define BCE_MISC_CFG_LEDMODE_UNUSED_XI (15L<<8) 1799#define BCE_MISC_CFG_PORT_SELECT_XI (1L<<13) 1800#define BCE_MISC_CFG_PARITY_MODE_XI (1L<<14) 1801 1802#define BCE_MISC_ID 0x00000808 1803#define BCE_MISC_ID_BOND_ID (0xfL<<0) 1804#define BCE_MISC_ID_BOND_ID_X (0L<<0) 1805#define BCE_MISC_ID_BOND_ID_C (3L<<0) 1806#define BCE_MISC_ID_BOND_ID_S (12L<<0) 1807#define BCE_MISC_ID_CHIP_METAL (0xffL<<4) 1808#define BCE_MISC_ID_CHIP_REV (0xfL<<12) 1809#define BCE_MISC_ID_CHIP_NUM (0xffffL<<16) 1810 1811#define BCE_MISC_ENABLE_STATUS_BITS 0x0000080c 1812#define BCE_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1813#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1) 1814#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1815#define BCE_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1816#define BCE_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4) 1817#define BCE_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5) 1818#define BCE_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1819#define BCE_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1820#define BCE_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1821#define BCE_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9) 1822#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1823#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1824#define BCE_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12) 1825#define BCE_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13) 1826#define BCE_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1827#define BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15) 1828#define BCE_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1829#define BCE_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17) 1830#define BCE_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18) 1831#define BCE_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19) 1832#define BCE_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1833#define BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21) 1834#define BCE_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1835#define BCE_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1836#define BCE_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1837#define BCE_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25) 1838#define BCE_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26) 1839#define BCE_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27) 1840#define BCE_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28) 1841#define BCE_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE (0x7L<<29) 1842 1843#define BCE_MISC_ENABLE_SET_BITS 0x00000810 1844#define BCE_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1845#define BCE_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1) 1846#define BCE_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1847#define BCE_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1848#define BCE_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4) 1849#define BCE_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5) 1850#define BCE_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1851#define BCE_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1852#define BCE_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1853#define BCE_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9) 1854#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1855#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1856#define BCE_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12) 1857#define BCE_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13) 1858#define BCE_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1859#define BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15) 1860#define BCE_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1861#define BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17) 1862#define BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18) 1863#define BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19) 1864#define BCE_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1865#define BCE_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21) 1866#define BCE_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1867#define BCE_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1868#define BCE_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1869#define BCE_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25) 1870#define BCE_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26) 1871#define BCE_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27) 1872#define BCE_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28) 1873#define BCE_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE (0x7L<<29) 1874 1875#define BCE_MISC_ENABLE_DEFAULT 0x05ffffff 1876#define BCE_MISC_ENABLE_DEFAULT_XI 0x17ffffff 1877 1878#define BCE_MISC_ENABLE_CLR_BITS 0x00000814 1879#define BCE_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1880#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1) 1881#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1882#define BCE_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1883#define BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4) 1884#define BCE_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5) 1885#define BCE_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1886#define BCE_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1887#define BCE_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1888#define BCE_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9) 1889#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1890#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1891#define BCE_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12) 1892#define BCE_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13) 1893#define BCE_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1894#define BCE_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15) 1895#define BCE_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1896#define BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17) 1897#define BCE_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18) 1898#define BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19) 1899#define BCE_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1900#define BCE_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21) 1901#define BCE_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1902#define BCE_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1903#define BCE_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1904#define BCE_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25) 1905#define BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26) 1906#define BCE_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27) 1907#define BCE_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28) 1908#define BCE_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE (0x7L<<29) 1909 1910#define BCE_MISC_ENABLE_CLR_DEFAULT 0x17ffffff 1911 1912#define BCE_MISC_CLOCK_CONTROL_BITS 0x00000818 1913#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1914#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1915#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1916#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1917#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1918#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1919#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1920#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1921#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1922#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1923#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1924#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1925#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1926#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1927#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1928#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1929#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1930#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI (0x7L<<8) 1931#define BCE_MISC_CLOCK_CONTROL_BITS_MIN_POWER (1L<<11) 1932#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1933#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1934#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1935#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1936#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1937#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1938#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI (0xfL<<12) 1939#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1940#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE (1L<<17) 1941#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE (1L<<18) 1942#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE (1L<<19) 1943#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_TE (0xfffL<<20) 1944#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI (1L<<17) 1945#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI (0x3fL<<18) 1946#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI (0x7L<<24) 1947#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI (1L<<27) 1948#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI (0xfL<<28) 1949 1950#define BCE_MISC_SPIO 0x0000081c 1951#define BCE_MISC_SPIO_VALUE (0xffL<<0) 1952#define BCE_MISC_SPIO_SET (0xffL<<8) 1953#define BCE_MISC_SPIO_CLR (0xffL<<16) 1954#define BCE_MISC_SPIO_FLOAT (0xffL<<24) 1955 1956#define BCE_MISC_SPIO_INT 0x00000820 1957#define BCE_MISC_SPIO_INT_INT_STATE_TE (0xfL<<0) 1958#define BCE_MISC_SPIO_INT_OLD_VALUE_TE (0xfL<<8) 1959#define BCE_MISC_SPIO_INT_OLD_SET_TE (0xfL<<16) 1960#define BCE_MISC_SPIO_INT_OLD_CLR_TE (0xfL<<24) 1961#define BCE_MISC_SPIO_INT_INT_STATE_XI (0xffL<<0) 1962#define BCE_MISC_SPIO_INT_OLD_VALUE_XI (0xffL<<8) 1963#define BCE_MISC_SPIO_INT_OLD_SET_XI (0xffL<<16) 1964#define BCE_MISC_SPIO_INT_OLD_CLR_XI (0xffL<<24) 1965 1966#define BCE_MISC_CONFIG_LFSR 0x00000824 1967#define BCE_MISC_CONFIG_LFSR_DIV (0xffffL<<0) 1968 1969#define BCE_MISC_LFSR_MASK_BITS 0x00000828 1970#define BCE_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1971#define BCE_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1) 1972#define BCE_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1973#define BCE_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1974#define BCE_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4) 1975#define BCE_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5) 1976#define BCE_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1977#define BCE_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1978#define BCE_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1979#define BCE_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9) 1980#define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1981#define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1982#define BCE_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12) 1983#define BCE_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13) 1984#define BCE_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1985#define BCE_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15) 1986#define BCE_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1987#define BCE_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17) 1988#define BCE_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18) 1989#define BCE_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19) 1990#define BCE_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1991#define BCE_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21) 1992#define BCE_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1993#define BCE_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1994#define BCE_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1995#define BCE_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25) 1996#define BCE_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26) 1997#define BCE_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27) 1998#define BCE_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28) 1999#define BCE_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE (0x7L<<29) 2000 2001#define BCE_MISC_ARB_REQ0 0x0000082c 2002#define BCE_MISC_ARB_REQ1 0x00000830 2003#define BCE_MISC_ARB_REQ2 0x00000834 2004#define BCE_MISC_ARB_REQ3 0x00000838 2005#define BCE_MISC_ARB_REQ4 0x0000083c 2006#define BCE_MISC_ARB_FREE0 0x00000840 2007#define BCE_MISC_ARB_FREE1 0x00000844 2008#define BCE_MISC_ARB_FREE2 0x00000848 2009#define BCE_MISC_ARB_FREE3 0x0000084c 2010#define BCE_MISC_ARB_FREE4 0x00000850 2011#define BCE_MISC_ARB_REQ_STATUS0 0x00000854 2012#define BCE_MISC_ARB_REQ_STATUS1 0x00000858 2013#define BCE_MISC_ARB_REQ_STATUS2 0x0000085c 2014#define BCE_MISC_ARB_REQ_STATUS3 0x00000860 2015#define BCE_MISC_ARB_REQ_STATUS4 0x00000864 2016#define BCE_MISC_ARB_GNT0 0x00000868 2017#define BCE_MISC_ARB_GNT0_0 (0x7L<<0) 2018#define BCE_MISC_ARB_GNT0_1 (0x7L<<4) 2019#define BCE_MISC_ARB_GNT0_2 (0x7L<<8) 2020#define BCE_MISC_ARB_GNT0_3 (0x7L<<12) 2021#define BCE_MISC_ARB_GNT0_4 (0x7L<<16) 2022#define BCE_MISC_ARB_GNT0_5 (0x7L<<20) 2023#define BCE_MISC_ARB_GNT0_6 (0x7L<<24) 2024#define BCE_MISC_ARB_GNT0_7 (0x7L<<28) 2025 2026#define BCE_MISC_ARB_GNT1 0x0000086c 2027#define BCE_MISC_ARB_GNT1_8 (0x7L<<0) 2028#define BCE_MISC_ARB_GNT1_9 (0x7L<<4) 2029#define BCE_MISC_ARB_GNT1_10 (0x7L<<8) 2030#define BCE_MISC_ARB_GNT1_11 (0x7L<<12) 2031#define BCE_MISC_ARB_GNT1_12 (0x7L<<16) 2032#define BCE_MISC_ARB_GNT1_13 (0x7L<<20) 2033#define BCE_MISC_ARB_GNT1_14 (0x7L<<24) 2034#define BCE_MISC_ARB_GNT1_15 (0x7L<<28) 2035 2036#define BCE_MISC_ARB_GNT2 0x00000870 2037#define BCE_MISC_ARB_GNT2_16 (0x7L<<0) 2038#define BCE_MISC_ARB_GNT2_17 (0x7L<<4) 2039#define BCE_MISC_ARB_GNT2_18 (0x7L<<8) 2040#define BCE_MISC_ARB_GNT2_19 (0x7L<<12) 2041#define BCE_MISC_ARB_GNT2_20 (0x7L<<16) 2042#define BCE_MISC_ARB_GNT2_21 (0x7L<<20) 2043#define BCE_MISC_ARB_GNT2_22 (0x7L<<24) 2044#define BCE_MISC_ARB_GNT2_23 (0x7L<<28) 2045 2046#define BCE_MISC_ARB_GNT3 0x00000874 2047#define BCE_MISC_ARB_GNT3_24 (0x7L<<0) 2048#define BCE_MISC_ARB_GNT3_25 (0x7L<<4) 2049#define BCE_MISC_ARB_GNT3_26 (0x7L<<8) 2050#define BCE_MISC_ARB_GNT3_27 (0x7L<<12) 2051#define BCE_MISC_ARB_GNT3_28 (0x7L<<16) 2052#define BCE_MISC_ARB_GNT3_29 (0x7L<<20) 2053#define BCE_MISC_ARB_GNT3_30 (0x7L<<24) 2054#define BCE_MISC_ARB_GNT3_31 (0x7L<<28) 2055 2056#define BCE_MISC_RESERVED1 0x00000878 2057#define BCE_MISC_RESERVED1_MISC_RESERVED1_VALUE (0x3fL<<0) 2058 2059#define BCE_MISC_RESERVED2 0x0000087c 2060#define BCE_MISC_RESERVED2_PCIE_DIS (1L<<0) 2061#define BCE_MISC_RESERVED2_LINK_IN_L23 (1L<<1) 2062 2063#define BCE_MISC_SM_ASF_CONTROL 0x00000880 2064#define BCE_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0) 2065#define BCE_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1) 2066#define BCE_MISC_SM_ASF_CONTROL_WG_TO (1L<<2) 2067#define BCE_MISC_SM_ASF_CONTROL_HB_TO (1L<<3) 2068#define BCE_MISC_SM_ASF_CONTROL_PA_TO (1L<<4) 2069#define BCE_MISC_SM_ASF_CONTROL_PL_TO (1L<<5) 2070#define BCE_MISC_SM_ASF_CONTROL_RT_TO (1L<<6) 2071#define BCE_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7) 2072#define BCE_MISC_SM_ASF_CONTROL_STRETCH_EN (1L<<8) 2073#define BCE_MISC_SM_ASF_CONTROL_STRETCH_PULSE (1L<<9) 2074#define BCE_MISC_SM_ASF_CONTROL_RES (0x3L<<10) 2075#define BCE_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12) 2076#define BCE_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13) 2077#define BCE_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14) 2078#define BCE_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15) 2079#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x7fL<<16) 2080#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x7fL<<23) 2081#define BCE_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30) 2082#define BCE_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31) 2083 2084#define BCE_MISC_SMB_IN 0x00000884 2085#define BCE_MISC_SMB_IN_DAT_IN (0xffL<<0) 2086#define BCE_MISC_SMB_IN_RDY (1L<<8) 2087#define BCE_MISC_SMB_IN_DONE (1L<<9) 2088#define BCE_MISC_SMB_IN_FIRSTBYTE (1L<<10) 2089#define BCE_MISC_SMB_IN_STATUS (0x7L<<11) 2090#define BCE_MISC_SMB_IN_STATUS_OK (0x0L<<11) 2091#define BCE_MISC_SMB_IN_STATUS_PEC (0x1L<<11) 2092#define BCE_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11) 2093#define BCE_MISC_SMB_IN_STATUS_STOP (0x3L<<11) 2094#define BCE_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11) 2095 2096#define BCE_MISC_SMB_OUT 0x00000888 2097#define BCE_MISC_SMB_OUT_DAT_OUT (0xffL<<0) 2098#define BCE_MISC_SMB_OUT_RDY (1L<<8) 2099#define BCE_MISC_SMB_OUT_START (1L<<9) 2100#define BCE_MISC_SMB_OUT_LAST (1L<<10) 2101#define BCE_MISC_SMB_OUT_ACC_TYPE (1L<<11) 2102#define BCE_MISC_SMB_OUT_ENB_PEC (1L<<12) 2103#define BCE_MISC_SMB_OUT_GET_RX_LEN (1L<<13) 2104#define BCE_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14) 2105#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20) 2106#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20) 2107#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20) 2108#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20) 2109#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20) 2110#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20) 2111#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20) 2112#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (6L<<20) 2113#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20) 2114#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20) 2115#define BCE_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24) 2116#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25) 2117#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26) 2118#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27) 2119#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28) 2120 2121#define BCE_MISC_SMB_WATCHDOG 0x0000088c 2122#define BCE_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0) 2123 2124#define BCE_MISC_SMB_HEARTBEAT 0x00000890 2125#define BCE_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0) 2126 2127#define BCE_MISC_SMB_POLL_ASF 0x00000894 2128#define BCE_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0) 2129 2130#define BCE_MISC_SMB_POLL_LEGACY 0x00000898 2131#define BCE_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0) 2132 2133#define BCE_MISC_SMB_RETRAN 0x0000089c 2134#define BCE_MISC_SMB_RETRAN_RETRAN (0xffL<<0) 2135 2136#define BCE_MISC_SMB_TIMESTAMP 0x000008a0 2137#define BCE_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0) 2138 2139#define BCE_MISC_PERR_ENA0 0x000008a4 2140#define BCE_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0) 2141#define BCE_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1) 2142#define BCE_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2) 2143#define BCE_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3) 2144#define BCE_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4) 2145#define BCE_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5) 2146#define BCE_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6) 2147#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7) 2148#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8) 2149#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9) 2150#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10) 2151#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11) 2152#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12) 2153#define BCE_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13) 2154#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14) 2155#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15) 2156#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16) 2157#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17) 2158#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18) 2159#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19) 2160#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20) 2161#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21) 2162#define BCE_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22) 2163#define BCE_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23) 2164#define BCE_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24) 2165#define BCE_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25) 2166#define BCE_MISC_PERR_ENA0_RBDC_MISC (1L<<26) 2167#define BCE_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27) 2168#define BCE_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28) 2169#define BCE_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29) 2170#define BCE_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30) 2171#define BCE_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31) 2172#define BCE_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI (1L<<0) 2173#define BCE_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI (1L<<1) 2174#define BCE_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI (1L<<2) 2175#define BCE_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI (1L<<3) 2176#define BCE_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI (1L<<4) 2177#define BCE_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI (1L<<5) 2178#define BCE_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI (1L<<6) 2179#define BCE_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI (1L<<7) 2180#define BCE_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI (1L<<8) 2181#define BCE_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI (1L<<9) 2182#define BCE_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI (1L<<10) 2183#define BCE_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI (1L<<11) 2184#define BCE_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI (1L<<12) 2185#define BCE_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI (1L<<13) 2186#define BCE_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI (1L<<14) 2187#define BCE_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI (1L<<15) 2188#define BCE_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI (1L<<16) 2189#define BCE_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI (1L<<17) 2190#define BCE_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI (1L<<18) 2191#define BCE_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI (1L<<19) 2192#define BCE_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI (1L<<20) 2193#define BCE_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI (1L<<21) 2194#define BCE_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI (1L<<22) 2195#define BCE_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI (1L<<23) 2196#define BCE_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI (1L<<24) 2197#define BCE_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI (1L<<25) 2198#define BCE_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI (1L<<26) 2199#define BCE_MISC_PERR_ENA0_TPBUF_PERR_EN_XI (1L<<27) 2200#define BCE_MISC_PERR_ENA0_THBUF_PERR_EN_XI (1L<<28) 2201#define BCE_MISC_PERR_ENA0_TDMA_PERR_EN_XI (1L<<29) 2202#define BCE_MISC_PERR_ENA0_TBDC_PERR_EN_XI (1L<<30) 2203#define BCE_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI (1L<<31) 2204 2205#define BCE_MISC_PERR_ENA1 0x000008a8 2206#define BCE_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0) 2207#define BCE_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1) 2208#define BCE_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2) 2209#define BCE_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3) 2210#define BCE_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4) 2211#define BCE_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5) 2212#define BCE_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6) 2213#define BCE_MISC_PERR_ENA1_TBDC_MISC (1L<<7) 2214#define BCE_MISC_PERR_ENA1_TDMA_MISC (1L<<8) 2215#define BCE_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9) 2216#define BCE_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10) 2217#define BCE_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11) 2218#define BCE_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12) 2219#define BCE_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13) 2220#define BCE_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14) 2221#define BCE_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15) 2222#define BCE_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16) 2223#define BCE_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17) 2224#define BCE_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18) 2225#define BCE_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19) 2226#define BCE_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20) 2227#define BCE_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21) 2228#define BCE_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22) 2229#define BCE_MISC_PERR_ENA1_CSQ_MISC (1L<<23) 2230#define BCE_MISC_PERR_ENA1_CPQ_MISC (1L<<24) 2231#define BCE_MISC_PERR_ENA1_MCPQ_MISC (1L<<25) 2232#define BCE_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26) 2233#define BCE_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27) 2234#define BCE_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28) 2235#define BCE_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) 2236#define BCE_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) 2237#define BCE_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) 2238#define BCE_MISC_PERR_ENA1_RBDC_PERR_EN_XI (1L<<0) 2239#define BCE_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI (1L<<2) 2240#define BCE_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI (1L<<3) 2241#define BCE_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI (1L<<4) 2242#define BCE_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI (1L<<5) 2243#define BCE_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI (1L<<6) 2244#define BCE_MISC_PERR_ENA1_TPATQ_PERR_EN_XI (1L<<7) 2245#define BCE_MISC_PERR_ENA1_MCPQ_PERR_EN_XI (1L<<8) 2246#define BCE_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI (1L<<9) 2247#define BCE_MISC_PERR_ENA1_TXPQ_PERR_EN_XI (1L<<10) 2248#define BCE_MISC_PERR_ENA1_COMTQ_PERR_EN_XI (1L<<11) 2249#define BCE_MISC_PERR_ENA1_COMQ_PERR_EN_XI (1L<<12) 2250#define BCE_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI (1L<<13) 2251#define BCE_MISC_PERR_ENA1_RXPQ_PERR_EN_XI (1L<<14) 2252#define BCE_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI (1L<<15) 2253#define BCE_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI (1L<<16) 2254#define BCE_MISC_PERR_ENA1_TASQ_PERR_EN_XI (1L<<17) 2255#define BCE_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI (1L<<18) 2256#define BCE_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI (1L<<19) 2257#define BCE_MISC_PERR_ENA1_COMXQ_PERR_EN_XI (1L<<20) 2258#define BCE_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI (1L<<21) 2259#define BCE_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI (1L<<22) 2260#define BCE_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI (1L<<23) 2261#define BCE_MISC_PERR_ENA1_CPQ_PERR_EN_XI (1L<<24) 2262#define BCE_MISC_PERR_ENA1_CSQ_PERR_EN_XI (1L<<25) 2263#define BCE_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI (1L<<26) 2264#define BCE_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI (1L<<27) 2265#define BCE_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI (1L<<28) 2266#define BCE_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI (1L<<29) 2267 2268#define BCE_MISC_PERR_ENA2 0x000008ac 2269#define BCE_MISC_PERR_ENA2_COMQ_MISC (1L<<0) 2270#define BCE_MISC_PERR_ENA2_COMXQ_MISC (1L<<1) 2271#define BCE_MISC_PERR_ENA2_COMTQ_MISC (1L<<2) 2272#define BCE_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3) 2273#define BCE_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4) 2274#define BCE_MISC_PERR_ENA2_TXPQ_MISC (1L<<5) 2275#define BCE_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6) 2276#define BCE_MISC_PERR_ENA2_TPATQ_MISC (1L<<7) 2277#define BCE_MISC_PERR_ENA2_TASQ_MISC (1L<<8) 2278#define BCE_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI (1L<<0) 2279#define BCE_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI (1L<<1) 2280#define BCE_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI (1L<<2) 2281#define BCE_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI (1L<<3) 2282#define BCE_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI (1L<<4) 2283#define BCE_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI (1L<<5) 2284#define BCE_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI (1L<<6) 2285 2286#define BCE_MISC_DEBUG_VECTOR_SEL 0x000008b0 2287#define BCE_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0) 2288#define BCE_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12) 2289#define BCE_MISC_DEBUG_VECTOR_SEL_1_XI (0xfffL<<15) 2290 2291#define BCE_MISC_VREG_CONTROL 0x000008b4 2292#define BCE_MISC_VREG_CONTROL_1_2 (0xfL<<0) 2293#define BCE_MISC_VREG_CONTROL_1_0_MAIN_XI (0xfL<<0) 2294#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI (0L<<0) 2295#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI (1L<<0) 2296#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI (2L<<0) 2297#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI (3L<<0) 2298#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI (4L<<0) 2299#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI (5L<<0) 2300#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI (6L<<0) 2301#define BCE_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI (7L<<0) 2302#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI (8L<<0) 2303#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI (9L<<0) 2304#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI (10L<<0) 2305#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI (11L<<0) 2306#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI (12L<<0) 2307#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI (13L<<0) 2308#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI (14L<<0) 2309#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI (15L<<0) 2310#define BCE_MISC_VREG_CONTROL_2_5 (0xfL<<4) 2311#define BCE_MISC_VREG_CONTROL_2_5_PLUS14 (0L<<4) 2312#define BCE_MISC_VREG_CONTROL_2_5_PLUS12 (1L<<4) 2313#define BCE_MISC_VREG_CONTROL_2_5_PLUS10 (2L<<4) 2314#define BCE_MISC_VREG_CONTROL_2_5_PLUS8 (3L<<4) 2315#define BCE_MISC_VREG_CONTROL_2_5_PLUS6 (4L<<4) 2316#define BCE_MISC_VREG_CONTROL_2_5_PLUS4 (5L<<4) 2317#define BCE_MISC_VREG_CONTROL_2_5_PLUS2 (6L<<4) 2318#define BCE_MISC_VREG_CONTROL_2_5_NOM (7L<<4) 2319#define BCE_MISC_VREG_CONTROL_2_5_MINUS2 (8L<<4) 2320#define BCE_MISC_VREG_CONTROL_2_5_MINUS4 (9L<<4) 2321#define BCE_MISC_VREG_CONTROL_2_5_MINUS6 (10L<<4) 2322#define BCE_MISC_VREG_CONTROL_2_5_MINUS8 (11L<<4) 2323#define BCE_MISC_VREG_CONTROL_2_5_MINUS10 (12L<<4) 2324#define BCE_MISC_VREG_CONTROL_2_5_MINUS12 (13L<<4) 2325#define BCE_MISC_VREG_CONTROL_2_5_MINUS14 (14L<<4) 2326#define BCE_MISC_VREG_CONTROL_2_5_MINUS16 (15L<<4) 2327#define BCE_MISC_VREG_CONTROL_1_0_MGMT (0xfL<<8) 2328#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS14 (0L<<8) 2329#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS12 (1L<<8) 2330#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS10 (2L<<8) 2331#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS8 (3L<<8) 2332#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS6 (4L<<8) 2333#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS4 (5L<<8) 2334#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS2 (6L<<8) 2335#define BCE_MISC_VREG_CONTROL_1_0_MGMT_NOM (7L<<8) 2336#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS2 (8L<<8) 2337#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS4 (9L<<8) 2338#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS6 (10L<<8) 2339#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS8 (11L<<8) 2340#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS10 (12L<<8) 2341#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS12 (13L<<8) 2342#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS14 (14L<<8) 2343#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS16 (15L<<8) 2344 2345#define BCE_MISC_FINAL_CLK_CTL_VAL 0x000008b8 2346#define BCE_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6) 2347 2348#define BCE_MISC_GP_HW_CTL0 0x000008bc 2349#define BCE_MISC_GP_HW_CTL0_TX_DRIVE (1L<<0) 2350#define BCE_MISC_GP_HW_CTL0_RMII_MODE (1L<<1) 2351#define BCE_MISC_GP_HW_CTL0_RMII_CRSDV_SEL (1L<<2) 2352#define BCE_MISC_GP_HW_CTL0_RVMII_MODE (1L<<3) 2353#define BCE_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE (1L<<4) 2354#define BCE_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE (1L<<5) 2355#define BCE_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE (1L<<6) 2356#define BCE_MISC_GP_HW_CTL0_RESERVED1_XI (0x7L<<4) 2357#define BCE_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY (1L<<7) 2358#define BCE_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE (1L<<8) 2359#define BCE_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE (1L<<9) 2360#define BCE_MISC_GP_HW_CTL0_LED_ACT_SEL_TE (1L<<10) 2361#define BCE_MISC_GP_HW_CTL0_RESERVED2_XI (0x7L<<8) 2362#define BCE_MISC_GP_HW_CTL0_UP1_DEF0 (1L<<11) 2363#define BCE_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF (1L<<12) 2364#define BCE_MISC_GP_HW_CTL0_FORCE2500_DEF (1L<<13) 2365#define BCE_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF (1L<<14) 2366#define BCE_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF (1L<<15) 2367#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI (0xfL<<16) 2368#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA (0L<<16) 2369#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA (1L<<16) 2370#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA (3L<<16) 2371#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA (5L<<16) 2372#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA (7L<<16) 2373#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN (15L<<16) 2374#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS (1L<<20) 2375#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS (1L<<21) 2376#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT (0x3L<<22) 2377#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P (0L<<22) 2378#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P (1L<<22) 2379#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P (2L<<22) 2380#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P (3L<<22) 2381#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT (0x3L<<24) 2382#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P (0L<<24) 2383#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P (1L<<24) 2384#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P (2L<<24) 2385#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P (3L<<24) 2386#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ (0x3L<<26) 2387#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA (0L<<26) 2388#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA (1L<<26) 2389#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA (2L<<26) 2390#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA (3L<<26) 2391#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ (0x3L<<28) 2392#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA (0L<<28) 2393#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA (1L<<28) 2394#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA (2L<<28) 2395#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA (3L<<28) 2396#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ (0x3L<<30) 2397#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57 (0L<<30) 2398#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45 (1L<<30) 2399#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62 (2L<<30) 2400#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66 (3L<<30) 2401 2402#define BCE_MISC_GP_HW_CTL1 0x000008c0 2403#define BCE_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE (1L<<0) 2404#define BCE_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE (1L<<1) 2405#define BCE_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE (1L<<2) 2406#define BCE_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE (1L<<3) 2407#define BCE_MISC_GP_HW_CTL1_RESERVED_SOFT_XI (0xffffL<<0) 2408#define BCE_MISC_GP_HW_CTL1_RESERVED_HARD_XI (0xffffL<<16) 2409 2410#define BCE_MISC_NEW_HW_CTL 0x000008c4 2411#define BCE_MISC_NEW_HW_CTL_MAIN_POR_BYPASS (1L<<0) 2412#define BCE_MISC_NEW_HW_CTL_RINGOSC_ENABLE (1L<<1) 2413#define BCE_MISC_NEW_HW_CTL_RINGOSC_SEL0 (1L<<2) 2414#define BCE_MISC_NEW_HW_CTL_RINGOSC_SEL1 (1L<<3) 2415#define BCE_MISC_NEW_HW_CTL_RESERVED_SHARED (0xfffL<<4) 2416#define BCE_MISC_NEW_HW_CTL_RESERVED_SPLIT (0xffffL<<16) 2417 2418#define BCE_MISC_NEW_CORE_CTL 0x000008c8 2419#define BCE_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0) 2420#define BCE_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1) 2421#define BCE_MISC_NEW_CORE_CTL_DMA_ENABLE (1L<<16) 2422#define BCE_MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffL<<2) 2423#define BCE_MISC_NEW_CORE_CTL_RESERVED_TC (0xffffL<<16) 2424 2425#define BCE_MISC_ECO_HW_CTL 0x000008cc 2426#define BCE_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN (1L<<0) 2427#define BCE_MISC_ECO_HW_CTL_RESERVED_SOFT (0x7fffL<<1) 2428#define BCE_MISC_ECO_HW_CTL_RESERVED_HARD (0xffffL<<16) 2429 2430#define BCE_MISC_ECO_CORE_CTL 0x000008d0 2431#define BCE_MISC_ECO_CORE_CTL_RESERVED_SOFT (0xffffL<<0) 2432#define BCE_MISC_ECO_CORE_CTL_RESERVED_HARD (0xffffL<<16) 2433 2434#define BCE_MISC_PPIO 0x000008d4 2435#define BCE_MISC_PPIO_VALUE (0xfL<<0) 2436#define BCE_MISC_PPIO_SET (0xfL<<8) 2437#define BCE_MISC_PPIO_CLR (0xfL<<16) 2438#define BCE_MISC_PPIO_FLOAT (0xfL<<24) 2439 2440#define BCE_MISC_PPIO_INT 0x000008d8 2441#define BCE_MISC_PPIO_INT_INT_STATE (0xfL<<0) 2442#define BCE_MISC_PPIO_INT_OLD_VALUE (0xfL<<8) 2443#define BCE_MISC_PPIO_INT_OLD_SET (0xfL<<16) 2444#define BCE_MISC_PPIO_INT_OLD_CLR (0xfL<<24) 2445 2446#define BCE_MISC_RESET_NUMS 0x000008dc 2447#define BCE_MISC_RESET_NUMS_NUM_HARD_RESETS (0x7L<<0) 2448#define BCE_MISC_RESET_NUMS_NUM_PCIE_RESETS (0x7L<<4) 2449#define BCE_MISC_RESET_NUMS_NUM_PERSTB_RESETS (0x7L<<8) 2450#define BCE_MISC_RESET_NUMS_NUM_CMN_RESETS (0x7L<<12) 2451#define BCE_MISC_RESET_NUMS_NUM_PORT_RESETS (0x7L<<16) 2452 2453#define BCE_MISC_CS16_ERR 0x000008e0 2454#define BCE_MISC_CS16_ERR_ENA_PCI (1L<<0) 2455#define BCE_MISC_CS16_ERR_ENA_RDMA (1L<<1) 2456#define BCE_MISC_CS16_ERR_ENA_TDMA (1L<<2) 2457#define BCE_MISC_CS16_ERR_ENA_EMAC (1L<<3) 2458#define BCE_MISC_CS16_ERR_ENA_CTX (1L<<4) 2459#define BCE_MISC_CS16_ERR_ENA_TBDR (1L<<5) 2460#define BCE_MISC_CS16_ERR_ENA_RBDC (1L<<6) 2461#define BCE_MISC_CS16_ERR_ENA_COM (1L<<7) 2462#define BCE_MISC_CS16_ERR_ENA_CP (1L<<8) 2463#define BCE_MISC_CS16_ERR_STA_PCI (1L<<16) 2464#define BCE_MISC_CS16_ERR_STA_RDMA (1L<<17) 2465#define BCE_MISC_CS16_ERR_STA_TDMA (1L<<18) 2466#define BCE_MISC_CS16_ERR_STA_EMAC (1L<<19) 2467#define BCE_MISC_CS16_ERR_STA_CTX (1L<<20) 2468#define BCE_MISC_CS16_ERR_STA_TBDR (1L<<21) 2469#define BCE_MISC_CS16_ERR_STA_RBDC (1L<<22) 2470#define BCE_MISC_CS16_ERR_STA_COM (1L<<23) 2471#define BCE_MISC_CS16_ERR_STA_CP (1L<<24) 2472 2473#define BCE_MISC_SPIO_EVENT 0x000008e4 2474#define BCE_MISC_SPIO_EVENT_ENABLE (0xffL<<0) 2475 2476#define BCE_MISC_PPIO_EVENT 0x000008e8 2477#define BCE_MISC_PPIO_EVENT_ENABLE (0xfL<<0) 2478 2479#define BCE_MISC_DUAL_MEDIA_CTRL 0x000008ec 2480#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID (0xffL<<0) 2481#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_X (0L<<0) 2482#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C (3L<<0) 2483#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S (12L<<0) 2484#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP (0x7L<<8) 2485#define BCE_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN (1L<<11) 2486#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET (1L<<12) 2487#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET (1L<<13) 2488#define BCE_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET (1L<<14) 2489#define BCE_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET (1L<<15) 2490#define BCE_MISC_DUAL_MEDIA_CTRL_LCPLL_RST (1L<<16) 2491#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES1_RST (1L<<17) 2492#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES0_RST (1L<<18) 2493#define BCE_MISC_DUAL_MEDIA_CTRL_PHY1_RST (1L<<19) 2494#define BCE_MISC_DUAL_MEDIA_CTRL_PHY0_RST (1L<<20) 2495#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL (0x7L<<21) 2496#define BCE_MISC_DUAL_MEDIA_CTRL_PORT_SWAP (1L<<24) 2497#define BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE (1L<<25) 2498#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ (0xfL<<26) 2499#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ (1L<<26) 2500#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ (2L<<26) 2501#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ (4L<<26) 2502#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ (8L<<26) 2503 2504#define BCE_MISC_OTP_CMD1 0x000008f0 2505#define BCE_MISC_OTP_CMD1_FMODE (0x7L<<0) 2506#define BCE_MISC_OTP_CMD1_FMODE_IDLE (0L<<0) 2507#define BCE_MISC_OTP_CMD1_FMODE_WRITE (1L<<0) 2508#define BCE_MISC_OTP_CMD1_FMODE_INIT (2L<<0) 2509#define BCE_MISC_OTP_CMD1_FMODE_SET (3L<<0) 2510#define BCE_MISC_OTP_CMD1_FMODE_RST (4L<<0) 2511#define BCE_MISC_OTP_CMD1_FMODE_VERIFY (5L<<0) 2512#define BCE_MISC_OTP_CMD1_FMODE_RESERVED0 (6L<<0) 2513#define BCE_MISC_OTP_CMD1_FMODE_RESERVED1 (7L<<0) 2514#define BCE_MISC_OTP_CMD1_USEPINS (1L<<8) 2515#define BCE_MISC_OTP_CMD1_PROGSEL (1L<<9) 2516#define BCE_MISC_OTP_CMD1_PROGSTART (1L<<10) 2517#define BCE_MISC_OTP_CMD1_PCOUNT (0x7L<<16) 2518#define BCE_MISC_OTP_CMD1_PBYP (1L<<19) 2519#define BCE_MISC_OTP_CMD1_VSEL (0xfL<<20) 2520#define BCE_MISC_OTP_CMD1_TM (0x7L<<27) 2521#define BCE_MISC_OTP_CMD1_SADBYP (1L<<30) 2522#define BCE_MISC_OTP_CMD1_DEBUG (1L<<31) 2523 2524#define BCE_MISC_OTP_CMD2 0x000008f4 2525#define BCE_MISC_OTP_CMD2_OTP_ROM_ADDR (0x3ffL<<0) 2526#define BCE_MISC_OTP_CMD2_DOSEL (0x7fL<<16) 2527#define BCE_MISC_OTP_CMD2_DOSEL_0 (0L<<16) 2528#define BCE_MISC_OTP_CMD2_DOSEL_1 (1L<<16) 2529#define BCE_MISC_OTP_CMD2_DOSEL_127 (127L<<16) 2530 2531#define BCE_MISC_OTP_STATUS 0x000008f8 2532#define BCE_MISC_OTP_STATUS_DATA (0xffL<<0) 2533#define BCE_MISC_OTP_STATUS_VALID (1L<<8) 2534#define BCE_MISC_OTP_STATUS_BUSY (1L<<9) 2535#define BCE_MISC_OTP_STATUS_BUSYSM (1L<<10) 2536#define BCE_MISC_OTP_STATUS_DONE (1L<<11) 2537 2538#define BCE_MISC_OTP_SHIFT1_CMD 0x000008fc 2539#define BCE_MISC_OTP_SHIFT1_CMD_RESET_MODE_N (1L<<0) 2540#define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_DONE (1L<<1) 2541#define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_START (1L<<2) 2542#define BCE_MISC_OTP_SHIFT1_CMD_LOAD_DATA (1L<<3) 2543#define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT (0x1fL<<8) 2544 2545#define BCE_MISC_OTP_SHIFT1_DATA 0x00000900 2546#define BCE_MISC_OTP_SHIFT2_CMD 0x00000904 2547#define BCE_MISC_OTP_SHIFT2_CMD_RESET_MODE_N (1L<<0) 2548#define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_DONE (1L<<1) 2549#define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_START (1L<<2) 2550#define BCE_MISC_OTP_SHIFT2_CMD_LOAD_DATA (1L<<3) 2551#define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT (0x1fL<<8) 2552 2553#define BCE_MISC_OTP_SHIFT2_DATA 0x00000908 2554#define BCE_MISC_BIST_CS0 0x0000090c 2555#define BCE_MISC_BIST_CS0_MBIST_EN (1L<<0) 2556#define BCE_MISC_BIST_CS0_BIST_SETUP (0x3L<<1) 2557#define BCE_MISC_BIST_CS0_MBIST_ASYNC_RESET (1L<<3) 2558#define BCE_MISC_BIST_CS0_MBIST_DONE (1L<<8) 2559#define BCE_MISC_BIST_CS0_MBIST_GO (1L<<9) 2560#define BCE_MISC_BIST_CS0_BIST_OVERRIDE (1L<<31) 2561 2562#define BCE_MISC_BIST_MEMSTATUS0 0x00000910 2563#define BCE_MISC_BIST_CS1 0x00000914 2564#define BCE_MISC_BIST_CS1_MBIST_EN (1L<<0) 2565#define BCE_MISC_BIST_CS1_BIST_SETUP (0x3L<<1) 2566#define BCE_MISC_BIST_CS1_MBIST_ASYNC_RESET (1L<<3) 2567#define BCE_MISC_BIST_CS1_MBIST_DONE (1L<<8) 2568#define BCE_MISC_BIST_CS1_MBIST_GO (1L<<9) 2569 2570#define BCE_MISC_BIST_MEMSTATUS1 0x00000918 2571#define BCE_MISC_BIST_CS2 0x0000091c 2572#define BCE_MISC_BIST_CS2_MBIST_EN (1L<<0) 2573#define BCE_MISC_BIST_CS2_BIST_SETUP (0x3L<<1) 2574#define BCE_MISC_BIST_CS2_MBIST_ASYNC_RESET (1L<<3) 2575#define BCE_MISC_BIST_CS2_MBIST_DONE (1L<<8) 2576#define BCE_MISC_BIST_CS2_MBIST_GO (1L<<9) 2577 2578#define BCE_MISC_BIST_MEMSTATUS2 0x00000920 2579#define BCE_MISC_BIST_CS3 0x00000924 2580#define BCE_MISC_BIST_CS3_MBIST_EN (1L<<0) 2581#define BCE_MISC_BIST_CS3_BIST_SETUP (0x3L<<1) 2582#define BCE_MISC_BIST_CS3_MBIST_ASYNC_RESET (1L<<3) 2583#define BCE_MISC_BIST_CS3_MBIST_DONE (1L<<8) 2584#define BCE_MISC_BIST_CS3_MBIST_GO (1L<<9) 2585 2586#define BCE_MISC_BIST_MEMSTATUS3 0x00000928 2587#define BCE_MISC_BIST_CS4 0x0000092c 2588#define BCE_MISC_BIST_CS4_MBIST_EN (1L<<0) 2589#define BCE_MISC_BIST_CS4_BIST_SETUP (0x3L<<1) 2590#define BCE_MISC_BIST_CS4_MBIST_ASYNC_RESET (1L<<3) 2591#define BCE_MISC_BIST_CS4_MBIST_DONE (1L<<8) 2592#define BCE_MISC_BIST_CS4_MBIST_GO (1L<<9) 2593 2594#define BCE_MISC_BIST_MEMSTATUS4 0x00000930 2595#define BCE_MISC_BIST_CS5 0x00000934 2596#define BCE_MISC_BIST_CS5_MBIST_EN (1L<<0) 2597#define BCE_MISC_BIST_CS5_BIST_SETUP (0x3L<<1) 2598#define BCE_MISC_BIST_CS5_MBIST_ASYNC_RESET (1L<<3) 2599#define BCE_MISC_BIST_CS5_MBIST_DONE (1L<<8) 2600#define BCE_MISC_BIST_CS5_MBIST_GO (1L<<9) 2601 2602#define BCE_MISC_BIST_MEMSTATUS5 0x00000938 2603#define BCE_MISC_MEM_TM0 0x0000093c 2604#define BCE_MISC_MEM_TM0_PCIE_REPLAY_TM (0xfL<<0) 2605#define BCE_MISC_MEM_TM0_MCP_SCPAD (0xfL<<8) 2606#define BCE_MISC_MEM_TM0_UMP_TM (0xffL<<16) 2607#define BCE_MISC_MEM_TM0_HB_MEM_TM (0xfL<<24) 2608 2609#define BCE_MISC_USPLL_CTRL 0x00000940 2610#define BCE_MISC_USPLL_CTRL_PH_DET_DIS (1L<<0) 2611#define BCE_MISC_USPLL_CTRL_FREQ_DET_DIS (1L<<1) 2612#define BCE_MISC_USPLL_CTRL_LCPX (0x3fL<<2) 2613#define BCE_MISC_USPLL_CTRL_RX (0x3L<<8) 2614#define BCE_MISC_USPLL_CTRL_VC_EN (1L<<10) 2615#define BCE_MISC_USPLL_CTRL_VCO_MG (0x3L<<11) 2616#define BCE_MISC_USPLL_CTRL_KVCO_XF (0x7L<<13) 2617#define BCE_MISC_USPLL_CTRL_KVCO_XS (0x7L<<16) 2618#define BCE_MISC_USPLL_CTRL_TESTD_EN (1L<<19) 2619#define BCE_MISC_USPLL_CTRL_TESTD_SEL (0x7L<<20) 2620#define BCE_MISC_USPLL_CTRL_TESTA_EN (1L<<23) 2621#define BCE_MISC_USPLL_CTRL_TESTA_SEL (0x3L<<24) 2622#define BCE_MISC_USPLL_CTRL_ATTEN_FREF (1L<<26) 2623#define BCE_MISC_USPLL_CTRL_DIGITAL_RST (1L<<27) 2624#define BCE_MISC_USPLL_CTRL_ANALOG_RST (1L<<28) 2625#define BCE_MISC_USPLL_CTRL_LOCK (1L<<29) 2626 2627#define BCE_MISC_PERR_STATUS0 0x00000944 2628#define BCE_MISC_PERR_STATUS0_COM_DMAE_PERR (1L<<0) 2629#define BCE_MISC_PERR_STATUS0_CP_DMAE_PERR (1L<<1) 2630#define BCE_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR (1L<<2) 2631#define BCE_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR (1L<<3) 2632#define BCE_MISC_PERR_STATUS0_CTX_PGTBL_PERR (1L<<4) 2633#define BCE_MISC_PERR_STATUS0_CTX_CACHE_PERR (1L<<5) 2634#define BCE_MISC_PERR_STATUS0_CTX_MIRROR_PERR (1L<<6) 2635#define BCE_MISC_PERR_STATUS0_COM_CTXC_PERR (1L<<7) 2636#define BCE_MISC_PERR_STATUS0_COM_SCPAD_PERR (1L<<8) 2637#define BCE_MISC_PERR_STATUS0_CP_CTXC_PERR (1L<<9) 2638#define BCE_MISC_PERR_STATUS0_CP_SCPAD_PERR (1L<<10) 2639#define BCE_MISC_PERR_STATUS0_RXP_RBUFC_PERR (1L<<11) 2640#define BCE_MISC_PERR_STATUS0_RXP_CTXC_PERR (1L<<12) 2641#define BCE_MISC_PERR_STATUS0_RXP_SCPAD_PERR (1L<<13) 2642#define BCE_MISC_PERR_STATUS0_TPAT_SCPAD_PERR (1L<<14) 2643#define BCE_MISC_PERR_STATUS0_TXP_CTXC_PERR (1L<<15) 2644#define BCE_MISC_PERR_STATUS0_TXP_SCPAD_PERR (1L<<16) 2645#define BCE_MISC_PERR_STATUS0_CS_TMEM_PERR (1L<<17) 2646#define BCE_MISC_PERR_STATUS0_MQ_CTX_PERR (1L<<18) 2647#define BCE_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR (1L<<19) 2648#define BCE_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR (1L<<20) 2649#define BCE_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR (1L<<21) 2650#define BCE_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR (1L<<22) 2651#define BCE_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR (1L<<23) 2652#define BCE_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR (1L<<24) 2653#define BCE_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR (1L<<25) 2654#define BCE_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR (1L<<26) 2655#define BCE_MISC_PERR_STATUS0_TPBUF_PERR (1L<<27) 2656#define BCE_MISC_PERR_STATUS0_THBUF_PERR (1L<<28) 2657#define BCE_MISC_PERR_STATUS0_TDMA_PERR (1L<<29) 2658#define BCE_MISC_PERR_STATUS0_TBDC_PERR (1L<<30) 2659#define BCE_MISC_PERR_STATUS0_TSCH_LR_PERR (1L<<31) 2660 2661#define BCE_MISC_PERR_STATUS1 0x00000948 2662#define BCE_MISC_PERR_STATUS1_RBDC_PERR (1L<<0) 2663#define BCE_MISC_PERR_STATUS1_RDMA_DFIFO_PERR (1L<<2) 2664#define BCE_MISC_PERR_STATUS1_HC_STATS_PERR (1L<<3) 2665#define BCE_MISC_PERR_STATUS1_HC_MSIX_PERR (1L<<4) 2666#define BCE_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR (1L<<5) 2667#define BCE_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR (1L<<6) 2668#define BCE_MISC_PERR_STATUS1_TPATQ_PERR (1L<<7) 2669#define BCE_MISC_PERR_STATUS1_MCPQ_PERR (1L<<8) 2670#define BCE_MISC_PERR_STATUS1_TDMAQ_PERR (1L<<9) 2671#define BCE_MISC_PERR_STATUS1_TXPQ_PERR (1L<<10) 2672#define BCE_MISC_PERR_STATUS1_COMTQ_PERR (1L<<11) 2673#define BCE_MISC_PERR_STATUS1_COMQ_PERR (1L<<12) 2674#define BCE_MISC_PERR_STATUS1_RLUPQ_PERR (1L<<13) 2675#define BCE_MISC_PERR_STATUS1_RXPQ_PERR (1L<<14) 2676#define BCE_MISC_PERR_STATUS1_RV2PPQ_PERR (1L<<15) 2677#define BCE_MISC_PERR_STATUS1_RDMAQ_PERR (1L<<16) 2678#define BCE_MISC_PERR_STATUS1_TASQ_PERR (1L<<17) 2679#define BCE_MISC_PERR_STATUS1_TBDRQ_PERR (1L<<18) 2680#define BCE_MISC_PERR_STATUS1_TSCHQ_PERR (1L<<19) 2681#define BCE_MISC_PERR_STATUS1_COMXQ_PERR (1L<<20) 2682#define BCE_MISC_PERR_STATUS1_RXPCQ_PERR (1L<<21) 2683#define BCE_MISC_PERR_STATUS1_RV2PTQ_PERR (1L<<22) 2684#define BCE_MISC_PERR_STATUS1_RV2PMQ_PERR (1L<<23) 2685#define BCE_MISC_PERR_STATUS1_CPQ_PERR (1L<<24) 2686#define BCE_MISC_PERR_STATUS1_CSQ_PERR (1L<<25) 2687#define BCE_MISC_PERR_STATUS1_RLUP_CID_PERR (1L<<26) 2688#define BCE_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR (1L<<27) 2689#define BCE_MISC_PERR_STATUS1_RV2PCSQ_PERR (1L<<28) 2690#define BCE_MISC_PERR_STATUS1_MQ_IDX_PERR (1L<<29) 2691 2692#define BCE_MISC_PERR_STATUS2 0x0000094c 2693#define BCE_MISC_PERR_STATUS2_TGT_FIFO_PERR (1L<<0) 2694#define BCE_MISC_PERR_STATUS2_UMP_TX_PERR (1L<<1) 2695#define BCE_MISC_PERR_STATUS2_UMP_RX_PERR (1L<<2) 2696#define BCE_MISC_PERR_STATUS2_MCP_ROM_PERR (1L<<3) 2697#define BCE_MISC_PERR_STATUS2_MCP_SCPAD_PERR (1L<<4) 2698#define BCE_MISC_PERR_STATUS2_HB_MEM_PERR (1L<<5) 2699#define BCE_MISC_PERR_STATUS2_PCIE_REPLAY_PERR (1L<<6) 2700 2701#define BCE_MISC_LCPLL_CTRL0 0x00000950 2702#define BCE_MISC_LCPLL_CTRL0_OAC (0x7L<<0) 2703#define BCE_MISC_LCPLL_CTRL0_OAC_NEGTWENTY (0L<<0) 2704#define BCE_MISC_LCPLL_CTRL0_OAC_ZERO (1L<<0) 2705#define BCE_MISC_LCPLL_CTRL0_OAC_TWENTY (3L<<0) 2706#define BCE_MISC_LCPLL_CTRL0_OAC_FORTY (7L<<0) 2707#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL (0x7L<<3) 2708#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_360 (0L<<3) 2709#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_480 (1L<<3) 2710#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_600 (3L<<3) 2711#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_720 (7L<<3) 2712#define BCE_MISC_LCPLL_CTRL0_BIAS_CTRL (0x3L<<6) 2713#define BCE_MISC_LCPLL_CTRL0_PLL_OBSERVE (0x7L<<8) 2714#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL (0x3L<<11) 2715#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_0 (0L<<11) 2716#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_1 (1L<<11) 2717#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_2 (2L<<11) 2718#define BCE_MISC_LCPLL_CTRL0_PLLSEQSTART (1L<<13) 2719#define BCE_MISC_LCPLL_CTRL0_RESERVED (1L<<14) 2720#define BCE_MISC_LCPLL_CTRL0_CAPRETRY_EN (1L<<15) 2721#define BCE_MISC_LCPLL_CTRL0_FREQMONITOR_EN (1L<<16) 2722#define BCE_MISC_LCPLL_CTRL0_FREQDETRESTART_EN (1L<<17) 2723#define BCE_MISC_LCPLL_CTRL0_FREQDETRETRY_EN (1L<<18) 2724#define BCE_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN (1L<<19) 2725#define BCE_MISC_LCPLL_CTRL0_PLLFORCEFDONE (1L<<20) 2726#define BCE_MISC_LCPLL_CTRL0_PLLFORCEFPASS (1L<<21) 2727#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN (1L<<22) 2728#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPDONE (1L<<23) 2729#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN (1L<<24) 2730#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPPASS (1L<<25) 2731#define BCE_MISC_LCPLL_CTRL0_CAPRESTART (1L<<26) 2732#define BCE_MISC_LCPLL_CTRL0_CAPSELECTM_EN (1L<<27) 2733 2734#define BCE_MISC_LCPLL_CTRL1 0x00000954 2735#define BCE_MISC_LCPLL_CTRL1_CAPSELECTM (0x1fL<<0) 2736#define BCE_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN (1L<<5) 2737#define BCE_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN (1L<<6) 2738#define BCE_MISC_LCPLL_CTRL1_SLOWDN_XOR (1L<<7) 2739 2740#define BCE_MISC_LCPLL_STATUS 0x00000958 2741#define BCE_MISC_LCPLL_STATUS_FREQDONE_SM (1L<<0) 2742#define BCE_MISC_LCPLL_STATUS_FREQPASS_SM (1L<<1) 2743#define BCE_MISC_LCPLL_STATUS_PLLSEQDONE (1L<<2) 2744#define BCE_MISC_LCPLL_STATUS_PLLSEQPASS (1L<<3) 2745#define BCE_MISC_LCPLL_STATUS_PLLSTATE (0x7L<<4) 2746#define BCE_MISC_LCPLL_STATUS_CAPSTATE (0x7L<<7) 2747#define BCE_MISC_LCPLL_STATUS_CAPSELECT (0x1fL<<10) 2748#define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR (1L<<15) 2749#define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0 (0L<<15) 2750#define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1 (1L<<15) 2751 2752#define BCE_MISC_OSCFUNDS_CTRL 0x0000095c 2753#define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON (1L<<5) 2754#define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF (0L<<5) 2755#define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON_ON (1L<<5) 2756#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM (0x3L<<6) 2757#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0 (0L<<6) 2758#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1 (1L<<6) 2759#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2 (2L<<6) 2760#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3 (3L<<6) 2761#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ (0x3L<<8) 2762#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0 (0L<<8) 2763#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1 (1L<<8) 2764#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2 (2L<<8) 2765#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3 (3L<<8) 2766#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ (0x3L<<10) 2767#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0 (0L<<10) 2768#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1 (1L<<10) 2769#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2 (2L<<10) 2770#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3 (3L<<10) 2771 2772/* 2773 * dma_reg definition 2774 * offset: 0xc00 2775 */ 2776#define BCE_DMA_COMMAND 0x00000c00 2777#define BCE_DMA_COMMAND_ENABLE (1L<<0) 2778 2779#define BCE_DMA_STATUS 0x00000c04 2780#define BCE_DMA_STATUS_PAR_ERROR_STATE (1L<<0) 2781#define BCE_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16) 2782#define BCE_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17) 2783#define BCE_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18) 2784#define BCE_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19) 2785#define BCE_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20) 2786#define BCE_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21) 2787#define BCE_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22) 2788#define BCE_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23) 2789#define BCE_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24) 2790#define BCE_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25) 2791 2792#define BCE_DMA_CONFIG 0x00000c08 2793#define BCE_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0) 2794#define BCE_DMA_CONFIG_DATA_WORD_SWAP (1L<<1) 2795#define BCE_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4) 2796#define BCE_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5) 2797#define BCE_DMA_CONFIG_ONE_DMA (1L<<6) 2798#define BCE_DMA_CONFIG_CNTL_TWO_DMA (1L<<7) 2799#define BCE_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8) 2800#define BCE_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10) 2801#define BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11) 2802#define BCE_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12) 2803#define BCE_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16) 2804#define BCE_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20) 2805#define BCE_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23) 2806#define BCE_DMA_CONFIG_BIG_SIZE (0xfL<<24) 2807#define BCE_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24) 2808#define BCE_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24) 2809#define BCE_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24) 2810#define BCE_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24) 2811#define BCE_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24) 2812 2813#define BCE_DMA_BLACKOUT 0x00000c0c 2814#define BCE_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0) 2815#define BCE_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8) 2816#define BCE_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16) 2817 2818#define BCE_DMA_RCHAN_STAT 0x00000c30 2819#define BCE_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0) 2820#define BCE_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3) 2821#define BCE_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4) 2822#define BCE_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7) 2823#define BCE_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8) 2824#define BCE_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11) 2825#define BCE_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12) 2826#define BCE_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15) 2827#define BCE_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16) 2828#define BCE_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19) 2829#define BCE_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20) 2830#define BCE_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23) 2831#define BCE_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24) 2832#define BCE_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27) 2833#define BCE_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28) 2834#define BCE_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31) 2835 2836#define BCE_DMA_WCHAN_STAT 0x00000c34 2837#define BCE_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0) 2838#define BCE_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3) 2839#define BCE_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4) 2840#define BCE_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7) 2841#define BCE_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8) 2842#define BCE_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11) 2843#define BCE_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12) 2844#define BCE_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15) 2845#define BCE_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16) 2846#define BCE_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19) 2847#define BCE_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20) 2848#define BCE_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23) 2849#define BCE_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24) 2850#define BCE_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27) 2851#define BCE_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28) 2852#define BCE_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31) 2853 2854#define BCE_DMA_RCHAN_ASSIGNMENT 0x00000c38 2855#define BCE_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0) 2856#define BCE_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4) 2857#define BCE_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8) 2858#define BCE_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12) 2859#define BCE_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16) 2860#define BCE_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20) 2861#define BCE_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24) 2862#define BCE_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28) 2863 2864#define BCE_DMA_WCHAN_ASSIGNMENT 0x00000c3c 2865#define BCE_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0) 2866#define BCE_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4) 2867#define BCE_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8) 2868#define BCE_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12) 2869#define BCE_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16) 2870#define BCE_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20) 2871#define BCE_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24) 2872#define BCE_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28) 2873 2874#define BCE_DMA_RCHAN_STAT_00 0x00000c40 2875#define BCE_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 2876 2877#define BCE_DMA_RCHAN_STAT_01 0x00000c44 2878#define BCE_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 2879 2880#define BCE_DMA_RCHAN_STAT_02 0x00000c48 2881#define BCE_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0) 2882#define BCE_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16) 2883#define BCE_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17) 2884#define BCE_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18) 2885 2886#define BCE_DMA_RCHAN_STAT_10 0x00000c4c 2887#define BCE_DMA_RCHAN_STAT_11 0x00000c50 2888#define BCE_DMA_RCHAN_STAT_12 0x00000c54 2889#define BCE_DMA_RCHAN_STAT_20 0x00000c58 2890#define BCE_DMA_RCHAN_STAT_21 0x00000c5c 2891#define BCE_DMA_RCHAN_STAT_22 0x00000c60 2892#define BCE_DMA_RCHAN_STAT_30 0x00000c64 2893#define BCE_DMA_RCHAN_STAT_31 0x00000c68 2894#define BCE_DMA_RCHAN_STAT_32 0x00000c6c 2895#define BCE_DMA_RCHAN_STAT_40 0x00000c70 2896#define BCE_DMA_RCHAN_STAT_41 0x00000c74 2897#define BCE_DMA_RCHAN_STAT_42 0x00000c78 2898#define BCE_DMA_RCHAN_STAT_50 0x00000c7c 2899#define BCE_DMA_RCHAN_STAT_51 0x00000c80 2900#define BCE_DMA_RCHAN_STAT_52 0x00000c84 2901#define BCE_DMA_RCHAN_STAT_60 0x00000c88 2902#define BCE_DMA_RCHAN_STAT_61 0x00000c8c 2903#define BCE_DMA_RCHAN_STAT_62 0x00000c90 2904#define BCE_DMA_RCHAN_STAT_70 0x00000c94 2905#define BCE_DMA_RCHAN_STAT_71 0x00000c98 2906#define BCE_DMA_RCHAN_STAT_72 0x00000c9c 2907#define BCE_DMA_WCHAN_STAT_00 0x00000ca0 2908#define BCE_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 2909 2910#define BCE_DMA_WCHAN_STAT_01 0x00000ca4 2911#define BCE_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 2912 2913#define BCE_DMA_WCHAN_STAT_02 0x00000ca8 2914#define BCE_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0) 2915#define BCE_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16) 2916#define BCE_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17) 2917#define BCE_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18) 2918 2919#define BCE_DMA_WCHAN_STAT_10 0x00000cac 2920#define BCE_DMA_WCHAN_STAT_11 0x00000cb0 2921#define BCE_DMA_WCHAN_STAT_12 0x00000cb4 2922#define BCE_DMA_WCHAN_STAT_20 0x00000cb8 2923#define BCE_DMA_WCHAN_STAT_21 0x00000cbc 2924#define BCE_DMA_WCHAN_STAT_22 0x00000cc0 2925#define BCE_DMA_WCHAN_STAT_30 0x00000cc4 2926#define BCE_DMA_WCHAN_STAT_31 0x00000cc8 2927#define BCE_DMA_WCHAN_STAT_32 0x00000ccc 2928#define BCE_DMA_WCHAN_STAT_40 0x00000cd0 2929#define BCE_DMA_WCHAN_STAT_41 0x00000cd4 2930#define BCE_DMA_WCHAN_STAT_42 0x00000cd8 2931#define BCE_DMA_WCHAN_STAT_50 0x00000cdc 2932#define BCE_DMA_WCHAN_STAT_51 0x00000ce0 2933#define BCE_DMA_WCHAN_STAT_52 0x00000ce4 2934#define BCE_DMA_WCHAN_STAT_60 0x00000ce8 2935#define BCE_DMA_WCHAN_STAT_61 0x00000cec 2936#define BCE_DMA_WCHAN_STAT_62 0x00000cf0 2937#define BCE_DMA_WCHAN_STAT_70 0x00000cf4 2938#define BCE_DMA_WCHAN_STAT_71 0x00000cf8 2939#define BCE_DMA_WCHAN_STAT_72 0x00000cfc 2940#define BCE_DMA_ARB_STAT_00 0x00000d00 2941#define BCE_DMA_ARB_STAT_00_MASTER (0xffffL<<0) 2942#define BCE_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16) 2943#define BCE_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24) 2944 2945#define BCE_DMA_ARB_STAT_01 0x00000d04 2946#define BCE_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0) 2947#define BCE_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4) 2948#define BCE_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8) 2949#define BCE_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12) 2950#define BCE_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16) 2951#define BCE_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20) 2952#define BCE_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24) 2953#define BCE_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28) 2954 2955#define BCE_DMA_FUSE_CTRL0_CMD 0x00000f00 2956#define BCE_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0) 2957#define BCE_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1) 2958#define BCE_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2) 2959#define BCE_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3) 2960#define BCE_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8) 2961 2962#define BCE_DMA_FUSE_CTRL0_DATA 0x00000f04 2963#define BCE_DMA_FUSE_CTRL1_CMD 0x00000f08 2964#define BCE_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0) 2965#define BCE_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1) 2966#define BCE_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2) 2967#define BCE_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3) 2968#define BCE_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8) 2969 2970#define BCE_DMA_FUSE_CTRL1_DATA 0x00000f0c 2971#define BCE_DMA_FUSE_CTRL2_CMD 0x00000f10 2972#define BCE_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0) 2973#define BCE_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1) 2974#define BCE_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2) 2975#define BCE_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3) 2976#define BCE_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8) 2977 2978#define BCE_DMA_FUSE_CTRL2_DATA 0x00000f14 2979 2980/* 2981 * context_reg definition 2982 * offset: 0x1000 2983 */ 2984#define BCE_CTX_COMMAND 0x00001000 2985#define BCE_CTX_COMMAND_ENABLED (1L<<0) 2986#define BCE_CTX_COMMAND_DISABLE_USAGE_CNT (1L<<1) 2987#define BCE_CTX_COMMAND_DISABLE_PLRU (1L<<2) 2988#define BCE_CTX_COMMAND_DISABLE_COMBINE_READ (1L<<3) 2989#define BCE_CTX_COMMAND_FLUSH_AHEAD (0x1fL<<8) 2990#define BCE_CTX_COMMAND_MEM_INIT (1L<<13) 2991#define BCE_CTX_COMMAND_PAGE_SIZE (0xfL<<16) 2992#define BCE_CTX_COMMAND_PAGE_SIZE_256 (0L<<16) 2993#define BCE_CTX_COMMAND_PAGE_SIZE_512 (1L<<16) 2994#define BCE_CTX_COMMAND_PAGE_SIZE_1K (2L<<16) 2995#define BCE_CTX_COMMAND_PAGE_SIZE_2K (3L<<16) 2996#define BCE_CTX_COMMAND_PAGE_SIZE_4K (4L<<16) 2997#define BCE_CTX_COMMAND_PAGE_SIZE_8K (5L<<16) 2998#define BCE_CTX_COMMAND_PAGE_SIZE_16K (6L<<16) 2999#define BCE_CTX_COMMAND_PAGE_SIZE_32K (7L<<16) 3000#define BCE_CTX_COMMAND_PAGE_SIZE_64K (8L<<16) 3001#define BCE_CTX_COMMAND_PAGE_SIZE_128K (9L<<16) 3002#define BCE_CTX_COMMAND_PAGE_SIZE_256K (10L<<16) 3003#define BCE_CTX_COMMAND_PAGE_SIZE_512K (11L<<16) 3004#define BCE_CTX_COMMAND_PAGE_SIZE_1M (12L<<16) 3005 3006#define BCE_CTX_STATUS 0x00001004 3007#define BCE_CTX_STATUS_LOCK_WAIT (1L<<0) 3008#define BCE_CTX_STATUS_READ_STAT (1L<<16) 3009#define BCE_CTX_STATUS_WRITE_STAT (1L<<17) 3010#define BCE_CTX_STATUS_ACC_STALL_STAT (1L<<18) 3011#define BCE_CTX_STATUS_LOCK_STALL_STAT (1L<<19) 3012#define BCE_CTX_STATUS_EXT_READ_STAT (1L<<20) 3013#define BCE_CTX_STATUS_EXT_WRITE_STAT (1L<<21) 3014#define BCE_CTX_STATUS_MISS_STAT (1L<<22) 3015#define BCE_CTX_STATUS_HIT_STAT (1L<<23) 3016#define BCE_CTX_STATUS_DEAD_LOCK (1L<<24) 3017#define BCE_CTX_STATUS_USAGE_CNT_ERR (1L<<25) 3018#define BCE_CTX_STATUS_INVALID_PAGE (1L<<26) 3019 3020#define BCE_CTX_VIRT_ADDR 0x00001008 3021#define BCE_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6) 3022 3023#define BCE_CTX_PAGE_TBL 0x0000100c 3024#define BCE_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6) 3025 3026#define BCE_CTX_DATA_ADR 0x00001010 3027#define BCE_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2) 3028 3029#define BCE_CTX_DATA 0x00001014 3030#define BCE_CTX_LOCK 0x00001018 3031#define BCE_CTX_LOCK_TYPE (0x7L<<0) 3032#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0) 3033#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0) 3034#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0) 3035#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0) 3036#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0) 3037#define BCE_CTX_LOCK_TYPE_VOID_XI (0L<<0) 3038#define BCE_CTX_LOCK_TYPE_PROTOCOL_XI (1L<<0) 3039#define BCE_CTX_LOCK_TYPE_TX_XI (2L<<0) 3040#define BCE_CTX_LOCK_TYPE_TIMER_XI (4L<<0) 3041#define BCE_CTX_LOCK_TYPE_COMPLETE_XI (7L<<0) 3042#define BCE_CTX_LOCK_CID_VALUE (0x3fffL<<7) 3043#define BCE_CTX_LOCK_GRANTED (1L<<26) 3044#define BCE_CTX_LOCK_MODE (0x7L<<27) 3045#define BCE_CTX_LOCK_MODE_UNLOCK (0x0L<<27) 3046#define BCE_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27) 3047#define BCE_CTX_LOCK_MODE_SURE (0x2L<<27) 3048#define BCE_CTX_LOCK_STATUS (1L<<30) 3049#define BCE_CTX_LOCK_REQ (1L<<31) 3050 3051#define BCE_CTX_CTX_CTRL 0x0000101c 3052#define BCE_CTX_CTX_CTRL_CTX_ADDR (0x7ffffL<<2) 3053#define BCE_CTX_CTX_CTRL_MOD_USAGE_CNT (0x3L<<21) 3054#define BCE_CTX_CTX_CTRL_NO_RAM_ACC (1L<<23) 3055#define BCE_CTX_CTX_CTRL_PREFETCH_SIZE (0x3L<<24) 3056#define BCE_CTX_CTX_CTRL_ATTR (1L<<26) 3057#define BCE_CTX_CTX_CTRL_WRITE_REQ (1L<<30) 3058#define BCE_CTX_CTX_CTRL_READ_REQ (1L<<31) 3059 3060#define BCE_CTX_CTX_DATA 0x00001020 3061#define BCE_CTX_ACCESS_STATUS 0x00001040 3062#define BCE_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0) 3063#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10) 3064#define BCE_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12) 3065#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14) 3066#define BCE_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17) 3067#define BCE_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI (0x1fL<<0) 3068#define BCE_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI (0x1fL<<5) 3069#define BCE_CTX_ACCESS_STATUS_REQUEST_XI (0x3fffffL<<10) 3070 3071#define BCE_CTX_DBG_LOCK_STATUS 0x00001044 3072#define BCE_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0) 3073#define BCE_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22) 3074 3075#define BCE_CTX_CACHE_CTRL_STATUS 0x00001048 3076#define BCE_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW (1L<<0) 3077#define BCE_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP (1L<<1) 3078#define BCE_CTX_CACHE_CTRL_STATUS_FLUSH_START (1L<<6) 3079#define BCE_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT (0x3fL<<7) 3080#define BCE_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED (0x3fL<<13) 3081#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE (1L<<19) 3082#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE (1L<<20) 3083#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE (1L<<21) 3084#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE (1L<<22) 3085#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE (1L<<23) 3086#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE (1L<<24) 3087#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE (1L<<25) 3088#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE (1L<<26) 3089#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE (1L<<27) 3090#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE (1L<<28) 3091#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE (1L<<29) 3092 3093#define BCE_CTX_CACHE_CTRL_SM_STATUS 0x0000104c 3094#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_DWC (0x7L<<0) 3095#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC (0x7L<<3) 3096#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC (0x7L<<6) 3097#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC (0x7L<<9) 3098#define BCE_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR (0x7fffL<<16) 3099 3100#define BCE_CTX_CACHE_STATUS 0x00001050 3101#define BCE_CTX_CACHE_STATUS_HELD_ENTRIES (0x3ffL<<0) 3102#define BCE_CTX_CACHE_STATUS_MAX_HELD_ENTRIES (0x3ffL<<16) 3103 3104#define BCE_CTX_DMA_STATUS 0x00001054 3105#define BCE_CTX_DMA_STATUS_RD_CHAN0_STATUS (0x3L<<0) 3106#define BCE_CTX_DMA_STATUS_RD_CHAN1_STATUS (0x3L<<2) 3107#define BCE_CTX_DMA_STATUS_RD_CHAN2_STATUS (0x3L<<4) 3108#define BCE_CTX_DMA_STATUS_RD_CHAN3_STATUS (0x3L<<6) 3109#define BCE_CTX_DMA_STATUS_RD_CHAN4_STATUS (0x3L<<8) 3110#define BCE_CTX_DMA_STATUS_RD_CHAN5_STATUS (0x3L<<10) 3111#define BCE_CTX_DMA_STATUS_RD_CHAN6_STATUS (0x3L<<12) 3112#define BCE_CTX_DMA_STATUS_RD_CHAN7_STATUS (0x3L<<14) 3113#define BCE_CTX_DMA_STATUS_RD_CHAN8_STATUS (0x3L<<16) 3114#define BCE_CTX_DMA_STATUS_RD_CHAN9_STATUS (0x3L<<18) 3115#define BCE_CTX_DMA_STATUS_RD_CHAN10_STATUS (0x3L<<20) 3116 3117#define BCE_CTX_REP_STATUS 0x00001058 3118#define BCE_CTX_REP_STATUS_ERROR_ENTRY (0x3ffL<<0) 3119#define BCE_CTX_REP_STATUS_ERROR_CLIENT_ID (0x1fL<<10) 3120#define BCE_CTX_REP_STATUS_USAGE_CNT_MAX_ERR (1L<<16) 3121#define BCE_CTX_REP_STATUS_USAGE_CNT_MIN_ERR (1L<<17) 3122#define BCE_CTX_REP_STATUS_USAGE_CNT_MISS_ERR (1L<<18) 3123 3124#define BCE_CTX_CKSUM_ERROR_STATUS 0x0000105c 3125#define BCE_CTX_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0) 3126#define BCE_CTX_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16) 3127 3128#define BCE_CTX_CHNL_LOCK_STATUS_0 0x00001080 3129#define BCE_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0) 3130#define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14) 3131#define BCE_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16) 3132#define BCE_CTX_CHNL_LOCK_STATUS_0_MODE_XI (1L<<14) 3133#define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE_XI (0x7L<<15) 3134 3135#define BCE_CTX_CHNL_LOCK_STATUS_1 0x00001084 3136#define BCE_CTX_CHNL_LOCK_STATUS_2 0x00001088 3137#define BCE_CTX_CHNL_LOCK_STATUS_3 0x0000108c 3138#define BCE_CTX_CHNL_LOCK_STATUS_4 0x00001090 3139#define BCE_CTX_CHNL_LOCK_STATUS_5 0x00001094 3140#define BCE_CTX_CHNL_LOCK_STATUS_6 0x00001098 3141#define BCE_CTX_CHNL_LOCK_STATUS_7 0x0000109c 3142#define BCE_CTX_CHNL_LOCK_STATUS_8 0x000010a0 3143#define BCE_CTX_CHNL_LOCK_STATUS_9 0x000010a4 3144 3145#define BCE_CTX_CACHE_DATA 0x000010c4 3146#define BCE_CTX_HOST_PAGE_TBL_CTRL 0x000010c8 3147#define BCE_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR (0x1ffL<<0) 3148#define BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ (1L<<30) 3149#define BCE_CTX_HOST_PAGE_TBL_CTRL_READ_REQ (1L<<31) 3150 3151#define BCE_CTX_HOST_PAGE_TBL_DATA0 0x000010cc 3152#define BCE_CTX_HOST_PAGE_TBL_DATA0_VALID (1L<<0) 3153#define BCE_CTX_HOST_PAGE_TBL_DATA0_VALUE (0xffffffL<<8) 3154 3155#define BCE_CTX_HOST_PAGE_TBL_DATA1 0x000010d0 3156#define BCE_CTX_CAM_CTRL 0x000010d4 3157#define BCE_CTX_CAM_CTRL_CAM_ADDR (0x3ffL<<0) 3158#define BCE_CTX_CAM_CTRL_RESET (1L<<27) 3159#define BCE_CTX_CAM_CTRL_INVALIDATE (1L<<28) 3160#define BCE_CTX_CAM_CTRL_SEARCH (1L<<29) 3161#define BCE_CTX_CAM_CTRL_WRITE_REQ (1L<<30) 3162#define BCE_CTX_CAM_CTRL_READ_REQ (1L<<31) 3163 3164/* 3165 * emac_reg definition 3166 * offset: 0x1400 3167 */ 3168#define BCE_EMAC_MODE 0x00001400 3169#define BCE_EMAC_MODE_RESET (1L<<0) 3170#define BCE_EMAC_MODE_HALF_DUPLEX (1L<<1) 3171#define BCE_EMAC_MODE_PORT (0x3L<<2) 3172#define BCE_EMAC_MODE_PORT_NONE (0L<<2) 3173#define BCE_EMAC_MODE_PORT_MII (1L<<2) 3174#define BCE_EMAC_MODE_PORT_GMII (2L<<2) 3175#define BCE_EMAC_MODE_PORT_MII_10 (3L<<2) 3176#define BCE_EMAC_MODE_MAC_LOOP (1L<<4) 3177#define BCE_EMAC_MODE_25G (1L<<5) 3178#define BCE_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) 3179#define BCE_EMAC_MODE_TX_BURST (1L<<8) 3180#define BCE_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) 3181#define BCE_EMAC_MODE_EXT_LINK_POL (1L<<10) 3182#define BCE_EMAC_MODE_FORCE_LINK (1L<<11) 3183#define BCE_EMAC_MODE_MPKT (1L<<18) 3184#define BCE_EMAC_MODE_MPKT_RCVD (1L<<19) 3185#define BCE_EMAC_MODE_ACPI_RCVD (1L<<20) 3186 3187#define BCE_EMAC_STATUS 0x00001404 3188#define BCE_EMAC_STATUS_LINK (1L<<11) 3189#define BCE_EMAC_STATUS_LINK_CHANGE (1L<<12) 3190#define BCE_EMAC_STATUS_MI_COMPLETE (1L<<22) 3191#define BCE_EMAC_STATUS_MI_INT (1L<<23) 3192#define BCE_EMAC_STATUS_AP_ERROR (1L<<24) 3193#define BCE_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31) 3194 3195#define BCE_EMAC_ATTENTION_ENA 0x00001408 3196#define BCE_EMAC_ATTENTION_ENA_LINK (1L<<11) 3197#define BCE_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22) 3198#define BCE_EMAC_ATTENTION_ENA_MI_INT (1L<<23) 3199#define BCE_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24) 3200 3201#define BCE_EMAC_LED 0x0000140c 3202#define BCE_EMAC_LED_OVERRIDE (1L<<0) 3203#define BCE_EMAC_LED_1000MB_OVERRIDE (1L<<1) 3204#define BCE_EMAC_LED_100MB_OVERRIDE (1L<<2) 3205#define BCE_EMAC_LED_10MB_OVERRIDE (1L<<3) 3206#define BCE_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4) 3207#define BCE_EMAC_LED_BLNK_TRAFFIC (1L<<5) 3208#define BCE_EMAC_LED_TRAFFIC (1L<<6) 3209#define BCE_EMAC_LED_1000MB (1L<<7) 3210#define BCE_EMAC_LED_100MB (1L<<8) 3211#define BCE_EMAC_LED_10MB (1L<<9) 3212#define BCE_EMAC_LED_TRAFFIC_STAT (1L<<10) 3213#define BCE_EMAC_LED_BLNK_RATE (0xfffL<<19) 3214#define BCE_EMAC_LED_BLNK_RATE_ENA (1L<<31) 3215 3216#define BCE_EMAC_MAC_MATCH0 0x00001410 3217#define BCE_EMAC_MAC_MATCH1 0x00001414 3218#define BCE_EMAC_MAC_MATCH2 0x00001418 3219#define BCE_EMAC_MAC_MATCH3 0x0000141c 3220#define BCE_EMAC_MAC_MATCH4 0x00001420 3221#define BCE_EMAC_MAC_MATCH5 0x00001424 3222#define BCE_EMAC_MAC_MATCH6 0x00001428 3223#define BCE_EMAC_MAC_MATCH7 0x0000142c 3224#define BCE_EMAC_MAC_MATCH8 0x00001430 3225#define BCE_EMAC_MAC_MATCH9 0x00001434 3226#define BCE_EMAC_MAC_MATCH10 0x00001438 3227#define BCE_EMAC_MAC_MATCH11 0x0000143c 3228#define BCE_EMAC_MAC_MATCH12 0x00001440 3229#define BCE_EMAC_MAC_MATCH13 0x00001444 3230#define BCE_EMAC_MAC_MATCH14 0x00001448 3231#define BCE_EMAC_MAC_MATCH15 0x0000144c 3232#define BCE_EMAC_MAC_MATCH16 0x00001450 3233#define BCE_EMAC_MAC_MATCH17 0x00001454 3234#define BCE_EMAC_MAC_MATCH18 0x00001458 3235#define BCE_EMAC_MAC_MATCH19 0x0000145c 3236#define BCE_EMAC_MAC_MATCH20 0x00001460 3237#define BCE_EMAC_MAC_MATCH21 0x00001464 3238#define BCE_EMAC_MAC_MATCH22 0x00001468 3239#define BCE_EMAC_MAC_MATCH23 0x0000146c 3240#define BCE_EMAC_MAC_MATCH24 0x00001470 3241#define BCE_EMAC_MAC_MATCH25 0x00001474 3242#define BCE_EMAC_MAC_MATCH26 0x00001478 3243#define BCE_EMAC_MAC_MATCH27 0x0000147c 3244#define BCE_EMAC_MAC_MATCH28 0x00001480 3245#define BCE_EMAC_MAC_MATCH29 0x00001484 3246#define BCE_EMAC_MAC_MATCH30 0x00001488 3247#define BCE_EMAC_MAC_MATCH31 0x0000148c 3248#define BCE_EMAC_BACKOFF_SEED 0x00001498 3249#define BCE_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0) 3250 3251#define BCE_EMAC_RX_MTU_SIZE 0x0000149c 3252#define BCE_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0) 3253#define BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 3254 3255#define BCE_EMAC_SERDES_CNTL 0x000014a4 3256#define BCE_EMAC_SERDES_CNTL_RXR (0x7L<<0) 3257#define BCE_EMAC_SERDES_CNTL_RXG (0x3L<<3) 3258#define BCE_EMAC_SERDES_CNTL_RXCKSEL (1L<<6) 3259#define BCE_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7) 3260#define BCE_EMAC_SERDES_CNTL_BGMAX (1L<<10) 3261#define BCE_EMAC_SERDES_CNTL_BGMIN (1L<<11) 3262#define BCE_EMAC_SERDES_CNTL_TXMODE (1L<<12) 3263#define BCE_EMAC_SERDES_CNTL_TXEDGE (1L<<13) 3264#define BCE_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14) 3265#define BCE_EMAC_SERDES_CNTL_PLLTEST (1L<<15) 3266#define BCE_EMAC_SERDES_CNTL_CDET_EN (1L<<16) 3267#define BCE_EMAC_SERDES_CNTL_TBI_LBK (1L<<17) 3268#define BCE_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18) 3269#define BCE_EMAC_SERDES_CNTL_REV_PHASE (1L<<19) 3270#define BCE_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20) 3271#define BCE_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22) 3272 3273#define BCE_EMAC_SERDES_STATUS 0x000014a8 3274#define BCE_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0) 3275#define BCE_EMAC_SERDES_STATUS_COMMA_DET (1L<<8) 3276 3277#define BCE_EMAC_MDIO_COMM 0x000014ac 3278#define BCE_EMAC_MDIO_COMM_DATA (0xffffL<<0) 3279#define BCE_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16) 3280#define BCE_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) 3281#define BCE_EMAC_MDIO_COMM_COMMAND (0x3L<<26) 3282#define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26) 3283#define BCE_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26) 3284#define BCE_EMAC_MDIO_COMM_COMMAND_READ (2L<<26) 3285#define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26) 3286#define BCE_EMAC_MDIO_COMM_FAIL (1L<<28) 3287#define BCE_EMAC_MDIO_COMM_START_BUSY (1L<<29) 3288#define BCE_EMAC_MDIO_COMM_DISEXT (1L<<30) 3289 3290#define BCE_EMAC_MDIO_STATUS 0x000014b0 3291#define BCE_EMAC_MDIO_STATUS_LINK (1L<<0) 3292#define BCE_EMAC_MDIO_STATUS_10MB (1L<<1) 3293 3294#define BCE_EMAC_MDIO_MODE 0x000014b4 3295#define BCE_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1) 3296#define BCE_EMAC_MDIO_MODE_AUTO_POLL (1L<<4) 3297#define BCE_EMAC_MDIO_MODE_BIT_BANG (1L<<8) 3298#define BCE_EMAC_MDIO_MODE_MDIO (1L<<9) 3299#define BCE_EMAC_MDIO_MODE_MDIO_OE (1L<<10) 3300#define BCE_EMAC_MDIO_MODE_MDC (1L<<11) 3301#define BCE_EMAC_MDIO_MODE_MDINT (1L<<12) 3302#define BCE_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16) 3303 3304#define BCE_EMAC_MDIO_AUTO_STATUS 0x000014b8 3305#define BCE_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0) 3306 3307#define BCE_EMAC_TX_MODE 0x000014bc 3308#define BCE_EMAC_TX_MODE_RESET (1L<<0) 3309#define BCE_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 3310#define BCE_EMAC_TX_MODE_FLOW_EN (1L<<4) 3311#define BCE_EMAC_TX_MODE_BIG_BACKOFF (1L<<5) 3312#define BCE_EMAC_TX_MODE_LONG_PAUSE (1L<<6) 3313#define BCE_EMAC_TX_MODE_LINK_AWARE (1L<<7) 3314 3315#define BCE_EMAC_TX_STATUS 0x000014c0 3316#define BCE_EMAC_TX_STATUS_XOFFED (1L<<0) 3317#define BCE_EMAC_TX_STATUS_XOFF_SENT (1L<<1) 3318#define BCE_EMAC_TX_STATUS_XON_SENT (1L<<2) 3319#define BCE_EMAC_TX_STATUS_LINK_UP (1L<<3) 3320#define BCE_EMAC_TX_STATUS_UNDERRUN (1L<<4) 3321 3322#define BCE_EMAC_TX_LENGTHS 0x000014c4 3323#define BCE_EMAC_TX_LENGTHS_SLOT (0xffL<<0) 3324#define BCE_EMAC_TX_LENGTHS_IPG (0xfL<<8) 3325#define BCE_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12) 3326 3327#define BCE_EMAC_RX_MODE 0x000014c8 3328#define BCE_EMAC_RX_MODE_RESET (1L<<0) 3329#define BCE_EMAC_RX_MODE_FLOW_EN (1L<<2) 3330#define BCE_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) 3331#define BCE_EMAC_RX_MODE_KEEP_PAUSE (1L<<4) 3332#define BCE_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5) 3333#define BCE_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6) 3334#define BCE_EMAC_RX_MODE_LLC_CHK (1L<<7) 3335#define BCE_EMAC_RX_MODE_PROMISCUOUS (1L<<8) 3336#define BCE_EMAC_RX_MODE_NO_CRC_CHK (1L<<9) 3337#define BCE_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) 3338#define BCE_EMAC_RX_MODE_FILT_BROADCAST (1L<<11) 3339#define BCE_EMAC_RX_MODE_SORT_MODE (1L<<12) 3340 3341#define BCE_EMAC_RX_STATUS 0x000014cc 3342#define BCE_EMAC_RX_STATUS_FFED (1L<<0) 3343#define BCE_EMAC_RX_STATUS_FF_RECEIVED (1L<<1) 3344#define BCE_EMAC_RX_STATUS_N_RECEIVED (1L<<2) 3345 3346#define BCE_EMAC_MULTICAST_HASH0 0x000014d0 3347#define BCE_EMAC_MULTICAST_HASH1 0x000014d4 3348#define BCE_EMAC_MULTICAST_HASH2 0x000014d8 3349#define BCE_EMAC_MULTICAST_HASH3 0x000014dc 3350#define BCE_EMAC_MULTICAST_HASH4 0x000014e0 3351#define BCE_EMAC_MULTICAST_HASH5 0x000014e4 3352#define BCE_EMAC_MULTICAST_HASH6 0x000014e8 3353#define BCE_EMAC_MULTICAST_HASH7 0x000014ec 3354#define BCE_EMAC_RX_STAT_IFHCINOCTETS 0x00001500 3355#define BCE_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504 3356#define BCE_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508 3357#define BCE_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c 3358#define BCE_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510 3359#define BCE_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514 3360#define BCE_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518 3361#define BCE_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c 3362#define BCE_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520 3363#define BCE_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524 3364#define BCE_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528 3365#define BCE_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c 3366#define BCE_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530 3367#define BCE_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534 3368#define BCE_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538 3369#define BCE_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c 3370#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540 3371#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544 3372#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548 3373#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c 3374#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550 3375#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554 3376#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558 3377#define BCE_EMAC_RXMAC_DEBUG0 0x0000155c 3378#define BCE_EMAC_RXMAC_DEBUG1 0x00001560 3379#define BCE_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0) 3380#define BCE_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1) 3381#define BCE_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2) 3382#define BCE_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3) 3383#define BCE_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4) 3384#define BCE_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5) 3385#define BCE_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6) 3386#define BCE_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7) 3387#define BCE_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23) 3388 3389#define BCE_EMAC_RXMAC_DEBUG2 0x00001564 3390#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0) 3391#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0) 3392#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0) 3393#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0) 3394#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0) 3395#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0) 3396#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0) 3397#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0) 3398#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0) 3399#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3) 3400#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3) 3401#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3) 3402#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3) 3403#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3) 3404#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3) 3405#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3) 3406#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3) 3407#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3) 3408#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3) 3409#define BCE_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7) 3410#define BCE_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15) 3411#define BCE_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16) 3412#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18) 3413#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18) 3414#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18) 3415#define BCE_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19) 3416#define BCE_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23) 3417 3418#define BCE_EMAC_RXMAC_DEBUG3 0x00001568 3419#define BCE_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0) 3420#define BCE_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16) 3421 3422#define BCE_EMAC_RXMAC_DEBUG4 0x0000156c 3423#define BCE_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0) 3424#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16) 3425#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16) 3426#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16) 3427#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16) 3428#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16) 3429#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16) 3430#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16) 3431#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16) 3432#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16) 3433#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16) 3434#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16) 3435#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16) 3436#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16) 3437#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16) 3438#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16) 3439#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16) 3440#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16) 3441#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16) 3442#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16) 3443#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16) 3444#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16) 3445#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16) 3446#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16) 3447#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16) 3448#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16) 3449#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16) 3450#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16) 3451#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16) 3452#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16) 3453#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16) 3454#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16) 3455#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16) 3456#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16) 3457#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16) 3458#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16) 3459#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16) 3460#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16) 3461#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16) 3462#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16) 3463#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16) 3464#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16) 3465#define BCE_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22) 3466#define BCE_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23) 3467#define BCE_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24) 3468#define BCE_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25) 3469#define BCE_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26) 3470#define BCE_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27) 3471#define BCE_EMAC_RXMAC_DEBUG4_START (1L<<28) 3472 3473#define BCE_EMAC_RXMAC_DEBUG5 0x00001570 3474#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0) 3475#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0) 3476#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0) 3477#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0) 3478#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0) 3479#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0) 3480#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0) 3481#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0) 3482#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4) 3483#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4) 3484#define