1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice unmodified, this list of conditions, and the following
12 *    disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30/* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD$");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/bus.h>
38#include <sys/endian.h>
39#include <sys/kernel.h>
40#include <sys/malloc.h>
41#include <sys/mbuf.h>
42#include <sys/rman.h>
43#include <sys/module.h>
44#include <sys/queue.h>
45#include <sys/socket.h>
46#include <sys/sockio.h>
47#include <sys/sysctl.h>
48#include <sys/taskqueue.h>
49
50#include <net/bpf.h>
51#include <net/if.h>
52#include <net/if_var.h>
53#include <net/if_arp.h>
54#include <net/ethernet.h>
55#include <net/if_dl.h>
56#include <net/if_media.h>
57#include <net/if_types.h>
58#include <net/if_vlan_var.h>
59
60#include <netinet/in.h>
61#include <netinet/in_systm.h>
62#include <netinet/ip.h>
63#include <netinet/tcp.h>
64
65#include <dev/mii/mii.h>
66#include <dev/mii/miivar.h>
67
68#include <dev/pci/pcireg.h>
69#include <dev/pci/pcivar.h>
70
71#include <machine/bus.h>
72#include <machine/in_cksum.h>
73
74#include <dev/age/if_agereg.h>
75#include <dev/age/if_agevar.h>
76
77/* "device miibus" required.  See GENERIC if you get errors here. */
78#include "miibus_if.h"
79
80#define	AGE_CSUM_FEATURES	(CSUM_TCP | CSUM_UDP)
81
82MODULE_DEPEND(age, pci, 1, 1, 1);
83MODULE_DEPEND(age, ether, 1, 1, 1);
84MODULE_DEPEND(age, miibus, 1, 1, 1);
85
86/* Tunables. */
87static int msi_disable = 0;
88static int msix_disable = 0;
89TUNABLE_INT("hw.age.msi_disable", &msi_disable);
90TUNABLE_INT("hw.age.msix_disable", &msix_disable);
91
92/*
93 * Devices supported by this driver.
94 */
95static struct age_dev {
96	uint16_t	age_vendorid;
97	uint16_t	age_deviceid;
98	const char	*age_name;
99} age_devs[] = {
100	{ VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1,
101	    "Attansic Technology Corp, L1 Gigabit Ethernet" },
102};
103
104static int age_miibus_readreg(device_t, int, int);
105static int age_miibus_writereg(device_t, int, int, int);
106static void age_miibus_statchg(device_t);
107static void age_mediastatus(struct ifnet *, struct ifmediareq *);
108static int age_mediachange(struct ifnet *);
109static int age_probe(device_t);
110static void age_get_macaddr(struct age_softc *);
111static void age_phy_reset(struct age_softc *);
112static int age_attach(device_t);
113static int age_detach(device_t);
114static void age_sysctl_node(struct age_softc *);
115static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int);
116static int age_check_boundary(struct age_softc *);
117static int age_dma_alloc(struct age_softc *);
118static void age_dma_free(struct age_softc *);
119static int age_shutdown(device_t);
120static void age_setwol(struct age_softc *);
121static int age_suspend(device_t);
122static int age_resume(device_t);
123static int age_encap(struct age_softc *, struct mbuf **);
124static void age_start(struct ifnet *);
125static void age_start_locked(struct ifnet *);
126static void age_watchdog(struct age_softc *);
127static int age_ioctl(struct ifnet *, u_long, caddr_t);
128static void age_mac_config(struct age_softc *);
129static void age_link_task(void *, int);
130static void age_stats_update(struct age_softc *);
131static int age_intr(void *);
132static void age_int_task(void *, int);
133static void age_txintr(struct age_softc *, int);
134static void age_rxeof(struct age_softc *sc, struct rx_rdesc *);
135static int age_rxintr(struct age_softc *, int, int);
136static void age_tick(void *);
137static void age_reset(struct age_softc *);
138static void age_init(void *);
139static void age_init_locked(struct age_softc *);
140static void age_stop(struct age_softc *);
141static void age_stop_txmac(struct age_softc *);
142static void age_stop_rxmac(struct age_softc *);
143static void age_init_tx_ring(struct age_softc *);
144static int age_init_rx_ring(struct age_softc *);
145static void age_init_rr_ring(struct age_softc *);
146static void age_init_cmb_block(struct age_softc *);
147static void age_init_smb_block(struct age_softc *);
148#ifndef __NO_STRICT_ALIGNMENT
149static struct mbuf *age_fixup_rx(struct ifnet *, struct mbuf *);
150#endif
151static int age_newbuf(struct age_softc *, struct age_rxdesc *);
152static void age_rxvlan(struct age_softc *);
153static void age_rxfilter(struct age_softc *);
154static int sysctl_age_stats(SYSCTL_HANDLER_ARGS);
155static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
156static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS);
157static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS);
158
159static device_method_t age_methods[] = {
160	/* Device interface. */
161	DEVMETHOD(device_probe,		age_probe),
162	DEVMETHOD(device_attach,	age_attach),
163	DEVMETHOD(device_detach,	age_detach),
164	DEVMETHOD(device_shutdown,	age_shutdown),
165	DEVMETHOD(device_suspend,	age_suspend),
166	DEVMETHOD(device_resume,	age_resume),
167
168	/* MII interface. */
169	DEVMETHOD(miibus_readreg,	age_miibus_readreg),
170	DEVMETHOD(miibus_writereg,	age_miibus_writereg),
171	DEVMETHOD(miibus_statchg,	age_miibus_statchg),
172	{ NULL, NULL }
173};
174
175static driver_t age_driver = {
176	"age",
177	age_methods,
178	sizeof(struct age_softc)
179};
180
181static devclass_t age_devclass;
182
183DRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0);
184MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, age, age_devs,
185    nitems(age_devs));
186DRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0);
187
188static struct resource_spec age_res_spec_mem[] = {
189	{ SYS_RES_MEMORY,	PCIR_BAR(0),	RF_ACTIVE },
190	{ -1,			0,		0 }
191};
192
193static struct resource_spec age_irq_spec_legacy[] = {
194	{ SYS_RES_IRQ,		0,		RF_ACTIVE | RF_SHAREABLE },
195	{ -1,			0,		0 }
196};
197
198static struct resource_spec age_irq_spec_msi[] = {
199	{ SYS_RES_IRQ,		1,		RF_ACTIVE },
200	{ -1,			0,		0 }
201};
202
203static struct resource_spec age_irq_spec_msix[] = {
204	{ SYS_RES_IRQ,		1,		RF_ACTIVE },
205	{ -1,			0,		0 }
206};
207
208/*
209 *	Read a PHY register on the MII of the L1.
210 */
211static int
212age_miibus_readreg(device_t dev, int phy, int reg)
213{
214	struct age_softc *sc;
215	uint32_t v;
216	int i;
217
218	sc = device_get_softc(dev);
219
220	CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
221	    MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
222	for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
223		DELAY(1);
224		v = CSR_READ_4(sc, AGE_MDIO);
225		if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
226			break;
227	}
228
229	if (i == 0) {
230		device_printf(sc->age_dev, "phy read timeout : %d\n", reg);
231		return (0);
232	}
233
234	return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
235}
236
237/*
238 *	Write a PHY register on the MII of the L1.
239 */
240static int
241age_miibus_writereg(device_t dev, int phy, int reg, int val)
242{
243	struct age_softc *sc;
244	uint32_t v;
245	int i;
246
247	sc = device_get_softc(dev);
248
249	CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
250	    (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
251	    MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
252	for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
253		DELAY(1);
254		v = CSR_READ_4(sc, AGE_MDIO);
255		if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
256			break;
257	}
258
259	if (i == 0)
260		device_printf(sc->age_dev, "phy write timeout : %d\n", reg);
261
262	return (0);
263}
264
265/*
266 *	Callback from MII layer when media changes.
267 */
268static void
269age_miibus_statchg(device_t dev)
270{
271	struct age_softc *sc;
272
273	sc = device_get_softc(dev);
274	taskqueue_enqueue(taskqueue_swi, &sc->age_link_task);
275}
276
277/*
278 *	Get the current interface media status.
279 */
280static void
281age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
282{
283	struct age_softc *sc;
284	struct mii_data *mii;
285
286	sc = ifp->if_softc;
287	AGE_LOCK(sc);
288	mii = device_get_softc(sc->age_miibus);
289
290	mii_pollstat(mii);
291	ifmr->ifm_status = mii->mii_media_status;
292	ifmr->ifm_active = mii->mii_media_active;
293	AGE_UNLOCK(sc);
294}
295
296/*
297 *	Set hardware to newly-selected media.
298 */
299static int
300age_mediachange(struct ifnet *ifp)
301{
302	struct age_softc *sc;
303	struct mii_data *mii;
304	struct mii_softc *miisc;
305	int error;
306
307	sc = ifp->if_softc;
308	AGE_LOCK(sc);
309	mii = device_get_softc(sc->age_miibus);
310	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
311		PHY_RESET(miisc);
312	error = mii_mediachg(mii);
313	AGE_UNLOCK(sc);
314
315	return (error);
316}
317
318static int
319age_probe(device_t dev)
320{
321	struct age_dev *sp;
322	int i;
323	uint16_t vendor, devid;
324
325	vendor = pci_get_vendor(dev);
326	devid = pci_get_device(dev);
327	sp = age_devs;
328	for (i = 0; i < nitems(age_devs); i++, sp++) {
329		if (vendor == sp->age_vendorid &&
330		    devid == sp->age_deviceid) {
331			device_set_desc(dev, sp->age_name);
332			return (BUS_PROBE_DEFAULT);
333		}
334	}
335
336	return (ENXIO);
337}
338
339static void
340age_get_macaddr(struct age_softc *sc)
341{
342	uint32_t ea[2], reg;
343	int i, vpdc;
344
345	reg = CSR_READ_4(sc, AGE_SPI_CTRL);
346	if ((reg & SPI_VPD_ENB) != 0) {
347		/* Get VPD stored in TWSI EEPROM. */
348		reg &= ~SPI_VPD_ENB;
349		CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);
350	}
351
352	if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) {
353		/*
354		 * PCI VPD capability found, let TWSI reload EEPROM.
355		 * This will set ethernet address of controller.
356		 */
357		CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
358		    TWSI_CTRL_SW_LD_START);
359		for (i = 100; i > 0; i--) {
360			DELAY(1000);
361			reg = CSR_READ_4(sc, AGE_TWSI_CTRL);
362			if ((reg & TWSI_CTRL_SW_LD_START) == 0)
363				break;
364		}
365		if (i == 0)
366			device_printf(sc->age_dev,
367			    "reloading EEPROM timeout!\n");
368	} else {
369		if (bootverbose)
370			device_printf(sc->age_dev,
371			    "PCI VPD capability not found!\n");
372	}
373
374	ea[0] = CSR_READ_4(sc, AGE_PAR0);
375	ea[1] = CSR_READ_4(sc, AGE_PAR1);
376	sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF;
377	sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF;
378	sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF;
379	sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF;
380	sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF;
381	sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF;
382}
383
384static void
385age_phy_reset(struct age_softc *sc)
386{
387	uint16_t reg, pn;
388	int i, linkup;
389
390	/* Reset PHY. */
391	CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST);
392	DELAY(2000);
393	CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR);
394	DELAY(2000);
395
396#define	ATPHY_DBG_ADDR		0x1D
397#define	ATPHY_DBG_DATA		0x1E
398#define	ATPHY_CDTC		0x16
399#define	PHY_CDTC_ENB		0x0001
400#define	PHY_CDTC_POFF		8
401#define	ATPHY_CDTS		0x1C
402#define	PHY_CDTS_STAT_OK	0x0000
403#define	PHY_CDTS_STAT_SHORT	0x0100
404#define	PHY_CDTS_STAT_OPEN	0x0200
405#define	PHY_CDTS_STAT_INVAL	0x0300
406#define	PHY_CDTS_STAT_MASK	0x0300
407
408	/* Check power saving mode. Magic from Linux. */
409	age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET);
410	for (linkup = 0, pn = 0; pn < 4; pn++) {
411		age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC,
412		    (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB);
413		for (i = 200; i > 0; i--) {
414			DELAY(1000);
415			reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
416			    ATPHY_CDTC);
417			if ((reg & PHY_CDTC_ENB) == 0)
418				break;
419		}
420		DELAY(1000);
421		reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
422		    ATPHY_CDTS);
423		if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) {
424			linkup++;
425			break;
426		}
427	}
428	age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR,
429	    BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
430	if (linkup == 0) {
431		age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
432		    ATPHY_DBG_ADDR, 0);
433		age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
434		    ATPHY_DBG_DATA, 0x124E);
435		age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
436		    ATPHY_DBG_ADDR, 1);
437		reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
438		    ATPHY_DBG_DATA);
439		age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
440		    ATPHY_DBG_DATA, reg | 0x03);
441		/* XXX */
442		DELAY(1500 * 1000);
443		age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
444		    ATPHY_DBG_ADDR, 0);
445		age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
446		    ATPHY_DBG_DATA, 0x024E);
447    }
448
449#undef	ATPHY_DBG_ADDR
450#undef	ATPHY_DBG_DATA
451#undef	ATPHY_CDTC
452#undef	PHY_CDTC_ENB
453#undef	PHY_CDTC_POFF
454#undef	ATPHY_CDTS
455#undef	PHY_CDTS_STAT_OK
456#undef	PHY_CDTS_STAT_SHORT
457#undef	PHY_CDTS_STAT_OPEN
458#undef	PHY_CDTS_STAT_INVAL
459#undef	PHY_CDTS_STAT_MASK
460}
461
462static int
463age_attach(device_t dev)
464{
465	struct age_softc *sc;
466	struct ifnet *ifp;
467	uint16_t burst;
468	int error, i, msic, msixc, pmc;
469
470	error = 0;
471	sc = device_get_softc(dev);
472	sc->age_dev = dev;
473
474	mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
475	    MTX_DEF);
476	callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0);
477	TASK_INIT(&sc->age_int_task, 0, age_int_task, sc);
478	TASK_INIT(&sc->age_link_task, 0, age_link_task, sc);
479
480	/* Map the device. */
481	pci_enable_busmaster(dev);
482	sc->age_res_spec = age_res_spec_mem;
483	sc->age_irq_spec = age_irq_spec_legacy;
484	error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res);
485	if (error != 0) {
486		device_printf(dev, "cannot allocate memory resources.\n");
487		goto fail;
488	}
489
490	/* Set PHY address. */
491	sc->age_phyaddr = AGE_PHY_ADDR;
492
493	/* Reset PHY. */
494	age_phy_reset(sc);
495
496	/* Reset the ethernet controller. */
497	age_reset(sc);
498
499	/* Get PCI and chip id/revision. */
500	sc->age_rev = pci_get_revid(dev);
501	sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>
502	    MASTER_CHIP_REV_SHIFT;
503	if (bootverbose) {
504		device_printf(dev, "PCI device revision : 0x%04x\n",
505		    sc->age_rev);
506		device_printf(dev, "Chip id/revision : 0x%04x\n",
507		    sc->age_chip_rev);
508	}
509
510	/*
511	 * XXX
512	 * Unintialized hardware returns an invalid chip id/revision
513	 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that
514	 * unplugged cable results in putting hardware into automatic
515	 * power down mode which in turn returns invalld chip revision.
516	 */
517	if (sc->age_chip_rev == 0xFFFF) {
518		device_printf(dev,"invalid chip revision : 0x%04x -- "
519		    "not initialized?\n", sc->age_chip_rev);
520		error = ENXIO;
521		goto fail;
522	}
523
524	device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n",
525	    CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),
526	    CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN));
527
528	/* Allocate IRQ resources. */
529	msixc = pci_msix_count(dev);
530	msic = pci_msi_count(dev);
531	if (bootverbose) {
532		device_printf(dev, "MSIX count : %d\n", msixc);
533		device_printf(dev, "MSI count : %d\n", msic);
534	}
535
536	/* Prefer MSIX over MSI. */
537	if (msix_disable == 0 || msi_disable == 0) {
538		if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES &&
539		    pci_alloc_msix(dev, &msixc) == 0) {
540			if (msic == AGE_MSIX_MESSAGES) {
541				device_printf(dev, "Using %d MSIX messages.\n",
542				    msixc);
543				sc->age_flags |= AGE_FLAG_MSIX;
544				sc->age_irq_spec = age_irq_spec_msix;
545			} else
546				pci_release_msi(dev);
547		}
548		if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 &&
549		    msic == AGE_MSI_MESSAGES &&
550		    pci_alloc_msi(dev, &msic) == 0) {
551			if (msic == AGE_MSI_MESSAGES) {
552				device_printf(dev, "Using %d MSI messages.\n",
553				    msic);
554				sc->age_flags |= AGE_FLAG_MSI;
555				sc->age_irq_spec = age_irq_spec_msi;
556			} else
557				pci_release_msi(dev);
558		}
559	}
560
561	error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq);
562	if (error != 0) {
563		device_printf(dev, "cannot allocate IRQ resources.\n");
564		goto fail;
565	}
566
567	/* Get DMA parameters from PCIe device control register. */
568	if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
569		sc->age_flags |= AGE_FLAG_PCIE;
570		burst = pci_read_config(dev, i + 0x08, 2);
571		/* Max read request size. */
572		sc->age_dma_rd_burst = ((burst >> 12) & 0x07) <<
573		    DMA_CFG_RD_BURST_SHIFT;
574		/* Max payload size. */
575		sc->age_dma_wr_burst = ((burst >> 5) & 0x07) <<
576		    DMA_CFG_WR_BURST_SHIFT;
577		if (bootverbose) {
578			device_printf(dev, "Read request size : %d bytes.\n",
579			    128 << ((burst >> 12) & 0x07));
580			device_printf(dev, "TLP payload size : %d bytes.\n",
581			    128 << ((burst >> 5) & 0x07));
582		}
583	} else {
584		sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128;
585		sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128;
586	}
587
588	/* Create device sysctl node. */
589	age_sysctl_node(sc);
590
591	if ((error = age_dma_alloc(sc)) != 0)
592		goto fail;
593
594	/* Load station address. */
595	age_get_macaddr(sc);
596
597	ifp = sc->age_ifp = if_alloc(IFT_ETHER);
598	if (ifp == NULL) {
599		device_printf(dev, "cannot allocate ifnet structure.\n");
600		error = ENXIO;
601		goto fail;
602	}
603
604	ifp->if_softc = sc;
605	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
606	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
607	ifp->if_ioctl = age_ioctl;
608	ifp->if_start = age_start;
609	ifp->if_init = age_init;
610	ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1;
611	IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
612	IFQ_SET_READY(&ifp->if_snd);
613	ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
614	ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO;
615	if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
616		sc->age_flags |= AGE_FLAG_PMCAP;
617		ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
618	}
619	ifp->if_capenable = ifp->if_capabilities;
620
621	/* Set up MII bus. */
622	error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange,
623	    age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY,
624	    0);
625	if (error != 0) {
626		device_printf(dev, "attaching PHYs failed\n");
627		goto fail;
628	}
629
630	ether_ifattach(ifp, sc->age_eaddr);
631
632	/* VLAN capability setup. */
633	ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
634	    IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
635	ifp->if_capenable = ifp->if_capabilities;
636
637	/* Tell the upper layer(s) we support long frames. */
638	ifp->if_hdrlen = sizeof(struct ether_vlan_header);
639
640	/* Create local taskq. */
641	sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK,
642	    taskqueue_thread_enqueue, &sc->age_tq);
643	if (sc->age_tq == NULL) {
644		device_printf(dev, "could not create taskqueue.\n");
645		ether_ifdetach(ifp);
646		error = ENXIO;
647		goto fail;
648	}
649	taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq",
650	    device_get_nameunit(sc->age_dev));
651
652	if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
653		msic = AGE_MSIX_MESSAGES;
654	else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
655		msic = AGE_MSI_MESSAGES;
656	else
657		msic = 1;
658	for (i = 0; i < msic; i++) {
659		error = bus_setup_intr(dev, sc->age_irq[i],
660		    INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc,
661		    &sc->age_intrhand[i]);
662		if (error != 0)
663			break;
664	}
665	if (error != 0) {
666		device_printf(dev, "could not set up interrupt handler.\n");
667		taskqueue_free(sc->age_tq);
668		sc->age_tq = NULL;
669		ether_ifdetach(ifp);
670		goto fail;
671	}
672
673fail:
674	if (error != 0)
675		age_detach(dev);
676
677	return (error);
678}
679
680static int
681age_detach(device_t dev)
682{
683	struct age_softc *sc;
684	struct ifnet *ifp;
685	int i, msic;
686
687	sc = device_get_softc(dev);
688
689	ifp = sc->age_ifp;
690	if (device_is_attached(dev)) {
691		AGE_LOCK(sc);
692		sc->age_flags |= AGE_FLAG_DETACH;
693		age_stop(sc);
694		AGE_UNLOCK(sc);
695		callout_drain(&sc->age_tick_ch);
696		taskqueue_drain(sc->age_tq, &sc->age_int_task);
697		taskqueue_drain(taskqueue_swi, &sc->age_link_task);
698		ether_ifdetach(ifp);
699	}
700
701	if (sc->age_tq != NULL) {
702		taskqueue_drain(sc->age_tq, &sc->age_int_task);
703		taskqueue_free(sc->age_tq);
704		sc->age_tq = NULL;
705	}
706
707	if (sc->age_miibus != NULL) {
708		device_delete_child(dev, sc->age_miibus);
709		sc->age_miibus = NULL;
710	}
711	bus_generic_detach(dev);
712	age_dma_free(sc);
713
714	if (ifp != NULL) {
715		if_free(ifp);
716		sc->age_ifp = NULL;
717	}
718
719	if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
720		msic = AGE_MSIX_MESSAGES;
721	else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
722		msic = AGE_MSI_MESSAGES;
723	else
724		msic = 1;
725	for (i = 0; i < msic; i++) {
726		if (sc->age_intrhand[i] != NULL) {
727			bus_teardown_intr(dev, sc->age_irq[i],
728			    sc->age_intrhand[i]);
729			sc->age_intrhand[i] = NULL;
730		}
731	}
732
733	bus_release_resources(dev, sc->age_irq_spec, sc->age_irq);
734	if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0)
735		pci_release_msi(dev);
736	bus_release_resources(dev, sc->age_res_spec, sc->age_res);
737	mtx_destroy(&sc->age_mtx);
738
739	return (0);
740}
741
742static void
743age_sysctl_node(struct age_softc *sc)
744{
745	int error;
746
747	SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
748	    SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
749	    "stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
750	    sc, 0, sysctl_age_stats, "I", "Statistics");
751
752	SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
753	    SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
754	    "int_mod", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
755	    &sc->age_int_mod, 0, sysctl_hw_age_int_mod, "I",
756	    "age interrupt moderation");
757
758	/* Pull in device tunables. */
759	sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
760	error = resource_int_value(device_get_name(sc->age_dev),
761	    device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod);
762	if (error == 0) {
763		if (sc->age_int_mod < AGE_IM_TIMER_MIN ||
764		    sc->age_int_mod > AGE_IM_TIMER_MAX) {
765			device_printf(sc->age_dev,
766			    "int_mod value out of range; using default: %d\n",
767			    AGE_IM_TIMER_DEFAULT);
768			sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
769		}
770	}
771
772	SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
773	    SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
774	    "process_limit", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
775	    &sc->age_process_limit, 0, sysctl_hw_age_proc_limit, "I",
776	    "max number of Rx events to process");
777
778	/* Pull in device tunables. */
779	sc->age_process_limit = AGE_PROC_DEFAULT;
780	error = resource_int_value(device_get_name(sc->age_dev),
781	    device_get_unit(sc->age_dev), "process_limit",
782	    &sc->age_process_limit);
783	if (error == 0) {
784		if (sc->age_process_limit < AGE_PROC_MIN ||
785		    sc->age_process_limit > AGE_PROC_MAX) {
786			device_printf(sc->age_dev,
787			    "process_limit value out of range; "
788			    "using default: %d\n", AGE_PROC_DEFAULT);
789			sc->age_process_limit = AGE_PROC_DEFAULT;
790		}
791	}
792}
793
794struct age_dmamap_arg {
795	bus_addr_t	age_busaddr;
796};
797
798static void
799age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
800{
801	struct age_dmamap_arg *ctx;
802
803	if (error != 0)
804		return;
805
806	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
807
808	ctx = (struct age_dmamap_arg *)arg;
809	ctx->age_busaddr = segs[0].ds_addr;
810}
811
812/*
813 * Attansic L1 controller have single register to specify high
814 * address part of DMA blocks. So all descriptor structures and
815 * DMA memory blocks should have the same high address of given
816 * 4GB address space(i.e. crossing 4GB boundary is not allowed).
817 */
818static int
819age_check_boundary(struct age_softc *sc)
820{
821	bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end;
822	bus_addr_t cmb_block_end, smb_block_end;
823
824	/* Tx/Rx descriptor queue should reside within 4GB boundary. */
825	tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ;
826	rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ;
827	rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ;
828	cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ;
829	smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ;
830
831	if ((AGE_ADDR_HI(tx_ring_end) !=
832	    AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) ||
833	    (AGE_ADDR_HI(rx_ring_end) !=
834	    AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) ||
835	    (AGE_ADDR_HI(rr_ring_end) !=
836	    AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) ||
837	    (AGE_ADDR_HI(cmb_block_end) !=
838	    AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) ||
839	    (AGE_ADDR_HI(smb_block_end) !=
840	    AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr)))
841		return (EFBIG);
842
843	if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) ||
844	    (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) ||
845	    (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) ||
846	    (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end)))
847		return (EFBIG);
848
849	return (0);
850}
851
852static int
853age_dma_alloc(struct age_softc *sc)
854{
855	struct age_txdesc *txd;
856	struct age_rxdesc *rxd;
857	bus_addr_t lowaddr;
858	struct age_dmamap_arg ctx;
859	int error, i;
860
861	lowaddr = BUS_SPACE_MAXADDR;
862
863again:
864	/* Create parent ring/DMA block tag. */
865	error = bus_dma_tag_create(
866	    bus_get_dma_tag(sc->age_dev), /* parent */
867	    1, 0,			/* alignment, boundary */
868	    lowaddr,			/* lowaddr */
869	    BUS_SPACE_MAXADDR,		/* highaddr */
870	    NULL, NULL,			/* filter, filterarg */
871	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
872	    0,				/* nsegments */
873	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
874	    0,				/* flags */
875	    NULL, NULL,			/* lockfunc, lockarg */
876	    &sc->age_cdata.age_parent_tag);
877	if (error != 0) {
878		device_printf(sc->age_dev,
879		    "could not create parent DMA tag.\n");
880		goto fail;
881	}
882
883	/* Create tag for Tx ring. */
884	error = bus_dma_tag_create(
885	    sc->age_cdata.age_parent_tag, /* parent */
886	    AGE_TX_RING_ALIGN, 0,	/* alignment, boundary */
887	    BUS_SPACE_MAXADDR,		/* lowaddr */
888	    BUS_SPACE_MAXADDR,		/* highaddr */
889	    NULL, NULL,			/* filter, filterarg */
890	    AGE_TX_RING_SZ,		/* maxsize */
891	    1,				/* nsegments */
892	    AGE_TX_RING_SZ,		/* maxsegsize */
893	    0,				/* flags */
894	    NULL, NULL,			/* lockfunc, lockarg */
895	    &sc->age_cdata.age_tx_ring_tag);
896	if (error != 0) {
897		device_printf(sc->age_dev,
898		    "could not create Tx ring DMA tag.\n");
899		goto fail;
900	}
901
902	/* Create tag for Rx ring. */
903	error = bus_dma_tag_create(
904	    sc->age_cdata.age_parent_tag, /* parent */
905	    AGE_RX_RING_ALIGN, 0,	/* alignment, boundary */
906	    BUS_SPACE_MAXADDR,		/* lowaddr */
907	    BUS_SPACE_MAXADDR,		/* highaddr */
908	    NULL, NULL,			/* filter, filterarg */
909	    AGE_RX_RING_SZ,		/* maxsize */
910	    1,				/* nsegments */
911	    AGE_RX_RING_SZ,		/* maxsegsize */
912	    0,				/* flags */
913	    NULL, NULL,			/* lockfunc, lockarg */
914	    &sc->age_cdata.age_rx_ring_tag);
915	if (error != 0) {
916		device_printf(sc->age_dev,
917		    "could not create Rx ring DMA tag.\n");
918		goto fail;
919	}
920
921	/* Create tag for Rx return ring. */
922	error = bus_dma_tag_create(
923	    sc->age_cdata.age_parent_tag, /* parent */
924	    AGE_RR_RING_ALIGN, 0,	/* alignment, boundary */
925	    BUS_SPACE_MAXADDR,		/* lowaddr */
926	    BUS_SPACE_MAXADDR,		/* highaddr */
927	    NULL, NULL,			/* filter, filterarg */
928	    AGE_RR_RING_SZ,		/* maxsize */
929	    1,				/* nsegments */
930	    AGE_RR_RING_SZ,		/* maxsegsize */
931	    0,				/* flags */
932	    NULL, NULL,			/* lockfunc, lockarg */
933	    &sc->age_cdata.age_rr_ring_tag);
934	if (error != 0) {
935		device_printf(sc->age_dev,
936		    "could not create Rx return ring DMA tag.\n");
937		goto fail;
938	}
939
940	/* Create tag for coalesing message block. */
941	error = bus_dma_tag_create(
942	    sc->age_cdata.age_parent_tag, /* parent */
943	    AGE_CMB_ALIGN, 0,		/* alignment, boundary */
944	    BUS_SPACE_MAXADDR,		/* lowaddr */
945	    BUS_SPACE_MAXADDR,		/* highaddr */
946	    NULL, NULL,			/* filter, filterarg */
947	    AGE_CMB_BLOCK_SZ,		/* maxsize */
948	    1,				/* nsegments */
949	    AGE_CMB_BLOCK_SZ,		/* maxsegsize */
950	    0,				/* flags */
951	    NULL, NULL,			/* lockfunc, lockarg */
952	    &sc->age_cdata.age_cmb_block_tag);
953	if (error != 0) {
954		device_printf(sc->age_dev,
955		    "could not create CMB DMA tag.\n");
956		goto fail;
957	}
958
959	/* Create tag for statistics message block. */
960	error = bus_dma_tag_create(
961	    sc->age_cdata.age_parent_tag, /* parent */
962	    AGE_SMB_ALIGN, 0,		/* alignment, boundary */
963	    BUS_SPACE_MAXADDR,		/* lowaddr */
964	    BUS_SPACE_MAXADDR,		/* highaddr */
965	    NULL, NULL,			/* filter, filterarg */
966	    AGE_SMB_BLOCK_SZ,		/* maxsize */
967	    1,				/* nsegments */
968	    AGE_SMB_BLOCK_SZ,		/* maxsegsize */
969	    0,				/* flags */
970	    NULL, NULL,			/* lockfunc, lockarg */
971	    &sc->age_cdata.age_smb_block_tag);
972	if (error != 0) {
973		device_printf(sc->age_dev,
974		    "could not create SMB DMA tag.\n");
975		goto fail;
976	}
977
978	/* Allocate DMA'able memory and load the DMA map. */
979	error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag,
980	    (void **)&sc->age_rdata.age_tx_ring,
981	    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
982	    &sc->age_cdata.age_tx_ring_map);
983	if (error != 0) {
984		device_printf(sc->age_dev,
985		    "could not allocate DMA'able memory for Tx ring.\n");
986		goto fail;
987	}
988	ctx.age_busaddr = 0;
989	error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag,
990	    sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring,
991	    AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0);
992	if (error != 0 || ctx.age_busaddr == 0) {
993		device_printf(sc->age_dev,
994		    "could not load DMA'able memory for Tx ring.\n");
995		goto fail;
996	}
997	sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr;
998	/* Rx ring */
999	error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag,
1000	    (void **)&sc->age_rdata.age_rx_ring,
1001	    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1002	    &sc->age_cdata.age_rx_ring_map);
1003	if (error != 0) {
1004		device_printf(sc->age_dev,
1005		    "could not allocate DMA'able memory for Rx ring.\n");
1006		goto fail;
1007	}
1008	ctx.age_busaddr = 0;
1009	error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag,
1010	    sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring,
1011	    AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0);
1012	if (error != 0 || ctx.age_busaddr == 0) {
1013		device_printf(sc->age_dev,
1014		    "could not load DMA'able memory for Rx ring.\n");
1015		goto fail;
1016	}
1017	sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr;
1018	/* Rx return ring */
1019	error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag,
1020	    (void **)&sc->age_rdata.age_rr_ring,
1021	    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1022	    &sc->age_cdata.age_rr_ring_map);
1023	if (error != 0) {
1024		device_printf(sc->age_dev,
1025		    "could not allocate DMA'able memory for Rx return ring.\n");
1026		goto fail;
1027	}
1028	ctx.age_busaddr = 0;
1029	error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag,
1030	    sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring,
1031	    AGE_RR_RING_SZ, age_dmamap_cb,
1032	    &ctx, 0);
1033	if (error != 0 || ctx.age_busaddr == 0) {
1034		device_printf(sc->age_dev,
1035		    "could not load DMA'able memory for Rx return ring.\n");
1036		goto fail;
1037	}
1038	sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr;
1039	/* CMB block */
1040	error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag,
1041	    (void **)&sc->age_rdata.age_cmb_block,
1042	    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1043	    &sc->age_cdata.age_cmb_block_map);
1044	if (error != 0) {
1045		device_printf(sc->age_dev,
1046		    "could not allocate DMA'able memory for CMB block.\n");
1047		goto fail;
1048	}
1049	ctx.age_busaddr = 0;
1050	error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag,
1051	    sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block,
1052	    AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1053	if (error != 0 || ctx.age_busaddr == 0) {
1054		device_printf(sc->age_dev,
1055		    "could not load DMA'able memory for CMB block.\n");
1056		goto fail;
1057	}
1058	sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr;
1059	/* SMB block */
1060	error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag,
1061	    (void **)&sc->age_rdata.age_smb_block,
1062	    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1063	    &sc->age_cdata.age_smb_block_map);
1064	if (error != 0) {
1065		device_printf(sc->age_dev,
1066		    "could not allocate DMA'able memory for SMB block.\n");
1067		goto fail;
1068	}
1069	ctx.age_busaddr = 0;
1070	error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag,
1071	    sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block,
1072	    AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1073	if (error != 0 || ctx.age_busaddr == 0) {
1074		device_printf(sc->age_dev,
1075		    "could not load DMA'able memory for SMB block.\n");
1076		goto fail;
1077	}
1078	sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr;
1079
1080	/*
1081	 * All ring buffer and DMA blocks should have the same
1082	 * high address part of 64bit DMA address space.
1083	 */
1084	if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1085	    (error = age_check_boundary(sc)) != 0) {
1086		device_printf(sc->age_dev, "4GB boundary crossed, "
1087		    "switching to 32bit DMA addressing mode.\n");
1088		age_dma_free(sc);
1089		/* Limit DMA address space to 32bit and try again. */
1090		lowaddr = BUS_SPACE_MAXADDR_32BIT;
1091		goto again;
1092	}
1093
1094	/*
1095	 * Create Tx/Rx buffer parent tag.
1096	 * L1 supports full 64bit DMA addressing in Tx/Rx buffers
1097	 * so it needs separate parent DMA tag.
1098	 * XXX
1099	 * It seems enabling 64bit DMA causes data corruption. Limit
1100	 * DMA address space to 32bit.
1101	 */
1102	error = bus_dma_tag_create(
1103	    bus_get_dma_tag(sc->age_dev), /* parent */
1104	    1, 0,			/* alignment, boundary */
1105	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
1106	    BUS_SPACE_MAXADDR,		/* highaddr */
1107	    NULL, NULL,			/* filter, filterarg */
1108	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
1109	    0,				/* nsegments */
1110	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
1111	    0,				/* flags */
1112	    NULL, NULL,			/* lockfunc, lockarg */
1113	    &sc->age_cdata.age_buffer_tag);
1114	if (error != 0) {
1115		device_printf(sc->age_dev,
1116		    "could not create parent buffer DMA tag.\n");
1117		goto fail;
1118	}
1119
1120	/* Create tag for Tx buffers. */
1121	error = bus_dma_tag_create(
1122	    sc->age_cdata.age_buffer_tag, /* parent */
1123	    1, 0,			/* alignment, boundary */
1124	    BUS_SPACE_MAXADDR,		/* lowaddr */
1125	    BUS_SPACE_MAXADDR,		/* highaddr */
1126	    NULL, NULL,			/* filter, filterarg */
1127	    AGE_TSO_MAXSIZE,		/* maxsize */
1128	    AGE_MAXTXSEGS,		/* nsegments */
1129	    AGE_TSO_MAXSEGSIZE,		/* maxsegsize */
1130	    0,				/* flags */
1131	    NULL, NULL,			/* lockfunc, lockarg */
1132	    &sc->age_cdata.age_tx_tag);
1133	if (error != 0) {
1134		device_printf(sc->age_dev, "could not create Tx DMA tag.\n");
1135		goto fail;
1136	}
1137
1138	/* Create tag for Rx buffers. */
1139	error = bus_dma_tag_create(
1140	    sc->age_cdata.age_buffer_tag, /* parent */
1141	    AGE_RX_BUF_ALIGN, 0,	/* alignment, boundary */
1142	    BUS_SPACE_MAXADDR,		/* lowaddr */
1143	    BUS_SPACE_MAXADDR,		/* highaddr */
1144	    NULL, NULL,			/* filter, filterarg */
1145	    MCLBYTES,			/* maxsize */
1146	    1,				/* nsegments */
1147	    MCLBYTES,			/* maxsegsize */
1148	    0,				/* flags */
1149	    NULL, NULL,			/* lockfunc, lockarg */
1150	    &sc->age_cdata.age_rx_tag);
1151	if (error != 0) {
1152		device_printf(sc->age_dev, "could not create Rx DMA tag.\n");
1153		goto fail;
1154	}
1155
1156	/* Create DMA maps for Tx buffers. */
1157	for (i = 0; i < AGE_TX_RING_CNT; i++) {
1158		txd = &sc->age_cdata.age_txdesc[i];
1159		txd->tx_m = NULL;
1160		txd->tx_dmamap = NULL;
1161		error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0,
1162		    &txd->tx_dmamap);
1163		if (error != 0) {
1164			device_printf(sc->age_dev,
1165			    "could not create Tx dmamap.\n");
1166			goto fail;
1167		}
1168	}
1169	/* Create DMA maps for Rx buffers. */
1170	if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1171	    &sc->age_cdata.age_rx_sparemap)) != 0) {
1172		device_printf(sc->age_dev,
1173		    "could not create spare Rx dmamap.\n");
1174		goto fail;
1175	}
1176	for (i = 0; i < AGE_RX_RING_CNT; i++) {
1177		rxd = &sc->age_cdata.age_rxdesc[i];
1178		rxd->rx_m = NULL;
1179		rxd->rx_dmamap = NULL;
1180		error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1181		    &rxd->rx_dmamap);
1182		if (error != 0) {
1183			device_printf(sc->age_dev,
1184			    "could not create Rx dmamap.\n");
1185			goto fail;
1186		}
1187	}
1188
1189fail:
1190	return (error);
1191}
1192
1193static void
1194age_dma_free(struct age_softc *sc)
1195{
1196	struct age_txdesc *txd;
1197	struct age_rxdesc *rxd;
1198	int i;
1199
1200	/* Tx buffers */
1201	if (sc->age_cdata.age_tx_tag != NULL) {
1202		for (i = 0; i < AGE_TX_RING_CNT; i++) {
1203			txd = &sc->age_cdata.age_txdesc[i];
1204			if (txd->tx_dmamap != NULL) {
1205				bus_dmamap_destroy(sc->age_cdata.age_tx_tag,
1206				    txd->tx_dmamap);
1207				txd->tx_dmamap = NULL;
1208			}
1209		}
1210		bus_dma_tag_destroy(sc->age_cdata.age_tx_tag);
1211		sc->age_cdata.age_tx_tag = NULL;
1212	}
1213	/* Rx buffers */
1214	if (sc->age_cdata.age_rx_tag != NULL) {
1215		for (i = 0; i < AGE_RX_RING_CNT; i++) {
1216			rxd = &sc->age_cdata.age_rxdesc[i];
1217			if (rxd->rx_dmamap != NULL) {
1218				bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1219				    rxd->rx_dmamap);
1220				rxd->rx_dmamap = NULL;
1221			}
1222		}
1223		if (sc->age_cdata.age_rx_sparemap != NULL) {
1224			bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1225			    sc->age_cdata.age_rx_sparemap);
1226			sc->age_cdata.age_rx_sparemap = NULL;
1227		}
1228		bus_dma_tag_destroy(sc->age_cdata.age_rx_tag);
1229		sc->age_cdata.age_rx_tag = NULL;
1230	}
1231	/* Tx ring. */
1232	if (sc->age_cdata.age_tx_ring_tag != NULL) {
1233		if (sc->age_rdata.age_tx_ring_paddr != 0)
1234			bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag,
1235			    sc->age_cdata.age_tx_ring_map);
1236		if (sc->age_rdata.age_tx_ring != NULL)
1237			bus_dmamem_free(sc->age_cdata.age_tx_ring_tag,
1238			    sc->age_rdata.age_tx_ring,
1239			    sc->age_cdata.age_tx_ring_map);
1240		sc->age_rdata.age_tx_ring_paddr = 0;
1241		sc->age_rdata.age_tx_ring = NULL;
1242		bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag);
1243		sc->age_cdata.age_tx_ring_tag = NULL;
1244	}
1245	/* Rx ring. */
1246	if (sc->age_cdata.age_rx_ring_tag != NULL) {
1247		if (sc->age_rdata.age_rx_ring_paddr != 0)
1248			bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag,
1249			    sc->age_cdata.age_rx_ring_map);
1250		if (sc->age_rdata.age_rx_ring != NULL)
1251			bus_dmamem_free(sc->age_cdata.age_rx_ring_tag,
1252			    sc->age_rdata.age_rx_ring,
1253			    sc->age_cdata.age_rx_ring_map);
1254		sc->age_rdata.age_rx_ring_paddr = 0;
1255		sc->age_rdata.age_rx_ring = NULL;
1256		bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag);
1257		sc->age_cdata.age_rx_ring_tag = NULL;
1258	}
1259	/* Rx return ring. */
1260	if (sc->age_cdata.age_rr_ring_tag != NULL) {
1261		if (sc->age_rdata.age_rr_ring_paddr != 0)
1262			bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag,
1263			    sc->age_cdata.age_rr_ring_map);
1264		if (sc->age_rdata.age_rr_ring != NULL)
1265			bus_dmamem_free(sc->age_cdata.age_rr_ring_tag,
1266			    sc->age_rdata.age_rr_ring,
1267			    sc->age_cdata.age_rr_ring_map);
1268		sc->age_rdata.age_rr_ring_paddr = 0;
1269		sc->age_rdata.age_rr_ring = NULL;
1270		bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag);
1271		sc->age_cdata.age_rr_ring_tag = NULL;
1272	}
1273	/* CMB block */
1274	if (sc->age_cdata.age_cmb_block_tag != NULL) {
1275		if (sc->age_rdata.age_cmb_block_paddr != 0)
1276			bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag,
1277			    sc->age_cdata.age_cmb_block_map);
1278		if (sc->age_rdata.age_cmb_block != NULL)
1279			bus_dmamem_free(sc->age_cdata.age_cmb_block_tag,
1280			    sc->age_rdata.age_cmb_block,
1281			    sc->age_cdata.age_cmb_block_map);
1282		sc->age_rdata.age_cmb_block_paddr = 0;
1283		sc->age_rdata.age_cmb_block = NULL;
1284		bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag);
1285		sc->age_cdata.age_cmb_block_tag = NULL;
1286	}
1287	/* SMB block */
1288	if (sc->age_cdata.age_smb_block_tag != NULL) {
1289		if (sc->age_rdata.age_smb_block_paddr != 0)
1290			bus_dmamap_unload(sc->age_cdata.age_smb_block_tag,
1291			    sc->age_cdata.age_smb_block_map);
1292		if (sc->age_rdata.age_smb_block != NULL)
1293			bus_dmamem_free(sc->age_cdata.age_smb_block_tag,
1294			    sc->age_rdata.age_smb_block,
1295			    sc->age_cdata.age_smb_block_map);
1296		sc->age_rdata.age_smb_block_paddr = 0;
1297		sc->age_rdata.age_smb_block = NULL;
1298		bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag);
1299		sc->age_cdata.age_smb_block_tag = NULL;
1300	}
1301
1302	if (sc->age_cdata.age_buffer_tag != NULL) {
1303		bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag);
1304		sc->age_cdata.age_buffer_tag = NULL;
1305	}
1306	if (sc->age_cdata.age_parent_tag != NULL) {
1307		bus_dma_tag_destroy(sc->age_cdata.age_parent_tag);
1308		sc->age_cdata.age_parent_tag = NULL;
1309	}
1310}
1311
1312/*
1313 *	Make sure the interface is stopped at reboot time.
1314 */
1315static int
1316age_shutdown(device_t dev)
1317{
1318
1319	return (age_suspend(dev));
1320}
1321
1322static void
1323age_setwol(struct age_softc *sc)
1324{
1325	struct ifnet *ifp;
1326	struct mii_data *mii;
1327	uint32_t reg, pmcs;
1328	uint16_t pmstat;
1329	int aneg, i, pmc;
1330
1331	AGE_LOCK_ASSERT(sc);
1332
1333	if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) {
1334		CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
1335		/*
1336		 * No PME capability, PHY power down.
1337		 * XXX
1338		 * Due to an unknown reason powering down PHY resulted
1339		 * in unexpected results such as inaccessbility of
1340		 * hardware of freshly rebooted system. Disable
1341		 * powering down PHY until I got more information for
1342		 * Attansic/Atheros PHY hardwares.
1343		 */
1344#ifdef notyet
1345		age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1346		    MII_BMCR, BMCR_PDOWN);
1347#endif
1348		return;
1349	}
1350
1351	ifp = sc->age_ifp;
1352	if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1353		/*
1354		 * Note, this driver resets the link speed to 10/100Mbps with
1355		 * auto-negotiation but we don't know whether that operation
1356		 * would succeed or not as it have no control after powering
1357		 * off. If the renegotiation fail WOL may not work. Running
1358		 * at 1Gbps will draw more power than 375mA at 3.3V which is
1359		 * specified in PCI specification and that would result in
1360		 * complete shutdowning power to ethernet controller.
1361		 *
1362		 * TODO
1363		 *  Save current negotiated media speed/duplex/flow-control
1364		 *  to softc and restore the same link again after resuming.
1365		 *  PHY handling such as power down/resetting to 100Mbps
1366		 *  may be better handled in suspend method in phy driver.
1367		 */
1368		mii = device_get_softc(sc->age_miibus);
1369		mii_pollstat(mii);
1370		aneg = 0;
1371		if ((mii->mii_media_status & IFM_AVALID) != 0) {
1372			switch IFM_SUBTYPE(mii->mii_media_active) {
1373			case IFM_10_T:
1374			case IFM_100_TX:
1375				goto got_link;
1376			case IFM_1000_T:
1377				aneg++;
1378			default:
1379				break;
1380			}
1381		}
1382		age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1383		    MII_100T2CR, 0);
1384		age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1385		    MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD |
1386		    ANAR_10 | ANAR_CSMA);
1387		age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1388		    MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1389		DELAY(1000);
1390		if (aneg != 0) {
1391			/* Poll link state until age(4) get a 10/100 link. */
1392			for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1393				mii_pollstat(mii);
1394				if ((mii->mii_media_status & IFM_AVALID) != 0) {
1395					switch (IFM_SUBTYPE(
1396					    mii->mii_media_active)) {
1397					case IFM_10_T:
1398					case IFM_100_TX:
1399						age_mac_config(sc);
1400						goto got_link;
1401					default:
1402						break;
1403					}
1404				}
1405				AGE_UNLOCK(sc);
1406				pause("agelnk", hz);
1407				AGE_LOCK(sc);
1408			}
1409			if (i == MII_ANEGTICKS_GIGE)
1410				device_printf(sc->age_dev,
1411				    "establishing link failed, "
1412				    "WOL may not work!");
1413		}
1414		/*
1415		 * No link, force MAC to have 100Mbps, full-duplex link.
1416		 * This is the last resort and may/may not work.
1417		 */
1418		mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1419		mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1420		age_mac_config(sc);
1421	}
1422
1423got_link:
1424	pmcs = 0;
1425	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1426		pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1427	CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs);
1428	reg = CSR_READ_4(sc, AGE_MAC_CFG);
1429	reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC);
1430	reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST);
1431	if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1432		reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1433	if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1434		reg |= MAC_CFG_RX_ENB;
1435		CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1436	}
1437
1438	/* Request PME. */
1439	pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2);
1440	pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1441	if ((ifp->if_capenable & IFCAP_WOL) != 0)
1442		pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1443	pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1444#ifdef notyet
1445	/* See above for powering down PHY issues. */
1446	if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1447		/* No WOL, PHY power down. */
1448		age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1449		    MII_BMCR, BMCR_PDOWN);
1450	}
1451#endif
1452}
1453
1454static int
1455age_suspend(device_t dev)
1456{
1457	struct age_softc *sc;
1458
1459	sc = device_get_softc(dev);
1460
1461	AGE_LOCK(sc);
1462	age_stop(sc);
1463	age_setwol(sc);
1464	AGE_UNLOCK(sc);
1465
1466	return (0);
1467}
1468
1469static int
1470age_resume(device_t dev)
1471{
1472	struct age_softc *sc;
1473	struct ifnet *ifp;
1474
1475	sc = device_get_softc(dev);
1476
1477	AGE_LOCK(sc);
1478	age_phy_reset(sc);
1479	ifp = sc->age_ifp;
1480	if ((ifp->if_flags & IFF_UP) != 0)
1481		age_init_locked(sc);
1482
1483	AGE_UNLOCK(sc);
1484
1485	return (0);
1486}
1487
1488static int
1489age_encap(struct age_softc *sc, struct mbuf **m_head)
1490{
1491	struct age_txdesc *txd, *txd_last;
1492	struct tx_desc *desc;
1493	struct mbuf *m;
1494	struct ip *ip;
1495	struct tcphdr *tcp;
1496	bus_dma_segment_t txsegs[AGE_MAXTXSEGS];
1497	bus_dmamap_t map;
1498	uint32_t cflags, hdrlen, ip_off, poff, vtag;
1499	int error, i, nsegs, prod, si;
1500
1501	AGE_LOCK_ASSERT(sc);
1502
1503	M_ASSERTPKTHDR((*m_head));
1504
1505	m = *m_head;
1506	ip = NULL;
1507	tcp = NULL;
1508	cflags = vtag = 0;
1509	ip_off = poff = 0;
1510	if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1511		/*
1512		 * L1 requires offset of TCP/UDP payload in its Tx
1513		 * descriptor to perform hardware Tx checksum offload.
1514		 * Additionally, TSO requires IP/TCP header size and
1515		 * modification of IP/TCP header in order to make TSO
1516		 * engine work. This kind of operation takes many CPU
1517		 * cycles on FreeBSD so fast host CPU is needed to get
1518		 * smooth TSO performance.
1519		 */
1520		struct ether_header *eh;
1521
1522		if (M_WRITABLE(m) == 0) {
1523			/* Get a writable copy. */
1524			m = m_dup(*m_head, M_NOWAIT);
1525			/* Release original mbufs. */
1526			m_freem(*m_head);
1527			if (m == NULL) {
1528				*m_head = NULL;
1529				return (ENOBUFS);
1530			}
1531			*m_head = m;
1532		}
1533		ip_off = sizeof(struct ether_header);
1534		m = m_pullup(m, ip_off);
1535		if (m == NULL) {
1536			*m_head = NULL;
1537			return (ENOBUFS);
1538		}
1539		eh = mtod(m, struct ether_header *);
1540		/*
1541		 * Check if hardware VLAN insertion is off.
1542		 * Additional check for LLC/SNAP frame?
1543		 */
1544		if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1545			ip_off = sizeof(struct ether_vlan_header);
1546			m = m_pullup(m, ip_off);
1547			if (m == NULL) {
1548				*m_head = NULL;
1549				return (ENOBUFS);
1550			}
1551		}
1552		m = m_pullup(m, ip_off + sizeof(struct ip));
1553		if (m == NULL) {
1554			*m_head = NULL;
1555			return (ENOBUFS);
1556		}
1557		ip = (struct ip *)(mtod(m, char *) + ip_off);
1558		poff = ip_off + (ip->ip_hl << 2);
1559		if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1560			m = m_pullup(m, poff + sizeof(struct tcphdr));
1561			if (m == NULL) {
1562				*m_head = NULL;
1563				return (ENOBUFS);
1564			}
1565			tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1566			m = m_pullup(m, poff + (tcp->th_off << 2));
1567			if (m == NULL) {
1568				*m_head = NULL;
1569				return (ENOBUFS);
1570			}
1571			/*
1572			 * L1 requires IP/TCP header size and offset as
1573			 * well as TCP pseudo checksum which complicates
1574			 * TSO configuration. I guess this comes from the
1575			 * adherence to Microsoft NDIS Large Send
1576			 * specification which requires insertion of
1577			 * pseudo checksum by upper stack. The pseudo
1578			 * checksum that NDIS refers to doesn't include
1579			 * TCP payload length so age(4) should recompute
1580			 * the pseudo checksum here. Hopefully this wouldn't
1581			 * be much burden on modern CPUs.
1582			 * Reset IP checksum and recompute TCP pseudo
1583			 * checksum as NDIS specification said.
1584			 */
1585			ip = (struct ip *)(mtod(m, char *) + ip_off);
1586			tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1587			ip->ip_sum = 0;
1588			tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1589			    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1590		}
1591		*m_head = m;
1592	}
1593
1594	si = prod = sc->age_cdata.age_tx_prod;
1595	txd = &sc->age_cdata.age_txdesc[prod];
1596	txd_last = txd;
1597	map = txd->tx_dmamap;
1598
1599	error =  bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1600	    *m_head, txsegs, &nsegs, 0);
1601	if (error == EFBIG) {
1602		m = m_collapse(*m_head, M_NOWAIT, AGE_MAXTXSEGS);
1603		if (m == NULL) {
1604			m_freem(*m_head);
1605			*m_head = NULL;
1606			return (ENOMEM);
1607		}
1608		*m_head = m;
1609		error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1610		    *m_head, txsegs, &nsegs, 0);
1611		if (error != 0) {
1612			m_freem(*m_head);
1613			*m_head = NULL;
1614			return (error);
1615		}
1616	} else if (error != 0)
1617		return (error);
1618	if (nsegs == 0) {
1619		m_freem(*m_head);
1620		*m_head = NULL;
1621		return (EIO);
1622	}
1623
1624	/* Check descriptor overrun. */
1625	if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) {
1626		bus_dmamap_unload(sc->age_cdata.age_tx_tag, map);
1627		return (ENOBUFS);
1628	}
1629
1630	m = *m_head;
1631	/* Configure VLAN hardware tag insertion. */
1632	if ((m->m_flags & M_VLANTAG) != 0) {
1633		vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1634		vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK);
1635		cflags |= AGE_TD_INSERT_VLAN_TAG;
1636	}
1637
1638	desc = NULL;
1639	i = 0;
1640	if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1641		/* Request TSO and set MSS. */
1642		cflags |= AGE_TD_TSO_IPV4;
1643		cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM;
1644		cflags |= ((uint32_t)m->m_pkthdr.tso_segsz <<
1645		    AGE_TD_TSO_MSS_SHIFT);
1646		/* Set IP/TCP header size. */
1647		cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT;
1648		cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT;
1649		/*
1650		 * L1 requires the first buffer should only hold IP/TCP
1651		 * header data. TCP payload should be handled in other
1652		 * descriptors.
1653		 */
1654		hdrlen = poff + (tcp->th_off << 2);
1655		desc = &sc->age_rdata.age_tx_ring[prod];
1656		desc->addr = htole64(txsegs[0].ds_addr);
1657		desc->len = htole32(AGE_TX_BYTES(hdrlen) | vtag);
1658		desc->flags = htole32(cflags);
1659		sc->age_cdata.age_tx_cnt++;
1660		AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1661		if (m->m_len - hdrlen > 0) {
1662			/* Handle remaining payload of the 1st fragment. */
1663			desc = &sc->age_rdata.age_tx_ring[prod];
1664			desc->addr = htole64(txsegs[0].ds_addr + hdrlen);
1665			desc->len = htole32(AGE_TX_BYTES(m->m_len - hdrlen) |
1666			    vtag);
1667			desc->flags = htole32(cflags);
1668			sc->age_cdata.age_tx_cnt++;
1669			AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1670		}
1671		/* Handle remaining fragments. */
1672		i = 1;
1673	} else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) {
1674		/* Configure Tx IP/TCP/UDP checksum offload. */
1675		cflags |= AGE_TD_CSUM;
1676		if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1677			cflags |= AGE_TD_TCPCSUM;
1678		if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1679			cflags |= AGE_TD_UDPCSUM;
1680		/* Set checksum start offset. */
1681		cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT);
1682		/* Set checksum insertion position of TCP/UDP. */
1683		cflags |= ((poff + m->m_pkthdr.csum_data) <<
1684		    AGE_TD_CSUM_XSUMOFFSET_SHIFT);
1685	}
1686	for (; i < nsegs; i++) {
1687		desc = &sc->age_rdata.age_tx_ring[prod];
1688		desc->addr = htole64(txsegs[i].ds_addr);
1689		desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag);
1690		desc->flags = htole32(cflags);
1691		sc->age_cdata.age_tx_cnt++;
1692		AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1693	}
1694	/* Update producer index. */
1695	sc->age_cdata.age_tx_prod = prod;
1696
1697	/* Set EOP on the last descriptor. */
1698	prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT;
1699	desc = &sc->age_rdata.age_tx_ring[prod];
1700	desc->flags |= htole32(AGE_TD_EOP);
1701
1702	/* Lastly set TSO header and modify IP/TCP header for TSO operation. */
1703	if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1704		desc = &sc->age_rdata.age_tx_ring[si];
1705		desc->flags |= htole32(AGE_TD_TSO_HDR);
1706	}
1707
1708	/* Swap dmamap of the first and the last. */
1709	txd = &sc->age_cdata.age_txdesc[prod];
1710	map = txd_last->tx_dmamap;
1711	txd_last->tx_dmamap = txd->tx_dmamap;
1712	txd->tx_dmamap = map;
1713	txd->tx_m = m;
1714
1715	/* Sync descriptors. */
1716	bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE);
1717	bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
1718	    sc->age_cdata.age_tx_ring_map,
1719	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1720
1721	return (0);
1722}
1723
1724static void
1725age_start(struct ifnet *ifp)
1726{
1727        struct age_softc *sc;
1728
1729	sc = ifp->if_softc;
1730	AGE_LOCK(sc);
1731	age_start_locked(ifp);
1732	AGE_UNLOCK(sc);
1733}
1734
1735static void
1736age_start_locked(struct ifnet *ifp)
1737{
1738        struct age_softc *sc;
1739        struct mbuf *m_head;
1740	int enq;
1741
1742	sc = ifp->if_softc;
1743
1744	AGE_LOCK_ASSERT(sc);
1745
1746	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1747	    IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0)
1748		return;
1749
1750	for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1751		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1752		if (m_head == NULL)
1753			break;
1754		/*
1755		 * Pack the data into the transmit ring. If we
1756		 * don't have room, set the OACTIVE flag and wait
1757		 * for the NIC to drain the ring.
1758		 */
1759		if (age_encap(sc, &m_head)) {
1760			if (m_head == NULL)
1761				break;
1762			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1763			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1764			break;
1765		}
1766
1767		enq++;
1768		/*
1769		 * If there's a BPF listener, bounce a copy of this frame
1770		 * to him.
1771		 */
1772		ETHER_BPF_MTAP(ifp, m_head);
1773	}
1774
1775	if (enq > 0) {
1776		/* Update mbox. */
1777		AGE_COMMIT_MBOX(sc);
1778		/* Set a timeout in case the chip goes out to lunch. */
1779		sc->age_watchdog_timer = AGE_TX_TIMEOUT;
1780	}
1781}
1782
1783static void
1784age_watchdog(struct age_softc *sc)
1785{
1786	struct ifnet *ifp;
1787
1788	AGE_LOCK_ASSERT(sc);
1789
1790	if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer)
1791		return;
1792
1793	ifp = sc->age_ifp;
1794	if ((sc->age_flags & AGE_FLAG_LINK) == 0) {
1795		if_printf(sc->age_ifp, "watchdog timeout (missed link)\n");
1796		if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1797		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1798		age_init_locked(sc);
1799		return;
1800	}
1801	if (sc->age_cdata.age_tx_cnt == 0) {
1802		if_printf(sc->age_ifp,
1803		    "watchdog timeout (missed Tx interrupts) -- recovering\n");
1804		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1805			age_start_locked(ifp);
1806		return;
1807	}
1808	if_printf(sc->age_ifp, "watchdog timeout\n");
1809	if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1810	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1811	age_init_locked(sc);
1812	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1813		age_start_locked(ifp);
1814}
1815
1816static int
1817age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1818{
1819	struct age_softc *sc;
1820	struct ifreq *ifr;
1821	struct mii_data *mii;
1822	uint32_t reg;
1823	int error, mask;
1824
1825	sc = ifp->if_softc;
1826	ifr = (struct ifreq *)data;
1827	error = 0;
1828	switch (cmd) {
1829	case SIOCSIFMTU:
1830		if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU)
1831			error = EINVAL;
1832		else if (ifp->if_mtu != ifr->ifr_mtu) {
1833			AGE_LOCK(sc);
1834			ifp->if_mtu = ifr->ifr_mtu;
1835			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1836				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1837				age_init_locked(sc);
1838			}
1839			AGE_UNLOCK(sc);
1840		}
1841		break;
1842	case SIOCSIFFLAGS:
1843		AGE_LOCK(sc);
1844		if ((ifp->if_flags & IFF_UP) != 0) {
1845			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1846				if (((ifp->if_flags ^ sc->age_if_flags)
1847				    & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1848					age_rxfilter(sc);
1849			} else {
1850				if ((sc->age_flags & AGE_FLAG_DETACH) == 0)
1851					age_init_locked(sc);
1852			}
1853		} else {
1854			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1855				age_stop(sc);
1856		}
1857		sc->age_if_flags = ifp->if_flags;
1858		AGE_UNLOCK(sc);
1859		break;
1860	case SIOCADDMULTI:
1861	case SIOCDELMULTI:
1862		AGE_LOCK(sc);
1863		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1864			age_rxfilter(sc);
1865		AGE_UNLOCK(sc);
1866		break;
1867	case SIOCSIFMEDIA:
1868	case SIOCGIFMEDIA:
1869		mii = device_get_softc(sc->age_miibus);
1870		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1871		break;
1872	case SIOCSIFCAP:
1873		AGE_LOCK(sc);
1874		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1875		if ((mask & IFCAP_TXCSUM) != 0 &&
1876		    (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1877			ifp->if_capenable ^= IFCAP_TXCSUM;
1878			if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1879				ifp->if_hwassist |= AGE_CSUM_FEATURES;
1880			else
1881				ifp->if_hwassist &= ~AGE_CSUM_FEATURES;
1882		}
1883		if ((mask & IFCAP_RXCSUM) != 0 &&
1884		    (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
1885			ifp->if_capenable ^= IFCAP_RXCSUM;
1886			reg = CSR_READ_4(sc, AGE_MAC_CFG);
1887			reg &= ~MAC_CFG_RXCSUM_ENB;
1888			if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1889				reg |= MAC_CFG_RXCSUM_ENB;
1890			CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1891		}
1892		if ((mask & IFCAP_TSO4) != 0 &&
1893		    (ifp->if_capabilities & IFCAP_TSO4) != 0) {
1894			ifp->if_capenable ^= IFCAP_TSO4;
1895			if ((ifp->if_capenable & IFCAP_TSO4) != 0)
1896				ifp->if_hwassist |= CSUM_TSO;
1897			else
1898				ifp->if_hwassist &= ~CSUM_TSO;
1899		}
1900
1901		if ((mask & IFCAP_WOL_MCAST) != 0 &&
1902		    (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
1903			ifp->if_capenable ^= IFCAP_WOL_MCAST;
1904		if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1905		    (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
1906			ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1907		if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1908		    (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
1909			ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1910		if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1911		    (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
1912			ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1913		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1914		    (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
1915			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1916			if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
1917				ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
1918			age_rxvlan(sc);
1919		}
1920		AGE_UNLOCK(sc);
1921		VLAN_CAPABILITIES(ifp);
1922		break;
1923	default:
1924		error = ether_ioctl(ifp, cmd, data);
1925		break;
1926	}
1927
1928	return (error);
1929}
1930
1931static void
1932age_mac_config(struct age_softc *sc)
1933{
1934	struct mii_data *mii;
1935	uint32_t reg;
1936
1937	AGE_LOCK_ASSERT(sc);
1938
1939	mii = device_get_softc(sc->age_miibus);
1940	reg = CSR_READ_4(sc, AGE_MAC_CFG);
1941	reg &= ~MAC_CFG_FULL_DUPLEX;
1942	reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC);
1943	reg &= ~MAC_CFG_SPEED_MASK;
1944	/* Reprogram MAC with resolved speed/duplex. */
1945	switch (IFM_SUBTYPE(mii->mii_media_active)) {
1946	case IFM_10_T:
1947	case IFM_100_TX:
1948		reg |= MAC_CFG_SPEED_10_100;
1949		break;
1950	case IFM_1000_T:
1951		reg |= MAC_CFG_SPEED_1000;
1952		break;
1953	}
1954	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1955		reg |= MAC_CFG_FULL_DUPLEX;
1956#ifdef notyet
1957		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1958			reg |= MAC_CFG_TX_FC;
1959		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1960			reg |= MAC_CFG_RX_FC;
1961#endif
1962	}
1963
1964	CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1965}
1966
1967static void
1968age_link_task(void *arg, int pending)
1969{
1970	struct age_softc *sc;
1971	struct mii_data *mii;
1972	struct ifnet *ifp;
1973	uint32_t reg;
1974
1975	sc = (struct age_softc *)arg;
1976
1977	AGE_LOCK(sc);
1978	mii = device_get_softc(sc->age_miibus);
1979	ifp = sc->age_ifp;
1980	if (mii == NULL || ifp == NULL ||
1981	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1982		AGE_UNLOCK(sc);
1983		return;
1984	}
1985
1986	sc->age_flags &= ~AGE_FLAG_LINK;
1987	if ((mii->mii_media_status & IFM_AVALID) != 0) {
1988		switch (IFM_SUBTYPE(mii->mii_media_active)) {
1989		case IFM_10_T:
1990		case IFM_100_TX:
1991		case IFM_1000_T:
1992			sc->age_flags |= AGE_FLAG_LINK;
1993			break;
1994		default:
1995			break;
1996		}
1997	}
1998
1999	/* Stop Rx/Tx MACs. */
2000	age_stop_rxmac(sc);
2001	age_stop_txmac(sc);
2002
2003	/* Program MACs with resolved speed/duplex/flow-control. */
2004	if ((sc->age_flags & AGE_FLAG_LINK) != 0) {
2005		age_mac_config(sc);
2006		reg = CSR_READ_4(sc, AGE_MAC_CFG);
2007		/* Restart DMA engine and Tx/Rx MAC. */
2008		CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |
2009		    DMA_CFG_RD_ENB | DMA_CFG_WR_ENB);
2010		reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
2011		CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2012	}
2013
2014	AGE_UNLOCK(sc);
2015}
2016
2017static void
2018age_stats_update(struct age_softc *sc)
2019{
2020	struct age_stats *stat;
2021	struct smb *smb;
2022	struct ifnet *ifp;
2023
2024	AGE_LOCK_ASSERT(sc);
2025
2026	stat = &sc->age_stat;
2027
2028	bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2029	    sc->age_cdata.age_smb_block_map,
2030	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2031
2032	smb = sc->age_rdata.age_smb_block;
2033	if (smb->updated == 0)
2034		return;
2035
2036	ifp = sc->age_ifp;
2037	/* Rx stats. */
2038	stat->rx_frames += smb->rx_frames;
2039	stat->rx_bcast_frames += smb->rx_bcast_frames;
2040	stat->rx_mcast_frames += smb->rx_mcast_frames;
2041	stat->rx_pause_frames += smb->rx_pause_frames;
2042	stat->rx_control_frames += smb->rx_control_frames;
2043	stat->rx_crcerrs += smb->rx_crcerrs;
2044	stat->rx_lenerrs += smb->rx_lenerrs;
2045	stat->rx_bytes += smb->rx_bytes;
2046	stat->rx_runts += smb->rx_runts;
2047	stat->rx_fragments += smb->rx_fragments;
2048	stat->rx_pkts_64 += smb->rx_pkts_64;
2049	stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2050	stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2051	stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2052	stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2053	stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2054	stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2055	stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2056	stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2057	stat->rx_desc_oflows += smb->rx_desc_oflows;
2058	stat->rx_alignerrs += smb->rx_alignerrs;
2059	stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2060	stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2061	stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2062
2063	/* Tx stats. */
2064	stat->tx_frames += smb->tx_frames;
2065	stat->tx_bcast_frames += smb->tx_bcast_frames;
2066	stat->tx_mcast_frames += smb->tx_mcast_frames;
2067	stat->tx_pause_frames += smb->tx_pause_frames;
2068	stat->tx_excess_defer += smb->tx_excess_defer;
2069	stat->tx_control_frames += smb->tx_control_frames;
2070	stat->tx_deferred += smb->tx_deferred;
2071	stat->tx_bytes += smb->tx_bytes;
2072	stat->tx_pkts_64 += smb->tx_pkts_64;
2073	stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2074	stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2075	stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2076	stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2077	stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2078	stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2079	stat->tx_single_colls += smb->tx_single_colls;
2080	stat->tx_multi_colls += smb->tx_multi_colls;
2081	stat->tx_late_colls += smb->tx_late_colls;
2082	stat->tx_excess_colls += smb->tx_excess_colls;
2083	stat->tx_underrun += smb->tx_underrun;
2084	stat->tx_desc_underrun += smb->tx_desc_underrun;
2085	stat->tx_lenerrs += smb->tx_lenerrs;
2086	stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2087	stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2088	stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2089
2090	/* Update counters in ifnet. */
2091	if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames);
2092
2093	if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls +
2094	    smb->tx_multi_colls + smb->tx_late_colls +
2095	    smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT);
2096
2097	if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_excess_colls +
2098	    smb->tx_late_colls + smb->tx_underrun +
2099	    smb->tx_pkts_truncated);
2100
2101	if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames);
2102
2103	if_inc_counter(ifp, IFCOUNTER_IERRORS, smb->rx_crcerrs +
2104	    smb->rx_lenerrs + smb->rx_runts + smb->rx_pkts_truncated +
2105	    smb->rx_fifo_oflows + smb->rx_desc_oflows +
2106	    smb->rx_alignerrs);
2107
2108	/* Update done, clear. */
2109	smb->updated = 0;
2110
2111	bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2112	    sc->age_cdata.age_smb_block_map,
2113	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2114}
2115
2116static int
2117age_intr(void *arg)
2118{
2119	struct age_softc *sc;
2120	uint32_t status;
2121
2122	sc = (struct age_softc *)arg;
2123
2124	status = CSR_READ_4(sc, AGE_INTR_STATUS);
2125	if (status == 0 || (status & AGE_INTRS) == 0)
2126		return (FILTER_STRAY);
2127	/* Disable interrupts. */
2128	CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT);
2129	taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2130
2131	return (FILTER_HANDLED);
2132}
2133
2134static void
2135age_int_task(void *arg, int pending)
2136{
2137	struct age_softc *sc;
2138	struct ifnet *ifp;
2139	struct cmb *cmb;
2140	uint32_t status;
2141
2142	sc = (struct age_softc *)arg;
2143
2144	AGE_LOCK(sc);
2145
2146	bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2147	    sc->age_cdata.age_cmb_block_map,
2148	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2149	cmb = sc->age_rdata.age_cmb_block;
2150	status = le32toh(cmb->intr_status);
2151	if (sc->age_morework != 0)
2152		status |= INTR_CMB_RX;
2153	if ((status & AGE_INTRS) == 0)
2154		goto done;
2155
2156	sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >>
2157	    TPD_CONS_SHIFT;
2158	sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >>
2159	    RRD_PROD_SHIFT;
2160	/* Let hardware know CMB was served. */
2161	cmb->intr_status = 0;
2162	bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2163	    sc->age_cdata.age_cmb_block_map,
2164	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2165
2166	ifp = sc->age_ifp;
2167	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2168		if ((status & INTR_CMB_RX) != 0)
2169			sc->age_morework = age_rxintr(sc, sc->age_rr_prod,
2170			    sc->age_process_limit);
2171		if ((status & INTR_CMB_TX) != 0)
2172			age_txintr(sc, sc->age_tpd_cons);
2173		if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2174			if ((status & INTR_DMA_RD_TO_RST) != 0)
2175				device_printf(sc->age_dev,
2176				    "DMA read error! -- resetting\n");
2177			if ((status & INTR_DMA_WR_TO_RST) != 0)
2178				device_printf(sc->age_dev,
2179				    "DMA write error! -- resetting\n");
2180			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2181			age_init_locked(sc);
2182		}
2183		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2184			age_start_locked(ifp);
2185		if ((status & INTR_SMB) != 0)
2186			age_stats_update(sc);
2187	}
2188
2189	/* Check whether CMB was updated while serving Tx/Rx/SMB handler. */
2190	bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2191	    sc->age_cdata.age_cmb_block_map,
2192	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2193	status = le32toh(cmb->intr_status);
2194	if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) {
2195		taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2196		AGE_UNLOCK(sc);
2197		return;
2198	}
2199
2200done:
2201	/* Re-enable interrupts. */
2202	CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2203	AGE_UNLOCK(sc);
2204}
2205
2206static void
2207age_txintr(struct age_softc *sc, int tpd_cons)
2208{
2209	struct ifnet *ifp;
2210	struct age_txdesc *txd;
2211	int cons, prog;
2212
2213	AGE_LOCK_ASSERT(sc);
2214
2215	ifp = sc->age_ifp;
2216
2217	bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2218	    sc->age_cdata.age_tx_ring_map,
2219	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2220
2221	/*
2222	 * Go through our Tx list and free mbufs for those
2223	 * frames which have been transmitted.
2224	 */
2225	cons = sc->age_cdata.age_tx_cons;
2226	for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) {
2227		if (sc->age_cdata.age_tx_cnt <= 0)
2228			break;
2229		prog++;
2230		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2231		sc->age_cdata.age_tx_cnt--;
2232		txd = &sc->age_cdata.age_txdesc[cons];
2233		/*
2234		 * Clear Tx descriptors, it's not required but would
2235		 * help debugging in case of Tx issues.
2236		 */
2237		txd->tx_desc->addr = 0;
2238		txd->tx_desc->len = 0;
2239		txd->tx_desc->flags = 0;
2240
2241		if (txd->tx_m == NULL)
2242			continue;
2243		/* Reclaim transmitted mbufs. */
2244		bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap,
2245		    BUS_DMASYNC_POSTWRITE);
2246		bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap);
2247		m_freem(txd->tx_m);
2248		txd->tx_m = NULL;
2249	}
2250
2251	if (prog > 0) {
2252		sc->age_cdata.age_tx_cons = cons;
2253
2254		/*
2255		 * Unarm watchdog timer only when there are no pending
2256		 * Tx descriptors in queue.
2257		 */
2258		if (sc->age_cdata.age_tx_cnt == 0)
2259			sc->age_watchdog_timer = 0;
2260		bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2261		    sc->age_cdata.age_tx_ring_map,
2262		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2263	}
2264}
2265
2266#ifndef __NO_STRICT_ALIGNMENT
2267static struct mbuf *
2268age_fixup_rx(struct ifnet *ifp, struct mbuf *m)
2269{
2270	struct mbuf *n;
2271        int i;
2272        uint16_t *src, *dst;
2273
2274	src = mtod(m, uint16_t *);
2275	dst = src - 3;
2276
2277	if (m->m_next == NULL) {
2278		for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
2279			*dst++ = *src++;
2280		m->m_data -= 6;
2281		return (m);
2282	}
2283	/*
2284	 * Append a new mbuf to received mbuf chain and copy ethernet
2285	 * header from the mbuf chain. This can save lots of CPU
2286	 * cycles for jumbo frame.
2287	 */
2288	MGETHDR(n, M_NOWAIT, MT_DATA);
2289	if (n == NULL) {
2290		if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2291		m_freem(m);
2292		return (NULL);
2293	}
2294	bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
2295	m->m_data += ETHER_HDR_LEN;
2296	m->m_len -= ETHER_HDR_LEN;
2297	n->m_len = ETHER_HDR_LEN;
2298	M_MOVE_PKTHDR(n, m);
2299	n->m_next = m;
2300	return (n);
2301}
2302#endif
2303
2304/* Receive a frame. */
2305static void
2306age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd)
2307{
2308	struct age_rxdesc *rxd;
2309	struct ifnet *ifp;
2310	struct mbuf *mp, *m;
2311	uint32_t status, index, vtag;
2312	int count, nsegs;
2313	int rx_cons;
2314
2315	AGE_LOCK_ASSERT(sc);
2316
2317	ifp = sc->age_ifp;
2318	status = le32toh(rxrd->flags);
2319	index = le32toh(rxrd->index);
2320	rx_cons = AGE_RX_CONS(index);
2321	nsegs = AGE_RX_NSEGS(index);
2322
2323	sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len));
2324	if ((status & (AGE_RRD_ERROR | AGE_RRD_LENGTH_NOK)) != 0) {
2325		/*
2326		 * We want to pass the following frames to upper
2327		 * layer regardless of error status of Rx return
2328		 * ring.
2329		 *
2330		 *  o IP/TCP/UDP checksum is bad.
2331		 *  o frame length and protocol specific length
2332		 *     does not match.
2333		 */
2334		status |= AGE_RRD_IPCSUM_NOK | AGE_RRD_TCP_UDPCSUM_NOK;
2335		if ((status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE |
2336		    AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0)
2337			return;
2338	}
2339
2340	for (count = 0; count < nsegs; count++,
2341	    AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) {
2342		rxd = &sc->age_cdata.age_rxdesc[rx_cons];
2343		mp = rxd->rx_m;
2344		/* Add a new receive buffer to the ring. */
2345		if (age_newbuf(sc, rxd) != 0) {
2346			if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2347			/* Reuse Rx buffers. */
2348			if (sc->age_cdata.age_rxhead != NULL)
2349				m_freem(sc->age_cdata.age_rxhead);
2350			break;
2351		}
2352
2353		/*
2354		 * Assume we've received a full sized frame.
2355		 * Actual size is fixed when we encounter the end of
2356		 * multi-segmented frame.
2357		 */
2358		mp->m_len = AGE_RX_BUF_SIZE;
2359
2360		/* Chain received mbufs. */
2361		if (sc->age_cdata.age_rxhead == NULL) {
2362			sc->age_cdata.age_rxhead = mp;
2363			sc->age_cdata.age_rxtail = mp;
2364		} else {
2365			mp->m_flags &= ~M_PKTHDR;
2366			sc->age_cdata.age_rxprev_tail =
2367			    sc->age_cdata.age_rxtail;
2368			sc->age_cdata.age_rxtail->m_next = mp;
2369			sc->age_cdata.age_rxtail = mp;
2370		}
2371
2372		if (count == nsegs - 1) {
2373			/* Last desc. for this frame. */
2374			m = sc->age_cdata.age_rxhead;
2375			m->m_flags |= M_PKTHDR;
2376			/*
2377			 * It seems that L1 controller has no way
2378			 * to tell hardware to strip CRC bytes.
2379			 */
2380			m->m_pkthdr.len = sc->age_cdata.age_rxlen -
2381			    ETHER_CRC_LEN;
2382			if (nsegs > 1) {
2383				/* Set last mbuf size. */
2384				mp->m_len = sc->age_cdata.age_rxlen -
2385				    ((nsegs - 1) * AGE_RX_BUF_SIZE);
2386				/* Remove the CRC bytes in chained mbufs. */
2387				if (mp->m_len <= ETHER_CRC_LEN) {
2388					sc->age_cdata.age_rxtail =
2389					    sc->age_cdata.age_rxprev_tail;
2390					sc->age_cdata.age_rxtail->m_len -=
2391					    (ETHER_CRC_LEN - mp->m_len);
2392					sc->age_cdata.age_rxtail->m_next = NULL;
2393					m_freem(mp);
2394				} else {
2395					mp->m_len -= ETHER_CRC_LEN;
2396				}
2397			} else
2398				m->m_len = m->m_pkthdr.len;
2399			m->m_pkthdr.rcvif = ifp;
2400			/*
2401			 * Set checksum information.
2402			 * It seems that L1 controller can compute partial
2403			 * checksum. The partial checksum value can be used
2404			 * to accelerate checksum computation for fragmented
2405			 * TCP/UDP packets. Upper network stack already
2406			 * takes advantage of the partial checksum value in
2407			 * IP reassembly stage. But I'm not sure the
2408			 * correctness of the partial hardware checksum
2409			 * assistance due to lack of data sheet. If it is
2410			 * proven to work on L1 I'll enable it.
2411			 */
2412			if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2413			    (status & AGE_RRD_IPV4) != 0) {
2414				if ((status & AGE_RRD_IPCSUM_NOK) == 0)
2415					m->m_pkthdr.csum_flags |=
2416					    CSUM_IP_CHECKED | CSUM_IP_VALID;
2417				if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) &&
2418				    (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) {
2419					m->m_pkthdr.csum_flags |=
2420					    CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2421					m->m_pkthdr.csum_data = 0xffff;
2422				}
2423				/*
2424				 * Don't mark bad checksum for TCP/UDP frames
2425				 * as fragmented frames may always have set
2426				 * bad checksummed bit of descriptor status.
2427				 */
2428			}
2429
2430			/* Check for VLAN tagged frames. */
2431			if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2432			    (status & AGE_RRD_VLAN) != 0) {
2433				vtag = AGE_RX_VLAN(le32toh(rxrd->vtags));
2434				m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag);
2435				m->m_flags |= M_VLANTAG;
2436			}
2437#ifndef __NO_STRICT_ALIGNMENT
2438			m = age_fixup_rx(ifp, m);
2439			if (m != NULL)
2440#endif
2441			{
2442			/* Pass it on. */
2443			AGE_UNLOCK(sc);
2444			(*ifp->if_input)(ifp, m);
2445			AGE_LOCK(sc);
2446			}
2447		}
2448	}
2449
2450	/* Reset mbuf chains. */
2451	AGE_RXCHAIN_RESET(sc);
2452}
2453
2454static int
2455age_rxintr(struct age_softc *sc, int rr_prod, int count)
2456{
2457	struct rx_rdesc *rxrd;
2458	int rr_cons, nsegs, pktlen, prog;
2459
2460	AGE_LOCK_ASSERT(sc);
2461
2462	rr_cons = sc->age_cdata.age_rr_cons;
2463	if (rr_cons == rr_prod)
2464		return (0);
2465
2466	bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2467	    sc->age_cdata.age_rr_ring_map,
2468	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2469	bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
2470	    sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE);
2471
2472	for (prog = 0; rr_cons != rr_prod; prog++) {
2473		if (count-- <= 0)
2474			break;
2475		rxrd = &sc->age_rdata.age_rr_ring[rr_cons];
2476		nsegs = AGE_RX_NSEGS(le32toh(rxrd->index));
2477		if (nsegs == 0)
2478			break;
2479		/*
2480		 * Check number of segments against received bytes.
2481		 * Non-matching value would indicate that hardware
2482		 * is still trying to update Rx return descriptors.
2483		 * I'm not sure whether this check is really needed.
2484		 */
2485		pktlen = AGE_RX_BYTES(le32toh(rxrd->len));
2486		if (nsegs != howmany(pktlen, AGE_RX_BUF_SIZE))
2487			break;
2488
2489		/* Received a frame. */
2490		age_rxeof(sc, rxrd);
2491		/* Clear return ring. */
2492		rxrd->index = 0;
2493		AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT);
2494		sc->age_cdata.age_rx_cons += nsegs;
2495		sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT;
2496	}
2497
2498	if (prog > 0) {
2499		/* Update the consumer index. */
2500		sc->age_cdata.age_rr_cons = rr_cons;
2501
2502		bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
2503		    sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE);
2504		/* Sync descriptors. */
2505		bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2506		    sc->age_cdata.age_rr_ring_map,
2507		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2508
2509		/* Notify hardware availability of new Rx buffers. */
2510		AGE_COMMIT_MBOX(sc);
2511	}
2512
2513	return (count > 0 ? 0 : EAGAIN);
2514}
2515
2516static void
2517age_tick(void *arg)
2518{
2519	struct age_softc *sc;
2520	struct mii_data *mii;
2521
2522	sc = (struct age_softc *)arg;
2523
2524	AGE_LOCK_ASSERT(sc);
2525
2526	mii = device_get_softc(sc->age_miibus);
2527	mii_tick(mii);
2528	age_watchdog(sc);
2529	callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2530}
2531
2532static void
2533age_reset(struct age_softc *sc)
2534{
2535	uint32_t reg;
2536	int i;
2537
2538	CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET);
2539	CSR_READ_4(sc, AGE_MASTER_CFG);
2540	DELAY(1000);
2541	for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2542		if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2543			break;
2544		DELAY(10);
2545	}
2546
2547	if (i == 0)
2548		device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg);
2549	/* Initialize PCIe module. From Linux. */
2550	CSR_WRITE_4(sc, 0x12FC, 0x6500);
2551	CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2552}
2553
2554static void
2555age_init(void *xsc)
2556{
2557	struct age_softc *sc;
2558
2559	sc = (struct age_softc *)xsc;
2560	AGE_LOCK(sc);
2561	age_init_locked(sc);
2562	AGE_UNLOCK(sc);
2563}
2564
2565static void
2566age_init_locked(struct age_softc *sc)
2567{
2568	struct ifnet *ifp;
2569	struct mii_data *mii;
2570	uint8_t eaddr[ETHER_ADDR_LEN];
2571	bus_addr_t paddr;
2572	uint32_t reg, fsize;
2573	uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo;
2574	int error;
2575
2576	AGE_LOCK_ASSERT(sc);
2577
2578	ifp = sc->age_ifp;
2579	mii = device_get_softc(sc->age_miibus);
2580
2581	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2582		return;
2583
2584	/*
2585	 * Cancel any pending I/O.
2586	 */
2587	age_stop(sc);
2588
2589	/*
2590	 * Reset the chip to a known state.
2591	 */
2592	age_reset(sc);
2593
2594	/* Initialize descriptors. */
2595	error = age_init_rx_ring(sc);
2596        if (error != 0) {
2597                device_printf(sc->age_dev, "no memory for Rx buffers.\n");
2598                age_stop(sc);
2599		return;
2600        }
2601	age_init_rr_ring(sc);
2602	age_init_tx_ring(sc);
2603	age_init_cmb_block(sc);
2604	age_init_smb_block(sc);
2605
2606	/* Reprogram the station address. */
2607	bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2608	CSR_WRITE_4(sc, AGE_PAR0,
2609	    eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2610	CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]);
2611
2612	/* Set descriptor base addresses. */
2613	paddr = sc->age_rdata.age_tx_ring_paddr;
2614	CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr));
2615	paddr = sc->age_rdata.age_rx_ring_paddr;
2616	CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr));
2617	paddr = sc->age_rdata.age_rr_ring_paddr;
2618	CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr));
2619	paddr = sc->age_rdata.age_tx_ring_paddr;
2620	CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr));
2621	paddr = sc->age_rdata.age_cmb_block_paddr;
2622	CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr));
2623	paddr = sc->age_rdata.age_smb_block_paddr;
2624	CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr));
2625	/* Set Rx/Rx return descriptor counter. */
2626	CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT,
2627	    ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) &
2628	    DESC_RRD_CNT_MASK) |
2629	    ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK));
2630	/* Set Tx descriptor counter. */
2631	CSR_WRITE_4(sc, AGE_DESC_TPD_CNT,
2632	    (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK);
2633
2634	/* Tell hardware that we're ready to load descriptors. */
2635	CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD);
2636
2637	/*
2638	 * Initialize mailbox register.
2639	 * Updated producer/consumer index information is exchanged
2640	 * through this mailbox register. However Tx producer and
2641	 * Rx return consumer/Rx producer are all shared such that
2642	 * it's hard to separate code path between Tx and Rx without
2643	 * locking. If L1 hardware have a separate mail box register
2644	 * for Tx and Rx consumer/producer management we could have
2645	 * indepent Tx/Rx handler which in turn Rx handler could have
2646	 * been run without any locking.
2647	 */
2648	AGE_COMMIT_MBOX(sc);
2649
2650	/* Configure IPG/IFG parameters. */
2651	CSR_WRITE_4(sc, AGE_IPG_IFG_CFG,
2652	    ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) |
2653	    ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2654	    ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2655	    ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK));
2656
2657	/* Set parameters for half-duplex media. */
2658	CSR_WRITE_4(sc, AGE_HDPX_CFG,
2659	    ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2660	    HDPX_CFG_LCOL_MASK) |
2661	    ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2662	    HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2663	    ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2664	    HDPX_CFG_ABEBT_MASK) |
2665	    ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2666	    HDPX_CFG_JAMIPG_MASK));
2667
2668	/* Configure interrupt moderation timer. */
2669	CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod));
2670	reg = CSR_READ_4(sc, AGE_MASTER_CFG);
2671	reg &= ~MASTER_MTIMER_ENB;
2672	if (AGE_USECS(sc->age_int_mod) == 0)
2673		reg &= ~MASTER_ITIMER_ENB;
2674	else
2675		reg |= MASTER_ITIMER_ENB;
2676	CSR_WRITE_4(sc, AGE_MASTER_CFG, reg);
2677	if (bootverbose)
2678		device_printf(sc->age_dev, "interrupt moderation is %d us.\n",
2679		    sc->age_int_mod);
2680	CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000));
2681
2682	/* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */
2683	if (ifp->if_mtu < ETHERMTU)
2684		sc->age_max_frame_size = ETHERMTU;
2685	else
2686		sc->age_max_frame_size = ifp->if_mtu;
2687	sc->age_max_frame_size += ETHER_HDR_LEN +
2688	    sizeof(struct ether_vlan_header) + ETHER_CRC_LEN;
2689	CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size);
2690	/* Configure jumbo frame. */
2691	fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t));
2692	CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG,
2693	    (((fsize / sizeof(uint64_t)) <<
2694	    RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) |
2695	    ((RXQ_JUMBO_CFG_LKAH_DEFAULT <<
2696	    RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) |
2697	    ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) &
2698	    RXQ_JUMBO_CFG_RRD_TIMER_MASK));
2699
2700	/* Configure flow-control parameters. From Linux. */
2701	if ((sc->age_flags & AGE_FLAG_PCIE) != 0) {
2702		/*
2703		 * Magic workaround for old-L1.
2704		 * Don't know which hw revision requires this magic.
2705		 */
2706		CSR_WRITE_4(sc, 0x12FC, 0x6500);
2707		/*
2708		 * Another magic workaround for flow-control mode
2709		 * change. From Linux.
2710		 */
2711		CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2712	}
2713	/*
2714	 * TODO
2715	 *  Should understand pause parameter relationships between FIFO
2716	 *  size and number of Rx descriptors and Rx return descriptors.
2717	 *
2718	 *  Magic parameters came from Linux.
2719	 */
2720	switch (sc->age_chip_rev) {
2721	case 0x8001:
2722	case 0x9001:
2723	case 0x9002:
2724	case 0x9003:
2725		rxf_hi = AGE_RX_RING_CNT / 16;
2726		rxf_lo = (AGE_RX_RING_CNT * 7) / 8;
2727		rrd_hi = (AGE_RR_RING_CNT * 7) / 8;
2728		rrd_lo = AGE_RR_RING_CNT / 16;
2729		break;
2730	default:
2731		reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);
2732		rxf_lo = reg / 16;
2733		if (rxf_lo < 192)
2734			rxf_lo = 192;
2735		rxf_hi = (reg * 7) / 8;
2736		if (rxf_hi < rxf_lo)
2737			rxf_hi = rxf_lo + 16;
2738		reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);
2739		rrd_lo = reg / 8;
2740		rrd_hi = (reg * 7) / 8;
2741		if (rrd_lo < 2)
2742			rrd_lo = 2;
2743		if (rrd_hi < rrd_lo)
2744			rrd_hi = rrd_lo + 3;
2745		break;
2746	}
2747	CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH,
2748	    ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) &
2749	    RXQ_FIFO_PAUSE_THRESH_LO_MASK) |
2750	    ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) &
2751	    RXQ_FIFO_PAUSE_THRESH_HI_MASK));
2752	CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH,
2753	    ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) &
2754	    RXQ_RRD_PAUSE_THRESH_LO_MASK) |
2755	    ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) &
2756	    RXQ_RRD_PAUSE_THRESH_HI_MASK));
2757
2758	/* Configure RxQ. */
2759	CSR_WRITE_4(sc, AGE_RXQ_CFG,
2760	    ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
2761	    RXQ_CFG_RD_BURST_MASK) |
2762	    ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT <<
2763	    RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) |
2764	    ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT <<
2765	    RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) |
2766	    RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2767
2768	/* Configure TxQ. */
2769	CSR_WRITE_4(sc, AGE_TXQ_CFG,
2770	    ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2771	    TXQ_CFG_TPD_BURST_MASK) |
2772	    ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) &
2773	    TXQ_CFG_TX_FIFO_BURST_MASK) |
2774	    ((TXQ_CFG_TPD_FETCH_DEFAULT <<
2775	    TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) |
2776	    TXQ_CFG_ENB);
2777
2778	CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG,
2779	    (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) &
2780	    TX_JUMBO_TPD_TH_MASK) |
2781	    ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) &
2782	    TX_JUMBO_TPD_IPG_MASK));
2783	/* Configure DMA parameters. */
2784	CSR_WRITE_4(sc, AGE_DMA_CFG,
2785	    DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 |
2786	    sc->age_dma_rd_burst | DMA_CFG_RD_ENB |
2787	    sc->age_dma_wr_burst | DMA_CFG_WR_ENB);
2788
2789	/* Configure CMB DMA write threshold. */
2790	CSR_WRITE_4(sc, AGE_CMB_WR_THRESH,
2791	    ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) &
2792	    CMB_WR_THRESH_RRD_MASK) |
2793	    ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) &
2794	    CMB_WR_THRESH_TPD_MASK));
2795
2796	/* Set CMB/SMB timer and enable them. */
2797	CSR_WRITE_4(sc, AGE_CMB_WR_TIMER,
2798	    ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) |
2799	    ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK));
2800	/* Request SMB updates for every seconds. */
2801	CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000));
2802	CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB);
2803
2804	/*
2805	 * Disable all WOL bits as WOL can interfere normal Rx
2806	 * operation.
2807	 */
2808	CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
2809
2810	/*
2811	 * Configure Tx/Rx MACs.
2812	 *  - Auto-padding for short frames.
2813	 *  - Enable CRC generation.
2814	 *  Start with full-duplex/1000Mbps media. Actual reconfiguration
2815	 *  of MAC is followed after link establishment.
2816	 */
2817	CSR_WRITE_4(sc, AGE_MAC_CFG,
2818	    MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD |
2819	    MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 |
2820	    ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2821	    MAC_CFG_PREAMBLE_MASK));
2822	/* Set up the receive filter. */
2823	age_rxfilter(sc);
2824	age_rxvlan(sc);
2825
2826	reg = CSR_READ_4(sc, AGE_MAC_CFG);
2827	if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2828		reg |= MAC_CFG_RXCSUM_ENB;
2829
2830	/* Ack all pending interrupts and clear it. */
2831	CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2832	CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS);
2833
2834	/* Finally enable Tx/Rx MAC. */
2835	CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2836
2837	sc->age_flags &= ~AGE_FLAG_LINK;
2838	/* Switch to the current media. */
2839	mii_mediachg(mii);
2840
2841	callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2842
2843	ifp->if_drv_flags |= IFF_DRV_RUNNING;
2844	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2845}
2846
2847static void
2848age_stop(struct age_softc *sc)
2849{
2850	struct ifnet *ifp;
2851	struct age_txdesc *txd;
2852	struct age_rxdesc *rxd;
2853	uint32_t reg;
2854	int i;
2855
2856	AGE_LOCK_ASSERT(sc);
2857	/*
2858	 * Mark the interface down and cancel the watchdog timer.
2859	 */
2860	ifp = sc->age_ifp;
2861	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2862	sc->age_flags &= ~AGE_FLAG_LINK;
2863	callout_stop(&sc->age_tick_ch);
2864	sc->age_watchdog_timer = 0;
2865
2866	/*
2867	 * Disable interrupts.
2868	 */
2869	CSR_WRITE_4(sc, AGE_INTR_MASK, 0);
2870	CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF);
2871	/* Stop CMB/SMB updates. */
2872	CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0);
2873	/* Stop Rx/Tx MAC. */
2874	age_stop_rxmac(sc);
2875	age_stop_txmac(sc);
2876	/* Stop DMA. */
2877	CSR_WRITE_4(sc, AGE_DMA_CFG,
2878	    CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB));
2879	/* Stop TxQ/RxQ. */
2880	CSR_WRITE_4(sc, AGE_TXQ_CFG,
2881	    CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB);
2882	CSR_WRITE_4(sc, AGE_RXQ_CFG,
2883	    CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB);
2884	for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2885		if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2886			break;
2887		DELAY(10);
2888	}
2889	if (i == 0)
2890		device_printf(sc->age_dev,
2891		    "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg);
2892
2893	 /* Reclaim Rx buffers that have been processed. */
2894	if (sc->age_cdata.age_rxhead != NULL)
2895		m_freem(sc->age_cdata.age_rxhead);
2896	AGE_RXCHAIN_RESET(sc);
2897	/*
2898	 * Free RX and TX mbufs still in the queues.
2899	 */
2900	for (i = 0; i < AGE_RX_RING_CNT; i++) {
2901		rxd = &sc->age_cdata.age_rxdesc[i];
2902		if (rxd->rx_m != NULL) {
2903			bus_dmamap_sync(sc->age_cdata.age_rx_tag,
2904			    rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2905			bus_dmamap_unload(sc->age_cdata.age_rx_tag,
2906			    rxd->rx_dmamap);
2907			m_freem(rxd->rx_m);
2908			rxd->rx_m = NULL;
2909		}
2910        }
2911	for (i = 0; i < AGE_TX_RING_CNT; i++) {
2912		txd = &sc->age_cdata.age_txdesc[i];
2913		if (txd->tx_m != NULL) {
2914			bus_dmamap_sync(sc->age_cdata.age_tx_tag,
2915			    txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2916			bus_dmamap_unload(sc->age_cdata.age_tx_tag,
2917			    txd->tx_dmamap);
2918			m_freem(txd->tx_m);
2919			txd->tx_m = NULL;
2920		}
2921        }
2922}
2923
2924static void
2925age_stop_txmac(struct age_softc *sc)
2926{
2927	uint32_t reg;
2928	int i;
2929
2930	AGE_LOCK_ASSERT(sc);
2931
2932	reg = CSR_READ_4(sc, AGE_MAC_CFG);
2933	if ((reg & MAC_CFG_TX_ENB) != 0) {
2934		reg &= ~MAC_CFG_TX_ENB;
2935		CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2936	}
2937	/* Stop Tx DMA engine. */
2938	reg = CSR_READ_4(sc, AGE_DMA_CFG);
2939	if ((reg & DMA_CFG_RD_ENB) != 0) {
2940		reg &= ~DMA_CFG_RD_ENB;
2941		CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2942	}
2943	for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2944		if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2945		    (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0)
2946			break;
2947		DELAY(10);
2948	}
2949	if (i == 0)
2950		device_printf(sc->age_dev, "stopping TxMAC timeout!\n");
2951}
2952
2953static void
2954age_stop_rxmac(struct age_softc *sc)
2955{
2956	uint32_t reg;
2957	int i;
2958
2959	AGE_LOCK_ASSERT(sc);
2960
2961	reg = CSR_READ_4(sc, AGE_MAC_CFG);
2962	if ((reg & MAC_CFG_RX_ENB) != 0) {
2963		reg &= ~MAC_CFG_RX_ENB;
2964		CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2965	}
2966	/* Stop Rx DMA engine. */
2967	reg = CSR_READ_4(sc, AGE_DMA_CFG);
2968	if ((reg & DMA_CFG_WR_ENB) != 0) {
2969		reg &= ~DMA_CFG_WR_ENB;
2970		CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2971	}
2972	for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2973		if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2974		    (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0)
2975			break;
2976		DELAY(10);
2977	}
2978	if (i == 0)
2979		device_printf(sc->age_dev, "stopping RxMAC timeout!\n");
2980}
2981
2982static void
2983age_init_tx_ring(struct age_softc *sc)
2984{
2985	struct age_ring_data *rd;
2986	struct age_txdesc *txd;
2987	int i;
2988
2989	AGE_LOCK_ASSERT(sc);
2990
2991	sc->age_cdata.age_tx_prod = 0;
2992	sc->age_cdata.age_tx_cons = 0;
2993	sc->age_cdata.age_tx_cnt = 0;
2994
2995	rd = &sc->age_rdata;
2996	bzero(rd->age_tx_ring, AGE_TX_RING_SZ);
2997	for (i = 0; i < AGE_TX_RING_CNT; i++) {
2998		txd = &sc->age_cdata.age_txdesc[i];
2999		txd->tx_desc = &rd->age_tx_ring[i];
3000		txd->tx_m = NULL;
3001	}
3002
3003	bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
3004	    sc->age_cdata.age_tx_ring_map,
3005	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3006}
3007
3008static int
3009age_init_rx_ring(struct age_softc *sc)
3010{
3011	struct age_ring_data *rd;
3012	struct age_rxdesc *rxd;
3013	int i;
3014
3015	AGE_LOCK_ASSERT(sc);
3016
3017	sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1;
3018	sc->age_morework = 0;
3019	rd = &sc->age_rdata;
3020	bzero(rd->age_rx_ring, AGE_RX_RING_SZ);
3021	for (i = 0; i < AGE_RX_RING_CNT; i++) {
3022		rxd = &sc->age_cdata.age_rxdesc[i];
3023		rxd->rx_m = NULL;
3024		rxd->rx_desc = &rd->age_rx_ring[i];
3025		if (age_newbuf(sc, rxd) != 0)
3026			return (ENOBUFS);
3027	}
3028
3029	bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
3030	    sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE);
3031
3032	return (0);
3033}
3034
3035static void
3036age_init_rr_ring(struct age_softc *sc)
3037{
3038	struct age_ring_data *rd;
3039
3040	AGE_LOCK_ASSERT(sc);
3041
3042	sc->age_cdata.age_rr_cons = 0;
3043	AGE_RXCHAIN_RESET(sc);
3044
3045	rd = &sc->age_rdata;
3046	bzero(rd->age_rr_ring, AGE_RR_RING_SZ);
3047	bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
3048	    sc->age_cdata.age_rr_ring_map,
3049	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3050}
3051
3052static void
3053age_init_cmb_block(struct age_softc *sc)
3054{
3055	struct age_ring_data *rd;
3056
3057	AGE_LOCK_ASSERT(sc);
3058
3059	rd = &sc->age_rdata;
3060	bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ);
3061	bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
3062	    sc->age_cdata.age_cmb_block_map,
3063	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3064}
3065
3066static void
3067age_init_smb_block(struct age_softc *sc)
3068{
3069	struct age_ring_data *rd;
3070
3071	AGE_LOCK_ASSERT(sc);
3072
3073	rd = &sc->age_rdata;
3074	bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ);
3075	bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
3076	    sc->age_cdata.age_smb_block_map,
3077	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3078}
3079
3080static int
3081age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd)
3082{
3083	struct rx_desc *desc;
3084	struct mbuf *m;
3085	bus_dma_segment_t segs[1];
3086	bus_dmamap_t map;
3087	int nsegs;
3088
3089	AGE_LOCK_ASSERT(sc);
3090
3091	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
3092	if (m == NULL)
3093		return (ENOBUFS);
3094	m->m_len = m->m_pkthdr.len = MCLBYTES;
3095#ifndef __NO_STRICT_ALIGNMENT
3096	m_adj(m, AGE_RX_BUF_ALIGN);
3097#endif
3098
3099	if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag,
3100	    sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3101		m_freem(m);
3102		return (ENOBUFS);
3103	}
3104	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3105
3106	if (rxd->rx_m != NULL) {
3107		bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3108		    BUS_DMASYNC_POSTREAD);
3109		bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap);
3110	}
3111	map = rxd->rx_dmamap;
3112	rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap;
3113	sc->age_cdata.age_rx_sparemap = map;
3114	bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3115	    BUS_DMASYNC_PREREAD);
3116	rxd->rx_m = m;
3117
3118	desc = rxd->rx_desc;
3119	desc->addr = htole64(segs[0].ds_addr);
3120	desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) <<
3121	    AGE_RD_LEN_SHIFT);
3122	return (0);
3123}
3124
3125static void
3126age_rxvlan(struct age_softc *sc)
3127{
3128	struct ifnet *ifp;
3129	uint32_t reg;
3130
3131	AGE_LOCK_ASSERT(sc);
3132
3133	ifp = sc->age_ifp;
3134	reg = CSR_READ_4(sc, AGE_MAC_CFG);
3135	reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3136	if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3137		reg |= MAC_CFG_VLAN_TAG_STRIP;
3138	CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
3139}
3140
3141static u_int
3142age_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
3143{
3144	uint32_t *mchash = arg;
3145	uint32_t crc;
3146
3147	crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
3148	mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3149
3150	return (1);
3151}
3152
3153static void
3154age_rxfilter(struct age_softc *sc)
3155{
3156	struct ifnet *ifp;
3157	uint32_t mchash[2];
3158	uint32_t rxcfg;
3159
3160	AGE_LOCK_ASSERT(sc);
3161
3162	ifp = sc->age_ifp;
3163
3164	rxcfg = CSR_READ_4(sc, AGE_MAC_CFG);
3165	rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3166	if ((ifp->if_flags & IFF_BROADCAST) != 0)
3167		rxcfg |= MAC_CFG_BCAST;
3168	if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3169		if ((ifp->if_flags & IFF_PROMISC) != 0)
3170			rxcfg |= MAC_CFG_PROMISC;
3171		if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3172			rxcfg |= MAC_CFG_ALLMULTI;
3173		CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF);
3174		CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF);
3175		CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3176		return;
3177	}
3178
3179	/* Program new filter. */
3180	bzero(mchash, sizeof(mchash));
3181	if_foreach_llmaddr(ifp, age_hash_maddr, mchash);
3182
3183	CSR_WRITE_4(sc, AGE_MAR0, mchash[0]);
3184	CSR_WRITE_4(sc, AGE_MAR1, mchash[1]);
3185	CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3186}
3187
3188static int
3189sysctl_age_stats(SYSCTL_HANDLER_ARGS)
3190{
3191	struct age_softc *sc;
3192	struct age_stats *stats;
3193	int error, result;
3194
3195	result = -1;
3196	error = sysctl_handle_int(oidp, &result, 0, req);
3197
3198	if (error != 0 || req->newptr == NULL)
3199		return (error);
3200
3201	if (result != 1)
3202		return (error);
3203
3204	sc = (struct age_softc *)arg1;
3205	stats = &sc->age_stat;
3206	printf("%s statistics:\n", device_get_nameunit(sc->age_dev));
3207	printf("Transmit good frames : %ju\n",
3208	    (uintmax_t)stats->tx_frames);
3209	printf("Transmit good broadcast frames : %ju\n",
3210	    (uintmax_t)stats->tx_bcast_frames);
3211	printf("Transmit good multicast frames : %ju\n",
3212	    (uintmax_t)stats->tx_mcast_frames);
3213	printf("Transmit pause control frames : %u\n",
3214	    stats->tx_pause_frames);
3215	printf("Transmit control frames : %u\n",
3216	    stats->tx_control_frames);
3217	printf("Transmit frames with excessive deferrals : %u\n",
3218	    stats->tx_excess_defer);
3219	printf("Transmit deferrals : %u\n",
3220	    stats->tx_deferred);
3221	printf("Transmit good octets : %ju\n",
3222	    (uintmax_t)stats->tx_bytes);
3223	printf("Transmit good broadcast octets : %ju\n",
3224	    (uintmax_t)stats->tx_bcast_bytes);
3225	printf("Transmit good multicast octets : %ju\n",
3226	    (uintmax_t)stats->tx_mcast_bytes);
3227	printf("Transmit frames 64 bytes : %ju\n",
3228	    (uintmax_t)stats->tx_pkts_64);
3229	printf("Transmit frames 65 to 127 bytes : %ju\n",
3230	    (uintmax_t)stats->tx_pkts_65_127);
3231	printf("Transmit frames 128 to 255 bytes : %ju\n",
3232	    (uintmax_t)stats->tx_pkts_128_255);
3233	printf("Transmit frames 256 to 511 bytes : %ju\n",
3234	    (uintmax_t)stats->tx_pkts_256_511);
3235	printf("Transmit frames 512 to 1024 bytes : %ju\n",
3236	    (uintmax_t)stats->tx_pkts_512_1023);
3237	printf("Transmit frames 1024 to 1518 bytes : %ju\n",
3238	    (uintmax_t)stats->tx_pkts_1024_1518);
3239	printf("Transmit frames 1519 to MTU bytes : %ju\n",
3240	    (uintmax_t)stats->tx_pkts_1519_max);
3241	printf("Transmit single collisions : %u\n",
3242	    stats->tx_single_colls);
3243	printf("Transmit multiple collisions : %u\n",
3244	    stats->tx_multi_colls);
3245	printf("Transmit late collisions : %u\n",
3246	    stats->tx_late_colls);
3247	printf("Transmit abort due to excessive collisions : %u\n",
3248	    stats->tx_excess_colls);
3249	printf("Transmit underruns due to FIFO underruns : %u\n",
3250	    stats->tx_underrun);
3251	printf("Transmit descriptor write-back errors : %u\n",
3252	    stats->tx_desc_underrun);
3253	printf("Transmit frames with length mismatched frame size : %u\n",
3254	    stats->tx_lenerrs);
3255	printf("Transmit frames with truncated due to MTU size : %u\n",
3256	    stats->tx_lenerrs);
3257
3258	printf("Receive good frames : %ju\n",
3259	    (uintmax_t)stats->rx_frames);
3260	printf("Receive good broadcast frames : %ju\n",
3261	    (uintmax_t)stats->rx_bcast_frames);
3262	printf("Receive good multicast frames : %ju\n",
3263	    (uintmax_t)stats->rx_mcast_frames);
3264	printf("Receive pause control frames : %u\n",
3265	    stats->rx_pause_frames);
3266	printf("Receive control frames : %u\n",
3267	    stats->rx_control_frames);
3268	printf("Receive CRC errors : %u\n",
3269	    stats->rx_crcerrs);
3270	printf("Receive frames with length errors : %u\n",
3271	    stats->rx_lenerrs);
3272	printf("Receive good octets : %ju\n",
3273	    (uintmax_t)stats->rx_bytes);
3274	printf("Receive good broadcast octets : %ju\n",
3275	    (uintmax_t)stats->rx_bcast_bytes);
3276	printf("Receive good multicast octets : %ju\n",
3277	    (uintmax_t)stats->rx_mcast_bytes);
3278	printf("Receive frames too short : %u\n",
3279	    stats->rx_runts);
3280	printf("Receive fragmented frames : %ju\n",
3281	    (uintmax_t)stats->rx_fragments);
3282	printf("Receive frames 64 bytes : %ju\n",
3283	    (uintmax_t)stats->rx_pkts_64);
3284	printf("Receive frames 65 to 127 bytes : %ju\n",
3285	    (uintmax_t)stats->rx_pkts_65_127);
3286	printf("Receive frames 128 to 255 bytes : %ju\n",
3287	    (uintmax_t)stats->rx_pkts_128_255);
3288	printf("Receive frames 256 to 511 bytes : %ju\n",
3289	    (uintmax_t)stats->rx_pkts_256_511);
3290	printf("Receive frames 512 to 1024 bytes : %ju\n",
3291	    (uintmax_t)stats->rx_pkts_512_1023);
3292	printf("Receive frames 1024 to 1518 bytes : %ju\n",
3293	    (uintmax_t)stats->rx_pkts_1024_1518);
3294	printf("Receive frames 1519 to MTU bytes : %ju\n",
3295	    (uintmax_t)stats->rx_pkts_1519_max);
3296	printf("Receive frames too long : %ju\n",
3297	    (uint64_t)stats->rx_pkts_truncated);
3298	printf("Receive frames with FIFO overflow : %u\n",
3299	    stats->rx_fifo_oflows);
3300	printf("Receive frames with return descriptor overflow : %u\n",
3301	    stats->rx_desc_oflows);
3302	printf("Receive frames with alignment errors : %u\n",
3303	    stats->rx_alignerrs);
3304	printf("Receive frames dropped due to address filtering : %ju\n",
3305	    (uint64_t)stats->rx_pkts_filtered);
3306
3307	return (error);
3308}
3309
3310static int
3311sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3312{
3313	int error, value;
3314
3315	if (arg1 == NULL)
3316		return (EINVAL);
3317	value = *(int *)arg1;
3318	error = sysctl_handle_int(oidp, &value, 0, req);
3319	if (error || req->newptr == NULL)
3320		return (error);
3321	if (value < low || value > high)
3322		return (EINVAL);
3323        *(int *)arg1 = value;
3324
3325        return (0);
3326}
3327
3328static int
3329sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS)
3330{
3331	return (sysctl_int_range(oidp, arg1, arg2, req,
3332	    AGE_PROC_MIN, AGE_PROC_MAX));
3333}
3334
3335static int
3336sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS)
3337{
3338
3339	return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN,
3340	    AGE_IM_TIMER_MAX));
3341}
3342