176ef03bjmallett/***********************license start***************
27453924jmallett * Copyright (c) 2003-2012  Cavium Inc. (support@cavium.com). All rights
376ef03bjmallett * reserved.
476ef03bjmallett *
576ef03bjmallett *
676ef03bjmallett * Redistribution and use in source and binary forms, with or without
776ef03bjmallett * modification, are permitted provided that the following conditions are
876ef03bjmallett * met:
976ef03bjmallett *
1076ef03bjmallett *   * Redistributions of source code must retain the above copyright
1176ef03bjmallett *     notice, this list of conditions and the following disclaimer.
1276ef03bjmallett *
1376ef03bjmallett *   * Redistributions in binary form must reproduce the above
1476ef03bjmallett *     copyright notice, this list of conditions and the following
1576ef03bjmallett *     disclaimer in the documentation and/or other materials provided
1676ef03bjmallett *     with the distribution.
1776ef03bjmallett
187453924jmallett *   * Neither the name of Cavium Inc. nor the names of
1976ef03bjmallett *     its contributors may be used to endorse or promote products
2076ef03bjmallett *     derived from this software without specific prior written
2176ef03bjmallett *     permission.
2276ef03bjmallett
2376ef03bjmallett * This Software, including technical data, may be subject to U.S. export  control
2476ef03bjmallett * laws, including the U.S. Export Administration Act and its  associated
2576ef03bjmallett * regulations, and may be subject to export or import  regulations in other
2676ef03bjmallett * countries.
2776ef03bjmallett
2876ef03bjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
297453924jmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
3076ef03bjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
3176ef03bjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
3276ef03bjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
3376ef03bjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
3476ef03bjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
3576ef03bjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
3676ef03bjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE  RISK ARISING OUT OF USE OR
3776ef03bjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
3876ef03bjmallett ***********************license end**************************************/
3976ef03bjmallett
4076ef03bjmallett
4176ef03bjmallett/**
4276ef03bjmallett * cvmx-sli-defs.h
4376ef03bjmallett *
4476ef03bjmallett * Configuration and status register (CSR) type definitions for
4576ef03bjmallett * Octeon sli.
4676ef03bjmallett *
4776ef03bjmallett * This file is auto generated. Do not edit.
4876ef03bjmallett *
4976ef03bjmallett * <hr>$Revision$<hr>
5076ef03bjmallett *
5176ef03bjmallett */
527453924jmallett#ifndef __CVMX_SLI_DEFS_H__
537453924jmallett#define __CVMX_SLI_DEFS_H__
5476ef03bjmallett
5576ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
5676ef03bjmallett#define CVMX_SLI_BIST_STATUS CVMX_SLI_BIST_STATUS_FUNC()
5776ef03bjmallettstatic inline uint64_t CVMX_SLI_BIST_STATUS_FUNC(void)
5876ef03bjmallett{
597453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
6076ef03bjmallett		cvmx_warn("CVMX_SLI_BIST_STATUS not supported on this chip\n");
6176ef03bjmallett	return 0x0000000000000580ull;
6276ef03bjmallett}
6376ef03bjmallett#else
6476ef03bjmallett#define CVMX_SLI_BIST_STATUS (0x0000000000000580ull)
6576ef03bjmallett#endif
6676ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
6776ef03bjmallettstatic inline uint64_t CVMX_SLI_CTL_PORTX(unsigned long offset)
6876ef03bjmallett{
6976ef03bjmallett	if (!(
707453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
717453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
727453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
737453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
747453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
7576ef03bjmallett		cvmx_warn("CVMX_SLI_CTL_PORTX(%lu) is invalid on this chip\n", offset);
767453924jmallett	return 0x0000000000000050ull + ((offset) & 3) * 16;
7776ef03bjmallett}
7876ef03bjmallett#else
797453924jmallett#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16)
8076ef03bjmallett#endif
8176ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
8276ef03bjmallett#define CVMX_SLI_CTL_STATUS CVMX_SLI_CTL_STATUS_FUNC()
8376ef03bjmallettstatic inline uint64_t CVMX_SLI_CTL_STATUS_FUNC(void)
8476ef03bjmallett{
857453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
8676ef03bjmallett		cvmx_warn("CVMX_SLI_CTL_STATUS not supported on this chip\n");
8776ef03bjmallett	return 0x0000000000000570ull;
8876ef03bjmallett}
8976ef03bjmallett#else
9076ef03bjmallett#define CVMX_SLI_CTL_STATUS (0x0000000000000570ull)
9176ef03bjmallett#endif
9276ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9376ef03bjmallett#define CVMX_SLI_DATA_OUT_CNT CVMX_SLI_DATA_OUT_CNT_FUNC()
9476ef03bjmallettstatic inline uint64_t CVMX_SLI_DATA_OUT_CNT_FUNC(void)
9576ef03bjmallett{
967453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
9776ef03bjmallett		cvmx_warn("CVMX_SLI_DATA_OUT_CNT not supported on this chip\n");
9876ef03bjmallett	return 0x00000000000005F0ull;
9976ef03bjmallett}
10076ef03bjmallett#else
10176ef03bjmallett#define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull)
10276ef03bjmallett#endif
10376ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10476ef03bjmallett#define CVMX_SLI_DBG_DATA CVMX_SLI_DBG_DATA_FUNC()
10576ef03bjmallettstatic inline uint64_t CVMX_SLI_DBG_DATA_FUNC(void)
10676ef03bjmallett{
1077453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
10876ef03bjmallett		cvmx_warn("CVMX_SLI_DBG_DATA not supported on this chip\n");
10976ef03bjmallett	return 0x0000000000000310ull;
11076ef03bjmallett}
11176ef03bjmallett#else
11276ef03bjmallett#define CVMX_SLI_DBG_DATA (0x0000000000000310ull)
11376ef03bjmallett#endif
11476ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
11576ef03bjmallett#define CVMX_SLI_DBG_SELECT CVMX_SLI_DBG_SELECT_FUNC()
11676ef03bjmallettstatic inline uint64_t CVMX_SLI_DBG_SELECT_FUNC(void)
11776ef03bjmallett{
1187453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
11976ef03bjmallett		cvmx_warn("CVMX_SLI_DBG_SELECT not supported on this chip\n");
12076ef03bjmallett	return 0x0000000000000300ull;
12176ef03bjmallett}
12276ef03bjmallett#else
12376ef03bjmallett#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull)
12476ef03bjmallett#endif
12576ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
12676ef03bjmallettstatic inline uint64_t CVMX_SLI_DMAX_CNT(unsigned long offset)
12776ef03bjmallett{
12876ef03bjmallett	if (!(
1297453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1307453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1317453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1327453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1337453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
13476ef03bjmallett		cvmx_warn("CVMX_SLI_DMAX_CNT(%lu) is invalid on this chip\n", offset);
13576ef03bjmallett	return 0x0000000000000400ull + ((offset) & 1) * 16;
13676ef03bjmallett}
13776ef03bjmallett#else
13876ef03bjmallett#define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16)
13976ef03bjmallett#endif
14076ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
14176ef03bjmallettstatic inline uint64_t CVMX_SLI_DMAX_INT_LEVEL(unsigned long offset)
14276ef03bjmallett{
14376ef03bjmallett	if (!(
1447453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1457453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1467453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1477453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1487453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
14976ef03bjmallett		cvmx_warn("CVMX_SLI_DMAX_INT_LEVEL(%lu) is invalid on this chip\n", offset);
15076ef03bjmallett	return 0x00000000000003E0ull + ((offset) & 1) * 16;
15176ef03bjmallett}
15276ef03bjmallett#else
15376ef03bjmallett#define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16)
15476ef03bjmallett#endif
15576ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
15676ef03bjmallettstatic inline uint64_t CVMX_SLI_DMAX_TIM(unsigned long offset)
15776ef03bjmallett{
15876ef03bjmallett	if (!(
1597453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1607453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1617453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1627453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1637453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
16476ef03bjmallett		cvmx_warn("CVMX_SLI_DMAX_TIM(%lu) is invalid on this chip\n", offset);
16576ef03bjmallett	return 0x0000000000000420ull + ((offset) & 1) * 16;
16676ef03bjmallett}
16776ef03bjmallett#else
16876ef03bjmallett#define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16)
16976ef03bjmallett#endif
17076ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
17176ef03bjmallett#define CVMX_SLI_INT_ENB_CIU CVMX_SLI_INT_ENB_CIU_FUNC()
17276ef03bjmallettstatic inline uint64_t CVMX_SLI_INT_ENB_CIU_FUNC(void)
17376ef03bjmallett{
1747453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
17576ef03bjmallett		cvmx_warn("CVMX_SLI_INT_ENB_CIU not supported on this chip\n");
17676ef03bjmallett	return 0x0000000000003CD0ull;
17776ef03bjmallett}
17876ef03bjmallett#else
17976ef03bjmallett#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull)
18076ef03bjmallett#endif
18176ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
18276ef03bjmallettstatic inline uint64_t CVMX_SLI_INT_ENB_PORTX(unsigned long offset)
18376ef03bjmallett{
18476ef03bjmallett	if (!(
1857453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1867453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1877453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1887453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1897453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
19076ef03bjmallett		cvmx_warn("CVMX_SLI_INT_ENB_PORTX(%lu) is invalid on this chip\n", offset);
19176ef03bjmallett	return 0x0000000000000340ull + ((offset) & 1) * 16;
19276ef03bjmallett}
19376ef03bjmallett#else
19476ef03bjmallett#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16)
19576ef03bjmallett#endif
19676ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
19776ef03bjmallett#define CVMX_SLI_INT_SUM CVMX_SLI_INT_SUM_FUNC()
19876ef03bjmallettstatic inline uint64_t CVMX_SLI_INT_SUM_FUNC(void)
19976ef03bjmallett{
2007453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
20176ef03bjmallett		cvmx_warn("CVMX_SLI_INT_SUM not supported on this chip\n");
20276ef03bjmallett	return 0x0000000000000330ull;
20376ef03bjmallett}
20476ef03bjmallett#else
20576ef03bjmallett#define CVMX_SLI_INT_SUM (0x0000000000000330ull)
20676ef03bjmallett#endif
20776ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
20876ef03bjmallett#define CVMX_SLI_LAST_WIN_RDATA0 CVMX_SLI_LAST_WIN_RDATA0_FUNC()
20976ef03bjmallettstatic inline uint64_t CVMX_SLI_LAST_WIN_RDATA0_FUNC(void)
21076ef03bjmallett{
2117453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
21276ef03bjmallett		cvmx_warn("CVMX_SLI_LAST_WIN_RDATA0 not supported on this chip\n");
21376ef03bjmallett	return 0x0000000000000600ull;
21476ef03bjmallett}
21576ef03bjmallett#else
21676ef03bjmallett#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull)
21776ef03bjmallett#endif
21876ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
21976ef03bjmallett#define CVMX_SLI_LAST_WIN_RDATA1 CVMX_SLI_LAST_WIN_RDATA1_FUNC()
22076ef03bjmallettstatic inline uint64_t CVMX_SLI_LAST_WIN_RDATA1_FUNC(void)
22176ef03bjmallett{
2227453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
22376ef03bjmallett		cvmx_warn("CVMX_SLI_LAST_WIN_RDATA1 not supported on this chip\n");
22476ef03bjmallett	return 0x0000000000000610ull;
22576ef03bjmallett}
22676ef03bjmallett#else
22776ef03bjmallett#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull)
22876ef03bjmallett#endif
22976ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2307453924jmallett#define CVMX_SLI_LAST_WIN_RDATA2 CVMX_SLI_LAST_WIN_RDATA2_FUNC()
2317453924jmallettstatic inline uint64_t CVMX_SLI_LAST_WIN_RDATA2_FUNC(void)
2327453924jmallett{
2337453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2347453924jmallett		cvmx_warn("CVMX_SLI_LAST_WIN_RDATA2 not supported on this chip\n");
2357453924jmallett	return 0x00000000000006C0ull;
2367453924jmallett}
2377453924jmallett#else
2387453924jmallett#define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull)
2397453924jmallett#endif
2407453924jmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2417453924jmallett#define CVMX_SLI_LAST_WIN_RDATA3 CVMX_SLI_LAST_WIN_RDATA3_FUNC()
2427453924jmallettstatic inline uint64_t CVMX_SLI_LAST_WIN_RDATA3_FUNC(void)
2437453924jmallett{
2447453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2457453924jmallett		cvmx_warn("CVMX_SLI_LAST_WIN_RDATA3 not supported on this chip\n");
2467453924jmallett	return 0x00000000000006D0ull;
2477453924jmallett}
2487453924jmallett#else
2497453924jmallett#define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull)
2507453924jmallett#endif
2517453924jmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
25276ef03bjmallett#define CVMX_SLI_MAC_CREDIT_CNT CVMX_SLI_MAC_CREDIT_CNT_FUNC()
25376ef03bjmallettstatic inline uint64_t CVMX_SLI_MAC_CREDIT_CNT_FUNC(void)
25476ef03bjmallett{
2557453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
25676ef03bjmallett		cvmx_warn("CVMX_SLI_MAC_CREDIT_CNT not supported on this chip\n");
25776ef03bjmallett	return 0x0000000000003D70ull;
25876ef03bjmallett}
25976ef03bjmallett#else
26076ef03bjmallett#define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull)
26176ef03bjmallett#endif
26276ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2637453924jmallett#define CVMX_SLI_MAC_CREDIT_CNT2 CVMX_SLI_MAC_CREDIT_CNT2_FUNC()
2647453924jmallettstatic inline uint64_t CVMX_SLI_MAC_CREDIT_CNT2_FUNC(void)
2657453924jmallett{
2667453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2677453924jmallett		cvmx_warn("CVMX_SLI_MAC_CREDIT_CNT2 not supported on this chip\n");
2687453924jmallett	return 0x0000000000003E10ull;
2697453924jmallett}
2707453924jmallett#else
2717453924jmallett#define CVMX_SLI_MAC_CREDIT_CNT2 (0x0000000000003E10ull)
2727453924jmallett#endif
2737453924jmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
27476ef03bjmallett#define CVMX_SLI_MAC_NUMBER CVMX_SLI_MAC_NUMBER_FUNC()
27576ef03bjmallettstatic inline uint64_t CVMX_SLI_MAC_NUMBER_FUNC(void)
27676ef03bjmallett{
2777453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
27876ef03bjmallett		cvmx_warn("CVMX_SLI_MAC_NUMBER not supported on this chip\n");
27976ef03bjmallett	return 0x0000000000003E00ull;
28076ef03bjmallett}
28176ef03bjmallett#else
28276ef03bjmallett#define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull)
28376ef03bjmallett#endif
28476ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
28576ef03bjmallett#define CVMX_SLI_MEM_ACCESS_CTL CVMX_SLI_MEM_ACCESS_CTL_FUNC()
28676ef03bjmallettstatic inline uint64_t CVMX_SLI_MEM_ACCESS_CTL_FUNC(void)
28776ef03bjmallett{
2887453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
28976ef03bjmallett		cvmx_warn("CVMX_SLI_MEM_ACCESS_CTL not supported on this chip\n");
29076ef03bjmallett	return 0x00000000000002F0ull;
29176ef03bjmallett}
29276ef03bjmallett#else
29376ef03bjmallett#define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull)
29476ef03bjmallett#endif
29576ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
29676ef03bjmallettstatic inline uint64_t CVMX_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)
29776ef03bjmallett{
29876ef03bjmallett	if (!(
2997453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 12) && (offset <= 27)))) ||
3007453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 12) && (offset <= 27)))) ||
3017453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 12) && (offset <= 27)))) ||
3027453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 12) && (offset <= 27)))) ||
3037453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 12) && (offset <= 27))))))
30476ef03bjmallett		cvmx_warn("CVMX_SLI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
3057453924jmallett	return 0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12;
30676ef03bjmallett}
30776ef03bjmallett#else
3087453924jmallett#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12)
30976ef03bjmallett#endif
31076ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
31176ef03bjmallett#define CVMX_SLI_MSI_ENB0 CVMX_SLI_MSI_ENB0_FUNC()
31276ef03bjmallettstatic inline uint64_t CVMX_SLI_MSI_ENB0_FUNC(void)
31376ef03bjmallett{
3147453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
31576ef03bjmallett		cvmx_warn("CVMX_SLI_MSI_ENB0 not supported on this chip\n");
31676ef03bjmallett	return 0x0000000000003C50ull;
31776ef03bjmallett}
31876ef03bjmallett#else
31976ef03bjmallett#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull)
32076ef03bjmallett#endif
32176ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
32276ef03bjmallett#define CVMX_SLI_MSI_ENB1 CVMX_SLI_MSI_ENB1_FUNC()
32376ef03bjmallettstatic inline uint64_t CVMX_SLI_MSI_ENB1_FUNC(void)
32476ef03bjmallett{
3257453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
32676ef03bjmallett		cvmx_warn("CVMX_SLI_MSI_ENB1 not supported on this chip\n");
32776ef03bjmallett	return 0x0000000000003C60ull;
32876ef03bjmallett}
32976ef03bjmallett#else
33076ef03bjmallett#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull)
33176ef03bjmallett#endif
33276ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
33376ef03bjmallett#define CVMX_SLI_MSI_ENB2 CVMX_SLI_MSI_ENB2_FUNC()
33476ef03bjmallettstatic inline uint64_t CVMX_SLI_MSI_ENB2_FUNC(void)
33576ef03bjmallett{
3367453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
33776ef03bjmallett		cvmx_warn("CVMX_SLI_MSI_ENB2 not supported on this chip\n");
33876ef03bjmallett	return 0x0000000000003C70ull;
33976ef03bjmallett}
34076ef03bjmallett#else
34176ef03bjmallett#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull)
34276ef03bjmallett#endif
34376ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
34476ef03bjmallett#define CVMX_SLI_MSI_ENB3 CVMX_SLI_MSI_ENB3_FUNC()
34576ef03bjmallettstatic inline uint64_t CVMX_SLI_MSI_ENB3_FUNC(void)
34676ef03bjmallett{
3477453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
34876ef03bjmallett		cvmx_warn("CVMX_SLI_MSI_ENB3 not supported on this chip\n");
34976ef03bjmallett	return 0x0000000000003C80ull;
35076ef03bjmallett}
35176ef03bjmallett#else
35276ef03bjmallett#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull)
35376ef03bjmallett#endif
35476ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
35576ef03bjmallett#define CVMX_SLI_MSI_RCV0 CVMX_SLI_MSI_RCV0_FUNC()
35676ef03bjmallettstatic inline uint64_t CVMX_SLI_MSI_RCV0_FUNC(void)
35776ef03bjmallett{
3587453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
35976ef03bjmallett		cvmx_warn("CVMX_SLI_MSI_RCV0 not supported on this chip\n");
36076ef03bjmallett	return 0x0000000000003C10ull;
36176ef03bjmallett}
36276ef03bjmallett#else
36376ef03bjmallett#define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull)
36476ef03bjmallett#endif
36576ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
36676ef03bjmallett#define CVMX_SLI_MSI_RCV1 CVMX_SLI_MSI_RCV1_FUNC()
36776ef03bjmallettstatic inline uint64_t CVMX_SLI_MSI_RCV1_FUNC(void)
36876ef03bjmallett{
3697453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
37076ef03bjmallett		cvmx_warn("CVMX_SLI_MSI_RCV1 not supported on this chip\n");
37176ef03bjmallett	return 0x0000000000003C20ull;
37276ef03bjmallett}
37376ef03bjmallett#else
37476ef03bjmallett#define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull)
37576ef03bjmallett#endif
37676ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
37776ef03bjmallett#define CVMX_SLI_MSI_RCV2 CVMX_SLI_MSI_RCV2_FUNC()
37876ef03bjmallettstatic inline uint64_t CVMX_SLI_MSI_RCV2_FUNC(void)
37976ef03bjmallett{
3807453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
38176ef03bjmallett		cvmx_warn("CVMX_SLI_MSI_RCV2 not supported on this chip\n");
38276ef03bjmallett	return 0x0000000000003C30ull;
38376ef03bjmallett}
38476ef03bjmallett#else
38576ef03bjmallett#define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull)
38676ef03bjmallett#endif
38776ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
38876ef03bjmallett#define CVMX_SLI_MSI_RCV3 CVMX_SLI_MSI_RCV3_FUNC()
38976ef03bjmallettstatic inline uint64_t CVMX_SLI_MSI_RCV3_FUNC(void)
39076ef03bjmallett{
3917453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
39276ef03bjmallett		cvmx_warn("CVMX_SLI_MSI_RCV3 not supported on this chip\n");
39376ef03bjmallett	return 0x0000000000003C40ull;
39476ef03bjmallett}
39576ef03bjmallett#else
39676ef03bjmallett#define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull)
39776ef03bjmallett#endif
39876ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
39976ef03bjmallett#define CVMX_SLI_MSI_RD_MAP CVMX_SLI_MSI_RD_MAP_FUNC()
40076ef03bjmallettstatic inline uint64_t CVMX_SLI_MSI_RD_MAP_FUNC(void)
40176ef03bjmallett{
4027453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
40376ef03bjmallett		cvmx_warn("CVMX_SLI_MSI_RD_MAP not supported on this chip\n");
40476ef03bjmallett	return 0x0000000000003CA0ull;
40576ef03bjmallett}
40676ef03bjmallett#else
40776ef03bjmallett#define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull)
40876ef03bjmallett#endif
40976ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
41076ef03bjmallett#define CVMX_SLI_MSI_W1C_ENB0 CVMX_SLI_MSI_W1C_ENB0_FUNC()
41176ef03bjmallettstatic inline uint64_t CVMX_SLI_MSI_W1C_ENB0_FUNC(void)
41276ef03bjmallett{
4137453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
41476ef03bjmallett		cvmx_warn("CVMX_SLI_MSI_W1C_ENB0 not supported on this chip\n");
41576ef03bjmallett	return 0x0000000000003CF0ull;
41676ef03bjmallett}
41776ef03bjmallett#else
41876ef03bjmallett#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
41976ef03bjmallett#endif
42076ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
42176ef03bjmallett#define CVMX_SLI_MSI_W1C_ENB1 CVMX_SLI_MSI_W1C_ENB1_FUNC()
42276ef03bjmallettstatic inline uint64_t CVMX_SLI_MSI_W1C_ENB1_FUNC(void)
42376ef03bjmallett{
4247453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
42576ef03bjmallett		cvmx_warn("CVMX_SLI_MSI_W1C_ENB1 not supported on this chip\n");
42676ef03bjmallett	return 0x0000000000003D00ull;
42776ef03bjmallett}
42876ef03bjmallett#else
42976ef03bjmallett#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull)
43076ef03bjmallett#endif
43176ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
43276ef03bjmallett#define CVMX_SLI_MSI_W1C_ENB2 CVMX_SLI_MSI_W1C_ENB2_FUNC()
43376ef03bjmallettstatic inline uint64_t CVMX_SLI_MSI_W1C_ENB2_FUNC(void)
43476ef03bjmallett{
4357453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
43676ef03bjmallett		cvmx_warn("CVMX_SLI_MSI_W1C_ENB2 not supported on this chip\n");
43776ef03bjmallett	return 0x0000000000003D10ull;
43876ef03bjmallett}
43976ef03bjmallett#else
44076ef03bjmallett#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull)
44176ef03bjmallett#endif
44276ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
44376ef03bjmallett#define CVMX_SLI_MSI_W1C_ENB3 CVMX_SLI_MSI_W1C_ENB3_FUNC()
44476ef03bjmallettstatic inline uint64_t CVMX_SLI_MSI_W1C_ENB3_FUNC(void)
44576ef03bjmallett{
4467453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
44776ef03bjmallett		cvmx_warn("CVMX_SLI_MSI_W1C_ENB3 not supported on this chip\n");
44876ef03bjmallett	return 0x0000000000003D20ull;
44976ef03bjmallett}
45076ef03bjmallett#else
45176ef03bjmallett#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull)
45276ef03bjmallett#endif
45376ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
45476ef03bjmallett#define CVMX_SLI_MSI_W1S_ENB0 CVMX_SLI_MSI_W1S_ENB0_FUNC()
45576ef03bjmallettstatic inline uint64_t CVMX_SLI_MSI_W1S_ENB0_FUNC(void)
45676ef03bjmallett{
4577453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
45876ef03bjmallett		cvmx_warn("CVMX_SLI_MSI_W1S_ENB0 not supported on this chip\n");
45976ef03bjmallett	return 0x0000000000003D30ull;
46076ef03bjmallett}
46176ef03bjmallett#else
46276ef03bjmallett#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull)
46376ef03bjmallett#endif
46476ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
46576ef03bjmallett#define CVMX_SLI_MSI_W1S_ENB1 CVMX_SLI_MSI_W1S_ENB1_FUNC()
46676ef03bjmallettstatic inline uint64_t CVMX_SLI_MSI_W1S_ENB1_FUNC(void)
46776ef03bjmallett{
4687453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
46976ef03bjmallett		cvmx_warn("CVMX_SLI_MSI_W1S_ENB1 not supported on this chip\n");
47076ef03bjmallett	return 0x0000000000003D40ull;
47176ef03bjmallett}
47276ef03bjmallett#else
47376ef03bjmallett#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull)
47476ef03bjmallett#endif
47576ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
47676ef03bjmallett#define CVMX_SLI_MSI_W1S_ENB2 CVMX_SLI_MSI_W1S_ENB2_FUNC()
47776ef03bjmallettstatic inline uint64_t CVMX_SLI_MSI_W1S_ENB2_FUNC(void)
47876ef03bjmallett{
4797453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
48076ef03bjmallett		cvmx_warn("CVMX_SLI_MSI_W1S_ENB2 not supported on this chip\n");
48176ef03bjmallett	return 0x0000000000003D50ull;
48276ef03bjmallett}
48376ef03bjmallett#else
48476ef03bjmallett#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull)
48576ef03bjmallett#endif
48676ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
48776ef03bjmallett#define CVMX_SLI_MSI_W1S_ENB3 CVMX_SLI_MSI_W1S_ENB3_FUNC()
48876ef03bjmallettstatic inline uint64_t CVMX_SLI_MSI_W1S_ENB3_FUNC(void)
48976ef03bjmallett{
4907453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
49176ef03bjmallett		cvmx_warn("CVMX_SLI_MSI_W1S_ENB3 not supported on this chip\n");
49276ef03bjmallett	return 0x0000000000003D60ull;
49376ef03bjmallett}
49476ef03bjmallett#else
49576ef03bjmallett#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull)
49676ef03bjmallett#endif
49776ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
49876ef03bjmallett#define CVMX_SLI_MSI_WR_MAP CVMX_SLI_MSI_WR_MAP_FUNC()
49976ef03bjmallettstatic inline uint64_t CVMX_SLI_MSI_WR_MAP_FUNC(void)
50076ef03bjmallett{
5017453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
50276ef03bjmallett		cvmx_warn("CVMX_SLI_MSI_WR_MAP not supported on this chip\n");
50376ef03bjmallett	return 0x0000000000003C90ull;
50476ef03bjmallett}
50576ef03bjmallett#else
50676ef03bjmallett#define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull)
50776ef03bjmallett#endif
50876ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
50976ef03bjmallett#define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC()
51076ef03bjmallettstatic inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void)
51176ef03bjmallett{
5127453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
51376ef03bjmallett		cvmx_warn("CVMX_SLI_PCIE_MSI_RCV not supported on this chip\n");
51476ef03bjmallett	return 0x0000000000003CB0ull;
51576ef03bjmallett}
51676ef03bjmallett#else
51776ef03bjmallett#define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull)
51876ef03bjmallett#endif
51976ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
52076ef03bjmallett#define CVMX_SLI_PCIE_MSI_RCV_B1 CVMX_SLI_PCIE_MSI_RCV_B1_FUNC()
52176ef03bjmallettstatic inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B1_FUNC(void)
52276ef03bjmallett{
5237453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
52476ef03bjmallett		cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B1 not supported on this chip\n");
52576ef03bjmallett	return 0x0000000000000650ull;
52676ef03bjmallett}
52776ef03bjmallett#else
52876ef03bjmallett#define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
52976ef03bjmallett#endif
53076ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
53176ef03bjmallett#define CVMX_SLI_PCIE_MSI_RCV_B2 CVMX_SLI_PCIE_MSI_RCV_B2_FUNC()
53276ef03bjmallettstatic inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B2_FUNC(void)
53376ef03bjmallett{
5347453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
53576ef03bjmallett		cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B2 not supported on this chip\n");
53676ef03bjmallett	return 0x0000000000000660ull;
53776ef03bjmallett}
53876ef03bjmallett#else
53976ef03bjmallett#define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
54076ef03bjmallett#endif
54176ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
54276ef03bjmallett#define CVMX_SLI_PCIE_MSI_RCV_B3 CVMX_SLI_PCIE_MSI_RCV_B3_FUNC()
54376ef03bjmallettstatic inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B3_FUNC(void)
54476ef03bjmallett{
5457453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
54676ef03bjmallett		cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B3 not supported on this chip\n");
54776ef03bjmallett	return 0x0000000000000670ull;
54876ef03bjmallett}
54976ef03bjmallett#else
55076ef03bjmallett#define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
55176ef03bjmallett#endif
55276ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
55376ef03bjmallettstatic inline uint64_t CVMX_SLI_PKTX_CNTS(unsigned long offset)
55476ef03bjmallett{
55576ef03bjmallett	if (!(
5567453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
5577453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
5587453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
5597453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
5607453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
56176ef03bjmallett		cvmx_warn("CVMX_SLI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
56276ef03bjmallett	return 0x0000000000002400ull + ((offset) & 31) * 16;
56376ef03bjmallett}
56476ef03bjmallett#else
56576ef03bjmallett#define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
56676ef03bjmallett#endif
56776ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56876ef03bjmallettstatic inline uint64_t CVMX_SLI_PKTX_INSTR_BADDR(unsigned long offset)
56976ef03bjmallett{
57076ef03bjmallett	if (!(
5717453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
5727453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
5737453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
5747453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
5757453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
57676ef03bjmallett		cvmx_warn("CVMX_SLI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
57776ef03bjmallett	return 0x0000000000002800ull + ((offset) & 31) * 16;
57876ef03bjmallett}
57976ef03bjmallett#else
58076ef03bjmallett#define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
58176ef03bjmallett#endif
58276ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
58376ef03bjmallettstatic inline uint64_t CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
58476ef03bjmallett{
58576ef03bjmallett	if (!(
5867453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
5877453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
5887453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
5897453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
5907453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
59176ef03bjmallett		cvmx_warn("CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
59276ef03bjmallett	return 0x0000000000002C00ull + ((offset) & 31) * 16;
59376ef03bjmallett}
59476ef03bjmallett#else
59576ef03bjmallett#define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
59676ef03bjmallett#endif
59776ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
59876ef03bjmallettstatic inline uint64_t CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
59976ef03bjmallett{
60076ef03bjmallett	if (!(
6017453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
6027453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
6037453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
6047453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
6057453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
60676ef03bjmallett		cvmx_warn("CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
60776ef03bjmallett	return 0x0000000000003000ull + ((offset) & 31) * 16;
60876ef03bjmallett}
60976ef03bjmallett#else
61076ef03bjmallett#define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
61176ef03bjmallett#endif
61276ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
61376ef03bjmallettstatic inline uint64_t CVMX_SLI_PKTX_INSTR_HEADER(unsigned long offset)
61476ef03bjmallett{
61576ef03bjmallett	if (!(
6167453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
6177453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
6187453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
6197453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
6207453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
62176ef03bjmallett		cvmx_warn("CVMX_SLI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
62276ef03bjmallett	return 0x0000000000003400ull + ((offset) & 31) * 16;
62376ef03bjmallett}
62476ef03bjmallett#else
62576ef03bjmallett#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
62676ef03bjmallett#endif
62776ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
62876ef03bjmallettstatic inline uint64_t CVMX_SLI_PKTX_IN_BP(unsigned long offset)
62976ef03bjmallett{
63076ef03bjmallett	if (!(
6317453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
6327453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
6337453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
6347453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
63576ef03bjmallett		cvmx_warn("CVMX_SLI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
63676ef03bjmallett	return 0x0000000000003800ull + ((offset) & 31) * 16;
63776ef03bjmallett}
63876ef03bjmallett#else
63976ef03bjmallett#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
64076ef03bjmallett#endif
64176ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
64276ef03bjmallettstatic inline uint64_t CVMX_SLI_PKTX_OUT_SIZE(unsigned long offset)
64376ef03bjmallett{
64476ef03bjmallett	if (!(
6457453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
6467453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
6477453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
6487453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
6497453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
65076ef03bjmallett		cvmx_warn("CVMX_SLI_PKTX_OUT_SIZE(%lu) is invalid on this chip\n", offset);
65176ef03bjmallett	return 0x0000000000000C00ull + ((offset) & 31) * 16;
65276ef03bjmallett}
65376ef03bjmallett#else
65476ef03bjmallett#define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16)
65576ef03bjmallett#endif
65676ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
65776ef03bjmallettstatic inline uint64_t CVMX_SLI_PKTX_SLIST_BADDR(unsigned long offset)
65876ef03bjmallett{
65976ef03bjmallett	if (!(
6607453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
6617453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
6627453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
6637453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
6647453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
66576ef03bjmallett		cvmx_warn("CVMX_SLI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
66676ef03bjmallett	return 0x0000000000001400ull + ((offset) & 31) * 16;
66776ef03bjmallett}
66876ef03bjmallett#else
66976ef03bjmallett#define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
67076ef03bjmallett#endif
67176ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67276ef03bjmallettstatic inline uint64_t CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
67376ef03bjmallett{
67476ef03bjmallett	if (!(
6757453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
6767453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
6777453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
6787453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
6797453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
68076ef03bjmallett		cvmx_warn("CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
68176ef03bjmallett	return 0x0000000000001800ull + ((offset) & 31) * 16;
68276ef03bjmallett}
68376ef03bjmallett#else
68476ef03bjmallett#define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
68576ef03bjmallett#endif
68676ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
68776ef03bjmallettstatic inline uint64_t CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
68876ef03bjmallett{
68976ef03bjmallett	if (!(
6907453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
6917453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
6927453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
6937453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
6947453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
69576ef03bjmallett		cvmx_warn("CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
69676ef03bjmallett	return 0x0000000000001C00ull + ((offset) & 31) * 16;
69776ef03bjmallett}
69876ef03bjmallett#else
69976ef03bjmallett#define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
70076ef03bjmallett#endif
70176ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
70276ef03bjmallett#define CVMX_SLI_PKT_CNT_INT CVMX_SLI_PKT_CNT_INT_FUNC()
70376ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_CNT_INT_FUNC(void)
70476ef03bjmallett{
7057453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
70676ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_CNT_INT not supported on this chip\n");
70776ef03bjmallett	return 0x0000000000001130ull;
70876ef03bjmallett}
70976ef03bjmallett#else
71076ef03bjmallett#define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull)
71176ef03bjmallett#endif
71276ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
71376ef03bjmallett#define CVMX_SLI_PKT_CNT_INT_ENB CVMX_SLI_PKT_CNT_INT_ENB_FUNC()
71476ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_CNT_INT_ENB_FUNC(void)
71576ef03bjmallett{
7167453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
71776ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_CNT_INT_ENB not supported on this chip\n");
71876ef03bjmallett	return 0x0000000000001150ull;
71976ef03bjmallett}
72076ef03bjmallett#else
72176ef03bjmallett#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull)
72276ef03bjmallett#endif
72376ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
72476ef03bjmallett#define CVMX_SLI_PKT_CTL CVMX_SLI_PKT_CTL_FUNC()
72576ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_CTL_FUNC(void)
72676ef03bjmallett{
7277453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
72876ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_CTL not supported on this chip\n");
72976ef03bjmallett	return 0x0000000000001220ull;
73076ef03bjmallett}
73176ef03bjmallett#else
73276ef03bjmallett#define CVMX_SLI_PKT_CTL (0x0000000000001220ull)
73376ef03bjmallett#endif
73476ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
73576ef03bjmallett#define CVMX_SLI_PKT_DATA_OUT_ES CVMX_SLI_PKT_DATA_OUT_ES_FUNC()
73676ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_DATA_OUT_ES_FUNC(void)
73776ef03bjmallett{
7387453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
73976ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_DATA_OUT_ES not supported on this chip\n");
74076ef03bjmallett	return 0x00000000000010B0ull;
74176ef03bjmallett}
74276ef03bjmallett#else
74376ef03bjmallett#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
74476ef03bjmallett#endif
74576ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
74676ef03bjmallett#define CVMX_SLI_PKT_DATA_OUT_NS CVMX_SLI_PKT_DATA_OUT_NS_FUNC()
74776ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_DATA_OUT_NS_FUNC(void)
74876ef03bjmallett{
7497453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
75076ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_DATA_OUT_NS not supported on this chip\n");
75176ef03bjmallett	return 0x00000000000010A0ull;
75276ef03bjmallett}
75376ef03bjmallett#else
75476ef03bjmallett#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
75576ef03bjmallett#endif
75676ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
75776ef03bjmallett#define CVMX_SLI_PKT_DATA_OUT_ROR CVMX_SLI_PKT_DATA_OUT_ROR_FUNC()
75876ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_DATA_OUT_ROR_FUNC(void)
75976ef03bjmallett{
7607453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
76176ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_DATA_OUT_ROR not supported on this chip\n");
76276ef03bjmallett	return 0x0000000000001090ull;
76376ef03bjmallett}
76476ef03bjmallett#else
76576ef03bjmallett#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
76676ef03bjmallett#endif
76776ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
76876ef03bjmallett#define CVMX_SLI_PKT_DPADDR CVMX_SLI_PKT_DPADDR_FUNC()
76976ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_DPADDR_FUNC(void)
77076ef03bjmallett{
7717453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
77276ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_DPADDR not supported on this chip\n");
77376ef03bjmallett	return 0x0000000000001080ull;
77476ef03bjmallett}
77576ef03bjmallett#else
77676ef03bjmallett#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull)
77776ef03bjmallett#endif
77876ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
77976ef03bjmallett#define CVMX_SLI_PKT_INPUT_CONTROL CVMX_SLI_PKT_INPUT_CONTROL_FUNC()
78076ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_INPUT_CONTROL_FUNC(void)
78176ef03bjmallett{
7827453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
78376ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_INPUT_CONTROL not supported on this chip\n");
78476ef03bjmallett	return 0x0000000000001170ull;
78576ef03bjmallett}
78676ef03bjmallett#else
78776ef03bjmallett#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull)
78876ef03bjmallett#endif
78976ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
79076ef03bjmallett#define CVMX_SLI_PKT_INSTR_ENB CVMX_SLI_PKT_INSTR_ENB_FUNC()
79176ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_INSTR_ENB_FUNC(void)
79276ef03bjmallett{
7937453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
79476ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_INSTR_ENB not supported on this chip\n");
79576ef03bjmallett	return 0x0000000000001000ull;
79676ef03bjmallett}
79776ef03bjmallett#else
79876ef03bjmallett#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull)
79976ef03bjmallett#endif
80076ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
80176ef03bjmallett#define CVMX_SLI_PKT_INSTR_RD_SIZE CVMX_SLI_PKT_INSTR_RD_SIZE_FUNC()
80276ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_INSTR_RD_SIZE_FUNC(void)
80376ef03bjmallett{
8047453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
80576ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_INSTR_RD_SIZE not supported on this chip\n");
80676ef03bjmallett	return 0x00000000000011A0ull;
80776ef03bjmallett}
80876ef03bjmallett#else
80976ef03bjmallett#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull)
81076ef03bjmallett#endif
81176ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
81276ef03bjmallett#define CVMX_SLI_PKT_INSTR_SIZE CVMX_SLI_PKT_INSTR_SIZE_FUNC()
81376ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_INSTR_SIZE_FUNC(void)
81476ef03bjmallett{
8157453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
81676ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_INSTR_SIZE not supported on this chip\n");
81776ef03bjmallett	return 0x0000000000001020ull;
81876ef03bjmallett}
81976ef03bjmallett#else
82076ef03bjmallett#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull)
82176ef03bjmallett#endif
82276ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
82376ef03bjmallett#define CVMX_SLI_PKT_INT_LEVELS CVMX_SLI_PKT_INT_LEVELS_FUNC()
82476ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_INT_LEVELS_FUNC(void)
82576ef03bjmallett{
8267453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
82776ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_INT_LEVELS not supported on this chip\n");
82876ef03bjmallett	return 0x0000000000001120ull;
82976ef03bjmallett}
83076ef03bjmallett#else
83176ef03bjmallett#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull)
83276ef03bjmallett#endif
83376ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
83476ef03bjmallett#define CVMX_SLI_PKT_IN_BP CVMX_SLI_PKT_IN_BP_FUNC()
83576ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_IN_BP_FUNC(void)
83676ef03bjmallett{
8377453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
83876ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_IN_BP not supported on this chip\n");
83976ef03bjmallett	return 0x0000000000001210ull;
84076ef03bjmallett}
84176ef03bjmallett#else
84276ef03bjmallett#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull)
84376ef03bjmallett#endif
84476ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
84576ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)
84676ef03bjmallett{
84776ef03bjmallett	if (!(
8487453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
8497453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
8507453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
8517453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
8527453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
85376ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
85476ef03bjmallett	return 0x0000000000002000ull + ((offset) & 31) * 16;
85576ef03bjmallett}
85676ef03bjmallett#else
85776ef03bjmallett#define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
85876ef03bjmallett#endif
85976ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
86076ef03bjmallett#define CVMX_SLI_PKT_IN_INSTR_COUNTS CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC()
86176ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC(void)
86276ef03bjmallett{
8637453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
86476ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
86576ef03bjmallett	return 0x0000000000001200ull;
86676ef03bjmallett}
86776ef03bjmallett#else
86876ef03bjmallett#define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull)
86976ef03bjmallett#endif
87076ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
87176ef03bjmallett#define CVMX_SLI_PKT_IN_PCIE_PORT CVMX_SLI_PKT_IN_PCIE_PORT_FUNC()
87276ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_IN_PCIE_PORT_FUNC(void)
87376ef03bjmallett{
8747453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
87576ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_IN_PCIE_PORT not supported on this chip\n");
87676ef03bjmallett	return 0x00000000000011B0ull;
87776ef03bjmallett}
87876ef03bjmallett#else
87976ef03bjmallett#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull)
88076ef03bjmallett#endif
88176ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
88276ef03bjmallett#define CVMX_SLI_PKT_IPTR CVMX_SLI_PKT_IPTR_FUNC()
88376ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_IPTR_FUNC(void)
88476ef03bjmallett{
8857453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
88676ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_IPTR not supported on this chip\n");
88776ef03bjmallett	return 0x0000000000001070ull;
88876ef03bjmallett}
88976ef03bjmallett#else
89076ef03bjmallett#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull)
89176ef03bjmallett#endif
89276ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
89376ef03bjmallett#define CVMX_SLI_PKT_OUTPUT_WMARK CVMX_SLI_PKT_OUTPUT_WMARK_FUNC()
89476ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_OUTPUT_WMARK_FUNC(void)
89576ef03bjmallett{
8967453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
89776ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_OUTPUT_WMARK not supported on this chip\n");
89876ef03bjmallett	return 0x0000000000001180ull;
89976ef03bjmallett}
90076ef03bjmallett#else
90176ef03bjmallett#define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull)
90276ef03bjmallett#endif
90376ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
90476ef03bjmallett#define CVMX_SLI_PKT_OUT_BMODE CVMX_SLI_PKT_OUT_BMODE_FUNC()
90576ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_OUT_BMODE_FUNC(void)
90676ef03bjmallett{
9077453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
90876ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_OUT_BMODE not supported on this chip\n");
90976ef03bjmallett	return 0x00000000000010D0ull;
91076ef03bjmallett}
91176ef03bjmallett#else
91276ef03bjmallett#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull)
91376ef03bjmallett#endif
91476ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
9157453924jmallett#define CVMX_SLI_PKT_OUT_BP_EN CVMX_SLI_PKT_OUT_BP_EN_FUNC()
9167453924jmallettstatic inline uint64_t CVMX_SLI_PKT_OUT_BP_EN_FUNC(void)
9177453924jmallett{
9187453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
9197453924jmallett		cvmx_warn("CVMX_SLI_PKT_OUT_BP_EN not supported on this chip\n");
9207453924jmallett	return 0x0000000000001240ull;
9217453924jmallett}
9227453924jmallett#else
9237453924jmallett#define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull)
9247453924jmallett#endif
9257453924jmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
92676ef03bjmallett#define CVMX_SLI_PKT_OUT_ENB CVMX_SLI_PKT_OUT_ENB_FUNC()
92776ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_OUT_ENB_FUNC(void)
92876ef03bjmallett{
9297453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
93076ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_OUT_ENB not supported on this chip\n");
93176ef03bjmallett	return 0x0000000000001010ull;
93276ef03bjmallett}
93376ef03bjmallett#else
93476ef03bjmallett#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull)
93576ef03bjmallett#endif
93676ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
93776ef03bjmallett#define CVMX_SLI_PKT_PCIE_PORT CVMX_SLI_PKT_PCIE_PORT_FUNC()
93876ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_PCIE_PORT_FUNC(void)
93976ef03bjmallett{
9407453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
94176ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_PCIE_PORT not supported on this chip\n");
94276ef03bjmallett	return 0x00000000000010E0ull;
94376ef03bjmallett}
94476ef03bjmallett#else
94576ef03bjmallett#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull)
94676ef03bjmallett#endif
94776ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
94876ef03bjmallett#define CVMX_SLI_PKT_PORT_IN_RST CVMX_SLI_PKT_PORT_IN_RST_FUNC()
94976ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_PORT_IN_RST_FUNC(void)
95076ef03bjmallett{
9517453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
95276ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_PORT_IN_RST not supported on this chip\n");
95376ef03bjmallett	return 0x00000000000011F0ull;
95476ef03bjmallett}
95576ef03bjmallett#else
95676ef03bjmallett#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull)
95776ef03bjmallett#endif
95876ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
95976ef03bjmallett#define CVMX_SLI_PKT_SLIST_ES CVMX_SLI_PKT_SLIST_ES_FUNC()
96076ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_SLIST_ES_FUNC(void)
96176ef03bjmallett{
9627453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
96376ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_SLIST_ES not supported on this chip\n");
96476ef03bjmallett	return 0x0000000000001050ull;
96576ef03bjmallett}
96676ef03bjmallett#else
96776ef03bjmallett#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull)
96876ef03bjmallett#endif
96976ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
97076ef03bjmallett#define CVMX_SLI_PKT_SLIST_NS CVMX_SLI_PKT_SLIST_NS_FUNC()
97176ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_SLIST_NS_FUNC(void)
97276ef03bjmallett{
9737453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
97476ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_SLIST_NS not supported on this chip\n");
97576ef03bjmallett	return 0x0000000000001040ull;
97676ef03bjmallett}
97776ef03bjmallett#else
97876ef03bjmallett#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull)
97976ef03bjmallett#endif
98076ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
98176ef03bjmallett#define CVMX_SLI_PKT_SLIST_ROR CVMX_SLI_PKT_SLIST_ROR_FUNC()
98276ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_SLIST_ROR_FUNC(void)
98376ef03bjmallett{
9847453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
98576ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_SLIST_ROR not supported on this chip\n");
98676ef03bjmallett	return 0x0000000000001030ull;
98776ef03bjmallett}
98876ef03bjmallett#else
98976ef03bjmallett#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull)
99076ef03bjmallett#endif
99176ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
99276ef03bjmallett#define CVMX_SLI_PKT_TIME_INT CVMX_SLI_PKT_TIME_INT_FUNC()
99376ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_TIME_INT_FUNC(void)
99476ef03bjmallett{
9957453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
99676ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_TIME_INT not supported on this chip\n");
99776ef03bjmallett	return 0x0000000000001140ull;
99876ef03bjmallett}
99976ef03bjmallett#else
100076ef03bjmallett#define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull)
100176ef03bjmallett#endif
100276ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
100376ef03bjmallett#define CVMX_SLI_PKT_TIME_INT_ENB CVMX_SLI_PKT_TIME_INT_ENB_FUNC()
100476ef03bjmallettstatic inline uint64_t CVMX_SLI_PKT_TIME_INT_ENB_FUNC(void)
100576ef03bjmallett{
10067453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
100776ef03bjmallett		cvmx_warn("CVMX_SLI_PKT_TIME_INT_ENB not supported on this chip\n");
100876ef03bjmallett	return 0x0000000000001160ull;
100976ef03bjmallett}
101076ef03bjmallett#else
101176ef03bjmallett#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull)
101276ef03bjmallett#endif
101376ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10147453924jmallettstatic inline uint64_t CVMX_SLI_PORTX_PKIND(unsigned long offset)
10157453924jmallett{
10167453924jmallett	if (!(
10177453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31)))))
10187453924jmallett		cvmx_warn("CVMX_SLI_PORTX_PKIND(%lu) is invalid on this chip\n", offset);
10197453924jmallett	return 0x0000000000000800ull + ((offset) & 31) * 16;
10207453924jmallett}
10217453924jmallett#else
10227453924jmallett#define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16)
10237453924jmallett#endif
10247453924jmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
102576ef03bjmallettstatic inline uint64_t CVMX_SLI_S2M_PORTX_CTL(unsigned long offset)
102676ef03bjmallett{
102776ef03bjmallett	if (!(
10287453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
10297453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
10307453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
10317453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
10327453924jmallett	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
103376ef03bjmallett		cvmx_warn("CVMX_SLI_S2M_PORTX_CTL(%lu) is invalid on this chip\n", offset);
10347453924jmallett	return 0x0000000000003D80ull + ((offset) & 3) * 16;
103576ef03bjmallett}
103676ef03bjmallett#else
10377453924jmallett#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16)
103876ef03bjmallett#endif
103976ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
104076ef03bjmallett#define CVMX_SLI_SCRATCH_1 CVMX_SLI_SCRATCH_1_FUNC()
104176ef03bjmallettstatic inline uint64_t CVMX_SLI_SCRATCH_1_FUNC(void)
104276ef03bjmallett{
10437453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
104476ef03bjmallett		cvmx_warn("CVMX_SLI_SCRATCH_1 not supported on this chip\n");
104576ef03bjmallett	return 0x00000000000003C0ull;
104676ef03bjmallett}
104776ef03bjmallett#else
104876ef03bjmallett#define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull)
104976ef03bjmallett#endif
105076ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
105176ef03bjmallett#define CVMX_SLI_SCRATCH_2 CVMX_SLI_SCRATCH_2_FUNC()
105276ef03bjmallettstatic inline uint64_t CVMX_SLI_SCRATCH_2_FUNC(void)
105376ef03bjmallett{
10547453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
105576ef03bjmallett		cvmx_warn("CVMX_SLI_SCRATCH_2 not supported on this chip\n");
105676ef03bjmallett	return 0x00000000000003D0ull;
105776ef03bjmallett}
105876ef03bjmallett#else
105976ef03bjmallett#define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull)
106076ef03bjmallett#endif
106176ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
106276ef03bjmallett#define CVMX_SLI_STATE1 CVMX_SLI_STATE1_FUNC()
106376ef03bjmallettstatic inline uint64_t CVMX_SLI_STATE1_FUNC(void)
106476ef03bjmallett{
10657453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
106676ef03bjmallett		cvmx_warn("CVMX_SLI_STATE1 not supported on this chip\n");
106776ef03bjmallett	return 0x0000000000000620ull;
106876ef03bjmallett}
106976ef03bjmallett#else
107076ef03bjmallett#define CVMX_SLI_STATE1 (0x0000000000000620ull)
107176ef03bjmallett#endif
107276ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
107376ef03bjmallett#define CVMX_SLI_STATE2 CVMX_SLI_STATE2_FUNC()
107476ef03bjmallettstatic inline uint64_t CVMX_SLI_STATE2_FUNC(void)
107576ef03bjmallett{
10767453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
107776ef03bjmallett		cvmx_warn("CVMX_SLI_STATE2 not supported on this chip\n");
107876ef03bjmallett	return 0x0000000000000630ull;
107976ef03bjmallett}
108076ef03bjmallett#else
108176ef03bjmallett#define CVMX_SLI_STATE2 (0x0000000000000630ull)
108276ef03bjmallett#endif
108376ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
108476ef03bjmallett#define CVMX_SLI_STATE3 CVMX_SLI_STATE3_FUNC()
108576ef03bjmallettstatic inline uint64_t CVMX_SLI_STATE3_FUNC(void)
108676ef03bjmallett{
10877453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
108876ef03bjmallett		cvmx_warn("CVMX_SLI_STATE3 not supported on this chip\n");
108976ef03bjmallett	return 0x0000000000000640ull;
109076ef03bjmallett}
109176ef03bjmallett#else
109276ef03bjmallett#define CVMX_SLI_STATE3 (0x0000000000000640ull)
109376ef03bjmallett#endif
109476ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
10957453924jmallett#define CVMX_SLI_TX_PIPE CVMX_SLI_TX_PIPE_FUNC()
10967453924jmallettstatic inline uint64_t CVMX_SLI_TX_PIPE_FUNC(void)
10977453924jmallett{
10987453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
10997453924jmallett		cvmx_warn("CVMX_SLI_TX_PIPE not supported on this chip\n");
11007453924jmallett	return 0x0000000000001230ull;
11017453924jmallett}
11027453924jmallett#else
11037453924jmallett#define CVMX_SLI_TX_PIPE (0x0000000000001230ull)
11047453924jmallett#endif
11057453924jmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
110676ef03bjmallett#define CVMX_SLI_WINDOW_CTL CVMX_SLI_WINDOW_CTL_FUNC()
110776ef03bjmallettstatic inline uint64_t CVMX_SLI_WINDOW_CTL_FUNC(void)
110876ef03bjmallett{
11097453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
111076ef03bjmallett		cvmx_warn("CVMX_SLI_WINDOW_CTL not supported on this chip\n");
111176ef03bjmallett	return 0x00000000000002E0ull;
111276ef03bjmallett}
111376ef03bjmallett#else
111476ef03bjmallett#define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull)
111576ef03bjmallett#endif
111676ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
111776ef03bjmallett#define CVMX_SLI_WIN_RD_ADDR CVMX_SLI_WIN_RD_ADDR_FUNC()
111876ef03bjmallettstatic inline uint64_t CVMX_SLI_WIN_RD_ADDR_FUNC(void)
111976ef03bjmallett{
11207453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
112176ef03bjmallett		cvmx_warn("CVMX_SLI_WIN_RD_ADDR not supported on this chip\n");
112276ef03bjmallett	return 0x0000000000000010ull;
112376ef03bjmallett}
112476ef03bjmallett#else
112576ef03bjmallett#define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull)
112676ef03bjmallett#endif
112776ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
112876ef03bjmallett#define CVMX_SLI_WIN_RD_DATA CVMX_SLI_WIN_RD_DATA_FUNC()
112976ef03bjmallettstatic inline uint64_t CVMX_SLI_WIN_RD_DATA_FUNC(void)
113076ef03bjmallett{
11317453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
113276ef03bjmallett		cvmx_warn("CVMX_SLI_WIN_RD_DATA not supported on this chip\n");
113376ef03bjmallett	return 0x0000000000000040ull;
113476ef03bjmallett}
113576ef03bjmallett#else
113676ef03bjmallett#define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull)
113776ef03bjmallett#endif
113876ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
113976ef03bjmallett#define CVMX_SLI_WIN_WR_ADDR CVMX_SLI_WIN_WR_ADDR_FUNC()
114076ef03bjmallettstatic inline uint64_t CVMX_SLI_WIN_WR_ADDR_FUNC(void)
114176ef03bjmallett{
11427453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
114376ef03bjmallett		cvmx_warn("CVMX_SLI_WIN_WR_ADDR not supported on this chip\n");
114476ef03bjmallett	return 0x0000000000000000ull;
114576ef03bjmallett}
114676ef03bjmallett#else
114776ef03bjmallett#define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull)
114876ef03bjmallett#endif
114976ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
115076ef03bjmallett#define CVMX_SLI_WIN_WR_DATA CVMX_SLI_WIN_WR_DATA_FUNC()
115176ef03bjmallettstatic inline uint64_t CVMX_SLI_WIN_WR_DATA_FUNC(void)
115276ef03bjmallett{
11537453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
115476ef03bjmallett		cvmx_warn("CVMX_SLI_WIN_WR_DATA not supported on this chip\n");
115576ef03bjmallett	return 0x0000000000000020ull;
115676ef03bjmallett}
115776ef03bjmallett#else
115876ef03bjmallett#define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull)
115976ef03bjmallett#endif
116076ef03bjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
116176ef03bjmallett#define CVMX_SLI_WIN_WR_MASK CVMX_SLI_WIN_WR_MASK_FUNC()
116276ef03bjmallettstatic inline uint64_t CVMX_SLI_WIN_WR_MASK_FUNC(void)
116376ef03bjmallett{
11647453924jmallett	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
116576ef03bjmallett		cvmx_warn("CVMX_SLI_WIN_WR_MASK not supported on this chip\n");
116676ef03bjmallett	return 0x0000000000000030ull;
116776ef03bjmallett}
116876ef03bjmallett#else
116976ef03bjmallett#define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull)
117076ef03bjmallett#endif
117176ef03bjmallett
117276ef03bjmallett/**
117376ef03bjmallett * cvmx_sli_bist_status
117476ef03bjmallett *
117576ef03bjmallett * SLI_BIST_STATUS = SLI's BIST Status Register
117676ef03bjmallett *
117776ef03bjmallett * Results from BIST runs of SLI's memories.
117876ef03bjmallett */
11797453924jmallettunion cvmx_sli_bist_status {
118076ef03bjmallett	uint64_t u64;
11817453924jmallett	struct cvmx_sli_bist_status_s {
11827453924jmallett#ifdef __BIG_ENDIAN_BITFIELD
11837453924jmallett	uint64_t reserved_32_63               : 32;
11847453924jmallett	uint64_t ncb_req                      : 1;  /**< BIST Status for NCB Request FIFO */
11857453924jmallett	uint64_t n2p0_c                       : 1;  /**< BIST Status for N2P Port0 Cmd */
11867453924jmallett	uint64_t n2p0_o                       : 1;  /**< BIST Status for N2P Port0 Data */
11877453924jmallett	uint64_t n2p1_c                       : 1;  /**< BIST Status for N2P Port1 Cmd */
11887453924jmallett	uint64_t n2p1_o                       : 1;  /**< BIST Status for N2P Port1 Data */
11897453924jmallett	uint64_t cpl_p0                       : 1;  /**< BIST Status for CPL Port 0 */
11907453924jmallett	uint64_t cpl_p1                       : 1;  /**< BIST Status for CPL Port 1 */
11917453924jmallett	uint64_t reserved_19_24               : 6;
11927453924jmallett	uint64_t p2n0_c0                      : 1;  /**< BIST Status for P2N Port0 C0 */
11937453924jmallett	uint64_t p2n0_c1                      : 1;  /**< BIST Status for P2N Port0 C1 */
11947453924jmallett	uint64_t p2n0_n                       : 1;  /**< BIST Status for P2N Port0 N */
11957453924jmallett	uint64_t p2n0_p0                      : 1;  /**< BIST Status for P2N Port0 P0 */
11967453924jmallett	uint64_t p2n0_p1                      : 1;  /**< BIST Status for P2N Port0 P1 */
11977453924jmallett	uint64_t p2n1_c0                      : 1;  /**< BIST Status for P2N Port1 C0 */
11987453924jmallett	uint64_t p2n1_c1                      : 1;  /**< BIST Status for P2N Port1 C1 */
11997453924jmallett	uint64_t p2n1_n                       : 1;  /**< BIST Status for P2N Port1 N */
12007453924jmallett	uint64_t p2n1_p0                      : 1;  /**< BIST Status for P2N Port1 P0 */
12017453924jmallett	uint64_t p2n1_p1                      : 1;  /**< BIST Status for P2N Port1 P1 */
12027453924jmallett	uint64_t reserved_6_8                 : 3;
12037453924jmallett	uint64_t dsi1_1                       : 1;  /**< BIST Status for DSI1 Memory 1 */
12047453924jmallett	uint64_t dsi1_0                       : 1;  /**< BIST Status for DSI1 Memory 0 */
12057453924jmallett	uint64_t dsi0_1                       : 1;  /**< BIST Status for DSI0 Memory 1 */
12067453924jmallett	uint64_t dsi0_0                       : 1;  /**< BIST Status for DSI0 Memory 0 */
12077453924jmallett	uint64_t msi                          : 1;  /**< BIST Status for MSI Memory Map */
12087453924jmallett	uint64_t ncb_cmd                      : 1;  /**< BIST Status for NCB Outbound Commands */
12097453924jmallett#else
12107453924jmallett	uint64_t ncb_cmd                      : 1;
12117453924jmallett	uint64_t msi                          : 1;
12127453924jmallett	uint64_t dsi0_0                       : 1;
12137453924jmallett	uint64_t dsi0_1                       : 1;
12147453924jmallett	uint64_t dsi1_0                       : 1;
12157453924jmallett	uint64_t dsi1_1                       : 1;
12167453924jmallett	uint64_t reserved_6_8                 : 3;
12177453924jmallett	uint64_t p2n1_p1                      : 1;
12187453924jmallett	uint64_t p2n1_p0                      : 1;
12197453924jmallett	uint64_t p2n1_n                       : 1;
12207453924jmallett	uint64_t p2n1_c1                      : 1;
12217453924jmallett	uint64_t p2n1_c0                      : 1;
12227453924jmallett	uint64_t p2n0_p1                      : 1;
12237453924jmallett	uint64_t p2n0_p0                      : 1;
12247453924jmallett	uint64_t p2n0_n                       : 1;
12257453924jmallett	uint64_t p2n0_c1                      : 1;
12267453924jmallett	uint64_t p2n0_c0                      : 1;
12277453924jmallett	uint64_t reserved_19_24               : 6;
12287453924jmallett	uint64_t cpl_p1                       : 1;
12297453924jmallett	uint64_t cpl_p0                       : 1;
12307453924jmallett	uint64_t n2p1_o                       : 1;
12317453924jmallett	uint64_t n2p1_c                       : 1;
12327453924jmallett	uint64_t n2p0_o                       : 1;
12337453924jmallett	uint64_t n2p0_c                       : 1;
12347453924jmallett	uint64_t ncb_req                      : 1;
12357453924jmallett	uint64_t reserved_32_63               : 32;
12367453924jmallett#endif
12377453924jmallett	} s;
12387453924jmallett	struct cvmx_sli_bist_status_cn61xx {
12397453924jmallett#ifdef __BIG_ENDIAN_BITFIELD
12407453924jmallett	uint64_t reserved_31_63               : 33;
12417453924jmallett	uint64_t n2p0_c                       : 1;  /**< BIST Status for N2P Port0 Cmd */
12427453924jmallett	uint64_t n2p0_o                       : 1;  /**< BIST Status for N2P Port0 Data */
12437453924jmallett	uint64_t reserved_27_28               : 2;
12447453924jmallett	uint64_t cpl_p0                       : 1;  /**< BIST Status for CPL Port 0 */
12457453924jmallett	uint64_t cpl_p1                       : 1;  /**< BIST Status for CPL Port 1 */
12467453924jmallett	uint64_t reserved_19_24               : 6;
12477453924jmallett	uint64_t p2n0_c0                      : 1;  /**< BIST Status for P2N Port0 C0 */
12487453924jmallett	uint64_t p2n0_c1                      : 1;  /**< BIST Status for P2N Port0 C1 */
12497453924jmallett	uint64_t p2n0_n                       : 1;  /**< BIST Status for P2N Port0 N */
12507453924jmallett	uint64_t p2n0_p0                      : 1;  /**< BIST Status for P2N Port0 P0 */
12517453924jmallett	uint64_t p2n0_p1                      : 1;  /**< BIST Status for P2N Port0 P1 */
12527453924jmallett	uint64_t p2n1_c0                      : 1;  /**< BIST Status for P2N Port1 C0 */
12537453924jmallett	uint64_t p2n1_c1                      : 1;  /**< BIST Status for P2N Port1 C1 */
12547453924jmallett	uint64_t p2n1_n                       : 1;  /**< BIST Status for P2N Port1 N */
12557453924jmallett	uint64_t p2n1_p0                      : 1;  /**< BIST Status for P2N Port1 P0 */
12567453924jmallett	uint64_t p2n1_p1                      : 1;  /**< BIST Status for P2N Port1 P1 */
12577453924jmallett	uint64_t reserved_6_8                 : 3;
12587453924jmallett	uint64_t dsi1_1                       : 1;  /**< BIST Status for DSI1 Memory 1 */
12597453924jmallett	uint64_t dsi1_0                       : 1;  /**< BIST Status for DSI1 Memory 0 */
12607453924jmallett	uint64_t dsi0_1                       : 1;  /**< BIST Status for DSI0 Memory 1 */
12617453924jmallett	uint64_t dsi0_0                       : 1;  /**< BIST Status for DSI0 Memory 0 */
12627453924jmallett	uint64_t msi                          : 1;  /**< BIST Status for MSI Memory Map */
12637453924jmallett	uint64_t ncb_cmd                      : 1;  /**< BIST Status for NCB Outbound Commands */
12647453924jmallett#else
12657453924jmallett	uint64_t ncb_cmd                      : 1;
12667453924jmallett	uint64_t msi                          : 1;
12677453924jmallett	uint64_t dsi0_0                       : 1;
12687453924jmallett	uint64_t dsi0_1                       : 1;
12697453924jmallett	uint64_t dsi1_0                       : 1;
12707453924jmallett	uint64_t dsi1_1                       : 1;
12717453924jmallett	uint64_t reserved_6_8                 : 3;
12727453924jmallett	uint64_t p2n1_p1                      : 1;
12737453924jmallett	uint64_t p2n1_p0                      : 1;
12747453924jmallett	uint64_t p2n1_n                       : 1;
12757453924jmallett	uint64_t p2n1_c1                      : 1;
12767453924jmallett	uint64_t p2n1_c0                      : 1;
12777453924jmallett	uint64_t p2n0_p1                      : 1;
12787453924jmallett	uint64_t p2n0_p0                      : 1;
12797453924jmallett	uint64_t p2n0_n                       : 1;
12807453924jmallett	uint64_t p2n0_c1                      : 1;
12817453924jmallett	uint64_t p2n0_c0                      : 1;
12827453924jmallett	uint64_t reserved_19_24               : 6;
12837453924jmallett	uint64_t cpl_p1                       : 1;
12847453924jmallett	uint64_t cpl_p0                       : 1;
12857453924jmallett	uint64_t reserved_27_28               : 2;
12867453924jmallett	uint64_t n2p0_o                       : 1;
12877453924jmallett	uint64_t n2p0_c                       : 1;
12887453924jmallett	uint64_t reserved_31_63               : 33;
12897453924jmallett#endif
12907453924jmallett	} cn61xx;
12917453924jmallett	struct cvmx_sli_bist_status_cn63xx {
12927453924jmallett#ifdef __BIG_ENDIAN_BITFIELD
129376ef03bjmallett	uint64_t reserved_31_63               : 33;
129476ef03bjmallett	uint64_t n2p0_c                       : 1;  /**< BIST Status for N2P Port0 Cmd */
129576ef03bjmallett	uint64_t n2p0_o                       : 1;  /**< BIST Status for N2P Port0 Data */
129676ef03bjmallett	uint64_t n2p1_c                       : 1;  /**< BIST Status for N2P Port1 Cmd */
129776ef03bjmallett	uint64_t n2p1_o                       : 1;  /**< BIST Status for N2P Port1 Data */
129876ef03bjmallett	uint64_t cpl_p0                       : 1;  /**< BIST Status for CPL Port 0 */
129976ef03bjmallett	uint64_t cpl_p1                       : 1;  /**< BIST Status for CPL Port 1 */
130076ef03bjmallett	uint64_t reserved_19_24               : 6;
130176ef03bjmallett	uint64_t p2n0_c0                      : 1;  /**< BIST Status for P2N Port0 C0 */
130276ef03bjmallett	uint64_t p2n0_c1                      : 1;  /**< BIST Status for P2N Port0 C1 */
130376ef03bjmallett	uint64_t p2n0_n                       : 1;  /**< BIST Status for P2N Port0 N */
130476ef03bjmallett	uint64_t p2n0_p0                      : 1;  /**< BIST Status for P2N Port0 P0 */
130576ef03bjmallett	uint64_t p2n0_p1                      : 1;  /**< BIST Status for P2N Port0 P1 */
130676ef03bjmallett	uint64_t p2n1_c0                      : 1;  /**< BIST Status for P2N Port1 C0 */
130776ef03bjmallett	uint64_t p2n1_c1                      : 1;  /**< BIST Status for P2N Port1 C1 */
130876ef03bjmallett	uint64_t p2n1_n                       : 1;  /**< BIST Status for P2N Port1 N */
130976ef03bjmallett	uint64_t p2n1_p0                      : 1;  /**< BIST Status for P2N Port1 P0 */
131076ef03bjmallett	uint64_t p2n1_p1                      : 1;  /**< BIST Status for P2N Port1 P1 */
131176ef03bjmallett	uint64_t reserved_6_8                 : 3;
131276ef03bjmallett	uint64_t dsi1_1                       : 1;  /**< BIST Status for DSI1 Memory 1 */
131376ef03bjmallett	uint64_t dsi1_0                       : 1;  /**< BIST Status for DSI1 Memory 0 */
131476ef03bjmallett	uint64_t dsi0_1                       : 1;  /**< BIST Status for DSI0 Memory 1 */
131576ef03bjmallett	uint64_t dsi0_0                       : 1;  /**< BIST Status for DSI0 Memory 0 */
131676ef03bjmallett	uint64_t msi                          : 1;  /**< BIST Status for MSI Memory Map */
131776ef03bjmallett	uint64_t ncb_cmd                      : 1;  /**< BIST Status for NCB Outbound Commands */
131876ef03bjmallett#else
131976ef03bjmallett	uint64_t ncb_cmd                      : 1;
132076ef03bjmallett	uint64_t msi                          : 1;
132176ef03bjmallett	uint64_t dsi0_0                       : 1;
132276ef03bjmallett	uint64_t dsi0_1                       : 1;
132376ef03bjmallett	uint64_t dsi1_0                       : 1;
132476ef03bjmallett	uint64_t dsi1_1                       : 1;
132576ef03bjmallett	uint64_t reserved_6_8                 : 3;
132676ef03bjmallett	uint64_t p2n1_p1                      : 1;
132776ef03bjmallett	uint64_t p2n1_p0                      : 1;
132876ef03bjmallett	uint64_t p2n1_n                       : 1;
132976ef03bjmallett	uint64_t p2n1_c1                      : 1;
133076ef03bjmallett	uint64_t p2n1_c0                      : 1;
133176ef03bjmallett	uint64_t p2n0_p1                      : 1;
133276ef03bjmallett	uint64_t p2n0_p0                      : 1;
133376ef03bjmallett	uint64_t p2n0_n                       : 1;
133476ef03bjmallett	uint64_t p2n0_c1                      : 1;
133576ef03bjmallett	uint64_t p2n0_c0                      : 1;
133676ef03bjmallett	uint64_t reserved_19_24               : 6;
133776ef03bjmallett	uint64_t cpl_p1                       : 1;
133876ef03bjmallett	uint64_t cpl_p0                       : 1;
133976ef03bjmallett	uint64_t n2p1_o                       : 1;
134076ef03bjmallett	uint64_t n2p1_c                       : 1;
134176ef03bjmallett	uint64_t n2p0_o                       : 1;
134276ef03bjmallett	uint64_t n2p0_c                       : 1;
134376ef03bjmallett	uint64_t reserved_31_63               : 33;
134476ef03bjmallett#endif
13457453924jmallett	} cn63xx;
13467453924jmallett	struct cvmx_sli_bist_status_cn63xx    cn63xxp1;
13477453924jmallett	struct cvmx_sli_bist_status_cn61xx    cn66xx;
13487453924jmallett	struct cvmx_sli_bist_status_s         cn68xx;
13497453924jmallett	struct cvmx_sli_bist_status_s         cn68xxp1;
13507453924jmallett	struct cvmx_sli_bist_status_cn61xx    cnf71xx;
135176ef03bjmallett};
135276ef03bjmalletttypedef union cvmx_sli_bist_status cvmx_sli_bist_status_t;
135376ef03bjmallett
135476ef03bjmallett/**
135576ef03bjmallett * cvmx_sli_ctl_port#
135676ef03bjmallett *
135776ef03bjmallett * SLI_CTL_PORTX = SLI's Control Port X
135876ef03bjmallett *
135976ef03bjmallett * Contains control for access for Port0
136076ef03bjmallett */
13617453924jmallettunion cvmx_sli_ctl_portx {
136276ef03bjmallett	uint64_t u64;
13637453924jmallett	struct cvmx_sli_ctl_portx_s {
13647453924jmallett#ifdef __BIG_ENDIAN_BITFIELD
136576ef03bjmallett	uint64_t reserved_22_63               : 42;
136676ef03bjmallett	uint64_t intd                         : 1;  /**< When '0' Intd wire asserted. Before mapping. */
136776ef03bjmallett	uint64_t intc                         : 1;  /**< When '0' Intc wire asserted. Before mapping. */
136876ef03bjmallett	uint64_t intb                         : 1;  /**< When '0' Intb wire asserted. Before mapping. */
136976ef03bjmallett	uint64_t inta                         : 1;  /**< When '0' Inta wire asserted. Before mapping. */
137076ef03bjmallett	uint64_t dis_port                     : 1;  /**< When set the output to the MAC is disabled. This
137176ef03bjmallett                                                         occurs when the MAC reset line transitions from
137276ef03bjmallett                                                         de-asserted to asserted. Writing a '1' to this
137376ef03bjmallett                                                         location will clear this condition when the MAC is
137476ef03bjmallett                                                         no longer in reset and the output to the MAC is at
137576ef03bjmallett                                                         the begining of a transfer. */
137676ef03bjmallett	uint64_t waitl_com                    : 1;  /**< When set '1' casues the SLI to wait for a commit
137776ef03bjmallett                                                         from the L2C before sending additional completions
137876ef03bjmallett                                                         to the L2C from a MAC.
137976ef03bjmallett                                                         Set this for more conservative behavior. Clear
138076ef03bjmallett                                                         this for more aggressive, higher-performance
138176ef03bjmallett                                                         behavior */
138276ef03bjmallett	uint64_t intd_map                     : 2;  /**< Maps INTD to INTA(00), INTB(01), INTC(10) or
138376ef03bjmallett                                                         INTD (11). */
138476ef03bjmallett	uint64_t intc_map                     : 2;  /**< Maps INTC to INTA(00), INTB(01), INTC(10) or
138576ef03bjmallett                                                         INTD (11). */
138676ef03bjmallett	uint64_t intb_map                     : 2;  /**< Maps INTB to INTA(00), INTB(01), INTC(10) or
138776ef03bjmallett                                                         INTD (11). */
138876ef03bjmallett	uint64_t inta_map                     : 2;  /**< Maps INTA to INTA(00), INTB(01), INTC(10) or
138976ef03bjmallett                                                         INTD (11). */
139076ef03bjmallett	uint64_t ctlp_ro                      : 1;  /**< Relaxed ordering enable for Completion TLPS. */
139176ef03bjmallett	uint64_t reserved_6_6                 : 1;
139276ef03bjmallett	uint64_t ptlp_ro                      : 1;  /**< Relaxed ordering enable for Posted TLPS. */
139376ef03bjmallett	uint64_t reserved_1_4                 : 4;
139476ef03bjmallett	uint64_t wait_com                     : 1;  /**< When set '1' casues the SLI to wait for a commit
139576ef03bjmallett                                                         from the L2C before sending additional stores to
139676ef03bjmallett                                                         the L2C from a MAC.
139776ef03bjmallett                                                         The SLI will request a commit on the last store
139876ef03bjmallett                                                         if more than one STORE operation is required on
139976ef03bjmallett                                                         the NCB.
140076ef03bjmallett                                                         Most applications will not notice a difference, so
140176ef03bjmallett                                                         should not set this bit. Setting the bit is more
140276ef03bjmallett                                                         conservative on ordering, lower performance */
140376ef03bjmallett#else
140476ef03bjmallett	uint64_t wait_com                     : 1;
140576ef03bjmallett	uint64_t reserved_1_4                 : 4;
140676ef03bjmallett	uint64_t ptlp_ro                      : 1;
140776ef03bjmallett	uint64_t reserved_6_6                 : 1;
140876ef03bjmallett	uint64_t ctlp_ro                      : 1;
140976ef03bjmallett	uint64_t inta_map                     : 2;
141076ef03bjmallett	uint64_t intb_map                     : 2;
141176ef03bjmallett	uint64_t intc_map                     : 2;
141276ef03bjmallett	uint64_t intd_map                     : 2;
141376ef03bjmallett	uint64_t waitl_com                    : 1;
141476ef03bjmallett	uint64_t dis_port                     : 1;
141576ef03bjmallett	uint64_t inta                         : 1;
141676ef03bjmallett	uint64_t intb                         : 1;
141776ef03bjmallett	uint64_t intc                         : 1;
141876ef03bjmallett	uint64_t intd                         : 1;
141976ef03bjmallett	uint64_t reserved_22_63               : 42;
142076ef03bjmallett#endif
142176ef03bjmallett	} s;
14227453924jmallett	struct cvmx_sli_ctl_portx_s           cn61xx;
142376ef03bjmallett	struct cvmx_sli_ctl_portx_s           cn63xx;
142476ef03bjmallett	struct cvmx_sli_ctl_portx_s           cn63xxp1;
14257453924jmallett	struct cvmx_sli_ctl_portx_s           cn66xx;
14267453924jmallett	struct cvmx_sli_ctl_portx_s           cn68xx;
14277453924jmallett	struct cvmx_sli_ctl_portx_s           cn68xxp1;
14287453924jmallett	struct cvmx_sli_ctl_portx_s           cnf71xx;
142976ef03bjmallett};
143076ef03bjmalletttypedef union cvmx_sli_ctl_portx cvmx_sli_ctl_portx_t;
143176ef03bjmallett
143276ef03bjmallett/**
143376ef03bjmallett * cvmx_sli_ctl_status
143476ef03bjmallett *
143576ef03bjmallett * SLI_CTL_STATUS = SLI Control Status Register
143676ef03bjmallett *
143776ef03bjmallett * Contains control and status for SLI. Writes to this register are not ordered with writes/reads to the MAC Memory space.
143876ef03bjmallett * To ensure that a write has completed the user must read the register before making an access(i.e. MAC memory space)
143976ef03bjmallett * that requires the value of this register to be updated.
144076ef03bjmallett */
14417453924jmallettunion cvmx_sli_ctl_status {
144276ef03bjmallett	uint64_t u64;
14437453924jmallett	struct cvmx_sli_ctl_status_s {
14447453924jmallett#ifdef __BIG_ENDIAN_BITFIELD
144576ef03bjmallett	uint64_t reserved_20_63               : 44;
144676ef03bjmallett	uint64_t p1_ntags                     : 6;  /**< Number of tags available for MAC Port1.
144776ef03bjmallett                                                         In RC mode 1 tag is needed for each outbound TLP
144876ef03bjmallett                                                         that requires a CPL TLP. In Endpoint mode the
144976ef03bjmallett                                                         number of tags required for a TLP request is
145076ef03bjmallett                                                         1 per 64-bytes of CPL data + 1.
145176ef03bjmallett                                                         This field should only be written as part of
145276ef03bjmallett                                                         reset sequence, before issuing any reads, CFGs, or
145376ef03bjmallett                                                         IO transactions from the core(s). */
14547453924jmallett	uint64_t p0_ntags                     : 6;  /**< Number of tags available for outbound TLPs to the
14557453924jmallett                                                         MACS. One tag is needed for each outbound TLP that
14567453924jmallett                                                         requires a CPL TLP.
145776ef03bjmallett                                                         This field should only be written as part of
145876ef03bjmallett                                                         reset sequence, before issuing any reads, CFGs, or
145976ef03bjmallett                                                         IO transactions from the core(s). */
146076ef03bjmallett	uint64_t chip_rev                     : 8;  /**< The chip revision. */
146176ef03bjmallett#else
146276ef03bjmallett	uint64_t chip_rev                     : 8;
146376ef03bjmallett	uint64_t p0_ntags                     : 6;
146476ef03bjmallett	uint64_t p1_ntags                     : 6;
146576ef03bjmallett	uint64_t reserved_20_63               : 44;
146676ef03bjmallett#endif
146776ef03bjmallett	} s;
14687453924jmallett	struct cvmx_sli_ctl_status_cn61xx {
14697453924jmallett#ifdef __BIG_ENDIAN_BITFIELD
14707453924jmallett	uint64_t reserved_14_63               : 50;
14717453924jmallett	uint64_t p0_ntags                     : 6;  /**< Number of tags available for outbound TLPs to the
14727453924jmallett                                                         MACS. One tag is needed for each outbound TLP that
14737453924jmallett                                                         requires a CPL TLP.
14747453924jmallett                                                         This field should only be written as part of
14757453924jmallett                                                         reset sequence, before issuing any reads, CFGs, or
14767453924jmallett                                                         IO transactions from the core(s). */
14777453924jmallett	uint64_t chip_rev                     : 8;  /**< The chip revision. */
14787453924jmallett#else
14797453924jmallett	uint64_t chip_rev                     : 8;
14807453924jmallett	uint64_t p0_ntags                     : 6;
14817453924jmallett	uint64_t reserved_14_63               : 50;
14827453924jmallett#endif
14837453924jmallett	} cn61xx;
148476ef03bjmallett	struct cvmx_sli_ctl_status_s          cn63xx;
148576ef03bjmallett	struct cvmx_sli_ctl_status_s          cn63xxp1;
14867453924jmallett	struct cvmx_sli_ctl_status_cn61xx     cn66xx;
14877453924jmallett	struct cvmx_sli_ctl_status_s          cn68xx;
14887453924jmallett	struct cvmx_sli_ctl_status_s          cn68xxp1;
14897453924jmallett	struct cvmx_sli_ctl_status_cn61xx     cnf71xx;
149076ef03bjmallett};
149176ef03bjmalletttypedef union cvmx_sli_ctl_status cvmx_sli_ctl_status_t;
149276ef03bjmallett
149376ef03bjmallett/**
149476ef03bjmallett * cvmx_sli_data_out_cnt
149576ef03bjmallett *
149676ef03bjmallett * SLI_DATA_OUT_CNT = SLI DATA OUT COUNT
149776ef03bjmallett *
149876ef03bjmallett * The EXEC data out fifo-count and the data unload counter.
149976ef03bjmallett */
15007453924jmallettunion cvmx_sli_data_out_cnt {
150176ef03bjmallett	uint64_t u64;
15027453924jmallett	struct cvmx_sli_data_out_cnt_s {
15037453924jmallett#ifdef __BIG_ENDIAN_BITFIELD
150476ef03bjmallett	uint64_t reserved_44_63               : 20;
15057453924jmallett	uint64_t p1_ucnt                      : 16; /**< SLI Order-FIFO1 Fifo Unload Count. This counter is
150676ef03bjmallett                                                         incremented by '1' every time a word is removed
150776ef03bjmallett                                                         from the Data Out FIFO, whose count is shown in
15087453924jmallett                                                         P1_FCNT. */
15097453924jmallett	uint64_t p1_fcnt                      : 6;  /**< SLI Order-FIFO1 Data Out Fifo Count. Number of
15107453924jmallett                                                         address data words to be sent out the Order-FIFO
15117453924jmallett                                                         presently buffered in the FIFO. */
15127453924jmallett	uint64_t p0_ucnt                      : 16; /**< SLI Order-FIFO0 Fifo Unload Count. This counter is
151376ef03bjmallett                                                         incremented by '1' every time a word is removed
151476ef03bjmallett                                                         from the Data Out FIFO, whose count is shown in
151576ef03bjmallett                                                         P0_FCNT. */
15167453924jmallett	uint64_t p0_fcnt                      : 6;  /**< SLI Order-FIFO0 Data Out Fifo Count. Number of
15177453924jmallett                                                         address data words to be sent out the Order-FIFO
15187453924jmallett                                                         presently buffered in the FIFO. */
151976ef03bjmallett#else
152076ef03bjmallett	uint64_t p0_fcnt                      : 6;
152176ef03bjmallett	uint64_t p0_ucnt                      : 16;
152276ef03bjmallett	uint64_t p1_fcnt                      : 6;
152376ef03bjmallett	uint64_t p1_ucnt                      : 16;
152476ef03bjmallett	uint64_t reserved_44_63               : 20;
152576ef03bjmallett#endif
152676ef03bjmallett	} s;
15277453924jmallett	struct cvmx_sli_data_out_cnt_s        cn61xx;
152876ef03bjmallett	struct cvmx_sli_data_out_cnt_s        cn63xx;
152976ef03bjmallett	struct cvmx_sli_data_out_cnt_s        cn63xxp1;
15307453924jmallett	struct cvmx_sli_data_out_cnt_s        cn66xx;
15317453924jmallett	struct cvmx_sli_data_out_cnt_s        cn68xx;
15327453924jmallett	struct cvmx_sli_data_out_cnt_s        cn68xxp1;
15337453924jmallett	struct cvmx_sli_data_out_cnt_s        cnf71xx;
153476ef03bjmallett};
153576ef03bjmalletttypedef union cvmx_sli_data_out_cnt cvmx_sli_data_out_cnt_t;
153676ef03bjmallett
153776ef03bjmallett/**
153876ef03bjmallett * cvmx_sli_dbg_data
153976ef03bjmallett *
154076ef03bjmallett * SLI_DBG_DATA = SLI Debug Data Register
154176ef03bjmallett *
154276ef03bjmallett * Value returned on the debug-data lines from the RSLs
154376ef03bjmallett */
15447453924jmallettunion cvmx_sli_dbg_data {
154576ef03bjmallett	uint64_t u64;
15467453924jmallett	struct cvmx_sli_dbg_data_s {
15477453924jmallett#ifdef __BIG_ENDIAN_BITFIELD
154876ef03bjmallett	uint64_t reserved_18_63               : 46;
154976ef03bjmallett	uint64_t dsel_ext                     : 1;  /**< Allows changes in the external pins to set the
155076ef03bjmallett                                                         debug select value. */
155176ef03bjmallett	uint64_t data                         : 17; /**< Value on the debug data lines. */
155276ef03bjmallett#else
155376ef03bjmallett	uint64_t data                         : 17;
155476ef03bjmallett	uint64_t dsel_ext                     : 1;
155576ef03bjmallett	uint64_t reserved_18_63               : 46;
155676ef03bjmallett#endif
155776ef03bjmallett	} s;
15587453924jmallett	struct cvmx_sli_dbg_data_s            cn61xx;
155976ef03bjmallett	struct cvmx_sli_dbg_data_s            cn63xx;
156076ef03bjmallett	struct cvmx_sli_dbg_data_s            cn63xxp1;
15617453924jmallett	struct cvmx_sli_dbg_data_s            cn66xx;
15627453924jmallett	struct cvmx_sli_dbg_data_s            cn68xx;
15637453924jmallett	struct cvmx_sli_dbg_data_s            cn68xxp1;
15647453924jmallett	struct cvmx_sli_dbg_data_s            cnf71xx;
156576ef03bjmallett};
156676ef03bjmalletttypedef union cvmx_sli_dbg_data cvmx_sli_dbg_data_t;
156776ef03bjmallett
156876ef03bjmallett/**
156976ef03bjmallett * cvmx_sli_dbg_select
157076ef03bjmallett *
157176ef03bjmallett * SLI_DBG_SELECT = Debug Select Register
157276ef03bjmallett *
157376ef03bjmallett * Contains the debug select value last written to the RSLs.
157476ef03bjmallett */
15757453924jmallettunion cvmx_sli_dbg_select {
157676ef03bjmallett	uint64_t u64;
15777453924jmallett	struct cvmx_sli_dbg_select_s {
15787453924jmallett#ifdef __BIG_ENDIAN_BITFIELD
157976ef03bjmallett	uint64_t reserved_33_63               : 31;
158076ef03bjmallett	uint64_t adbg_sel                     : 1;  /**< When set '1' the SLI_DBG_DATA[DATA] will only be
158176ef03bjmallett                                                         loaded when SLI_DBG_DATA[DATA] bit [16] is a '1'.
158276ef03bjmallett                                                         When the debug data comes from an Async-RSL bit
158376ef03bjmallett                                                         16 is used to tell that the data present is valid. */
158476ef03bjmallett	uint64_t dbg_sel                      : 32; /**< When this register is written the RML will write
158576ef03bjmallett                                                         all "F"s to the previous RTL to disable it from
158676ef03bjmallett                                                         sending Debug-Data. The RML will then send a write
158776ef03bjmallett                                                         to the new RSL with the supplied Debug-Select
158876ef03bjmallett                                                         value. Because it takes time for the new Debug
158976ef03bjmallett                                                         Select value to take effect and the requested
159076ef03bjmallett                                                         Debug-Data to return, time is needed to the new
159176ef03bjmallett                                                         Debug-Data to arrive.  The inititator of the Debug
159276ef03bjmallett                                                         Select should issue a read to a CSR before reading
159376ef03bjmallett                                                         the Debug Data (this read could also be to the
159476ef03bjmallett                                                         SLI_DBG_DATA but the returned value for the first
159576ef03bjmallett                                                         read will return NS data. */
159676ef03bjmallett#else
159776ef03bjmallett	uint64_t dbg_sel                      : 32;
159876ef03bjmallett	uint64_t adbg_sel                     : 1;
159976ef03bjmallett	uint64_t reserved_33_63               : 31;
160076ef03bjmallett#endif
160176ef03bjmallett	} s;
16027453924jmallett	struct cvmx_sli_dbg_select_s          cn61xx;
160376ef03bjmallett	struct cvmx_sli_dbg_select_s          cn63xx;
160476ef03bjmallett	struct cvmx_sli_dbg_select_s          cn63xxp1;
16057453924jmallett	struct cvmx_sli_dbg_select_s          cn66xx;
16067453924jmallett	struct cvmx_sli_dbg_select_s          cn68xx;
16077453924jmallett	struct cvmx_sli_dbg_select_s          cn68xxp1;
16087453924jmallett	struct cvmx_sli_dbg_select_s          cnf71xx;
160976ef03bjmallett};
161076ef03bjmalletttypedef union cvmx_sli_dbg_select cvmx_sli_dbg_select_t;
161176ef03bjmallett
161276ef03bjmallett/**
161376ef03bjmallett * cvmx_sli_dma#_cnt
161476ef03bjmallett *
161576ef03bjmallett * SLI_DMAx_CNT = SLI DMA Count
161676ef03bjmallett *
161776ef03bjmallett * The DMA Count value.
161876ef03bjmallett */
16197453924jmallettunion cvmx_sli_dmax_cnt {
162076ef03bjmallett	uint64_t u64;
16217453924jmallett	struct cvmx_sli_dmax_cnt_s {
16227453924jmallett#ifdef __BIG_ENDIAN_BITFIELD
162376ef03bjmallett	uint64_t reserved_32_63               : 32;
162476ef03bjmallett	uint64_t cnt                          : 32; /**< The DMA counter.
162576ef03bjmallett                                                         Writing this field will cause the written value
162676ef03bjmallett                                                         to be subtracted from DMA. HW will optionally
162776ef03bjmallett                                                         increment this field after it completes an
162876ef03bjmallett                                                         OUTBOUND or EXTERNAL-ONLY DMA instruction. These
162976ef03bjmallett                                                         increments may cause interrupts. Refer to
163076ef03bjmallett                                                         SLI_DMAx_INT_LEVEL and SLI_INT_SUM[DCNT,DTIME]. */
163176ef03bjmallett#else
163276ef03bjmallett	uint64_t cnt                          : 32;
163376ef03bjmallett	uint64_t reserved_32_63               : 32;
163476ef03bjmallett#endif
163576ef03bjmallett	} s;
16367453924jmallett	struct cvmx_sli_dmax_cnt_s            cn61xx;
163776ef03bjmallett	struct cvmx_sli_dmax_cnt_s            cn63xx;
163876ef03bjmallett	struct cvmx_sli_dmax_cnt_s            cn63xxp1;
16397453924jmallett	struct cvmx_sli_dmax_cnt_s            cn66xx;
16407453924jmallett	struct cvmx_sli_dmax_cnt_s            cn68xx;
16417453924jmallett	struct cvmx_sli_dmax_cnt_s            cn68xxp1;
16427453924jmallett	struct cvmx_sli_dmax_cnt_s            cnf71xx;
164376ef03bjmallett};
164476ef03bjmalletttypedef union cvmx_sli_dmax_cnt cvmx_sli_dmax_cnt_t;
164576ef03bjmallett
164676ef03bjmallett/**
164776ef03bjmallett * cvmx_sli_dma#_int_level
164876ef03bjmallett *
164976ef03bjmallett * SLI_DMAx_INT_LEVEL = SLI DMAx Interrupt Level
165076ef03bjmallett *
165176ef03bjmallett * Thresholds for DMA count and timer interrupts.
165276ef03bjmallett */
16537453924jmallettunion cvmx_sli_dmax_int_level {
165476ef03bjmallett	uint64_t u64;
16557453924jmallett	struct cvmx_sli_dmax_int_level_s {
16567453924jmallett#ifdef __BIG_ENDIAN_BITFIELD
165776ef03bjmallett	uint64_t time                         : 32; /**< Whenever the SLI_DMAx_TIM[TIM] timer exceeds
165876ef03bjmallett                                                         this value, SLI_INT_SUM[DTIME<x>] is set.
165976ef03bjmallett                                                         The SLI_DMAx_TIM[TIM] timer increments every SLI
166076ef03bjmallett                                                         clock whenever SLI_DMAx_CNT[CNT]!=0, and is
166176ef03bjmallett                                                         cleared when SLI_INT_SUM[DTIME<x>] is written with
166276ef03bjmallett                                                         one. */
166376ef03bjmallett	uint64_t cnt                          : 32; /**< Whenever SLI_DMAx_CNT[CNT] exceeds this value,
166476ef03bjmallett                                                         SLI_INT_SUM[DCNT<x>] is set. */
166576ef03bjmallett#else
166676ef03bjmallett	uint64_t cnt                          : 32;
166776ef03bjmallett	uint64_t time                         : 32;
166876ef03bjmallett#endif
166976ef03bjmallett	} s;
16707453924jmallett	struct cvmx_sli_dmax_int_level_s      cn61xx;
167176ef03bjmallett	struct cvmx_sli_dmax_int_level_s      cn63xx;
167276ef03bjmallett	struct cvmx_sli_dmax_int_level_s      cn63xxp1;
16737453924jmallett	struct cvmx_sli_dmax_int_level_s      cn66xx;
16747453924jmallett	struct cvmx_sli_dmax_int_level_s      cn68xx;
16757453924jmallett	struct cvmx_sli_dmax_int_level_s      cn68xxp1;
16767453924jmallett	struct cvmx_sli_dmax_int_level_s      cnf71xx;
167776ef03bjmallett};
167876ef03bjmalletttypedef union cvmx_sli_dmax_int_level cvmx_sli_dmax_int_level_t;
167976ef03bjmallett
168076ef03bjmallett/**
168176ef03bjmallett * cvmx_sli_dma#_tim
168276ef03bjmallett *
168376ef03bjmallett * SLI_DMAx_TIM = SLI DMA Timer
168476ef03bjmallett *
168576ef03bjmallett * The DMA Timer value.
168676ef03bjmallett */
16877453924jmallettunion cvmx_sli_dmax_tim {
168876ef03bjmallett	uint64_t u64;
16897453924jmallett	struct cvmx_sli_dmax_tim_s {
16907453924jmallett#ifdef __BIG_ENDIAN_BITFIELD
169176ef03bjmallett	uint64_t reserved_32_63               : 32;
169276ef03bjmallett	uint64_t tim                          : 32; /**< The DMA timer value.
169376ef03bjmallett                                                         The timer will increment when SLI_DMAx_CNT[CNT]!=0
169476ef03bjmallett                                                         and will clear when SLI_DMAx_CNT[CNT]==0 */
169576ef03bjmallett#else
169676ef03bjmallett	uint64_t tim                          : 32;
169776ef03bjmallett	uint64_t reserved_32_63               : 32;
169876ef03bjmallett#endif
169976ef03bjmallett	} s;
17007453924jmallett	struct cvmx_sli_dmax_tim_s            cn61xx;
170176ef03bjmallett	struct cvmx_sli_dmax_tim_s            cn63xx;
170276ef03bjmallett	struct cvmx_sli_dmax_tim_s            cn63xxp1;
17037453924jmallett	struct cvmx_sli_dmax_tim_s            cn66xx;
17047453924jmallett	struct cvmx_sli_dmax_tim_s            cn68xx;
17057453924jmallett	struct cvmx_sli_dmax_tim_s            cn68xxp1;
17067453924jmallett	struct cvmx_sli_dmax_tim_s            cnf71xx;
170776ef03bjmallett};
170876ef03bjmalletttypedef union cvmx_sli_dmax_tim cvmx_sli_dmax_tim_t;
170976ef03bjmallett
171076ef03bjmallett/**
171176ef03bjmallett * cvmx_sli_int_enb_ciu
171276ef03bjmallett *
171376ef03bjmallett * SLI_INT_ENB_CIU = SLI's Interrupt Enable CIU Register
171476ef03bjmallett *
171576ef03bjmallett * Used to enable the various interrupting conditions of SLI
171676ef03bjmallett */
17177453924jmallettunion cvmx_sli_int_enb_ciu {
171876ef03bjmallett	uint64_t u64;
17197453924jmallett	struct cvmx_sli_int_enb_ciu_s {
17207453924jmallett#ifdef __BIG_ENDIAN_BITFIELD
17217453924jmallett	uint64_t reserved_62_63               : 2;
17227453924jmallett	uint64_t pipe_err                     : 1;  /**< Illegal packet csr address. */
172376ef03bjmallett	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
17247453924jmallett	uint64_t sprt3_err                    : 1;  /**< Error Response received on SLI port 3. */
17257453924jmallett	uint64_t sprt2_err                    : 1;  /**< Error Response received on SLI port 2. */
172676ef03bjmallett	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
172776ef03bjmallett	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
172876ef03bjmallett	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
172976ef03bjmallett	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
173076ef03bjmallett	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
173176ef03bjmallett	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
173276ef03bjmallett	uint64_t pin_bp                       : 1;  /**< Packet Input Count exceeded WMARK. */
173376ef03bjmallett	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
173476ef03bjmallett	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
173576ef03bjmallett	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
173676ef03bjmallett	uint64_t reserved_38_47               : 10;
173776ef03bjmallett	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
173876ef03bjmallett	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
173976ef03bjmallett	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
17407453924jmallett	uint64_t reserved_28_31               : 4;
17417453924jmallett	uint64_t m3_un_wi                     : 1;  /**< Reserved. */
17427453924jmallett	uint64_t m3_un_b0                     : 1;  /**< Reserved. */
17437453924jmallett	uint64_t m3_up_wi                     : 1;  /**< Reserved. */
17447453924jmallett	uint64_t m3_up_b0                     : 1;  /**< Reserved. */
17457453924jmallett	uint64_t m2_un_wi                     : 1;  /**< Reserved. */
17467453924jmallett	uint64_t m2_un_b0                     : 1;  /**< Reserved. */
17477453924jmallett	uint64_t m2_up_wi                     : 1;  /**< Reserved. */
17487453924jmallett	uint64_t m2_up_b0                     : 1;  /**< Reserved. */
17497453924jmallett	uint64_t reserved_18_19               : 2;
175076ef03bjmallett	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
175176ef03bjmallett                                                         interrupt on the RSL.
175276ef03bjmallett                                                         THIS SHOULD NEVER BE SET */
175376ef03bjmallett	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
175476ef03bjmallett                                                         interrupt on the RSL.
175576ef03bjmallett                                                         THIS SHOULD NEVER BE SET */
175676ef03bjmallett	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
175776ef03bjmallett                                                         interrupt on the RSL. */
175876ef03bjmallett	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
175976ef03bjmallett                                                         interrupt on the RSL. */
176076ef03bjmallett	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
176176ef03bjmallett                                                         interrupt on the RSL. */
176276ef03bjmallett	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
176376ef03bjmallett                                                         interrupt on the RSL. */
176476ef03bjmallett	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
176576ef03bjmallett                                                         interrupt on the RSL. */
176676ef03bjmallett	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
176776ef03bjmallett                                                         interrupt on the RSL. */
176876ef03bjmallett	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
176976ef03bjmallett                                                         interrupt on the RSL. */
177076ef03bjmallett	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
177176ef03bjmallett                                                         interrupt on the RSL. */
177276ef03bjmallett	uint64_t reserved_6_7                 : 2;
177376ef03bjmallett	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
177476ef03bjmallett                                                         interrupt on the RSL. */
177576ef03bjmallett	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
177676ef03bjmallett                                                         interrupt on the RSL. */
177776ef03bjmallett	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
177876ef03bjmallett                                                         interrupt on the RSL. */
177976ef03bjmallett	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
178076ef03bjmallett                                                         interrupt on the RSL. */
178176ef03bjmallett	uint64_t reserved_1_1                 : 1;
178276ef03bjmallett	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
178376ef03bjmallett                                                         interrupt on the RSL. */
178476ef03bjmallett#else
178576ef03bjmallett	uint64_t rml_to                       : 1;
178676ef03bjmallett	uint64_t reserved_1_1                 : 1;
178776ef03bjmallett	uint64_t bar0_to                      : 1;
178876ef03bjmallett	uint64_t iob2big                      : 1;
178976ef03bjmallett	uint64_t pcnt                         : 1;
179076ef03bjmallett	uint64_t ptime                        : 1;
179176ef03bjmallett	uint64_t reserved_6_7                 : 2;
179276ef03bjmallett	uint64_t m0_up_b0                     : 1;
179376ef03bjmallett	uint64_t m0_up_wi                     : 1;
179476ef03bjmallett	uint64_t m0_un_b0                     : 1;
179576ef03bjmallett	uint64_t m0_un_wi                     : 1;
179676ef03bjmallett	uint64_t m1_up_b0                     : 1;
179776ef03bjmallett	uint64_t m1_up_wi                     : 1;
179876ef03bjmallett	uint64_t m1_un_b0                     : 1;
179976ef03bjmallett	uint64_t m1_un_wi                     : 1;
180076ef03bjmallett	uint64_t mio_int0                     : 1;
180176ef03bjmallett	uint64_t mio_int1                     : 1;
18027453924jmallett	uint64_t reserved_18_19               : 2;
18037453924jmallett	uint64_t m2_up_b0                     : 1;
18047453924jmallett	uint64_t m2_up_wi                     : 1;
18057453924jmallett	uint64_t m2_un_b0                     : 1;
18067453924jmallett	uint64_t m2_un_wi                     : 1;
18077453924jmallett	uint64_t m3_up_b0                     : 1;
18087453924jmallett	uint64_t m3_up_wi                     : 1;
18097453924jmallett	uint64_t m3_un_b0                     : 1;
18107453924jmallett	uint64_t m3_un_wi                     : 1;
18117453924jmallett	uint64_t reserved_28_31               : 4;
181276ef03bjmallett	uint64_t dmafi                        : 2;
181376ef03bjmallett	uint64_t dcnt                         : 2;
181476ef03bjmallett	uint64_t dtime                        : 2;
181576ef03bjmallett	uint64_t reserved_38_47               : 10;
181676ef03bjmallett	uint64_t pidbof                       : 1;
181776ef03bjmallett	uint64_t psldbof                      : 1;
181876ef03bjmallett	uint64_t pout_err                     : 1;
181976ef03bjmallett	uint64_t pin_bp                       : 1;
182076ef03bjmallett	uint64_t pgl_err                      : 1;
182176ef03bjmallett	uint64_t pdi_err                      : 1;
182276ef03bjmallett	uint64_t pop_err                      : 1;
182376ef03bjmallett	uint64_t pins_err                     : 1;
182476ef03bjmallett	uint64_t sprt0_err                    : 1;
182576ef03bjmallett	uint64_t sprt1_err                    : 1;
18267453924jmallett	uint64_t sprt2_err                    : 1;
18277453924jmallett	uint64_t sprt3_err                    : 1;
182876ef03bjmallett	uint64_t ill_pad                      : 1;
18297453924jmallett	uint64_t pipe_err                     : 1;
18307453924jmallett	uint64_t reserved_62_63               : 2;
183176ef03bjmallett#endif
183276ef03bjmallett	} s;
18337453924jmallett	struct cvmx_sli_int_enb_ciu_cn61xx {
18347453924jmallett#ifdef __BIG_ENDIAN_BITFIELD
183576ef03bjmallett	uint64_t reserved_61_63               : 3;
183676ef03bjmallett	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
18377453924jmallett	uint64_t sprt3_err                    : 1;  /**< Error Response received on SLI port 3. */
18387453924jmallett	uint64_t sprt2_err                    : 1;  /**< Error Response received on SLI port 2. */
183976ef03bjmallett	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
184076ef03bjmallett	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
184176ef03bjmallett	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
184276ef03bjmallett	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
184376ef03bjmallett	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
184476ef03bjmallett	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
184576ef03bjmallett	uint64_t pin_bp                       : 1;  /**< Packet Input Count exceeded WMARK. */
184676ef03bjmallett	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
184776ef03bjmallett	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
184876ef03bjmallett	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
184976ef03bjmallett	uint64_t reserved_38_47               : 10;
185076ef03bjmallett	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
185176ef03bjmallett	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
185276ef03bjmallett	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
18537453924jmallett	uint64_t reserved_28_31               : 4;
18547453924jmallett	uint64_t m3_un_wi                     : 1;  /**< Reserved. */
18557453924jmallett	uint64_t m3_un_b0                     : 1;  /**< Reserved. */
18567453924jmallett	uint64_t m3_up_wi                     : 1;  /**< Reserved. */
18577453924jmallett	uint64_t m3_up_b0                     : 1;  /**< Reserved. */
18587453924jmallett	uint64_t m2_un_wi                     : 1;  /**< Reserved. */
18597453924jmallett	uint64_t m2_un_b0                     : 1;  /**< Reserved. */
18607453924jmallett	uint64_t m2_up_wi                     : 1;  /**< Reserved. */
18617453924jmallett	uint64_t m2_up_b0                     : 1;  /**< Reserved. */
18627453924jmallett	uint64_t reserved_18_19               : 2;
186376ef03bjmallett	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
18647453924jmallett                                                         interrupt on the RSL.
18657453924jmallett                                                         THIS SHOULD NEVER BE SET */
186676ef03bjmallett	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
18677453924jmallett                                                         interrupt on the RSL.
18687453924jmallett                                                         THIS SHOULD NEVER BE SET */
186976ef03bjmallett	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
18707453924jmallett                                                         interrupt on the RSL. */
187176ef03bjmallett	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
18727453924jmallett                                                         interrupt on the RSL. */
187376ef03bjmallett	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
18747453924jmallett                                                         interrupt on the RSL. */
187576ef03bjmallett	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
18767453924jmallett                                                         interrupt on the RSL. */
187776ef03bjmallett	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
18787453924jmallett                                                         interrupt on the RSL. */
187976ef03bjmallett	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
18807453924jmallett                                                         interrupt on the RSL. */
188176ef03bjmallett	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
18827453924jmallett                                                         interrupt on the RSL. */
188376ef03bjmallett	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
18847453924jmallett                                                         interrupt on the RSL. */
188576ef03bjmallett	uint64_t reserved_6_7                 : 2;
188676ef03bjmallett	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
18877453924jmallett                                                         interrupt on the RSL. */
188876ef03bjmallett	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
18897453924jmallett                                                         interrupt on the RSL. */
189076ef03bjmallett	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
18917453924jmallett                                                         interrupt on the RSL. */
189276ef03bjmallett	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
18937453924jmallett                                                         interrupt on the RSL. */
189476ef03bjmallett	uint64_t reserved_1_1                 : 1;
189576ef03bjmallett	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
18967453924jmallett                                                         interrupt on the RSL. */
189776ef03bjmallett#else
189876ef03bjmallett	uint64_t rml_to                       : 1;
189976ef03bjmallett	uint64_t reserved_1_1                 : 1;
190076ef03bjmallett	uint64_t bar0_to                      : 1;
190176ef03bjmallett	uint64_t iob2big                      : 1;
190276ef03bjmallett	uint64_t pcnt                         : 1;
190376ef03bjmallett	uint64_t ptime                        : 1;
190476ef03bjmallett	uint64_t reserved_6_7                 : 2;
190576ef03bjmallett	uint64_t m0_up_b0                     : 1;
190676ef03bjmallett	uint64_t m0_up_wi                     : 1;
190776ef03bjmallett	uint64_t m0_un_b0                     : 1;
190876ef03bjmallett	uint64_t m0_un_wi                     : 1;
190976ef03bjmallett	uint64_t m1_up_b0                     : 1;
191076ef03bjmallett	uint64_t m1_up_wi                     : 1;
191176ef03bjmallett	uint64_t m1_un_b0                     : 1;
191276ef03bjmallett	uint64_t m1_un_wi                     : 1;
191376ef03bjmallett	uint64_t mio_int0                     : 1;
191476ef03bjmallett	uint64_t mio_int1                     : 1;
19157453924jmallett	uint64_t reserved_18_19               : 2;
19167453924jmallett	uint64_t m2_up_b0                     : 1;
19177453924jmallett	uint64_t m2_up_wi                     : 1;
19187453924jmallett	uint64_t m2_un_b0                     : 1;
19197453924jmallett	uint64_t m2_un_wi                     : 1;
19207453924jmallett	uint64_t m3_up_b0                     : 1;
19217453924jmallett	uint64_t m3_up_wi                     : 1;
19227453924jmallett	uint64_t m3_un_b0                     : 1;
19237453924jmallett	uint64_t m3_un_wi                     : 1;
19247453924jmallett	uint64_t reserved_28_31               : 4;
192576ef03bjmallett	uint64_t dmafi                        : 2;
192676ef03bjmallett	uint64_t dcnt                         : 2;
192776ef03bjmallett	uint64_t dtime                        : 2;
192876ef03bjmallett	uint64_t reserved_38_47               : 10;
192976ef03bjmallett	uint64_t pidbof                       : 1;
193076ef03bjmallett	uint64_t psldbof                      : 1;
193176ef03bjmallett	uint64_t pout_err                     : 1;
193276ef03bjmallett	uint64_t pin_bp                       : 1;
193376ef03bjmallett	uint64_t pgl_err                      : 1;
193476ef03bjmallett	uint64_t pdi_err                      : 1;
193576ef03bjmallett	uint64_t pop_err                      : 1;
193676ef03bjmallett	uint64_t pins_err                     : 1;
193776ef03bjmallett	uint64_t sprt0_err                    : 1;
193876ef03bjmallett	uint64_t sprt1_err                    : 1;
19397453924jmallett	uint64_t sprt2_err                    : 1;
19407453924jmallett	uint64_t sprt3_err                    : 1;
194176ef03bjmallett	uint64_t ill_pad                      : 1;
194276ef03bjmallett	uint64_t reserved_61_63               : 3;
194376ef03bjmallett#endif
19447453924jmallett	} cn61xx;
19457453924jmallett	struct cvmx_sli_int_enb_ciu_cn63xx {
19467453924jmallett#ifdef __BIG_ENDIAN_BITFIELD
194776ef03bjmallett	uint64_t reserved_61_63               : 3;
19487453924jmallett	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
194976ef03bjmallett	uint64_t reserved_58_59               : 2;
19507453924jmallett	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
19517453924jmallett	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
19527453924jmallett	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
19537453924jmallett	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
19547453924jmallett	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
19557453924jmallett	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
19567453924jmallett	uint64_t pin_bp                       : 1;  /**< Packet Input Count exceeded WMARK. */
19577453924jmallett	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
19587453924jmallett	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
19597453924jmallett	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
19607453924jmallett	uint64_t reserved_38_47               : 10;
19617453924jmallett	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
19627453924jmallett	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
19637453924jmallett	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
19647453924jmallett	uint64_t reserved_18_31               : 14;
19657453924jmallett	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
19667453924jmallett                                                         interrupt on the RSL.
19677453924jmallett                                                         THIS SHOULD NEVER BE SET */
19687453924jmallett	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
19697453924jmallett                                                         interrupt on the RSL.
19707453924jmallett                                                         THIS SHOULD NEVER BE SET */
19717453924jmallett	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
19727453924jmallett                                                         interrupt on the RSL. */
19737453924jmallett	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
19747453924jmallett                                                         interrupt on the RSL. */
19757453924jmallett	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
19767453924jmallett                                                         interrupt on the RSL. */
19777453924jmallett	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
19787453924jmallett                                                         interrupt on the RSL. */
19797453924jmallett	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
19807453924jmallett                                                         interrupt on the RSL. */
19817453924jmallett	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
19827453924jmallett                                                         interrupt on the RSL. */
19837453924jmallett	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
19847453924jmallett                                                         interrupt on the RSL. */
19857453924jmallett	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
19867453924jmallett                                                         interrupt on the RSL. */
19877453924jmallett	uint64_t reserved_6_7                 : 2;
19887453924jmallett	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
19897453924jmallett                                                         interrupt on the RSL. */
19907453924jmallett	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
19917453924jmallett                                                         interrupt on the RSL. */
19927453924jmallett	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
19937453924jmallett                                                         interrupt on the RSL. */
19947453924jmallett	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
19957453924jmallett                                                         interrupt on the RSL. */
19967453924jmallett	uint64_t reserved_1_1                 : 1;
19977453924jmallett	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
19987453924jmallett                                                         interrupt on the RSL. */
19997453924jmallett#else
20007453924jmallett	uint64_t rml_to                       : 1;
20017453924jmallett	uint64_t reserved_1_1                 : 1;
20027453924jmallett	uint64_t bar0_to                      : 1;
20037453924jmallett	uint64_t iob2big                      : 1;
20047453924jmallett	uint64_t pcnt                         : 1;
20057453924jmallett	uint64_t ptime                        : 1;
20067453924jmallett	uint64_t reserved_6_7                 : 2;
20077453924jmallett	uint64_t m0_up_b0                     : 1;
20087453924jmallett	uint64_t m0_up_wi                     : 1;
20097453924jmallett	uint64_t m0_un_b0                     : 1;
20107453924jmallett	uint64_t m0_un_wi                     : 1;
20117453924jmallett	uint64_t m1_up_b0                     : 1;
20127453924jmallett	uint64_t m1_up_wi                     : 1;
20137453924jmallett	uint64_t m1_un_b0                     : 1;
20147453924jmallett	uint64_t m1_un_wi                     : 1;
20157453924jmallett	uint64_t mio_int0                     : 1;
20167453924jmallett	uint64_t mio_int1                     : 1;
20177453924jmallett	uint64_t reserved_18_31               : 14;
20187453924jmallett	uint64_t dmafi                        : 2;
20197453924jmallett	uint64_t dcnt                         : 2;
20207453924jmallett	uint64_t dtime                        : 2;
20217453924jmallett	uint64_t reserved_38_47               : 10;
20227453924jmallett	uint64_t pidbof                       : 1;
20237453924jmallett	uint64_t psldbof                      : 1;
20247453924jmallett	uint64_t pout_err                     : 1;
20257453924jmallett	uint64_t pin_bp                       : 1;
20267453924jmallett	uint64_t pgl_err                      : 1;
20277453924jmallett	uint64_t pdi_err                      : 1;
20287453924jmallett	uint64_t pop_err                      : 1;
20297453924jmallett	uint64_t pins_err                     : 1;
20307453924jmallett	uint64_t sprt0_err                    : 1;
20317453924jmallett	uint64_t sprt1_err                    : 1;
20327453924jmallett	uint64_t reserved_58_59               : 2;
20337453924jmallett	uint64_t ill_pad                      : 1;
20347453924jmallett	uint64_t reserved_61_63               : 3;
20357453924jmallett#endif
20367453924jmallett	} cn63xx;
20377453924jmallett	struct cvmx_sli_int_enb_ciu_cn63xx    cn63xxp1;
20387453924jmallett	struct cvmx_sli_int_enb_ciu_cn61xx    cn66xx;
20397453924jmallett	struct cvmx_sli_int_enb_ciu_cn68xx {
20407453924jmallett#ifdef __BIG_ENDIAN_BITFIELD
20417453924jmallett	uint64_t reserved_62_63               : 2;
20427453924jmallett	uint64_t pipe_err                     : 1;  /**< Illegal packet csr address. */
20437453924jmallett	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
20447453924jmallett	uint64_t reserved_58_59               : 2;
20457453924jmallett	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
20467453924jmallett	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
20477453924jmallett	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
20487453924jmallett	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
20497453924jmallett	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
20507453924jmallett	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
20517453924jmallett	uint64_t reserved_51_51               : 1;
20527453924jmallett	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
20537453924jmallett	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
20547453924jmallett	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
20557453924jmallett	uint64_t reserved_38_47               : 10;
20567453924jmallett	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
20577453924jmallett	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
20587453924jmallett	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
20597453924jmallett	uint64_t reserved_18_31               : 14;
20607453924jmallett	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
20617453924jmallett                                                         interrupt on the RSL.
20627453924jmallett                                                         THIS SHOULD NEVER BE SET */
20637453924jmallett	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
20647453924jmallett                                                         interrupt on the RSL.
20657453924jmallett                                                         THIS SHOULD NEVER BE SET */
20667453924jmallett	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
20677453924jmallett                                                         interrupt on the RSL. */
20687453924jmallett	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
20697453924jmallett                                                         interrupt on the RSL. */
20707453924jmallett	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
20717453924jmallett                                                         interrupt on the RSL. */
20727453924jmallett	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
20737453924jmallett                                                         interrupt on the RSL. */
20747453924jmallett	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
20757453924jmallett                                                         interrupt on the RSL. */
20767453924jmallett	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
20777453924jmallett                                                         interrupt on the RSL. */
20787453924jmallett	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
20797453924jmallett                                                         interrupt on the RSL. */
20807453924jmallett	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
20817453924jmallett                                                         interrupt on the RSL. */
20827453924jmallett	uint64_t reserved_6_7                 : 2;
20837453924jmallett	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
20847453924jmallett                                                         interrupt on the RSL. */
20857453924jmallett	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
20867453924jmallett                                                         interrupt on the RSL. */
20877453924jmallett	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
20887453924jmallett                                                         interrupt on the RSL. */
20897453924jmallett	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
20907453924jmallett                                                         interrupt on the RSL. */
20917453924jmallett	uint64_t reserved_1_1                 : 1;
20927453924jmallett	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
20937453924jmallett                                                         interrupt on the RSL. */
20947453924jmallett#else
20957453924jmallett	uint64_t rml_to                       : 1;
20967453924jmallett	uint64_t reserved_1_1                 : 1;
20977453924jmallett	uint64_t bar0_to                      : 1;
20987453924jmallett	uint64_t iob2big                      : 1;
20997453924jmallett	uint64_t pcnt                         : 1;
21007453924jmallett	uint64_t ptime                        : 1;
21017453924jmallett	uint64_t reserved_6_7                 : 2;
21027453924jmallett	uint64_t m0_up_b0                     : 1;
21037453924jmallett	uint64_t m0_up_wi                     : 1;
21047453924jmallett	uint64_t m0_un_b0                     : 1;
21057453924jmallett	uint64_t m0_un_wi                     : 1;
21067453924jmallett	uint64_t m1_up_b0                     : 1;
21077453924jmallett	uint64_t m1_up_wi                     : 1;
21087453924jmallett	uint64_t m1_un_b0                     : 1;
21097453924jmallett	uint64_t m1_un_wi                     : 1;
21107453924jmallett	uint64_t mio_int0                     : 1;
21117453924jmallett	uint64_t mio_int1                     : 1;
21127453924jmallett	uint64_t reserved_18_31               : 14;
21137453924jmallett	uint64_t dmafi                        : 2;
21147453924jmallett	uint64_t dcnt                         : 2;
21157453924jmallett	uint64_t dtime                        : 2;
21167453924jmallett	uint64_t reserved_38_47               : 10;
21177453924jmallett	uint64_t pidbof                       : 1;
21187453924jmallett	uint64_t psldbof                      : 1;
21197453924jmallett	uint64_t pout_err                     : 1;
21207453924jmallett	uint64_t reserved_51_51               : 1;
21217453924jmallett	uint64_t pgl_err                      : 1;
21227453924jmallett	uint64_t pdi_err                      : 1;
21237453924jmallett	uint64_t pop_err                      : 1;
21247453924jmallett	uint64_t pins_err                     : 1;
21257453924jmallett	uint64_t sprt0_err                    : 1;
21267453924jmallett	uint64_t sprt1_err                    : 1;
21277453924jmallett	uint64_t reserved_58_59               : 2;
21287453924jmallett	uint64_t ill_pad                      : 1;
21297453924jmallett	uint64_t pipe_err                     : 1;
21307453924jmallett	uint64_t reserved_62_63               : 2;
21317453924jmallett#endif
21327453924jmallett	} cn68xx;
21337453924jmallett	struct cvmx_sli_int_enb_ciu_cn68xx    cn68xxp1;
21347453924jmallett	struct cvmx_sli_int_enb_ciu_cn61xx    cnf71xx;
21357453924jmallett};
21367453924jmalletttypedef union cvmx_sli_int_enb_ciu cvmx_sli_int_enb_ciu_t;
21377453924jmallett
21387453924jmallett/**
21397453924jmallett * cvmx_sli_int_enb_port#
21407453924jmallett *
21417453924jmallett * SLI_INT_ENB_PORTX = SLI's Interrupt Enable Register per mac port
21427453924jmallett *
21437453924jmallett * Used to allow the generation of interrupts (MSI/INTA) to the PORT X
21447453924jmallett *
21457453924jmallett * Notes:
21467453924jmallett * This CSR is not used when the corresponding MAC is sRIO.
21477453924jmallett *
21487453924jmallett */
21497453924jmallettunion cvmx_sli_int_enb_portx {
21507453924jmallett	uint64_t u64;
21517453924jmallett	struct cvmx_sli_int_enb_portx_s {
21527453924jmallett#ifdef __BIG_ENDIAN_BITFIELD
21537453924jmallett	uint64_t reserved_62_63               : 2;
21547453924jmallett	uint64_t pipe_err                     : 1;  /**< Out of range PIPE value. */
21557453924jmallett	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
21567453924jmallett	uint64_t sprt3_err                    : 1;  /**< Error Response received on SLI port 3. */
21577453924jmallett	uint64_t sprt2_err                    : 1;  /**< Error Response received on SLI port 2. */
21587453924jmallett	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
21597453924jmallett	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
21607453924jmallett	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
21617453924jmallett	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
21627453924jmallett	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
21637453924jmallett	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
21647453924jmallett	uint64_t pin_bp                       : 1;  /**< Packet Input Count exceeded WMARK. */
21657453924jmallett	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
21667453924jmallett	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
21677453924jmallett	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
21687453924jmallett	uint64_t reserved_38_47               : 10;
21697453924jmallett	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
21707453924jmallett	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
21717453924jmallett	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
21727453924jmallett	uint64_t reserved_28_31               : 4;
21737453924jmallett	uint64_t m3_un_wi                     : 1;  /**< Reserved. */
21747453924jmallett	uint64_t m3_un_b0                     : 1;  /**< Reserved. */
21757453924jmallett	uint64_t m3_up_wi                     : 1;  /**< Reserved. */
21767453924jmallett	uint64_t m3_up_b0                     : 1;  /**< Reserved. */
21777453924jmallett	uint64_t m2_un_wi                     : 1;  /**< Reserved. */
21787453924jmallett	uint64_t m2_un_b0                     : 1;  /**< Reserved. */
21797453924jmallett	uint64_t m2_up_wi                     : 1;  /**< Reserved. */
21807453924jmallett	uint64_t m2_up_b0                     : 1;  /**< Reserved. */
21817453924jmallett	uint64_t mac1_int                     : 1;  /**< Enables SLI_INT_SUM[19] to generate an
21827453924jmallett                                                         interrupt to the PCIE-Port1 for MSI/inta.
21837453924jmallett                                                         The valuse of this bit has NO effect on PCIE Port0.
21847453924jmallett                                                         SLI_INT_ENB_PORT0[MAC1_INT] sould NEVER be set. */
21857453924jmallett	uint64_t mac0_int                     : 1;  /**< Enables SLI_INT_SUM[18] to generate an
21867453924jmallett                                                         interrupt to the PCIE-Port0 for MSI/inta.
21877453924jmallett                                                         The valus of this bit has NO effect on PCIE Port1.
21887453924jmallett                                                         SLI_INT_ENB_PORT1[MAC0_INT] sould NEVER be set. */
21897453924jmallett	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
21907453924jmallett                                                         interrupt to the PCIE core for MSI/inta.
21917453924jmallett                                                         SLI_INT_ENB_PORT0[MIO_INT1] should NEVER be set. */
21927453924jmallett	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
21937453924jmallett                                                         interrupt to the PCIE core for MSI/inta.
21947453924jmallett                                                         SLI_INT_ENB_PORT1[MIO_INT0] should NEVER be set. */
21957453924jmallett	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
21967453924jmallett                                                         interrupt to the PCIE core for MSI/inta. */
21977453924jmallett	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
21987453924jmallett                                                         interrupt to the PCIE core for MSI/inta. */
21997453924jmallett	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
22007453924jmallett                                                         interrupt to the PCIE core for MSI/inta. */
22017453924jmallett	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
22027453924jmallett                                                         interrupt to the PCIE core for MSI/inta. */
22037453924jmallett	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
22047453924jmallett                                                         interrupt to the PCIE core for MSI/inta. */
22057453924jmallett	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
22067453924jmallett                                                         interrupt to the PCIE core for MSI/inta. */
22077453924jmallett	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
22087453924jmallett                                                         interrupt to the PCIE core for MSI/inta. */
22097453924jmallett	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
22107453924jmallett                                                         interrupt to the PCIE core for MSI/inta. */
22117453924jmallett	uint64_t reserved_6_7                 : 2;
22127453924jmallett	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
22137453924jmallett                                                         interrupt to the PCIE core for MSI/inta. */
22147453924jmallett	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
22157453924jmallett                                                         interrupt to the PCIE core for MSI/inta. */
22167453924jmallett	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
22177453924jmallett                                                         interrupt to the PCIE core for MSI/inta. */
22187453924jmallett	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
22197453924jmallett                                                         interrupt to the PCIE core for MSI/inta. */
22207453924jmallett	uint64_t reserved_1_1                 : 1;
22217453924jmallett	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
22227453924jmallett                                                         interrupt to the PCIE core for MSI/inta. */
22237453924jmallett#else
22247453924jmallett	uint64_t rml_to                       : 1;
22257453924jmallett	uint64_t reserved_1_1                 : 1;
22267453924jmallett	uint64_t bar0_to                      : 1;
22277453924jmallett	uint64_t iob2big                      : 1;
22287453924jmallett	uint64_t pcnt                         : 1;
22297453924jmallett	uint64_t ptime                        : 1;
22307453924jmallett	uint64_t reserved_6_7                 : 2;
22317453924jmallett	uint64_t m0_up_b0                     : 1;
22327453924jmallett	uint64_t m0_up_wi                     : 1;
22337453924jmallett	uint64_t m0_un_b0                     : 1;
22347453924jmallett	uint64_t m0_un_wi                     : 1;
22357453924jmallett	uint64_t m1_up_b0                     : 1;
22367453924jmallett	uint64_t m1_up_wi                     : 1;
22377453924jmallett	uint64_t m1_un_b0                     : 1;
22387453924jmallett	uint64_t m1_un_wi                     : 1;
22397453924jmallett	uint64_t mio_int0                     : 1;
22407453924jmallett	uint64_t mio_int1                     : 1;
22417453924jmallett	uint64_t mac0_int                     : 1;
22427453924jmallett	uint64_t mac1_int                     : 1;
22437453924jmallett	uint64_t m2_up_b0                     : 1;
22447453924jmallett	uint64_t m2_up_wi                     : 1;
22457453924jmallett	uint64_t m2_un_b0                     : 1;
22467453924jmallett	uint64_t m2_un_wi                     : 1;
22477453924jmallett	uint64_t m3_up_b0                     : 1;
22487453924jmallett	uint64_t m3_up_wi                     : 1;
22497453924jmallett	uint64_t m3_un_b0                     : 1;
22507453924jmallett	uint64_t m3_un_wi                     : 1;
22517453924jmallett	uint64_t reserved_28_31               : 4;
22527453924jmallett	uint64_t dmafi                        : 2;
22537453924jmallett	uint64_t dcnt                         : 2;
22547453924jmallett	uint64_t dtime                        : 2;
22557453924jmallett	uint64_t reserved_38_47               : 10;
22567453924jmallett	uint64_t pidbof                       : 1;
22577453924jmallett	uint64_t psldbof                      : 1;
22587453924jmallett	uint64_t pout_err                     : 1;
22597453924jmallett	uint64_t pin_bp                       : 1;
22607453924jmallett	uint64_t pgl_err                      : 1;
22617453924jmallett	uint64_t pdi_err                      : 1;
22627453924jmallett	uint64_t pop_err                      : 1;
22637453924jmallett	uint64_t pins_err                     : 1;
22647453924jmallett	uint64_t sprt0_err                    : 1;
22657453924jmallett	uint64_t sprt1_err                    : 1;
22667453924jmallett	uint64_t sprt2_err                    : 1;
22677453924jmallett	uint64_t sprt3_err                    : 1;
22687453924jmallett	uint64_t ill_pad                      : 1;
22697453924jmallett	uint64_t pipe_err                     : 1;
22707453924jmallett	uint64_t reserved_62_63               : 2;
22717453924jmallett#endif
22727453924jmallett	} s;
22737453924jmallett	struct cvmx_sli_int_enb_portx_cn61xx {
22747453924jmallett#ifdef __BIG_ENDIAN_BITFIELD
22757453924jmallett	uint64_t reserved_61_63               : 3;
22767453924jmallett	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
22777453924jmallett	uint64_t sprt3_err                    : 1;  /**< Error Response received on SLI port 3. */
22787453924jmallett	uint64_t sprt2_err                    : 1;  /**< Error Response received on SLI port 2. */
22797453924jmallett	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
22807453924jmallett	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
22817453924jmallett	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
22827453924jmallett	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
22837453924jmallett	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
22847453924jmallett	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
22857453924jmallett	uint64_t pin_bp                       : 1;  /**< Packet Input Count exceeded WMARK. */
22867453924jmallett	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
22877453924jmallett	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
22887453924jmallett	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
22897453924jmallett	uint64_t reserved_38_47               : 10;
22907453924jmallett	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
22917453924jmallett	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
22927453924jmallett	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
22937453924jmallett	uint64_t reserved_28_31               : 4;
22947453924jmallett	uint64_t m3_un_wi                     : 1;  /**< Reserved. */
22957453924jmallett	uint64_t m3_un_b0                     : 1;  /**< Reserved. */
22967453924jmallett	uint64_t m3_up_wi                     : 1;  /**< Reserved. */
22977453924jmallett	uint64_t m3_up_b0                     : 1;  /**< Reserved. */
22987453924jmallett	uint64_t m2_un_wi                     : 1;  /**< Reserved. */
22997453924jmallett	uint64_t m2_un_b0                     : 1;  /**< Reserved. */
23007453924jmallett	uint64_t m2_up_wi                     : 1;  /**< Reserved. */
2301