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39
40
41/**
42 * cvmx-sli-defs.h
43 *
44 * Configuration and status register (CSR) type definitions for
45 * Octeon sli.
46 *
47 * This file is auto generated. Do not edit.
48 *
49 * <hr>$Revision$<hr>
50 *
51 */
52#ifndef __CVMX_SLI_DEFS_H__
53#define __CVMX_SLI_DEFS_H__
54
55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56#define CVMX_SLI_BIST_STATUS CVMX_SLI_BIST_STATUS_FUNC()
57static inline uint64_t CVMX_SLI_BIST_STATUS_FUNC(void)
58{
59	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
60		cvmx_warn("CVMX_SLI_BIST_STATUS not supported on this chip\n");
61	return 0x0000000000000580ull;
62}
63#else
64#define CVMX_SLI_BIST_STATUS (0x0000000000000580ull)
65#endif
66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67static inline uint64_t CVMX_SLI_CTL_PORTX(unsigned long offset)
68{
69	if (!(
70	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
71	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
72	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
73	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
74	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
75		cvmx_warn("CVMX_SLI_CTL_PORTX(%lu) is invalid on this chip\n", offset);
76	return 0x0000000000000050ull + ((offset) & 3) * 16;
77}
78#else
79#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16)
80#endif
81#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
82#define CVMX_SLI_CTL_STATUS CVMX_SLI_CTL_STATUS_FUNC()
83static inline uint64_t CVMX_SLI_CTL_STATUS_FUNC(void)
84{
85	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
86		cvmx_warn("CVMX_SLI_CTL_STATUS not supported on this chip\n");
87	return 0x0000000000000570ull;
88}
89#else
90#define CVMX_SLI_CTL_STATUS (0x0000000000000570ull)
91#endif
92#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
93#define CVMX_SLI_DATA_OUT_CNT CVMX_SLI_DATA_OUT_CNT_FUNC()
94static inline uint64_t CVMX_SLI_DATA_OUT_CNT_FUNC(void)
95{
96	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
97		cvmx_warn("CVMX_SLI_DATA_OUT_CNT not supported on this chip\n");
98	return 0x00000000000005F0ull;
99}
100#else
101#define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull)
102#endif
103#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
104#define CVMX_SLI_DBG_DATA CVMX_SLI_DBG_DATA_FUNC()
105static inline uint64_t CVMX_SLI_DBG_DATA_FUNC(void)
106{
107	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
108		cvmx_warn("CVMX_SLI_DBG_DATA not supported on this chip\n");
109	return 0x0000000000000310ull;
110}
111#else
112#define CVMX_SLI_DBG_DATA (0x0000000000000310ull)
113#endif
114#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
115#define CVMX_SLI_DBG_SELECT CVMX_SLI_DBG_SELECT_FUNC()
116static inline uint64_t CVMX_SLI_DBG_SELECT_FUNC(void)
117{
118	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
119		cvmx_warn("CVMX_SLI_DBG_SELECT not supported on this chip\n");
120	return 0x0000000000000300ull;
121}
122#else
123#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull)
124#endif
125#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
126static inline uint64_t CVMX_SLI_DMAX_CNT(unsigned long offset)
127{
128	if (!(
129	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
130	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
131	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
132	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
133	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
134		cvmx_warn("CVMX_SLI_DMAX_CNT(%lu) is invalid on this chip\n", offset);
135	return 0x0000000000000400ull + ((offset) & 1) * 16;
136}
137#else
138#define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16)
139#endif
140#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
141static inline uint64_t CVMX_SLI_DMAX_INT_LEVEL(unsigned long offset)
142{
143	if (!(
144	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
145	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
146	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
147	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
148	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
149		cvmx_warn("CVMX_SLI_DMAX_INT_LEVEL(%lu) is invalid on this chip\n", offset);
150	return 0x00000000000003E0ull + ((offset) & 1) * 16;
151}
152#else
153#define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16)
154#endif
155#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
156static inline uint64_t CVMX_SLI_DMAX_TIM(unsigned long offset)
157{
158	if (!(
159	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
160	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
161	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
162	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
163	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
164		cvmx_warn("CVMX_SLI_DMAX_TIM(%lu) is invalid on this chip\n", offset);
165	return 0x0000000000000420ull + ((offset) & 1) * 16;
166}
167#else
168#define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16)
169#endif
170#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
171#define CVMX_SLI_INT_ENB_CIU CVMX_SLI_INT_ENB_CIU_FUNC()
172static inline uint64_t CVMX_SLI_INT_ENB_CIU_FUNC(void)
173{
174	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
175		cvmx_warn("CVMX_SLI_INT_ENB_CIU not supported on this chip\n");
176	return 0x0000000000003CD0ull;
177}
178#else
179#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull)
180#endif
181#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
182static inline uint64_t CVMX_SLI_INT_ENB_PORTX(unsigned long offset)
183{
184	if (!(
185	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
186	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
187	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
188	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
189	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
190		cvmx_warn("CVMX_SLI_INT_ENB_PORTX(%lu) is invalid on this chip\n", offset);
191	return 0x0000000000000340ull + ((offset) & 1) * 16;
192}
193#else
194#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16)
195#endif
196#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
197#define CVMX_SLI_INT_SUM CVMX_SLI_INT_SUM_FUNC()
198static inline uint64_t CVMX_SLI_INT_SUM_FUNC(void)
199{
200	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
201		cvmx_warn("CVMX_SLI_INT_SUM not supported on this chip\n");
202	return 0x0000000000000330ull;
203}
204#else
205#define CVMX_SLI_INT_SUM (0x0000000000000330ull)
206#endif
207#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
208#define CVMX_SLI_LAST_WIN_RDATA0 CVMX_SLI_LAST_WIN_RDATA0_FUNC()
209static inline uint64_t CVMX_SLI_LAST_WIN_RDATA0_FUNC(void)
210{
211	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
212		cvmx_warn("CVMX_SLI_LAST_WIN_RDATA0 not supported on this chip\n");
213	return 0x0000000000000600ull;
214}
215#else
216#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull)
217#endif
218#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
219#define CVMX_SLI_LAST_WIN_RDATA1 CVMX_SLI_LAST_WIN_RDATA1_FUNC()
220static inline uint64_t CVMX_SLI_LAST_WIN_RDATA1_FUNC(void)
221{
222	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
223		cvmx_warn("CVMX_SLI_LAST_WIN_RDATA1 not supported on this chip\n");
224	return 0x0000000000000610ull;
225}
226#else
227#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull)
228#endif
229#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
230#define CVMX_SLI_LAST_WIN_RDATA2 CVMX_SLI_LAST_WIN_RDATA2_FUNC()
231static inline uint64_t CVMX_SLI_LAST_WIN_RDATA2_FUNC(void)
232{
233	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
234		cvmx_warn("CVMX_SLI_LAST_WIN_RDATA2 not supported on this chip\n");
235	return 0x00000000000006C0ull;
236}
237#else
238#define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull)
239#endif
240#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
241#define CVMX_SLI_LAST_WIN_RDATA3 CVMX_SLI_LAST_WIN_RDATA3_FUNC()
242static inline uint64_t CVMX_SLI_LAST_WIN_RDATA3_FUNC(void)
243{
244	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
245		cvmx_warn("CVMX_SLI_LAST_WIN_RDATA3 not supported on this chip\n");
246	return 0x00000000000006D0ull;
247}
248#else
249#define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull)
250#endif
251#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
252#define CVMX_SLI_MAC_CREDIT_CNT CVMX_SLI_MAC_CREDIT_CNT_FUNC()
253static inline uint64_t CVMX_SLI_MAC_CREDIT_CNT_FUNC(void)
254{
255	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
256		cvmx_warn("CVMX_SLI_MAC_CREDIT_CNT not supported on this chip\n");
257	return 0x0000000000003D70ull;
258}
259#else
260#define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull)
261#endif
262#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
263#define CVMX_SLI_MAC_CREDIT_CNT2 CVMX_SLI_MAC_CREDIT_CNT2_FUNC()
264static inline uint64_t CVMX_SLI_MAC_CREDIT_CNT2_FUNC(void)
265{
266	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
267		cvmx_warn("CVMX_SLI_MAC_CREDIT_CNT2 not supported on this chip\n");
268	return 0x0000000000003E10ull;
269}
270#else
271#define CVMX_SLI_MAC_CREDIT_CNT2 (0x0000000000003E10ull)
272#endif
273#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
274#define CVMX_SLI_MAC_NUMBER CVMX_SLI_MAC_NUMBER_FUNC()
275static inline uint64_t CVMX_SLI_MAC_NUMBER_FUNC(void)
276{
277	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
278		cvmx_warn("CVMX_SLI_MAC_NUMBER not supported on this chip\n");
279	return 0x0000000000003E00ull;
280}
281#else
282#define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull)
283#endif
284#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
285#define CVMX_SLI_MEM_ACCESS_CTL CVMX_SLI_MEM_ACCESS_CTL_FUNC()
286static inline uint64_t CVMX_SLI_MEM_ACCESS_CTL_FUNC(void)
287{
288	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
289		cvmx_warn("CVMX_SLI_MEM_ACCESS_CTL not supported on this chip\n");
290	return 0x00000000000002F0ull;
291}
292#else
293#define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull)
294#endif
295#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
296static inline uint64_t CVMX_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)
297{
298	if (!(
299	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 12) && (offset <= 27)))) ||
300	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 12) && (offset <= 27)))) ||
301	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 12) && (offset <= 27)))) ||
302	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 12) && (offset <= 27)))) ||
303	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 12) && (offset <= 27))))))
304		cvmx_warn("CVMX_SLI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
305	return 0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12;
306}
307#else
308#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12)
309#endif
310#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
311#define CVMX_SLI_MSI_ENB0 CVMX_SLI_MSI_ENB0_FUNC()
312static inline uint64_t CVMX_SLI_MSI_ENB0_FUNC(void)
313{
314	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
315		cvmx_warn("CVMX_SLI_MSI_ENB0 not supported on this chip\n");
316	return 0x0000000000003C50ull;
317}
318#else
319#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull)
320#endif
321#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
322#define CVMX_SLI_MSI_ENB1 CVMX_SLI_MSI_ENB1_FUNC()
323static inline uint64_t CVMX_SLI_MSI_ENB1_FUNC(void)
324{
325	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
326		cvmx_warn("CVMX_SLI_MSI_ENB1 not supported on this chip\n");
327	return 0x0000000000003C60ull;
328}
329#else
330#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull)
331#endif
332#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
333#define CVMX_SLI_MSI_ENB2 CVMX_SLI_MSI_ENB2_FUNC()
334static inline uint64_t CVMX_SLI_MSI_ENB2_FUNC(void)
335{
336	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
337		cvmx_warn("CVMX_SLI_MSI_ENB2 not supported on this chip\n");
338	return 0x0000000000003C70ull;
339}
340#else
341#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull)
342#endif
343#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
344#define CVMX_SLI_MSI_ENB3 CVMX_SLI_MSI_ENB3_FUNC()
345static inline uint64_t CVMX_SLI_MSI_ENB3_FUNC(void)
346{
347	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
348		cvmx_warn("CVMX_SLI_MSI_ENB3 not supported on this chip\n");
349	return 0x0000000000003C80ull;
350}
351#else
352#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull)
353#endif
354#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
355#define CVMX_SLI_MSI_RCV0 CVMX_SLI_MSI_RCV0_FUNC()
356static inline uint64_t CVMX_SLI_MSI_RCV0_FUNC(void)
357{
358	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
359		cvmx_warn("CVMX_SLI_MSI_RCV0 not supported on this chip\n");
360	return 0x0000000000003C10ull;
361}
362#else
363#define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull)
364#endif
365#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
366#define CVMX_SLI_MSI_RCV1 CVMX_SLI_MSI_RCV1_FUNC()
367static inline uint64_t CVMX_SLI_MSI_RCV1_FUNC(void)
368{
369	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
370		cvmx_warn("CVMX_SLI_MSI_RCV1 not supported on this chip\n");
371	return 0x0000000000003C20ull;
372}
373#else
374#define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull)
375#endif
376#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
377#define CVMX_SLI_MSI_RCV2 CVMX_SLI_MSI_RCV2_FUNC()
378static inline uint64_t CVMX_SLI_MSI_RCV2_FUNC(void)
379{
380	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
381		cvmx_warn("CVMX_SLI_MSI_RCV2 not supported on this chip\n");
382	return 0x0000000000003C30ull;
383}
384#else
385#define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull)
386#endif
387#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
388#define CVMX_SLI_MSI_RCV3 CVMX_SLI_MSI_RCV3_FUNC()
389static inline uint64_t CVMX_SLI_MSI_RCV3_FUNC(void)
390{
391	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
392		cvmx_warn("CVMX_SLI_MSI_RCV3 not supported on this chip\n");
393	return 0x0000000000003C40ull;
394}
395#else
396#define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull)
397#endif
398#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
399#define CVMX_SLI_MSI_RD_MAP CVMX_SLI_MSI_RD_MAP_FUNC()
400static inline uint64_t CVMX_SLI_MSI_RD_MAP_FUNC(void)
401{
402	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
403		cvmx_warn("CVMX_SLI_MSI_RD_MAP not supported on this chip\n");
404	return 0x0000000000003CA0ull;
405}
406#else
407#define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull)
408#endif
409#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
410#define CVMX_SLI_MSI_W1C_ENB0 CVMX_SLI_MSI_W1C_ENB0_FUNC()
411static inline uint64_t CVMX_SLI_MSI_W1C_ENB0_FUNC(void)
412{
413	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
414		cvmx_warn("CVMX_SLI_MSI_W1C_ENB0 not supported on this chip\n");
415	return 0x0000000000003CF0ull;
416}
417#else
418#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
419#endif
420#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
421#define CVMX_SLI_MSI_W1C_ENB1 CVMX_SLI_MSI_W1C_ENB1_FUNC()
422static inline uint64_t CVMX_SLI_MSI_W1C_ENB1_FUNC(void)
423{
424	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
425		cvmx_warn("CVMX_SLI_MSI_W1C_ENB1 not supported on this chip\n");
426	return 0x0000000000003D00ull;
427}
428#else
429#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull)
430#endif
431#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
432#define CVMX_SLI_MSI_W1C_ENB2 CVMX_SLI_MSI_W1C_ENB2_FUNC()
433static inline uint64_t CVMX_SLI_MSI_W1C_ENB2_FUNC(void)
434{
435	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
436		cvmx_warn("CVMX_SLI_MSI_W1C_ENB2 not supported on this chip\n");
437	return 0x0000000000003D10ull;
438}
439#else
440#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull)
441#endif
442#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
443#define CVMX_SLI_MSI_W1C_ENB3 CVMX_SLI_MSI_W1C_ENB3_FUNC()
444static inline uint64_t CVMX_SLI_MSI_W1C_ENB3_FUNC(void)
445{
446	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
447		cvmx_warn("CVMX_SLI_MSI_W1C_ENB3 not supported on this chip\n");
448	return 0x0000000000003D20ull;
449}
450#else
451#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull)
452#endif
453#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
454#define CVMX_SLI_MSI_W1S_ENB0 CVMX_SLI_MSI_W1S_ENB0_FUNC()
455static inline uint64_t CVMX_SLI_MSI_W1S_ENB0_FUNC(void)
456{
457	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
458		cvmx_warn("CVMX_SLI_MSI_W1S_ENB0 not supported on this chip\n");
459	return 0x0000000000003D30ull;
460}
461#else
462#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull)
463#endif
464#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
465#define CVMX_SLI_MSI_W1S_ENB1 CVMX_SLI_MSI_W1S_ENB1_FUNC()
466static inline uint64_t CVMX_SLI_MSI_W1S_ENB1_FUNC(void)
467{
468	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
469		cvmx_warn("CVMX_SLI_MSI_W1S_ENB1 not supported on this chip\n");
470	return 0x0000000000003D40ull;
471}
472#else
473#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull)
474#endif
475#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
476#define CVMX_SLI_MSI_W1S_ENB2 CVMX_SLI_MSI_W1S_ENB2_FUNC()
477static inline uint64_t CVMX_SLI_MSI_W1S_ENB2_FUNC(void)
478{
479	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
480		cvmx_warn("CVMX_SLI_MSI_W1S_ENB2 not supported on this chip\n");
481	return 0x0000000000003D50ull;
482}
483#else
484#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull)
485#endif
486#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
487#define CVMX_SLI_MSI_W1S_ENB3 CVMX_SLI_MSI_W1S_ENB3_FUNC()
488static inline uint64_t CVMX_SLI_MSI_W1S_ENB3_FUNC(void)
489{
490	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
491		cvmx_warn("CVMX_SLI_MSI_W1S_ENB3 not supported on this chip\n");
492	return 0x0000000000003D60ull;
493}
494#else
495#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull)
496#endif
497#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
498#define CVMX_SLI_MSI_WR_MAP CVMX_SLI_MSI_WR_MAP_FUNC()
499static inline uint64_t CVMX_SLI_MSI_WR_MAP_FUNC(void)
500{
501	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
502		cvmx_warn("CVMX_SLI_MSI_WR_MAP not supported on this chip\n");
503	return 0x0000000000003C90ull;
504}
505#else
506#define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull)
507#endif
508#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
509#define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC()
510static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void)
511{
512	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
513		cvmx_warn("CVMX_SLI_PCIE_MSI_RCV not supported on this chip\n");
514	return 0x0000000000003CB0ull;
515}
516#else
517#define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull)
518#endif
519#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
520#define CVMX_SLI_PCIE_MSI_RCV_B1 CVMX_SLI_PCIE_MSI_RCV_B1_FUNC()
521static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B1_FUNC(void)
522{
523	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
524		cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B1 not supported on this chip\n");
525	return 0x0000000000000650ull;
526}
527#else
528#define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
529#endif
530#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
531#define CVMX_SLI_PCIE_MSI_RCV_B2 CVMX_SLI_PCIE_MSI_RCV_B2_FUNC()
532static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B2_FUNC(void)
533{
534	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
535		cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B2 not supported on this chip\n");
536	return 0x0000000000000660ull;
537}
538#else
539#define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
540#endif
541#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
542#define CVMX_SLI_PCIE_MSI_RCV_B3 CVMX_SLI_PCIE_MSI_RCV_B3_FUNC()
543static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_B3_FUNC(void)
544{
545	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
546		cvmx_warn("CVMX_SLI_PCIE_MSI_RCV_B3 not supported on this chip\n");
547	return 0x0000000000000670ull;
548}
549#else
550#define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
551#endif
552#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
553static inline uint64_t CVMX_SLI_PKTX_CNTS(unsigned long offset)
554{
555	if (!(
556	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
557	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
558	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
559	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
560	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
561		cvmx_warn("CVMX_SLI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
562	return 0x0000000000002400ull + ((offset) & 31) * 16;
563}
564#else
565#define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
566#endif
567#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
568static inline uint64_t CVMX_SLI_PKTX_INSTR_BADDR(unsigned long offset)
569{
570	if (!(
571	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
572	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
573	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
574	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
575	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
576		cvmx_warn("CVMX_SLI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
577	return 0x0000000000002800ull + ((offset) & 31) * 16;
578}
579#else
580#define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
581#endif
582#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
583static inline uint64_t CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
584{
585	if (!(
586	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
587	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
588	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
589	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
590	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
591		cvmx_warn("CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
592	return 0x0000000000002C00ull + ((offset) & 31) * 16;
593}
594#else
595#define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
596#endif
597#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
598static inline uint64_t CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
599{
600	if (!(
601	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
602	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
603	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
604	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
605	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
606		cvmx_warn("CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
607	return 0x0000000000003000ull + ((offset) & 31) * 16;
608}
609#else
610#define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
611#endif
612#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
613static inline uint64_t CVMX_SLI_PKTX_INSTR_HEADER(unsigned long offset)
614{
615	if (!(
616	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
617	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
618	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
619	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
620	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
621		cvmx_warn("CVMX_SLI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
622	return 0x0000000000003400ull + ((offset) & 31) * 16;
623}
624#else
625#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
626#endif
627#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
628static inline uint64_t CVMX_SLI_PKTX_IN_BP(unsigned long offset)
629{
630	if (!(
631	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
632	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
633	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
634	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
635		cvmx_warn("CVMX_SLI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
636	return 0x0000000000003800ull + ((offset) & 31) * 16;
637}
638#else
639#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
640#endif
641#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
642static inline uint64_t CVMX_SLI_PKTX_OUT_SIZE(unsigned long offset)
643{
644	if (!(
645	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
646	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
647	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
648	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
649	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
650		cvmx_warn("CVMX_SLI_PKTX_OUT_SIZE(%lu) is invalid on this chip\n", offset);
651	return 0x0000000000000C00ull + ((offset) & 31) * 16;
652}
653#else
654#define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16)
655#endif
656#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
657static inline uint64_t CVMX_SLI_PKTX_SLIST_BADDR(unsigned long offset)
658{
659	if (!(
660	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
661	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
662	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
663	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
664	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
665		cvmx_warn("CVMX_SLI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
666	return 0x0000000000001400ull + ((offset) & 31) * 16;
667}
668#else
669#define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
670#endif
671#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
672static inline uint64_t CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
673{
674	if (!(
675	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
676	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
677	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
678	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
679	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
680		cvmx_warn("CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
681	return 0x0000000000001800ull + ((offset) & 31) * 16;
682}
683#else
684#define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
685#endif
686#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
687static inline uint64_t CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
688{
689	if (!(
690	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
691	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
692	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
693	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
694	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
695		cvmx_warn("CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
696	return 0x0000000000001C00ull + ((offset) & 31) * 16;
697}
698#else
699#define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
700#endif
701#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
702#define CVMX_SLI_PKT_CNT_INT CVMX_SLI_PKT_CNT_INT_FUNC()
703static inline uint64_t CVMX_SLI_PKT_CNT_INT_FUNC(void)
704{
705	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
706		cvmx_warn("CVMX_SLI_PKT_CNT_INT not supported on this chip\n");
707	return 0x0000000000001130ull;
708}
709#else
710#define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull)
711#endif
712#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
713#define CVMX_SLI_PKT_CNT_INT_ENB CVMX_SLI_PKT_CNT_INT_ENB_FUNC()
714static inline uint64_t CVMX_SLI_PKT_CNT_INT_ENB_FUNC(void)
715{
716	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
717		cvmx_warn("CVMX_SLI_PKT_CNT_INT_ENB not supported on this chip\n");
718	return 0x0000000000001150ull;
719}
720#else
721#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull)
722#endif
723#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
724#define CVMX_SLI_PKT_CTL CVMX_SLI_PKT_CTL_FUNC()
725static inline uint64_t CVMX_SLI_PKT_CTL_FUNC(void)
726{
727	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
728		cvmx_warn("CVMX_SLI_PKT_CTL not supported on this chip\n");
729	return 0x0000000000001220ull;
730}
731#else
732#define CVMX_SLI_PKT_CTL (0x0000000000001220ull)
733#endif
734#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
735#define CVMX_SLI_PKT_DATA_OUT_ES CVMX_SLI_PKT_DATA_OUT_ES_FUNC()
736static inline uint64_t CVMX_SLI_PKT_DATA_OUT_ES_FUNC(void)
737{
738	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
739		cvmx_warn("CVMX_SLI_PKT_DATA_OUT_ES not supported on this chip\n");
740	return 0x00000000000010B0ull;
741}
742#else
743#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
744#endif
745#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
746#define CVMX_SLI_PKT_DATA_OUT_NS CVMX_SLI_PKT_DATA_OUT_NS_FUNC()
747static inline uint64_t CVMX_SLI_PKT_DATA_OUT_NS_FUNC(void)
748{
749	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
750		cvmx_warn("CVMX_SLI_PKT_DATA_OUT_NS not supported on this chip\n");
751	return 0x00000000000010A0ull;
752}
753#else
754#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
755#endif
756#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
757#define CVMX_SLI_PKT_DATA_OUT_ROR CVMX_SLI_PKT_DATA_OUT_ROR_FUNC()
758static inline uint64_t CVMX_SLI_PKT_DATA_OUT_ROR_FUNC(void)
759{
760	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
761		cvmx_warn("CVMX_SLI_PKT_DATA_OUT_ROR not supported on this chip\n");
762	return 0x0000000000001090ull;
763}
764#else
765#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
766#endif
767#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
768#define CVMX_SLI_PKT_DPADDR CVMX_SLI_PKT_DPADDR_FUNC()
769static inline uint64_t CVMX_SLI_PKT_DPADDR_FUNC(void)
770{
771	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
772		cvmx_warn("CVMX_SLI_PKT_DPADDR not supported on this chip\n");
773	return 0x0000000000001080ull;
774}
775#else
776#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull)
777#endif
778#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
779#define CVMX_SLI_PKT_INPUT_CONTROL CVMX_SLI_PKT_INPUT_CONTROL_FUNC()
780static inline uint64_t CVMX_SLI_PKT_INPUT_CONTROL_FUNC(void)
781{
782	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
783		cvmx_warn("CVMX_SLI_PKT_INPUT_CONTROL not supported on this chip\n");
784	return 0x0000000000001170ull;
785}
786#else
787#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull)
788#endif
789#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
790#define CVMX_SLI_PKT_INSTR_ENB CVMX_SLI_PKT_INSTR_ENB_FUNC()
791static inline uint64_t CVMX_SLI_PKT_INSTR_ENB_FUNC(void)
792{
793	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
794		cvmx_warn("CVMX_SLI_PKT_INSTR_ENB not supported on this chip\n");
795	return 0x0000000000001000ull;
796}
797#else
798#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull)
799#endif
800#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
801#define CVMX_SLI_PKT_INSTR_RD_SIZE CVMX_SLI_PKT_INSTR_RD_SIZE_FUNC()
802static inline uint64_t CVMX_SLI_PKT_INSTR_RD_SIZE_FUNC(void)
803{
804	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
805		cvmx_warn("CVMX_SLI_PKT_INSTR_RD_SIZE not supported on this chip\n");
806	return 0x00000000000011A0ull;
807}
808#else
809#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull)
810#endif
811#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
812#define CVMX_SLI_PKT_INSTR_SIZE CVMX_SLI_PKT_INSTR_SIZE_FUNC()
813static inline uint64_t CVMX_SLI_PKT_INSTR_SIZE_FUNC(void)
814{
815	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
816		cvmx_warn("CVMX_SLI_PKT_INSTR_SIZE not supported on this chip\n");
817	return 0x0000000000001020ull;
818}
819#else
820#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull)
821#endif
822#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
823#define CVMX_SLI_PKT_INT_LEVELS CVMX_SLI_PKT_INT_LEVELS_FUNC()
824static inline uint64_t CVMX_SLI_PKT_INT_LEVELS_FUNC(void)
825{
826	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
827		cvmx_warn("CVMX_SLI_PKT_INT_LEVELS not supported on this chip\n");
828	return 0x0000000000001120ull;
829}
830#else
831#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull)
832#endif
833#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
834#define CVMX_SLI_PKT_IN_BP CVMX_SLI_PKT_IN_BP_FUNC()
835static inline uint64_t CVMX_SLI_PKT_IN_BP_FUNC(void)
836{
837	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
838		cvmx_warn("CVMX_SLI_PKT_IN_BP not supported on this chip\n");
839	return 0x0000000000001210ull;
840}
841#else
842#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull)
843#endif
844#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
845static inline uint64_t CVMX_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)
846{
847	if (!(
848	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
849	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
850	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
851	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
852	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
853		cvmx_warn("CVMX_SLI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
854	return 0x0000000000002000ull + ((offset) & 31) * 16;
855}
856#else
857#define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
858#endif
859#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
860#define CVMX_SLI_PKT_IN_INSTR_COUNTS CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC()
861static inline uint64_t CVMX_SLI_PKT_IN_INSTR_COUNTS_FUNC(void)
862{
863	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
864		cvmx_warn("CVMX_SLI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
865	return 0x0000000000001200ull;
866}
867#else
868#define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull)
869#endif
870#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
871#define CVMX_SLI_PKT_IN_PCIE_PORT CVMX_SLI_PKT_IN_PCIE_PORT_FUNC()
872static inline uint64_t CVMX_SLI_PKT_IN_PCIE_PORT_FUNC(void)
873{
874	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
875		cvmx_warn("CVMX_SLI_PKT_IN_PCIE_PORT not supported on this chip\n");
876	return 0x00000000000011B0ull;
877}
878#else
879#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull)
880#endif
881#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
882#define CVMX_SLI_PKT_IPTR CVMX_SLI_PKT_IPTR_FUNC()
883static inline uint64_t CVMX_SLI_PKT_IPTR_FUNC(void)
884{
885	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
886		cvmx_warn("CVMX_SLI_PKT_IPTR not supported on this chip\n");
887	return 0x0000000000001070ull;
888}
889#else
890#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull)
891#endif
892#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
893#define CVMX_SLI_PKT_OUTPUT_WMARK CVMX_SLI_PKT_OUTPUT_WMARK_FUNC()
894static inline uint64_t CVMX_SLI_PKT_OUTPUT_WMARK_FUNC(void)
895{
896	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
897		cvmx_warn("CVMX_SLI_PKT_OUTPUT_WMARK not supported on this chip\n");
898	return 0x0000000000001180ull;
899}
900#else
901#define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull)
902#endif
903#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
904#define CVMX_SLI_PKT_OUT_BMODE CVMX_SLI_PKT_OUT_BMODE_FUNC()
905static inline uint64_t CVMX_SLI_PKT_OUT_BMODE_FUNC(void)
906{
907	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
908		cvmx_warn("CVMX_SLI_PKT_OUT_BMODE not supported on this chip\n");
909	return 0x00000000000010D0ull;
910}
911#else
912#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull)
913#endif
914#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
915#define CVMX_SLI_PKT_OUT_BP_EN CVMX_SLI_PKT_OUT_BP_EN_FUNC()
916static inline uint64_t CVMX_SLI_PKT_OUT_BP_EN_FUNC(void)
917{
918	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
919		cvmx_warn("CVMX_SLI_PKT_OUT_BP_EN not supported on this chip\n");
920	return 0x0000000000001240ull;
921}
922#else
923#define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull)
924#endif
925#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
926#define CVMX_SLI_PKT_OUT_ENB CVMX_SLI_PKT_OUT_ENB_FUNC()
927static inline uint64_t CVMX_SLI_PKT_OUT_ENB_FUNC(void)
928{
929	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
930		cvmx_warn("CVMX_SLI_PKT_OUT_ENB not supported on this chip\n");
931	return 0x0000000000001010ull;
932}
933#else
934#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull)
935#endif
936#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
937#define CVMX_SLI_PKT_PCIE_PORT CVMX_SLI_PKT_PCIE_PORT_FUNC()
938static inline uint64_t CVMX_SLI_PKT_PCIE_PORT_FUNC(void)
939{
940	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
941		cvmx_warn("CVMX_SLI_PKT_PCIE_PORT not supported on this chip\n");
942	return 0x00000000000010E0ull;
943}
944#else
945#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull)
946#endif
947#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
948#define CVMX_SLI_PKT_PORT_IN_RST CVMX_SLI_PKT_PORT_IN_RST_FUNC()
949static inline uint64_t CVMX_SLI_PKT_PORT_IN_RST_FUNC(void)
950{
951	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
952		cvmx_warn("CVMX_SLI_PKT_PORT_IN_RST not supported on this chip\n");
953	return 0x00000000000011F0ull;
954}
955#else
956#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull)
957#endif
958#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
959#define CVMX_SLI_PKT_SLIST_ES CVMX_SLI_PKT_SLIST_ES_FUNC()
960static inline uint64_t CVMX_SLI_PKT_SLIST_ES_FUNC(void)
961{
962	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
963		cvmx_warn("CVMX_SLI_PKT_SLIST_ES not supported on this chip\n");
964	return 0x0000000000001050ull;
965}
966#else
967#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull)
968#endif
969#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
970#define CVMX_SLI_PKT_SLIST_NS CVMX_SLI_PKT_SLIST_NS_FUNC()
971static inline uint64_t CVMX_SLI_PKT_SLIST_NS_FUNC(void)
972{
973	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
974		cvmx_warn("CVMX_SLI_PKT_SLIST_NS not supported on this chip\n");
975	return 0x0000000000001040ull;
976}
977#else
978#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull)
979#endif
980#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
981#define CVMX_SLI_PKT_SLIST_ROR CVMX_SLI_PKT_SLIST_ROR_FUNC()
982static inline uint64_t CVMX_SLI_PKT_SLIST_ROR_FUNC(void)
983{
984	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
985		cvmx_warn("CVMX_SLI_PKT_SLIST_ROR not supported on this chip\n");
986	return 0x0000000000001030ull;
987}
988#else
989#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull)
990#endif
991#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
992#define CVMX_SLI_PKT_TIME_INT CVMX_SLI_PKT_TIME_INT_FUNC()
993static inline uint64_t CVMX_SLI_PKT_TIME_INT_FUNC(void)
994{
995	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
996		cvmx_warn("CVMX_SLI_PKT_TIME_INT not supported on this chip\n");
997	return 0x0000000000001140ull;
998}
999#else
1000#define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull)
1001#endif
1002#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1003#define CVMX_SLI_PKT_TIME_INT_ENB CVMX_SLI_PKT_TIME_INT_ENB_FUNC()
1004static inline uint64_t CVMX_SLI_PKT_TIME_INT_ENB_FUNC(void)
1005{
1006	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1007		cvmx_warn("CVMX_SLI_PKT_TIME_INT_ENB not supported on this chip\n");
1008	return 0x0000000000001160ull;
1009}
1010#else
1011#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull)
1012#endif
1013#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1014static inline uint64_t CVMX_SLI_PORTX_PKIND(unsigned long offset)
1015{
1016	if (!(
1017	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31)))))
1018		cvmx_warn("CVMX_SLI_PORTX_PKIND(%lu) is invalid on this chip\n", offset);
1019	return 0x0000000000000800ull + ((offset) & 31) * 16;
1020}
1021#else
1022#define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16)
1023#endif
1024#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1025static inline uint64_t CVMX_SLI_S2M_PORTX_CTL(unsigned long offset)
1026{
1027	if (!(
1028	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1029	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1030	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
1031	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1032	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1033		cvmx_warn("CVMX_SLI_S2M_PORTX_CTL(%lu) is invalid on this chip\n", offset);
1034	return 0x0000000000003D80ull + ((offset) & 3) * 16;
1035}
1036#else
1037#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16)
1038#endif
1039#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1040#define CVMX_SLI_SCRATCH_1 CVMX_SLI_SCRATCH_1_FUNC()
1041static inline uint64_t CVMX_SLI_SCRATCH_1_FUNC(void)
1042{
1043	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1044		cvmx_warn("CVMX_SLI_SCRATCH_1 not supported on this chip\n");
1045	return 0x00000000000003C0ull;
1046}
1047#else
1048#define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull)
1049#endif
1050#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1051#define CVMX_SLI_SCRATCH_2 CVMX_SLI_SCRATCH_2_FUNC()
1052static inline uint64_t CVMX_SLI_SCRATCH_2_FUNC(void)
1053{
1054	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1055		cvmx_warn("CVMX_SLI_SCRATCH_2 not supported on this chip\n");
1056	return 0x00000000000003D0ull;
1057}
1058#else
1059#define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull)
1060#endif
1061#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1062#define CVMX_SLI_STATE1 CVMX_SLI_STATE1_FUNC()
1063static inline uint64_t CVMX_SLI_STATE1_FUNC(void)
1064{
1065	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1066		cvmx_warn("CVMX_SLI_STATE1 not supported on this chip\n");
1067	return 0x0000000000000620ull;
1068}
1069#else
1070#define CVMX_SLI_STATE1 (0x0000000000000620ull)
1071#endif
1072#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1073#define CVMX_SLI_STATE2 CVMX_SLI_STATE2_FUNC()
1074static inline uint64_t CVMX_SLI_STATE2_FUNC(void)
1075{
1076	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1077		cvmx_warn("CVMX_SLI_STATE2 not supported on this chip\n");
1078	return 0x0000000000000630ull;
1079}
1080#else
1081#define CVMX_SLI_STATE2 (0x0000000000000630ull)
1082#endif
1083#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1084#define CVMX_SLI_STATE3 CVMX_SLI_STATE3_FUNC()
1085static inline uint64_t CVMX_SLI_STATE3_FUNC(void)
1086{
1087	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1088		cvmx_warn("CVMX_SLI_STATE3 not supported on this chip\n");
1089	return 0x0000000000000640ull;
1090}
1091#else
1092#define CVMX_SLI_STATE3 (0x0000000000000640ull)
1093#endif
1094#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1095#define CVMX_SLI_TX_PIPE CVMX_SLI_TX_PIPE_FUNC()
1096static inline uint64_t CVMX_SLI_TX_PIPE_FUNC(void)
1097{
1098	if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
1099		cvmx_warn("CVMX_SLI_TX_PIPE not supported on this chip\n");
1100	return 0x0000000000001230ull;
1101}
1102#else
1103#define CVMX_SLI_TX_PIPE (0x0000000000001230ull)
1104#endif
1105#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1106#define CVMX_SLI_WINDOW_CTL CVMX_SLI_WINDOW_CTL_FUNC()
1107static inline uint64_t CVMX_SLI_WINDOW_CTL_FUNC(void)
1108{
1109	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1110		cvmx_warn("CVMX_SLI_WINDOW_CTL not supported on this chip\n");
1111	return 0x00000000000002E0ull;
1112}
1113#else
1114#define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull)
1115#endif
1116#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1117#define CVMX_SLI_WIN_RD_ADDR CVMX_SLI_WIN_RD_ADDR_FUNC()
1118static inline uint64_t CVMX_SLI_WIN_RD_ADDR_FUNC(void)
1119{
1120	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1121		cvmx_warn("CVMX_SLI_WIN_RD_ADDR not supported on this chip\n");
1122	return 0x0000000000000010ull;
1123}
1124#else
1125#define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull)
1126#endif
1127#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1128#define CVMX_SLI_WIN_RD_DATA CVMX_SLI_WIN_RD_DATA_FUNC()
1129static inline uint64_t CVMX_SLI_WIN_RD_DATA_FUNC(void)
1130{
1131	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1132		cvmx_warn("CVMX_SLI_WIN_RD_DATA not supported on this chip\n");
1133	return 0x0000000000000040ull;
1134}
1135#else
1136#define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull)
1137#endif
1138#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1139#define CVMX_SLI_WIN_WR_ADDR CVMX_SLI_WIN_WR_ADDR_FUNC()
1140static inline uint64_t CVMX_SLI_WIN_WR_ADDR_FUNC(void)
1141{
1142	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1143		cvmx_warn("CVMX_SLI_WIN_WR_ADDR not supported on this chip\n");
1144	return 0x0000000000000000ull;
1145}
1146#else
1147#define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull)
1148#endif
1149#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1150#define CVMX_SLI_WIN_WR_DATA CVMX_SLI_WIN_WR_DATA_FUNC()
1151static inline uint64_t CVMX_SLI_WIN_WR_DATA_FUNC(void)
1152{
1153	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1154		cvmx_warn("CVMX_SLI_WIN_WR_DATA not supported on this chip\n");
1155	return 0x0000000000000020ull;
1156}
1157#else
1158#define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull)
1159#endif
1160#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1161#define CVMX_SLI_WIN_WR_MASK CVMX_SLI_WIN_WR_MASK_FUNC()
1162static inline uint64_t CVMX_SLI_WIN_WR_MASK_FUNC(void)
1163{
1164	if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1165		cvmx_warn("CVMX_SLI_WIN_WR_MASK not supported on this chip\n");
1166	return 0x0000000000000030ull;
1167}
1168#else
1169#define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull)
1170#endif
1171
1172/**
1173 * cvmx_sli_bist_status
1174 *
1175 * SLI_BIST_STATUS = SLI's BIST Status Register
1176 *
1177 * Results from BIST runs of SLI's memories.
1178 */
1179union cvmx_sli_bist_status {
1180	uint64_t u64;
1181	struct cvmx_sli_bist_status_s {
1182#ifdef __BIG_ENDIAN_BITFIELD
1183	uint64_t reserved_32_63               : 32;
1184	uint64_t ncb_req                      : 1;  /**< BIST Status for NCB Request FIFO */
1185	uint64_t n2p0_c                       : 1;  /**< BIST Status for N2P Port0 Cmd */
1186	uint64_t n2p0_o                       : 1;  /**< BIST Status for N2P Port0 Data */
1187	uint64_t n2p1_c                       : 1;  /**< BIST Status for N2P Port1 Cmd */
1188	uint64_t n2p1_o                       : 1;  /**< BIST Status for N2P Port1 Data */
1189	uint64_t cpl_p0                       : 1;  /**< BIST Status for CPL Port 0 */
1190	uint64_t cpl_p1                       : 1;  /**< BIST Status for CPL Port 1 */
1191	uint64_t reserved_19_24               : 6;
1192	uint64_t p2n0_c0                      : 1;  /**< BIST Status for P2N Port0 C0 */
1193	uint64_t p2n0_c1                      : 1;  /**< BIST Status for P2N Port0 C1 */
1194	uint64_t p2n0_n                       : 1;  /**< BIST Status for P2N Port0 N */
1195	uint64_t p2n0_p0                      : 1;  /**< BIST Status for P2N Port0 P0 */
1196	uint64_t p2n0_p1                      : 1;  /**< BIST Status for P2N Port0 P1 */
1197	uint64_t p2n1_c0                      : 1;  /**< BIST Status for P2N Port1 C0 */
1198	uint64_t p2n1_c1                      : 1;  /**< BIST Status for P2N Port1 C1 */
1199	uint64_t p2n1_n                       : 1;  /**< BIST Status for P2N Port1 N */
1200	uint64_t p2n1_p0                      : 1;  /**< BIST Status for P2N Port1 P0 */
1201	uint64_t p2n1_p1                      : 1;  /**< BIST Status for P2N Port1 P1 */
1202	uint64_t reserved_6_8                 : 3;
1203	uint64_t dsi1_1                       : 1;  /**< BIST Status for DSI1 Memory 1 */
1204	uint64_t dsi1_0                       : 1;  /**< BIST Status for DSI1 Memory 0 */
1205	uint64_t dsi0_1                       : 1;  /**< BIST Status for DSI0 Memory 1 */
1206	uint64_t dsi0_0                       : 1;  /**< BIST Status for DSI0 Memory 0 */
1207	uint64_t msi                          : 1;  /**< BIST Status for MSI Memory Map */
1208	uint64_t ncb_cmd                      : 1;  /**< BIST Status for NCB Outbound Commands */
1209#else
1210	uint64_t ncb_cmd                      : 1;
1211	uint64_t msi                          : 1;
1212	uint64_t dsi0_0                       : 1;
1213	uint64_t dsi0_1                       : 1;
1214	uint64_t dsi1_0                       : 1;
1215	uint64_t dsi1_1                       : 1;
1216	uint64_t reserved_6_8                 : 3;
1217	uint64_t p2n1_p1                      : 1;
1218	uint64_t p2n1_p0                      : 1;
1219	uint64_t p2n1_n                       : 1;
1220	uint64_t p2n1_c1                      : 1;
1221	uint64_t p2n1_c0                      : 1;
1222	uint64_t p2n0_p1                      : 1;
1223	uint64_t p2n0_p0                      : 1;
1224	uint64_t p2n0_n                       : 1;
1225	uint64_t p2n0_c1                      : 1;
1226	uint64_t p2n0_c0                      : 1;
1227	uint64_t reserved_19_24               : 6;
1228	uint64_t cpl_p1                       : 1;
1229	uint64_t cpl_p0                       : 1;
1230	uint64_t n2p1_o                       : 1;
1231	uint64_t n2p1_c                       : 1;
1232	uint64_t n2p0_o                       : 1;
1233	uint64_t n2p0_c                       : 1;
1234	uint64_t ncb_req                      : 1;
1235	uint64_t reserved_32_63               : 32;
1236#endif
1237	} s;
1238	struct cvmx_sli_bist_status_cn61xx {
1239#ifdef __BIG_ENDIAN_BITFIELD
1240	uint64_t reserved_31_63               : 33;
1241	uint64_t n2p0_c                       : 1;  /**< BIST Status for N2P Port0 Cmd */
1242	uint64_t n2p0_o                       : 1;  /**< BIST Status for N2P Port0 Data */
1243	uint64_t reserved_27_28               : 2;
1244	uint64_t cpl_p0                       : 1;  /**< BIST Status for CPL Port 0 */
1245	uint64_t cpl_p1                       : 1;  /**< BIST Status for CPL Port 1 */
1246	uint64_t reserved_19_24               : 6;
1247	uint64_t p2n0_c0                      : 1;  /**< BIST Status for P2N Port0 C0 */
1248	uint64_t p2n0_c1                      : 1;  /**< BIST Status for P2N Port0 C1 */
1249	uint64_t p2n0_n                       : 1;  /**< BIST Status for P2N Port0 N */
1250	uint64_t p2n0_p0                      : 1;  /**< BIST Status for P2N Port0 P0 */
1251	uint64_t p2n0_p1                      : 1;  /**< BIST Status for P2N Port0 P1 */
1252	uint64_t p2n1_c0                      : 1;  /**< BIST Status for P2N Port1 C0 */
1253	uint64_t p2n1_c1                      : 1;  /**< BIST Status for P2N Port1 C1 */
1254	uint64_t p2n1_n                       : 1;  /**< BIST Status for P2N Port1 N */
1255	uint64_t p2n1_p0                      : 1;  /**< BIST Status for P2N Port1 P0 */
1256	uint64_t p2n1_p1                      : 1;  /**< BIST Status for P2N Port1 P1 */
1257	uint64_t reserved_6_8                 : 3;
1258	uint64_t dsi1_1                       : 1;  /**< BIST Status for DSI1 Memory 1 */
1259	uint64_t dsi1_0                       : 1;  /**< BIST Status for DSI1 Memory 0 */
1260	uint64_t dsi0_1                       : 1;  /**< BIST Status for DSI0 Memory 1 */
1261	uint64_t dsi0_0                       : 1;  /**< BIST Status for DSI0 Memory 0 */
1262	uint64_t msi                          : 1;  /**< BIST Status for MSI Memory Map */
1263	uint64_t ncb_cmd                      : 1;  /**< BIST Status for NCB Outbound Commands */
1264#else
1265	uint64_t ncb_cmd                      : 1;
1266	uint64_t msi                          : 1;
1267	uint64_t dsi0_0                       : 1;
1268	uint64_t dsi0_1                       : 1;
1269	uint64_t dsi1_0                       : 1;
1270	uint64_t dsi1_1                       : 1;
1271	uint64_t reserved_6_8                 : 3;
1272	uint64_t p2n1_p1                      : 1;
1273	uint64_t p2n1_p0                      : 1;
1274	uint64_t p2n1_n                       : 1;
1275	uint64_t p2n1_c1                      : 1;
1276	uint64_t p2n1_c0                      : 1;
1277	uint64_t p2n0_p1                      : 1;
1278	uint64_t p2n0_p0                      : 1;
1279	uint64_t p2n0_n                       : 1;
1280	uint64_t p2n0_c1                      : 1;
1281	uint64_t p2n0_c0                      : 1;
1282	uint64_t reserved_19_24               : 6;
1283	uint64_t cpl_p1                       : 1;
1284	uint64_t cpl_p0                       : 1;
1285	uint64_t reserved_27_28               : 2;
1286	uint64_t n2p0_o                       : 1;
1287	uint64_t n2p0_c                       : 1;
1288	uint64_t reserved_31_63               : 33;
1289#endif
1290	} cn61xx;
1291	struct cvmx_sli_bist_status_cn63xx {
1292#ifdef __BIG_ENDIAN_BITFIELD
1293	uint64_t reserved_31_63               : 33;
1294	uint64_t n2p0_c                       : 1;  /**< BIST Status for N2P Port0 Cmd */
1295	uint64_t n2p0_o                       : 1;  /**< BIST Status for N2P Port0 Data */
1296	uint64_t n2p1_c                       : 1;  /**< BIST Status for N2P Port1 Cmd */
1297	uint64_t n2p1_o                       : 1;  /**< BIST Status for N2P Port1 Data */
1298	uint64_t cpl_p0                       : 1;  /**< BIST Status for CPL Port 0 */
1299	uint64_t cpl_p1                       : 1;  /**< BIST Status for CPL Port 1 */
1300	uint64_t reserved_19_24               : 6;
1301	uint64_t p2n0_c0                      : 1;  /**< BIST Status for P2N Port0 C0 */
1302	uint64_t p2n0_c1                      : 1;  /**< BIST Status for P2N Port0 C1 */
1303	uint64_t p2n0_n                       : 1;  /**< BIST Status for P2N Port0 N */
1304	uint64_t p2n0_p0                      : 1;  /**< BIST Status for P2N Port0 P0 */
1305	uint64_t p2n0_p1                      : 1;  /**< BIST Status for P2N Port0 P1 */
1306	uint64_t p2n1_c0                      : 1;  /**< BIST Status for P2N Port1 C0 */
1307	uint64_t p2n1_c1                      : 1;  /**< BIST Status for P2N Port1 C1 */
1308	uint64_t p2n1_n                       : 1;  /**< BIST Status for P2N Port1 N */
1309	uint64_t p2n1_p0                      : 1;  /**< BIST Status for P2N Port1 P0 */
1310	uint64_t p2n1_p1                      : 1;  /**< BIST Status for P2N Port1 P1 */
1311	uint64_t reserved_6_8                 : 3;
1312	uint64_t dsi1_1                       : 1;  /**< BIST Status for DSI1 Memory 1 */
1313	uint64_t dsi1_0                       : 1;  /**< BIST Status for DSI1 Memory 0 */
1314	uint64_t dsi0_1                       : 1;  /**< BIST Status for DSI0 Memory 1 */
1315	uint64_t dsi0_0                       : 1;  /**< BIST Status for DSI0 Memory 0 */
1316	uint64_t msi                          : 1;  /**< BIST Status for MSI Memory Map */
1317	uint64_t ncb_cmd                      : 1;  /**< BIST Status for NCB Outbound Commands */
1318#else
1319	uint64_t ncb_cmd                      : 1;
1320	uint64_t msi                          : 1;
1321	uint64_t dsi0_0                       : 1;
1322	uint64_t dsi0_1                       : 1;
1323	uint64_t dsi1_0                       : 1;
1324	uint64_t dsi1_1                       : 1;
1325	uint64_t reserved_6_8                 : 3;
1326	uint64_t p2n1_p1                      : 1;
1327	uint64_t p2n1_p0                      : 1;
1328	uint64_t p2n1_n                       : 1;
1329	uint64_t p2n1_c1                      : 1;
1330	uint64_t p2n1_c0                      : 1;
1331	uint64_t p2n0_p1                      : 1;
1332	uint64_t p2n0_p0                      : 1;
1333	uint64_t p2n0_n                       : 1;
1334	uint64_t p2n0_c1                      : 1;
1335	uint64_t p2n0_c0                      : 1;
1336	uint64_t reserved_19_24               : 6;
1337	uint64_t cpl_p1                       : 1;
1338	uint64_t cpl_p0                       : 1;
1339	uint64_t n2p1_o                       : 1;
1340	uint64_t n2p1_c                       : 1;
1341	uint64_t n2p0_o                       : 1;
1342	uint64_t n2p0_c                       : 1;
1343	uint64_t reserved_31_63               : 33;
1344#endif
1345	} cn63xx;
1346	struct cvmx_sli_bist_status_cn63xx    cn63xxp1;
1347	struct cvmx_sli_bist_status_cn61xx    cn66xx;
1348	struct cvmx_sli_bist_status_s         cn68xx;
1349	struct cvmx_sli_bist_status_s         cn68xxp1;
1350	struct cvmx_sli_bist_status_cn61xx    cnf71xx;
1351};
1352typedef union cvmx_sli_bist_status cvmx_sli_bist_status_t;
1353
1354/**
1355 * cvmx_sli_ctl_port#
1356 *
1357 * SLI_CTL_PORTX = SLI's Control Port X
1358 *
1359 * Contains control for access for Port0
1360 */
1361union cvmx_sli_ctl_portx {
1362	uint64_t u64;
1363	struct cvmx_sli_ctl_portx_s {
1364#ifdef __BIG_ENDIAN_BITFIELD
1365	uint64_t reserved_22_63               : 42;
1366	uint64_t intd                         : 1;  /**< When '0' Intd wire asserted. Before mapping. */
1367	uint64_t intc                         : 1;  /**< When '0' Intc wire asserted. Before mapping. */
1368	uint64_t intb                         : 1;  /**< When '0' Intb wire asserted. Before mapping. */
1369	uint64_t inta                         : 1;  /**< When '0' Inta wire asserted. Before mapping. */
1370	uint64_t dis_port                     : 1;  /**< When set the output to the MAC is disabled. This
1371                                                         occurs when the MAC reset line transitions from
1372                                                         de-asserted to asserted. Writing a '1' to this
1373                                                         location will clear this condition when the MAC is
1374                                                         no longer in reset and the output to the MAC is at
1375                                                         the begining of a transfer. */
1376	uint64_t waitl_com                    : 1;  /**< When set '1' casues the SLI to wait for a commit
1377                                                         from the L2C before sending additional completions
1378                                                         to the L2C from a MAC.
1379                                                         Set this for more conservative behavior. Clear
1380                                                         this for more aggressive, higher-performance
1381                                                         behavior */
1382	uint64_t intd_map                     : 2;  /**< Maps INTD to INTA(00), INTB(01), INTC(10) or
1383                                                         INTD (11). */
1384	uint64_t intc_map                     : 2;  /**< Maps INTC to INTA(00), INTB(01), INTC(10) or
1385                                                         INTD (11). */
1386	uint64_t intb_map                     : 2;  /**< Maps INTB to INTA(00), INTB(01), INTC(10) or
1387                                                         INTD (11). */
1388	uint64_t inta_map                     : 2;  /**< Maps INTA to INTA(00), INTB(01), INTC(10) or
1389                                                         INTD (11). */
1390	uint64_t ctlp_ro                      : 1;  /**< Relaxed ordering enable for Completion TLPS. */
1391	uint64_t reserved_6_6                 : 1;
1392	uint64_t ptlp_ro                      : 1;  /**< Relaxed ordering enable for Posted TLPS. */
1393	uint64_t reserved_1_4                 : 4;
1394	uint64_t wait_com                     : 1;  /**< When set '1' casues the SLI to wait for a commit
1395                                                         from the L2C before sending additional stores to
1396                                                         the L2C from a MAC.
1397                                                         The SLI will request a commit on the last store
1398                                                         if more than one STORE operation is required on
1399                                                         the NCB.
1400                                                         Most applications will not notice a difference, so
1401                                                         should not set this bit. Setting the bit is more
1402                                                         conservative on ordering, lower performance */
1403#else
1404	uint64_t wait_com                     : 1;
1405	uint64_t reserved_1_4                 : 4;
1406	uint64_t ptlp_ro                      : 1;
1407	uint64_t reserved_6_6                 : 1;
1408	uint64_t ctlp_ro                      : 1;
1409	uint64_t inta_map                     : 2;
1410	uint64_t intb_map                     : 2;
1411	uint64_t intc_map                     : 2;
1412	uint64_t intd_map                     : 2;
1413	uint64_t waitl_com                    : 1;
1414	uint64_t dis_port                     : 1;
1415	uint64_t inta                         : 1;
1416	uint64_t intb                         : 1;
1417	uint64_t intc                         : 1;
1418	uint64_t intd                         : 1;
1419	uint64_t reserved_22_63               : 42;
1420#endif
1421	} s;
1422	struct cvmx_sli_ctl_portx_s           cn61xx;
1423	struct cvmx_sli_ctl_portx_s           cn63xx;
1424	struct cvmx_sli_ctl_portx_s           cn63xxp1;
1425	struct cvmx_sli_ctl_portx_s           cn66xx;
1426	struct cvmx_sli_ctl_portx_s           cn68xx;
1427	struct cvmx_sli_ctl_portx_s           cn68xxp1;
1428	struct cvmx_sli_ctl_portx_s           cnf71xx;
1429};
1430typedef union cvmx_sli_ctl_portx cvmx_sli_ctl_portx_t;
1431
1432/**
1433 * cvmx_sli_ctl_status
1434 *
1435 * SLI_CTL_STATUS = SLI Control Status Register
1436 *
1437 * Contains control and status for SLI. Writes to this register are not ordered with writes/reads to the MAC Memory space.
1438 * To ensure that a write has completed the user must read the register before making an access(i.e. MAC memory space)
1439 * that requires the value of this register to be updated.
1440 */
1441union cvmx_sli_ctl_status {
1442	uint64_t u64;
1443	struct cvmx_sli_ctl_status_s {
1444#ifdef __BIG_ENDIAN_BITFIELD
1445	uint64_t reserved_20_63               : 44;
1446	uint64_t p1_ntags                     : 6;  /**< Number of tags available for MAC Port1.
1447                                                         In RC mode 1 tag is needed for each outbound TLP
1448                                                         that requires a CPL TLP. In Endpoint mode the
1449                                                         number of tags required for a TLP request is
1450                                                         1 per 64-bytes of CPL data + 1.
1451                                                         This field should only be written as part of
1452                                                         reset sequence, before issuing any reads, CFGs, or
1453                                                         IO transactions from the core(s). */
1454	uint64_t p0_ntags                     : 6;  /**< Number of tags available for outbound TLPs to the
1455                                                         MACS. One tag is needed for each outbound TLP that
1456                                                         requires a CPL TLP.
1457                                                         This field should only be written as part of
1458                                                         reset sequence, before issuing any reads, CFGs, or
1459                                                         IO transactions from the core(s). */
1460	uint64_t chip_rev                     : 8;  /**< The chip revision. */
1461#else
1462	uint64_t chip_rev                     : 8;
1463	uint64_t p0_ntags                     : 6;
1464	uint64_t p1_ntags                     : 6;
1465	uint64_t reserved_20_63               : 44;
1466#endif
1467	} s;
1468	struct cvmx_sli_ctl_status_cn61xx {
1469#ifdef __BIG_ENDIAN_BITFIELD
1470	uint64_t reserved_14_63               : 50;
1471	uint64_t p0_ntags                     : 6;  /**< Number of tags available for outbound TLPs to the
1472                                                         MACS. One tag is needed for each outbound TLP that
1473                                                         requires a CPL TLP.
1474                                                         This field should only be written as part of
1475                                                         reset sequence, before issuing any reads, CFGs, or
1476                                                         IO transactions from the core(s). */
1477	uint64_t chip_rev                     : 8;  /**< The chip revision. */
1478#else
1479	uint64_t chip_rev                     : 8;
1480	uint64_t p0_ntags                     : 6;
1481	uint64_t reserved_14_63               : 50;
1482#endif
1483	} cn61xx;
1484	struct cvmx_sli_ctl_status_s          cn63xx;
1485	struct cvmx_sli_ctl_status_s          cn63xxp1;
1486	struct cvmx_sli_ctl_status_cn61xx     cn66xx;
1487	struct cvmx_sli_ctl_status_s          cn68xx;
1488	struct cvmx_sli_ctl_status_s          cn68xxp1;
1489	struct cvmx_sli_ctl_status_cn61xx     cnf71xx;
1490};
1491typedef union cvmx_sli_ctl_status cvmx_sli_ctl_status_t;
1492
1493/**
1494 * cvmx_sli_data_out_cnt
1495 *
1496 * SLI_DATA_OUT_CNT = SLI DATA OUT COUNT
1497 *
1498 * The EXEC data out fifo-count and the data unload counter.
1499 */
1500union cvmx_sli_data_out_cnt {
1501	uint64_t u64;
1502	struct cvmx_sli_data_out_cnt_s {
1503#ifdef __BIG_ENDIAN_BITFIELD
1504	uint64_t reserved_44_63               : 20;
1505	uint64_t p1_ucnt                      : 16; /**< SLI Order-FIFO1 Fifo Unload Count. This counter is
1506                                                         incremented by '1' every time a word is removed
1507                                                         from the Data Out FIFO, whose count is shown in
1508                                                         P1_FCNT. */
1509	uint64_t p1_fcnt                      : 6;  /**< SLI Order-FIFO1 Data Out Fifo Count. Number of
1510                                                         address data words to be sent out the Order-FIFO
1511                                                         presently buffered in the FIFO. */
1512	uint64_t p0_ucnt                      : 16; /**< SLI Order-FIFO0 Fifo Unload Count. This counter is
1513                                                         incremented by '1' every time a word is removed
1514                                                         from the Data Out FIFO, whose count is shown in
1515                                                         P0_FCNT. */
1516	uint64_t p0_fcnt                      : 6;  /**< SLI Order-FIFO0 Data Out Fifo Count. Number of
1517                                                         address data words to be sent out the Order-FIFO
1518                                                         presently buffered in the FIFO. */
1519#else
1520	uint64_t p0_fcnt                      : 6;
1521	uint64_t p0_ucnt                      : 16;
1522	uint64_t p1_fcnt                      : 6;
1523	uint64_t p1_ucnt                      : 16;
1524	uint64_t reserved_44_63               : 20;
1525#endif
1526	} s;
1527	struct cvmx_sli_data_out_cnt_s        cn61xx;
1528	struct cvmx_sli_data_out_cnt_s        cn63xx;
1529	struct cvmx_sli_data_out_cnt_s        cn63xxp1;
1530	struct cvmx_sli_data_out_cnt_s        cn66xx;
1531	struct cvmx_sli_data_out_cnt_s        cn68xx;
1532	struct cvmx_sli_data_out_cnt_s        cn68xxp1;
1533	struct cvmx_sli_data_out_cnt_s        cnf71xx;
1534};
1535typedef union cvmx_sli_data_out_cnt cvmx_sli_data_out_cnt_t;
1536
1537/**
1538 * cvmx_sli_dbg_data
1539 *
1540 * SLI_DBG_DATA = SLI Debug Data Register
1541 *
1542 * Value returned on the debug-data lines from the RSLs
1543 */
1544union cvmx_sli_dbg_data {
1545	uint64_t u64;
1546	struct cvmx_sli_dbg_data_s {
1547#ifdef __BIG_ENDIAN_BITFIELD
1548	uint64_t reserved_18_63               : 46;
1549	uint64_t dsel_ext                     : 1;  /**< Allows changes in the external pins to set the
1550                                                         debug select value. */
1551	uint64_t data                         : 17; /**< Value on the debug data lines. */
1552#else
1553	uint64_t data                         : 17;
1554	uint64_t dsel_ext                     : 1;
1555	uint64_t reserved_18_63               : 46;
1556#endif
1557	} s;
1558	struct cvmx_sli_dbg_data_s            cn61xx;
1559	struct cvmx_sli_dbg_data_s            cn63xx;
1560	struct cvmx_sli_dbg_data_s            cn63xxp1;
1561	struct cvmx_sli_dbg_data_s            cn66xx;
1562	struct cvmx_sli_dbg_data_s            cn68xx;
1563	struct cvmx_sli_dbg_data_s            cn68xxp1;
1564	struct cvmx_sli_dbg_data_s            cnf71xx;
1565};
1566typedef union cvmx_sli_dbg_data cvmx_sli_dbg_data_t;
1567
1568/**
1569 * cvmx_sli_dbg_select
1570 *
1571 * SLI_DBG_SELECT = Debug Select Register
1572 *
1573 * Contains the debug select value last written to the RSLs.
1574 */
1575union cvmx_sli_dbg_select {
1576	uint64_t u64;
1577	struct cvmx_sli_dbg_select_s {
1578#ifdef __BIG_ENDIAN_BITFIELD
1579	uint64_t reserved_33_63               : 31;
1580	uint64_t adbg_sel                     : 1;  /**< When set '1' the SLI_DBG_DATA[DATA] will only be
1581                                                         loaded when SLI_DBG_DATA[DATA] bit [16] is a '1'.
1582                                                         When the debug data comes from an Async-RSL bit
1583                                                         16 is used to tell that the data present is valid. */
1584	uint64_t dbg_sel                      : 32; /**< When this register is written the RML will write
1585                                                         all "F"s to the previous RTL to disable it from
1586                                                         sending Debug-Data. The RML will then send a write
1587                                                         to the new RSL with the supplied Debug-Select
1588                                                         value. Because it takes time for the new Debug
1589                                                         Select value to take effect and the requested
1590                                                         Debug-Data to return, time is needed to the new
1591                                                         Debug-Data to arrive.  The inititator of the Debug
1592                                                         Select should issue a read to a CSR before reading
1593                                                         the Debug Data (this read could also be to the
1594                                                         SLI_DBG_DATA but the returned value for the first
1595                                                         read will return NS data. */
1596#else
1597	uint64_t dbg_sel                      : 32;
1598	uint64_t adbg_sel                     : 1;
1599	uint64_t reserved_33_63               : 31;
1600#endif
1601	} s;
1602	struct cvmx_sli_dbg_select_s          cn61xx;
1603	struct cvmx_sli_dbg_select_s          cn63xx;
1604	struct cvmx_sli_dbg_select_s          cn63xxp1;
1605	struct cvmx_sli_dbg_select_s          cn66xx;
1606	struct cvmx_sli_dbg_select_s          cn68xx;
1607	struct cvmx_sli_dbg_select_s          cn68xxp1;
1608	struct cvmx_sli_dbg_select_s          cnf71xx;
1609};
1610typedef union cvmx_sli_dbg_select cvmx_sli_dbg_select_t;
1611
1612/**
1613 * cvmx_sli_dma#_cnt
1614 *
1615 * SLI_DMAx_CNT = SLI DMA Count
1616 *
1617 * The DMA Count value.
1618 */
1619union cvmx_sli_dmax_cnt {
1620	uint64_t u64;
1621	struct cvmx_sli_dmax_cnt_s {
1622#ifdef __BIG_ENDIAN_BITFIELD
1623	uint64_t reserved_32_63               : 32;
1624	uint64_t cnt                          : 32; /**< The DMA counter.
1625                                                         Writing this field will cause the written value
1626                                                         to be subtracted from DMA. HW will optionally
1627                                                         increment this field after it completes an
1628                                                         OUTBOUND or EXTERNAL-ONLY DMA instruction. These
1629                                                         increments may cause interrupts. Refer to
1630                                                         SLI_DMAx_INT_LEVEL and SLI_INT_SUM[DCNT,DTIME]. */
1631#else
1632	uint64_t cnt                          : 32;
1633	uint64_t reserved_32_63               : 32;
1634#endif
1635	} s;
1636	struct cvmx_sli_dmax_cnt_s            cn61xx;
1637	struct cvmx_sli_dmax_cnt_s            cn63xx;
1638	struct cvmx_sli_dmax_cnt_s            cn63xxp1;
1639	struct cvmx_sli_dmax_cnt_s            cn66xx;
1640	struct cvmx_sli_dmax_cnt_s            cn68xx;
1641	struct cvmx_sli_dmax_cnt_s            cn68xxp1;
1642	struct cvmx_sli_dmax_cnt_s            cnf71xx;
1643};
1644typedef union cvmx_sli_dmax_cnt cvmx_sli_dmax_cnt_t;
1645
1646/**
1647 * cvmx_sli_dma#_int_level
1648 *
1649 * SLI_DMAx_INT_LEVEL = SLI DMAx Interrupt Level
1650 *
1651 * Thresholds for DMA count and timer interrupts.
1652 */
1653union cvmx_sli_dmax_int_level {
1654	uint64_t u64;
1655	struct cvmx_sli_dmax_int_level_s {
1656#ifdef __BIG_ENDIAN_BITFIELD
1657	uint64_t time                         : 32; /**< Whenever the SLI_DMAx_TIM[TIM] timer exceeds
1658                                                         this value, SLI_INT_SUM[DTIME<x>] is set.
1659                                                         The SLI_DMAx_TIM[TIM] timer increments every SLI
1660                                                         clock whenever SLI_DMAx_CNT[CNT]!=0, and is
1661                                                         cleared when SLI_INT_SUM[DTIME<x>] is written with
1662                                                         one. */
1663	uint64_t cnt                          : 32; /**< Whenever SLI_DMAx_CNT[CNT] exceeds this value,
1664                                                         SLI_INT_SUM[DCNT<x>] is set. */
1665#else
1666	uint64_t cnt                          : 32;
1667	uint64_t time                         : 32;
1668#endif
1669	} s;
1670	struct cvmx_sli_dmax_int_level_s      cn61xx;
1671	struct cvmx_sli_dmax_int_level_s      cn63xx;
1672	struct cvmx_sli_dmax_int_level_s      cn63xxp1;
1673	struct cvmx_sli_dmax_int_level_s      cn66xx;
1674	struct cvmx_sli_dmax_int_level_s      cn68xx;
1675	struct cvmx_sli_dmax_int_level_s      cn68xxp1;
1676	struct cvmx_sli_dmax_int_level_s      cnf71xx;
1677};
1678typedef union cvmx_sli_dmax_int_level cvmx_sli_dmax_int_level_t;
1679
1680/**
1681 * cvmx_sli_dma#_tim
1682 *
1683 * SLI_DMAx_TIM = SLI DMA Timer
1684 *
1685 * The DMA Timer value.
1686 */
1687union cvmx_sli_dmax_tim {
1688	uint64_t u64;
1689	struct cvmx_sli_dmax_tim_s {
1690#ifdef __BIG_ENDIAN_BITFIELD
1691	uint64_t reserved_32_63               : 32;
1692	uint64_t tim                          : 32; /**< The DMA timer value.
1693                                                         The timer will increment when SLI_DMAx_CNT[CNT]!=0
1694                                                         and will clear when SLI_DMAx_CNT[CNT]==0 */
1695#else
1696	uint64_t tim                          : 32;
1697	uint64_t reserved_32_63               : 32;
1698#endif
1699	} s;
1700	struct cvmx_sli_dmax_tim_s            cn61xx;
1701	struct cvmx_sli_dmax_tim_s            cn63xx;
1702	struct cvmx_sli_dmax_tim_s            cn63xxp1;
1703	struct cvmx_sli_dmax_tim_s            cn66xx;
1704	struct cvmx_sli_dmax_tim_s            cn68xx;
1705	struct cvmx_sli_dmax_tim_s            cn68xxp1;
1706	struct cvmx_sli_dmax_tim_s            cnf71xx;
1707};
1708typedef union cvmx_sli_dmax_tim cvmx_sli_dmax_tim_t;
1709
1710/**
1711 * cvmx_sli_int_enb_ciu
1712 *
1713 * SLI_INT_ENB_CIU = SLI's Interrupt Enable CIU Register
1714 *
1715 * Used to enable the various interrupting conditions of SLI
1716 */
1717union cvmx_sli_int_enb_ciu {
1718	uint64_t u64;
1719	struct cvmx_sli_int_enb_ciu_s {
1720#ifdef __BIG_ENDIAN_BITFIELD
1721	uint64_t reserved_62_63               : 2;
1722	uint64_t pipe_err                     : 1;  /**< Illegal packet csr address. */
1723	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
1724	uint64_t sprt3_err                    : 1;  /**< Error Response received on SLI port 3. */
1725	uint64_t sprt2_err                    : 1;  /**< Error Response received on SLI port 2. */
1726	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
1727	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
1728	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
1729	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
1730	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
1731	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
1732	uint64_t pin_bp                       : 1;  /**< Packet Input Count exceeded WMARK. */
1733	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
1734	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
1735	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
1736	uint64_t reserved_38_47               : 10;
1737	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
1738	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
1739	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
1740	uint64_t reserved_28_31               : 4;
1741	uint64_t m3_un_wi                     : 1;  /**< Reserved. */
1742	uint64_t m3_un_b0                     : 1;  /**< Reserved. */
1743	uint64_t m3_up_wi                     : 1;  /**< Reserved. */
1744	uint64_t m3_up_b0                     : 1;  /**< Reserved. */
1745	uint64_t m2_un_wi                     : 1;  /**< Reserved. */
1746	uint64_t m2_un_b0                     : 1;  /**< Reserved. */
1747	uint64_t m2_up_wi                     : 1;  /**< Reserved. */
1748	uint64_t m2_up_b0                     : 1;  /**< Reserved. */
1749	uint64_t reserved_18_19               : 2;
1750	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
1751                                                         interrupt on the RSL.
1752                                                         THIS SHOULD NEVER BE SET */
1753	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
1754                                                         interrupt on the RSL.
1755                                                         THIS SHOULD NEVER BE SET */
1756	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
1757                                                         interrupt on the RSL. */
1758	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
1759                                                         interrupt on the RSL. */
1760	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
1761                                                         interrupt on the RSL. */
1762	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
1763                                                         interrupt on the RSL. */
1764	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
1765                                                         interrupt on the RSL. */
1766	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
1767                                                         interrupt on the RSL. */
1768	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
1769                                                         interrupt on the RSL. */
1770	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
1771                                                         interrupt on the RSL. */
1772	uint64_t reserved_6_7                 : 2;
1773	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
1774                                                         interrupt on the RSL. */
1775	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
1776                                                         interrupt on the RSL. */
1777	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
1778                                                         interrupt on the RSL. */
1779	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
1780                                                         interrupt on the RSL. */
1781	uint64_t reserved_1_1                 : 1;
1782	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
1783                                                         interrupt on the RSL. */
1784#else
1785	uint64_t rml_to                       : 1;
1786	uint64_t reserved_1_1                 : 1;
1787	uint64_t bar0_to                      : 1;
1788	uint64_t iob2big                      : 1;
1789	uint64_t pcnt                         : 1;
1790	uint64_t ptime                        : 1;
1791	uint64_t reserved_6_7                 : 2;
1792	uint64_t m0_up_b0                     : 1;
1793	uint64_t m0_up_wi                     : 1;
1794	uint64_t m0_un_b0                     : 1;
1795	uint64_t m0_un_wi                     : 1;
1796	uint64_t m1_up_b0                     : 1;
1797	uint64_t m1_up_wi                     : 1;
1798	uint64_t m1_un_b0                     : 1;
1799	uint64_t m1_un_wi                     : 1;
1800	uint64_t mio_int0                     : 1;
1801	uint64_t mio_int1                     : 1;
1802	uint64_t reserved_18_19               : 2;
1803	uint64_t m2_up_b0                     : 1;
1804	uint64_t m2_up_wi                     : 1;
1805	uint64_t m2_un_b0                     : 1;
1806	uint64_t m2_un_wi                     : 1;
1807	uint64_t m3_up_b0                     : 1;
1808	uint64_t m3_up_wi                     : 1;
1809	uint64_t m3_un_b0                     : 1;
1810	uint64_t m3_un_wi                     : 1;
1811	uint64_t reserved_28_31               : 4;
1812	uint64_t dmafi                        : 2;
1813	uint64_t dcnt                         : 2;
1814	uint64_t dtime                        : 2;
1815	uint64_t reserved_38_47               : 10;
1816	uint64_t pidbof                       : 1;
1817	uint64_t psldbof                      : 1;
1818	uint64_t pout_err                     : 1;
1819	uint64_t pin_bp                       : 1;
1820	uint64_t pgl_err                      : 1;
1821	uint64_t pdi_err                      : 1;
1822	uint64_t pop_err                      : 1;
1823	uint64_t pins_err                     : 1;
1824	uint64_t sprt0_err                    : 1;
1825	uint64_t sprt1_err                    : 1;
1826	uint64_t sprt2_err                    : 1;
1827	uint64_t sprt3_err                    : 1;
1828	uint64_t ill_pad                      : 1;
1829	uint64_t pipe_err                     : 1;
1830	uint64_t reserved_62_63               : 2;
1831#endif
1832	} s;
1833	struct cvmx_sli_int_enb_ciu_cn61xx {
1834#ifdef __BIG_ENDIAN_BITFIELD
1835	uint64_t reserved_61_63               : 3;
1836	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
1837	uint64_t sprt3_err                    : 1;  /**< Error Response received on SLI port 3. */
1838	uint64_t sprt2_err                    : 1;  /**< Error Response received on SLI port 2. */
1839	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
1840	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
1841	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
1842	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
1843	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
1844	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
1845	uint64_t pin_bp                       : 1;  /**< Packet Input Count exceeded WMARK. */
1846	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
1847	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
1848	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
1849	uint64_t reserved_38_47               : 10;
1850	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
1851	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
1852	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
1853	uint64_t reserved_28_31               : 4;
1854	uint64_t m3_un_wi                     : 1;  /**< Reserved. */
1855	uint64_t m3_un_b0                     : 1;  /**< Reserved. */
1856	uint64_t m3_up_wi                     : 1;  /**< Reserved. */
1857	uint64_t m3_up_b0                     : 1;  /**< Reserved. */
1858	uint64_t m2_un_wi                     : 1;  /**< Reserved. */
1859	uint64_t m2_un_b0                     : 1;  /**< Reserved. */
1860	uint64_t m2_up_wi                     : 1;  /**< Reserved. */
1861	uint64_t m2_up_b0                     : 1;  /**< Reserved. */
1862	uint64_t reserved_18_19               : 2;
1863	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
1864                                                         interrupt on the RSL.
1865                                                         THIS SHOULD NEVER BE SET */
1866	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
1867                                                         interrupt on the RSL.
1868                                                         THIS SHOULD NEVER BE SET */
1869	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
1870                                                         interrupt on the RSL. */
1871	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
1872                                                         interrupt on the RSL. */
1873	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
1874                                                         interrupt on the RSL. */
1875	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
1876                                                         interrupt on the RSL. */
1877	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
1878                                                         interrupt on the RSL. */
1879	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
1880                                                         interrupt on the RSL. */
1881	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
1882                                                         interrupt on the RSL. */
1883	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
1884                                                         interrupt on the RSL. */
1885	uint64_t reserved_6_7                 : 2;
1886	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
1887                                                         interrupt on the RSL. */
1888	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
1889                                                         interrupt on the RSL. */
1890	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
1891                                                         interrupt on the RSL. */
1892	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
1893                                                         interrupt on the RSL. */
1894	uint64_t reserved_1_1                 : 1;
1895	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
1896                                                         interrupt on the RSL. */
1897#else
1898	uint64_t rml_to                       : 1;
1899	uint64_t reserved_1_1                 : 1;
1900	uint64_t bar0_to                      : 1;
1901	uint64_t iob2big                      : 1;
1902	uint64_t pcnt                         : 1;
1903	uint64_t ptime                        : 1;
1904	uint64_t reserved_6_7                 : 2;
1905	uint64_t m0_up_b0                     : 1;
1906	uint64_t m0_up_wi                     : 1;
1907	uint64_t m0_un_b0                     : 1;
1908	uint64_t m0_un_wi                     : 1;
1909	uint64_t m1_up_b0                     : 1;
1910	uint64_t m1_up_wi                     : 1;
1911	uint64_t m1_un_b0                     : 1;
1912	uint64_t m1_un_wi                     : 1;
1913	uint64_t mio_int0                     : 1;
1914	uint64_t mio_int1                     : 1;
1915	uint64_t reserved_18_19               : 2;
1916	uint64_t m2_up_b0                     : 1;
1917	uint64_t m2_up_wi                     : 1;
1918	uint64_t m2_un_b0                     : 1;
1919	uint64_t m2_un_wi                     : 1;
1920	uint64_t m3_up_b0                     : 1;
1921	uint64_t m3_up_wi                     : 1;
1922	uint64_t m3_un_b0                     : 1;
1923	uint64_t m3_un_wi                     : 1;
1924	uint64_t reserved_28_31               : 4;
1925	uint64_t dmafi                        : 2;
1926	uint64_t dcnt                         : 2;
1927	uint64_t dtime                        : 2;
1928	uint64_t reserved_38_47               : 10;
1929	uint64_t pidbof                       : 1;
1930	uint64_t psldbof                      : 1;
1931	uint64_t pout_err                     : 1;
1932	uint64_t pin_bp                       : 1;
1933	uint64_t pgl_err                      : 1;
1934	uint64_t pdi_err                      : 1;
1935	uint64_t pop_err                      : 1;
1936	uint64_t pins_err                     : 1;
1937	uint64_t sprt0_err                    : 1;
1938	uint64_t sprt1_err                    : 1;
1939	uint64_t sprt2_err                    : 1;
1940	uint64_t sprt3_err                    : 1;
1941	uint64_t ill_pad                      : 1;
1942	uint64_t reserved_61_63               : 3;
1943#endif
1944	} cn61xx;
1945	struct cvmx_sli_int_enb_ciu_cn63xx {
1946#ifdef __BIG_ENDIAN_BITFIELD
1947	uint64_t reserved_61_63               : 3;
1948	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
1949	uint64_t reserved_58_59               : 2;
1950	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
1951	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
1952	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
1953	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
1954	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
1955	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
1956	uint64_t pin_bp                       : 1;  /**< Packet Input Count exceeded WMARK. */
1957	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
1958	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
1959	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
1960	uint64_t reserved_38_47               : 10;
1961	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
1962	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
1963	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
1964	uint64_t reserved_18_31               : 14;
1965	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
1966                                                         interrupt on the RSL.
1967                                                         THIS SHOULD NEVER BE SET */
1968	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
1969                                                         interrupt on the RSL.
1970                                                         THIS SHOULD NEVER BE SET */
1971	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
1972                                                         interrupt on the RSL. */
1973	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
1974                                                         interrupt on the RSL. */
1975	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
1976                                                         interrupt on the RSL. */
1977	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
1978                                                         interrupt on the RSL. */
1979	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
1980                                                         interrupt on the RSL. */
1981	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
1982                                                         interrupt on the RSL. */
1983	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
1984                                                         interrupt on the RSL. */
1985	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
1986                                                         interrupt on the RSL. */
1987	uint64_t reserved_6_7                 : 2;
1988	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
1989                                                         interrupt on the RSL. */
1990	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
1991                                                         interrupt on the RSL. */
1992	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
1993                                                         interrupt on the RSL. */
1994	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
1995                                                         interrupt on the RSL. */
1996	uint64_t reserved_1_1                 : 1;
1997	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
1998                                                         interrupt on the RSL. */
1999#else
2000	uint64_t rml_to                       : 1;
2001	uint64_t reserved_1_1                 : 1;
2002	uint64_t bar0_to                      : 1;
2003	uint64_t iob2big                      : 1;
2004	uint64_t pcnt                         : 1;
2005	uint64_t ptime                        : 1;
2006	uint64_t reserved_6_7                 : 2;
2007	uint64_t m0_up_b0                     : 1;
2008	uint64_t m0_up_wi                     : 1;
2009	uint64_t m0_un_b0                     : 1;
2010	uint64_t m0_un_wi                     : 1;
2011	uint64_t m1_up_b0                     : 1;
2012	uint64_t m1_up_wi                     : 1;
2013	uint64_t m1_un_b0                     : 1;
2014	uint64_t m1_un_wi                     : 1;
2015	uint64_t mio_int0                     : 1;
2016	uint64_t mio_int1                     : 1;
2017	uint64_t reserved_18_31               : 14;
2018	uint64_t dmafi                        : 2;
2019	uint64_t dcnt                         : 2;
2020	uint64_t dtime                        : 2;
2021	uint64_t reserved_38_47               : 10;
2022	uint64_t pidbof                       : 1;
2023	uint64_t psldbof                      : 1;
2024	uint64_t pout_err                     : 1;
2025	uint64_t pin_bp                       : 1;
2026	uint64_t pgl_err                      : 1;
2027	uint64_t pdi_err                      : 1;
2028	uint64_t pop_err                      : 1;
2029	uint64_t pins_err                     : 1;
2030	uint64_t sprt0_err                    : 1;
2031	uint64_t sprt1_err                    : 1;
2032	uint64_t reserved_58_59               : 2;
2033	uint64_t ill_pad                      : 1;
2034	uint64_t reserved_61_63               : 3;
2035#endif
2036	} cn63xx;
2037	struct cvmx_sli_int_enb_ciu_cn63xx    cn63xxp1;
2038	struct cvmx_sli_int_enb_ciu_cn61xx    cn66xx;
2039	struct cvmx_sli_int_enb_ciu_cn68xx {
2040#ifdef __BIG_ENDIAN_BITFIELD
2041	uint64_t reserved_62_63               : 2;
2042	uint64_t pipe_err                     : 1;  /**< Illegal packet csr address. */
2043	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
2044	uint64_t reserved_58_59               : 2;
2045	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
2046	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
2047	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
2048	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
2049	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
2050	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
2051	uint64_t reserved_51_51               : 1;
2052	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
2053	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
2054	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
2055	uint64_t reserved_38_47               : 10;
2056	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
2057	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
2058	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
2059	uint64_t reserved_18_31               : 14;
2060	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
2061                                                         interrupt on the RSL.
2062                                                         THIS SHOULD NEVER BE SET */
2063	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
2064                                                         interrupt on the RSL.
2065                                                         THIS SHOULD NEVER BE SET */
2066	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
2067                                                         interrupt on the RSL. */
2068	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
2069                                                         interrupt on the RSL. */
2070	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
2071                                                         interrupt on the RSL. */
2072	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
2073                                                         interrupt on the RSL. */
2074	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
2075                                                         interrupt on the RSL. */
2076	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
2077                                                         interrupt on the RSL. */
2078	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
2079                                                         interrupt on the RSL. */
2080	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
2081                                                         interrupt on the RSL. */
2082	uint64_t reserved_6_7                 : 2;
2083	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
2084                                                         interrupt on the RSL. */
2085	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
2086                                                         interrupt on the RSL. */
2087	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
2088                                                         interrupt on the RSL. */
2089	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
2090                                                         interrupt on the RSL. */
2091	uint64_t reserved_1_1                 : 1;
2092	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
2093                                                         interrupt on the RSL. */
2094#else
2095	uint64_t rml_to                       : 1;
2096	uint64_t reserved_1_1                 : 1;
2097	uint64_t bar0_to                      : 1;
2098	uint64_t iob2big                      : 1;
2099	uint64_t pcnt                         : 1;
2100	uint64_t ptime                        : 1;
2101	uint64_t reserved_6_7                 : 2;
2102	uint64_t m0_up_b0                     : 1;
2103	uint64_t m0_up_wi                     : 1;
2104	uint64_t m0_un_b0                     : 1;
2105	uint64_t m0_un_wi                     : 1;
2106	uint64_t m1_up_b0                     : 1;
2107	uint64_t m1_up_wi                     : 1;
2108	uint64_t m1_un_b0                     : 1;
2109	uint64_t m1_un_wi                     : 1;
2110	uint64_t mio_int0                     : 1;
2111	uint64_t mio_int1                     : 1;
2112	uint64_t reserved_18_31               : 14;
2113	uint64_t dmafi                        : 2;
2114	uint64_t dcnt                         : 2;
2115	uint64_t dtime                        : 2;
2116	uint64_t reserved_38_47               : 10;
2117	uint64_t pidbof                       : 1;
2118	uint64_t psldbof                      : 1;
2119	uint64_t pout_err                     : 1;
2120	uint64_t reserved_51_51               : 1;
2121	uint64_t pgl_err                      : 1;
2122	uint64_t pdi_err                      : 1;
2123	uint64_t pop_err                      : 1;
2124	uint64_t pins_err                     : 1;
2125	uint64_t sprt0_err                    : 1;
2126	uint64_t sprt1_err                    : 1;
2127	uint64_t reserved_58_59               : 2;
2128	uint64_t ill_pad                      : 1;
2129	uint64_t pipe_err                     : 1;
2130	uint64_t reserved_62_63               : 2;
2131#endif
2132	} cn68xx;
2133	struct cvmx_sli_int_enb_ciu_cn68xx    cn68xxp1;
2134	struct cvmx_sli_int_enb_ciu_cn61xx    cnf71xx;
2135};
2136typedef union cvmx_sli_int_enb_ciu cvmx_sli_int_enb_ciu_t;
2137
2138/**
2139 * cvmx_sli_int_enb_port#
2140 *
2141 * SLI_INT_ENB_PORTX = SLI's Interrupt Enable Register per mac port
2142 *
2143 * Used to allow the generation of interrupts (MSI/INTA) to the PORT X
2144 *
2145 * Notes:
2146 * This CSR is not used when the corresponding MAC is sRIO.
2147 *
2148 */
2149union cvmx_sli_int_enb_portx {
2150	uint64_t u64;
2151	struct cvmx_sli_int_enb_portx_s {
2152#ifdef __BIG_ENDIAN_BITFIELD
2153	uint64_t reserved_62_63               : 2;
2154	uint64_t pipe_err                     : 1;  /**< Out of range PIPE value. */
2155	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
2156	uint64_t sprt3_err                    : 1;  /**< Error Response received on SLI port 3. */
2157	uint64_t sprt2_err                    : 1;  /**< Error Response received on SLI port 2. */
2158	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
2159	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
2160	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
2161	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
2162	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
2163	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
2164	uint64_t pin_bp                       : 1;  /**< Packet Input Count exceeded WMARK. */
2165	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
2166	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
2167	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
2168	uint64_t reserved_38_47               : 10;
2169	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
2170	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
2171	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
2172	uint64_t reserved_28_31               : 4;
2173	uint64_t m3_un_wi                     : 1;  /**< Reserved. */
2174	uint64_t m3_un_b0                     : 1;  /**< Reserved. */
2175	uint64_t m3_up_wi                     : 1;  /**< Reserved. */
2176	uint64_t m3_up_b0                     : 1;  /**< Reserved. */
2177	uint64_t m2_un_wi                     : 1;  /**< Reserved. */
2178	uint64_t m2_un_b0                     : 1;  /**< Reserved. */
2179	uint64_t m2_up_wi                     : 1;  /**< Reserved. */
2180	uint64_t m2_up_b0                     : 1;  /**< Reserved. */
2181	uint64_t mac1_int                     : 1;  /**< Enables SLI_INT_SUM[19] to generate an
2182                                                         interrupt to the PCIE-Port1 for MSI/inta.
2183                                                         The valuse of this bit has NO effect on PCIE Port0.
2184                                                         SLI_INT_ENB_PORT0[MAC1_INT] sould NEVER be set. */
2185	uint64_t mac0_int                     : 1;  /**< Enables SLI_INT_SUM[18] to generate an
2186                                                         interrupt to the PCIE-Port0 for MSI/inta.
2187                                                         The valus of this bit has NO effect on PCIE Port1.
2188                                                         SLI_INT_ENB_PORT1[MAC0_INT] sould NEVER be set. */
2189	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
2190                                                         interrupt to the PCIE core for MSI/inta.
2191                                                         SLI_INT_ENB_PORT0[MIO_INT1] should NEVER be set. */
2192	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
2193                                                         interrupt to the PCIE core for MSI/inta.
2194                                                         SLI_INT_ENB_PORT1[MIO_INT0] should NEVER be set. */
2195	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
2196                                                         interrupt to the PCIE core for MSI/inta. */
2197	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
2198                                                         interrupt to the PCIE core for MSI/inta. */
2199	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
2200                                                         interrupt to the PCIE core for MSI/inta. */
2201	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
2202                                                         interrupt to the PCIE core for MSI/inta. */
2203	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
2204                                                         interrupt to the PCIE core for MSI/inta. */
2205	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
2206                                                         interrupt to the PCIE core for MSI/inta. */
2207	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
2208                                                         interrupt to the PCIE core for MSI/inta. */
2209	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
2210                                                         interrupt to the PCIE core for MSI/inta. */
2211	uint64_t reserved_6_7                 : 2;
2212	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
2213                                                         interrupt to the PCIE core for MSI/inta. */
2214	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
2215                                                         interrupt to the PCIE core for MSI/inta. */
2216	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
2217                                                         interrupt to the PCIE core for MSI/inta. */
2218	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
2219                                                         interrupt to the PCIE core for MSI/inta. */
2220	uint64_t reserved_1_1                 : 1;
2221	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
2222                                                         interrupt to the PCIE core for MSI/inta. */
2223#else
2224	uint64_t rml_to                       : 1;
2225	uint64_t reserved_1_1                 : 1;
2226	uint64_t bar0_to                      : 1;
2227	uint64_t iob2big                      : 1;
2228	uint64_t pcnt                         : 1;
2229	uint64_t ptime                        : 1;
2230	uint64_t reserved_6_7                 : 2;
2231	uint64_t m0_up_b0                     : 1;
2232	uint64_t m0_up_wi                     : 1;
2233	uint64_t m0_un_b0                     : 1;
2234	uint64_t m0_un_wi                     : 1;
2235	uint64_t m1_up_b0                     : 1;
2236	uint64_t m1_up_wi                     : 1;
2237	uint64_t m1_un_b0                     : 1;
2238	uint64_t m1_un_wi                     : 1;
2239	uint64_t mio_int0                     : 1;
2240	uint64_t mio_int1                     : 1;
2241	uint64_t mac0_int                     : 1;
2242	uint64_t mac1_int                     : 1;
2243	uint64_t m2_up_b0                     : 1;
2244	uint64_t m2_up_wi                     : 1;
2245	uint64_t m2_un_b0                     : 1;
2246	uint64_t m2_un_wi                     : 1;
2247	uint64_t m3_up_b0                     : 1;
2248	uint64_t m3_up_wi                     : 1;
2249	uint64_t m3_un_b0                     : 1;
2250	uint64_t m3_un_wi                     : 1;
2251	uint64_t reserved_28_31               : 4;
2252	uint64_t dmafi                        : 2;
2253	uint64_t dcnt                         : 2;
2254	uint64_t dtime                        : 2;
2255	uint64_t reserved_38_47               : 10;
2256	uint64_t pidbof                       : 1;
2257	uint64_t psldbof                      : 1;
2258	uint64_t pout_err                     : 1;
2259	uint64_t pin_bp                       : 1;
2260	uint64_t pgl_err                      : 1;
2261	uint64_t pdi_err                      : 1;
2262	uint64_t pop_err                      : 1;
2263	uint64_t pins_err                     : 1;
2264	uint64_t sprt0_err                    : 1;
2265	uint64_t sprt1_err                    : 1;
2266	uint64_t sprt2_err                    : 1;
2267	uint64_t sprt3_err                    : 1;
2268	uint64_t ill_pad                      : 1;
2269	uint64_t pipe_err                     : 1;
2270	uint64_t reserved_62_63               : 2;
2271#endif
2272	} s;
2273	struct cvmx_sli_int_enb_portx_cn61xx {
2274#ifdef __BIG_ENDIAN_BITFIELD
2275	uint64_t reserved_61_63               : 3;
2276	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
2277	uint64_t sprt3_err                    : 1;  /**< Error Response received on SLI port 3. */
2278	uint64_t sprt2_err                    : 1;  /**< Error Response received on SLI port 2. */
2279	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
2280	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
2281	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
2282	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
2283	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
2284	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
2285	uint64_t pin_bp                       : 1;  /**< Packet Input Count exceeded WMARK. */
2286	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
2287	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
2288	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
2289	uint64_t reserved_38_47               : 10;
2290	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
2291	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
2292	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
2293	uint64_t reserved_28_31               : 4;
2294	uint64_t m3_un_wi                     : 1;  /**< Reserved. */
2295	uint64_t m3_un_b0                     : 1;  /**< Reserved. */
2296	uint64_t m3_up_wi                     : 1;  /**< Reserved. */
2297	uint64_t m3_up_b0                     : 1;  /**< Reserved. */
2298	uint64_t m2_un_wi                     : 1;  /**< Reserved. */
2299	uint64_t m2_un_b0                     : 1;  /**< Reserved. */
2300	uint64_t m2_up_wi                     : 1;  /**< Reserved. */
2301	uint64_t m2_up_b0                     : 1;  /**< Reserved. */
2302	uint64_t mac1_int                     : 1;  /**< Enables SLI_INT_SUM[19] to generate an
2303                                                         interrupt to the PCIE-Port1 for MSI/inta.
2304                                                         The valuse of this bit has NO effect on PCIE Port0.
2305                                                         SLI_INT_ENB_PORT0[MAC1_INT] sould NEVER be set. */
2306	uint64_t mac0_int                     : 1;  /**< Enables SLI_INT_SUM[18] to generate an
2307                                                         interrupt to the PCIE-Port0 for MSI/inta.
2308                                                         The valus of this bit has NO effect on PCIE Port1.
2309                                                         SLI_INT_ENB_PORT1[MAC0_INT] sould NEVER be set. */
2310	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
2311                                                         interrupt to the PCIE core for MSI/inta.
2312                                                         SLI_INT_ENB_PORT0[MIO_INT1] should NEVER be set. */
2313	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
2314                                                         interrupt to the PCIE core for MSI/inta.
2315                                                         SLI_INT_ENB_PORT1[MIO_INT0] should NEVER be set. */
2316	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
2317                                                         interrupt to the PCIE core for MSI/inta. */
2318	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
2319                                                         interrupt to the PCIE core for MSI/inta. */
2320	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
2321                                                         interrupt to the PCIE core for MSI/inta. */
2322	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
2323                                                         interrupt to the PCIE core for MSI/inta. */
2324	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
2325                                                         interrupt to the PCIE core for MSI/inta. */
2326	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
2327                                                         interrupt to the PCIE core for MSI/inta. */
2328	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
2329                                                         interrupt to the PCIE core for MSI/inta. */
2330	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
2331                                                         interrupt to the PCIE core for MSI/inta. */
2332	uint64_t reserved_6_7                 : 2;
2333	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
2334                                                         interrupt to the PCIE core for MSI/inta. */
2335	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
2336                                                         interrupt to the PCIE core for MSI/inta. */
2337	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
2338                                                         interrupt to the PCIE core for MSI/inta. */
2339	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
2340                                                         interrupt to the PCIE core for MSI/inta. */
2341	uint64_t reserved_1_1                 : 1;
2342	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
2343                                                         interrupt to the PCIE core for MSI/inta. */
2344#else
2345	uint64_t rml_to                       : 1;
2346	uint64_t reserved_1_1                 : 1;
2347	uint64_t bar0_to                      : 1;
2348	uint64_t iob2big                      : 1;
2349	uint64_t pcnt                         : 1;
2350	uint64_t ptime                        : 1;
2351	uint64_t reserved_6_7                 : 2;
2352	uint64_t m0_up_b0                     : 1;
2353	uint64_t m0_up_wi                     : 1;
2354	uint64_t m0_un_b0                     : 1;
2355	uint64_t m0_un_wi                     : 1;
2356	uint64_t m1_up_b0                     : 1;
2357	uint64_t m1_up_wi                     : 1;
2358	uint64_t m1_un_b0                     : 1;
2359	uint64_t m1_un_wi                     : 1;
2360	uint64_t mio_int0                     : 1;
2361	uint64_t mio_int1                     : 1;
2362	uint64_t mac0_int                     : 1;
2363	uint64_t mac1_int                     : 1;
2364	uint64_t m2_up_b0                     : 1;
2365	uint64_t m2_up_wi                     : 1;
2366	uint64_t m2_un_b0                     : 1;
2367	uint64_t m2_un_wi                     : 1;
2368	uint64_t m3_up_b0                     : 1;
2369	uint64_t m3_up_wi                     : 1;
2370	uint64_t m3_un_b0                     : 1;
2371	uint64_t m3_un_wi                     : 1;
2372	uint64_t reserved_28_31               : 4;
2373	uint64_t dmafi                        : 2;
2374	uint64_t dcnt                         : 2;
2375	uint64_t dtime                        : 2;
2376	uint64_t reserved_38_47               : 10;
2377	uint64_t pidbof                       : 1;
2378	uint64_t psldbof                      : 1;
2379	uint64_t pout_err                     : 1;
2380	uint64_t pin_bp                       : 1;
2381	uint64_t pgl_err                      : 1;
2382	uint64_t pdi_err                      : 1;
2383	uint64_t pop_err                      : 1;
2384	uint64_t pins_err                     : 1;
2385	uint64_t sprt0_err                    : 1;
2386	uint64_t sprt1_err                    : 1;
2387	uint64_t sprt2_err                    : 1;
2388	uint64_t sprt3_err                    : 1;
2389	uint64_t ill_pad                      : 1;
2390	uint64_t reserved_61_63               : 3;
2391#endif
2392	} cn61xx;
2393	struct cvmx_sli_int_enb_portx_cn63xx {
2394#ifdef __BIG_ENDIAN_BITFIELD
2395	uint64_t reserved_61_63               : 3;
2396	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
2397	uint64_t reserved_58_59               : 2;
2398	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
2399	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
2400	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
2401	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
2402	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
2403	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
2404	uint64_t pin_bp                       : 1;  /**< Packet Input Count exceeded WMARK. */
2405	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
2406	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
2407	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
2408	uint64_t reserved_38_47               : 10;
2409	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
2410	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
2411	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
2412	uint64_t reserved_20_31               : 12;
2413	uint64_t mac1_int                     : 1;  /**< Enables SLI_INT_SUM[19] to generate an
2414                                                         interrupt to the PCIE-Port1 for MSI/inta.
2415                                                         The valuse of this bit has NO effect on PCIE Port0.
2416                                                         SLI_INT_ENB_PORT0[MAC1_INT] sould NEVER be set. */
2417	uint64_t mac0_int                     : 1;  /**< Enables SLI_INT_SUM[18] to generate an
2418                                                         interrupt to the PCIE-Port0 for MSI/inta.
2419                                                         The valus of this bit has NO effect on PCIE Port1.
2420                                                         SLI_INT_ENB_PORT1[MAC0_INT] sould NEVER be set. */
2421	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
2422                                                         interrupt to the PCIE core for MSI/inta.
2423                                                         SLI_INT_ENB_PORT0[MIO_INT1] should NEVER be set. */
2424	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
2425                                                         interrupt to the PCIE core for MSI/inta.
2426                                                         SLI_INT_ENB_PORT1[MIO_INT0] should NEVER be set. */
2427	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
2428                                                         interrupt to the PCIE core for MSI/inta. */
2429	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
2430                                                         interrupt to the PCIE core for MSI/inta. */
2431	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
2432                                                         interrupt to the PCIE core for MSI/inta. */
2433	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
2434                                                         interrupt to the PCIE core for MSI/inta. */
2435	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
2436                                                         interrupt to the PCIE core for MSI/inta. */
2437	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
2438                                                         interrupt to the PCIE core for MSI/inta. */
2439	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
2440                                                         interrupt to the PCIE core for MSI/inta. */
2441	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
2442                                                         interrupt to the PCIE core for MSI/inta. */
2443	uint64_t reserved_6_7                 : 2;
2444	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
2445                                                         interrupt to the PCIE core for MSI/inta. */
2446	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
2447                                                         interrupt to the PCIE core for MSI/inta. */
2448	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
2449                                                         interrupt to the PCIE core for MSI/inta. */
2450	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
2451                                                         interrupt to the PCIE core for MSI/inta. */
2452	uint64_t reserved_1_1                 : 1;
2453	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
2454                                                         interrupt to the PCIE core for MSI/inta. */
2455#else
2456	uint64_t rml_to                       : 1;
2457	uint64_t reserved_1_1                 : 1;
2458	uint64_t bar0_to                      : 1;
2459	uint64_t iob2big                      : 1;
2460	uint64_t pcnt                         : 1;
2461	uint64_t ptime                        : 1;
2462	uint64_t reserved_6_7                 : 2;
2463	uint64_t m0_up_b0                     : 1;
2464	uint64_t m0_up_wi                     : 1;
2465	uint64_t m0_un_b0                     : 1;
2466	uint64_t m0_un_wi                     : 1;
2467	uint64_t m1_up_b0                     : 1;
2468	uint64_t m1_up_wi                     : 1;
2469	uint64_t m1_un_b0                     : 1;
2470	uint64_t m1_un_wi                     : 1;
2471	uint64_t mio_int0                     : 1;
2472	uint64_t mio_int1                     : 1;
2473	uint64_t mac0_int                     : 1;
2474	uint64_t mac1_int                     : 1;
2475	uint64_t reserved_20_31               : 12;
2476	uint64_t dmafi                        : 2;
2477	uint64_t dcnt                         : 2;
2478	uint64_t dtime                        : 2;
2479	uint64_t reserved_38_47               : 10;
2480	uint64_t pidbof                       : 1;
2481	uint64_t psldbof                      : 1;
2482	uint64_t pout_err                     : 1;
2483	uint64_t pin_bp                       : 1;
2484	uint64_t pgl_err                      : 1;
2485	uint64_t pdi_err                      : 1;
2486	uint64_t pop_err                      : 1;
2487	uint64_t pins_err                     : 1;
2488	uint64_t sprt0_err                    : 1;
2489	uint64_t sprt1_err                    : 1;
2490	uint64_t reserved_58_59               : 2;
2491	uint64_t ill_pad                      : 1;
2492	uint64_t reserved_61_63               : 3;
2493#endif
2494	} cn63xx;
2495	struct cvmx_sli_int_enb_portx_cn63xx  cn63xxp1;
2496	struct cvmx_sli_int_enb_portx_cn61xx  cn66xx;
2497	struct cvmx_sli_int_enb_portx_cn68xx {
2498#ifdef __BIG_ENDIAN_BITFIELD
2499	uint64_t reserved_62_63               : 2;
2500	uint64_t pipe_err                     : 1;  /**< Out of range PIPE value. */
2501	uint64_t ill_pad                      : 1;  /**< Illegal packet csr address. */
2502	uint64_t reserved_58_59               : 2;
2503	uint64_t sprt1_err                    : 1;  /**< Error Response received on SLI port 1. */
2504	uint64_t sprt0_err                    : 1;  /**< Error Response received on SLI port 0. */
2505	uint64_t pins_err                     : 1;  /**< Read Error during packet instruction fetch. */
2506	uint64_t pop_err                      : 1;  /**< Read Error during packet scatter pointer fetch. */
2507	uint64_t pdi_err                      : 1;  /**< Read Error during packet data fetch. */
2508	uint64_t pgl_err                      : 1;  /**< Read Error during gather list fetch. */
2509	uint64_t reserved_51_51               : 1;
2510	uint64_t pout_err                     : 1;  /**< Packet Out Interrupt, Error From PKO. */
2511	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell Count Overflow. */
2512	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell Count Overflow. */
2513	uint64_t reserved_38_47               : 10;
2514	uint64_t dtime                        : 2;  /**< DMA Timer Interrupts */
2515	uint64_t dcnt                         : 2;  /**< DMA Count Interrupts */
2516	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts */
2517	uint64_t reserved_20_31               : 12;
2518	uint64_t mac1_int                     : 1;  /**< Enables SLI_INT_SUM[19] to generate an
2519                                                         interrupt to the PCIE-Port1 for MSI/inta.
2520                                                         The valuse of this bit has NO effect on PCIE Port0.
2521                                                         SLI_INT_ENB_PORT0[MAC1_INT] sould NEVER be set. */
2522	uint64_t mac0_int                     : 1;  /**< Enables SLI_INT_SUM[18] to generate an
2523                                                         interrupt to the PCIE-Port0 for MSI/inta.
2524                                                         The valus of this bit has NO effect on PCIE Port1.
2525                                                         SLI_INT_ENB_PORT1[MAC0_INT] sould NEVER be set. */
2526	uint64_t mio_int1                     : 1;  /**< Enables SLI_INT_SUM[17] to generate an
2527                                                         interrupt to the PCIE core for MSI/inta.
2528                                                         SLI_INT_ENB_PORT0[MIO_INT1] should NEVER be set. */
2529	uint64_t mio_int0                     : 1;  /**< Enables SLI_INT_SUM[16] to generate an
2530                                                         interrupt to the PCIE core for MSI/inta.
2531                                                         SLI_INT_ENB_PORT1[MIO_INT0] should NEVER be set. */
2532	uint64_t m1_un_wi                     : 1;  /**< Enables SLI_INT_SUM[15] to generate an
2533                                                         interrupt to the PCIE core for MSI/inta. */
2534	uint64_t m1_un_b0                     : 1;  /**< Enables SLI_INT_SUM[14] to generate an
2535                                                         interrupt to the PCIE core for MSI/inta. */
2536	uint64_t m1_up_wi                     : 1;  /**< Enables SLI_INT_SUM[13] to generate an
2537                                                         interrupt to the PCIE core for MSI/inta. */
2538	uint64_t m1_up_b0                     : 1;  /**< Enables SLI_INT_SUM[12] to generate an
2539                                                         interrupt to the PCIE core for MSI/inta. */
2540	uint64_t m0_un_wi                     : 1;  /**< Enables SLI_INT_SUM[11] to generate an
2541                                                         interrupt to the PCIE core for MSI/inta. */
2542	uint64_t m0_un_b0                     : 1;  /**< Enables SLI_INT_SUM[10] to generate an
2543                                                         interrupt to the PCIE core for MSI/inta. */
2544	uint64_t m0_up_wi                     : 1;  /**< Enables SLI_INT_SUM[9] to generate an
2545                                                         interrupt to the PCIE core for MSI/inta. */
2546	uint64_t m0_up_b0                     : 1;  /**< Enables SLI_INT_SUM[8] to generate an
2547                                                         interrupt to the PCIE core for MSI/inta. */
2548	uint64_t reserved_6_7                 : 2;
2549	uint64_t ptime                        : 1;  /**< Enables SLI_INT_SUM[5] to generate an
2550                                                         interrupt to the PCIE core for MSI/inta. */
2551	uint64_t pcnt                         : 1;  /**< Enables SLI_INT_SUM[4] to generate an
2552                                                         interrupt to the PCIE core for MSI/inta. */
2553	uint64_t iob2big                      : 1;  /**< Enables SLI_INT_SUM[3] to generate an
2554                                                         interrupt to the PCIE core for MSI/inta. */
2555	uint64_t bar0_to                      : 1;  /**< Enables SLI_INT_SUM[2] to generate an
2556                                                         interrupt to the PCIE core for MSI/inta. */
2557	uint64_t reserved_1_1                 : 1;
2558	uint64_t rml_to                       : 1;  /**< Enables SLI_INT_SUM[0] to generate an
2559                                                         interrupt to the PCIE core for MSI/inta. */
2560#else
2561	uint64_t rml_to                       : 1;
2562	uint64_t reserved_1_1                 : 1;
2563	uint64_t bar0_to                      : 1;
2564	uint64_t iob2big                      : 1;
2565	uint64_t pcnt                         : 1;
2566	uint64_t ptime                        : 1;
2567	uint64_t reserved_6_7                 : 2;
2568	uint64_t m0_up_b0                     : 1;
2569	uint64_t m0_up_wi                     : 1;
2570	uint64_t m0_un_b0                     : 1;
2571	uint64_t m0_un_wi                     : 1;
2572	uint64_t m1_up_b0                     : 1;
2573	uint64_t m1_up_wi                     : 1;
2574	uint64_t m1_un_b0                     : 1;
2575	uint64_t m1_un_wi                     : 1;
2576	uint64_t mio_int0                     : 1;
2577	uint64_t mio_int1                     : 1;
2578	uint64_t mac0_int                     : 1;
2579	uint64_t mac1_int                     : 1;
2580	uint64_t reserved_20_31               : 12;
2581	uint64_t dmafi                        : 2;
2582	uint64_t dcnt                         : 2;
2583	uint64_t dtime                        : 2;
2584	uint64_t reserved_38_47               : 10;
2585	uint64_t pidbof                       : 1;
2586	uint64_t psldbof                      : 1;
2587	uint64_t pout_err                     : 1;
2588	uint64_t reserved_51_51               : 1;
2589	uint64_t pgl_err                      : 1;
2590	uint64_t pdi_err                      : 1;
2591	uint64_t pop_err                      : 1;
2592	uint64_t pins_err                     : 1;
2593	uint64_t sprt0_err                    : 1;
2594	uint64_t sprt1_err                    : 1;
2595	uint64_t reserved_58_59               : 2;
2596	uint64_t ill_pad                      : 1;
2597	uint64_t pipe_err                     : 1;
2598	uint64_t reserved_62_63               : 2;
2599#endif
2600	} cn68xx;
2601	struct cvmx_sli_int_enb_portx_cn68xx  cn68xxp1;
2602	struct cvmx_sli_int_enb_portx_cn61xx  cnf71xx;
2603};
2604typedef union cvmx_sli_int_enb_portx cvmx_sli_int_enb_portx_t;
2605
2606/**
2607 * cvmx_sli_int_sum
2608 *
2609 * SLI_INT_SUM = SLI Interrupt Summary Register
2610 *
2611 * Set when an interrupt condition occurs, write '1' to clear.
2612 */
2613union cvmx_sli_int_sum {
2614	uint64_t u64;
2615	struct cvmx_sli_int_sum_s {
2616#ifdef __BIG_ENDIAN_BITFIELD
2617	uint64_t reserved_62_63               : 2;
2618	uint64_t pipe_err                     : 1;  /**< Set when a PIPE value outside range is received. */
2619	uint64_t ill_pad                      : 1;  /**< Set when a BAR0 address R/W falls into theaddress
2620                                                         range of the Packet-CSR, but for an unused
2621                                                         address. */
2622	uint64_t sprt3_err                    : 1;  /**< Reserved. */
2623	uint64_t sprt2_err                    : 1;  /**< Reserved. */
2624	uint64_t sprt1_err                    : 1;  /**< When an error response received on SLI port 1
2625                                                         this bit is set. */
2626	uint64_t sprt0_err                    : 1;  /**< When an error response received on SLI port 0
2627                                                         this bit is set. */
2628	uint64_t pins_err                     : 1;  /**< When a read error occurs on a packet instruction
2629                                                         this bit is set. */
2630	uint64_t pop_err                      : 1;  /**< When a read error occurs on a packet scatter
2631                                                         pointer pair this bit is set. */
2632	uint64_t pdi_err                      : 1;  /**< When a read error occurs on a packet data read
2633                                                         this bit is set. */
2634	uint64_t pgl_err                      : 1;  /**< When a read error occurs on a packet gather list
2635                                                         read this bit is set. */
2636	uint64_t pin_bp                       : 1;  /**< Packet input count has exceeded the WMARK.
2637                                                         See SLI_PKT_IN_BP */
2638	uint64_t pout_err                     : 1;  /**< Set when PKO sends packet data with the error bit
2639                                                         set. */
2640	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell count overflowed. Which
2641                                                         doorbell can be found in DPI_PINT_INFO[PSLDBOF] */
2642	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell count overflowed. Which
2643                                                         doorbell can be found in DPI_PINT_INFO[PIDBOF] */
2644	uint64_t reserved_38_47               : 10;
2645	uint64_t dtime                        : 2;  /**< Whenever SLI_DMAx_CNT[CNT] is not 0, the
2646                                                         SLI_DMAx_TIM[TIM] timer increments every SLI
2647                                                         clock.
2648                                                         DTIME[x] is set whenever SLI_DMAx_TIM[TIM] >
2649                                                         SLI_DMAx_INT_LEVEL[TIME].
2650                                                         DTIME[x] is normally cleared by clearing
2651                                                         SLI_DMAx_CNT[CNT] (which also clears
2652                                                         SLI_DMAx_TIM[TIM]). */
2653	uint64_t dcnt                         : 2;  /**< DCNT[x] is set whenever SLI_DMAx_CNT[CNT] >
2654                                                         SLI_DMAx_INT_LEVEL[CNT].
2655                                                         DCNT[x] is normally cleared by decreasing
2656                                                         SLI_DMAx_CNT[CNT]. */
2657	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts. */
2658	uint64_t reserved_28_31               : 4;
2659	uint64_t m3_un_wi                     : 1;  /**< Reserved. */
2660	uint64_t m3_un_b0                     : 1;  /**< Reserved. */
2661	uint64_t m3_up_wi                     : 1;  /**< Reserved. */
2662	uint64_t m3_up_b0                     : 1;  /**< Reserved. */
2663	uint64_t m2_un_wi                     : 1;  /**< Reserved. */
2664	uint64_t m2_un_b0                     : 1;  /**< Reserved. */
2665	uint64_t m2_up_wi                     : 1;  /**< Reserved. */
2666	uint64_t m2_up_b0                     : 1;  /**< Reserved. */
2667	uint64_t mac1_int                     : 1;  /**< Interrupt from MAC1.
2668                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB_INT) */
2669	uint64_t mac0_int                     : 1;  /**< Interrupt from MAC0.
2670                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB_INT) */
2671	uint64_t mio_int1                     : 1;  /**< Interrupt from MIO for PORT 1.
2672                                                         See CIU_INT33_SUM0, CIU_INT_SUM1
2673                                                         (enabled by CIU_INT33_EN0, CIU_INT33_EN1) */
2674	uint64_t mio_int0                     : 1;  /**< Interrupt from MIO for PORT 0.
2675                                                         See CIU_INT32_SUM0, CIU_INT_SUM1
2676                                                         (enabled by CIU_INT32_EN0, CIU_INT32_EN1) */
2677	uint64_t m1_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register
2678                                                         from MAC 1. This occurs when the window registers
2679                                                         are disabeld and a window register access occurs. */
2680	uint64_t m1_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0 from MAC 1.
2681                                                         This occurs when the BAR 0 address space is
2682                                                         disabeled. */
2683	uint64_t m1_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register
2684                                                         from MAC 1. This occurs when the window registers
2685                                                         are disabeld and a window register access occurs. */
2686	uint64_t m1_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0 from MAC 1.
2687                                                         This occurs when the BAR 0 address space is
2688                                                         disabeled. */
2689	uint64_t m0_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register
2690                                                         from MAC 0. This occurs when the window registers
2691                                                         are disabeld and a window register access occurs. */
2692	uint64_t m0_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0 from MAC 0.
2693                                                         This occurs when the BAR 0 address space is
2694                                                         disabeled. */
2695	uint64_t m0_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register
2696                                                         from MAC 0. This occurs when the window registers
2697                                                         are disabeld and a window register access occurs. */
2698	uint64_t m0_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0 from MAC 0.
2699                                                         This occurs when the BAR 0 address space is
2700                                                         disabeled. */
2701	uint64_t reserved_6_7                 : 2;
2702	uint64_t ptime                        : 1;  /**< Packet Timer has an interrupt. Which rings can
2703                                                         be found in SLI_PKT_TIME_INT. */
2704	uint64_t pcnt                         : 1;  /**< Packet Counter has an interrupt. Which rings can
2705                                                         be found in SLI_PKT_CNT_INT. */
2706	uint64_t iob2big                      : 1;  /**< A requested IOBDMA is to large. */
2707	uint64_t bar0_to                      : 1;  /**< BAR0 R/W to a NCB device did not receive
2708                                                         read-data/commit in 0xffff core clocks. */
2709	uint64_t reserved_1_1                 : 1;
2710	uint64_t rml_to                       : 1;  /**< A read or write transfer did not complete
2711                                                         within 0xffff core clocks. */
2712#else
2713	uint64_t rml_to                       : 1;
2714	uint64_t reserved_1_1                 : 1;
2715	uint64_t bar0_to                      : 1;
2716	uint64_t iob2big                      : 1;
2717	uint64_t pcnt                         : 1;
2718	uint64_t ptime                        : 1;
2719	uint64_t reserved_6_7                 : 2;
2720	uint64_t m0_up_b0                     : 1;
2721	uint64_t m0_up_wi                     : 1;
2722	uint64_t m0_un_b0                     : 1;
2723	uint64_t m0_un_wi                     : 1;
2724	uint64_t m1_up_b0                     : 1;
2725	uint64_t m1_up_wi                     : 1;
2726	uint64_t m1_un_b0                     : 1;
2727	uint64_t m1_un_wi                     : 1;
2728	uint64_t mio_int0                     : 1;
2729	uint64_t mio_int1                     : 1;
2730	uint64_t mac0_int                     : 1;
2731	uint64_t mac1_int                     : 1;
2732	uint64_t m2_up_b0                     : 1;
2733	uint64_t m2_up_wi                     : 1;
2734	uint64_t m2_un_b0                     : 1;
2735	uint64_t m2_un_wi                     : 1;
2736	uint64_t m3_up_b0                     : 1;
2737	uint64_t m3_up_wi                     : 1;
2738	uint64_t m3_un_b0                     : 1;
2739	uint64_t m3_un_wi                     : 1;
2740	uint64_t reserved_28_31               : 4;
2741	uint64_t dmafi                        : 2;
2742	uint64_t dcnt                         : 2;
2743	uint64_t dtime                        : 2;
2744	uint64_t reserved_38_47               : 10;
2745	uint64_t pidbof                       : 1;
2746	uint64_t psldbof                      : 1;
2747	uint64_t pout_err                     : 1;
2748	uint64_t pin_bp                       : 1;
2749	uint64_t pgl_err                      : 1;
2750	uint64_t pdi_err                      : 1;
2751	uint64_t pop_err                      : 1;
2752	uint64_t pins_err                     : 1;
2753	uint64_t sprt0_err                    : 1;
2754	uint64_t sprt1_err                    : 1;
2755	uint64_t sprt2_err                    : 1;
2756	uint64_t sprt3_err                    : 1;
2757	uint64_t ill_pad                      : 1;
2758	uint64_t pipe_err                     : 1;
2759	uint64_t reserved_62_63               : 2;
2760#endif
2761	} s;
2762	struct cvmx_sli_int_sum_cn61xx {
2763#ifdef __BIG_ENDIAN_BITFIELD
2764	uint64_t reserved_61_63               : 3;
2765	uint64_t ill_pad                      : 1;  /**< Set when a BAR0 address R/W falls into theaddress
2766                                                         range of the Packet-CSR, but for an unused
2767                                                         address. */
2768	uint64_t sprt3_err                    : 1;  /**< Reserved. */
2769	uint64_t sprt2_err                    : 1;  /**< Reserved. */
2770	uint64_t sprt1_err                    : 1;  /**< When an error response received on SLI port 1
2771                                                         this bit is set. */
2772	uint64_t sprt0_err                    : 1;  /**< When an error response received on SLI port 0
2773                                                         this bit is set. */
2774	uint64_t pins_err                     : 1;  /**< When a read error occurs on a packet instruction
2775                                                         this bit is set. */
2776	uint64_t pop_err                      : 1;  /**< When a read error occurs on a packet scatter
2777                                                         pointer pair this bit is set. */
2778	uint64_t pdi_err                      : 1;  /**< When a read error occurs on a packet data read
2779                                                         this bit is set. */
2780	uint64_t pgl_err                      : 1;  /**< When a read error occurs on a packet gather list
2781                                                         read this bit is set. */
2782	uint64_t pin_bp                       : 1;  /**< Packet input count has exceeded the WMARK.
2783                                                         See SLI_PKT_IN_BP */
2784	uint64_t pout_err                     : 1;  /**< Set when PKO sends packet data with the error bit
2785                                                         set. */
2786	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell count overflowed. Which
2787                                                         doorbell can be found in DPI_PINT_INFO[PSLDBOF] */
2788	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell count overflowed. Which
2789                                                         doorbell can be found in DPI_PINT_INFO[PIDBOF] */
2790	uint64_t reserved_38_47               : 10;
2791	uint64_t dtime                        : 2;  /**< Whenever SLI_DMAx_CNT[CNT] is not 0, the
2792                                                         SLI_DMAx_TIM[TIM] timer increments every SLI
2793                                                         clock.
2794                                                         DTIME[x] is set whenever SLI_DMAx_TIM[TIM] >
2795                                                         SLI_DMAx_INT_LEVEL[TIME].
2796                                                         DTIME[x] is normally cleared by clearing
2797                                                         SLI_DMAx_CNT[CNT] (which also clears
2798                                                         SLI_DMAx_TIM[TIM]). */
2799	uint64_t dcnt                         : 2;  /**< DCNT[x] is set whenever SLI_DMAx_CNT[CNT] >
2800                                                         SLI_DMAx_INT_LEVEL[CNT].
2801                                                         DCNT[x] is normally cleared by decreasing
2802                                                         SLI_DMAx_CNT[CNT]. */
2803	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts. */
2804	uint64_t reserved_28_31               : 4;
2805	uint64_t m3_un_wi                     : 1;  /**< Reserved. */
2806	uint64_t m3_un_b0                     : 1;  /**< Reserved. */
2807	uint64_t m3_up_wi                     : 1;  /**< Reserved. */
2808	uint64_t m3_up_b0                     : 1;  /**< Reserved. */
2809	uint64_t m2_un_wi                     : 1;  /**< Reserved. */
2810	uint64_t m2_un_b0                     : 1;  /**< Reserved. */
2811	uint64_t m2_up_wi                     : 1;  /**< Reserved. */
2812	uint64_t m2_up_b0                     : 1;  /**< Reserved. */
2813	uint64_t mac1_int                     : 1;  /**< Interrupt from MAC1.
2814                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB_INT) */
2815	uint64_t mac0_int                     : 1;  /**< Interrupt from MAC0.
2816                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB_INT) */
2817	uint64_t mio_int1                     : 1;  /**< Interrupt from MIO for PORT 1.
2818                                                         See CIU_INT33_SUM0, CIU_INT_SUM1
2819                                                         (enabled by CIU_INT33_EN0, CIU_INT33_EN1) */
2820	uint64_t mio_int0                     : 1;  /**< Interrupt from MIO for PORT 0.
2821                                                         See CIU_INT32_SUM0, CIU_INT_SUM1
2822                                                         (enabled by CIU_INT32_EN0, CIU_INT32_EN1) */
2823	uint64_t m1_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register
2824                                                         from MAC 1. This occurs when the window registers
2825                                                         are disabeld and a window register access occurs. */
2826	uint64_t m1_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0 from MAC 1.
2827                                                         This occurs when the BAR 0 address space is
2828                                                         disabeled. */
2829	uint64_t m1_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register
2830                                                         from MAC 1. This occurs when the window registers
2831                                                         are disabeld and a window register access occurs. */
2832	uint64_t m1_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0 from MAC 1.
2833                                                         This occurs when the BAR 0 address space is
2834                                                         disabeled. */
2835	uint64_t m0_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register
2836                                                         from MAC 0. This occurs when the window registers
2837                                                         are disabeld and a window register access occurs. */
2838	uint64_t m0_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0 from MAC 0.
2839                                                         This occurs when the BAR 0 address space is
2840                                                         disabeled. */
2841	uint64_t m0_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register
2842                                                         from MAC 0. This occurs when the window registers
2843                                                         are disabeld and a window register access occurs. */
2844	uint64_t m0_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0 from MAC 0.
2845                                                         This occurs when the BAR 0 address space is
2846                                                         disabeled. */
2847	uint64_t reserved_6_7                 : 2;
2848	uint64_t ptime                        : 1;  /**< Packet Timer has an interrupt. Which rings can
2849                                                         be found in SLI_PKT_TIME_INT. */
2850	uint64_t pcnt                         : 1;  /**< Packet Counter has an interrupt. Which rings can
2851                                                         be found in SLI_PKT_CNT_INT. */
2852	uint64_t iob2big                      : 1;  /**< A requested IOBDMA is to large. */
2853	uint64_t bar0_to                      : 1;  /**< BAR0 R/W to a NCB device did not receive
2854                                                         read-data/commit in 0xffff core clocks. */
2855	uint64_t reserved_1_1                 : 1;
2856	uint64_t rml_to                       : 1;  /**< A read or write transfer did not complete
2857                                                         within 0xffff core clocks. */
2858#else
2859	uint64_t rml_to                       : 1;
2860	uint64_t reserved_1_1                 : 1;
2861	uint64_t bar0_to                      : 1;
2862	uint64_t iob2big                      : 1;
2863	uint64_t pcnt                         : 1;
2864	uint64_t ptime                        : 1;
2865	uint64_t reserved_6_7                 : 2;
2866	uint64_t m0_up_b0                     : 1;
2867	uint64_t m0_up_wi                     : 1;
2868	uint64_t m0_un_b0                     : 1;
2869	uint64_t m0_un_wi                     : 1;
2870	uint64_t m1_up_b0                     : 1;
2871	uint64_t m1_up_wi                     : 1;
2872	uint64_t m1_un_b0                     : 1;
2873	uint64_t m1_un_wi                     : 1;
2874	uint64_t mio_int0                     : 1;
2875	uint64_t mio_int1                     : 1;
2876	uint64_t mac0_int                     : 1;
2877	uint64_t mac1_int                     : 1;
2878	uint64_t m2_up_b0                     : 1;
2879	uint64_t m2_up_wi                     : 1;
2880	uint64_t m2_un_b0                     : 1;
2881	uint64_t m2_un_wi                     : 1;
2882	uint64_t m3_up_b0                     : 1;
2883	uint64_t m3_up_wi                     : 1;
2884	uint64_t m3_un_b0                     : 1;
2885	uint64_t m3_un_wi                     : 1;
2886	uint64_t reserved_28_31               : 4;
2887	uint64_t dmafi                        : 2;
2888	uint64_t dcnt                         : 2;
2889	uint64_t dtime                        : 2;
2890	uint64_t reserved_38_47               : 10;
2891	uint64_t pidbof                       : 1;
2892	uint64_t psldbof                      : 1;
2893	uint64_t pout_err                     : 1;
2894	uint64_t pin_bp                       : 1;
2895	uint64_t pgl_err                      : 1;
2896	uint64_t pdi_err                      : 1;
2897	uint64_t pop_err                      : 1;
2898	uint64_t pins_err                     : 1;
2899	uint64_t sprt0_err                    : 1;
2900	uint64_t sprt1_err                    : 1;
2901	uint64_t sprt2_err                    : 1;
2902	uint64_t sprt3_err                    : 1;
2903	uint64_t ill_pad                      : 1;
2904	uint64_t reserved_61_63               : 3;
2905#endif
2906	} cn61xx;
2907	struct cvmx_sli_int_sum_cn63xx {
2908#ifdef __BIG_ENDIAN_BITFIELD
2909	uint64_t reserved_61_63               : 3;
2910	uint64_t ill_pad                      : 1;  /**< Set when a BAR0 address R/W falls into theaddress
2911                                                         range of the Packet-CSR, but for an unused
2912                                                         address. */
2913	uint64_t reserved_58_59               : 2;
2914	uint64_t sprt1_err                    : 1;  /**< When an error response received on SLI port 1
2915                                                         this bit is set. */
2916	uint64_t sprt0_err                    : 1;  /**< When an error response received on SLI port 0
2917                                                         this bit is set. */
2918	uint64_t pins_err                     : 1;  /**< When a read error occurs on a packet instruction
2919                                                         this bit is set. */
2920	uint64_t pop_err                      : 1;  /**< When a read error occurs on a packet scatter
2921                                                         pointer pair this bit is set. */
2922	uint64_t pdi_err                      : 1;  /**< When a read error occurs on a packet data read
2923                                                         this bit is set. */
2924	uint64_t pgl_err                      : 1;  /**< When a read error occurs on a packet gather list
2925                                                         read this bit is set. */
2926	uint64_t pin_bp                       : 1;  /**< Packet input count has exceeded the WMARK.
2927                                                         See SLI_PKT_IN_BP */
2928	uint64_t pout_err                     : 1;  /**< Set when PKO sends packet data with the error bit
2929                                                         set. */
2930	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell count overflowed. Which
2931                                                         doorbell can be found in DPI_PINT_INFO[PSLDBOF] */
2932	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell count overflowed. Which
2933                                                         doorbell can be found in DPI_PINT_INFO[PIDBOF] */
2934	uint64_t reserved_38_47               : 10;
2935	uint64_t dtime                        : 2;  /**< Whenever SLI_DMAx_CNT[CNT] is not 0, the
2936                                                         SLI_DMAx_TIM[TIM] timer increments every SLI
2937                                                         clock.
2938                                                         DTIME[x] is set whenever SLI_DMAx_TIM[TIM] >
2939                                                         SLI_DMAx_INT_LEVEL[TIME].
2940                                                         DTIME[x] is normally cleared by clearing
2941                                                         SLI_DMAx_CNT[CNT] (which also clears
2942                                                         SLI_DMAx_TIM[TIM]). */
2943	uint64_t dcnt                         : 2;  /**< DCNT[x] is set whenever SLI_DMAx_CNT[CNT] >
2944                                                         SLI_DMAx_INT_LEVEL[CNT].
2945                                                         DCNT[x] is normally cleared by decreasing
2946                                                         SLI_DMAx_CNT[CNT]. */
2947	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts. */
2948	uint64_t reserved_20_31               : 12;
2949	uint64_t mac1_int                     : 1;  /**< Interrupt from MAC1.
2950                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB_INT) */
2951	uint64_t mac0_int                     : 1;  /**< Interrupt from MAC0.
2952                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB_INT) */
2953	uint64_t mio_int1                     : 1;  /**< Interrupt from MIO for PORT 1.
2954                                                         See CIU_INT33_SUM0, CIU_INT_SUM1
2955                                                         (enabled by CIU_INT33_EN0, CIU_INT33_EN1) */
2956	uint64_t mio_int0                     : 1;  /**< Interrupt from MIO for PORT 0.
2957                                                         See CIU_INT32_SUM0, CIU_INT_SUM1
2958                                                         (enabled by CIU_INT32_EN0, CIU_INT32_EN1) */
2959	uint64_t m1_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register
2960                                                         from MAC 1. This occurs when the window registers
2961                                                         are disabeld and a window register access occurs. */
2962	uint64_t m1_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0 from MAC 1.
2963                                                         This occurs when the BAR 0 address space is
2964                                                         disabeled. */
2965	uint64_t m1_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register
2966                                                         from MAC 1. This occurs when the window registers
2967                                                         are disabeld and a window register access occurs. */
2968	uint64_t m1_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0 from MAC 1.
2969                                                         This occurs when the BAR 0 address space is
2970                                                         disabeled. */
2971	uint64_t m0_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register
2972                                                         from MAC 0. This occurs when the window registers
2973                                                         are disabeld and a window register access occurs. */
2974	uint64_t m0_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0 from MAC 0.
2975                                                         This occurs when the BAR 0 address space is
2976                                                         disabeled. */
2977	uint64_t m0_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register
2978                                                         from MAC 0. This occurs when the window registers
2979                                                         are disabeld and a window register access occurs. */
2980	uint64_t m0_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0 from MAC 0.
2981                                                         This occurs when the BAR 0 address space is
2982                                                         disabeled. */
2983	uint64_t reserved_6_7                 : 2;
2984	uint64_t ptime                        : 1;  /**< Packet Timer has an interrupt. Which rings can
2985                                                         be found in SLI_PKT_TIME_INT. */
2986	uint64_t pcnt                         : 1;  /**< Packet Counter has an interrupt. Which rings can
2987                                                         be found in SLI_PKT_CNT_INT. */
2988	uint64_t iob2big                      : 1;  /**< A requested IOBDMA is to large. */
2989	uint64_t bar0_to                      : 1;  /**< BAR0 R/W to a NCB device did not receive
2990                                                         read-data/commit in 0xffff core clocks. */
2991	uint64_t reserved_1_1                 : 1;
2992	uint64_t rml_to                       : 1;  /**< A read or write transfer did not complete
2993                                                         within 0xffff core clocks. */
2994#else
2995	uint64_t rml_to                       : 1;
2996	uint64_t reserved_1_1                 : 1;
2997	uint64_t bar0_to                      : 1;
2998	uint64_t iob2big                      : 1;
2999	uint64_t pcnt                         : 1;
3000	uint64_t ptime                        : 1;
3001	uint64_t reserved_6_7                 : 2;
3002	uint64_t m0_up_b0                     : 1;
3003	uint64_t m0_up_wi                     : 1;
3004	uint64_t m0_un_b0                     : 1;
3005	uint64_t m0_un_wi                     : 1;
3006	uint64_t m1_up_b0                     : 1;
3007	uint64_t m1_up_wi                     : 1;
3008	uint64_t m1_un_b0                     : 1;
3009	uint64_t m1_un_wi                     : 1;
3010	uint64_t mio_int0                     : 1;
3011	uint64_t mio_int1                     : 1;
3012	uint64_t mac0_int                     : 1;
3013	uint64_t mac1_int                     : 1;
3014	uint64_t reserved_20_31               : 12;
3015	uint64_t dmafi                        : 2;
3016	uint64_t dcnt                         : 2;
3017	uint64_t dtime                        : 2;
3018	uint64_t reserved_38_47               : 10;
3019	uint64_t pidbof                       : 1;
3020	uint64_t psldbof                      : 1;
3021	uint64_t pout_err                     : 1;
3022	uint64_t pin_bp                       : 1;
3023	uint64_t pgl_err                      : 1;
3024	uint64_t pdi_err                      : 1;
3025	uint64_t pop_err                      : 1;
3026	uint64_t pins_err                     : 1;
3027	uint64_t sprt0_err                    : 1;
3028	uint64_t sprt1_err                    : 1;
3029	uint64_t reserved_58_59               : 2;
3030	uint64_t ill_pad                      : 1;
3031	uint64_t reserved_61_63               : 3;
3032#endif
3033	} cn63xx;
3034	struct cvmx_sli_int_sum_cn63xx        cn63xxp1;
3035	struct cvmx_sli_int_sum_cn61xx        cn66xx;
3036	struct cvmx_sli_int_sum_cn68xx {
3037#ifdef __BIG_ENDIAN_BITFIELD
3038	uint64_t reserved_62_63               : 2;
3039	uint64_t pipe_err                     : 1;  /**< Set when a PIPE value outside range is received. */
3040	uint64_t ill_pad                      : 1;  /**< Set when a BAR0 address R/W falls into theaddress
3041                                                         range of the Packet-CSR, but for an unused
3042                                                         address. */
3043	uint64_t reserved_58_59               : 2;
3044	uint64_t sprt1_err                    : 1;  /**< When an error response received on SLI port 1
3045                                                         this bit is set. */
3046	uint64_t sprt0_err                    : 1;  /**< When an error response received on SLI port 0
3047                                                         this bit is set. */
3048	uint64_t pins_err                     : 1;  /**< When a read error occurs on a packet instruction
3049                                                         this bit is set. */
3050	uint64_t pop_err                      : 1;  /**< When a read error occurs on a packet scatter
3051                                                         pointer pair this bit is set. */
3052	uint64_t pdi_err                      : 1;  /**< When a read error occurs on a packet data read
3053                                                         this bit is set. */
3054	uint64_t pgl_err                      : 1;  /**< When a read error occurs on a packet gather list
3055                                                         read this bit is set. */
3056	uint64_t reserved_51_51               : 1;
3057	uint64_t pout_err                     : 1;  /**< Set when PKO sends packet data with the error bit
3058                                                         set. */
3059	uint64_t psldbof                      : 1;  /**< Packet Scatterlist Doorbell count overflowed. Which
3060                                                         doorbell can be found in DPI_PINT_INFO[PSLDBOF] */
3061	uint64_t pidbof                       : 1;  /**< Packet Instruction Doorbell count overflowed. Which
3062                                                         doorbell can be found in DPI_PINT_INFO[PIDBOF] */
3063	uint64_t reserved_38_47               : 10;
3064	uint64_t dtime                        : 2;  /**< Whenever SLI_DMAx_CNT[CNT] is not 0, the
3065                                                         SLI_DMAx_TIM[TIM] timer increments every SLI
3066                                                         clock.
3067                                                         DTIME[x] is set whenever SLI_DMAx_TIM[TIM] >
3068                                                         SLI_DMAx_INT_LEVEL[TIME].
3069                                                         DTIME[x] is normally cleared by clearing
3070                                                         SLI_DMAx_CNT[CNT] (which also clears
3071                                                         SLI_DMAx_TIM[TIM]). */
3072	uint64_t dcnt                         : 2;  /**< DCNT[x] is set whenever SLI_DMAx_CNT[CNT] >
3073                                                         SLI_DMAx_INT_LEVEL[CNT].
3074                                                         DCNT[x] is normally cleared by decreasing
3075                                                         SLI_DMAx_CNT[CNT]. */
3076	uint64_t dmafi                        : 2;  /**< DMA set Forced Interrupts. */
3077	uint64_t reserved_20_31               : 12;
3078	uint64_t mac1_int                     : 1;  /**< Interrupt from MAC1.
3079                                                         See PEM1_INT_SUM (enabled by PEM1_INT_ENB_INT) */
3080	uint64_t mac0_int                     : 1;  /**< Interrupt from MAC0.
3081                                                         See PEM0_INT_SUM (enabled by PEM0_INT_ENB_INT) */
3082	uint64_t mio_int1                     : 1;  /**< Interrupt from MIO for PORT 1.
3083                                                         See CIU_INT33_SUM0, CIU_INT_SUM1
3084                                                         (enabled by CIU_INT33_EN0, CIU_INT33_EN1) */
3085	uint64_t mio_int0                     : 1;  /**< Interrupt from MIO for PORT 0.
3086                                                         See CIU_INT32_SUM0, CIU_INT_SUM1
3087                                                         (enabled by CIU_INT32_EN0, CIU_INT32_EN1) */
3088	uint64_t m1_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register
3089                                                         from MAC 1. This occurs when the window registers
3090                                                         are disabeld and a window register access occurs. */
3091	uint64_t m1_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0 from MAC 1.
3092                                                         This occurs when the BAR 0 address space is
3093                                                         disabeled. */
3094	uint64_t m1_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register
3095                                                         from MAC 1. This occurs when the window registers
3096                                                         are disabeld and a window register access occurs. */
3097	uint64_t m1_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0 from MAC 1.
3098                                                         This occurs when the BAR 0 address space is
3099                                                         disabeled. */
3100	uint64_t m0_un_wi                     : 1;  /**< Received Unsupported N-TLP for Window Register
3101                                                         from MAC 0. This occurs when the window registers
3102                                                         are disabeld and a window register access occurs. */
3103	uint64_t m0_un_b0                     : 1;  /**< Received Unsupported N-TLP for Bar0 from MAC 0.
3104                                                         This occurs when the BAR 0 address space is
3105                                                         disabeled. */
3106	uint64_t m0_up_wi                     : 1;  /**< Received Unsupported P-TLP for Window Register
3107                                                         from MAC 0. This occurs when the window registers
3108                                                         are disabeld and a window register access occurs. */
3109	uint64_t m0_up_b0                     : 1;  /**< Received Unsupported P-TLP for Bar0 from MAC 0.
3110                                                         This occurs when the BAR 0 address space is
3111                                                         disabeled. */
3112	uint64_t reserved_6_7                 : 2;
3113	uint64_t ptime                        : 1;  /**< Packet Timer has an interrupt. Which rings can
3114                                                         be found in SLI_PKT_TIME_INT. */
3115	uint64_t pcnt                         : 1;  /**< Packet Counter has an interrupt. Which rings can
3116                                                         be found in SLI_PKT_CNT_INT. */
3117	uint64_t iob2big                      : 1;  /**< A requested IOBDMA is to large. */
3118	uint64_t bar0_to                      : 1;  /**< BAR0 R/W to a NCB device did not receive
3119                                                         read-data/commit in 0xffff core clocks. */
3120	uint64_t reserved_1_1                 : 1;
3121	uint64_t rml_to                       : 1;  /**< A read or write transfer did not complete
3122                                                         within 0xffff core clocks. */
3123#else
3124	uint64_t rml_to                       : 1;
3125	uint64_t reserved_1_1                 : 1;
3126	uint64_t bar0_to                      : 1;
3127	uint64_t iob2big                      : 1;
3128	uint64_t pcnt                         : 1;
3129	uint64_t ptime                        : 1;
3130	uint64_t reserved_6_7                 : 2;
3131	uint64_t m0_up_b0                     : 1;
3132	uint64_t m0_up_wi                     : 1;
3133	uint64_t m0_un_b0                     : 1;
3134	uint64_t m0_un_wi                     : 1;
3135	uint64_t m1_up_b0                     : 1;
3136	uint64_t m1_up_wi                     : 1;
3137	uint64_t m1_un_b0                     : 1;
3138	uint64_t m1_un_wi                     : 1;
3139	uint64_t mio_int0                     : 1;
3140	uint64_t mio_int1                     : 1;
3141	uint64_t mac0_int                     : 1;
3142	uint64_t mac1_int                     : 1;
3143	uint64_t reserved_20_31               : 12;
3144	uint64_t dmafi                        : 2;
3145	uint64_t dcnt                         : 2;
3146	uint64_t dtime                        : 2;
3147	uint64_t reserved_38_47               : 10;
3148	uint64_t pidbof                       : 1;
3149	uint64_t psldbof                      : 1;
3150	uint64_t pout_err                     : 1;
3151	uint64_t reserved_51_51               : 1;
3152	uint64_t pgl_err                      : 1;
3153	uint64_t pdi_err                      : 1;
3154	uint64_t pop_err                      : 1;
3155	uint64_t pins_err                     : 1;
3156	uint64_t sprt0_err                    : 1;
3157	uint64_t sprt1_err                    : 1;
3158	uint64_t reserved_58_59               : 2;
3159	uint64_t ill_pad                      : 1;
3160	uint64_t pipe_err                     : 1;
3161	uint64_t reserved_62_63               : 2;
3162#endif
3163	} cn68xx;
3164	struct cvmx_sli_int_sum_cn68xx        cn68xxp1;
3165	struct cvmx_sli_int_sum_cn61xx        cnf71xx;
3166};
3167typedef union cvmx_sli_int_sum cvmx_sli_int_sum_t;
3168
3169/**
3170 * cvmx_sli_last_win_rdata0
3171 *
3172 * SLI_LAST_WIN_RDATA0 = SLI Last Window Read Data
3173 *
3174 * The data from the last initiated window read by MAC 0.
3175 */
3176union cvmx_sli_last_win_rdata0 {
3177	uint64_t u64;
3178	struct cvmx_sli_last_win_rdata0_s {
3179#ifdef __BIG_ENDIAN_BITFIELD
3180	uint64_t data                         : 64; /**< Last window read data. */
3181#else
3182	uint64_t data                         : 64;
3183#endif
3184	} s;
3185	struct cvmx_sli_last_win_rdata0_s     cn61xx;
3186	struct cvmx_sli_last_win_rdata0_s     cn63xx;
3187	struct cvmx_sli_last_win_rdata0_s     cn63xxp1;
3188	struct cvmx_sli_last_win_rdata0_s     cn66xx;
3189	struct cvmx_sli_last_win_rdata0_s     cn68xx;
3190	struct cvmx_sli_last_win_rdata0_s     cn68xxp1;
3191	struct cvmx_sli_last_win_rdata0_s     cnf71xx;
3192};
3193typedef union cvmx_sli_last_win_rdata0 cvmx_sli_last_win_rdata0_t;
3194
3195/**
3196 * cvmx_sli_last_win_rdata1
3197 *
3198 * SLI_LAST_WIN_RDATA1 = SLI Last Window Read Data
3199 *
3200 * The data from the last initiated window read by MAC 1.
3201 */
3202union cvmx_sli_last_win_rdata1 {
3203	uint64_t u64;
3204	struct cvmx_sli_last_win_rdata1_s {
3205#ifdef __BIG_ENDIAN_BITFIELD
3206	uint64_t data                         : 64; /**< Last window read data. */
3207#else
3208	uint64_t data                         : 64;
3209#endif
3210	} s;
3211	struct cvmx_sli_last_win_rdata1_s     cn61xx;
3212	struct cvmx_sli_last_win_rdata1_s     cn63xx;
3213	struct cvmx_sli_last_win_rdata1_s     cn63xxp1;
3214	struct cvmx_sli_last_win_rdata1_s     cn66xx;
3215	struct cvmx_sli_last_win_rdata1_s     cn68xx;
3216	struct cvmx_sli_last_win_rdata1_s     cn68xxp1;
3217	struct cvmx_sli_last_win_rdata1_s     cnf71xx;
3218};
3219typedef union cvmx_sli_last_win_rdata1 cvmx_sli_last_win_rdata1_t;
3220
3221/**
3222 * cvmx_sli_last_win_rdata2
3223 *
3224 * SLI_LAST_WIN_RDATA2 = SLI Last Window Read Data
3225 *
3226 * The data from the last initiated window read by MAC 2.
3227 */
3228union cvmx_sli_last_win_rdata2 {
3229	uint64_t u64;
3230	struct cvmx_sli_last_win_rdata2_s {
3231#ifdef __BIG_ENDIAN_BITFIELD
3232	uint64_t data                         : 64; /**< Last window read data. */
3233#else
3234	uint64_t data                         : 64;
3235#endif
3236	} s;
3237	struct cvmx_sli_last_win_rdata2_s     cn61xx;
3238	struct cvmx_sli_last_win_rdata2_s     cn66xx;
3239	struct cvmx_sli_last_win_rdata2_s     cnf71xx;
3240};
3241typedef union cvmx_sli_last_win_rdata2 cvmx_sli_last_win_rdata2_t;
3242
3243/**
3244 * cvmx_sli_last_win_rdata3
3245 *
3246 * SLI_LAST_WIN_RDATA3 = SLI Last Window Read Data
3247 *
3248 * The data from the last initiated window read by MAC 3.
3249 */
3250union cvmx_sli_last_win_rdata3 {
3251	uint64_t u64;
3252	struct cvmx_sli_last_win_rdata3_s {
3253#ifdef __BIG_ENDIAN_BITFIELD
3254	uint64_t data                         : 64; /**< Last window read data. */
3255#else
3256	uint64_t data                         : 64;
3257#endif
3258	} s;
3259	struct cvmx_sli_last_win_rdata3_s     cn61xx;
3260	struct cvmx_sli_last_win_rdata3_s     cn66xx;
3261	struct cvmx_sli_last_win_rdata3_s     cnf71xx;
3262};
3263typedef union cvmx_sli_last_win_rdata3 cvmx_sli_last_win_rdata3_t;
3264
3265/**
3266 * cvmx_sli_mac_credit_cnt
3267 *
3268 * SLI_MAC_CREDIT_CNT = SLI MAC Credit Count
3269 *
3270 * Contains the number of credits for the MAC port FIFOs used by the SLI. This value needs to be set BEFORE S2M traffic
3271 * flow starts. A write to this register will cause the credit counts in the SLI for the MAC ports to be reset to the value
3272 * in this register.
3273 */
3274union cvmx_sli_mac_credit_cnt {
3275	uint64_t u64;
3276	struct cvmx_sli_mac_credit_cnt_s {
3277#ifdef __BIG_ENDIAN_BITFIELD
3278	uint64_t reserved_54_63               : 10;
3279	uint64_t p1_c_d                       : 1;  /**< When set does not allow writing of P1_CCNT. */
3280	uint64_t p1_n_d                       : 1;  /**< When set does not allow writing of P1_NCNT. */
3281	uint64_t p1_p_d                       : 1;  /**< When set does not allow writing of P1_PCNT. */
3282	uint64_t p0_c_d                       : 1;  /**< When set does not allow writing of P0_CCNT. */
3283	uint64_t p0_n_d                       : 1;  /**< When set does not allow writing of P0_NCNT. */
3284	uint64_t p0_p_d                       : 1;  /**< When set does not allow writing of P0_PCNT. */
3285	uint64_t p1_ccnt                      : 8;  /**< Port1 C-TLP FIFO Credits.
3286                                                         Legal values are 0x25 to 0x80. */
3287	uint64_t p1_ncnt                      : 8;  /**< Port1 N-TLP FIFO Credits.
3288                                                         Legal values are 0x5 to 0x10. */
3289	uint64_t p1_pcnt                      : 8;  /**< Port1 P-TLP FIFO Credits.
3290                                                         Legal values are 0x25 to 0x80. */
3291	uint64_t p0_ccnt                      : 8;  /**< Port0 C-TLP FIFO Credits.
3292                                                         Legal values are 0x25 to 0x80. */
3293	uint64_t p0_ncnt                      : 8;  /**< Port0 N-TLP FIFO Credits.
3294                                                         Legal values are 0x5 to 0x10. */
3295	uint64_t p0_pcnt                      : 8;  /**< Port0 P-TLP FIFO Credits.
3296                                                         Legal values are 0x25 to 0x80. */
3297#else
3298	uint64_t p0_pcnt                      : 8;
3299	uint64_t p0_ncnt                      : 8;
3300	uint64_t p0_ccnt                      : 8;
3301	uint64_t p1_pcnt                      : 8;
3302	uint64_t p1_ncnt                      : 8;
3303	uint64_t p1_ccnt                      : 8;
3304	uint64_t p0_p_d                       : 1;
3305	uint64_t p0_n_d                       : 1;
3306	uint64_t p0_c_d                       : 1;
3307	uint64_t p1_p_d                       : 1;
3308	uint64_t p1_n_d                       : 1;
3309	uint64_t p1_c_d                       : 1;
3310	uint64_t reserved_54_63               : 10;
3311#endif
3312	} s;
3313	struct cvmx_sli_mac_credit_cnt_s      cn61xx;
3314	struct cvmx_sli_mac_credit_cnt_s      cn63xx;
3315	struct cvmx_sli_mac_credit_cnt_cn63xxp1 {
3316#ifdef __BIG_ENDIAN_BITFIELD
3317	uint64_t reserved_48_63               : 16;
3318	uint64_t p1_ccnt                      : 8;  /**< Port1 C-TLP FIFO Credits.
3319                                                         Legal values are 0x25 to 0x80. */
3320	uint64_t p1_ncnt                      : 8;  /**< Port1 N-TLP FIFO Credits.
3321                                                         Legal values are 0x5 to 0x10. */
3322	uint64_t p1_pcnt                      : 8;  /**< Port1 P-TLP FIFO Credits.
3323                                                         Legal values are 0x25 to 0x80. */
3324	uint64_t p0_ccnt                      : 8;  /**< Port0 C-TLP FIFO Credits.
3325                                                         Legal values are 0x25 to 0x80. */
3326	uint64_t p0_ncnt                      : 8;  /**< Port0 N-TLP FIFO Credits.
3327                                                         Legal values are 0x5 to 0x10. */
3328	uint64_t p0_pcnt                      : 8;  /**< Port0 P-TLP FIFO Credits.
3329                                                         Legal values are 0x25 to 0x80. */
3330#else
3331	uint64_t p0_pcnt                      : 8;
3332	uint64_t p0_ncnt                      : 8;
3333	uint64_t p0_ccnt                      : 8;
3334	uint64_t p1_pcnt                      : 8;
3335	uint64_t p1_ncnt                      : 8;
3336	uint64_t p1_ccnt                      : 8;
3337	uint64_t reserved_48_63               : 16;
3338#endif
3339	} cn63xxp1;
3340	struct cvmx_sli_mac_credit_cnt_s      cn66xx;
3341	struct cvmx_sli_mac_credit_cnt_s      cn68xx;
3342	struct cvmx_sli_mac_credit_cnt_s      cn68xxp1;
3343	struct cvmx_sli_mac_credit_cnt_s      cnf71xx;
3344};
3345typedef union cvmx_sli_mac_credit_cnt cvmx_sli_mac_credit_cnt_t;
3346
3347/**
3348 * cvmx_sli_mac_credit_cnt2
3349 *
3350 * SLI_MAC_CREDIT_CNT2 = SLI MAC Credit Count2
3351 *
3352 * Contains the number of credits for the MAC port FIFOs (for MACs 2 and 3) used by the SLI. This value needs to be set BEFORE S2M traffic
3353 * flow starts. A write to this register will cause the credit counts in the SLI for the MAC ports to be reset to the value
3354 * in this register.
3355 */
3356union cvmx_sli_mac_credit_cnt2 {
3357	uint64_t u64;
3358	struct cvmx_sli_mac_credit_cnt2_s {
3359#ifdef __BIG_ENDIAN_BITFIELD
3360	uint64_t reserved_54_63               : 10;
3361	uint64_t p3_c_d                       : 1;  /**< When set does not allow writing of P3_CCNT. */
3362	uint64_t p3_n_d                       : 1;  /**< When set does not allow writing of P3_NCNT. */
3363	uint64_t p3_p_d                       : 1;  /**< When set does not allow writing of P3_PCNT. */
3364	uint64_t p2_c_d                       : 1;  /**< When set does not allow writing of P2_CCNT. */
3365	uint64_t p2_n_d                       : 1;  /**< When set does not allow writing of P2_NCNT. */
3366	uint64_t p2_p_d                       : 1;  /**< When set does not allow writing of P2_PCNT. */
3367	uint64_t p3_ccnt                      : 8;  /**< Port3 C-TLP FIFO Credits.
3368                                                         Legal values are 0x25 to 0x80. */
3369	uint64_t p3_ncnt                      : 8;  /**< Port3 N-TLP FIFO Credits.
3370                                                         Legal values are 0x5 to 0x10. */
3371	uint64_t p3_pcnt                      : 8;  /**< Port3 P-TLP FIFO Credits.
3372                                                         Legal values are 0x25 to 0x80. */
3373	uint64_t p2_ccnt                      : 8;  /**< Port2 C-TLP FIFO Credits.
3374                                                         Legal values are 0x25 to 0x80. */
3375	uint64_t p2_ncnt                      : 8;  /**< Port2 N-TLP FIFO Credits.
3376                                                         Legal values are 0x5 to 0x10. */
3377	uint64_t p2_pcnt                      : 8;  /**< Port2 P-TLP FIFO Credits.
3378                                                         Legal values are 0x25 to 0x80. */
3379#else
3380	uint64_t p2_pcnt                      : 8;
3381	uint64_t p2_ncnt                      : 8;
3382	uint64_t p2_ccnt                      : 8;
3383	uint64_t p3_pcnt                      : 8;
3384	uint64_t p3_ncnt                      : 8;
3385	uint64_t p3_ccnt                      : 8;
3386	uint64_t p2_p_d                       : 1;
3387	uint64_t p2_n_d                       : 1;
3388	uint64_t p2_c_d                       : 1;
3389	uint64_t p3_p_d                       : 1;
3390	uint64_t p3_n_d                       : 1;
3391	uint64_t p3_c_d                       : 1;
3392	uint64_t reserved_54_63               : 10;
3393#endif
3394	} s;
3395	struct cvmx_sli_mac_credit_cnt2_s     cn61xx;
3396	struct cvmx_sli_mac_credit_cnt2_s     cn66xx;
3397	struct cvmx_sli_mac_credit_cnt2_s     cnf71xx;
3398};
3399typedef union cvmx_sli_mac_credit_cnt2 cvmx_sli_mac_credit_cnt2_t;
3400
3401/**
3402 * cvmx_sli_mac_number
3403 *
3404 * 0x13DA0 - 0x13DF0 reserved for ports 2 - 7
3405 *
3406 *                  SLI_MAC_NUMBER = SLI MAC Number
3407 *
3408 * When read from a MAC port it returns the MAC's port number.
3409 */
3410union cvmx_sli_mac_number {
3411	uint64_t u64;
3412	struct cvmx_sli_mac_number_s {
3413#ifdef __BIG_ENDIAN_BITFIELD
3414	uint64_t reserved_9_63                : 55;
3415	uint64_t a_mode                       : 1;  /**< SLI in Authenticate Mode. */
3416	uint64_t num                          : 8;  /**< The mac number. */
3417#else
3418	uint64_t num                          : 8;
3419	uint64_t a_mode                       : 1;
3420	uint64_t reserved_9_63                : 55;
3421#endif
3422	} s;
3423	struct cvmx_sli_mac_number_s          cn61xx;
3424	struct cvmx_sli_mac_number_cn63xx {
3425#ifdef __BIG_ENDIAN_BITFIELD
3426	uint64_t reserved_8_63                : 56;
3427	uint64_t num                          : 8;  /**< The mac number. */
3428#else
3429	uint64_t num                          : 8;
3430	uint64_t reserved_8_63                : 56;
3431#endif
3432	} cn63xx;
3433	struct cvmx_sli_mac_number_s          cn66xx;
3434	struct cvmx_sli_mac_number_cn63xx     cn68xx;
3435	struct cvmx_sli_mac_number_cn63xx     cn68xxp1;
3436	struct cvmx_sli_mac_number_s          cnf71xx;
3437};
3438typedef union cvmx_sli_mac_number cvmx_sli_mac_number_t;
3439
3440/**
3441 * cvmx_sli_mem_access_ctl
3442 *
3443 * SLI_MEM_ACCESS_CTL = SLI's Memory Access Control
3444 *
3445 * Contains control for access to the MAC address space.
3446 */
3447union cvmx_sli_mem_access_ctl {
3448	uint64_t u64;
3449	struct cvmx_sli_mem_access_ctl_s {
3450#ifdef __BIG_ENDIAN_BITFIELD
3451	uint64_t reserved_14_63               : 50;
3452	uint64_t max_word                     : 4;  /**< The maximum number of words to merge into a single
3453                                                         write operation from the PPs to the MAC. Legal
3454                                                         values are 1 to 16, where a '0' is treated as 16. */
3455	uint64_t timer                        : 10; /**< When the SLI starts a PP to MAC write it waits
3456                                                         no longer than the value of TIMER in eclks to
3457                                                         merge additional writes from the PPs into 1
3458                                                         large write. The values for this field is 1 to
3459                                                         1024 where a value of '0' is treated as 1024. */
3460#else
3461	uint64_t timer                        : 10;
3462	uint64_t max_word                     : 4;
3463	uint64_t reserved_14_63               : 50;
3464#endif
3465	} s;
3466	struct cvmx_sli_mem_access_ctl_s      cn61xx;
3467	struct cvmx_sli_mem_access_ctl_s      cn63xx;
3468	struct cvmx_sli_mem_access_ctl_s      cn63xxp1;
3469	struct cvmx_sli_mem_access_ctl_s      cn66xx;
3470	struct cvmx_sli_mem_access_ctl_s      cn68xx;
3471	struct cvmx_sli_mem_access_ctl_s      cn68xxp1;
3472	struct cvmx_sli_mem_access_ctl_s      cnf71xx;
3473};
3474typedef union cvmx_sli_mem_access_ctl cvmx_sli_mem_access_ctl_t;
3475
3476/**
3477 * cvmx_sli_mem_access_subid#
3478 *
3479 * // *
3480 * // * 8070 - 80C0 saved for ports 2 through 7
3481 * // *
3482 * // *
3483 * // * 0x80d0 free
3484 * // *
3485 *
3486 *                   SLI_MEM_ACCESS_SUBIDX = SLI Memory Access SubidX Register
3487 *
3488 *  Contains address index and control bits for access to memory from Core PPs.
3489 */
3490union cvmx_sli_mem_access_subidx {
3491	uint64_t u64;
3492	struct cvmx_sli_mem_access_subidx_s {
3493#ifdef __BIG_ENDIAN_BITFIELD
3494	uint64_t reserved_43_63               : 21;
3495	uint64_t zero                         : 1;  /**< Causes all byte reads to be zero length reads.
3496                                                         Returns to the EXEC a zero for all read data.
3497                                                         This must be zero for sRIO ports. */
3498	uint64_t port                         : 3;  /**< Physical MAC Port that reads/writes to
3499                                                         this subid are sent to. Must be <= 1, as there are
3500                                                         only two ports present. */
3501	uint64_t nmerge                       : 1;  /**< When set, no merging is allowed in this window. */
3502	uint64_t esr                          : 2;  /**< ES<1:0> for reads to this subid.
3503                                                         ES<1:0> is the endian-swap attribute for these MAC
3504                                                         memory space reads. */
3505	uint64_t esw                          : 2;  /**< ES<1:0> for writes to this subid.
3506                                                         ES<1:0> is the endian-swap attribute for these MAC
3507                                                         memory space writes. */
3508	uint64_t wtype                        : 2;  /**< ADDRTYPE<1:0> for writes to this subid
3509                                                         For PCIe:
3510                                                         - ADDRTYPE<0> is the relaxed-order attribute
3511                                                         - ADDRTYPE<1> is the no-snoop attribute
3512                                                         For sRIO:
3513                                                         - ADDRTYPE<1:0> help select an SRIO*_S2M_TYPE*
3514                                                           entry */
3515	uint64_t rtype                        : 2;  /**< ADDRTYPE<1:0> for reads to this subid
3516                                                         For PCIe:
3517                                                         - ADDRTYPE<0> is the relaxed-order attribute
3518                                                         - ADDRTYPE<1> is the no-snoop attribute
3519                                                         For sRIO:
3520                                                         - ADDRTYPE<1:0> help select an SRIO*_S2M_TYPE*
3521                                                           entry */
3522	uint64_t reserved_0_29                : 30;
3523#else
3524	uint64_t reserved_0_29                : 30;
3525	uint64_t rtype                        : 2;
3526	uint64_t wtype                        : 2;
3527	uint64_t esw                          : 2;
3528	uint64_t esr                          : 2;
3529	uint64_t nmerge                       : 1;
3530	uint64_t port                         : 3;
3531	uint64_t zero                         : 1;
3532	uint64_t reserved_43_63               : 21;
3533#endif
3534	} s;
3535	struct cvmx_sli_mem_access_subidx_cn61xx {
3536#ifdef __BIG_ENDIAN_BITFIELD
3537	uint64_t reserved_43_63               : 21;
3538	uint64_t zero                         : 1;  /**< Causes all byte reads to be zero length reads.
3539                                                         Returns to the EXEC a zero for all read data.
3540                                                         This must be zero for sRIO ports. */
3541	uint64_t port                         : 3;  /**< Physical MAC Port that reads/writes to
3542                                                         this subid are sent to. Must be <= 1, as there are
3543                                                         only two ports present. */
3544	uint64_t nmerge                       : 1;  /**< When set, no merging is allowed in this window. */
3545	uint64_t esr                          : 2;  /**< ES<1:0> for reads to this subid.
3546                                                         ES<1:0> is the endian-swap attribute for these MAC
3547                                                         memory space reads. */
3548	uint64_t esw                          : 2;  /**< ES<1:0> for writes to this subid.
3549                                                         ES<1:0> is the endian-swap attribute for these MAC
3550                                                         memory space writes. */
3551	uint64_t wtype                        : 2;  /**< ADDRTYPE<1:0> for writes to this subid
3552                                                         For PCIe:
3553                                                         - ADDRTYPE<0> is the relaxed-order attribute
3554                                                         - ADDRTYPE<1> is the no-snoop attribute
3555                                                         For sRIO:
3556                                                         - ADDRTYPE<1:0> help select an SRIO*_S2M_TYPE*
3557                                                           entry */
3558	uint64_t rtype                        : 2;  /**< ADDRTYPE<1:0> for reads to this subid
3559                                                         For PCIe:
3560                                                         - ADDRTYPE<0> is the relaxed-order attribute
3561                                                         - ADDRTYPE<1> is the no-snoop attribute
3562                                                         For sRIO:
3563                                                         - ADDRTYPE<1:0> help select an SRIO*_S2M_TYPE*
3564                                                           entry */
3565	uint64_t ba                           : 30; /**< Address Bits <63:34> for reads/writes that use
3566                                                         this subid. */
3567#else
3568	uint64_t ba                           : 30;
3569	uint64_t rtype                        : 2;
3570	uint64_t wtype                        : 2;
3571	uint64_t esw                          : 2;
3572	uint64_t esr                          : 2;
3573	uint64_t nmerge                       : 1;
3574	uint64_t port                         : 3;
3575	uint64_t zero                         : 1;
3576	uint64_t reserved_43_63               : 21;
3577#endif
3578	} cn61xx;
3579	struct cvmx_sli_mem_access_subidx_cn61xx cn63xx;
3580	struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1;
3581	struct cvmx_sli_mem_access_subidx_cn61xx cn66xx;
3582	struct cvmx_sli_mem_access_subidx_cn68xx {
3583#ifdef __BIG_ENDIAN_BITFIELD
3584	uint64_t reserved_43_63               : 21;
3585	uint64_t zero                         : 1;  /**< Causes all byte reads to be zero length reads.
3586                                                         Returns to the EXEC a zero for all read data.
3587                                                         This must be zero for sRIO ports. */
3588	uint64_t port                         : 3;  /**< Physical MAC Port that reads/writes to
3589                                                         this subid are sent to. Must be <= 1, as there are
3590                                                         only two ports present. */
3591	uint64_t nmerge                       : 1;  /**< When set, no merging is allowed in this window. */
3592	uint64_t esr                          : 2;  /**< ES<1:0> for reads to this subid.
3593                                                         ES<1:0> is the endian-swap attribute for these MAC
3594                                                         memory space reads. */
3595	uint64_t esw                          : 2;  /**< ES<1:0> for writes to this subid.
3596                                                         ES<1:0> is the endian-swap attribute for these MAC
3597                                                         memory space writes. */
3598	uint64_t wtype                        : 2;  /**< ADDRTYPE<1:0> for writes to this subid
3599                                                         For PCIe:
3600                                                         - ADDRTYPE<0> is the relaxed-order attribute
3601                                                         - ADDRTYPE<1> is the no-snoop attribute */
3602	uint64_t rtype                        : 2;  /**< ADDRTYPE<1:0> for reads to this subid
3603                                                         For PCIe:
3604                                                         - ADDRTYPE<0> is the relaxed-order attribute
3605                                                         - ADDRTYPE<1> is the no-snoop attribute */
3606	uint64_t ba                           : 28; /**< Address Bits <63:36> for reads/writes that use
3607                                                         this subid. */
3608	uint64_t reserved_0_1                 : 2;
3609#else
3610	uint64_t reserved_0_1                 : 2;
3611	uint64_t ba                           : 28;
3612	uint64_t rtype                        : 2;
3613	uint64_t wtype                        : 2;
3614	uint64_t esw                          : 2;
3615	uint64_t esr                          : 2;
3616	uint64_t nmerge                       : 1;
3617	uint64_t port                         : 3;
3618	uint64_t zero                         : 1;
3619	uint64_t reserved_43_63               : 21;
3620#endif
3621	} cn68xx;
3622	struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1;
3623	struct cvmx_sli_mem_access_subidx_cn61xx cnf71xx;
3624};
3625typedef union cvmx_sli_mem_access_subidx cvmx_sli_mem_access_subidx_t;
3626
3627/**
3628 * cvmx_sli_msi_enb0
3629 *
3630 * SLI_MSI_ENB0 = SLI MSI Enable0
3631 *
3632 * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV0.
3633 */
3634union cvmx_sli_msi_enb0 {
3635	uint64_t u64;
3636	struct cvmx_sli_msi_enb0_s {
3637#ifdef __BIG_ENDIAN_BITFIELD
3638	uint64_t enb                          : 64; /**< Enables bit [63:0] of SLI_MSI_RCV0. */
3639#else
3640	uint64_t enb                          : 64;
3641#endif
3642	} s;
3643	struct cvmx_sli_msi_enb0_s            cn61xx;
3644	struct cvmx_sli_msi_enb0_s            cn63xx;
3645	struct cvmx_sli_msi_enb0_s            cn63xxp1;
3646	struct cvmx_sli_msi_enb0_s            cn66xx;
3647	struct cvmx_sli_msi_enb0_s            cn68xx;
3648	struct cvmx_sli_msi_enb0_s            cn68xxp1;
3649	struct cvmx_sli_msi_enb0_s            cnf71xx;
3650};
3651typedef union cvmx_sli_msi_enb0 cvmx_sli_msi_enb0_t;
3652
3653/**
3654 * cvmx_sli_msi_enb1
3655 *
3656 * SLI_MSI_ENB1 = SLI MSI Enable1
3657 *
3658 * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV1.
3659 */
3660union cvmx_sli_msi_enb1 {
3661	uint64_t u64;
3662	struct cvmx_sli_msi_enb1_s {
3663#ifdef __BIG_ENDIAN_BITFIELD
3664	uint64_t enb                          : 64; /**< Enables bit [63:0] of SLI_MSI_RCV1. */
3665#else
3666	uint64_t enb                          : 64;
3667#endif
3668	} s;
3669	struct cvmx_sli_msi_enb1_s            cn61xx;
3670	struct cvmx_sli_msi_enb1_s            cn63xx;
3671	struct cvmx_sli_msi_enb1_s            cn63xxp1;
3672	struct cvmx_sli_msi_enb1_s            cn66xx;
3673	struct cvmx_sli_msi_enb1_s            cn68xx;
3674	struct cvmx_sli_msi_enb1_s            cn68xxp1;
3675	struct cvmx_sli_msi_enb1_s            cnf71xx;
3676};
3677typedef union cvmx_sli_msi_enb1 cvmx_sli_msi_enb1_t;
3678
3679/**
3680 * cvmx_sli_msi_enb2
3681 *
3682 * SLI_MSI_ENB2 = SLI MSI Enable2
3683 *
3684 * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV2.
3685 */
3686union cvmx_sli_msi_enb2 {
3687	uint64_t u64;
3688	struct cvmx_sli_msi_enb2_s {
3689#ifdef __BIG_ENDIAN_BITFIELD
3690	uint64_t enb                          : 64; /**< Enables bit [63:0] of SLI_MSI_RCV2. */
3691#else
3692	uint64_t enb                          : 64;
3693#endif
3694	} s;
3695	struct cvmx_sli_msi_enb2_s            cn61xx;
3696	struct cvmx_sli_msi_enb2_s            cn63xx;
3697	struct cvmx_sli_msi_enb2_s            cn63xxp1;
3698	struct cvmx_sli_msi_enb2_s            cn66xx;
3699	struct cvmx_sli_msi_enb2_s            cn68xx;
3700	struct cvmx_sli_msi_enb2_s            cn68xxp1;
3701	struct cvmx_sli_msi_enb2_s            cnf71xx;
3702};
3703typedef union cvmx_sli_msi_enb2 cvmx_sli_msi_enb2_t;
3704
3705/**
3706 * cvmx_sli_msi_enb3
3707 *
3708 * SLI_MSI_ENB3 = SLI MSI Enable3
3709 *
3710 * Used to enable the interrupt generation for the bits in the SLI_MSI_RCV3.
3711 */
3712union cvmx_sli_msi_enb3 {
3713	uint64_t u64;
3714	struct cvmx_sli_msi_enb3_s {
3715#ifdef __BIG_ENDIAN_BITFIELD
3716	uint64_t enb                          : 64; /**< Enables bit [63:0] of SLI_MSI_RCV3. */
3717#else
3718	uint64_t enb                          : 64;
3719#endif
3720	} s;
3721	struct cvmx_sli_msi_enb3_s            cn61xx;
3722	struct cvmx_sli_msi_enb3_s            cn63xx;
3723	struct cvmx_sli_msi_enb3_s            cn63xxp1;
3724	struct cvmx_sli_msi_enb3_s            cn66xx;
3725	struct cvmx_sli_msi_enb3_s            cn68xx;
3726	struct cvmx_sli_msi_enb3_s            cn68xxp1;
3727	struct cvmx_sli_msi_enb3_s            cnf71xx;
3728};
3729typedef union cvmx_sli_msi_enb3 cvmx_sli_msi_enb3_t;
3730
3731/**
3732 * cvmx_sli_msi_rcv0
3733 *
3734 * SLI_MSI_RCV0 = SLI MSI Receive0
3735 *
3736 * Contains bits [63:0] of the 256 bits of MSI interrupts.
3737 */
3738union cvmx_sli_msi_rcv0 {
3739	uint64_t u64;
3740	struct cvmx_sli_msi_rcv0_s {
3741#ifdef __BIG_ENDIAN_BITFIELD
3742	uint64_t intr                         : 64; /**< Bits 63-0 of the 256 bits of MSI interrupt. */
3743#else
3744	uint64_t intr                         : 64;
3745#endif
3746	} s;
3747	struct cvmx_sli_msi_rcv0_s            cn61xx;
3748	struct cvmx_sli_msi_rcv0_s            cn63xx;
3749	struct cvmx_sli_msi_rcv0_s            cn63xxp1;
3750	struct cvmx_sli_msi_rcv0_s            cn66xx;
3751	struct cvmx_sli_msi_rcv0_s            cn68xx;
3752	struct cvmx_sli_msi_rcv0_s            cn68xxp1;
3753	struct cvmx_sli_msi_rcv0_s            cnf71xx;
3754};
3755typedef union cvmx_sli_msi_rcv0 cvmx_sli_msi_rcv0_t;
3756
3757/**
3758 * cvmx_sli_msi_rcv1
3759 *
3760 * SLI_MSI_RCV1 = SLI MSI Receive1
3761 *
3762 * Contains bits [127:64] of the 256 bits of MSI interrupts.
3763 */
3764union cvmx_sli_msi_rcv1 {
3765	uint64_t u64;
3766	struct cvmx_sli_msi_rcv1_s {
3767#ifdef __BIG_ENDIAN_BITFIELD
3768	uint64_t intr                         : 64; /**< Bits 127-64 of the 256 bits of MSI interrupt. */
3769#else
3770	uint64_t intr                         : 64;
3771#endif
3772	} s;
3773	struct cvmx_sli_msi_rcv1_s            cn61xx;
3774	struct cvmx_sli_msi_rcv1_s            cn63xx;
3775	struct cvmx_sli_msi_rcv1_s            cn63xxp1;
3776	struct cvmx_sli_msi_rcv1_s            cn66xx;
3777	struct cvmx_sli_msi_rcv1_s            cn68xx;
3778	struct cvmx_sli_msi_rcv1_s            cn68xxp1;
3779	struct cvmx_sli_msi_rcv1_s            cnf71xx;
3780};
3781typedef union cvmx_sli_msi_rcv1 cvmx_sli_msi_rcv1_t;
3782
3783/**
3784 * cvmx_sli_msi_rcv2
3785 *
3786 * SLI_MSI_RCV2 = SLI MSI Receive2
3787 *
3788 * Contains bits [191:128] of the 256 bits of MSI interrupts.
3789 */
3790union cvmx_sli_msi_rcv2 {
3791	uint64_t u64;
3792	struct cvmx_sli_msi_rcv2_s {
3793#ifdef __BIG_ENDIAN_BITFIELD
3794	uint64_t intr                         : 64; /**< Bits 191-128 of the 256 bits of MSI interrupt. */
3795#else
3796	uint64_t intr                         : 64;
3797#endif
3798	} s;
3799	struct cvmx_sli_msi_rcv2_s            cn61xx;
3800	struct cvmx_sli_msi_rcv2_s            cn63xx;
3801	struct cvmx_sli_msi_rcv2_s            cn63xxp1;
3802	struct cvmx_sli_msi_rcv2_s            cn66xx;
3803	struct cvmx_sli_msi_rcv2_s            cn68xx;
3804	struct cvmx_sli_msi_rcv2_s            cn68xxp1;
3805	struct cvmx_sli_msi_rcv2_s            cnf71xx;
3806};
3807typedef union cvmx_sli_msi_rcv2 cvmx_sli_msi_rcv2_t;
3808
3809/**
3810 * cvmx_sli_msi_rcv3
3811 *
3812 * SLI_MSI_RCV3 = SLI MSI Receive3
3813 *
3814 * Contains bits [255:192] of the 256 bits of MSI interrupts.
3815 */
3816union cvmx_sli_msi_rcv3 {
3817	uint64_t u64;
3818	struct cvmx_sli_msi_rcv3_s {
3819#ifdef __BIG_ENDIAN_BITFIELD
3820	uint64_t intr                         : 64; /**< Bits 255-192 of the 256 bits of MSI interrupt. */
3821#else
3822	uint64_t intr                         : 64;
3823#endif
3824	} s;
3825	struct cvmx_sli_msi_rcv3_s            cn61xx;
3826	struct cvmx_sli_msi_rcv3_s            cn63xx;
3827	struct cvmx_sli_msi_rcv3_s            cn63xxp1;
3828	struct cvmx_sli_msi_rcv3_s            cn66xx;
3829	struct cvmx_sli_msi_rcv3_s            cn68xx;
3830	struct cvmx_sli_msi_rcv3_s            cn68xxp1;
3831	struct cvmx_sli_msi_rcv3_s            cnf71xx;
3832};
3833typedef union cvmx_sli_msi_rcv3 cvmx_sli_msi_rcv3_t;
3834
3835/**
3836 * cvmx_sli_msi_rd_map
3837 *
3838 * SLI_MSI_RD_MAP = SLI MSI Read MAP
3839 *
3840 * Used to read the mapping function of the SLI_PCIE_MSI_RCV to SLI_MSI_RCV registers.
3841 */
3842union cvmx_sli_msi_rd_map {
3843	uint64_t u64;
3844	struct cvmx_sli_msi_rd_map_s {
3845#ifdef __BIG_ENDIAN_BITFIELD
3846	uint64_t reserved_16_63               : 48;
3847	uint64_t rd_int                       : 8;  /**< The value of the map at the location PREVIOUSLY
3848                                                         written to the MSI_INT field of this register. */
3849	uint64_t msi_int                      : 8;  /**< Selects the value that would be received when the
3850                                                         SLI_PCIE_MSI_RCV register is written. */
3851#else
3852	uint64_t msi_int                      : 8;
3853	uint64_t rd_int                       : 8;
3854	uint64_t reserved_16_63               : 48;
3855#endif
3856	} s;
3857	struct cvmx_sli_msi_rd_map_s          cn61xx;
3858	struct cvmx_sli_msi_rd_map_s          cn63xx;
3859	struct cvmx_sli_msi_rd_map_s          cn63xxp1;
3860	struct cvmx_sli_msi_rd_map_s          cn66xx;
3861	struct cvmx_sli_msi_rd_map_s          cn68xx;
3862	struct cvmx_sli_msi_rd_map_s          cn68xxp1;
3863	struct cvmx_sli_msi_rd_map_s          cnf71xx;
3864};
3865typedef union cvmx_sli_msi_rd_map cvmx_sli_msi_rd_map_t;
3866
3867/**
3868 * cvmx_sli_msi_w1c_enb0
3869 *
3870 * SLI_MSI_W1C_ENB0 = SLI MSI Write 1 To Clear Enable0
3871 *
3872 * Used to clear bits in SLI_MSI_ENB0.
3873 */
3874union cvmx_sli_msi_w1c_enb0 {
3875	uint64_t u64;
3876	struct cvmx_sli_msi_w1c_enb0_s {
3877#ifdef __BIG_ENDIAN_BITFIELD
3878	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
3879                                                         cooresponding bit in SLI_MSI_ENB0.
3880                                                         A read to this address will return 0. */
3881#else
3882	uint64_t clr                          : 64;
3883#endif
3884	} s;
3885	struct cvmx_sli_msi_w1c_enb0_s        cn61xx;
3886	struct cvmx_sli_msi_w1c_enb0_s        cn63xx;
3887	struct cvmx_sli_msi_w1c_enb0_s        cn63xxp1;
3888	struct cvmx_sli_msi_w1c_enb0_s        cn66xx;
3889	struct cvmx_sli_msi_w1c_enb0_s        cn68xx;
3890	struct cvmx_sli_msi_w1c_enb0_s        cn68xxp1;
3891	struct cvmx_sli_msi_w1c_enb0_s        cnf71xx;
3892};
3893typedef union cvmx_sli_msi_w1c_enb0 cvmx_sli_msi_w1c_enb0_t;
3894
3895/**
3896 * cvmx_sli_msi_w1c_enb1
3897 *
3898 * SLI_MSI_W1C_ENB1 = SLI MSI Write 1 To Clear Enable1
3899 *
3900 * Used to clear bits in SLI_MSI_ENB1.
3901 */
3902union cvmx_sli_msi_w1c_enb1 {
3903	uint64_t u64;
3904	struct cvmx_sli_msi_w1c_enb1_s {
3905#ifdef __BIG_ENDIAN_BITFIELD
3906	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
3907                                                         cooresponding bit in SLI_MSI_ENB1.
3908                                                         A read to this address will return 0. */
3909#else
3910	uint64_t clr                          : 64;
3911#endif
3912	} s;
3913	struct cvmx_sli_msi_w1c_enb1_s        cn61xx;
3914	struct cvmx_sli_msi_w1c_enb1_s        cn63xx;
3915	struct cvmx_sli_msi_w1c_enb1_s        cn63xxp1;
3916	struct cvmx_sli_msi_w1c_enb1_s        cn66xx;
3917	struct cvmx_sli_msi_w1c_enb1_s        cn68xx;
3918	struct cvmx_sli_msi_w1c_enb1_s        cn68xxp1;
3919	struct cvmx_sli_msi_w1c_enb1_s        cnf71xx;
3920};
3921typedef union cvmx_sli_msi_w1c_enb1 cvmx_sli_msi_w1c_enb1_t;
3922
3923/**
3924 * cvmx_sli_msi_w1c_enb2
3925 *
3926 * SLI_MSI_W1C_ENB2 = SLI MSI Write 1 To Clear Enable2
3927 *
3928 * Used to clear bits in SLI_MSI_ENB2.
3929 */
3930union cvmx_sli_msi_w1c_enb2 {
3931	uint64_t u64;
3932	struct cvmx_sli_msi_w1c_enb2_s {
3933#ifdef __BIG_ENDIAN_BITFIELD
3934	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
3935                                                         cooresponding bit in SLI_MSI_ENB2.
3936                                                         A read to this address will return 0. */
3937#else
3938	uint64_t clr                          : 64;
3939#endif
3940	} s;
3941	struct cvmx_sli_msi_w1c_enb2_s        cn61xx;
3942	struct cvmx_sli_msi_w1c_enb2_s        cn63xx;
3943	struct cvmx_sli_msi_w1c_enb2_s        cn63xxp1;
3944	struct cvmx_sli_msi_w1c_enb2_s        cn66xx;
3945	struct cvmx_sli_msi_w1c_enb2_s        cn68xx;
3946	struct cvmx_sli_msi_w1c_enb2_s        cn68xxp1;
3947	struct cvmx_sli_msi_w1c_enb2_s        cnf71xx;
3948};
3949typedef union cvmx_sli_msi_w1c_enb2 cvmx_sli_msi_w1c_enb2_t;
3950
3951/**
3952 * cvmx_sli_msi_w1c_enb3
3953 *
3954 * SLI_MSI_W1C_ENB3 = SLI MSI Write 1 To Clear Enable3
3955 *
3956 * Used to clear bits in SLI_MSI_ENB3.
3957 */
3958union cvmx_sli_msi_w1c_enb3 {
3959	uint64_t u64;
3960	struct cvmx_sli_msi_w1c_enb3_s {
3961#ifdef __BIG_ENDIAN_BITFIELD
3962	uint64_t clr                          : 64; /**< A write of '1' to a vector will clear the
3963                                                         cooresponding bit in SLI_MSI_ENB3.
3964                                                         A read to this address will return 0. */
3965#else
3966	uint64_t clr                          : 64;
3967#endif
3968	} s;
3969	struct cvmx_sli_msi_w1c_enb3_s        cn61xx;
3970	struct cvmx_sli_msi_w1c_enb3_s        cn63xx;
3971	struct cvmx_sli_msi_w1c_enb3_s        cn63xxp1;
3972	struct cvmx_sli_msi_w1c_enb3_s        cn66xx;
3973	struct cvmx_sli_msi_w1c_enb3_s        cn68xx;
3974	struct cvmx_sli_msi_w1c_enb3_s        cn68xxp1;
3975	struct cvmx_sli_msi_w1c_enb3_s        cnf71xx;
3976};
3977typedef union cvmx_sli_msi_w1c_enb3 cvmx_sli_msi_w1c_enb3_t;
3978
3979/**
3980 * cvmx_sli_msi_w1s_enb0
3981 *
3982 * SLI_MSI_W1S_ENB0 = SLI MSI Write 1 To Set Enable0
3983 *
3984 * Used to set bits in SLI_MSI_ENB0.
3985 */
3986union cvmx_sli_msi_w1s_enb0 {
3987	uint64_t u64;
3988	struct cvmx_sli_msi_w1s_enb0_s {
3989#ifdef __BIG_ENDIAN_BITFIELD
3990	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
3991                                                         cooresponding bit in SLI_MSI_ENB0.
3992                                                         A read to this address will return 0. */
3993#else
3994	uint64_t set                          : 64;
3995#endif
3996	} s;
3997	struct cvmx_sli_msi_w1s_enb0_s        cn61xx;
3998	struct cvmx_sli_msi_w1s_enb0_s        cn63xx;
3999	struct cvmx_sli_msi_w1s_enb0_s        cn63xxp1;
4000	struct cvmx_sli_msi_w1s_enb0_s        cn66xx;
4001	struct cvmx_sli_msi_w1s_enb0_s        cn68xx;
4002	struct cvmx_sli_msi_w1s_enb0_s        cn68xxp1;
4003	struct cvmx_sli_msi_w1s_enb0_s        cnf71xx;
4004};
4005typedef union cvmx_sli_msi_w1s_enb0 cvmx_sli_msi_w1s_enb0_t;
4006
4007/**
4008 * cvmx_sli_msi_w1s_enb1
4009 *
4010 * SLI_MSI_W1S_ENB0 = SLI MSI Write 1 To Set Enable1
4011 *
4012 * Used to set bits in SLI_MSI_ENB1.
4013 */
4014union cvmx_sli_msi_w1s_enb1 {
4015	uint64_t u64;
4016	struct cvmx_sli_msi_w1s_enb1_s {
4017#ifdef __BIG_ENDIAN_BITFIELD
4018	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
4019                                                         cooresponding bit in SLI_MSI_ENB1.
4020                                                         A read to this address will return 0. */
4021#else
4022	uint64_t set                          : 64;
4023#endif
4024	} s;
4025	struct cvmx_sli_msi_w1s_enb1_s        cn61xx;
4026	struct cvmx_sli_msi_w1s_enb1_s        cn63xx;
4027	struct cvmx_sli_msi_w1s_enb1_s        cn63xxp1;
4028	struct cvmx_sli_msi_w1s_enb1_s        cn66xx;
4029	struct cvmx_sli_msi_w1s_enb1_s        cn68xx;
4030	struct cvmx_sli_msi_w1s_enb1_s        cn68xxp1;
4031	struct cvmx_sli_msi_w1s_enb1_s        cnf71xx;
4032};
4033typedef union cvmx_sli_msi_w1s_enb1 cvmx_sli_msi_w1s_enb1_t;
4034
4035/**
4036 * cvmx_sli_msi_w1s_enb2
4037 *
4038 * SLI_MSI_W1S_ENB2 = SLI MSI Write 1 To Set Enable2
4039 *
4040 * Used to set bits in SLI_MSI_ENB2.
4041 */
4042union cvmx_sli_msi_w1s_enb2 {
4043	uint64_t u64;
4044	struct cvmx_sli_msi_w1s_enb2_s {
4045#ifdef __BIG_ENDIAN_BITFIELD
4046	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
4047                                                         cooresponding bit in SLI_MSI_ENB2.
4048                                                         A read to this address will return 0. */
4049#else
4050	uint64_t set                          : 64;
4051#endif
4052	} s;
4053	struct cvmx_sli_msi_w1s_enb2_s        cn61xx;
4054	struct cvmx_sli_msi_w1s_enb2_s        cn63xx;
4055	struct cvmx_sli_msi_w1s_enb2_s        cn63xxp1;
4056	struct cvmx_sli_msi_w1s_enb2_s        cn66xx;
4057	struct cvmx_sli_msi_w1s_enb2_s        cn68xx;
4058	struct cvmx_sli_msi_w1s_enb2_s        cn68xxp1;
4059	struct cvmx_sli_msi_w1s_enb2_s        cnf71xx;
4060};
4061typedef union cvmx_sli_msi_w1s_enb2 cvmx_sli_msi_w1s_enb2_t;
4062
4063/**
4064 * cvmx_sli_msi_w1s_enb3
4065 *
4066 * SLI_MSI_W1S_ENB3 = SLI MSI Write 1 To Set Enable3
4067 *
4068 * Used to set bits in SLI_MSI_ENB3.
4069 */
4070union cvmx_sli_msi_w1s_enb3 {
4071	uint64_t u64;
4072	struct cvmx_sli_msi_w1s_enb3_s {
4073#ifdef __BIG_ENDIAN_BITFIELD
4074	uint64_t set                          : 64; /**< A write of '1' to a vector will set the
4075                                                         cooresponding bit in SLI_MSI_ENB3.
4076                                                         A read to this address will return 0. */
4077#else
4078	uint64_t set                          : 64;
4079#endif
4080	} s;
4081	struct cvmx_sli_msi_w1s_enb3_s        cn61xx;
4082	struct cvmx_sli_msi_w1s_enb3_s        cn63xx;
4083	struct cvmx_sli_msi_w1s_enb3_s        cn63xxp1;
4084	struct cvmx_sli_msi_w1s_enb3_s        cn66xx;
4085	struct cvmx_sli_msi_w1s_enb3_s        cn68xx;
4086	struct cvmx_sli_msi_w1s_enb3_s        cn68xxp1;
4087	struct cvmx_sli_msi_w1s_enb3_s        cnf71xx;
4088};
4089typedef union cvmx_sli_msi_w1s_enb3 cvmx_sli_msi_w1s_enb3_t;
4090
4091/**
4092 * cvmx_sli_msi_wr_map
4093 *
4094 * SLI_MSI_WR_MAP = SLI MSI Write MAP
4095 *
4096 * Used to write the mapping function of the SLI_PCIE_MSI_RCV to SLI_MSI_RCV registers.
4097 */
4098union cvmx_sli_msi_wr_map {
4099	uint64_t u64;
4100	struct cvmx_sli_msi_wr_map_s {
4101#ifdef __BIG_ENDIAN_BITFIELD
4102	uint64_t reserved_16_63               : 48;
4103	uint64_t ciu_int                      : 8;  /**< Selects which bit in the SLI_MSI_RCV# (0-255)
4104                                                         will be set when the value specified in the
4105                                                         MSI_INT of this register is recevied during a
4106                                                         write to the SLI_PCIE_MSI_RCV register. */
4107	uint64_t msi_int                      : 8;  /**< Selects the value that would be received when the
4108                                                         SLI_PCIE_MSI_RCV register is written. */
4109#else
4110	uint64_t msi_int                      : 8;
4111	uint64_t ciu_int                      : 8;
4112	uint64_t reserved_16_63               : 48;
4113#endif
4114	} s;
4115	struct cvmx_sli_msi_wr_map_s          cn61xx;
4116	struct cvmx_sli_msi_wr_map_s          cn63xx;
4117	struct cvmx_sli_msi_wr_map_s          cn63xxp1;
4118	struct cvmx_sli_msi_wr_map_s          cn66xx;
4119	struct cvmx_sli_msi_wr_map_s          cn68xx;
4120	struct cvmx_sli_msi_wr_map_s          cn68xxp1;
4121	struct cvmx_sli_msi_wr_map_s          cnf71xx;
4122};
4123typedef union cvmx_sli_msi_wr_map cvmx_sli_msi_wr_map_t;
4124
4125/**
4126 * cvmx_sli_pcie_msi_rcv
4127 *
4128 * SLI_PCIE_MSI_RCV = SLI MAC MSI Receive
4129 *
4130 * Register where MSI writes are directed from the MAC.
4131 */
4132union cvmx_sli_pcie_msi_rcv {
4133	uint64_t u64;
4134	struct cvmx_sli_pcie_msi_rcv_s {
4135#ifdef __BIG_ENDIAN_BITFIELD
4136	uint64_t reserved_8_63                : 56;
4137	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
4138                                                         one of the SLI_MSI_RCV# registers being set.
4139                                                         Which bit is set is dependent on the previously
4140                                                         written using the SLI_MSI_WR_MAP register or if
4141                                                         not previously written the reset value of the MAP. */
4142#else
4143	uint64_t intr                         : 8;
4144	uint64_t reserved_8_63                : 56;
4145#endif
4146	} s;
4147	struct cvmx_sli_pcie_msi_rcv_s        cn61xx;
4148	struct cvmx_sli_pcie_msi_rcv_s        cn63xx;
4149	struct cvmx_sli_pcie_msi_rcv_s        cn63xxp1;
4150	struct cvmx_sli_pcie_msi_rcv_s        cn66xx;
4151	struct cvmx_sli_pcie_msi_rcv_s        cn68xx;
4152	struct cvmx_sli_pcie_msi_rcv_s        cn68xxp1;
4153	struct cvmx_sli_pcie_msi_rcv_s        cnf71xx;
4154};
4155typedef union cvmx_sli_pcie_msi_rcv cvmx_sli_pcie_msi_rcv_t;
4156
4157/**
4158 * cvmx_sli_pcie_msi_rcv_b1
4159 *
4160 * SLI_PCIE_MSI_RCV_B1 = SLI MAC MSI Receive Byte 1
4161 *
4162 * Register where MSI writes are directed from the MAC.
4163 *
4164 * Notes:
4165 * This CSR can be used by PCIe and sRIO MACs.
4166 *
4167 */
4168union cvmx_sli_pcie_msi_rcv_b1 {
4169	uint64_t u64;
4170	struct cvmx_sli_pcie_msi_rcv_b1_s {
4171#ifdef __BIG_ENDIAN_BITFIELD
4172	uint64_t reserved_16_63               : 48;
4173	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
4174                                                         one of the SLI_MSI_RCV# registers being set.
4175                                                         Which bit is set is dependent on the previously
4176                                                         written using the SLI_MSI_WR_MAP register or if
4177                                                         not previously written the reset value of the MAP. */
4178	uint64_t reserved_0_7                 : 8;
4179#else
4180	uint64_t reserved_0_7                 : 8;
4181	uint64_t intr                         : 8;
4182	uint64_t reserved_16_63               : 48;
4183#endif
4184	} s;
4185	struct cvmx_sli_pcie_msi_rcv_b1_s     cn61xx;
4186	struct cvmx_sli_pcie_msi_rcv_b1_s     cn63xx;
4187	struct cvmx_sli_pcie_msi_rcv_b1_s     cn63xxp1;
4188	struct cvmx_sli_pcie_msi_rcv_b1_s     cn66xx;
4189	struct cvmx_sli_pcie_msi_rcv_b1_s     cn68xx;
4190	struct cvmx_sli_pcie_msi_rcv_b1_s     cn68xxp1;
4191	struct cvmx_sli_pcie_msi_rcv_b1_s     cnf71xx;
4192};
4193typedef union cvmx_sli_pcie_msi_rcv_b1 cvmx_sli_pcie_msi_rcv_b1_t;
4194
4195/**
4196 * cvmx_sli_pcie_msi_rcv_b2
4197 *
4198 * SLI_PCIE_MSI_RCV_B2 = SLI MAC MSI Receive Byte 2
4199 *
4200 * Register where MSI writes are directed from the MAC.
4201 *
4202 * Notes:
4203 * This CSR can be used by PCIe and sRIO MACs.
4204 *
4205 */
4206union cvmx_sli_pcie_msi_rcv_b2 {
4207	uint64_t u64;
4208	struct cvmx_sli_pcie_msi_rcv_b2_s {
4209#ifdef __BIG_ENDIAN_BITFIELD
4210	uint64_t reserved_24_63               : 40;
4211	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
4212                                                         one of the SLI_MSI_RCV# registers being set.
4213                                                         Which bit is set is dependent on the previously
4214                                                         written using the SLI_MSI_WR_MAP register or if
4215                                                         not previously written the reset value of the MAP. */
4216	uint64_t reserved_0_15                : 16;
4217#else
4218	uint64_t reserved_0_15                : 16;
4219	uint64_t intr                         : 8;
4220	uint64_t reserved_24_63               : 40;
4221#endif
4222	} s;
4223	struct cvmx_sli_pcie_msi_rcv_b2_s     cn61xx;
4224	struct cvmx_sli_pcie_msi_rcv_b2_s     cn63xx;
4225	struct cvmx_sli_pcie_msi_rcv_b2_s     cn63xxp1;
4226	struct cvmx_sli_pcie_msi_rcv_b2_s     cn66xx;
4227	struct cvmx_sli_pcie_msi_rcv_b2_s     cn68xx;
4228	struct cvmx_sli_pcie_msi_rcv_b2_s     cn68xxp1;
4229	struct cvmx_sli_pcie_msi_rcv_b2_s     cnf71xx;
4230};
4231typedef union cvmx_sli_pcie_msi_rcv_b2 cvmx_sli_pcie_msi_rcv_b2_t;
4232
4233/**
4234 * cvmx_sli_pcie_msi_rcv_b3
4235 *
4236 * SLI_PCIE_MSI_RCV_B3 = SLI MAC MSI Receive Byte 3
4237 *
4238 * Register where MSI writes are directed from the MAC.
4239 *
4240 * Notes:
4241 * This CSR can be used by PCIe and sRIO MACs.
4242 *
4243 */
4244union cvmx_sli_pcie_msi_rcv_b3 {
4245	uint64_t u64;
4246	struct cvmx_sli_pcie_msi_rcv_b3_s {
4247#ifdef __BIG_ENDIAN_BITFIELD
4248	uint64_t reserved_32_63               : 32;
4249	uint64_t intr                         : 8;  /**< A write to this register will result in a bit in
4250                                                         one of the SLI_MSI_RCV# registers being set.
4251                                                         Which bit is set is dependent on the previously
4252                                                         written using the SLI_MSI_WR_MAP register or if
4253                                                         not previously written the reset value of the MAP. */
4254	uint64_t reserved_0_23                : 24;
4255#else
4256	uint64_t reserved_0_23                : 24;
4257	uint64_t intr                         : 8;
4258	uint64_t reserved_32_63               : 32;
4259#endif
4260	} s;
4261	struct cvmx_sli_pcie_msi_rcv_b3_s     cn61xx;
4262	struct cvmx_sli_pcie_msi_rcv_b3_s     cn63xx;
4263	struct cvmx_sli_pcie_msi_rcv_b3_s     cn63xxp1;
4264	struct cvmx_sli_pcie_msi_rcv_b3_s     cn66xx;
4265	struct cvmx_sli_pcie_msi_rcv_b3_s     cn68xx;
4266	struct cvmx_sli_pcie_msi_rcv_b3_s     cn68xxp1;
4267	struct cvmx_sli_pcie_msi_rcv_b3_s     cnf71xx;
4268};
4269typedef union cvmx_sli_pcie_msi_rcv_b3 cvmx_sli_pcie_msi_rcv_b3_t;
4270
4271/**
4272 * cvmx_sli_pkt#_cnts
4273 *
4274 * SLI_PKT[0..31]_CNTS = SLI Packet ring# Counts
4275 *
4276 * The counters for output rings.
4277 */
4278union cvmx_sli_pktx_cnts {
4279	uint64_t u64;
4280	struct cvmx_sli_pktx_cnts_s {
4281#ifdef __BIG_ENDIAN_BITFIELD
4282	uint64_t reserved_54_63               : 10;
4283	uint64_t timer                        : 22; /**< Timer incremented every 1024 core clocks
4284                                                         when SLI_PKTS#_CNTS[CNT] is non zero. Field
4285                                                         cleared when SLI_PKTS#_CNTS[CNT] goes to 0.
4286                                                         Field is also cleared when SLI_PKT_TIME_INT is
4287                                                         cleared.
4288                                                         The first increment of this count can occur
4289                                                         between 0 to 1023 core clocks. */
4290	uint64_t cnt                          : 32; /**< ring counter. This field is incremented as
4291                                                         packets are sent out and decremented in response to
4292                                                         writes to this field.
4293                                                         When SLI_PKT_OUT_BMODE is '0' a value of 1 is
4294                                                         added to the register for each packet, when '1'
4295                                                         and the info-pointer is NOT used the length of the
4296                                                         packet plus 8 is added, when '1' and info-pointer
4297                                                         mode IS used the packet length is added to this
4298                                                         field. */
4299#else
4300	uint64_t cnt                          : 32;
4301	uint64_t timer                        : 22;
4302	uint64_t reserved_54_63               : 10;
4303#endif
4304	} s;
4305	struct cvmx_sli_pktx_cnts_s           cn61xx;
4306	struct cvmx_sli_pktx_cnts_s           cn63xx;
4307	struct cvmx_sli_pktx_cnts_s           cn63xxp1;
4308	struct cvmx_sli_pktx_cnts_s           cn66xx;
4309	struct cvmx_sli_pktx_cnts_s           cn68xx;
4310	struct cvmx_sli_pktx_cnts_s           cn68xxp1;
4311	struct cvmx_sli_pktx_cnts_s           cnf71xx;
4312};
4313typedef union cvmx_sli_pktx_cnts cvmx_sli_pktx_cnts_t;
4314
4315/**
4316 * cvmx_sli_pkt#_in_bp
4317 *
4318 * SLI_PKT[0..31]_IN_BP = SLI Packet ring# Input Backpressure
4319 *
4320 * The counters and thresholds for input packets to apply backpressure to processing of the packets.
4321 */
4322union cvmx_sli_pktx_in_bp {
4323	uint64_t u64;
4324	struct cvmx_sli_pktx_in_bp_s {
4325#ifdef __BIG_ENDIAN_BITFIELD
4326	uint64_t wmark                        : 32; /**< When CNT is greater than this threshold no more
4327                                                         packets will be processed for this ring.
4328                                                         When writing this field of the SLI_PKT#_IN_BP
4329                                                         register, use a 4-byte write so as to not write
4330                                                         any other field of this register. */
4331	uint64_t cnt                          : 32; /**< ring counter. This field is incremented by one
4332                                                         whenever OCTEON receives, buffers, and creates a
4333                                                         work queue entry for a packet that arrives by the
4334                                                         cooresponding input ring. A write to this field
4335                                                         will be subtracted from the field value.
4336                                                         When writing this field of the SLI_PKT#_IN_BP
4337                                                         register, use a 4-byte write so as to not write
4338                                                         any other field of this register. */
4339#else
4340	uint64_t cnt                          : 32;
4341	uint64_t wmark                        : 32;
4342#endif
4343	} s;
4344	struct cvmx_sli_pktx_in_bp_s          cn61xx;
4345	struct cvmx_sli_pktx_in_bp_s          cn63xx;
4346	struct cvmx_sli_pktx_in_bp_s          cn63xxp1;
4347	struct cvmx_sli_pktx_in_bp_s          cn66xx;
4348	struct cvmx_sli_pktx_in_bp_s          cnf71xx;
4349};
4350typedef union cvmx_sli_pktx_in_bp cvmx_sli_pktx_in_bp_t;
4351
4352/**
4353 * cvmx_sli_pkt#_instr_baddr
4354 *
4355 * SLI_PKT[0..31]_INSTR_BADDR = SLI Packet ring# Instruction Base Address
4356 *
4357 * Start of Instruction for input packets.
4358 */
4359union cvmx_sli_pktx_instr_baddr {
4360	uint64_t u64;
4361	struct cvmx_sli_pktx_instr_baddr_s {
4362#ifdef __BIG_ENDIAN_BITFIELD
4363	uint64_t addr                         : 61; /**< Base address for Instructions. */
4364	uint64_t reserved_0_2                 : 3;
4365#else
4366	uint64_t reserved_0_2                 : 3;
4367	uint64_t addr                         : 61;
4368#endif
4369	} s;
4370	struct cvmx_sli_pktx_instr_baddr_s    cn61xx;
4371	struct cvmx_sli_pktx_instr_baddr_s    cn63xx;
4372	struct cvmx_sli_pktx_instr_baddr_s    cn63xxp1;
4373	struct cvmx_sli_pktx_instr_baddr_s    cn66xx;
4374	struct cvmx_sli_pktx_instr_baddr_s    cn68xx;
4375	struct cvmx_sli_pktx_instr_baddr_s    cn68xxp1;
4376	struct cvmx_sli_pktx_instr_baddr_s    cnf71xx;
4377};
4378typedef union cvmx_sli_pktx_instr_baddr cvmx_sli_pktx_instr_baddr_t;
4379
4380/**
4381 * cvmx_sli_pkt#_instr_baoff_dbell
4382 *
4383 * SLI_PKT[0..31]_INSTR_BAOFF_DBELL = SLI Packet ring# Instruction Base Address Offset and Doorbell
4384 *
4385 * The doorbell and base address offset for next read.
4386 */
4387union cvmx_sli_pktx_instr_baoff_dbell {
4388	uint64_t u64;
4389	struct cvmx_sli_pktx_instr_baoff_dbell_s {
4390#ifdef __BIG_ENDIAN_BITFIELD
4391	uint64_t aoff                         : 32; /**< The offset from the SLI_PKT[0..31]_INSTR_BADDR
4392                                                         where the next instruction will be read. */
4393	uint64_t dbell                        : 32; /**< Instruction doorbell count. Writes to this field
4394                                                         will increment the value here. Reads will return
4395                                                         present value. A write of 0xffffffff will set the
4396                                                         DBELL and AOFF fields to '0'. */
4397#else
4398	uint64_t dbell                        : 32;
4399	uint64_t aoff                         : 32;
4400#endif
4401	} s;
4402	struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx;
4403	struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx;
4404	struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1;
4405	struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx;
4406	struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx;
4407	struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1;
4408	struct cvmx_sli_pktx_instr_baoff_dbell_s cnf71xx;
4409};
4410typedef union cvmx_sli_pktx_instr_baoff_dbell cvmx_sli_pktx_instr_baoff_dbell_t;
4411
4412/**
4413 * cvmx_sli_pkt#_instr_fifo_rsize
4414 *
4415 * SLI_PKT[0..31]_INSTR_FIFO_RSIZE = SLI Packet ring# Instruction FIFO and Ring Size.
4416 *
4417 * Fifo field and ring size for Instructions.
4418 */
4419union cvmx_sli_pktx_instr_fifo_rsize {
4420	uint64_t u64;
4421	struct cvmx_sli_pktx_instr_fifo_rsize_s {
4422#ifdef __BIG_ENDIAN_BITFIELD
4423	uint64_t max                          : 9;  /**< Max Fifo Size. */
4424	uint64_t rrp                          : 9;  /**< Fifo read pointer. */
4425	uint64_t wrp                          : 9;  /**< Fifo write pointer. */
4426	uint64_t fcnt                         : 5;  /**< Fifo count. */
4427	uint64_t rsize                        : 32; /**< Instruction ring size. */
4428#else
4429	uint64_t rsize                        : 32;
4430	uint64_t fcnt                         : 5;
4431	uint64_t wrp                          : 9;
4432	uint64_t rrp                          : 9;
4433	uint64_t max                          : 9;
4434#endif
4435	} s;
4436	struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx;
4437	struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx;
4438	struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1;
4439	struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx;
4440	struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx;
4441	struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1;
4442	struct cvmx_sli_pktx_instr_fifo_rsize_s cnf71xx;
4443};
4444typedef union cvmx_sli_pktx_instr_fifo_rsize cvmx_sli_pktx_instr_fifo_rsize_t;
4445
4446/**
4447 * cvmx_sli_pkt#_instr_header
4448 *
4449 * SLI_PKT[0..31]_INSTR_HEADER = SLI Packet ring# Instruction Header.
4450 *
4451 * VAlues used to build input packet header.
4452 */
4453union cvmx_sli_pktx_instr_header {
4454	uint64_t u64;
4455	struct cvmx_sli_pktx_instr_header_s {
4456#ifdef __BIG_ENDIAN_BITFIELD
4457	uint64_t reserved_44_63               : 20;
4458	uint64_t pbp                          : 1;  /**< Enable Packet-by-packet mode.
4459                                                         Allows DPI to generate PKT_INST_HDR[PM,SL]
4460                                                         differently per DPI instruction.
4461                                                         USE_IHDR must be set whenever PBP is set. */
4462	uint64_t reserved_38_42               : 5;
4463	uint64_t rparmode                     : 2;  /**< Parse Mode. Becomes PKT_INST_HDR[PM]
4464                                                         when DPI_INST_HDR[R]==1 and PBP==0 */
4465	uint64_t reserved_35_35               : 1;
4466	uint64_t rskp_len                     : 7;  /**< Skip Length. Becomes PKT_INST_HDR[SL]
4467                                                         when DPI_INST_HDR[R]==1 and PBP==0 */
4468	uint64_t rngrpext                     : 2;  /**< Becomes PKT_INST_HDR[GRPEXT]
4469                                                         when DPI_INST_HDR[R]==1 */
4470	uint64_t rnqos                        : 1;  /**< Becomes PKT_INST_HDR[NQOS]
4471                                                         when DPI_INST_HDR[R]==1 */
4472	uint64_t rngrp                        : 1;  /**< Becomes PKT_INST_HDR[NGRP]
4473                                                         when DPI_INST_HDR[R]==1 */
4474	uint64_t rntt                         : 1;  /**< Becomes PKT_INST_HDR[NTT]
4475                                                         when DPI_INST_HDR[R]==1 */
4476	uint64_t rntag                        : 1;  /**< Becomes PKT_INST_HDR[NTAG]
4477                                                         when DPI_INST_HDR[R]==1 */
4478	uint64_t use_ihdr                     : 1;  /**< When set '1' DPI always prepends a PKT_INST_HDR
4479                                                         as part of the packet data sent to PIP/IPD,
4480                                                         regardless of DPI_INST_HDR[R]. (DPI also always
4481                                                         prepends a PKT_INST_HDR when DPI_INST_HDR[R]=1.)
4482                                                         USE_IHDR must be set whenever PBP is set. */
4483	uint64_t reserved_16_20               : 5;
4484	uint64_t par_mode                     : 2;  /**< Parse Mode. Becomes PKT_INST_HDR[PM]
4485                                                         when DPI_INST_HDR[R]==0 and USE_IHDR==1 and PBP==0 */
4486	uint64_t reserved_13_13               : 1;
4487	uint64_t skp_len                      : 7;  /**< Skip Length. Becomes PKT_INST_HDR[SL]
4488                                                         when DPI_INST_HDR[R]==0 and USE_IHDR==1 and PBP==0 */
4489	uint64_t ngrpext                      : 2;  /**< Becomes PKT_INST_HDR[GRPEXT]
4490                                                         when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */
4491	uint64_t nqos                         : 1;  /**< Becomes PKT_INST_HDR[NQOS]
4492                                                         when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */
4493	uint64_t ngrp                         : 1;  /**< Becomes PKT_INST_HDR[NGRP]
4494                                                         when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */
4495	uint64_t ntt                          : 1;  /**< Becomes PKT_INST_HDR[NTT]
4496                                                         when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */
4497	uint64_t ntag                         : 1;  /**< Becomes PKT_INST_HDR[NTAG]
4498                                                         when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */
4499#else
4500	uint64_t ntag                         : 1;
4501	uint64_t ntt                          : 1;
4502	uint64_t ngrp                         : 1;
4503	uint64_t nqos                         : 1;
4504	uint64_t ngrpext                      : 2;
4505	uint64_t skp_len                      : 7;
4506	uint64_t reserved_13_13               : 1;
4507	uint64_t par_mode                     : 2;
4508	uint64_t reserved_16_20               : 5;
4509	uint64_t use_ihdr                     : 1;
4510	uint64_t rntag                        : 1;
4511	uint64_t rntt                         : 1;
4512	uint64_t rngrp                        : 1;
4513	uint64_t rnqos                        : 1;
4514	uint64_t rngrpext                     : 2;
4515	uint64_t rskp_len                     : 7;
4516	uint64_t reserved_35_35               : 1;
4517	uint64_t rparmode                     : 2;
4518	uint64_t reserved_38_42               : 5;
4519	uint64_t pbp                          : 1;
4520	uint64_t reserved_44_63               : 20;
4521#endif
4522	} s;
4523	struct cvmx_sli_pktx_instr_header_cn61xx {
4524#ifdef __BIG_ENDIAN_BITFIELD
4525	uint64_t reserved_44_63               : 20;
4526	uint64_t pbp                          : 1;  /**< Enable Packet-by-packet mode.
4527                                                         Allows DPI to generate PKT_INST_HDR[PM,SL]
4528                                                         differently per DPI instruction.
4529                                                         USE_IHDR must be set whenever PBP is set. */
4530	uint64_t reserved_38_42               : 5;
4531	uint64_t rparmode                     : 2;  /**< Parse Mode. Becomes PKT_INST_HDR[PM]
4532                                                         when DPI_INST_HDR[R]==1 and PBP==0 */
4533	uint64_t reserved_35_35               : 1;
4534	uint64_t rskp_len                     : 7;  /**< Skip Length. Becomes PKT_INST_HDR[SL]
4535                                                         when DPI_INST_HDR[R]==1 and PBP==0 */
4536	uint64_t reserved_26_27               : 2;
4537	uint64_t rnqos                        : 1;  /**< Becomes PKT_INST_HDR[NQOS]
4538                                                         when DPI_INST_HDR[R]==1 */
4539	uint64_t rngrp                        : 1;  /**< Becomes PKT_INST_HDR[NGRP]
4540                                                         when DPI_INST_HDR[R]==1 */
4541	uint64_t rntt                         : 1;  /**< Becomes PKT_INST_HDR[NTT]
4542                                                         when DPI_INST_HDR[R]==1 */
4543	uint64_t rntag                        : 1;  /**< Becomes PKT_INST_HDR[NTAG]
4544                                                         when DPI_INST_HDR[R]==1 */
4545	uint64_t use_ihdr                     : 1;  /**< When set '1' DPI always prepends a PKT_INST_HDR
4546                                                         as part of the packet data sent to PIP/IPD,
4547                                                         regardless of DPI_INST_HDR[R]. (DPI also always
4548                                                         prepends a PKT_INST_HDR when DPI_INST_HDR[R]=1.)
4549                                                         USE_IHDR must be set whenever PBP is set. */
4550	uint64_t reserved_16_20               : 5;
4551	uint64_t par_mode                     : 2;  /**< Parse Mode. Becomes PKT_INST_HDR[PM]
4552                                                         when DPI_INST_HDR[R]==0 and USE_IHDR==1 and PBP==0 */
4553	uint64_t reserved_13_13               : 1;
4554	uint64_t skp_len                      : 7;  /**< Skip Length. Becomes PKT_INST_HDR[SL]
4555                                                         when DPI_INST_HDR[R]==0 and USE_IHDR==1 and PBP==0 */
4556	uint64_t reserved_4_5                 : 2;
4557	uint64_t nqos                         : 1;  /**< Becomes PKT_INST_HDR[NQOS]
4558                                                         when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */
4559	uint64_t ngrp                         : 1;  /**< Becomes PKT_INST_HDR[NGRP]
4560                                                         when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */
4561	uint64_t ntt                          : 1;  /**< Becomes PKT_INST_HDR[NTT]
4562                                                         when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */
4563	uint64_t ntag                         : 1;  /**< Becomes PKT_INST_HDR[NTAG]
4564                                                         when DPI_INST_HDR[R]==0 (and USE_IHDR==1) */
4565#else
4566	uint64_t ntag                         : 1;
4567	uint64_t ntt                          : 1;
4568	uint64_t ngrp                         : 1;
4569	uint64_t nqos                         : 1;
4570	uint64_t reserved_4_5                 : 2;
4571	uint64_t skp_len                      : 7;
4572	uint64_t reserved_13_13               : 1;
4573	uint64_t par_mode                     : 2;
4574	uint64_t reserved_16_20               : 5;
4575	uint64_t use_ihdr                     : 1;
4576	uint64_t rntag                        : 1;
4577	uint64_t rntt                         : 1;
4578	uint64_t rngrp                        : 1;
4579	uint64_t rnqos                        : 1;
4580	uint64_t reserved_26_27               : 2;
4581	uint64_t rskp_len                     : 7;
4582	uint64_t reserved_35_35               : 1;
4583	uint64_t rparmode                     : 2;
4584	uint64_t reserved_38_42               : 5;
4585	uint64_t pbp                          : 1;
4586	uint64_t reserved_44_63               : 20;
4587#endif
4588	} cn61xx;
4589	struct cvmx_sli_pktx_instr_header_cn61xx cn63xx;
4590	struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1;
4591	struct cvmx_sli_pktx_instr_header_cn61xx cn66xx;
4592	struct cvmx_sli_pktx_instr_header_s   cn68xx;
4593	struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1;
4594	struct cvmx_sli_pktx_instr_header_cn61xx cnf71xx;
4595};
4596typedef union cvmx_sli_pktx_instr_header cvmx_sli_pktx_instr_header_t;
4597
4598/**
4599 * cvmx_sli_pkt#_out_size
4600 *
4601 * SLI_PKT[0..31]_OUT_SIZE = SLI Packet Out Size
4602 *
4603 * Contains the BSIZE and ISIZE for output packet ports.
4604 */
4605union cvmx_sli_pktx_out_size {
4606	uint64_t u64;
4607	struct cvmx_sli_pktx_out_size_s {
4608#ifdef __BIG_ENDIAN_BITFIELD
4609	uint64_t reserved_23_63               : 41;
4610	uint64_t isize                        : 7;  /**< INFO BYTES size (bytes) for ring X. Legal sizes
4611                                                         are 0 to 120. Not used in buffer-pointer-only mode. */
4612	uint64_t bsize                        : 16; /**< BUFFER SIZE (bytes) for ring X. */
4613#else
4614	uint64_t bsize                        : 16;
4615	uint64_t isize                        : 7;
4616	uint64_t reserved_23_63               : 41;
4617#endif
4618	} s;
4619	struct cvmx_sli_pktx_out_size_s       cn61xx;
4620	struct cvmx_sli_pktx_out_size_s       cn63xx;
4621	struct cvmx_sli_pktx_out_size_s       cn63xxp1;
4622	struct cvmx_sli_pktx_out_size_s       cn66xx;
4623	struct cvmx_sli_pktx_out_size_s       cn68xx;
4624	struct cvmx_sli_pktx_out_size_s       cn68xxp1;
4625	struct cvmx_sli_pktx_out_size_s       cnf71xx;
4626};
4627typedef union cvmx_sli_pktx_out_size cvmx_sli_pktx_out_size_t;
4628
4629/**
4630 * cvmx_sli_pkt#_slist_baddr
4631 *
4632 * SLI_PKT[0..31]_SLIST_BADDR = SLI Packet ring# Scatter List Base Address
4633 *
4634 * Start of Scatter List for output packet pointers - MUST be 16 byte alligned
4635 */
4636union cvmx_sli_pktx_slist_baddr {
4637	uint64_t u64;
4638	struct cvmx_sli_pktx_slist_baddr_s {
4639#ifdef __BIG_ENDIAN_BITFIELD
4640	uint64_t addr                         : 60; /**< Base address for scatter list pointers. */
4641	uint64_t reserved_0_3                 : 4;
4642#else
4643	uint64_t reserved_0_3                 : 4;
4644	uint64_t addr                         : 60;
4645#endif
4646	} s;
4647	struct cvmx_sli_pktx_slist_baddr_s    cn61xx;
4648	struct cvmx_sli_pktx_slist_baddr_s    cn63xx;
4649	struct cvmx_sli_pktx_slist_baddr_s    cn63xxp1;
4650	struct cvmx_sli_pktx_slist_baddr_s    cn66xx;
4651	struct cvmx_sli_pktx_slist_baddr_s    cn68xx;
4652	struct cvmx_sli_pktx_slist_baddr_s    cn68xxp1;
4653	struct cvmx_sli_pktx_slist_baddr_s    cnf71xx;
4654};
4655typedef union cvmx_sli_pktx_slist_baddr cvmx_sli_pktx_slist_baddr_t;
4656
4657/**
4658 * cvmx_sli_pkt#_slist_baoff_dbell
4659 *
4660 * SLI_PKT[0..31]_SLIST_BAOFF_DBELL = SLI Packet ring# Scatter List Base Address Offset and Doorbell
4661 *
4662 * The doorbell and base address offset for next read.
4663 */
4664union cvmx_sli_pktx_slist_baoff_dbell {
4665	uint64_t u64;
4666	struct cvmx_sli_pktx_slist_baoff_dbell_s {
4667#ifdef __BIG_ENDIAN_BITFIELD
4668	uint64_t aoff                         : 32; /**< The offset from the SLI_PKT[0..31]_SLIST_BADDR
4669                                                         where the next SList pointer will be read.
4670                                                         A write of 0xFFFFFFFF to the DBELL field will
4671                                                         clear DBELL and AOFF */
4672	uint64_t dbell                        : 32; /**< Scatter list doorbell count. Writes to this field
4673                                                         will increment the value here. Reads will return
4674                                                         present value. The value of this field is
4675                                                         decremented as read operations are ISSUED for
4676                                                         scatter pointers.
4677                                                         A write of 0xFFFFFFFF will clear DBELL and AOFF */
4678#else
4679	uint64_t dbell                        : 32;
4680	uint64_t aoff                         : 32;
4681#endif
4682	} s;
4683	struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx;
4684	struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx;
4685	struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1;
4686	struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx;
4687	struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx;
4688	struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1;
4689	struct cvmx_sli_pktx_slist_baoff_dbell_s cnf71xx;
4690};
4691typedef union cvmx_sli_pktx_slist_baoff_dbell cvmx_sli_pktx_slist_baoff_dbell_t;
4692
4693/**
4694 * cvmx_sli_pkt#_slist_fifo_rsize
4695 *
4696 * SLI_PKT[0..31]_SLIST_FIFO_RSIZE = SLI Packet ring# Scatter List FIFO and Ring Size.
4697 *
4698 * The number of scatter pointer pairs in the scatter list.
4699 */
4700union cvmx_sli_pktx_slist_fifo_rsize {
4701	uint64_t u64;
4702	struct cvmx_sli_pktx_slist_fifo_rsize_s {
4703#ifdef __BIG_ENDIAN_BITFIELD
4704	uint64_t reserved_32_63               : 32;
4705	uint64_t rsize                        : 32; /**< The number of scatter pointer pairs contained in
4706                                                         the scatter list ring. */
4707#else
4708	uint64_t rsize                        : 32;
4709	uint64_t reserved_32_63               : 32;
4710#endif
4711	} s;
4712	struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx;
4713	struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx;
4714	struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1;
4715	struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx;
4716	struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx;
4717	struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1;
4718	struct cvmx_sli_pktx_slist_fifo_rsize_s cnf71xx;
4719};
4720typedef union cvmx_sli_pktx_slist_fifo_rsize cvmx_sli_pktx_slist_fifo_rsize_t;
4721
4722/**
4723 * cvmx_sli_pkt_cnt_int
4724 *
4725 * SLI_PKT_CNT_INT = SLI Packet Counter Interrupt
4726 *
4727 * The packets rings that are interrupting because of Packet Counters.
4728 */
4729union cvmx_sli_pkt_cnt_int {
4730	uint64_t u64;
4731	struct cvmx_sli_pkt_cnt_int_s {
4732#ifdef __BIG_ENDIAN_BITFIELD
4733	uint64_t reserved_32_63               : 32;
4734	uint64_t port                         : 32; /**< Output ring packet counter interrupt bits
4735                                                         SLI sets PORT<i> whenever
4736                                                         SLI_PKTi_CNTS[CNT] > SLI_PKT_INT_LEVELS[CNT].
4737                                                         SLI_PKT_CNT_INT_ENB[PORT<i>] is the corresponding
4738                                                         enable. */
4739#else
4740	uint64_t port                         : 32;
4741	uint64_t reserved_32_63               : 32;
4742#endif
4743	} s;
4744	struct cvmx_sli_pkt_cnt_int_s         cn61xx;
4745	struct cvmx_sli_pkt_cnt_int_s         cn63xx;
4746	struct cvmx_sli_pkt_cnt_int_s         cn63xxp1;
4747	struct cvmx_sli_pkt_cnt_int_s         cn66xx;
4748	struct cvmx_sli_pkt_cnt_int_s         cn68xx;
4749	struct cvmx_sli_pkt_cnt_int_s         cn68xxp1;
4750	struct cvmx_sli_pkt_cnt_int_s         cnf71xx;
4751};
4752typedef union cvmx_sli_pkt_cnt_int cvmx_sli_pkt_cnt_int_t;
4753
4754/**
4755 * cvmx_sli_pkt_cnt_int_enb
4756 *
4757 * SLI_PKT_CNT_INT_ENB = SLI Packet Counter Interrupt Enable
4758 *
4759 * Enable for the packets rings that are interrupting because of Packet Counters.
4760 */
4761union cvmx_sli_pkt_cnt_int_enb {
4762	uint64_t u64;
4763	struct cvmx_sli_pkt_cnt_int_enb_s {
4764#ifdef __BIG_ENDIAN_BITFIELD
4765	uint64_t reserved_32_63               : 32;
4766	uint64_t port                         : 32; /**< Output ring packet counter interrupt enables
4767                                                         When both PORT<i> and corresponding
4768                                                         SLI_PKT_CNT_INT[PORT<i>] are set, for any i,
4769                                                         then SLI_INT_SUM[PCNT] is set, which can cause
4770                                                         an interrupt. */
4771#else
4772	uint64_t port                         : 32;
4773	uint64_t reserved_32_63               : 32;
4774#endif
4775	} s;
4776	struct cvmx_sli_pkt_cnt_int_enb_s     cn61xx;
4777	struct cvmx_sli_pkt_cnt_int_enb_s     cn63xx;
4778	struct cvmx_sli_pkt_cnt_int_enb_s     cn63xxp1;
4779	struct cvmx_sli_pkt_cnt_int_enb_s     cn66xx;
4780	struct cvmx_sli_pkt_cnt_int_enb_s     cn68xx;
4781	struct cvmx_sli_pkt_cnt_int_enb_s     cn68xxp1;
4782	struct cvmx_sli_pkt_cnt_int_enb_s     cnf71xx;
4783};
4784typedef union cvmx_sli_pkt_cnt_int_enb cvmx_sli_pkt_cnt_int_enb_t;
4785
4786/**
4787 * cvmx_sli_pkt_ctl
4788 *
4789 * SLI_PKT_CTL = SLI Packet Control
4790 *
4791 * Control for packets.
4792 */
4793union cvmx_sli_pkt_ctl {
4794	uint64_t u64;
4795	struct cvmx_sli_pkt_ctl_s {
4796#ifdef __BIG_ENDIAN_BITFIELD
4797	uint64_t reserved_5_63                : 59;
4798	uint64_t ring_en                      : 1;  /**< When '0' forces "relative Q position" received
4799                                                         from PKO to be zero, and replicates the back-
4800                                                         pressure indication for the first ring attached
4801                                                         to a PKO port across all the rings attached to a
4802                                                         PKO port. When '1' backpressure is on a per
4803                                                         port/ring. */
4804	uint64_t pkt_bp                       : 4;  /**< When set '1' enable the port level backpressure for
4805                                                         PKO ports associated with the bit. */
4806#else
4807	uint64_t pkt_bp                       : 4;
4808	uint64_t ring_en                      : 1;
4809	uint64_t reserved_5_63                : 59;
4810#endif
4811	} s;
4812	struct cvmx_sli_pkt_ctl_s             cn61xx;
4813	struct cvmx_sli_pkt_ctl_s             cn63xx;
4814	struct cvmx_sli_pkt_ctl_s             cn63xxp1;
4815	struct cvmx_sli_pkt_ctl_s             cn66xx;
4816	struct cvmx_sli_pkt_ctl_s             cn68xx;
4817	struct cvmx_sli_pkt_ctl_s             cn68xxp1;
4818	struct cvmx_sli_pkt_ctl_s             cnf71xx;
4819};
4820typedef union cvmx_sli_pkt_ctl cvmx_sli_pkt_ctl_t;
4821
4822/**
4823 * cvmx_sli_pkt_data_out_es
4824 *
4825 * SLI_PKT_DATA_OUT_ES = SLI's Packet Data Out Endian Swap
4826 *
4827 * The Endian Swap for writing Data Out.
4828 */
4829union cvmx_sli_pkt_data_out_es {
4830	uint64_t u64;
4831	struct cvmx_sli_pkt_data_out_es_s {
4832#ifdef __BIG_ENDIAN_BITFIELD
4833	uint64_t es                           : 64; /**< ES<1:0> or MACADD<63:62> for buffer/info writes.
4834                                                         ES<2i+1:2i> becomes either ES<1:0> or
4835                                                         MACADD<63:62> for writes to buffer/info pair
4836                                                         MAC memory space addresses fetched from packet
4837                                                         output ring i. ES<1:0> if SLI_PKT_DPADDR[DPTR<i>]=1
4838                                                         , else MACADD<63:62>.
4839                                                         In the latter case, ES<1:0> comes from DPTR<63:62>.
4840                                                         ES<1:0> is the endian-swap attribute for these MAC
4841                                                         memory space writes. */
4842#else
4843	uint64_t es                           : 64;
4844#endif
4845	} s;
4846	struct cvmx_sli_pkt_data_out_es_s     cn61xx;
4847	struct cvmx_sli_pkt_data_out_es_s     cn63xx;
4848	struct cvmx_sli_pkt_data_out_es_s     cn63xxp1;
4849	struct cvmx_sli_pkt_data_out_es_s     cn66xx;
4850	struct cvmx_sli_pkt_data_out_es_s     cn68xx;
4851	struct cvmx_sli_pkt_data_out_es_s     cn68xxp1;
4852	struct cvmx_sli_pkt_data_out_es_s     cnf71xx;
4853};
4854typedef union cvmx_sli_pkt_data_out_es cvmx_sli_pkt_data_out_es_t;
4855
4856/**
4857 * cvmx_sli_pkt_data_out_ns
4858 *
4859 * SLI_PKT_DATA_OUT_NS = SLI's Packet Data Out No Snoop
4860 *
4861 * The NS field for the TLP when writing packet data.
4862 */
4863union cvmx_sli_pkt_data_out_ns {
4864	uint64_t u64;
4865	struct cvmx_sli_pkt_data_out_ns_s {
4866#ifdef __BIG_ENDIAN_BITFIELD
4867	uint64_t reserved_32_63               : 32;
4868	uint64_t nsr                          : 32; /**< ADDRTYPE<1> or MACADD<61> for buffer/info writes.
4869                                                         NSR<i> becomes either ADDRTYPE<1> or MACADD<61>
4870                                                         for writes to buffer/info pair MAC memory space
4871                                                         addresses fetched from packet output ring i.
4872                                                         ADDRTYPE<1> if SLI_PKT_DPADDR[DPTR<i>]=1, else
4873                                                         MACADD<61>.
4874                                                         In the latter case,ADDRTYPE<1> comes from DPTR<61>.
4875                                                         ADDRTYPE<1> is the no-snoop attribute for PCIe
4876                                                         , helps select an SRIO*_S2M_TYPE* entry with sRIO. */
4877#else
4878