17d671d9br/*-
28ce15a8br * Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com>
37d671d9br * All rights reserved.
47d671d9br *
57d671d9br * This software was developed by SRI International and the University of
67d671d9br * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
77d671d9br * ("CTSRD"), as part of the DARPA CRASH research programme.
87d671d9br *
97d671d9br * Redistribution and use in source and binary forms, with or without
107d671d9br * modification, are permitted provided that the following conditions
117d671d9br * are met:
127d671d9br * 1. Redistributions of source code must retain the above copyright
137d671d9br *    notice, this list of conditions and the following disclaimer.
147d671d9br * 2. Redistributions in binary form must reproduce the above copyright
157d671d9br *    notice, this list of conditions and the following disclaimer in the
167d671d9br *    documentation and/or other materials provided with the distribution.
177d671d9br *
187d671d9br * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
197d671d9br * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
207d671d9br * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
217d671d9br * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
227d671d9br * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
237d671d9br * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
247d671d9br * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
257d671d9br * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
267d671d9br * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
277d671d9br * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
287d671d9br * SUCH DAMAGE.
297d671d9br */
307d671d9br
317d671d9br#include <sys/cdefs.h>
327d671d9br__FBSDID("$FreeBSD$");
337d671d9br
347d671d9br#include <sys/param.h>
357d671d9br#include <sys/systm.h>
367d671d9br#include <sys/bus.h>
377d671d9br#include <sys/rman.h>
387d671d9br#include <sys/kernel.h>
39250e158cem#include <sys/lock.h>
407d671d9br#include <sys/module.h>
41250e158cem#include <sys/mutex.h>
427d671d9br#include <machine/bus.h>
437d671d9br
447d671d9br#include <arm64/coresight/coresight.h>
457d671d9br
467d671d9brstatic struct mtx cs_mtx;
477d671d9brstruct coresight_device_list cs_devs;
487d671d9br
497d671d9brint
507d671d9brcoresight_register(struct coresight_desc *desc)
517d671d9br{
527d671d9br	struct coresight_device *cs_dev;
537d671d9br
547d671d9br	cs_dev = malloc(sizeof(struct coresight_device),
557d671d9br	    M_CORESIGHT, M_WAITOK | M_ZERO);
567d671d9br	cs_dev->dev = desc->dev;
577d671d9br	cs_dev->pdata = desc->pdata;
587d671d9br	cs_dev->dev_type = desc->dev_type;
597d671d9br
607d671d9br	mtx_lock(&cs_mtx);
617d671d9br	TAILQ_INSERT_TAIL(&cs_devs, cs_dev, link);
627d671d9br	mtx_unlock(&cs_mtx);
637d671d9br
647d671d9br	return (0);
657d671d9br}
667d671d9br
677d671d9brstruct endpoint *
687d671d9brcoresight_get_output_endpoint(struct coresight_platform_data *pdata)
697d671d9br{
707d671d9br	struct endpoint *endp;
717d671d9br
727d671d9br	if (pdata->out_ports != 1)
737d671d9br		return (NULL);
747d671d9br
757d671d9br	TAILQ_FOREACH(endp, &pdata->endpoints, link) {
768ce15a8br		if (endp->input == 0)
777d671d9br			return (endp);
787d671d9br	}
797d671d9br
807d671d9br	return (NULL);
817d671d9br}
827d671d9br
837d671d9brstruct coresight_device *
847d671d9brcoresight_get_output_device(struct endpoint *endp, struct endpoint **out_endp)
857d671d9br{
868ce15a8br	struct coresight_platform_data *pdata;
877d671d9br	struct coresight_device *cs_dev;
887d671d9br	struct endpoint *endp2;
897d671d9br
907d671d9br	TAILQ_FOREACH(cs_dev, &cs_devs, link) {
918ce15a8br		pdata = cs_dev->pdata;
927d671d9br		TAILQ_FOREACH(endp2, &cs_dev->pdata->endpoints, link) {
938ce15a8br			switch (pdata->bus_type) {
948ce15a8br			case CORESIGHT_BUS_FDT:
958ce15a8br#ifdef FDT
968ce15a8br				if (endp->their_node == endp2->my_node) {
978ce15a8br					*out_endp = endp2;
988ce15a8br					return (cs_dev);
998ce15a8br				}
1008ce15a8br#endif
1018ce15a8br				break;
1028ce15a8br
1038ce15a8br			case CORESIGHT_BUS_ACPI:
1048ce15a8br#ifdef DEV_ACPI
1058ce15a8br				if (endp->their_handle == endp2->my_handle) {
1068ce15a8br					*out_endp = endp2;
1078ce15a8br					return (cs_dev);
1088ce15a8br				}
1098ce15a8br#endif
1108ce15a8br				break;
1117d671d9br			}
1127d671d9br		}
1137d671d9br	}
1147d671d9br
1157d671d9br	return (NULL);
1167d671d9br}
1177d671d9br
1187d671d9brstatic void
1197d671d9brcoresight_init(void)
1207d671d9br{
1217d671d9br
1227d671d9br	mtx_init(&cs_mtx, "ARM Coresight", NULL, MTX_DEF);
1237d671d9br	TAILQ_INIT(&cs_devs);
1247d671d9br}
1257d671d9br
1267d671d9brSYSINIT(coresight, SI_SUB_DRIVERS, SI_ORDER_FIRST, coresight_init, NULL);
127