1fb9cbc2mmel/*-
2fb9cbc2mmel * Copyright (c) 2016 Michal Meloun
3fb9cbc2mmel * All rights reserved.
4fb9cbc2mmel *
5fb9cbc2mmel * Redistribution and use in source and binary forms, with or without
6fb9cbc2mmel * modification, are permitted provided that the following conditions
7fb9cbc2mmel * are met:
8fb9cbc2mmel * 1. Redistributions of source code must retain the above copyright
9fb9cbc2mmel *    notice, this list of conditions and the following disclaimer.
10fb9cbc2mmel * 2. Redistributions in binary form must reproduce the above copyright
11fb9cbc2mmel *    notice, this list of conditions and the following disclaimer in the
12fb9cbc2mmel *    documentation and/or other materials provided with the distribution.
13fb9cbc2mmel *
14fb9cbc2mmel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15fb9cbc2mmel * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16fb9cbc2mmel * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17fb9cbc2mmel * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18fb9cbc2mmel * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19fb9cbc2mmel * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20fb9cbc2mmel * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21fb9cbc2mmel * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22fb9cbc2mmel * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23fb9cbc2mmel * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24fb9cbc2mmel * SUCH DAMAGE.
25fb9cbc2mmel */
26fb9cbc2mmel
27fb9cbc2mmel#include <sys/cdefs.h>
28fb9cbc2mmel__FBSDID("$FreeBSD$");
29fb9cbc2mmel
30fb9cbc2mmel#include <sys/param.h>
31fb9cbc2mmel#include <sys/systm.h>
32fb9cbc2mmel#include <sys/bus.h>
33fb9cbc2mmel#include <sys/kernel.h>
34fb9cbc2mmel#include <sys/malloc.h>
35fb9cbc2mmel
36fb9cbc2mmel#include <machine/bus.h>
37fb9cbc2mmel
38fb9cbc2mmel#include <dev/extres/clk/clk.h>
39fb9cbc2mmel#include <dev/drm2/drmP.h>
40fb9cbc2mmel#include <dev/drm2/drm_crtc_helper.h>
41fb9cbc2mmel#include <dev/drm2/drm_fb_helper.h>
42fb9cbc2mmel
43fb9cbc2mmel#include <arm/nvidia/drm2/tegra_drm.h>
44fb9cbc2mmel
45fb9cbc2mmelstatic void
46fb9cbc2mmelfb_destroy(struct drm_framebuffer *drm_fb)
47fb9cbc2mmel{
48fb9cbc2mmel	struct tegra_fb *fb;
49fb9cbc2mmel	struct tegra_bo *bo;
50fb9cbc2mmel	unsigned int i;
51fb9cbc2mmel
52fb9cbc2mmel	fb = container_of(drm_fb, struct tegra_fb, drm_fb);
53fb9cbc2mmel	for (i = 0; i < fb->nplanes; i++) {
54fb9cbc2mmel		bo = fb->planes[i];
55fb9cbc2mmel		if (bo != NULL)
56fb9cbc2mmel			drm_gem_object_unreference_unlocked(&bo->gem_obj);
57fb9cbc2mmel	}
58fb9cbc2mmel
59fb9cbc2mmel	drm_framebuffer_cleanup(drm_fb);
60fb9cbc2mmel	free(fb->planes, DRM_MEM_DRIVER);
61fb9cbc2mmel}
62fb9cbc2mmel
63fb9cbc2mmelstatic int
64fb9cbc2mmelfb_create_handle(struct drm_framebuffer *drm_fb, struct drm_file *file,
65fb9cbc2mmel unsigned int *handle)
66fb9cbc2mmel{
67fb9cbc2mmel	struct tegra_fb *fb;
68fb9cbc2mmel	int rv;
69fb9cbc2mmel
70fb9cbc2mmel	fb = container_of(drm_fb, struct tegra_fb, drm_fb);
71fb9cbc2mmel	rv = drm_gem_handle_create(file, &fb->planes[0]->gem_obj, handle);
72fb9cbc2mmel	return (rv);
73fb9cbc2mmel}
74fb9cbc2mmel
75fb9cbc2mmel/* XXX Probably not needed */
76fb9cbc2mmelstatic int
77fb9cbc2mmelfb_dirty(struct drm_framebuffer *fb, struct drm_file *file_priv,
78fb9cbc2mmelunsigned flags, unsigned color, struct drm_clip_rect *clips, unsigned num_clips)
79fb9cbc2mmel{
80fb9cbc2mmel
81fb9cbc2mmel	return (0);
82fb9cbc2mmel}
83fb9cbc2mmel
84fb9cbc2mmelstatic const struct drm_framebuffer_funcs fb_funcs = {
85fb9cbc2mmel	.destroy = fb_destroy,
86fb9cbc2mmel	.create_handle = fb_create_handle,
87fb9cbc2mmel	.dirty = fb_dirty,
88fb9cbc2mmel};
89fb9cbc2mmel
90fb9cbc2mmelstatic int
91fb9cbc2mmelfb_alloc(struct drm_device *drm, struct drm_mode_fb_cmd2 *mode_cmd,
92fb9cbc2mmel    struct tegra_bo **planes, int num_planes, struct tegra_fb **res_fb)
93fb9cbc2mmel{
94fb9cbc2mmel	struct tegra_fb *fb;
95fb9cbc2mmel	int i;
96fb9cbc2mmel	int rv;
97fb9cbc2mmel
98fb9cbc2mmel	fb = malloc(sizeof(*fb), DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
99fb9cbc2mmel	fb->planes = malloc(num_planes * sizeof(*fb->planes), DRM_MEM_DRIVER,
100fb9cbc2mmel	    M_WAITOK | M_ZERO);
101fb9cbc2mmel	fb->nplanes = num_planes;
102fb9cbc2mmel
103fb9cbc2mmel	drm_helper_mode_fill_fb_struct(&fb->drm_fb, mode_cmd);
104fb9cbc2mmel	for (i = 0; i < fb->nplanes; i++)
105fb9cbc2mmel		fb->planes[i] = planes[i];
106fb9cbc2mmel	rv = drm_framebuffer_init(drm, &fb->drm_fb, &fb_funcs);
107fb9cbc2mmel	if (rv < 0) {
108fb9cbc2mmel		device_printf(drm->dev,
109fb9cbc2mmel		    "Cannot initialize frame buffer %d\n", rv);
110fb9cbc2mmel		free(fb->planes, DRM_MEM_DRIVER);
111fb9cbc2mmel		return (rv);
112fb9cbc2mmel	}
113fb9cbc2mmel	*res_fb = fb;
114fb9cbc2mmel	return (0);
115fb9cbc2mmel}
116fb9cbc2mmel
117fb9cbc2mmelstatic int
118fb9cbc2mmeltegra_fb_probe(struct drm_fb_helper *helper,
119fb9cbc2mmel    struct drm_fb_helper_surface_size *sizes)
120fb9cbc2mmel{
121fb9cbc2mmel	u_int bpp, size;
122fb9cbc2mmel	struct tegra_drm *drm;
123fb9cbc2mmel	struct tegra_fb *fb;
124fb9cbc2mmel	struct fb_info *info;
125fb9cbc2mmel	struct tegra_bo *bo;
126fb9cbc2mmel	struct drm_mode_fb_cmd2 mode_cmd;
127fb9cbc2mmel	struct drm_device *drm_dev;
128fb9cbc2mmel	int rv;
129fb9cbc2mmel
130fb9cbc2mmel	if (helper->fb != NULL)
131fb9cbc2mmel		return (0);
132fb9cbc2mmel
133fb9cbc2mmel	DRM_DEBUG_KMS("surface: %d x %d (bpp: %d)\n", sizes->surface_width,
134fb9cbc2mmel	    sizes->surface_height, sizes->surface_bpp);
135fb9cbc2mmel
136fb9cbc2mmel	drm_dev = helper->dev;
137fb9cbc2mmel	fb = container_of(helper, struct tegra_fb, fb_helper);
138fb9cbc2mmel	drm = container_of(drm_dev, struct tegra_drm, drm_dev);
139fb9cbc2mmel	bpp = (sizes->surface_bpp + 7) / 8;
140fb9cbc2mmel
141fb9cbc2mmel	/* Create mode_cmd */
142fb9cbc2mmel	memset(&mode_cmd, 0, sizeof(mode_cmd));
143fb9cbc2mmel	mode_cmd.width = sizes->surface_width;
144fb9cbc2mmel	mode_cmd.height = sizes->surface_height;
145fb9cbc2mmel	mode_cmd.pitches[0] = roundup(sizes->surface_width * bpp,
146fb9cbc2mmel	    drm->pitch_align);
147fb9cbc2mmel	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
148fb9cbc2mmel	    sizes->surface_depth);
149fb9cbc2mmel	size = mode_cmd.pitches[0] * mode_cmd.height;
150fb9cbc2mmel
151fb9cbc2mmel	DRM_LOCK(drm_dev);
152fb9cbc2mmel	rv = tegra_bo_create(drm_dev, size, &bo);
153fb9cbc2mmel	DRM_UNLOCK(drm_dev);
154fb9cbc2mmel	if (rv != 0)
155fb9cbc2mmel		return (rv);
156fb9cbc2mmel
157fb9cbc2mmel	info = framebuffer_alloc();
158fb9cbc2mmel	if (info == NULL) {
159fb9cbc2mmel		device_printf(drm_dev->dev,
160fb9cbc2mmel		    "Cannot allocate DRM framebuffer info.\n");
161fb9cbc2mmel		rv = -ENOMEM;
162fb9cbc2mmel		goto err_object;
163fb9cbc2mmel	}
164fb9cbc2mmel
165fb9cbc2mmel	rv = fb_alloc(drm_dev, &mode_cmd,  &bo, 1, &fb);
166fb9cbc2mmel	if (rv != 0) {
167fb9cbc2mmel		device_printf(drm_dev->dev,
168fb9cbc2mmel		     "Cannot allocate DRM framebuffer.\n");
169fb9cbc2mmel		goto err_fb;
170fb9cbc2mmel	}
171fb9cbc2mmel	helper->fb = &fb->drm_fb;
172fb9cbc2mmel	helper->fbdev = info;
173fb9cbc2mmel
174fb9cbc2mmel	/* Fill FB info */
175fb9cbc2mmel	info->fb_vbase = bo->vbase;
176fb9cbc2mmel	info->fb_pbase = bo->pbase;
177fb9cbc2mmel	info->fb_size = size;
178fb9cbc2mmel	info->fb_bpp = sizes->surface_bpp;
179fb9cbc2mmel	drm_fb_helper_fill_fix(info, fb->drm_fb.pitches[0], fb->drm_fb.depth);
180fb9cbc2mmel	drm_fb_helper_fill_var(info, helper, fb->drm_fb.width,
181fb9cbc2mmel	    fb->drm_fb.height);
182fb9cbc2mmel
183fb9cbc2mmel	DRM_DEBUG_KMS("allocated %dx%d (s %dbits) fb size: %d, bo %p\n",
184fb9cbc2mmel		      fb->drm_fb.width, fb->drm_fb.height, fb->drm_fb.depth,
185fb9cbc2mmel		      size, bo);
186fb9cbc2mmel	return (1);
187fb9cbc2mmelerr_fb:
188fb9cbc2mmel	drm_gem_object_unreference_unlocked(&bo->gem_obj);
189fb9cbc2mmel	framebuffer_release(info);
190fb9cbc2mmelerr_object:
191fb9cbc2mmel	drm_gem_object_release(&bo->gem_obj);
192fb9cbc2mmel	return (rv);
193fb9cbc2mmel}
194fb9cbc2mmel
195fb9cbc2mmelstatic struct drm_fb_helper_funcs fb_helper_funcs = {
196fb9cbc2mmel	.fb_probe = tegra_fb_probe,
197fb9cbc2mmel};
198fb9cbc2mmel
199fb9cbc2mmel/*
200fb9cbc2mmel *	Exported functions
201fb9cbc2mmel */
202fb9cbc2mmelstruct fb_info *
203fb9cbc2mmeltegra_drm_fb_getinfo(struct drm_device *drm_dev)
204fb9cbc2mmel{
205fb9cbc2mmel	struct tegra_fb *fb;
206fb9cbc2mmel	struct tegra_drm *drm;
207fb9cbc2mmel
208fb9cbc2mmel	drm = container_of(drm_dev, struct tegra_drm, drm_dev);
209fb9cbc2mmel	fb = drm->fb;
210fb9cbc2mmel	if (fb == NULL)
211fb9cbc2mmel		return (NULL);
212fb9cbc2mmel	return (fb->fb_helper.fbdev);
213fb9cbc2mmel}
214fb9cbc2mmel
215fb9cbc2mmelstruct tegra_bo *
216fb9cbc2mmeltegra_fb_get_plane(struct tegra_fb *fb, int idx)
217fb9cbc2mmel{
218fb9cbc2mmel
219fb9cbc2mmel	if (idx >= drm_format_num_planes(fb->drm_fb.pixel_format))
220fb9cbc2mmel		return (NULL);
221fb9cbc2mmel	if (idx >= fb->nplanes)
222fb9cbc2mmel		return (NULL);
223fb9cbc2mmel	return (fb->planes[idx]);
224fb9cbc2mmel}
225fb9cbc2mmel
226fb9cbc2mmelint
227fb9cbc2mmeltegra_drm_fb_init(struct drm_device *drm_dev)
228fb9cbc2mmel{
229fb9cbc2mmel	struct tegra_fb *fb;
230fb9cbc2mmel	struct tegra_drm *drm;
231fb9cbc2mmel	int rv;
232fb9cbc2mmel
233fb9cbc2mmel	drm = drm_dev->dev_private;
234fb9cbc2mmel	drm = container_of(drm_dev, struct tegra_drm, drm_dev);
235fb9cbc2mmel	fb = malloc(sizeof(*fb), DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
236fb9cbc2mmel	drm->fb = fb;
237fb9cbc2mmel
238fb9cbc2mmel	fb->fb_helper.funcs = &fb_helper_funcs;
239fb9cbc2mmel	rv = drm_fb_helper_init(drm_dev, &fb->fb_helper,
240fb9cbc2mmel	    drm_dev->mode_config.num_crtc, drm_dev->mode_config.num_connector);
241fb9cbc2mmel	if (rv != 0) {
242fb9cbc2mmel		device_printf(drm_dev->dev,
243fb9cbc2mmel		    "Cannot initialize frame buffer %d\n", rv);
244fb9cbc2mmel		return (rv);
245fb9cbc2mmel	}
246fb9cbc2mmel
247fb9cbc2mmel	rv = drm_fb_helper_single_add_all_connectors(&fb->fb_helper);
248fb9cbc2mmel	if (rv != 0) {
249fb9cbc2mmel		device_printf(drm_dev->dev, "Cannot add all connectors: %d\n",
250fb9cbc2mmel		    rv);
251fb9cbc2mmel		goto err_fini;
252fb9cbc2mmel	}
253fb9cbc2mmel
254fb9cbc2mmel	rv = drm_fb_helper_initial_config(&fb->fb_helper, 32);
255fb9cbc2mmel	if (rv != 0) {
256fb9cbc2mmel		device_printf(drm_dev->dev,
257fb9cbc2mmel		    "Cannot set initial config: %d\n", rv);
258fb9cbc2mmel		goto err_fini;
259fb9cbc2mmel	}
260fb9cbc2mmel	/* XXXX Setup initial mode for FB */
261fb9cbc2mmel	/* drm_fb_helper_set_par(fb->fb_helper.fbdev); */
262fb9cbc2mmel	return 0;
263fb9cbc2mmel
264fb9cbc2mmelerr_fini:
265fb9cbc2mmel	drm_fb_helper_fini(&fb->fb_helper);
266fb9cbc2mmel	return (rv);
267fb9cbc2mmel}
268fb9cbc2mmel
269fb9cbc2mmelint
270fb9cbc2mmeltegra_drm_fb_create(struct drm_device *drm, struct drm_file *file,
271fb9cbc2mmel    struct drm_mode_fb_cmd2 *cmd, struct drm_framebuffer **fb_res)
272fb9cbc2mmel{
273fb9cbc2mmel	int hsub, vsub, i;
274fb9cbc2mmel	int width, height, size, bpp;
275fb9cbc2mmel	struct tegra_bo *planes[4];
276fb9cbc2mmel	struct drm_gem_object *gem_obj;
277fb9cbc2mmel	struct tegra_fb *fb;
278fb9cbc2mmel	int rv, nplanes;
279fb9cbc2mmel
280fb9cbc2mmel	hsub = drm_format_horz_chroma_subsampling(cmd->pixel_format);
281fb9cbc2mmel	vsub = drm_format_vert_chroma_subsampling(cmd->pixel_format);
282fb9cbc2mmel
283fb9cbc2mmel	nplanes = drm_format_num_planes(cmd->pixel_format);
284fb9cbc2mmel	for (i = 0; i < nplanes; i++) {
285fb9cbc2mmel		width = cmd->width;
286fb9cbc2mmel		height = cmd->height;
287fb9cbc2mmel		if (i != 0) {
288fb9cbc2mmel			width /= hsub;
289fb9cbc2mmel			height /= vsub;
290fb9cbc2mmel		}
291fb9cbc2mmel		gem_obj = drm_gem_object_lookup(drm, file, cmd->handles[i]);
292fb9cbc2mmel		if (gem_obj == NULL) {
293fb9cbc2mmel			rv = -ENXIO;
294fb9cbc2mmel			goto fail;
295fb9cbc2mmel		}
296fb9cbc2mmel
297fb9cbc2mmel		bpp = drm_format_plane_cpp(cmd->pixel_format, i);
298fb9cbc2mmel		size = (height - 1) * cmd->pitches[i] +
299fb9cbc2mmel		    width * bpp + cmd->offsets[i];
300fb9cbc2mmel		if (gem_obj->size < size) {
301fb9cbc2mmel			rv = -EINVAL;
302fb9cbc2mmel			goto fail;
303fb9cbc2mmel		}
304fb9cbc2mmel		planes[i] = container_of(gem_obj, struct tegra_bo, gem_obj);
305fb9cbc2mmel	}
306fb9cbc2mmel
307fb9cbc2mmel	rv = fb_alloc(drm, cmd, planes, nplanes, &fb);
308fb9cbc2mmel	if (rv != 0)
309fb9cbc2mmel		goto fail;
310fb9cbc2mmel
311fb9cbc2mmel	*fb_res = &fb->drm_fb;
312fb9cbc2mmel	return (0);
313fb9cbc2mmel
314fb9cbc2mmelfail:
315fb9cbc2mmel	while (i--)
316fb9cbc2mmel		drm_gem_object_unreference_unlocked(&planes[i]->gem_obj);
317fb9cbc2mmel	return (rv);
318fb9cbc2mmel}
319fb9cbc2mmel
320fb9cbc2mmelvoid
321fb9cbc2mmeltegra_drm_fb_destroy(struct drm_device *drm_dev)
322fb9cbc2mmel{
323fb9cbc2mmel	struct fb_info *info;
324fb9cbc2mmel	struct tegra_fb *fb;
325fb9cbc2mmel	struct tegra_drm *drm;
326fb9cbc2mmel
327fb9cbc2mmel	drm = container_of(drm_dev, struct tegra_drm, drm_dev);
328fb9cbc2mmel	fb = drm->fb;
329fb9cbc2mmel	if (fb == NULL)
330fb9cbc2mmel		return;
331fb9cbc2mmel	info = fb->fb_helper.fbdev;
332fb9cbc2mmel	drm_framebuffer_remove(&fb->drm_fb);
333fb9cbc2mmel	framebuffer_release(info);
334fb9cbc2mmel	drm_fb_helper_fini(&fb->fb_helper);
335fb9cbc2mmel	drm_framebuffer_cleanup(&fb->drm_fb);
336fb9cbc2mmel	free(fb, DRM_MEM_DRIVER);
337fb9cbc2mmel	drm->fb = NULL;
338fb9cbc2mmel}
339