1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * Vybrid Family Inter-Integrated Circuit (I2C)
31 * Chapter 48, Vybrid Reference Manual, Rev. 5, 07/2013
32 */
33
34/*
35 * This driver is based on the I2C driver for i.MX
36 */
37
38#include <sys/cdefs.h>
39__FBSDID("$FreeBSD$");
40
41#include <sys/param.h>
42#include <sys/systm.h>
43#include <sys/bus.h>
44#include <sys/kernel.h>
45#include <sys/module.h>
46#include <sys/malloc.h>
47#include <sys/rman.h>
48#include <sys/timeet.h>
49#include <sys/timetc.h>
50
51#include <dev/iicbus/iiconf.h>
52#include <dev/iicbus/iicbus.h>
53
54#include "iicbus_if.h"
55
56#include <dev/ofw/openfirm.h>
57#include <dev/ofw/ofw_bus.h>
58#include <dev/ofw/ofw_bus_subr.h>
59
60#ifdef EXT_RESOURCES
61#include <dev/extres/clk/clk.h>
62#endif
63
64#include <machine/bus.h>
65#include <machine/cpu.h>
66#include <machine/intr.h>
67
68#include <arm/freescale/vybrid/vf_common.h>
69
70#define	I2C_IBAD	0x0	/* I2C Bus Address Register */
71#define	I2C_IBFD	0x1	/* I2C Bus Frequency Divider Register */
72#define	I2C_IBCR	0x2	/* I2C Bus Control Register */
73#define	 IBCR_MDIS		(1 << 7) /* Module disable. */
74#define	 IBCR_IBIE		(1 << 6) /* I-Bus Interrupt Enable. */
75#define	 IBCR_MSSL		(1 << 5) /* Master/Slave mode select. */
76#define	 IBCR_TXRX		(1 << 4) /* Transmit/Receive mode select. */
77#define	 IBCR_NOACK		(1 << 3) /* Data Acknowledge disable. */
78#define	 IBCR_RSTA		(1 << 2) /* Repeat Start. */
79#define	 IBCR_DMAEN		(1 << 1) /* DMA Enable. */
80#define	I2C_IBSR	0x3	/* I2C Bus Status Register */
81#define	 IBSR_TCF		(1 << 7) /* Transfer complete. */
82#define	 IBSR_IAAS		(1 << 6) /* Addressed as a slave. */
83#define	 IBSR_IBB		(1 << 5) /* Bus busy. */
84#define	 IBSR_IBAL		(1 << 4) /* Arbitration Lost. */
85#define	 IBSR_SRW		(1 << 2) /* Slave Read/Write. */
86#define	 IBSR_IBIF		(1 << 1) /* I-Bus Interrupt Flag. */
87#define	 IBSR_RXAK		(1 << 0) /* Received Acknowledge. */
88#define	I2C_IBDR	0x4	/* I2C Bus Data I/O Register */
89#define	I2C_IBIC	0x5	/* I2C Bus Interrupt Config Register */
90#define	 IBIC_BIIE		(1 << 7) /* Bus Idle Interrupt Enable bit. */
91#define	I2C_IBDBG	0x6	/* I2C Bus Debug Register */
92
93#ifdef DEBUG
94#define vf_i2c_dbg(_sc, fmt, args...) \
95	device_printf((_sc)->dev, fmt, ##args)
96#else
97#define vf_i2c_dbg(_sc, fmt, args...)
98#endif
99
100#define	HW_UNKNOWN	0x00
101#define	HW_MVF600	0x01
102#define	HW_VF610	0x02
103
104static int i2c_repeated_start(device_t, u_char, int);
105static int i2c_start(device_t, u_char, int);
106static int i2c_stop(device_t);
107static int i2c_reset(device_t, u_char, u_char, u_char *);
108static int i2c_read(device_t, char *, int, int *, int, int);
109static int i2c_write(device_t, const char *, int, int *, int);
110static phandle_t i2c_get_node(device_t, device_t);
111
112struct i2c_div_type {
113	uint32_t reg_val;
114	uint32_t div;
115};
116
117struct i2c_softc {
118	struct resource		*res[2];
119	bus_space_tag_t		bst;
120	bus_space_handle_t	bsh;
121#ifdef EXT_RESOURCES
122	clk_t			clock;
123	uint32_t		freq;
124#endif
125	device_t		dev;
126	device_t		iicbus;
127	struct mtx		mutex;
128	uintptr_t		hwtype;
129};
130
131static struct resource_spec i2c_spec[] = {
132	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
133	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
134	{ -1, 0 }
135};
136
137#ifdef EXT_RESOURCES
138static struct i2c_div_type vf610_div_table[] = {
139	{ 0x00, 20 }, { 0x01, 22 }, { 0x02, 24 }, { 0x03, 26 },
140	{ 0x04, 28 }, { 0x05, 30 }, { 0x09, 32 }, { 0x06, 34 },
141	{ 0x0A, 36 }, { 0x0B, 40 }, { 0x0C, 44 }, { 0x0D, 48 },
142	{ 0x0E, 56 }, { 0x12, 64 }, { 0x13, 72 }, { 0x14, 80 },
143	{ 0x15, 88 }, { 0x19, 96 }, { 0x16, 104 }, { 0x1A, 112 },
144	{ 0x17, 128 }, { 0x1D, 160 }, { 0x1E, 192 }, { 0x22, 224 },
145	{ 0x1F, 240 }, { 0x23, 256 }, { 0x24, 288 }, { 0x25, 320 },
146	{ 0x26, 384 }, { 0x2A, 448 }, { 0x27, 480 }, { 0x2B, 512 },
147	{ 0x2C, 576 }, { 0x2D, 640 }, { 0x2E, 768 }, { 0x32, 896 },
148	{ 0x2F, 960 }, { 0x33, 1024 }, { 0x34, 1152 }, { 0x35, 1280 },
149	{ 0x36, 1536 }, { 0x3A, 1792 }, { 0x37, 1920 }, { 0x3B, 2048 },
150	{ 0x3C, 2304 }, { 0x3D, 2560 }, { 0x3E, 3072 }, { 0x3F, 3840 }
151};
152#endif
153
154static const struct ofw_compat_data i2c_compat_data[] = {
155	{"fsl,mvf600-i2c",	HW_MVF600},
156	{"fsl,vf610-i2c",	HW_VF610},
157	{NULL,			HW_UNKNOWN}
158};
159
160static int
161i2c_probe(device_t dev)
162{
163
164	if (!ofw_bus_status_okay(dev))
165		return (ENXIO);
166
167	if (!ofw_bus_search_compatible(dev, i2c_compat_data)->ocd_data)
168		return (ENXIO);
169
170	device_set_desc(dev, "Vybrid Family Inter-Integrated Circuit (I2C)");
171	return (BUS_PROBE_DEFAULT);
172}
173
174static int
175i2c_attach(device_t dev)
176{
177	struct i2c_softc *sc;
178#ifdef EXT_RESOURCES
179	phandle_t node;
180#endif
181	int error;
182
183	sc = device_get_softc(dev);
184	sc->dev = dev;
185	sc->hwtype = ofw_bus_search_compatible(dev, i2c_compat_data)->ocd_data;
186#ifdef EXT_RESOURCES
187	node = ofw_bus_get_node(dev);
188
189	error = clk_get_by_ofw_index(dev, node, 0, &sc->clock);
190	if (error != 0) {
191		sc->freq = 0;
192		device_printf(dev, "Parent clock not found.\n");
193	} else {
194		if (OF_hasprop(node, "clock-frequency"))
195			OF_getencprop(node, "clock-frequency", &sc->freq,
196			    sizeof(sc->freq));
197		else
198			sc->freq = 100000;
199	}
200#endif
201
202	mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF);
203
204	error = bus_alloc_resources(dev, i2c_spec, sc->res);
205	if (error != 0) {
206		mtx_destroy(&sc->mutex);
207		device_printf(dev, "could not allocate resources\n");
208		return (ENXIO);
209	}
210
211	/* Memory interface */
212	sc->bst = rman_get_bustag(sc->res[0]);
213	sc->bsh = rman_get_bushandle(sc->res[0]);
214
215	WRITE1(sc, I2C_IBIC, IBIC_BIIE);
216
217	sc->iicbus = device_add_child(dev, "iicbus", -1);
218	if (sc->iicbus == NULL) {
219		device_printf(dev, "could not add iicbus child");
220		mtx_destroy(&sc->mutex);
221		bus_release_resources(dev, i2c_spec, sc->res);
222		return (ENXIO);
223	}
224
225	bus_generic_attach(dev);
226
227	return (0);
228}
229
230static int
231i2c_detach(device_t dev)
232{
233	struct i2c_softc *sc;
234	int error = 0;
235
236	sc = device_get_softc(dev);
237
238	error = bus_generic_detach(dev);
239	if (error != 0) {
240		device_printf(dev, "cannot detach child devices.\n");
241		return (error);
242	}
243
244	error = device_delete_child(dev, sc->iicbus);
245	if (error != 0) {
246		device_printf(dev, "could not delete iicbus child.\n");
247		return (error);
248	}
249
250	bus_release_resources(dev, i2c_spec, sc->res);
251
252	mtx_destroy(&sc->mutex);
253
254	return (0);
255}
256
257/* Wait for transfer interrupt flag */
258static int
259wait_for_iif(struct i2c_softc *sc)
260{
261	int retry;
262
263	retry = 1000;
264	while (retry --) {
265		if (READ1(sc, I2C_IBSR) & IBSR_IBIF) {
266			WRITE1(sc, I2C_IBSR, IBSR_IBIF);
267			return (IIC_NOERR);
268		}
269		DELAY(10);
270	}
271
272	return (IIC_ETIMEOUT);
273}
274
275/* Wait for free bus */
276static int
277wait_for_nibb(struct i2c_softc *sc)
278{
279	int retry;
280
281	retry = 1000;
282	while (retry --) {
283		if ((READ1(sc, I2C_IBSR) & IBSR_IBB) == 0)
284			return (IIC_NOERR);
285		DELAY(10);
286	}
287
288	return (IIC_ETIMEOUT);
289}
290
291/* Wait for transfer complete+interrupt flag */
292static int
293wait_for_icf(struct i2c_softc *sc)
294{
295	int retry;
296
297	retry = 1000;
298	while (retry --) {
299		if (READ1(sc, I2C_IBSR) & IBSR_TCF) {
300			if (READ1(sc, I2C_IBSR) & IBSR_IBIF) {
301				WRITE1(sc, I2C_IBSR, IBSR_IBIF);
302				return (IIC_NOERR);
303			}
304		}
305		DELAY(10);
306	}
307
308	return (IIC_ETIMEOUT);
309}
310
311static int
312i2c_repeated_start(device_t dev, u_char slave, int timeout)
313{
314	struct i2c_softc *sc;
315	int error;
316	int reg;
317
318	sc = device_get_softc(dev);
319
320	vf_i2c_dbg(sc, "i2c repeated start\n");
321
322	mtx_lock(&sc->mutex);
323
324	WRITE1(sc, I2C_IBAD, slave);
325
326	if ((READ1(sc, I2C_IBSR) & IBSR_IBB) == 0) {
327		mtx_unlock(&sc->mutex);
328		return (IIC_EBUSERR);
329	}
330
331	/* Set repeated start condition */
332	DELAY(10);
333
334	reg = READ1(sc, I2C_IBCR);
335	reg |= (IBCR_RSTA | IBCR_IBIE);
336	WRITE1(sc, I2C_IBCR, reg);
337
338	DELAY(10);
339
340	/* Write target address - LSB is R/W bit */
341	WRITE1(sc, I2C_IBDR, slave);
342
343	error = wait_for_iif(sc);
344
345	mtx_unlock(&sc->mutex);
346
347	if (error != 0)
348		return (error);
349
350	return (IIC_NOERR);
351}
352
353static int
354i2c_start(device_t dev, u_char slave, int timeout)
355{
356	struct i2c_softc *sc;
357	int error;
358	int reg;
359
360	sc = device_get_softc(dev);
361
362	vf_i2c_dbg(sc, "i2c start\n");
363
364	mtx_lock(&sc->mutex);
365
366	WRITE1(sc, I2C_IBAD, slave);
367
368	if (READ1(sc, I2C_IBSR) & IBSR_IBB) {
369		mtx_unlock(&sc->mutex);
370		vf_i2c_dbg(sc, "cant i2c start: IIC_EBUSBSY\n");
371		return (IIC_EBUSERR);
372	}
373
374	/* Set start condition */
375	reg = (IBCR_MSSL | IBCR_NOACK | IBCR_IBIE);
376	WRITE1(sc, I2C_IBCR, reg);
377
378	DELAY(100);
379
380	reg |= (IBCR_TXRX);
381	WRITE1(sc, I2C_IBCR, reg);
382
383	/* Write target address - LSB is R/W bit */
384	WRITE1(sc, I2C_IBDR, slave);
385
386	error = wait_for_iif(sc);
387
388	mtx_unlock(&sc->mutex);
389	if (error != 0) {
390		vf_i2c_dbg(sc, "cant i2c start: iif error\n");
391		return (error);
392	}
393
394	return (IIC_NOERR);
395}
396
397static int
398i2c_stop(device_t dev)
399{
400	struct i2c_softc *sc;
401
402	sc = device_get_softc(dev);
403
404	vf_i2c_dbg(sc, "i2c stop\n");
405
406	mtx_lock(&sc->mutex);
407
408	WRITE1(sc, I2C_IBCR, IBCR_NOACK | IBCR_IBIE);
409
410	DELAY(100);
411
412	/* Reset controller if bus still busy after STOP */
413	if (wait_for_nibb(sc) == IIC_ETIMEOUT) {
414		WRITE1(sc, I2C_IBCR, IBCR_MDIS);
415		DELAY(1000);
416		WRITE1(sc, I2C_IBCR, IBCR_NOACK);
417	}
418	mtx_unlock(&sc->mutex);
419
420	return (IIC_NOERR);
421}
422
423static uint32_t
424i2c_get_div_val(device_t dev)
425{
426	struct i2c_softc *sc;
427#ifdef EXT_RESOURCES
428	uint64_t clk_freq;
429	int error, i;
430
431	sc = device_get_softc(dev);
432
433	if (sc->hwtype == HW_MVF600)
434		return 20;
435
436	if (sc->freq == 0)
437		return vf610_div_table[nitems(vf610_div_table) - 1].reg_val;
438
439	error = clk_get_freq(sc->clock, &clk_freq);
440	if (error != 0) {
441		device_printf(dev, "Could not get parent clock frequency. "
442		    "Using default divider.\n");
443		return vf610_div_table[nitems(vf610_div_table) - 1].reg_val;
444	}
445
446	for (i = 0; i < nitems(vf610_div_table) - 1; i++)
447		if ((clk_freq / vf610_div_table[i].div) <= sc->freq)
448			break;
449
450	return vf610_div_table[i].reg_val;
451#else
452	sc = device_get_softc(dev);
453
454	if (sc->hwtype == HW_VF610)
455		return 0x3F;
456	else
457		return 20;
458#endif
459}
460
461static int
462i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr)
463{
464	struct i2c_softc *sc;
465	uint32_t div;
466
467	sc = device_get_softc(dev);
468	div = i2c_get_div_val(dev);
469	vf_i2c_dbg(sc, "Div val: %02x\n", div);
470
471	vf_i2c_dbg(sc, "i2c reset\n");
472
473	switch (speed) {
474	case IIC_FAST:
475	case IIC_SLOW:
476	case IIC_UNKNOWN:
477	case IIC_FASTEST:
478	default:
479		break;
480	}
481
482	mtx_lock(&sc->mutex);
483	WRITE1(sc, I2C_IBCR, IBCR_MDIS);
484
485	DELAY(1000);
486
487	WRITE1(sc, I2C_IBFD, div);
488	WRITE1(sc, I2C_IBCR, 0x0); /* Enable i2c */
489
490	DELAY(1000);
491
492	mtx_unlock(&sc->mutex);
493
494	return (IIC_NOERR);
495}
496
497static int
498i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay)
499{
500	struct i2c_softc *sc;
501	int error;
502
503	sc = device_get_softc(dev);
504
505	vf_i2c_dbg(sc, "i2c read\n");
506
507	*read = 0;
508
509	mtx_lock(&sc->mutex);
510
511	if (len) {
512		if (len == 1)
513			WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL |	\
514			    IBCR_NOACK);
515		else
516			WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL);
517
518		/* dummy read */
519		READ1(sc, I2C_IBDR);
520		DELAY(1000);
521	}
522
523	while (*read < len) {
524		error = wait_for_icf(sc);
525		if (error != 0) {
526			mtx_unlock(&sc->mutex);
527			return (error);
528		}
529
530		if ((*read == len - 2) && last) {
531			/* NO ACK on last byte */
532			WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_MSSL |	\
533			    IBCR_NOACK);
534		}
535
536		if ((*read == len - 1) && last) {
537			/* Transfer done, remove master bit */
538			WRITE1(sc, I2C_IBCR, IBCR_IBIE | IBCR_NOACK);
539		}
540
541		*buf++ = READ1(sc, I2C_IBDR);
542		(*read)++;
543	}
544	mtx_unlock(&sc->mutex);
545
546	return (IIC_NOERR);
547}
548
549static int
550i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout)
551{
552	struct i2c_softc *sc;
553	int error;
554
555	sc = device_get_softc(dev);
556
557	vf_i2c_dbg(sc, "i2c write\n");
558
559	*sent = 0;
560
561	mtx_lock(&sc->mutex);
562	while (*sent < len) {
563		WRITE1(sc, I2C_IBDR, *buf++);
564
565		error = wait_for_iif(sc);
566		if (error != 0) {
567			mtx_unlock(&sc->mutex);
568			return (error);
569		}
570
571		(*sent)++;
572	}
573	mtx_unlock(&sc->mutex);
574
575	return (IIC_NOERR);
576}
577
578static phandle_t
579i2c_get_node(device_t bus, device_t dev)
580{
581
582	return ofw_bus_get_node(bus);
583}
584
585static device_method_t i2c_methods[] = {
586	DEVMETHOD(device_probe,			i2c_probe),
587	DEVMETHOD(device_attach,		i2c_attach),
588	DEVMETHOD(device_detach,		i2c_detach),
589
590	DEVMETHOD(ofw_bus_get_node,		i2c_get_node),
591
592	DEVMETHOD(iicbus_callback,		iicbus_null_callback),
593	DEVMETHOD(iicbus_repeated_start,	i2c_repeated_start),
594	DEVMETHOD(iicbus_start,			i2c_start),
595	DEVMETHOD(iicbus_stop,			i2c_stop),
596	DEVMETHOD(iicbus_reset,			i2c_reset),
597	DEVMETHOD(iicbus_read,			i2c_read),
598	DEVMETHOD(iicbus_write,			i2c_write),
599	DEVMETHOD(iicbus_transfer,		iicbus_transfer_gen),
600	{ 0, 0 }
601};
602
603static driver_t i2c_driver = {
604	"i2c",
605	i2c_methods,
606	sizeof(struct i2c_softc),
607};
608
609static devclass_t i2c_devclass;
610
611DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0);
612DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0);
613DRIVER_MODULE(ofw_iicbus, i2c, ofw_iicbus_driver, ofw_iicbus_devclass, 0, 0);
614