1//===- llvm/CodeGen/GlobalISel/CallLowering.h - Call lowering ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file describes how to lower LLVM calls to machine code calls.
11///
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H
15#define LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H
16
17#include "llvm/ADT/ArrayRef.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/CodeGen/CallingConvLower.h"
20#include "llvm/CodeGen/TargetCallingConv.h"
21#include "llvm/IR/CallingConv.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/MachineValueType.h"
24#include <cstdint>
25#include <functional>
26
27namespace llvm {
28
29class CCState;
30class CallBase;
31class DataLayout;
32class Function;
33class MachineIRBuilder;
34class MachineOperand;
35struct MachinePointerInfo;
36class MachineRegisterInfo;
37class TargetLowering;
38class Type;
39class Value;
40
41class CallLowering {
42  const TargetLowering *TLI;
43
44  virtual void anchor();
45public:
46  struct ArgInfo {
47    SmallVector<Register, 4> Regs;
48    // If the argument had to be split into multiple parts according to the
49    // target calling convention, then this contains the original vregs
50    // if the argument was an incoming arg.
51    SmallVector<Register, 2> OrigRegs;
52    Type *Ty;
53    SmallVector<ISD::ArgFlagsTy, 4> Flags;
54    bool IsFixed;
55
56    ArgInfo(ArrayRef<Register> Regs, Type *Ty,
57            ArrayRef<ISD::ArgFlagsTy> Flags = ArrayRef<ISD::ArgFlagsTy>(),
58            bool IsFixed = true)
59        : Regs(Regs.begin(), Regs.end()), Ty(Ty),
60          Flags(Flags.begin(), Flags.end()), IsFixed(IsFixed) {
61      if (!Regs.empty() && Flags.empty())
62        this->Flags.push_back(ISD::ArgFlagsTy());
63      // FIXME: We should have just one way of saying "no register".
64      assert(((Ty->isVoidTy() || Ty->isEmptyTy()) ==
65              (Regs.empty() || Regs[0] == 0)) &&
66             "only void types should have no register");
67    }
68
69    ArgInfo() : Ty(nullptr), IsFixed(false) {}
70  };
71
72  struct CallLoweringInfo {
73    /// Calling convention to be used for the call.
74    CallingConv::ID CallConv = CallingConv::C;
75
76    /// Destination of the call. It should be either a register, globaladdress,
77    /// or externalsymbol.
78    MachineOperand Callee = MachineOperand::CreateImm(0);
79
80    /// Descriptor for the return type of the function.
81    ArgInfo OrigRet;
82
83    /// List of descriptors of the arguments passed to the function.
84    SmallVector<ArgInfo, 8> OrigArgs;
85
86    /// Valid if the call has a swifterror inout parameter, and contains the
87    /// vreg that the swifterror should be copied into after the call.
88    Register SwiftErrorVReg;
89
90    MDNode *KnownCallees = nullptr;
91
92    /// True if the call must be tail call optimized.
93    bool IsMustTailCall = false;
94
95    /// True if the call passes all target-independent checks for tail call
96    /// optimization.
97    bool IsTailCall = false;
98
99    /// True if the call was lowered as a tail call. This is consumed by the
100    /// legalizer. This allows the legalizer to lower libcalls as tail calls.
101    bool LoweredTailCall = false;
102
103    /// True if the call is to a vararg function.
104    bool IsVarArg = false;
105  };
106
107  /// Argument handling is mostly uniform between the four places that
108  /// make these decisions: function formal arguments, call
109  /// instruction args, call instruction returns and function
110  /// returns. However, once a decision has been made on where an
111  /// argument should go, exactly what happens can vary slightly. This
112  /// class abstracts the differences.
113  struct ValueHandler {
114    ValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
115                 CCAssignFn *AssignFn)
116      : MIRBuilder(MIRBuilder), MRI(MRI), AssignFn(AssignFn) {}
117
118    virtual ~ValueHandler() = default;
119
120    /// Returns true if the handler is dealing with incoming arguments,
121    /// i.e. those that move values from some physical location to vregs.
122    virtual bool isIncomingArgumentHandler() const = 0;
123
124    /// Materialize a VReg containing the address of the specified
125    /// stack-based object. This is either based on a FrameIndex or
126    /// direct SP manipulation, depending on the context. \p MPO
127    /// should be initialized to an appropriate description of the
128    /// address created.
129    virtual Register getStackAddress(uint64_t Size, int64_t Offset,
130                                     MachinePointerInfo &MPO) = 0;
131
132    /// The specified value has been assigned to a physical register,
133    /// handle the appropriate COPY (either to or from) and mark any
134    /// relevant uses/defines as needed.
135    virtual void assignValueToReg(Register ValVReg, Register PhysReg,
136                                  CCValAssign &VA) = 0;
137
138    /// The specified value has been assigned to a stack
139    /// location. Load or store it there, with appropriate extension
140    /// if necessary.
141    virtual void assignValueToAddress(Register ValVReg, Register Addr,
142                                      uint64_t Size, MachinePointerInfo &MPO,
143                                      CCValAssign &VA) = 0;
144
145    /// An overload which takes an ArgInfo if additional information about
146    /// the arg is needed.
147    virtual void assignValueToAddress(const ArgInfo &Arg, Register Addr,
148                                      uint64_t Size, MachinePointerInfo &MPO,
149                                      CCValAssign &VA) {
150      assignValueToAddress(Arg.Regs[0], Addr, Size, MPO, VA);
151    }
152
153    /// Handle custom values, which may be passed into one or more of \p VAs.
154    /// \return The number of \p VAs that have been assigned after the first
155    ///         one, and which should therefore be skipped from further
156    ///         processing.
157    virtual unsigned assignCustomValue(const ArgInfo &Arg,
158                                       ArrayRef<CCValAssign> VAs) {
159      // This is not a pure virtual method because not all targets need to worry
160      // about custom values.
161      llvm_unreachable("Custom values not supported");
162    }
163
164    /// Extend a register to the location type given in VA, capped at extending
165    /// to at most MaxSize bits. If MaxSizeBits is 0 then no maximum is set.
166    Register extendRegister(Register ValReg, CCValAssign &VA,
167                            unsigned MaxSizeBits = 0);
168
169    virtual bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
170                           CCValAssign::LocInfo LocInfo, const ArgInfo &Info,
171                           ISD::ArgFlagsTy Flags, CCState &State) {
172      return AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
173    }
174
175    MachineIRBuilder &MIRBuilder;
176    MachineRegisterInfo &MRI;
177    CCAssignFn *AssignFn;
178
179  private:
180    virtual void anchor();
181  };
182
183protected:
184  /// Getter for generic TargetLowering class.
185  const TargetLowering *getTLI() const {
186    return TLI;
187  }
188
189  /// Getter for target specific TargetLowering class.
190  template <class XXXTargetLowering>
191    const XXXTargetLowering *getTLI() const {
192    return static_cast<const XXXTargetLowering *>(TLI);
193  }
194
195  template <typename FuncInfoTy>
196  void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL,
197                   const FuncInfoTy &FuncInfo) const;
198
199  /// Generate instructions for packing \p SrcRegs into one big register
200  /// corresponding to the aggregate type \p PackedTy.
201  ///
202  /// \param SrcRegs should contain one virtual register for each base type in
203  ///                \p PackedTy, as returned by computeValueLLTs.
204  ///
205  /// \return The packed register.
206  Register packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy,
207                    MachineIRBuilder &MIRBuilder) const;
208
209  /// Generate instructions for unpacking \p SrcReg into the \p DstRegs
210  /// corresponding to the aggregate type \p PackedTy.
211  ///
212  /// \param DstRegs should contain one virtual register for each base type in
213  ///        \p PackedTy, as returned by computeValueLLTs.
214  void unpackRegs(ArrayRef<Register> DstRegs, Register SrcReg, Type *PackedTy,
215                  MachineIRBuilder &MIRBuilder) const;
216
217  /// Invoke Handler::assignArg on each of the given \p Args and then use
218  /// \p Callback to move them to the assigned locations.
219  ///
220  /// \return True if everything has succeeded, false otherwise.
221  bool handleAssignments(MachineIRBuilder &MIRBuilder,
222                         SmallVectorImpl<ArgInfo> &Args,
223                         ValueHandler &Handler) const;
224  bool handleAssignments(CCState &CCState,
225                         SmallVectorImpl<CCValAssign> &ArgLocs,
226                         MachineIRBuilder &MIRBuilder,
227                         SmallVectorImpl<ArgInfo> &Args,
228                         ValueHandler &Handler) const;
229
230  /// Analyze passed or returned values from a call, supplied in \p ArgInfo,
231  /// incorporating info about the passed values into \p CCState.
232  ///
233  /// Used to check if arguments are suitable for tail call lowering.
234  bool analyzeArgInfo(CCState &CCState, SmallVectorImpl<ArgInfo> &Args,
235                      CCAssignFn &AssignFnFixed,
236                      CCAssignFn &AssignFnVarArg) const;
237
238  /// \returns True if the calling convention for a callee and its caller pass
239  /// results in the same way. Typically used for tail call eligibility checks.
240  ///
241  /// \p Info is the CallLoweringInfo for the call.
242  /// \p MF is the MachineFunction for the caller.
243  /// \p InArgs contains the results of the call.
244  /// \p CalleeAssignFnFixed is the CCAssignFn to be used for the callee for
245  /// fixed arguments.
246  /// \p CalleeAssignFnVarArg is similar, but for varargs.
247  /// \p CallerAssignFnFixed is the CCAssignFn to be used for the caller for
248  /// fixed arguments.
249  /// \p CallerAssignFnVarArg is similar, but for varargs.
250  bool resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF,
251                         SmallVectorImpl<ArgInfo> &InArgs,
252                         CCAssignFn &CalleeAssignFnFixed,
253                         CCAssignFn &CalleeAssignFnVarArg,
254                         CCAssignFn &CallerAssignFnFixed,
255                         CCAssignFn &CallerAssignFnVarArg) const;
256
257public:
258  CallLowering(const TargetLowering *TLI) : TLI(TLI) {}
259  virtual ~CallLowering() = default;
260
261  /// \return true if the target is capable of handling swifterror values that
262  /// have been promoted to a specified register. The extended versions of
263  /// lowerReturn and lowerCall should be implemented.
264  virtual bool supportSwiftError() const {
265    return false;
266  }
267
268  /// This hook must be implemented to lower outgoing return values, described
269  /// by \p Val, into the specified virtual registers \p VRegs.
270  /// This hook is used by GlobalISel.
271  ///
272  /// \p SwiftErrorVReg is non-zero if the function has a swifterror parameter
273  /// that needs to be implicitly returned.
274  ///
275  /// \return True if the lowering succeeds, false otherwise.
276  virtual bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
277                           ArrayRef<Register> VRegs,
278                           Register SwiftErrorVReg) const {
279    if (!supportSwiftError()) {
280      assert(SwiftErrorVReg == 0 && "attempt to use unsupported swifterror");
281      return lowerReturn(MIRBuilder, Val, VRegs);
282    }
283    return false;
284  }
285
286  /// This hook behaves as the extended lowerReturn function, but for targets
287  /// that do not support swifterror value promotion.
288  virtual bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
289                           ArrayRef<Register> VRegs) const {
290    return false;
291  }
292
293  virtual bool fallBackToDAGISel(const Function &F) const { return false; }
294
295  /// This hook must be implemented to lower the incoming (formal)
296  /// arguments, described by \p VRegs, for GlobalISel. Each argument
297  /// must end up in the related virtual registers described by \p VRegs.
298  /// In other words, the first argument should end up in \c VRegs[0],
299  /// the second in \c VRegs[1], and so on. For each argument, there will be one
300  /// register for each non-aggregate type, as returned by \c computeValueLLTs.
301  /// \p MIRBuilder is set to the proper insertion for the argument
302  /// lowering.
303  ///
304  /// \return True if the lowering succeeded, false otherwise.
305  virtual bool lowerFormalArguments(MachineIRBuilder &MIRBuilder,
306                                    const Function &F,
307                                    ArrayRef<ArrayRef<Register>> VRegs) const {
308    return false;
309  }
310
311  /// This hook must be implemented to lower the given call instruction,
312  /// including argument and return value marshalling.
313  ///
314  ///
315  /// \return true if the lowering succeeded, false otherwise.
316  virtual bool lowerCall(MachineIRBuilder &MIRBuilder,
317                         CallLoweringInfo &Info) const {
318    return false;
319  }
320
321  /// Lower the given call instruction, including argument and return value
322  /// marshalling.
323  ///
324  /// \p CI is the call/invoke instruction.
325  ///
326  /// \p ResRegs are the registers where the call's return value should be
327  /// stored (or 0 if there is no return value). There will be one register for
328  /// each non-aggregate type, as returned by \c computeValueLLTs.
329  ///
330  /// \p ArgRegs is a list of lists of virtual registers containing each
331  /// argument that needs to be passed (argument \c i should be placed in \c
332  /// ArgRegs[i]). For each argument, there will be one register for each
333  /// non-aggregate type, as returned by \c computeValueLLTs.
334  ///
335  /// \p SwiftErrorVReg is non-zero if the call has a swifterror inout
336  /// parameter, and contains the vreg that the swifterror should be copied into
337  /// after the call.
338  ///
339  /// \p GetCalleeReg is a callback to materialize a register for the callee if
340  /// the target determines it cannot jump to the destination based purely on \p
341  /// CI. This might be because \p CI is indirect, or because of the limited
342  /// range of an immediate jump.
343  ///
344  /// \return true if the lowering succeeded, false otherwise.
345  bool lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &Call,
346                 ArrayRef<Register> ResRegs,
347                 ArrayRef<ArrayRef<Register>> ArgRegs, Register SwiftErrorVReg,
348                 std::function<unsigned()> GetCalleeReg) const;
349};
350
351} // end namespace llvm
352
353#endif // LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H
354