Searched refs:xsave (Results 1 - 20 of 20) sorted by relevance

/illumos-gate/usr/src/test/util-tests/tests/dis/i386/
H A D32.xsave.s17 * Test 32-bit xsave related instructions
25 xsave (%eax)
H A D64.xsave.s17 * Test 64-bit xsave related instructions
25 xsave (%rax)
/illumos-gate/usr/src/lib/libxcurses2/src/libc/xcurses/
H A Dwadd_wch.c55 int xsave = w->_curx; local
60 w->_curx = (short) xsave;
/illumos-gate/usr/src/uts/intel/ia32/ml/
H A Dfloat.s114 * These three functions define the Intel "xsave" handling for CPUs with
133 movl FPU_CTX_FPU_XSAVE_MASK(%rdi), %eax /* xsave flags in EDX:EAX */
136 xsave (%rsi)
145 movl FPU_CTX_FPU_XSAVE_MASK(%rdi), %eax /* xsave flags in EDX:EAX */
156 * fxsave, xsave or xsaveopt instruction ONLY if the exception summary bit is
163 * the same logic after the xsave* instruction.
195 xsave (%rsi)
244 xsave(struct xsave_state *f, uint64_t m)
262 ENTRY_NP(xsave) function
267 xsave (
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/illumos-gate/usr/src/uts/intel/sys/
H A Dfp.h66 #define FP_XSAVE 3 /* xsave/xrstor instructions */
233 * This structure is written to memory by one of the 'xsave' instruction
235 * area. The header portion of the xsave layout is documented in section
240 * statically. Enabling additional xsave-related CPU features requires an
241 * increase in the size. We dynamically allocate the per-lwp xsave area at
244 * of the xsave area. The locations and size of new, extended, components is
248 * xsave component usage is tracked using bits in the xs_xstate_bv field. The
263 * elements of the xsave area are active.
266 * form of xsave (xsavec).
270 uint64_t xs_xstate_bv; /* 512-519 start xsave heade
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/illumos-gate/usr/src/lib/libmvec/common/vis/
H A D__vsincos.S51 #define xsave STACK_BIAS-0x8 define
138 stx %i1,[%fp+xsave] ! save arguments
143 st %i1,[%fp+xsave] ! save arguments
791 ldx [%fp+xsave],%o1
798 ld [%fp+xsave],%o1
H A D__vsincosf.S72 #define xsave STACK_BIAS-0x8 define
157 stx %i1,[%fp+xsave] ! save arguments
162 st %i1,[%fp+xsave] ! save arguments
687 ldx [%fp+xsave],%o1
693 ld [%fp+xsave],%o1
H A D__vcosf.S72 #define xsave STACK_BIAS-0x8 define
156 stx %i1,[%fp+xsave] ! save arguments
159 st %i1,[%fp+xsave] ! save arguments
1916 ldx [%fp+xsave],%o1
1919 ld [%fp+xsave],%o1
H A D__vsinf.S72 #define xsave STACK_BIAS-0x8 define
156 stx %i1,[%fp+xsave] ! save arguments
159 st %i1,[%fp+xsave] ! save arguments
1908 ldx [%fp+xsave],%o1
1911 ld [%fp+xsave],%o1
H A D__vsin.S85 #define xsave STACK_BIAS-0x8 define
190 stx %i1,[%fp+xsave] ! save arguments
193 st %i1,[%fp+xsave] ! save arguments
2875 ldx [%fp+xsave],%o1
2878 ld [%fp+xsave],%o1
H A D__vcos.S85 #define xsave STACK_BIAS-0x8 define
260 stx %i1,[%fp+xsave] ! save arguments
263 st %i1,[%fp+xsave] ! save arguments
2951 ldx [%fp+xsave],%o1
2954 ld [%fp+xsave],%o1
H A D__vcos_ultra3.S54 #define xsave STACK_BIAS-0x8 define
141 stx %i1,[%fp+xsave] ! save arguments
144 st %i1,[%fp+xsave] ! save arguments
3236 ldx [%fp+xsave],%o1
3239 ld [%fp+xsave],%o1
H A D__vsin_ultra3.S54 #define xsave STACK_BIAS-0x8 define
141 stx %i1,[%fp+xsave] ! save arguments
144 st %i1,[%fp+xsave] ! save arguments
3247 ldx [%fp+xsave],%o1
3250 ld [%fp+xsave],%o1
/illumos-gate/usr/src/lib/libmvec/common/
H A D__vcosbig_ultra3.c79 double x0, x1, x2, *py0, *py1, *py2, *xsave, *ysave; local
84 xsave = x;
652 __vlibm_vcos_big(nsave, xsave, sxsave, ysave, sysave, 0x413921fb);
H A D__vsinbig_ultra3.c79 double x0, x1, x2, *py0, *py1, *py2, *xsave, *ysave; local
84 xsave = x;
652 __vlibm_vsin_big(nsave, xsave, sxsave, ysave, sysave, 0x413921fb);
H A D__vcos.c102 double x0, x1, x2, *py0 = 0, *py1 = 0, *py2, *xsave, *ysave; local
107 xsave = x;
1100 __vlibm_vcos_big(nsave, xsave, sxsave, ysave, sysave, 0x413921fb);
H A D__vsin.c82 double x0, x1, x2, *py0 = 0, *py1 = 0, *py2, *xsave, *ysave; local
87 xsave = x;
1108 __vlibm_vsin_big(nsave, xsave, sxsave, ysave, sysave, 0x413921fb);
H A D__vsincos.c99 *xsave, *ysave, *csave; local
104 xsave = x;
702 x = xsave;
1545 __vlibm_vsincos_big(nsave, xsave, sxsave, ysave, sysave, csave, scsave, 0x413921fb);
/illumos-gate/usr/src/uts/intel/ia32/os/
H A Dfpu.c136 * supports the execution of the xsave and xrstor family of
142 * CR4.OSXSAVE will be enabled and used whenever xsave is reported in cpuid.
144 * %xcr0 is used to manage the behavior of the xsave feature set and is only
145 * present on the system if xsave is supported. %xcr0 is read and written to
147 * whenever the xsave feature set is supported. Each bit in %xcr0 refers to a
148 * different component of the xsave state and controls whether or not that
155 * part of the xsave state. Bits that can be set in %xcr0 are reserved in
157 * relevant to how the xsave instructions operate.
169 * o xsave
182 * The final and by far the most complex mechanism is that of the xsave se
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/illumos-gate/usr/src/cmd/sgs/rtld/amd64/
H A Dboot_elf.s81 * To deal with this problem, Intel has suggested using the xsave family of
125 * This macro is used to zero the xsave header. The contents of scratchreg will
126 * be destroyed. locreg should contain the starting address of the xsave header.
255 xsave (%rdi) /* save data */

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