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/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A Dmisc_bits.h41 #define MISCS_REGISTERS_RESET_CONFIG_NCSI (0x1<<0)
42 #define MISCS_REGISTERS_RESET_CONFIG_UMAC (0x1<<1)
43 #define MISCS_REGISTERS_RESET_CONFIG_MSTAT (0x1<<2)
44 #define MISCS_REGISTERS_RESET_CONFIG_CPMU (0x1<<3)
45 #define MISCS_REGISTERS_RESET_CONFIG_PXPV_AUTO_MODE (0x1<<4)
46 #define MISCS_REGISTERS_RESET_CONFIG_NWM_MAC_CORE (0x1<<5)
47 #define MISCS_REGISTERS_RESET_CONFIG_RSRV6 (0x1<<6)
48 #define MISCS_REGISTERS_RESET_CONFIG_RST_MCP_N_RESET_REG_HARD_CORE_AUTO_MODE (0x1<<7)
49 #define MISCS_REGISTERS_RESET_CONFIG_RST_MCP_N_HARD_CORE_RST_B_AUTO_MODE (0x1<<8)
50 #define MISCS_REGISTERS_RESET_CONFIG_RST_MCP_N_RESET_CMN_CPU_AUTO_MODE (0x1<<
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H A Dreg_addr_e5.h40 #define PGLCS_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42 #define PGLCS_REG_INT_STS_RASDP_ERROR (0x1<<1) // It indicates rasdp error
45 #define PGLCS_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PGLCS_REG_INT_STS.ADDRESS_ERROR .
47 #define PGLCS_REG_INT_MASK_RASDP_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: PGLCS_REG_INT_STS.RASDP_ERROR .
50 #define PGLCS_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
52 #define PGLCS_REG_INT_STS_WR_RASDP_ERROR (0x1<<1) // It indicates rasdp error
55 #define PGLCS_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
57 #define PGLCS_REG_INT_STS_CLR_RASDP_ERROR (0x1<<1) // It indicates rasdp error
59 #define PGLCS_REG_RASDP_ERROR_MODE_EN_OFF 0x001d10UL //Access:RW DataWidth:0x1 // Disable rasdp error mode check
99 #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN (0x1<<
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H A Dreg_addr_k2.h40 #define PGLCS_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42 #define PGLCS_REG_INT_STS_RASDP_ERROR (0x1<<1) // It indicates rasdp error
45 #define PGLCS_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PGLCS_REG_INT_STS.ADDRESS_ERROR .
47 #define PGLCS_REG_INT_MASK_RASDP_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: PGLCS_REG_INT_STS.RASDP_ERROR .
50 #define PGLCS_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
52 #define PGLCS_REG_INT_STS_WR_RASDP_ERROR (0x1<<1) // It indicates rasdp error
55 #define PGLCS_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
57 #define PGLCS_REG_INT_STS_CLR_RASDP_ERROR (0x1<<1) // It indicates rasdp error
59 #define PGLCS_REG_RASDP_ERROR_MODE_EN_OFF 0x001d10UL //Access:RW DataWidth:0x1 // Disable rasdp error mode check
99 #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN (0x1<<
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H A Dreg_addr_bb.h39 #define PGLCS_REG_INT_STS 0x001d00UL //Access:R DataWidth:0x1 // Multi Field Register.
40 #define PGLCS_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42 #define PGLCS_REG_INT_STS_RASDP_ERROR (0x1<<1) // It indicates rasdp error
44 #define PGLCS_REG_INT_MASK 0x001d04UL //Access:RW DataWidth:0x1 // Multi Field Register.
45 #define PGLCS_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PGLCS_REG_INT_STS.ADDRESS_ERROR .
47 #define PGLCS_REG_INT_MASK_RASDP_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: PGLCS_REG_INT_STS.RASDP_ERROR .
49 #define PGLCS_REG_INT_STS_WR 0x001d08UL //Access:WR DataWidth:0x1 // Multi Field Register.
50 #define PGLCS_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
52 #define PGLCS_REG_INT_STS_WR_RASDP_ERROR (0x1<<1) // It indicates rasdp error
54 #define PGLCS_REG_INT_STS_CLR 0x001d0cUL //Access:RC DataWidth:0x1 // Mult
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H A Dreg_addr_ah_compile15.h40 #define PGLCS_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42 #define PGLCS_REG_INT_STS_RASDP_ERROR (0x1<<1) // It indicates rasdp error
45 #define PGLCS_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PGLCS_REG_INT_STS.ADDRESS_ERROR .
47 #define PGLCS_REG_INT_MASK_RASDP_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: PGLCS_REG_INT_STS.RASDP_ERROR .
50 #define PGLCS_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
52 #define PGLCS_REG_INT_STS_WR_RASDP_ERROR (0x1<<1) // It indicates rasdp error
55 #define PGLCS_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
57 #define PGLCS_REG_INT_STS_CLR_RASDP_ERROR (0x1<<1) // It indicates rasdp error
59 #define PGLCS_REG_RASDP_ERROR_MODE_EN_OFF 0x001d10UL //Access:RW DataWidth:0x1 Disable rasdp error mode check Chips: K2
96 #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN (0x1<<
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H A Dreg_addr.h40 #define PGLCS_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
42 #define PGLCS_REG_INT_STS_RASDP_ERROR_K2_E5 (0x1<<1) // It indicates rasdp error
45 #define PGLCS_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PGLCS_REG_INT_STS.ADDRESS_ERROR .
47 #define PGLCS_REG_INT_MASK_RASDP_ERROR_K2_E5 (0x1<<1) // This bit masks, when set, the Interrupt bit: PGLCS_REG_INT_STS.RASDP_ERROR .
50 #define PGLCS_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
52 #define PGLCS_REG_INT_STS_WR_RASDP_ERROR_K2_E5 (0x1<<1) // It indicates rasdp error
55 #define PGLCS_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
57 #define PGLCS_REG_INT_STS_CLR_RASDP_ERROR_K2_E5 (0x1<<1) // It indicates rasdp error
59 #define PGLCS_REG_RASDP_ERROR_MODE_EN_OFF_K2_E5 0x001d10UL //Access:RW DataWidth:0x1 // Disable rasdp error mode check
100 #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_K2_E5 (0x1<<
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/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Daeu_inputs.h49 #define AEU_INPUTS_ATTN_BITS_NIG_ATTENTION_FOR_FUNCTION0 (0x1<<0)// Type: Event, Required Destination: MCP/Driver0
50 #define AEU_INPUTS_ATTN_BITS_NIG_ATTENTION_FOR_FUNCTION1 (0x1<<1)// Type: Event, Required Destination: MCP/Driver1
51 #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)// Type: Event, Required Destination: MCP
52 #define AEU_INPUTS_ATTN_BITS_GPIO1_FUNCTION_0 (0x1<<3)// Type: Event, Required Destination: MCP
53 #define AEU_INPUTS_ATTN_BITS_GPIO2_FUNCTION_0 (0x1<<4)// Type: Event, Required Destination: MCP
54 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5)// Type: Event, Required Destination: MCP
55 #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_1 (0x1<<6)// Type: Event, Required Destination: MCP
56 #define AEU_INPUTS_ATTN_BITS_GPIO1_FUNCTION_1 (0x1<<7)// Type: Event, Required Destination: MCP
57 #define AEU_INPUTS_ATTN_BITS_GPIO2_FUNCTION_1 (0x1<<8)// Type: Event, Required Destination: MCP
58 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<
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H A Dmisc_bits.h4 #define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0)
5 #define MISC_REGISTERS_RESET_REG_1_RST_PRS (0x1<<1)
6 #define MISC_REGISTERS_RESET_REG_1_RST_SRC (0x1<<2)
7 #define MISC_REGISTERS_RESET_REG_1_RST_TSDM (0x1<<3)
8 #define MISC_REGISTERS_RESET_REG_1_RST_TSEM (0x1<<4)
9 #define MISC_REGISTERS_RESET_REG_1_RST_TCM (0x1<<5)
10 #define MISC_REGISTERS_RESET_REG_1_RST_RBCR (0x1<<6)
11 #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
12 #define MISC_REGISTERS_RESET_REG_1_RST_USDM (0x1<<8)
13 #define MISC_REGISTERS_RESET_REG_1_RST_UCM (0x1<<
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H A D57712_reg.h4 #define ATC_REG_ATC_1_WAY 0x110004UL //ACCESS:RW DataWidth:0x1 Description: If set the ATC will use only one way per set
7 #define ATC_REG_ATC_WAIT_IF_MISS 0x110010UL //ACCESS:RW DataWidth:0x1 Description: WaitIfMiss configuration bit
8 #define ATC_REG_ATC_WAIT_IF_PENDING 0x110014UL //ACCESS:RW DataWidth:0x1 Description: WaitTransPending cofiguration bit
21 #define ATC_REG_ATC_DISABLE_BYPASS 0x110048UL //ACCESS:RW DataWidth:0x1 Description: disables the bypass on the GPA table
22 #define ATC_REG_ATC_ISSUE_4_CYCLES 0x11004cUL //ACCESS:RW DataWidth:0x1 Description: Issue event once in four cycles (instead of 2)
25 #define ATC_REG_ATC_PIGGYBACKED_TREQ_EN 0x110058UL //ACCESS:RW DataWidth:0x1 Description: Piggybacked treq issue enabled
26 #define ATC_REG_ATC_WAIT_RESP 0x11005cUL //ACCESS:RW DataWidth:0x1 Description: Allows the ATC to return Wait response
35 #define ATC_REG_ATC_CHECK_TAGS 0x110080UL //ACCESS:RW DataWidth:0x1 Description: CheckTags configuration bit - when set the available NPH credits is checked before issuing TREQ
38 #define ATC_REG_ATC_DIS_MLKP 0x11008cUL //ACCESS:RW DataWidth:0x1 Description: Disables the main lookup interface
39 #define ATC_REG_ATC_DIS_PLKP 0x110090UL //ACCESS:RW DataWidth:0x1 Descriptio
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/illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/
H A Decore_hw_defs.h40 #define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
41 #define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
42 #define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
43 #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
44 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
45 #define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
48 #define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
49 #define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
50 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
72 #define IGU_CTRL_REG_RESERVED_MASK 0x1
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H A Decore_hsi_fcoe.h68 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 /* Does this connection support protection (if couple of GOS share this connection it�� ��������������s enough that one of them support protection) */
70 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss this is critical since if line mss restrict us we can�� ��������������t rely on this size �� �������������� it depends on vlan num) */
78 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner Vlan flag */
80 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 /* Outer Vlan flag */
95 #define FCOE_VLAN_FIELDS_CLI_MASK 0x1
159 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1 /* Is inner vlan taken from vntag default vlan (in this case I have to update inner vlan each time the default change) */
161 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1 /* AreSupport rec_tov timer */
163 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner Vlan flag */
165 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 /* Outer Vlan flag */
189 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1 /* S
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H A Decore_hsi_toe.h96 #define E4_YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
98 #define E4_YSTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
107 #define E4_YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK 0x1 /* cf0en */
109 #define E4_YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_EN_MASK 0x1 /* cf1en */
111 #define E4_YSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
113 #define E4_YSTORM_TOE_CONN_AG_CTX_REL_SEQ_EN_MASK 0x1 /* rule0en */
115 #define E4_YSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
117 #define E4_YSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
119 #define E4_YSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
121 #define E4_YSTORM_TOE_CONN_AG_CTX_CONS_PROD_EN_MASK 0x1 /* rule4e
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H A Decore_hsi_iscsi.h80 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
82 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 /* exist_in_qm1 */
84 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm2 */
86 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
88 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
90 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1 /* cf_array_active */
92 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */
94 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */
97 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */
99 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1 /* bit
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H A Decore_hsi_rdma.h217 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1
219 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
221 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
223 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
225 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
227 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1
229 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
231 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
233 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1
241 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1 /* Bi
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H A Decore_hsi_roce.h126 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
128 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
132 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1
177 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
179 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
181 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
183 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
185 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
187 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
320 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
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/illumos-gate/usr/src/uts/intel/io/dktp/controller/ata/
H A Data.conf37 ata-options=0x1;
42 drive0_block_factor=0x1;
43 drive1_block_factor=0x1;
/illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/hsi_repository/
H A Decore_hsi_fcoe.h68 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 /* Does this connection support protection (if couple of GOS share this connection it�� ��������������s enough that one of them support protection) */
70 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss this is critical since if line mss restrict us we can�� ��������������t rely on this size �� �������������� it depends on vlan num) */
78 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner Vlan flag */
80 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 /* Outer Vlan flag */
95 #define FCOE_VLAN_FIELDS_CLI_MASK 0x1
159 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1 /* Is inner vlan taken from vntag default vlan (in this case I have to update inner vlan each time the default change) */
161 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1 /* AreSupport rec_tov timer */
163 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner Vlan flag */
165 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 /* Outer Vlan flag */
189 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1 /* S
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H A Decore_hsi_iwarp.h81 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
83 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 /* exist_in_qm1 */
85 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1 /* exist_in_qm2 */
87 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
89 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
91 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* cf_array_active */
93 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */
95 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */
98 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */
100 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1 /* bit
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H A Decore_hsi_toe.h96 #define E4_YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
98 #define E4_YSTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
107 #define E4_YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK 0x1 /* cf0en */
109 #define E4_YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_EN_MASK 0x1 /* cf1en */
111 #define E4_YSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */
113 #define E4_YSTORM_TOE_CONN_AG_CTX_REL_SEQ_EN_MASK 0x1 /* rule0en */
115 #define E4_YSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
117 #define E4_YSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */
119 #define E4_YSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */
121 #define E4_YSTORM_TOE_CONN_AG_CTX_CONS_PROD_EN_MASK 0x1 /* rule4e
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H A Decore_hsi_iscsi.h80 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
82 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 /* exist_in_qm1 */
84 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm2 */
86 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
88 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
90 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1 /* cf_array_active */
92 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */
94 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */
97 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */
99 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1 /* bit
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H A Decore_hsi_rdma.h217 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1
219 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
221 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
223 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
225 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
227 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1
229 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
231 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
233 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1
241 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1 /* Bi
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H A Decore_hsi_roce.h126 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
128 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
132 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1
177 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
179 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
181 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
183 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
185 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
187 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
320 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
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H A Decore_hsi_eth.h72 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
74 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */
76 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */
78 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
80 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */
82 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */
84 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
86 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
89 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
91 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit
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H A DpreRoce.h99 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
101 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */
103 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */
105 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
107 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */
109 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */
111 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
113 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
116 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
118 #define E4_XSTORM_PRE_ROCE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit
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H A Dqed_hsi_rdma.h61 #define RDMA_CQE_RESPONDER_TOGGLE_BIT_MASK 0x1 /* indicates a valid completion written by FW. FW toggle this bit each time it finishes producing all PBL entries */
65 #define RDMA_CQE_RESPONDER_INV_FLG_MASK 0x1 /* r_key invalidated indicator */
67 #define RDMA_CQE_RESPONDER_IMM_FLG_MASK 0x1 /* immediate data indicator */
69 #define RDMA_CQE_RESPONDER_RDMA_FLG_MASK 0x1 /* 1=this CQE relates to an RDMA Write. 0=Send. */
86 #define RDMA_CQE_REQUESTER_TOGGLE_BIT_MASK 0x1 /* indicates a valid completion written by FW. FW toggle this bit each time it finishes producing all PBL entries */
101 #define RDMA_CQE_COMMON_TOGGLE_BIT_MASK 0x1 /* indicates a valid completion written by FW. FW toggle this bit each time it finishes producing all PBL entries */
205 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_CRC_MASK 0x1 /* CRC error occurred. */
207 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_APP_TAG_MASK 0x1 /* App Tag error occurred. */
209 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_REF_TAG_MASK 0x1 /* Ref Tag error occurred. */
213 #define RDMA_DIF_ERROR_RESULT_TOGGLE_BIT_MASK 0x1 /* Use
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