1 /*
2  * Copyright (c) 2012-2015 Solarflare Communications Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  *    this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright notice,
11  *    this list of conditions and the following disclaimer in the documentation
12  *    and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  *
26  * The views and conclusions contained in the software and documentation are
27  * those of the authors and should not be interpreted as representing official
28  * policies, either expressed or implied, of the FreeBSD Project.
29  */
30 
31 /* These structures define the layouts for the TLV items stored in static and
32  * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.).
33  *
34  * They contain the same sort of information that was kept in the
35  * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures
36  * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for
37  * Siena.
38  *
39  * These are used directly by the MC and should also be usable directly on host
40  * systems which are little-endian and do not do strange things with structure
41  * padding.  (Big-endian host systems will require some byte-swapping.)
42  *
43  *                                    -----
44  *
45  * Please refer to SF-108797-SW for a general overview of the TLV partition
46  * format.
47  *
48  *                                    -----
49  *
50  * The current tag IDs have a general structure: with the exception of the
51  * special values defined in the document, they are of the form 0xLTTTNNNN,
52  * where:
53  *
54  *   -  L is a location, indicating where this tag is expected to be found:
55  *        0: static configuration
56  *        1: dynamic configuration
57  *        2: firmware internal use
58  *        3: license partition
59  *
60  *   -  TTT is a type, which is just a unique value.  The same type value
61  *      might appear in both locations, indicating a relationship between
62  *      the items (e.g. static and dynamic VPD below).
63  *
64  *   -  NNNN is an index of some form.  Some item types are per-port, some
65  *      are per-PF, some are per-partition-type.
66  *
67  *                                    -----
68  *
69  * As with the previous Siena structures, each structure here is laid out
70  * carefully: values are aligned to their natural boundary, with explicit
71  * padding fields added where necessary.  (No, technically this does not
72  * absolutely guarantee portability.  But, in practice, compilers are generally
73  * sensible enough not to introduce completely pointless padding, and it works
74  * well enough.)
75  */
76 
77 
78 #ifndef CI_MGMT_TLV_LAYOUT_H
79 #define CI_MGMT_TLV_LAYOUT_H
80 
81 
82 /* ----------------------------------------------------------------------------
83  *  General structure (defined by SF-108797-SW)
84  * ----------------------------------------------------------------------------
85  */
86 
87 
88 /* The "end" tag.
89  *
90  * (Note that this is *not* followed by length or value fields: anything after
91  * the tag itself is irrelevant.)
92  */
93 
94 #define TLV_TAG_END                     (0xEEEEEEEE)
95 
96 
97 /* Other special reserved tag values.
98  */
99 
100 #define TLV_TAG_SKIP                    (0x00000000)
101 #define TLV_TAG_INVALID                 (0xFFFFFFFF)
102 
103 
104 /* TLV partition header.
105  *
106  * In a TLV partition, this must be the first item in the sequence, at offset
107  * 0.
108  */
109 
110 #define TLV_TAG_PARTITION_HEADER        (0xEF10DA7A)
111 
112 struct tlv_partition_header {
113   uint32_t tag;
114   uint32_t length;
115   uint16_t type_id;
116 /* 0 indicates the default segment (always located at offset 0), while other values
117  * are for RFID-selectable presets that should immediately follow the default segment.
118  * The default segment may also have preset > 0, which means that it is a preset
119  * selected through an RFID command and copied by FW to the location at offset 0. */
120   uint16_t preset;
121   uint32_t generation;
122   uint32_t total_length;
123 };
124 
125 
126 /* TLV partition trailer.
127  *
128  * In a TLV partition, this must be the last item in the sequence, immediately
129  * preceding the TLV_TAG_END word.
130  */
131 
132 #define TLV_TAG_PARTITION_TRAILER       (0xEF101A57)
133 
134 struct tlv_partition_trailer {
135   uint32_t tag;
136   uint32_t length;
137   uint32_t generation;
138   uint32_t checksum;
139 };
140 
141 
142 /* Appendable TLV partition header.
143  *
144  * In an appendable TLV partition, this must be the first item in the sequence,
145  * at offset 0.  (Note that, unlike the configuration partitions, there is no
146  * trailer before the TLV_TAG_END word.)
147  */
148 
149 #define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7)
150 
151 struct tlv_appendable_partition_header {
152   uint32_t tag;
153   uint32_t length;
154   uint16_t type_id;
155   uint16_t reserved;
156 };
157 
158 
159 /* ----------------------------------------------------------------------------
160  *  Configuration items
161  * ----------------------------------------------------------------------------
162  */
163 
164 
165 /* NIC global capabilities.
166  */
167 
168 #define TLV_TAG_GLOBAL_CAPABILITIES     (0x00010000)
169 
170 struct tlv_global_capabilities {
171   uint32_t tag;
172   uint32_t length;
173   uint32_t flags;
174 };
175 
176 
177 /* Siena-style per-port MAC address allocation.
178  *
179  * There are <count> addresses, starting at <base_address> and incrementing
180  * by adding <stride> to the low-order byte(s).
181  *
182  * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool
183  * of contiguous MAC addresses for the firmware to allocate as it sees fit.)
184  */
185 
186 #define TLV_TAG_PORT_MAC(port)          (0x00020000 + (port))
187 
188 struct tlv_port_mac {
189   uint32_t tag;
190   uint32_t length;
191   uint8_t  base_address[6];
192   uint16_t reserved;
193   uint16_t count;
194   uint16_t stride;
195 };
196 
197 
198 /* Static VPD.
199  *
200  * This is the portion of VPD which is set at manufacturing time and not
201  * expected to change.  It is formatted as a standard PCI VPD block. There are
202  * global and per-pf TLVs for this, the global TLV is new for Medford and is
203  * used in preference to the per-pf TLV.
204  */
205 
206 #define TLV_TAG_PF_STATIC_VPD(pf)       (0x00030000 + (pf))
207 
208 struct tlv_pf_static_vpd {
209   uint32_t tag;
210   uint32_t length;
211   uint8_t  bytes[];
212 };
213 
214 #define TLV_TAG_GLOBAL_STATIC_VPD       (0x001f0000)
215 
216 struct tlv_global_static_vpd {
217   uint32_t tag;
218   uint32_t length;
219   uint8_t  bytes[];
220 };
221 
222 
223 /* Dynamic VPD.
224  *
225  * This is the portion of VPD which may be changed (e.g. by firmware updates).
226  * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs
227  * for this, the global TLV is new for Medford and is used in preference to the
228  * per-pf TLV.
229  */
230 
231 #define TLV_TAG_PF_DYNAMIC_VPD(pf)      (0x10030000 + (pf))
232 
233 struct tlv_pf_dynamic_vpd {
234   uint32_t tag;
235   uint32_t length;
236   uint8_t  bytes[];
237 };
238 
239 #define TLV_TAG_GLOBAL_DYNAMIC_VPD      (0x10200000)
240 
241 struct tlv_global_dynamic_vpd {
242   uint32_t tag;
243   uint32_t length;
244   uint8_t  bytes[];
245 };
246 
247 
248 /* "DBI" PCI config space changes.
249  *
250  * This is a set of edits made to the default PCI config space values before
251  * the device is allowed to enumerate. There are global and per-pf TLVs for
252  * this, the global TLV is new for Medford and is used in preference to the
253  * per-pf TLV.
254  */
255 
256 #define TLV_TAG_PF_DBI(pf)              (0x00040000 + (pf))
257 
258 struct tlv_pf_dbi {
259   uint32_t tag;
260   uint32_t length;
261   struct {
262     uint16_t addr;
263     uint16_t byte_enables;
264     uint32_t value;
265   } items[];
266 };
267 
268 
269 #define TLV_TAG_GLOBAL_DBI              (0x00210000)
270 
271 struct tlv_global_dbi {
272   uint32_t tag;
273   uint32_t length;
274   struct {
275     uint16_t addr;
276     uint16_t byte_enables;
277     uint32_t value;
278   } items[];
279 };
280 
281 
282 /* Partition subtype codes.
283  *
284  * A subtype may optionally be stored for each type of partition present in
285  * the NVRAM.  For example, this may be used to allow a generic firmware update
286  * utility to select a specific variant of firmware for a specific variant of
287  * board.
288  *
289  * The description[] field is an optional string which is returned in the
290  * MC_CMD_NVRAM_METADATA response if present.
291  */
292 
293 #define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type))
294 
295 struct tlv_partition_subtype {
296   uint32_t tag;
297   uint32_t length;
298   uint32_t subtype;
299   uint8_t  description[];
300 };
301 
302 
303 /* Partition version codes.
304  *
305  * A version may optionally be stored for each type of partition present in
306  * the NVRAM.  This provides a standard way of tracking the currently stored
307  * version of each of the various component images.
308  */
309 
310 #define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type))
311 
312 struct tlv_partition_version {
313   uint32_t tag;
314   uint32_t length;
315   uint16_t version_w;
316   uint16_t version_x;
317   uint16_t version_y;
318   uint16_t version_z;
319 };
320 
321 /* Global PCIe configuration */
322 
323 #define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000)
324 
325 struct tlv_pcie_config {
326   uint32_t tag;
327   uint32_t length;
328   int16_t max_pf_number;                        /**< Largest PF RID (lower PFs may be hidden) */
329   uint16_t pf_aper;                             /**< BIU aperture for PF BAR2 */
330   uint16_t vf_aper;                             /**< BIU aperture for VF BAR0 */
331   uint16_t int_aper;                            /**< BIU aperture for PF BAR4 and VF BAR2 */
332 #define TLV_MAX_PF_DEFAULT (-1)                 /* Use FW default for largest PF RID  */
333 #define TLV_APER_DEFAULT (0xFFFF)               /* Use FW default for a given aperture */
334 };
335 
336 /* Per-PF configuration. Note that not all these fields are necessarily useful
337  * as the apertures are constrained by the BIU settings (the one case we do
338  * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can
339  * tidy things up later */
340 
341 #define TLV_TAG_PF_PCIE_CONFIG(pf)  (0x10080000 + (pf))
342 
343 struct tlv_per_pf_pcie_config {
344   uint32_t tag;
345   uint32_t length;
346   uint8_t vfs_total;
347   uint8_t port_allocation;
348   uint16_t vectors_per_pf;
349   uint16_t vectors_per_vf;
350   uint8_t pf_bar0_aperture;
351   uint8_t pf_bar2_aperture;
352   uint8_t vf_bar0_aperture;
353   uint8_t vf_base;
354   uint16_t supp_pagesz;
355   uint16_t msix_vec_base;
356 };
357 
358 
359 /* Development ONLY. This is a single TLV tag for all the gubbins
360  * that can be set through the MC command-line other than the PCIe
361  * settings. This is a temporary measure. */
362 #define TLV_TAG_TMP_GUBBINS (0x10090000)        /* legacy symbol - do not use */
363 #define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS
364 
365 struct tlv_tmp_gubbins {
366   uint32_t tag;
367   uint32_t length;
368   /* Consumed by dpcpu.c */
369   uint64_t tx0_tags;     /* Bitmap */
370   uint64_t tx1_tags;     /* Bitmap */
371   uint64_t dl_tags;      /* Bitmap */
372   uint32_t flags;
373 #define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */
374 #define TLV_DPCPU_BIU_TAGS  (2) /* Use BIU tag manager */
375 #define TLV_DPCPU_TX0_TAGS  (4) /* tx0_tags is valid */
376 #define TLV_DPCPU_TX1_TAGS  (8) /* tx1_tags is valid */
377 #define TLV_DPCPU_DL_TAGS  (16) /* dl_tags is valid */
378   /* Consumed by features.c */
379   uint32_t dut_features;        /* All 1s -> leave alone */
380   int8_t with_rmon;             /* 0 -> off, 1 -> on, -1 -> leave alone */
381   /* Consumed by clocks_hunt.c */
382   int8_t clk_mode;             /* 0 -> off, 1 -> on, -1 -> leave alone */
383   /* No longer used, superseded by TLV_TAG_DESCRIPTOR_CACHE_CONFIG. */
384   int8_t rx_dc_size;           /* -1 -> leave alone */
385   int8_t tx_dc_size;
386   int16_t num_q_allocs;
387 };
388 
389 /* Global port configuration
390  *
391  * This is now deprecated in favour of a platform-provided default
392  * and dynamic config override via tlv_global_port_options.
393  */
394 #define TLV_TAG_GLOBAL_PORT_CONFIG      (0x000a0000)
395 
396 struct tlv_global_port_config {
397   uint32_t tag;
398   uint32_t length;
399   uint32_t ports_per_core;
400   uint32_t max_port_speed;
401 };
402 
403 
404 /* Firmware options.
405  *
406  * This is intended for user-configurable selection of optional firmware
407  * features and variants.
408  *
409  * Initially, this consists only of the satellite CPU firmware variant
410  * selection, but this tag could be extended in the future (using the
411  * tag length to determine whether additional fields are present).
412  */
413 
414 #define TLV_TAG_FIRMWARE_OPTIONS        (0x100b0000)
415 
416 struct tlv_firmware_options {
417   uint32_t tag;
418   uint32_t length;
419   uint32_t firmware_variant;
420 #define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff)
421 
422 /* These are the values for overriding the driver's choice; the definitions
423  * are taken from MCDI so that they don't get out of step.  Include
424  * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if
425  * you need to use these constants.
426  */
427 #define TLV_FIRMWARE_VARIANT_FULL_FEATURED   MC_CMD_FW_FULL_FEATURED
428 #define TLV_FIRMWARE_VARIANT_LOW_LATENCY     MC_CMD_FW_LOW_LATENCY
429 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM   MC_CMD_FW_PACKED_STREAM
430 #define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE    MC_CMD_FW_HIGH_TX_RATE
431 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \
432                                              MC_CMD_FW_PACKED_STREAM_HASH_MODE_1
433 };
434 
435 /* Voltage settings
436  *
437  * Intended for boards with A0 silicon where the core voltage may
438  * need tweaking. Most likely set once when the pass voltage is
439  * determined. */
440 
441 #define TLV_TAG_0V9_SETTINGS (0x000c0000)
442 
443 struct tlv_0v9_settings {
444   uint32_t tag;
445   uint32_t length;
446   uint16_t flags; /* Boards with high 0v9 settings may need active cooling */
447 #define TLV_TAG_0V9_REQUIRES_FAN (1)
448   uint16_t target_voltage; /* In millivolts */
449   /* Since the limits are meant to be centred to the target (and must at least
450    * contain it) they need setting as well. */
451   uint16_t warn_low;       /* In millivolts */
452   uint16_t warn_high;      /* In millivolts */
453   uint16_t panic_low;      /* In millivolts */
454   uint16_t panic_high;     /* In millivolts */
455 };
456 
457 
458 /* Clock configuration */
459 
460 #define TLV_TAG_CLOCK_CONFIG       (0x000d0000) /* legacy symbol - do not use */
461 #define TLV_TAG_CLOCK_CONFIG_HUNT  TLV_TAG_CLOCK_CONFIG
462 
463 struct tlv_clock_config {
464   uint32_t tag;
465   uint32_t length;
466   uint16_t clk_sys;        /* MHz */
467   uint16_t clk_dpcpu;      /* MHz */
468   uint16_t clk_icore;      /* MHz */
469   uint16_t clk_pcs;        /* MHz */
470 };
471 
472 #define TLV_TAG_CLOCK_CONFIG_MEDFORD      (0x00100000)
473 
474 struct tlv_clock_config_medford {
475   uint32_t tag;
476   uint32_t length;
477   uint16_t clk_sys;        /* MHz */
478   uint16_t clk_mc;         /* MHz */
479   uint16_t clk_rmon;       /* MHz */
480   uint16_t clk_vswitch;    /* MHz */
481   uint16_t clk_dpcpu;      /* MHz */
482   uint16_t clk_pcs;        /* MHz */
483 };
484 
485 
486 /* EF10-style global pool of MAC addresses.
487  *
488  * There are <count> addresses, starting at <base_address>, which are
489  * contiguous.  Firmware is responsible for allocating addresses from this
490  * pool to ports / PFs as appropriate.
491  */
492 
493 #define TLV_TAG_GLOBAL_MAC              (0x000e0000)
494 
495 struct tlv_global_mac {
496   uint32_t tag;
497   uint32_t length;
498   uint8_t  base_address[6];
499   uint16_t reserved1;
500   uint16_t count;
501   uint16_t reserved2;
502 };
503 
504 #define TLV_TAG_ATB_0V9_TARGET     (0x000f0000) /* legacy symbol - do not use */
505 #define TLV_TAG_ATB_0V9_TARGET_HUNT     TLV_TAG_ATB_0V9_TARGET
506 
507 /* The target value for the 0v9 power rail measured on-chip at the
508  * analogue test bus */
509 struct tlv_0v9_atb_target {
510   uint32_t tag;
511   uint32_t length;
512   uint16_t millivolts;
513   uint16_t reserved;
514 };
515 
516 /* Global PCIe configuration, second revision. This represents the visible PFs
517  * by a bitmap rather than having the number of the highest visible one. As such
518  * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG
519  * can and it should be used in place of that tag in future (but compatibility with
520  * the old tag will be left in the firmware indefinitely).  */
521 
522 #define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000)
523 
524 struct tlv_pcie_config_r2 {
525   uint32_t tag;
526   uint32_t length;
527   uint16_t visible_pfs;                         /**< Bitmap of visible PFs */
528   uint16_t pf_aper;                             /**< BIU aperture for PF BAR2 */
529   uint16_t vf_aper;                             /**< BIU aperture for VF BAR0 */
530   uint16_t int_aper;                            /**< BIU aperture for PF BAR4 and VF BAR2 */
531 };
532 
533 /* Dynamic port mode.
534  *
535  * Allows selecting alternate port configuration for platforms that support it
536  * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the
537  * number of externally visible ports (and, hence, PF to port mapping), so must
538  * be done at boot time.
539  *
540  * This tag supercedes tlv_global_port_config.
541  */
542 
543 #define TLV_TAG_GLOBAL_PORT_MODE         (0x10110000)
544 
545 struct tlv_global_port_mode {
546   uint32_t tag;
547   uint32_t length;
548   uint32_t port_mode;
549 #define TLV_PORT_MODE_DEFAULT           (0xffffffff) /* Default for given platform */
550 #define TLV_PORT_MODE_10G                        (0) /* 10G, single SFP/10G-KR */
551 #define TLV_PORT_MODE_40G                        (1) /* 40G, single QSFP/40G-KR */
552 #define TLV_PORT_MODE_10G_10G                    (2) /* 2x10G, dual SFP/10G-KR or single QSFP */
553 #define TLV_PORT_MODE_40G_40G                    (3) /* 40G + 40G, dual QSFP/40G-KR (Greenport, Medford) */
554 #define TLV_PORT_MODE_10G_10G_10G_10G            (4) /* 2x10G + 2x10G, quad SFP/10G-KR or dual QSFP (Greenport, Medford) */
555 #define TLV_PORT_MODE_10G_10G_10G_10G_Q          (5) /* 4x10G, single QSFP, cage 0 (Medford) */
556 #define TLV_PORT_MODE_40G_10G_10G                (6) /* 1x40G + 2x10G, dual QSFP (Greenport, Medford) */
557 #define TLV_PORT_MODE_10G_10G_40G                (7) /* 2x10G + 1x40G, dual QSFP (Greenport, Medford) */
558 #define TLV_PORT_MODE_10G_10G_10G_10G_Q2         (8) /* 4x10G, single QSFP, cage 1 (Medford) */
559 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_10G_10G_10G_10G_Q2
560 };
561 
562 /* Type of the v-switch created implicitly by the firmware */
563 
564 #define TLV_TAG_VSWITCH_TYPE(port)       (0x10120000 + (port))
565 
566 struct tlv_vswitch_type {
567   uint32_t tag;
568   uint32_t length;
569   uint32_t vswitch_type;
570 #define TLV_VSWITCH_TYPE_DEFAULT        (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */
571 #define TLV_VSWITCH_TYPE_NONE                    (0)
572 #define TLV_VSWITCH_TYPE_VLAN                    (1)
573 #define TLV_VSWITCH_TYPE_VEB                     (2)
574 #define TLV_VSWITCH_TYPE_VEPA                    (3)
575 #define TLV_VSWITCH_TYPE_MUX                     (4)
576 #define TLV_VSWITCH_TYPE_TEST                    (5)
577 };
578 
579 /* A VLAN tag for the v-port created implicitly by the firmware */
580 
581 #define TLV_TAG_VPORT_VLAN_TAG(pf)               (0x10130000 + (pf))
582 
583 struct tlv_vport_vlan_tag {
584   uint32_t tag;
585   uint32_t length;
586   uint32_t vlan_tag;
587 #define TLV_VPORT_NO_VLAN_TAG                    (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */
588 };
589 
590 /* Offset to be applied to the 0v9 setting, wherever it came from */
591 
592 #define TLV_TAG_ATB_0V9_OFFSET           (0x10140000)
593 
594 struct tlv_0v9_atb_offset {
595   uint32_t tag;
596   uint32_t length;
597   int16_t  offset_millivolts;
598   uint16_t reserved;
599 };
600 
601 /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port).
602  * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583.
603  * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while
604  * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default:
605  * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */
606 
607 #define TLV_TAG_PRIVILEGE_MASK          (0x10150000) /* legacy symbol - do not use */
608 
609 struct tlv_privilege_mask {                          /* legacy structure - do not use */
610   uint32_t tag;
611   uint32_t length;
612   uint32_t privilege_mask;
613 };
614 
615 #define TLV_TAG_PRIVILEGE_MASK_ADD      (0x10150000)
616 
617 struct tlv_privilege_mask_add {
618   uint32_t tag;
619   uint32_t length;
620   uint32_t privilege_mask_add;
621 };
622 
623 #define TLV_TAG_PRIVILEGE_MASK_REM      (0x10160000)
624 
625 struct tlv_privilege_mask_rem {
626   uint32_t tag;
627   uint32_t length;
628   uint32_t privilege_mask_rem;
629 };
630 
631 /* Additional privileges given to all PFs.
632  * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
633 
634 #define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS         (0x10190000)
635 
636 struct tlv_privilege_mask_add_all_pfs {
637   uint32_t tag;
638   uint32_t length;
639   uint32_t privilege_mask_add;
640 };
641 
642 /* Additional privileges given to a selected PF.
643  * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
644 
645 #define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf)   (0x101A0000 + (pf))
646 
647 struct tlv_privilege_mask_add_single_pf {
648   uint32_t tag;
649   uint32_t length;
650   uint32_t privilege_mask_add;
651 };
652 
653 /* Turning on/off the PFIOV mode.
654  * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */
655 
656 #define TLV_TAG_PFIOV(port)             (0x10170000 + (port))
657 
658 struct tlv_pfiov {
659   uint32_t tag;
660   uint32_t length;
661   uint32_t pfiov;
662 #define TLV_PFIOV_OFF                    (0) /* Default */
663 #define TLV_PFIOV_ON                     (1)
664 };
665 
666 /* Multicast filter chaining mode selection.
667  *
668  * When enabled, multicast packets are delivered to all recipients of all
669  * matching multicast filters, with the exception that IP multicast filters
670  * will steal traffic from MAC multicast filters on a per-function basis.
671  * (New behaviour.)
672  *
673  * When disabled, multicast packets will always be delivered only to the
674  * recipients of the highest priority matching multicast filter.
675  * (Legacy behaviour.)
676  *
677  * The DEFAULT mode (which is the same as the tag not being present at all)
678  * is equivalent to ENABLED in production builds, and DISABLED in eftest
679  * builds.
680  *
681  * This option is intended to provide run-time control over this feature
682  * while it is being stabilised and may be withdrawn at some point in the
683  * future; the new behaviour is intended to become the standard behaviour.
684  */
685 
686 #define TLV_TAG_MCAST_FILTER_CHAINING   (0x10180000)
687 
688 struct tlv_mcast_filter_chaining {
689   uint32_t tag;
690   uint32_t length;
691   uint32_t mode;
692 #define TLV_MCAST_FILTER_CHAINING_DEFAULT  (0xffffffff)
693 #define TLV_MCAST_FILTER_CHAINING_DISABLED (0)
694 #define TLV_MCAST_FILTER_CHAINING_ENABLED  (1)
695 };
696 
697 /* Pacer rate limit per PF */
698 #define TLV_TAG_RATE_LIMIT(pf)    (0x101b0000 + (pf))
699 
700 struct tlv_rate_limit {
701   uint32_t tag;
702   uint32_t length;
703   uint32_t rate_mbps;
704 };
705 
706 /* OCSD Enable/Disable
707  *
708  * This setting allows OCSD to be disabled. This is a requirement for HP
709  * servers to support PCI passthrough for virtualization.
710  *
711  * The DEFAULT mode (which is the same as the tag not being present) is
712  * equivalent to ENABLED.
713  *
714  * This option is not used by the MCFW, and is entirely handled by the various
715  * drivers that support OCSD, by reading the setting before they attempt
716  * to enable OCSD.
717  *
718  * bit0: OCSD Disabled/Enabled
719  */
720 
721 #define TLV_TAG_OCSD (0x101C0000)
722 
723 struct tlv_ocsd {
724   uint32_t tag;
725   uint32_t length;
726   uint32_t mode;
727 #define TLV_OCSD_DISABLED 0
728 #define TLV_OCSD_ENABLED 1 /* Default */
729 };
730 
731 /* Descriptor cache config.
732  *
733  * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also
734  * sets the total number of VIs. When the number of VIs is reduced VIs are taken
735  * away from the highest numbered port first, so a vi_count of 1024 means 1024
736  * VIs on the first port and 0 on the second (on a Torino).
737  */
738 
739 #define TLV_TAG_DESCRIPTOR_CACHE_CONFIG    (0x101d0000)
740 
741 struct tlv_descriptor_cache_config {
742   uint32_t tag;
743   uint32_t length;
744   uint8_t rx_desc_cache_size;
745   uint8_t tx_desc_cache_size;
746   uint16_t vi_count;
747 };
748 #define TLV_DESC_CACHE_DEFAULT (0xff)
749 #define TLV_VI_COUNT_DEFAULT   (0xffff)
750 
751 /* RX event merging config (read batching).
752  *
753  * Sets the global maximum number of events for the merging bins, and the
754  * global timeout configuration for the bins.
755  */
756 
757 #define TLV_TAG_RX_EVENT_MERGING_CONFIG    (0x101e0000)
758 
759 struct tlv_rx_event_merging_config {
760   uint32_t  tag;
761   uint32_t  length;
762   uint32_t  max_events;
763 #define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
764   uint32_t  timeout_ns;
765 };
766 #define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT 7
767 #define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT 8740
768 
769 #define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000)
770 struct tlv_pcie_link_settings {
771   uint32_t tag;
772   uint32_t length;
773   uint16_t gen;   /* Target PCIe generation: 1, 2, 3 */
774   uint16_t width; /* Number of lanes */
775 };
776 
777 #define TLV_TAG_LICENSE (0x30800000)
778 
779 typedef struct tlv_license {
780   uint32_t  tag;
781   uint32_t  length;
782   uint8_t   data[];
783 } tlv_license_t;
784 
785 #endif /* CI_MGMT_TLV_LAYOUT_H */
786