/gfx-drm/usr/src/cmd/mdb/i915/ |
H A D | i915.c | 698 uint32_t val; in i915_register_read() local 746 uint32_t val; in i915_error_reg_dump() local 1382 uint32_t val; in i915_interrupt_info() local 1484 &val); in i915_interrupt_info() 1494 val); in i915_interrupt_info() 1505 val); in i915_interrupt_info() 1511 val); in i915_interrupt_info() 1522 val); in i915_interrupt_info() 1533 val); in i915_interrupt_info() 1673 if (val) { in i915_fbc_status() [all …]
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/gfx-drm/usr/src/uts/intel/io/i915/ |
H A D | dvo_ivch.c | 383 uint16_t val; in ivch_dump_regs() local 385 (void) ivch_read(dvo, VR00, &val); in ivch_dump_regs() 387 (void) ivch_read(dvo, VR01, &val); in ivch_dump_regs() 389 (void) ivch_read(dvo, VR30, &val); in ivch_dump_regs() 391 (void) ivch_read(dvo, VR40, &val); in ivch_dump_regs() 395 (void) ivch_read(dvo, VR80, &val); in ivch_dump_regs() 397 (void) ivch_read(dvo, VR81, &val); in ivch_dump_regs() 399 (void) ivch_read(dvo, VR82, &val); in ivch_dump_regs() 401 (void) ivch_read(dvo, VR83, &val); in ivch_dump_regs() 403 (void) ivch_read(dvo, VR84, &val); in ivch_dump_regs() [all …]
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H A D | intel_hdmi.c | 198 I915_WRITE(reg, val); in ibx_write_infoframe() 214 I915_WRITE(reg, val); in ibx_write_infoframe() 241 I915_WRITE(reg, val); in cpt_write_infoframe() 436 val |= port; in g4x_set_infoframes() 496 val |= port; in ibx_set_infoframes() 999 switch (val) { in intel_hdmi_set_property() 1039 u32 val; in intel_hdmi_pre_enable() local 1046 val = 0; in intel_hdmi_pre_enable() 1048 val |= (1<<21); in intel_hdmi_pre_enable() 1050 val &= ~(1<<21); in intel_hdmi_pre_enable() [all …]
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H A D | dvo_tfp410.c | 279 uint8_t val, val2; in tfp410_dump_regs() local 281 (void) tfp410_readb(dvo, TFP410_REV, &val); in tfp410_dump_regs() 282 DRM_LOG_KMS("TFP410_REV: 0x%02X\n", val); in tfp410_dump_regs() 283 (void) tfp410_readb(dvo, TFP410_CTL_1, &val); in tfp410_dump_regs() 284 DRM_LOG_KMS("TFP410_CTL1: 0x%02X\n", val); in tfp410_dump_regs() 285 (void) tfp410_readb(dvo, TFP410_CTL_2, &val); in tfp410_dump_regs() 286 DRM_LOG_KMS("TFP410_CTL2: 0x%02X\n", val); in tfp410_dump_regs() 288 DRM_LOG_KMS("TFP410_CTL3: 0x%02X\n", val); in tfp410_dump_regs() 292 DRM_LOG_KMS("TFP410_DE_DLY: 0x%02X\n", val); in tfp410_dump_regs() 294 DRM_LOG_KMS("TFP410_DE_CTL: 0x%02X\n", val); in tfp410_dump_regs() [all …]
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H A D | intel_sideband.c | 50 I915_WRITE(VLV_IOSF_DATA, *val); in vlv_sideband_rw() 60 *val = I915_READ(VLV_IOSF_DATA); in vlv_sideband_rw() 68 u32 val = 0; in vlv_punit_read() local 74 PUNIT_OPCODE_REG_READ, addr, &val); in vlv_punit_read() 77 return val; in vlv_punit_read() 92 u32 val = 0; in vlv_nc_read() local 101 return val; in vlv_nc_read() 106 u32 val = 0; in vlv_dpio_read() local 109 DPIO_OPCODE_REG_READ, reg, &val); in vlv_dpio_read() 111 return val; in vlv_dpio_read() [all …]
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H A D | dvo_ch7017.c | 185 .buf = val, in ch7017_read() 193 uint8_t buf[2] = { addr, val }; in ch7017_write() 209 u8 val; in ch7017_init() local 221 switch (val) { in ch7017_init() 344 uint8_t val; in ch7017_dpms() local 363 val | CH7017_LVDS_POWER_DOWN_EN); in ch7017_dpms() 372 uint8_t val; in ch7017_get_hw_state() local 376 if (val & CH7017_LVDS_POWER_DOWN_EN) in ch7017_get_hw_state() 384 uint8_t val; in ch7017_dump_regs() local 388 (void) ch7017_read(dvo, reg, &val); \ in ch7017_dump_regs() [all …]
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H A D | intel_ddi.c | 369 uint32_t val; in intel_ddi_put_crtc_pll() local 376 val = I915_READ(SPLL_CTL); in intel_ddi_put_crtc_pll() 643 uint32_t reg, val; in intel_ddi_pll_mode_set() local 724 I915_WRITE(reg, val); in intel_ddi_pll_mode_set() 858 I915_WRITE(reg, val); in intel_ddi_disable_transcoder_func() 1073 uint32_t val; in intel_ddi_post_disable() local 1203 uint32_t val; in intel_ddi_prepare_link_retrain() local 1242 uint32_t val; in intel_ddi_fdi_disable() local 1247 val &= ~FDI_RX_ENABLE; in intel_ddi_fdi_disable() 1256 val &= ~FDI_PCDCLK; in intel_ddi_fdi_disable() [all …]
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H A D | dvo_sil164.c | 256 uint8_t val; in sil164_dump_regs() local 258 (void) sil164_readb(dvo, SIL164_FREQ_LO, &val); in sil164_dump_regs() 259 DRM_LOG_KMS("SIL164_FREQ_LO: 0x%02x\n", val); in sil164_dump_regs() 260 (void) sil164_readb(dvo, SIL164_FREQ_HI, &val); in sil164_dump_regs() 261 DRM_LOG_KMS("SIL164_FREQ_HI: 0x%02x\n", val); in sil164_dump_regs() 262 (void) sil164_readb(dvo, SIL164_REG8, &val); in sil164_dump_regs() 263 DRM_LOG_KMS("SIL164_REG8: 0x%02x\n", val); in sil164_dump_regs() 264 (void) sil164_readb(dvo, SIL164_REG9, &val); in sil164_dump_regs() 265 DRM_LOG_KMS("SIL164_REG9: 0x%02x\n", val); in sil164_dump_regs() 266 (void) sil164_readb(dvo, SIL164_REGC, &val); in sil164_dump_regs() [all …]
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H A D | intel_panel.c | 334 u32 val; in i915_read_blc_pwm_ctl() local 342 } else if (val == 0) { in i915_read_blc_pwm_ctl() 362 return val; in i915_read_blc_pwm_ctl() 393 return val; in intel_panel_compute_brightness() 399 return max - val; in intel_panel_compute_brightness() 402 return val; in intel_panel_compute_brightness() 408 u32 val; in intel_panel_get_backlight() local 418 val >>= 1; in intel_panel_get_backlight() 424 val *= lbpc; in intel_panel_get_backlight() 428 val = intel_panel_compute_brightness(dev, val); in intel_panel_get_backlight() [all …]
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H A D | intel_ringbuffer.h | 55 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) argument 58 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) argument 61 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) argument 64 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) argument 67 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) argument
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H A D | intel_i2c.c | 74 u32 val; in intel_i2c_quirk_set() local 80 val = I915_READ(DSPCLK_GATE_D); in intel_i2c_quirk_set() 85 I915_WRITE(DSPCLK_GATE_D, val); in intel_i2c_quirk_set() 308 u32 val, loop = 0; in gmbus_xfer_read() local 317 *buf++ = val & 0xff; in gmbus_xfer_read() 318 val >>= 8; in gmbus_xfer_read() 331 u32 val, loop; in gmbus_xfer_write() local 333 val = loop = 0; in gmbus_xfer_write() 335 val |= *buf++ << (8 * loop++); in gmbus_xfer_write() 348 val = loop = 0; in gmbus_xfer_write() [all …]
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H A D | intel_pm.c | 1881 u32 val; in sandybridge_update_wm() local 1983 u32 val; in ivybridge_update_wm() local 2521 uint32_t val; in hsw_write_wm_values() local 2737 u32 val; in sandybridge_update_sprite_wm() local 3135 vlv_gpu_freq(dev_priv->mem_freq, val), val); in valleyview_set_rps() 3430 u32 val, rp0; in valleyview_rps_max_freq() local 3806 val *= 255; in intel_init_emon() 5168 val /= mult; in vlv_freq_opcode() 5170 val += 0xbd; in vlv_freq_opcode() 5173 val = 0xea; in vlv_freq_opcode() [all …]
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H A D | i915_drv.c | 1223 u8 val; in i915_read8() local 1239 return val; in i915_read8() 1244 u16 val; in i915_read16() local 1260 return val; in i915_read16() 1265 u32 val; in i915_read32() local 1281 return val; in i915_read32() 1286 u64 val; in i915_read64() local 1306 u8 val) in i915_write8() argument 1328 u16 val) in i915_write16() argument 1350 u32 val) in i915_write32() argument [all …]
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H A D | dvo_ns2501.c | 563 uint8_t val; in ns2501_dump_regs() local 565 ns2501_readb(dvo, NS2501_FREQ_LO, &val); in ns2501_dump_regs() 566 DRM_LOG_KMS("NS2501_FREQ_LO: 0x%02x\n", val); in ns2501_dump_regs() 567 ns2501_readb(dvo, NS2501_FREQ_HI, &val); in ns2501_dump_regs() 568 DRM_LOG_KMS("NS2501_FREQ_HI: 0x%02x\n", val); in ns2501_dump_regs() 569 ns2501_readb(dvo, NS2501_REG8, &val); in ns2501_dump_regs() 570 DRM_LOG_KMS("NS2501_REG8: 0x%02x\n", val); in ns2501_dump_regs() 571 ns2501_readb(dvo, NS2501_REG9, &val); in ns2501_dump_regs() 572 DRM_LOG_KMS("NS2501_REG9: 0x%02x\n", val); in ns2501_dump_regs() 573 ns2501_readb(dvo, NS2501_REGC, &val); in ns2501_dump_regs() [all …]
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H A D | intel_display.c | 895 u32 val; in assert_pll() local 949 u32 val; in assert_fdi_tx() local 975 u32 val; in assert_fdi_rx() local 992 u32 val; in assert_fdi_tx_pll_enabled() local 1012 u32 val; in assert_fdi_rx_pll_enabled() local 1024 u32 val; in assert_panel_unlocked() local 1053 u32 val; in assert_pipe() local 1080 u32 val; in assert_plane() local 1099 u32 val; in assert_planes_disabled() local 1129 u32 val; in assert_sprites_disabled() local [all …]
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H A D | dvo_ch7xxx.c | 334 u8 val; in ch7xxx_get_hw_state() local 336 ch7xxx_readb(dvo, CH7xxx_PM, &val); in ch7xxx_get_hw_state() 338 if (val & (CH7xxx_PM_DVIL | CH7xxx_PM_DVIP)) in ch7xxx_get_hw_state() 349 uint8_t val; in ch7xxx_dump_regs() local 352 (void) ch7xxx_readb(dvo, i, &val); in ch7xxx_dump_regs() 353 DRM_LOG_KMS("%02X ", val); in ch7xxx_dump_regs()
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H A D | i915_drv.h | 1939 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1941 extern void gen6_set_rps(struct drm_device *dev, u8 val); 1986 int vlv_gpu_freq(int ddr_freq, int val); 1987 int vlv_freq_opcode(int ddr_freq, int val); 2000 u ## x val); 2009 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (u32)(val)) argument 2011 #define I915_WRITE_NOTRACE(reg, val) DRM_WRITE32(dev_priv->regs, (reg), (val)) argument 2013 #define I915_WRITE16(reg,val) i915_write16(dev_priv, (reg), (u16)(val)) argument 2015 #define I915_WRITE16_NOTRACE(reg, val) DRM_WRITE16(dev_priv->regs, (reg), (val)) argument 2017 #define I915_WRITE8(reg,val) i915_write8(dev_priv, (reg), (u8)(val)) argument [all …]
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H A D | intel_tv.c | 1450 uint64_t val) in intel_tv_set_property() argument 1463 intel_tv->margin[TV_MARGIN_LEFT] != val) { in intel_tv_set_property() 1464 intel_tv->margin[TV_MARGIN_LEFT] = (int) val; in intel_tv_set_property() 1467 intel_tv->margin[TV_MARGIN_RIGHT] != val) { in intel_tv_set_property() 1468 intel_tv->margin[TV_MARGIN_RIGHT] = (int) val; in intel_tv_set_property() 1471 intel_tv->margin[TV_MARGIN_TOP] != val) { in intel_tv_set_property() 1472 intel_tv->margin[TV_MARGIN_TOP] = (int) val; in intel_tv_set_property() 1475 intel_tv->margin[TV_MARGIN_BOTTOM] != val) { in intel_tv_set_property() 1476 intel_tv->margin[TV_MARGIN_BOTTOM] = (int) val; in intel_tv_set_property() 1479 if (val >= ARRAY_SIZE(tv_modes)) { in intel_tv_set_property() [all …]
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H A D | intel_sdvo.c | 242 u32 bval = val, cval = val; in intel_sdvo_write_sdvox() 246 I915_WRITE(intel_sdvo->sdvo_reg, val); in intel_sdvo_write_sdvox() 1321 u8 val; in intel_sdvo_get_config() local 1360 switch (val) { in intel_sdvo_get_config() 2008 uint64_t val) in intel_sdvo_set_property() argument 2022 int i = (int)val; in intel_sdvo_set_property() 2046 switch (val) { in intel_sdvo_set_property() 2081 if (val >= TV_FORMAT_NUM) in intel_sdvo_set_property() 2091 temp_value = (uint16_t)val; in intel_sdvo_set_property() 2106 intel_sdvo_connector->left, val); in intel_sdvo_set_property() [all …]
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/gfx-drm/usr/src/uts/common/io/drm/ |
H A D | drm_sun_pci.c | 149 void pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) in pci_read_config_byte() argument 151 *val = pci_config_get8(pdev->pci_cfg_acc_handle, where); in pci_read_config_byte() 154 void pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) in pci_read_config_word() argument 156 *val = pci_config_get16(pdev->pci_cfg_acc_handle, where); in pci_read_config_word() 159 void pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) in pci_read_config_dword() argument 161 *val = pci_config_get32(pdev->pci_cfg_acc_handle, where); in pci_read_config_dword() 164 void pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) in pci_write_config_byte() argument 166 pci_config_put8(pdev->pci_cfg_acc_handle, where, val); in pci_write_config_byte() 169 void pci_write_config_word(struct pci_dev *pdev, int where, u16 val) in pci_write_config_word() argument 171 pci_config_put16(pdev->pci_cfg_acc_handle, where, val); in pci_write_config_word() [all …]
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/gfx-drm/usr/src/uts/common/drm/ |
H A D | drm_sun_pci.h | 73 extern void pci_read_config_byte(struct pci_dev *dev, int where, u8 *val); 74 extern void pci_read_config_word(struct pci_dev *dev, int where, u16 *val); 75 extern void pci_read_config_dword(struct pci_dev *dev, int where, u32 *val); 76 extern void pci_write_config_byte(struct pci_dev *dev, int where, u8 val); 77 extern void pci_write_config_word(struct pci_dev *dev, int where, u16 val); 78 extern void pci_write_config_dword(struct pci_dev *dev, int where, u32 val);
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H A D | drm_linux.h | 47 #define clamp_int64_t(val) \ argument 48 val = min((int64_t)INT_MAX, val); \ 49 val = max((int64_t)INT_MIN, val); 126 #define put_user(val,ptr) DRM_COPY_TO_USER(ptr,(&val),sizeof(val)) argument
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H A D | drm_crtc.h | 372 struct drm_property *property, uint64_t val); 483 uint64_t val); 654 struct drm_property *property, uint64_t val); 897 extern const char *drm_get_dpms_name(int val); 898 extern const char *drm_get_dvi_i_subconnector_name(int val); 899 extern const char *drm_get_dvi_i_select_name(int val); 900 extern const char *drm_get_tv_subconnector_name(int val); 901 extern const char *drm_get_tv_select_name(int val); 946 uint64_t val);
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H A D | drm_fourcc.h | 160 #define fourcc_mod_code(vendor, val) \ argument 161 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL))
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/gfx-drm/usr/src/uts/intel/io/radeon/ |
H A D | radeon_drv.h | 165 #define SET_RING_HEAD(dev_priv, val) \ argument 166 DRM_WRITE32((dev_priv)->ring_rptr, 0, (val)) 1008 #define RADEON_WRITE(reg, val) \ argument 1009 DRM_WRITE32(dev_priv->mmio, (reg), (val)) 1012 #define RADEON_WRITE8(reg, val) \ argument 1013 DRM_WRITE8(dev_priv->mmio, (reg), (val)) 1015 #define RADEON_WRITE_PLL(addr, val) \ argument 1022 #define RADEON_WRITE_PCIE(addr, val) \ argument 1026 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \ 1175 #define OUT_RING_REG(reg, val) do { \ argument [all …]
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