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Searched refs:tdc (Results 1 – 20 of 20) sorted by relevance

/illumos-gate/usr/src/uts/common/io/nxge/
H A Dnxge_txdma.c110 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { in nxge_init_txdma_channels()
132 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { in nxge_init_txdma_channels()
193 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { in nxge_uninit_txdma_channels()
1339 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { in nxge_txdma_hw_mode()
1491 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { in nxge_fixup_txdma_rings()
1579 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { in nxge_txdma_hw_kick()
1715 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { in nxge_txdma_hung()
1872 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { in nxge_fixup_hung_txdma_rings()
2025 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { in nxge_reclaim_rings()
2066 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { in nxge_txdma_regs_dump_channels()
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H A Dnxge_send.c338 tx_ring_p->tdc, in nxge_start()
354 tx_ring_p->tdc, mark_mode)); in nxge_start()
361 tx_ring_p->tdc)); in nxge_start()
364 tx_ring_p->tdc)); in nxge_start()
373 tx_ring_p->tdc)); in nxge_start()
471 tx_ring_p->tdc)); in nxge_start()
971 tx_ring_p->tdc, in nxge_start()
998 (uint8_t)tx_ring_p->tdc, in nxge_start()
1040 (uint8_t)tx_ring_p->tdc, in nxge_start()
1088 tx_ring_p->tdc, in nxge_start()
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H A Dnxge_virtual.c1948 p_cfgp->tdc.count = ndmas; in nxge_use_default_dma_config_n2()
1949 p_cfgp->tdc.owned = p_cfgp->tdc.count; in nxge_use_default_dma_config_n2()
1953 p_cfgp, p_cfgp->tdc.count, p_cfgp->tdc.start)); in nxge_use_default_dma_config_n2()
2171 p_cfgp->tdc.start = *prop_val; in nxge_use_cfg_dma_config()
2208 p_cfgp->tdc.start = st_txdma; in nxge_use_cfg_dma_config()
2249 p_cfgp->tdc.count = tx_ndmas; in nxge_use_cfg_dma_config()
2250 p_cfgp->tdc.owned = p_cfgp->tdc.count; in nxge_use_cfg_dma_config()
2418 p_cfgp->tdc.start, p_cfgp->tdc.count, in nxge_use_cfg_dma_config()
2612 end = p_cfgp->tdc.start + p_cfgp->tdc.owned; in nxge_set_hw_dma_config()
2754 if (tdc >= nxgep->pt_config.hw_config.tdc.start && in nxge_check_txdma_port_member()
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H A Dnxge_ndd.c971 int tdc; in nxge_param_get_txdma_info() local
995 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { in nxge_param_get_txdma_info()
996 if ((1 << tdc) & set->owned.map) { in nxge_param_get_txdma_info()
998 buf_len, "%d\n", tdc); in nxge_param_get_txdma_info()
2146 int tdc; in nxge_param_dump_tdc() local
2150 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { in nxge_param_dump_tdc()
2151 if ((1 << tdc) & set->owned.map) { in nxge_param_dump_tdc()
2152 (void) nxge_txdma_regs_dump(nxgep, tdc); in nxge_param_dump_tdc()
2258 int rdc, tdc, block; in nxge_param_dump_ptrs() local
2340 for (tdc = 0; tdc < p_cfgp->tdc.count; tdc++) { in nxge_param_dump_ptrs()
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H A Dnxge_intr.c273 limit = first + hardware->tdc.count; in nxge_intr_vec_find()
808 if (hardware->tdc.count == 0) { in nxge_hio_tdsv_add()
809 hardware->tdc.start = dc->channel; in nxge_hio_tdsv_add()
812 hardware->tdc.count++; in nxge_hio_tdsv_add()
813 hardware->tdc.owned++; in nxge_hio_tdsv_add()
H A Dnxge_hio_guest.c392 dc = &nhd->tdc[0]; in nxge_guest_dc_alloc()
479 hardware->tdc.start = first; in res_map_parse()
480 hardware->tdc.count = count; in res_map_parse()
481 hardware->tdc.owned = count; in res_map_parse()
H A Dnxge_main.c3059 dma_poolp->ndmas = p_cfgp->tdc.owned; in nxge_alloc_tx_mem_pool()
3066 dma_cntl_poolp->ndmas = p_cfgp->tdc.owned; in nxge_alloc_tx_mem_pool()
3081 nxgep->tx_rings->ndmas = p_cfgp->tdc.owned; in nxge_alloc_tx_mem_pool()
4448 cap_rings->mr_rnum = p_cfgp->tdc.count; in nxge_m_getcapab()
4465 p_cfgp->tdc.count)); in nxge_m_getcapab()
5524 channel = nxgep->pt_config.hw_config.tdc.start + rhp->index; in nxge_tx_ring_start()
5543 channel = nxgep->pt_config.hw_config.tdc.start + rhp->index; in nxge_tx_ring_stop()
5677 rtype, index, p_cfgp->tdc.count)); in nxge_fill_ring()
5679 ASSERT((index >= 0) && (index < p_cfgp->tdc.count)); in nxge_fill_ring()
5685 channel = nxgep->pt_config.hw_config.tdc.start + index; in nxge_fill_ring()
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H A Dnxge_kstats.c2171 int tdc = set[i]; in nxge_m_tx_stat() local
2174 val += statsp->tdc_stats[tdc].oerrors; in nxge_m_tx_stat()
2178 val += statsp->tdc_stats[tdc].obytes; in nxge_m_tx_stat()
2182 val += statsp->tdc_stats[tdc].opackets; in nxge_m_tx_stat()
2247 r_index = nxgep->pt_config.hw_config.tdc.start + rhp->index; in nxge_tx_ring_stat()
H A Dnxge_hio.c610 current = (type == VP_BOUND_TX) ? &nhd->tdc[0] : &nhd->rdc[0]; in nxge_grp_dc_find()
1630 offset = nxge->pt_config.hw_config.tdc.start; in nxge_hio_share_query()
2330 dc = type == MAC_RING_TYPE_TX ? &nhd->tdc[channel] : &nhd->rdc[channel]; in nxge_hio_dc_share()
/illumos-gate/usr/src/uts/common/io/hxge/
H A Dhxge_txdma.c618 uint8_t tdc; in hxge_txdma_reclaim() local
642 tdc = tx_ring_p->tdc; in hxge_txdma_reclaim()
1845 tx_ring_p->tdc)); in hxge_unmap_txdma_channel_cfg_ring()
1928 tx_ring_p->tdc = channel; in hxge_map_txdma_channel_buf_ring()
2029 tx_ring_p->tdc)); in hxge_unmap_txdma_channel_buf_ring()
2410 uint16_t tdc; in hxge_txdma_get_ring() local
2437 tdc = tx_rings->rings[index]->tdc; in hxge_txdma_get_ring()
2440 if (channel == tdc) { in hxge_txdma_get_ring()
2456 int index, tdc, ndmas; in hxge_txdma_get_mbox() local
2493 tdc = tx_rings->rings[index]->tdc; in hxge_txdma_get_mbox()
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H A Dhxge_send.c150 "==> hxge_start: tx dma channel %d", tx_ring_p->tdc)); in hxge_start()
153 tx_ring_p->tdc, tx_ring_p->descs_pending)); in hxge_start()
201 tx_ring_p->tdc, mp->b_rptr, dump_len)); in hxge_start()
215 tx_ring_p->tdc, mark_mode)); in hxge_start()
219 "TX Descriptor ring is full: channel %d", tx_ring_p->tdc)); in hxge_start()
221 "TX Descriptor ring is full: channel %d", tx_ring_p->tdc)); in hxge_start()
758 tx_ring_p->tdc, tx_ring_p->wr_index, tx_ring_p->wr_index_wrap, in hxge_start()
768 TDC_TDR_KICK, (uint8_t)tx_ring_p->tdc, kick.value); in hxge_start()
H A Dhxge_txdma.h142 uint16_t tdc; member
182 uint16_t tdc; member
H A Dhxge_ndd.c1150 int rdc, tdc, block; in hxge_param_dump_ptrs() local
1224 for (tdc = 0; tdc < p_cfgp->max_tdcs; tdc++) { in hxge_param_dump_ptrs()
1226 " %d\t $%p\n", tdc, (void *)tx_rings[tdc]); in hxge_param_dump_ptrs()
H A Dhxge_virtual.c358 hxge_check_txdma_port_member(p_hxge_t hxgep, uint8_t tdc) in hxge_check_txdma_port_member() argument
370 if (tdc < p_cfgp->max_tdcs) in hxge_check_txdma_port_member()
H A Dhxge.h316 uint8_t tdc[HXGE_MAX_TDCS]; member
/illumos-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_txdma.c133 ASSERT(TXDMA_CHANNEL_VALID(tdc)); in npi_txdma_dump_tdc_regs()
134 if (!TXDMA_CHANNEL_VALID(tdc)) { in npi_txdma_dump_tdc_regs()
138 tdc)); in npi_txdma_dump_tdc_regs()
140 return (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(tdc)); in npi_txdma_dump_tdc_regs()
145 tdc)); in npi_txdma_dump_tdc_regs()
151 tdc); in npi_txdma_dump_tdc_regs()
207 ASSERT(TXDMA_CHANNEL_VALID(tdc)); in npi_txdma_tdc_regs_zero()
208 if (!TXDMA_CHANNEL_VALID(tdc)) { in npi_txdma_tdc_regs_zero()
212 tdc)); in npi_txdma_tdc_regs_zero()
218 tdc)); in npi_txdma_tdc_regs_zero()
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H A Dnpi_txc.c141 npi_txc_dump_tdc_fzc_regs(npi_handle_t handle, uint8_t tdc) in npi_txc_dump_tdc_fzc_regs() argument
146 ASSERT(TXDMA_CHANNEL_VALID(tdc)); in npi_txc_dump_tdc_fzc_regs()
147 if (!TXDMA_CHANNEL_VALID(tdc)) { in npi_txc_dump_tdc_fzc_regs()
151 tdc)); in npi_txc_dump_tdc_fzc_regs()
152 return (NPI_FAILURE | NPI_TXC_CHANNEL_INVALID(tdc)); in npi_txc_dump_tdc_fzc_regs()
157 tdc)); in npi_txc_dump_tdc_fzc_regs()
161 offset = TXC_FZC_REG_CN_OFFSET(txc_fzc_dmc_offset[i], tdc); in npi_txc_dump_tdc_fzc_regs()
169 "\n TXC FZC Register Dump for Channel %d done\n", tdc)); in npi_txc_dump_tdc_fzc_regs()
/illumos-gate/usr/src/uts/common/sys/nxge/
H A Dnxge_txdma.h158 uint16_t tdc; member
205 uint16_t tdc; member
H A Dnxge_hio.h312 nxge_hio_dc_t tdc[NXGE_MAX_TDCS]; member
H A Dnxge_common.h386 tdc_cfg_t tdc; member