Home
last modified time | relevance | path

Searched refs:t1_write_reg_4 (Results 1 – 15 of 15) sorted by relevance

/illumos-gate/usr/src/uts/common/io/chxge/com/
H A Dtp.c128 t1_write_reg_4(adapter, A_TP_DACK_TIME, in tp_set_tcp_time_params()
164 t1_write_reg_4(adap, A_TP_MIB_INDEX, 0); in t1_tp_get_mib_statistics()
184 t1_write_reg_4(ap, A_TP_IN_CONFIG, val); in tp_init()
231 t1_write_reg_4(ap, A_TP_SYNC_TIME_HI, 0); in tp_init()
232 t1_write_reg_4(ap, A_TP_SYNC_TIME_LO, 0); in tp_init()
233 t1_write_reg_4(ap, A_TP_INT_ENABLE, 0); in tp_init()
268 t1_write_reg_4(ap, A_TP_PC_CONFIG, val); in tp_init()
324 t1_write_reg_4(tp->adapter, A_PL_ENABLE, in t1_tp_intr_enable()
331 t1_write_reg_4(tp->adapter, A_PL_ENABLE, in t1_tp_intr_enable()
344 t1_write_reg_4(tp->adapter, A_PL_ENABLE, in t1_tp_intr_disable()
[all …]
H A Despi.c57 t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0); in tricn_write()
75 t1_write_reg_4(adapter, A_ESPI_CMD_ADDR,
80 t1_write_reg_4(adapter, A_ESPI_GOSTAT, 0);
202 t1_write_reg_4(adapter, A_PORT_CONFIG, in espi_setup_for_pm3393()
218 t1_write_reg_4(adapter, A_PORT_CONFIG, in espi_setup_for_vsc7321()
227 t1_write_reg_4(adapter, A_PORT_CONFIG, in espi_setup_for_vsc7321()
257 t1_write_reg_4(adapter, A_PORT_CONFIG, in espi_setup_for_ixf1010()
267 t1_write_reg_4(adapter, A_ESPI_TRAIN, 0); in t1_espi_init()
270 t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, in t1_espi_init()
353 t1_write_reg_4(adapter, A_ESPI_MISC_CONTROL, in t1_espi_get_mon()
[all …]
H A Dmc5.c239 t1_write_reg_4(adap, A_MC5_DBGI_REQ_DATA0, in init_mask_data_array()
253 t1_write_reg_4(adap, A_MC5_RSP_LATENCY, in init_lara7000()
319 t1_write_reg_4(adap, A_MC5_PART_ID_INDEX, 2); in init_idt52100()
381 t1_write_reg_4(mc5->adapter, A_MC5_CONFIG, in mc5_dbgi_mode_enable()
389 t1_write_reg_4(mc5->adapter, A_MC5_CONFIG, in mc5_dbgi_mode_disable()
412 t1_write_reg_4(adap, A_MC5_CONFIG, cfg); in t1_mc5_init()
430 t1_write_reg_4(adap, A_MC5_DBGI_REQ_ADDR1, 0); in t1_mc5_init()
520 t1_write_reg_4(mc5->adapter, A_PL_ENABLE, in t1_mc5_intr_enable()
538 t1_write_reg_4(mc5->adapter, A_PL_ENABLE, in t1_mc5_intr_disable()
624 t1_write_reg_4(adap, A_MC5_INT_CAUSE, cause); in t1_mc5_intr_handler()
[all …]
H A Dmc3.c55 t1_write_reg_4(mc3->adapter, A_PL_ENABLE, in t1_mc3_intr_enable()
67 t1_write_reg_4(mc3->adapter, A_PL_ENABLE, in t1_mc3_intr_disable()
72 t1_write_reg_4(mc3->adapter, A_PL_ENABLE, in t1_mc3_intr_disable()
101 t1_write_reg_4(mc3->adapter, A_PL_CAUSE, in t1_mc3_intr_clear()
168 t1_write_reg_4(adapter, cause_reg, cause); in t1_mc3_intr_handler()
182 t1_write_reg_4(adapter, addr, val); in wrreg_wait()
225 t1_write_reg_4(adapter, A_MC3_CFG, val); in t1_mc3_init()
234 t1_write_reg_4(adapter, A_MC3_STROBE, in t1_mc3_init()
241 t1_write_reg_4(adapter, A_MC3_STROBE, in t1_mc3_init()
293 t1_write_reg_4(adapter, A_MC3_REFRESH, in t1_mc3_init()
[all …]
H A Dulp.c48 t1_write_reg_4(ulp->adapter, A_PL_ENABLE, in t1_ulp_intr_enable()
56 t1_write_reg_4(ulp->adapter, A_PL_CAUSE, F_PL_INTR_ULP); in t1_ulp_intr_clear()
57 t1_write_reg_4(ulp->adapter, A_ULP_INT_CAUSE, 0xffffffff); in t1_ulp_intr_clear()
66 t1_write_reg_4(ulp->adapter, A_PL_ENABLE, in t1_ulp_intr_disable()
68 t1_write_reg_4(ulp->adapter, A_ULP_INT_ENABLE, 0); in t1_ulp_intr_disable()
113 t1_write_reg_4(ulp->adapter, A_ULP_INT_CAUSE, cause); in t1_ulp_intr_handler()
133 t1_write_reg_4(adapter, A_ULP_HREG_INDEX, i); in t1_ulp_init()
134 t1_write_reg_4(adapter, A_ULP_HREG_DATA, 0); in t1_ulp_init()
137 t1_write_reg_4(adapter, A_ULP_ULIMIT, pm_tx_base); in t1_ulp_init()
142 t1_write_reg_4(adapter, A_ULP_HREG_INDEX, 0); in t1_ulp_init()
[all …]
H A Dmc4.c66 t1_write_reg_4(adapter, addr, val); in wrreg_wait()
101 t1_write_reg_4(adapter, A_MC4_STROBE, in t1_mc4_init()
114 t1_write_reg_4(adapter, A_MC4_STROBE, in t1_mc4_init()
157 t1_write_reg_4(adapter, A_MC4_REFRESH, in t1_mc4_init()
161 t1_write_reg_4(adapter, A_MC4_ECC_CNTL, in t1_mc4_init()
165 t1_write_reg_4(adapter, A_MC4_BIST_ADDR_BEG, 0); in t1_mc4_init()
167 t1_write_reg_4(adapter, A_MC4_BIST_DATA, 0); in t1_mc4_init()
218 t1_write_reg_4(mc4->adapter, A_PL_ENABLE, in t1_mc4_intr_enable()
231 t1_write_reg_4(mc4->adapter, A_PL_ENABLE, in t1_mc4_intr_disable()
309 t1_write_reg_4(adap, A_MC4_BD_ADDR, start); in t1_mc4_bd_read()
[all …]
H A Dch_mac.c97 t1_write_reg_4(mac->adapter, in mac_intr_enable()
123 t1_write_reg_4(mac->adapter, in mac_intr_disable()
148 t1_write_reg_4(mac->adapter, in mac_intr_clear()
209 t1_write_reg_4(mac->adapter, in mac_set_rx_mode()
246 t1_write_reg_4(mac->adapter, in mac_set_speed_duplex_fc()
261 t1_write_reg_4(mac->adapter, in mac_enable()
276 t1_write_reg_4(mac->adapter, in mac_disable()
284 t1_write_reg_4(mac->adapter, in mac_set_ifs()
296 t1_write_reg_4(mac->adapter, in mac_enable_isl()
306 t1_write_reg_4(mac->adapter, in mac_set_mtu()
[all …]
H A Dcspi.c36 t1_write_reg_4(cspi->adapter, A_CSPI_INTR_ENABLE, 0xffffffff); in t1_cspi_intr_enable()
42 t1_write_reg_4(cspi->adapter, A_CSPI_INTR_ENABLE, 0); in t1_cspi_intr_disable()
60 t1_write_reg_4(adapter, A_CSPI_CALENDAR_LEN, 15); in t1_cspi_init()
61 t1_write_reg_4(adapter, A_CSPI_FIFO_STATUS_ENABLE, 1); in t1_cspi_init()
H A Dch_subr.c88 t1_write_reg_4(adapter, A_TPI_ADDR, addr); in __t1_tpi_write()
89 t1_write_reg_4(adapter, A_TPI_WR_DATA, value); in __t1_tpi_write()
90 t1_write_reg_4(adapter, A_TPI_CSR, F_TPIWR); in __t1_tpi_write()
119 t1_write_reg_4(adapter, A_TPI_ADDR, addr); in __t1_tpi_read()
120 t1_write_reg_4(adapter, A_TPI_CSR, 0); in __t1_tpi_read()
257 t1_write_reg_4(adapter, A_PL_CAUSE, cause); in fpga_slow_intr()
286 t1_write_reg_4(adapter, A_MI0_ADDR, in fpga_mdio_read()
305 t1_write_reg_4(adapter, A_MI0_ADDR, in fpga_mdio_write()
1051 t1_write_reg_4(adapter, A_PL_ENABLE, 0); in t1_interrupts_disable()
1090 t1_write_reg_4(adapter, A_PL_CAUSE, in t1_interrupts_clear()
[all …]
H A Dpm3393.c167 t1_write_reg_4(cmac->adapter, A_PL_ENABLE, pl_intr); in pm3393_interrupt_enable()
249 t1_write_reg_4(cmac->adapter, A_PL_CAUSE, pl_intr); in pm3393_interrupt_clear()
/illumos-gate/usr/src/uts/common/io/chxge/
H A Dsge.c283 t1_write_reg_4(sge->obj, A_SG_CONTROL, 0x0); in sge_stop()
289 t1_write_reg_4(sge->obj, A_SG_INT_CAUSE, status); in sge_stop()
509 t1_write_reg_4(sge->obj, A_SG_INT_ENABLE, 0); in t1_sge_intr_disable()
529 t1_write_reg_4(sge->obj, A_SG_INT_ENABLE, en); in t1_sge_intr_enable()
576 t1_write_reg_4(obj, A_SG_INT_CAUSE, cause); in t1_sge_intr_error_handler()
624 t1_write_reg_4(adapter, A_SG_RSPQUEUECREDIT, n); in sge_data_in()
737 t1_write_reg_4(adapter, A_SG_SLEEPING, cidx); in sge_data_in()
1437 t1_write_reg_4(ap, A_SG_CONTROL, 0); in configure_sge()
1496 t1_write_reg_4(ap, A_SG_INTRTIMER, in configure_sge()
1506 t1_write_reg_4(adapter, base_reg_lo, (u32)addr); in setup_ring_params()
[all …]
H A Dglue.c96 t1_write_reg_4(ch_t *obj, uint32_t reg_val, uint32_t write_val) in t1_write_reg_4() function
244 t1_write_reg_4(chp, pe->addr, pe->pe_reg_val); in pe_ioctl()
H A Dpe.c1519 t1_write_reg_4(adapter, A_PL_CAUSE, F_PL_INTR_EXT); in ext_intr_task()
1521 t1_write_reg_4(adapter, A_PL_ENABLE, enable | F_PL_INTR_EXT); in ext_intr_task()
1534 t1_write_reg_4(adapter, A_PL_ENABLE, enable & ~F_PL_INTR_EXT); in t1_os_elmer0_ext_intr()
1598 t1_write_reg_4(adapter, MTUREG(i), mtu); in update_mtu_tab()
H A Dch.h284 void t1_write_reg_4(ch_t *obj, uint32_t reg_val, uint32_t write_val);
H A Dch.c770 t1_write_reg_4(chp->sge->obj, A_SG_CONTROL, 0x0); in ch_quiesce()
771 t1_write_reg_4(chp->sge->obj, A_SG_INT_CAUSE, 0x0); in ch_quiesce()