/illumos-gate/usr/src/uts/sun4u/sys/ |
H A D | cheetahasm.h | 80 and afar, scr3, scr3; \ 132 add scr3, scr1, scr3; \ 173 and afar, scr3, scr3; \ 174 sllx scr3, CH_ICACHE_IDX_SHIFT, scr3; \ 196 andn scr3, CH_ICTAG_TMASK, scr3; \ 213 add scr3, scr1, scr3; \ 239 or scr3, scr1, scr3; /* or WAY bits */ \ 261 add scr3, CH_ECACHE_STGREG_SIZE, scr3 386 add scr3, CH_ECACHE_STGREG_SIZE, scr3 510 and scr3, scr1, scr3; \ [all …]
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H A D | traptrace.h | 228 sub scr3, TRAP_ENT_SIZE, scr3; \ 229 cmp scr1, scr3; \ 298 set code, scr3; \ 299 or scr2, scr3, scr2; \ 313 sll scr3, 16, scr3; \ 314 or scr2, scr3, scr2; \ 316 or scr2, scr3, scr2; \ 321 sll scr3, 16, scr3; \ 322 or scr2, scr3, scr2; \ 323 rdpr %wstate, scr3; \ [all …]
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/illumos-gate/usr/src/uts/sun4v/sys/ |
H A D | traptrace.h | 285 sub scr3, TRAP_ENT_SIZE, scr3; \ 286 cmp scr1, scr3; \ 354 set code, scr3; \ 355 or scr2, scr3, scr2; \ 369 sll scr3, 16, scr3; \ 370 or scr2, scr3, scr2; \ 372 or scr2, scr3, scr2; \ 377 sll scr3, 16, scr3; \ 378 or scr2, scr3, scr2; \ 379 rdpr %wstate, scr3; \ [all …]
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/illumos-gate/usr/src/uts/sun4u/cpu/ |
H A D | us3_jalapeno_asm.S | 182 ldxa [scr2]ASI_IO, scr3; \ 184 and scr3, scr4, scr3; \ 185 or old_lvl, scr3, old_lvl; \ 197 JP_ADJUST_FSM(0, scr3, scr4); \ 198 set jp_estar_tl0_data, scr3; \ 199 ldx [scr3], %g0; \ 201 JP_ESTAR_TRIGGER(scr3, scr4); \ 208 JP_ESTAR_TRIGGER(scr3, scr4) 247 JP_ADJUST_FSM(0, scr3, scr4); \ 248 set jp_estar_tl0_data, scr3; \ [all …]
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H A D | us3_cheetahplus_asm.S | 96 #define PN_ECACHE_REFLUSH_LINE(l2_index, l3_index, scr2, scr3) \ argument 98 set PN_L2_SET_SIZE, scr3; \ 103 sub scr2, scr3, scr2; \ 110 set PN_L3_SET_SIZE, scr3; \ 115 sub scr2, scr3, scr2; 131 #define PN_ECACHE_FLUSH_LINE(physaddr, l2_idx_out, l3_idx_out, scr3, scr4) \ argument 140 set PN_L2_IDX_DISP_FLUSH, scr3; \ 141 or l2_idx_out, scr3, l2_idx_out; \ 142 PN_ECACHE_REFLUSH_LINE(l2_idx_out, l3_idx_out, scr3, scr4)
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H A D | common_asm.S | 54 #define DELTA_NATIVE_TIME(delta, reg, scr1, scr2, scr3) \ argument 184 #define DELTA_NATIVE_TIME(delta, reg, scr1, scr2, scr3) \ argument
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/illumos-gate/usr/src/uts/sun4v/vm/ |
H A D | mach_sfmmu.h | 236 #define ITLB_STUFF(tte, scr1, scr2, scr3, scr4) \ argument 239 mov %o2, scr3; \ 253 mov scr3, %o2; \ 263 #define DTLB_STUFF(tte, scr1, scr2, scr3, scr4) \ argument 266 mov %o2, scr3; \ 280 mov scr3, %o2; \ 293 #define TTETOPFN(tte, vaddr, label, scr1, scr2, scr3) \ argument 298 add scr2, MMU_PAGESHIFT + TTE_PA_LSHIFT, scr3; \ 301 srlx tte, scr3, tte; \ 304 add scr2, MMU_PAGESHIFT, scr3; \ [all …]
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/illumos-gate/usr/src/uts/sun4u/vm/ |
H A D | mach_sfmmu.h | 215 #define ITLB_STUFF(tte, scr1, scr2, scr3, scr4) \ argument 225 #define DTLB_STUFF(tte, scr1, scr2, scr3, scr4) \ argument 239 #define TTETOPFN(tte, vaddr, label, scr1, scr2, scr3) \ argument 242 srlx tte, TTE_SZ2_SHFT, scr3; \ 243 and scr3, TTE_SZ2_BITS, scr3; /* scr3 = tte_size2 */ \ 244 or scr1, scr3, scr1; \ 248 add scr2, MMU_PAGESHIFT + TTE_PA_LSHIFT, scr3; \ 251 srlx tte, scr3, tte; \ 255 add scr2, MMU_PAGESHIFT, scr3; \ 256 sllx scr1, scr3, scr1; \
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/illumos-gate/usr/src/uts/sun4u/io/ |
H A D | panther_asm.S | 75 #define PN_ECACHE_REFLUSH_LINE(l2_index, l3_index, scr2, scr3) \ argument 77 set PN_L2_SET_SIZE, scr3; \ 82 sub scr2, scr3, scr2; \ 89 set PN_L3_SET_SIZE, scr3; \ 94 sub scr2, scr3, scr2; 110 #define PN_ECACHE_FLUSH_LINE(physaddr, l2_idx_out, l3_idx_out, scr3, scr4) \ argument 119 set PN_L2_IDX_DISP_FLUSH, scr3; \ 120 or l2_idx_out, scr3, l2_idx_out; \ 121 PN_ECACHE_REFLUSH_LINE(l2_idx_out, l3_idx_out, scr3, scr4)
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/illumos-gate/usr/src/uts/sparc/v7/sys/ |
H A D | traptrace.h | 163 #define TRACE_UNFL(code, addr, scr1, scr2, scr3) \ argument 172 TRACE_NEXT(scr1, scr2, scr3) 176 #define TRACE_UNFL(code, addr, scr1, scr2, scr3)
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