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Searched refs:scr2 (Results 1 – 18 of 18) sorted by relevance

/illumos-gate/usr/src/uts/sun4u/sys/
H A Dtraptrace.h217 add scr1, scr2, scr2; \
277 ld [scr2 + CPU_BASE_SPL], scr2; \
280 ldxa [scr2]ASI_DMMU, scr2; \
299 or scr2, scr3, scr2; \
311 sll scr2, 24, scr2; \
314 or scr2, scr3, scr2; \
316 or scr2, scr3, scr2; \
319 sll scr2, 24, scr2; \
322 or scr2, scr3, scr2; \
324 or scr2, scr3, scr2; \
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H A Dcheetahasm.h83 or scr2, CH_DCTAG_VALID_BIT, scr2; /* tag we want */ \
99 clr scr2; \
108 add scr2, 8, scr2; \
114 clr scr2; \
127 add scr2, 8, scr2; \
176 andn scr2, CH_ICPATAG_LBITS, scr2; /* mask off lower */ \
208 add scr2, 8, scr2; \
414 and scr2, COREID_MASK, scr2; \
416 sll scr1, scr2, scr2; /* ... we need to park... */ \
528 ldxa [scr3 + scr2]ASI_L2_DATA, scr2; /* Read and record */ \
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H A Dmachthread.h178 set rtt_ctx_end, scr2; \
179 cmp scr1, scr2; \
182 set rtt_ctx_start, scr2; \
183 cmp scr1, scr2; \
197 set TSTATE_KERN | TSTATE_IE, scr2; \
198 or scr1, scr2, scr2; \
199 wrpr %g0, scr2, %tstate; \
248 sethi %hi(kcontextreg), scr2; \
249 ldx [scr2 + %lo(kcontextreg)], scr2; \
251 xor scr2, scr1, scr1; \
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H A Dmachclock.h47 #define RD_TICK(out, scr1, scr2, label) \ argument
58 #define RD_CLOCK_TICK(out, scr1, scr2, label) \ argument
60 RD_TICK(out,scr1,scr2,label)
/illumos-gate/usr/src/uts/sun4v/sys/
H A Dtraptrace.h272 sll scr2, TRAPTR_SIZE_SHIFT, scr2; \
274 add scr1, scr2, scr2; \
336 ld [scr2 + CPU_BASE_SPL], scr2; \
355 or scr2, scr3, scr2; \
367 sll scr2, 24, scr2; \
370 or scr2, scr3, scr2; \
372 or scr2, scr3, scr2; \
375 sll scr2, 24, scr2; \
378 or scr2, scr3, scr2; \
380 or scr2, scr3, scr2; \
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H A Dmachclock.h55 #define RD_STICK(out, scr1, scr2, label) \ argument
58 ldx [scr1 + %lo(native_stick_offset)], scr2; \
61 sub scr1, scr2, scr2; \
63 brnz,pn scr2, .rd_stick.label; \
81 RD_STICK(out,scr1,scr2,label)
103 #define RD_TICK(out, scr1, scr2, label) \ argument
109 sub scr1, scr2, scr2; \
111 brnz,pn scr2, .rd_tick.label; \
173 sub scr1, scr2, scr2; \
175 brnz,pn scr2, .rd_stickcmpr.label; \
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/illumos-gate/usr/src/uts/sparc/v7/sys/
H A Dtraptrace.h120 CPU_INDEX(scr2); \
121 sll scr2, TRAPTR_SIZE_SHIFT, scr2; \
123 add scr2, scr1, scr1; \
126 cmp ptr, scr2; \
130 set panicstr, scr2; \
131 ld [scr2], scr2; \
132 tst scr2; \
147 and old, PSR_PIL, scr2; \
148 subcc scr1, scr2, scr1; \
165 set code, scr2; \
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/illumos-gate/usr/src/uts/intel/sys/
H A Dtraptrace.h124 addq scr2, scr1; \
176 9: movq (reg, scr1, 1), scr2; \
177 movq scr2, (ptr, scr1, 1); \
181 movq %gs:CPU_THREAD, scr2; \
183 __GETCR2(movq, scr2); \
184 movq scr2, TTR_CR2(ptr)
191 9: movl (reg, scr1, 1), scr2; \
192 movl scr2, (ptr, scr1, 1); \
196 movl %gs:CPU_THREAD, scr2; \
198 __GETCR2(movl, scr2); \
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/illumos-gate/usr/src/uts/sun4v/vm/
H A Dmach_sfmmu.h90 or scr2, %lo(KERNELBASE), scr2; \
183 srlx scr2, MMU_PAGESHIFT, scr2; /* align to page boundary */ \
185 sllx scr2, MMU_PAGESHIFT, scr2; \
190 srlx scr2, MMU_PAGESHIFT, scr2; /* align to page boundry */ \
192 sllx scr2, MMU_PAGESHIFT, scr2; \
238 mov %o1, scr2; \
252 mov scr2, %o1; \
265 mov %o1, scr2; \
279 mov scr2, %o1; \
297 add scr2, scr1, scr2; /* mulx 3 */ \
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/illumos-gate/usr/src/uts/sun4u/cpu/
H A Dus3_jalapeno_asm.S106 set speed, scr2; \
107 or scr1, scr2, scr1; \
131 srlx scr2, JBUS_SLAVE_T_PORT_BIT, scr2; \
132 btst 1, scr2; \
151 set value, scr2; \
152 or scr1, scr2, scr1; \
227 and scr2, 3, scr2; \
228 add scr2, 1, scr2; \
229 cmp scr2, 3; \
302 or scr2, scr1, scr2; \
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H A Dus3_cheetahplus_asm.S77 set CHP_ECACHE_IDX_DISP_FLUSH, scr2; \
78 or scr2, scr1, scr1; \
97 set PN_L2_MAX_SET, scr2; \
101 cmp scr2, %g0; \
103 sub scr2, scr3, scr2; \
104 mov 6, scr2; \
106 cmp scr2, %g0; \
108 sub scr2, 1, scr2; \
109 set PN_L3_MAX_SET, scr2; \
113 cmp scr2, %g0; \
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H A Dus3_cheetah_asm.S58 #define ECACHE_REFLUSH_LINE(ecache_size, alias_address, scr2) \ argument
61 #define ECACHE_FLUSH_LINE(physaddr, ecache_size, scr1, scr2) \ argument
63 add ecache_size, ecache_size, scr2; \
64 sub scr2, 1, scr2; \
65 and scr1, scr2, scr1; \
66 ASM_LDX(scr2, ecache_flushaddr); \
67 add scr1, scr2, scr1; \
68 ECACHE_REFLUSH_LINE(ecache_size, scr1, scr2)
H A Dcommon_asm.S52 #define GET_NATIVE_TIME(out, scr1, scr2) \ argument
54 #define DELTA_NATIVE_TIME(delta, reg, scr1, scr2, scr3) \ argument
60 #define WR_TICKCMPR(in, scr1, scr2, label) \ argument
182 #define GET_NATIVE_TIME(out, scr1, scr2) \ argument
184 #define DELTA_NATIVE_TIME(delta, reg, scr1, scr2, scr3) \ argument
199 #define WR_TICKCMPR(cmpr,scr1,scr2,label) \ argument
206 #define WR_TICKCMPR(in,scr1,scr2,label) \ argument
H A Dopl_olympus_asm.S448 #define OPL_TRAPTRACE(ptr, scr1, scr2, label) \ argument
459 rd %asi, scr2; \
477 wr %g0, scr2, %asi; \
483 ld [ptr + TRAPTR_LIMIT], scr2; \
486 sub scr2, TRAP_ENT_SIZE, scr2; \
487 cmp scr1, scr2; \
H A Dspitfire_asm.S311 #define GET_CPU_PRIVATE_PTR(r_or_s, scr1, scr2, label) \ argument
312 CPU_ADDR(scr1, scr2); \
/illumos-gate/usr/src/uts/sun4/sys/
H A Dclock.h244 #define NATIVE_TIME_TO_NSEC_SCALE(out, scr1, scr2, shift) \ argument
245 srlx out, 32, scr2; /* check high 32 bits */ \
247 brz,a,pt scr2, 6f; /* if clear, 32-bit fast path */\
250 srlx out, 32, scr2; /* scr2 = hi32(tick<<4) = H */ \
251 mulx scr2, scr1, scr2; /* scr2 = (H*F) */ \
256 add scr1, scr2, out; /* out = (H*F) + ((L*F) >> 32) */\
261 #define NATIVE_TIME_TO_NSEC(out, scr1, scr2) \ argument
264 NATIVE_TIME_TO_NSEC_SCALE(out, scr1, scr2, NSEC_SHIFT);
/illumos-gate/usr/src/uts/sun4u/vm/
H A Dmach_sfmmu.h122 sethi %hi(KERNELBASE), scr2; \
123 or scr2, %lo(KERNELBASE), scr2; \
124 cmp scr1, scr2; \
245 sllx scr1, 1, scr2; \
246 add scr2, scr1, scr2; /* mulx 3 */ \
250 brz,pt scr2, label##1; \
253 sllx tte, scr2, tte; \
255 add scr2, MMU_PAGESHIFT, scr3; \
258 and vaddr, scr1, scr2; \
259 srln scr2, MMU_PAGESHIFT, scr2; \
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/illumos-gate/usr/src/uts/sun4u/io/
H A Dpanther_asm.S76 set PN_L2_MAX_SET, scr2; \
79 ldxa [l2_index + scr2]ASI_L2_TAG, %g0; \
80 cmp scr2, %g0; \
82 sub scr2, scr3, scr2; \
83 mov 6, scr2; \
85 cmp scr2, %g0; \
87 sub scr2, 1, scr2; \
88 set PN_L3_MAX_SET, scr2; \
91 ldxa [l3_index + scr2]ASI_EC_DIAG, %g0; \
92 cmp scr2, %g0; \
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