1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
25 */
26
27 /*
28 * rtls -- REALTEK 8139-serials PCI Fast Ethernet Driver, Depends on the
29 * Generic LAN Driver utility functions in /kernel/misc/mac
30 *
31 * This product is covered by one or more of the following patents:
32 * US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776, and
33 * US6,327,625.
34 *
35 * Currently supports:
36 * RTL8139
37 */
38
39 #include <sys/types.h>
40 #include <sys/debug.h>
41 #include <sys/errno.h>
42
43 #include <sys/stropts.h>
44 #include <sys/stream.h>
45 #include <sys/kmem.h>
46 #include <sys/conf.h>
47 #include <sys/ddi.h>
48 #include <sys/devops.h>
49 #include <sys/ksynch.h>
50 #include <sys/stat.h>
51 #include <sys/conf.h>
52 #include <sys/modctl.h>
53 #include <sys/dlpi.h>
54 #include <sys/ethernet.h>
55 #include <sys/vlan.h>
56 #include <sys/strsun.h>
57 #include <sys/pci.h>
58 #include <sys/sunddi.h>
59 #include <sys/mii.h>
60 #include <sys/miiregs.h>
61 #include <sys/mac_provider.h>
62 #include <sys/mac_ether.h>
63
64 #include "rtls.h"
65
66 /*
67 * Declarations and Module Linkage
68 */
69
70 /*
71 * This is the string displayed by modinfo, etc.
72 */
73 static char rtls_ident[] = "RealTek 8139 Ethernet driver";
74
75 #ifdef RTLS_DEBUG
76 int rtls_debug = 0;
77 #endif
78
79 /*
80 * Required system entry points
81 */
82 static int rtls_attach(dev_info_t *, ddi_attach_cmd_t);
83 static int rtls_detach(dev_info_t *, ddi_detach_cmd_t);
84 static int rtls_quiesce(dev_info_t *);
85
86 /*
87 * Required driver entry points for MAC
88 */
89 static int rtls_m_start(void *);
90 static void rtls_m_stop(void *);
91 static int rtls_m_unicst(void *, const uint8_t *);
92 static int rtls_m_multicst(void *, boolean_t, const uint8_t *);
93 static int rtls_m_promisc(void *, boolean_t);
94 static mblk_t *rtls_m_tx(void *, mblk_t *);
95 static int rtls_m_getprop(void *, const char *, mac_prop_id_t, uint_t,
96 void *);
97 static int rtls_m_setprop(void *, const char *, mac_prop_id_t, uint_t,
98 const void *);
99 static void rtls_m_propinfo(void *, const char *, mac_prop_id_t,
100 mac_prop_info_handle_t);
101 static int rtls_m_stat(void *, uint_t, uint64_t *);
102
103 static uint_t rtls_intr(caddr_t);
104
105 /*
106 * MII entry points
107 */
108 static uint16_t rtls_mii_read(void *, uint8_t, uint8_t);
109 static void rtls_mii_write(void *, uint8_t, uint8_t, uint16_t);
110 static void rtls_mii_notify(void *, link_state_t);
111
112 /*
113 * Internal functions used by the above entry points
114 */
115 static int rtls_chip_reset(rtls_t *, boolean_t);
116 static void rtls_chip_init(rtls_t *);
117 static void rtls_chip_stop(rtls_t *rtlsp);
118 static void rtls_chip_start(rtls_t *rtlsp);
119 static void rtls_chip_restart(rtls_t *rtlsp);
120 static void rtls_get_mac_addr(rtls_t *, uint8_t *);
121 static void rtls_set_mac_addr(rtls_t *, const uint8_t *);
122 static uint_t rtls_hash_index(const uint8_t *);
123 static boolean_t rtls_send(rtls_t *, mblk_t *);
124 static void rtls_receive(rtls_t *);
125
126 /*
127 * Buffer Management Routines
128 */
129 static int rtls_alloc_bufs(rtls_t *);
130 static void rtls_free_bufs(rtls_t *);
131 static int rtls_alloc_dma_mem(rtls_t *, size_t, ddi_device_acc_attr_t *,
132 uint_t, dma_area_t *);
133 static void rtls_free_dma_mem(dma_area_t *);
134
135 #ifdef RTLS_DEBUG
136 static void rtls_reg_print(rtls_t *); /* debug routine */
137 #endif
138
139 #define RTLS_DRIVER_NAME "rtls"
140
141 /*
142 * Used for buffers allocated by ddi_dma_mem_alloc()
143 */
144 static ddi_dma_attr_t dma_attr = {
145 DMA_ATTR_V0, /* dma_attr version */
146 0, /* dma_attr_addr_lo */
147 (uint_t)0xFFFFFFFF, /* dma_attr_addr_hi */
148 0x7FFFFFFF, /* dma_attr_count_max */
149 4, /* dma_attr_align */
150 0x3F, /* dma_attr_burstsizes */
151 1, /* dma_attr_minxfer */
152 (uint_t)0xFFFFFFFF, /* dma_attr_maxxfer */
153 (uint_t)0xFFFFFFFF, /* dma_attr_seg */
154 1, /* dma_attr_sgllen */
155 1, /* dma_attr_granular */
156 0, /* dma_attr_flags */
157 };
158
159 /*
160 * PIO access attributes for registers
161 */
162 static ddi_device_acc_attr_t rtls_reg_accattr = {
163 DDI_DEVICE_ATTR_V0,
164 DDI_STRUCTURE_LE_ACC,
165 DDI_STRICTORDER_ACC
166 };
167
168 /*
169 * DMA access attributes for data
170 */
171 static ddi_device_acc_attr_t rtls_buf_accattr = {
172 DDI_DEVICE_ATTR_V0,
173 DDI_NEVERSWAP_ACC,
174 DDI_STRICTORDER_ACC
175 };
176
177 uchar_t rtls_broadcastaddr[] = {
178 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
179 };
180
181 static mac_callbacks_t rtls_m_callbacks = {
182 MC_PROPERTIES,
183 rtls_m_stat,
184 rtls_m_start,
185 rtls_m_stop,
186 rtls_m_promisc,
187 rtls_m_multicst,
188 rtls_m_unicst,
189 rtls_m_tx,
190 NULL,
191 NULL, /* mc_ioctl */
192 NULL, /* mc_getcapab */
193 NULL, /* mc_open */
194 NULL, /* mc_close */
195 rtls_m_setprop,
196 rtls_m_getprop,
197 rtls_m_propinfo
198 };
199
200 static mii_ops_t rtls_mii_ops = {
201 MII_OPS_VERSION,
202 rtls_mii_read,
203 rtls_mii_write,
204 rtls_mii_notify, /* notify */
205 NULL, /* reset */
206 };
207
208 DDI_DEFINE_STREAM_OPS(rtls_dev_ops, nulldev, nulldev, rtls_attach, rtls_detach,
209 nodev, NULL, D_MP, NULL, rtls_quiesce);
210
211 /*
212 * Standard module linkage initialization for a MAC driver
213 */
214 static struct modldrv rtls_modldrv = {
215 &mod_driverops, /* type of module. This one is a driver */
216 rtls_ident, /* short description */
217 &rtls_dev_ops /* driver specific ops */
218 };
219
220 static struct modlinkage modlinkage = {
221 MODREV_1, { (void *)&rtls_modldrv, NULL }
222 };
223
224 /*
225 * ========== RealTek chip register access Routines ==========
226 */
227 static uint8_t rtls_reg_get8(rtls_t *rtlsp, uint32_t reg);
228 #pragma inline(rtls_reg_get8)
229 static uint8_t
rtls_reg_get8(rtls_t * rtlsp,uint32_t reg)230 rtls_reg_get8(rtls_t *rtlsp, uint32_t reg)
231 {
232 uint8_t *addr;
233
234 addr = REG8(rtlsp->io_reg, reg);
235 return (ddi_get8(rtlsp->io_handle, addr));
236 }
237
238 static uint16_t rtls_reg_get16(rtls_t *rtlsp, uint32_t reg);
239 #pragma inline(rtls_reg_get16)
240 static uint16_t
rtls_reg_get16(rtls_t * rtlsp,uint32_t reg)241 rtls_reg_get16(rtls_t *rtlsp, uint32_t reg)
242 {
243 uint16_t *addr;
244
245 addr = REG16(rtlsp->io_reg, reg);
246 return (ddi_get16(rtlsp->io_handle, addr));
247 }
248
249 static uint32_t rtls_reg_get32(rtls_t *rtlsp, uint32_t reg);
250 #pragma inline(rtls_reg_get32)
251 static uint32_t
rtls_reg_get32(rtls_t * rtlsp,uint32_t reg)252 rtls_reg_get32(rtls_t *rtlsp, uint32_t reg)
253 {
254 uint32_t *addr;
255
256 addr = REG32(rtlsp->io_reg, reg);
257 return (ddi_get32(rtlsp->io_handle, addr));
258 }
259
260 static void rtls_reg_set8(rtls_t *rtlsp, uint32_t reg, uint8_t value);
261 #pragma inline(rtls_reg_set8)
262 static void
rtls_reg_set8(rtls_t * rtlsp,uint32_t reg,uint8_t value)263 rtls_reg_set8(rtls_t *rtlsp, uint32_t reg, uint8_t value)
264 {
265 uint8_t *addr;
266
267 addr = REG8(rtlsp->io_reg, reg);
268 ddi_put8(rtlsp->io_handle, addr, value);
269 }
270
271 static void rtls_reg_set16(rtls_t *rtlsp, uint32_t reg, uint16_t value);
272 #pragma inline(rtls_reg_set16)
273 static void
rtls_reg_set16(rtls_t * rtlsp,uint32_t reg,uint16_t value)274 rtls_reg_set16(rtls_t *rtlsp, uint32_t reg, uint16_t value)
275 {
276 uint16_t *addr;
277
278 addr = REG16(rtlsp->io_reg, reg);
279 ddi_put16(rtlsp->io_handle, addr, value);
280 }
281
282 static void rtls_reg_set32(rtls_t *rtlsp, uint32_t reg, uint32_t value);
283 #pragma inline(rtls_reg_set32)
284 static void
rtls_reg_set32(rtls_t * rtlsp,uint32_t reg,uint32_t value)285 rtls_reg_set32(rtls_t *rtlsp, uint32_t reg, uint32_t value)
286 {
287 uint32_t *addr;
288
289 addr = REG32(rtlsp->io_reg, reg);
290 ddi_put32(rtlsp->io_handle, addr, value);
291 }
292
293 /*
294 * ========== Module Loading Entry Points ==========
295 */
296 int
_init(void)297 _init(void)
298 {
299 int rv;
300
301 mac_init_ops(&rtls_dev_ops, RTLS_DRIVER_NAME);
302 if ((rv = mod_install(&modlinkage)) != DDI_SUCCESS) {
303 mac_fini_ops(&rtls_dev_ops);
304 }
305 return (rv);
306 }
307
308 int
_fini(void)309 _fini(void)
310 {
311 int rv;
312
313 if ((rv = mod_remove(&modlinkage)) == DDI_SUCCESS) {
314 mac_fini_ops(&rtls_dev_ops);
315 }
316 return (rv);
317 }
318
319 int
_info(struct modinfo * modinfop)320 _info(struct modinfo *modinfop)
321 {
322 return (mod_info(&modlinkage, modinfop));
323 }
324
325
326 /*
327 * ========== DDI Entry Points ==========
328 */
329
330 /*
331 * attach(9E) -- Attach a device to the system
332 *
333 * Called once for each board successfully probed.
334 */
335 static int
rtls_attach(dev_info_t * devinfo,ddi_attach_cmd_t cmd)336 rtls_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
337 {
338 rtls_t *rtlsp; /* Our private device info */
339 ddi_acc_handle_t pci_handle;
340 uint16_t pci_commond;
341 uint16_t vendorid;
342 uint16_t deviceid;
343 uint32_t device;
344 mac_register_t *macp;
345 int err;
346
347 switch (cmd) {
348 case DDI_ATTACH:
349 break;
350 case DDI_RESUME:
351 if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) {
352 return (DDI_FAILURE);
353 }
354 mutex_enter(&rtlsp->rtls_io_lock);
355 mutex_enter(&rtlsp->rtls_rx_lock);
356 mutex_enter(&rtlsp->rtls_tx_lock);
357 /*
358 * Turn on Master Enable (DMA) and IO Enable bits.
359 * Enable PCI Memory Space accesses
360 * Disable Memory Write/Invalidate
361 */
362 if (pci_config_setup(devinfo, &pci_handle) != DDI_SUCCESS) {
363 mutex_exit(&rtlsp->rtls_tx_lock);
364 mutex_exit(&rtlsp->rtls_rx_lock);
365 mutex_exit(&rtlsp->rtls_io_lock);
366 return (DDI_FAILURE);
367 }
368 pci_commond = pci_config_get16(pci_handle, PCI_CONF_COMM);
369 pci_commond &= ~PCI_COMM_MEMWR_INVAL;
370 pci_commond |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO;
371 pci_config_put32(pci_handle, PCI_CONF_COMM, pci_commond);
372 pci_config_teardown(&pci_handle);
373
374 rtls_chip_restart(rtlsp);
375 rtlsp->chip_error = B_FALSE;
376 rtlsp->tx_retry = 0;
377 rtlsp->rtls_suspended = B_FALSE;
378 mutex_exit(&rtlsp->rtls_tx_lock);
379 mutex_exit(&rtlsp->rtls_rx_lock);
380 mutex_exit(&rtlsp->rtls_io_lock);
381
382 mii_resume(rtlsp->mii);
383
384 mac_tx_update(rtlsp->mh);
385 return (DDI_SUCCESS);
386 default:
387 return (DDI_FAILURE);
388 }
389
390 /*
391 * we don't support high level interrupts in the driver
392 */
393 if (ddi_intr_hilevel(devinfo, 0) != 0) {
394 cmn_err(CE_WARN, "unsupported high level interrupt");
395 return (DDI_FAILURE);
396 }
397
398 /*
399 * Get handle to access pci configuration space
400 */
401 if (pci_config_setup(devinfo, &pci_handle) != DDI_SUCCESS) {
402 cmn_err(CE_WARN, "pci_config_setup fail.");
403 return (DDI_FAILURE);
404 }
405
406 /*
407 * Make sure we support this particular vendor/device
408 */
409 vendorid = pci_config_get16(pci_handle, PCI_CONF_VENID);
410 deviceid = pci_config_get16(pci_handle, PCI_CONF_DEVID);
411 device = vendorid;
412 device = (device << 16) | deviceid; /* combine two id together */
413
414 /*
415 * See if we support this device
416 * We do not return for wrong device id. It's user risk.
417 */
418 switch (device) {
419 default:
420 cmn_err(CE_WARN,
421 "RTLS doesn't support this device: "
422 "vendorID = 0x%x, deviceID = 0x%x",
423 vendorid, deviceid);
424 break;
425 case RTLS_SUPPORT_DEVICE_1:
426 case RTLS_SUPPORT_DEVICE_2:
427 case RTLS_SUPPORT_DEVICE_3:
428 case RTLS_SUPPORT_DEVICE_4:
429 break;
430 }
431
432 /*
433 * Turn on Master Enable (DMA) and IO Enable bits.
434 * Enable PCI Memory Space accesses
435 * Disable Memory Write/Invalidate
436 */
437 pci_commond = pci_config_get16(pci_handle, PCI_CONF_COMM);
438 pci_commond &= ~PCI_COMM_MEMWR_INVAL;
439 pci_commond |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO;
440 pci_config_put32(pci_handle, PCI_CONF_COMM, pci_commond);
441
442 /*
443 * Free handle to access pci configuration space
444 */
445 pci_config_teardown(&pci_handle);
446
447 rtlsp = kmem_zalloc(sizeof (rtls_t), KM_SLEEP);
448
449 ddi_set_driver_private(devinfo, rtlsp);
450 rtlsp->devinfo = devinfo;
451 rtlsp->instance = ddi_get_instance(devinfo);
452
453 /*
454 * Map operating register
455 */
456 err = ddi_regs_map_setup(devinfo, 1, &rtlsp->io_reg,
457 (offset_t)0, 0, &rtls_reg_accattr, &rtlsp->io_handle);
458 if (err != DDI_SUCCESS) {
459 kmem_free((caddr_t)rtlsp, sizeof (rtls_t));
460 cmn_err(CE_WARN, "ddi_regs_map_setup fail.");
461 return (DDI_FAILURE);
462 }
463
464 /*
465 * Allocate the TX and RX descriptors/buffers
466 */
467 if (rtls_alloc_bufs(rtlsp) == DDI_FAILURE) {
468 cmn_err(CE_WARN, "DMA buffer allocation fail.");
469 goto fail;
470 }
471
472 /*
473 * Reset the chip
474 */
475 err = rtls_chip_reset(rtlsp, B_FALSE);
476 if (err != DDI_SUCCESS)
477 goto fail;
478
479 /*
480 * Init rtls_t structure
481 */
482 rtls_get_mac_addr(rtlsp, rtlsp->netaddr);
483
484 /*
485 * Add the interrupt handler
486 *
487 * This will prevent receiving interrupts before device is ready, as
488 * we are initializing device after setting the interrupts. So we
489 * will not get our interrupt handler invoked by OS while our device
490 * is still coming up or timer routines will not start till we are
491 * all set to process...
492 */
493
494 if (ddi_add_intr(devinfo, 0, &rtlsp->iblk, NULL, rtls_intr,
495 (caddr_t)rtlsp) != DDI_SUCCESS) {
496 cmn_err(CE_WARN, "ddi_add_intr fail.");
497 goto late_fail;
498 }
499
500 if ((rtlsp->mii = mii_alloc(rtlsp, devinfo, &rtls_mii_ops)) == NULL) {
501 ddi_remove_intr(devinfo, 0, rtlsp->iblk);
502 goto late_fail;
503 }
504 /*
505 * Note: Some models of 8139 can support pause, but we have
506 * not implemented support for it at this time. This might be
507 * an interesting feature to add later.
508 */
509 mii_set_pauseable(rtlsp->mii, B_FALSE, B_FALSE);
510
511 if ((macp = mac_alloc(MAC_VERSION)) == NULL) {
512 cmn_err(CE_WARN, "mac_alloc fail.");
513 ddi_remove_intr(devinfo, 0, rtlsp->iblk);
514 goto late_fail;
515 }
516
517 /*
518 * Init mutex
519 */
520 mutex_init(&rtlsp->rtls_io_lock, NULL, MUTEX_DRIVER, rtlsp->iblk);
521 mutex_init(&rtlsp->rtls_tx_lock, NULL, MUTEX_DRIVER, rtlsp->iblk);
522 mutex_init(&rtlsp->rtls_rx_lock, NULL, MUTEX_DRIVER, rtlsp->iblk);
523
524 /*
525 * Initialize pointers to device specific functions which will be
526 * used by the generic layer.
527 */
528 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
529 macp->m_driver = rtlsp;
530 macp->m_dip = devinfo;
531 macp->m_src_addr = rtlsp->netaddr;
532 macp->m_callbacks = &rtls_m_callbacks;
533 macp->m_min_sdu = 0;
534 macp->m_max_sdu = ETHERMTU;
535 macp->m_margin = VLAN_TAGSZ;
536
537 if (mac_register(macp, &rtlsp->mh) != 0) {
538 ddi_remove_intr(devinfo, 0, rtlsp->iblk);
539 mutex_destroy(&rtlsp->rtls_io_lock);
540 mutex_destroy(&rtlsp->rtls_tx_lock);
541 mutex_destroy(&rtlsp->rtls_rx_lock);
542 goto late_fail;
543 }
544
545 mac_free(macp);
546
547 return (DDI_SUCCESS);
548
549 late_fail:
550 if (macp)
551 mac_free(macp);
552 if (rtlsp->mii)
553 mii_free(rtlsp->mii);
554
555 fail:
556 ddi_regs_map_free(&rtlsp->io_handle);
557 rtls_free_bufs(rtlsp);
558 kmem_free(rtlsp, sizeof (rtls_t));
559
560 return (DDI_FAILURE);
561 }
562
563 /*
564 * detach(9E) -- Detach a device from the system
565 */
566 static int
rtls_detach(dev_info_t * devinfo,ddi_detach_cmd_t cmd)567 rtls_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
568 {
569 rtls_t *rtlsp; /* our private device info */
570
571 /*
572 * Get the driver private structure
573 */
574 if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) {
575 return (DDI_FAILURE);
576 }
577
578 switch (cmd) {
579 case DDI_DETACH:
580 break;
581
582 case DDI_SUSPEND:
583 mii_suspend(rtlsp->mii);
584
585 mutex_enter(&rtlsp->rtls_io_lock);
586 mutex_enter(&rtlsp->rtls_rx_lock);
587 mutex_enter(&rtlsp->rtls_tx_lock);
588
589 rtlsp->rtls_suspended = B_TRUE;
590 rtls_chip_stop(rtlsp);
591
592 mutex_exit(&rtlsp->rtls_tx_lock);
593 mutex_exit(&rtlsp->rtls_rx_lock);
594 mutex_exit(&rtlsp->rtls_io_lock);
595 return (DDI_SUCCESS);
596
597 default:
598 return (DDI_FAILURE);
599 }
600
601 if (mac_unregister(rtlsp->mh) != 0) {
602 /* device busy */
603 return (DDI_FAILURE);
604 }
605
606 ddi_remove_intr(devinfo, 0, rtlsp->iblk);
607
608 mii_free(rtlsp->mii);
609
610 mutex_destroy(&rtlsp->rtls_io_lock);
611 mutex_destroy(&rtlsp->rtls_tx_lock);
612 mutex_destroy(&rtlsp->rtls_rx_lock);
613
614 ddi_regs_map_free(&rtlsp->io_handle);
615 rtls_free_bufs(rtlsp);
616 kmem_free(rtlsp, sizeof (rtls_t));
617
618 return (DDI_SUCCESS);
619 }
620
621 /*
622 * quiesce(9E) entry point.
623 *
624 * This function is called when the system is single-threaded at high
625 * PIL with preemption disabled. Therefore, this function must not be
626 * blocked.
627 *
628 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
629 * DDI_FAILURE indicates an error condition and should almost never happen.
630 */
631 static int
rtls_quiesce(dev_info_t * devinfo)632 rtls_quiesce(dev_info_t *devinfo)
633 {
634 rtls_t *rtlsp; /* our private device info */
635
636 /*
637 * Get the driver private structure
638 */
639 if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) {
640 return (DDI_FAILURE);
641 }
642 return (rtls_chip_reset(rtlsp, B_TRUE));
643 }
644
645 /*
646 * ========== MAC Entry Points ==========
647 */
648
649 /*
650 * rtls_m_start() -- start the board receiving and allow transmits
651 */
652 static int
rtls_m_start(void * arg)653 rtls_m_start(void *arg)
654 {
655 rtls_t *rtlsp = (rtls_t *)arg;
656
657 mutex_enter(&rtlsp->rtls_io_lock);
658 mutex_enter(&rtlsp->rtls_rx_lock);
659 mutex_enter(&rtlsp->rtls_tx_lock);
660
661 if (!rtlsp->rtls_suspended)
662 rtls_chip_restart(rtlsp);
663
664 rtlsp->rtls_running = B_TRUE;
665
666 mutex_exit(&rtlsp->rtls_tx_lock);
667 mutex_exit(&rtlsp->rtls_rx_lock);
668 mutex_exit(&rtlsp->rtls_io_lock);
669
670 drv_usecwait(100);
671
672 mii_start(rtlsp->mii);
673
674 return (0);
675 }
676
677 /*
678 * rtls_m_stop() -- stop board receiving and transmits
679 */
680 static void
rtls_m_stop(void * arg)681 rtls_m_stop(void *arg)
682 {
683 rtls_t *rtlsp = (rtls_t *)arg;
684
685 mii_stop(rtlsp->mii);
686
687 mutex_enter(&rtlsp->rtls_io_lock);
688
689 if (!rtlsp->rtls_suspended)
690 rtls_chip_stop(rtlsp);
691 rtlsp->rtls_running = B_FALSE;
692
693 mutex_exit(&rtlsp->rtls_io_lock);
694 }
695
696 /*
697 * rtls_m_unicst() -- set the physical network address
698 * on the board
699 */
700 static int
rtls_m_unicst(void * arg,const uint8_t * macaddr)701 rtls_m_unicst(void *arg, const uint8_t *macaddr)
702 {
703 rtls_t *rtlsp = arg;
704
705 mutex_enter(&rtlsp->rtls_io_lock);
706 bcopy(macaddr, rtlsp->netaddr, ETHERADDRL);
707 if (!rtlsp->rtls_suspended)
708 rtls_set_mac_addr(rtlsp, rtlsp->netaddr);
709 mutex_exit(&rtlsp->rtls_io_lock);
710 return (0);
711 }
712
713 /*
714 * rtls_m_multicst() -- set(enable) or disable a multicast address
715 *
716 * Program the hardware to enable/disable the multicast address in "mcast".
717 */
718 static int
rtls_m_multicst(void * arg,boolean_t enable,const uint8_t * mcast)719 rtls_m_multicst(void *arg, boolean_t enable, const uint8_t *mcast)
720 {
721 rtls_t *rtlsp = (rtls_t *)arg;
722 uint_t index;
723 uint32_t *hashp;
724
725 mutex_enter(&rtlsp->rtls_io_lock);
726 hashp = rtlsp->multi_hash;
727 index = rtls_hash_index(mcast);
728 /* index value is between 0 and 63 */
729
730 if (enable) {
731 if (rtlsp->multicast_cnt[index]++) {
732 mutex_exit(&rtlsp->rtls_io_lock);
733 return (0);
734 }
735 hashp[index/32] |= 1<< (index % 32);
736 } else {
737 if (--rtlsp->multicast_cnt[index]) {
738 mutex_exit(&rtlsp->rtls_io_lock);
739 return (0);
740 }
741 hashp[index/32] &= ~(1<< (index % 32));
742 }
743
744 /*
745 * Set multicast register
746 */
747 if (!rtlsp->rtls_suspended) {
748 rtls_reg_set32(rtlsp, MULTICAST_0_REG, hashp[0]);
749 rtls_reg_set32(rtlsp, MULTICAST_4_REG, hashp[1]);
750 }
751
752 mutex_exit(&rtlsp->rtls_io_lock);
753
754 return (0);
755 }
756
757 /*
758 * rtls_hash_index() -- a hashing function used for setting the
759 * node address or a multicast address
760 */
761 static uint_t
rtls_hash_index(const uint8_t * address)762 rtls_hash_index(const uint8_t *address)
763 {
764 uint32_t crc = (ulong_t)RTLS_HASH_CRC;
765 uint32_t const POLY = RTLS_HASH_POLY;
766 uint32_t msb;
767 int bytes;
768 uchar_t currentbyte;
769 uint_t index;
770 int bit;
771
772 for (bytes = 0; bytes < ETHERADDRL; bytes++) {
773 currentbyte = address[bytes];
774 for (bit = 0; bit < 8; bit++) {
775 msb = crc >> 31;
776 crc <<= 1;
777 if (msb ^ (currentbyte & 1)) {
778 crc ^= POLY;
779 crc |= 0x00000001;
780 }
781 currentbyte >>= 1;
782 }
783 }
784
785 index = crc >> 26;
786
787 return (index);
788 }
789
790 /*
791 * rtls_m_promisc() -- set or reset promiscuous mode on the board
792 */
793 static int
rtls_m_promisc(void * arg,boolean_t on)794 rtls_m_promisc(void *arg, boolean_t on)
795 {
796 rtls_t *rtlsp = arg;
797
798 mutex_enter(&rtlsp->rtls_io_lock);
799
800 rtlsp->promisc = on;
801 if (!rtlsp->rtls_suspended) {
802 uint32_t val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG);
803 if (on) {
804 val32 |= RX_ACCEPT_ALL_PACKET;
805 } else {
806 val32 &= ~RX_ACCEPT_ALL_PACKET;
807 }
808 rtls_reg_set32(rtlsp, RX_CONFIG_REG, val32);
809 }
810 mutex_exit(&rtlsp->rtls_io_lock);
811
812 return (0);
813 }
814
815 /*
816 * rtls_m_stat() -- retrieve statistic
817 *
818 * MAC calls this routine just before it reads the driver's statistics
819 * structure. If your board maintains statistics, this is the time to
820 * read them in and update the values in the structure. If the driver
821 * maintains statistics continuously, this routine need do nothing.
822 */
823 static int
rtls_m_stat(void * arg,uint_t stat,uint64_t * val)824 rtls_m_stat(void *arg, uint_t stat, uint64_t *val)
825 {
826 rtls_t *rtlsp = arg;
827
828 if (mii_m_getstat(rtlsp->mii, stat, val) == 0) {
829 return (0);
830 }
831
832 switch (stat) {
833 case MAC_STAT_IPACKETS:
834 *val = rtlsp->stats.ipackets;
835 break;
836 case MAC_STAT_RBYTES:
837 *val = rtlsp->stats.rbytes;
838 break;
839 case MAC_STAT_OPACKETS:
840 *val = rtlsp->stats.opackets;
841 break;
842 case MAC_STAT_OBYTES:
843 *val = rtlsp->stats.obytes;
844 break;
845 case MAC_STAT_IERRORS:
846 *val = rtlsp->stats.rcv_err;
847 break;
848 case MAC_STAT_OERRORS:
849 *val = rtlsp->stats.xmt_err;
850 break;
851 case MAC_STAT_MULTIRCV:
852 *val = rtlsp->stats.multi_rcv;
853 break;
854 case MAC_STAT_BRDCSTRCV:
855 *val = rtlsp->stats.brdcst_rcv;
856 break;
857 case MAC_STAT_MULTIXMT:
858 *val = rtlsp->stats.multi_xmt;
859 break;
860 case MAC_STAT_BRDCSTXMT:
861 *val = rtlsp->stats.brdcst_xmt;
862 break;
863 case MAC_STAT_UNDERFLOWS:
864 *val = rtlsp->stats.underflow;
865 break;
866 case MAC_STAT_OVERFLOWS:
867 *val = rtlsp->stats.overflow;
868 break;
869 case MAC_STAT_NORCVBUF:
870 *val = rtlsp->stats.no_rcvbuf;
871 break;
872 case MAC_STAT_COLLISIONS:
873 *val = rtlsp->stats.collisions;
874 break;
875 case ETHER_STAT_FCS_ERRORS:
876 *val = rtlsp->stats.crc_err;
877 break;
878 case ETHER_STAT_ALIGN_ERRORS:
879 *val = rtlsp->stats.frame_err;
880 break;
881 case ETHER_STAT_DEFER_XMTS:
882 *val = rtlsp->stats.defer;
883 break;
884 case ETHER_STAT_TX_LATE_COLLISIONS:
885 *val = rtlsp->stats.xmt_latecoll;
886 break;
887 case ETHER_STAT_TOOLONG_ERRORS:
888 *val = rtlsp->stats.too_long;
889 break;
890 case ETHER_STAT_TOOSHORT_ERRORS:
891 *val = rtlsp->stats.in_short;
892 break;
893 case ETHER_STAT_CARRIER_ERRORS:
894 *val = rtlsp->stats.no_carrier;
895 break;
896 case ETHER_STAT_FIRST_COLLISIONS:
897 *val = rtlsp->stats.firstcol;
898 break;
899 case ETHER_STAT_MULTI_COLLISIONS:
900 *val = rtlsp->stats.multicol;
901 break;
902 default:
903 return (ENOTSUP);
904 }
905
906 /*
907 * RTL8139 don't support MII statistics,
908 * these values are maintained by the driver software.
909 */
910
911 #ifdef RTLS_DEBUG
912 if (rtls_debug & RTLS_TRACE)
913 rtls_reg_print(rtlsp);
914 #endif
915
916 return (0);
917 }
918
919 int
rtls_m_getprop(void * arg,const char * name,mac_prop_id_t num,uint_t sz,void * val)920 rtls_m_getprop(void *arg, const char *name, mac_prop_id_t num, uint_t sz,
921 void *val)
922 {
923 rtls_t *rtlsp = arg;
924
925 return (mii_m_getprop(rtlsp->mii, name, num, sz, val));
926 }
927
928 int
rtls_m_setprop(void * arg,const char * name,mac_prop_id_t num,uint_t sz,const void * val)929 rtls_m_setprop(void *arg, const char *name, mac_prop_id_t num, uint_t sz,
930 const void *val)
931 {
932 rtls_t *rtlsp = arg;
933
934 return (mii_m_setprop(rtlsp->mii, name, num, sz, val));
935 }
936
937 static void
rtls_m_propinfo(void * arg,const char * name,mac_prop_id_t num,mac_prop_info_handle_t prh)938 rtls_m_propinfo(void *arg, const char *name, mac_prop_id_t num,
939 mac_prop_info_handle_t prh)
940 {
941 rtls_t *rtlsp = arg;
942
943 mii_m_propinfo(rtlsp->mii, name, num, prh);
944 }
945
946 /*
947 * rtls_send() -- send a packet
948 *
949 * Called when a packet is ready to be transmitted. A pointer to an
950 * M_DATA message that contains the packet is passed to this routine.
951 * The complete LLC header is contained in the message's first message
952 * block, and the remainder of the packet is contained within
953 * additional M_DATA message blocks linked to the first message block.
954 *
955 * Returns B_TRUE if the packet was properly disposed of, or B_FALSE if
956 * if the packet is being deferred and should be tried again later.
957 */
958
959 static boolean_t
rtls_send(rtls_t * rtlsp,mblk_t * mp)960 rtls_send(rtls_t *rtlsp, mblk_t *mp)
961 {
962 int totlen;
963 int ncc;
964 uint16_t cur_desc;
965 uint32_t tx_status;
966
967 ASSERT(mp != NULL);
968 ASSERT(rtlsp->rtls_running);
969
970 mutex_enter(&rtlsp->rtls_tx_lock);
971
972 if (rtlsp->rtls_suspended) {
973 mutex_exit(&rtlsp->rtls_tx_lock);
974 return (B_FALSE);
975 }
976
977 /*
978 * If chip error ...
979 */
980 if (rtlsp->chip_error) {
981 #ifdef RTLS_DEBUG
982 cmn_err(CE_WARN,
983 "%s: send fail--CHIP ERROR!",
984 mac_name(rtlsp->mh));
985 #endif
986 mutex_exit(&rtlsp->rtls_tx_lock);
987 freemsg(mp);
988 return (B_TRUE);
989 }
990
991 /*
992 * If chip link down ... Note that experimentation shows that
993 * the device seems not to care about whether or not we have
994 * this check, but if we don't add the check here, it might
995 * not be properly reported as a carrier error.
996 */
997 if (rtls_reg_get8(rtlsp, MEDIA_STATUS_REG) & MEDIA_STATUS_LINK) {
998 #ifdef RTLS_DEBUG
999 cmn_err(CE_WARN,
1000 "%s: send fail--LINK DOWN!",
1001 mac_name(rtlsp->mh));
1002 #endif
1003 rtlsp->stats.no_carrier++;
1004 mutex_exit(&rtlsp->rtls_tx_lock);
1005 freemsg(mp);
1006 return (B_TRUE);
1007 }
1008
1009 /*
1010 * Current transmit descriptor
1011 */
1012 cur_desc = rtlsp->tx_current_desc;
1013 ASSERT(cur_desc < RTLS_MAX_TX_DESC);
1014
1015 /*
1016 * RealTek 8139 has 4 tx descriptor for transmit. In the first tx loop
1017 * of transmit,we needn't judge transmit status.
1018 */
1019 if (rtlsp->tx_first_loop < RTLS_MAX_TX_DESC) {
1020 rtlsp->tx_first_loop++;
1021 goto tx_ready;
1022 }
1023
1024 /*
1025 * If it's not the first tx loop, we need judge whether the chip is
1026 * busy or not. Otherwise, we have to reschedule send and wait...
1027 */
1028 tx_status = rtls_reg_get32(rtlsp, TX_STATUS_DESC0_REG + 4 * cur_desc);
1029
1030 /*
1031 * H/W doesn't complete packet transmit
1032 */
1033 if (!(tx_status & TX_COMPLETE_FLAG)) {
1034 #ifdef RTLS_DEBUG
1035 if (rtls_debug & RTLS_SEND) {
1036 cmn_err(CE_NOTE,
1037 "%s: rtls_send: need_sched", mac_name(rtlsp->mh));
1038 }
1039 #endif
1040 /*
1041 * Through test, we find RTL8139 tx status might be
1042 * not-completing all along. We have to reset chip
1043 * to make RTL8139 tansmit re-work.
1044 */
1045 if (rtlsp->tx_retry++ > RTLS_TX_RETRY_NUM) {
1046
1047 /*
1048 * Wait transmit h/w more time...
1049 */
1050 RTLS_TX_WAIT_TIMEOUT; /* 100 ms */
1051
1052 /*
1053 * Judge tx status again, if it remains not-completing,
1054 * we can confirm RTL8139 is in chip error state
1055 * and must reset it.
1056 */
1057 tx_status = rtls_reg_get32(rtlsp,
1058 TX_STATUS_DESC0_REG + 4 * cur_desc);
1059 if (!(tx_status & TX_COMPLETE_FLAG)) {
1060 #ifdef RTLS_DEBUG
1061 cmn_err(CE_NOTE, "%s: tx chip_error = 0x%x",
1062 mac_name(rtlsp->mh), tx_status);
1063 #endif
1064 rtlsp->tx_retry = 0;
1065 rtlsp->chip_error = B_TRUE;
1066 rtlsp->stats.xmt_err++;
1067 rtlsp->stats.mac_xmt_err++;
1068 mutex_exit(&rtlsp->rtls_tx_lock);
1069 freemsg(mp);
1070 return (B_TRUE);
1071 }
1072 } else {
1073 rtlsp->stats.defer++;
1074 rtlsp->need_sched = B_TRUE;
1075 mutex_exit(&rtlsp->rtls_tx_lock);
1076 return (B_FALSE);
1077 }
1078 }
1079
1080 /*
1081 * Transmit error?
1082 */
1083 if (tx_status & TX_ERR_FLAG) {
1084 #ifdef RTLS_DEBUG
1085 if (rtls_debug & RTLS_SEND) {
1086 cmn_err(CE_NOTE, "%s: transmit error, status = 0x%x",
1087 mac_name(rtlsp->mh), tx_status);
1088 }
1089 #endif
1090 rtlsp->stats.xmt_err++;
1091 if (tx_status & TX_STATUS_TX_UNDERRUN)
1092 rtlsp->stats.underflow++;
1093 if (tx_status & TX_STATUS_CS_LOST)
1094 rtlsp->stats.no_carrier++;
1095 if (tx_status & TX_STATUS_OWC)
1096 rtlsp->stats.xmt_latecoll++;
1097 }
1098 ncc = ((tx_status & TX_STATUS_NCC) >> TX_STATUS_NCC_SHIFT);
1099 if (ncc != 0) {
1100 rtlsp->stats.collisions += ncc;
1101 rtlsp->stats.firstcol++;
1102 rtlsp->stats.multicol += ncc - 1;
1103 }
1104
1105 tx_ready:
1106 /*
1107 * Initialize variable
1108 */
1109 rtlsp->tx_retry = 0;
1110 totlen = 0;
1111
1112 /*
1113 * Copy packet to tx descriptor buffer
1114 */
1115 totlen = msgsize(mp);
1116 if (totlen > (ETHERMAX + 4)) { /* 4 bytes for VLAN header */
1117 cmn_err(CE_NOTE,
1118 "%s: rtls_send: try to send large %d packet",
1119 mac_name(rtlsp->mh), totlen);
1120 rtlsp->stats.mac_xmt_err++;
1121 rtlsp->stats.xmt_err++;
1122 freemsg(mp);
1123 mutex_exit(&rtlsp->rtls_tx_lock);
1124 return (B_TRUE);
1125 }
1126
1127 /* this will free the mblk */
1128 mcopymsg(mp, rtlsp->tx_buf[cur_desc]);
1129
1130 /* update stats */
1131 if (*rtlsp->tx_buf[cur_desc] & 0x1) {
1132 uint16_t *ptr = (void *)rtlsp->tx_buf[cur_desc];
1133 if ((ptr[0] == 0xffff) &&
1134 (ptr[1] == 0xffff) &&
1135 (ptr[2] == 0xffff)) {
1136 rtlsp->stats.brdcst_xmt++;
1137 } else {
1138 rtlsp->stats.multi_xmt++;
1139 }
1140 }
1141 rtlsp->stats.opackets++;
1142 rtlsp->stats.obytes += totlen;
1143
1144 if (totlen < ETHERMIN) {
1145 bzero(rtlsp->tx_buf[cur_desc] + totlen, ETHERMIN - totlen);
1146 totlen = ETHERMIN;
1147 }
1148
1149 /* make sure caches are flushed */
1150 (void) ddi_dma_sync(rtlsp->dma_area_tx[cur_desc].dma_hdl, 0, totlen,
1151 DDI_DMA_SYNC_FORDEV);
1152
1153 /*
1154 * Start transmit
1155 * set transmit FIFO threshhold to 0x30*32 = 1536 bytes
1156 * to avoid tx underrun.
1157 */
1158 rtls_reg_set32(rtlsp, TX_STATUS_DESC0_REG + 4 * cur_desc,
1159 totlen | (0x30 << TX_STATUS_TX_THRESHOLD_SHIFT));
1160
1161 /*
1162 * Update the value of current tx descriptor
1163 */
1164 cur_desc++;
1165 cur_desc %= RTLS_MAX_TX_DESC;
1166 rtlsp->tx_current_desc = cur_desc;
1167
1168 mutex_exit(&rtlsp->rtls_tx_lock);
1169
1170 return (B_TRUE);
1171 }
1172
1173 /*
1174 * rtls_m_tx() -- send a chain of packets, linked by mp->b_next.
1175 */
1176 static mblk_t *
rtls_m_tx(void * arg,mblk_t * mp)1177 rtls_m_tx(void *arg, mblk_t *mp)
1178 {
1179 rtls_t *rtlsp = arg;
1180 mblk_t *next;
1181
1182 while (mp != NULL) {
1183 next = mp->b_next;
1184 mp->b_next = NULL;
1185 if (!rtls_send(rtlsp, mp)) {
1186 mp->b_next = next;
1187 break;
1188 }
1189 mp = next;
1190 }
1191 return (mp);
1192 }
1193
1194 /*
1195 * rtls_receive() -- receive packets
1196 *
1197 * Called when receive interrupts detected
1198 */
1199 static void
rtls_receive(rtls_t * rtlsp)1200 rtls_receive(rtls_t *rtlsp)
1201 {
1202 mblk_t *head = NULL;
1203 mblk_t **mpp;
1204 mblk_t *mp;
1205 uint16_t rx_status;
1206 uint16_t packet_len;
1207 int wrap_size;
1208 uint32_t cur_rx;
1209 uint8_t *rx_ptr;
1210
1211 mpp = &head;
1212
1213 mutex_enter(&rtlsp->rtls_rx_lock);
1214
1215 if (rtlsp->rtls_suspended) {
1216 mutex_exit(&rtlsp->rtls_rx_lock);
1217 return;
1218 }
1219
1220 while ((rtls_reg_get8(rtlsp, RT_COMMAND_REG)
1221 & RT_COMMAND_BUFF_EMPTY) == 0) {
1222
1223 /*
1224 * Chip error state
1225 */
1226 if (rtlsp->chip_error) {
1227 #ifdef RTLS_DEBUG
1228 cmn_err(CE_WARN,
1229 "%s: receive fail--CHIP ERROR!",
1230 mac_name(rtlsp->mh));
1231 #endif
1232 break;
1233 }
1234
1235 cur_rx = rtlsp->cur_rx;
1236 rx_ptr = rtlsp->rx_ring + cur_rx;
1237 packet_len = (rx_ptr[3] << 8) | (rx_ptr[2]);
1238 rx_status = rx_ptr[0];
1239
1240 /*
1241 * DMA still in progress
1242 */
1243 if (packet_len == RX_STATUS_DMA_BUSY) {
1244 cmn_err(CE_NOTE, "%s: Rx DMA still in progress",
1245 mac_name(rtlsp->mh));
1246 break;
1247 }
1248
1249 /*
1250 * Check receive status
1251 */
1252 if ((rx_status & RX_ERR_FLAGS) ||
1253 (!(rx_status & RX_HEADER_STATUS_ROK)) ||
1254 (packet_len < (ETHERMIN + ETHERFCSL)) ||
1255 (packet_len > (ETHERMAX + ETHERFCSL + 4))) {
1256 #ifdef RTLS_DEBUG
1257 cmn_err(CE_NOTE,
1258 "%s: receive error, status = 0x%x, length = %d",
1259 mac_name(rtlsp->mh), rx_status, packet_len);
1260 #endif
1261 /*
1262 * Rx error statistics
1263 */
1264 if ((rx_status & RX_HEADER_STATUS_RUNT) ||
1265 (packet_len < (ETHERMIN + ETHERFCSL)))
1266 rtlsp->stats.in_short++;
1267 else if (packet_len > (ETHERMAX + ETHERFCSL + 4))
1268 rtlsp->stats.too_long++;
1269 else if (rx_status & RX_HEADER_STATUS_CRC)
1270 rtlsp->stats.crc_err++;
1271 else if (rx_status & RX_HEADER_STATUS_FAE)
1272 rtlsp->stats.frame_err++;
1273
1274 /*
1275 * Set chip_error flag to reset chip:
1276 * (suggested in RealTek programming guide.)
1277 */
1278 rtlsp->chip_error = B_TRUE;
1279 mutex_exit(&rtlsp->rtls_rx_lock);
1280 return;
1281 }
1282
1283 /*
1284 * We need not up-send ETHERFCSL bytes of receive packet
1285 */
1286 packet_len -= ETHERFCSL;
1287
1288 /*
1289 * Allocate buffer to receive this good packet
1290 */
1291 mp = allocb(packet_len, 0);
1292
1293 /*
1294 * Copy the data found into the new cluster, we have (+4)
1295 * to get us past the packet head data that the rtl chip
1296 * places at the start of the message
1297 */
1298 if ((cur_rx + packet_len + RX_HEADER_SIZE)
1299 > RTLS_RX_BUF_RING) {
1300 wrap_size = cur_rx + packet_len + RX_HEADER_SIZE
1301 - RTLS_RX_BUF_RING;
1302 #ifdef RTLS_DEBUG
1303 if (rtls_debug & RTLS_RECV) {
1304 cmn_err(CE_NOTE,
1305 "%s: Rx: packet_len = %d, wrap_size = %d",
1306 mac_name(rtlsp->mh), packet_len, wrap_size);
1307 }
1308 #endif
1309
1310 if (mp != NULL) {
1311 /* Flush caches */
1312 (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl,
1313 cur_rx + RX_HEADER_SIZE,
1314 packet_len - wrap_size,
1315 DDI_DMA_SYNC_FORKERNEL);
1316 (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl,
1317 0, wrap_size,
1318 DDI_DMA_SYNC_FORKERNEL);
1319
1320 /*
1321 * Copy in first section of message as stored
1322 * at the end of the ring buffer
1323 */
1324 bcopy(rx_ptr + RX_HEADER_SIZE,
1325 mp->b_wptr, packet_len - wrap_size);
1326 mp->b_wptr += packet_len - wrap_size;
1327 bcopy(rtlsp->rx_ring, mp->b_wptr, wrap_size);
1328 mp->b_wptr += wrap_size;
1329 *mpp = mp;
1330 mpp = &mp->b_next;
1331
1332 rtlsp->stats.ipackets++;
1333 if (rx_status & RX_HEADER_STATUS_BCAST)
1334 rtlsp->stats.brdcst_rcv++;
1335 if (rx_status & RX_HEADER_STATUS_MULTI)
1336 rtlsp->stats.multi_rcv++;
1337 rtlsp->stats.rbytes += packet_len;
1338 } else {
1339 rtlsp->stats.no_rcvbuf++;
1340 }
1341
1342 cur_rx = RTLS_RX_ADDR_ALIGNED(wrap_size + ETHERFCSL);
1343 /* 4-byte aligned */
1344 } else {
1345
1346 if (mp != NULL) {
1347 /* Flush caches */
1348 (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl,
1349 cur_rx + RX_HEADER_SIZE, packet_len,
1350 DDI_DMA_SYNC_FORKERNEL);
1351 bcopy(rx_ptr + RX_HEADER_SIZE, mp->b_wptr,
1352 packet_len);
1353 mp->b_wptr += packet_len;
1354 *mpp = mp;
1355 mpp = &mp->b_next;
1356
1357 rtlsp->stats.ipackets++;
1358 if (rx_status & RX_HEADER_STATUS_BCAST)
1359 rtlsp->stats.brdcst_rcv++;
1360 if (rx_status & RX_HEADER_STATUS_MULTI)
1361 rtlsp->stats.multi_rcv++;
1362 rtlsp->stats.rbytes += packet_len;
1363 } else {
1364 rtlsp->stats.no_rcvbuf++;
1365 }
1366 cur_rx += packet_len + RX_HEADER_SIZE + ETHERFCSL;
1367
1368 cur_rx = RTLS_RX_ADDR_ALIGNED(cur_rx);
1369 /* 4-byte aligned */
1370 }
1371
1372 /*
1373 * Update rx buffer ring read pointer:
1374 * give us a little leeway to ensure no overflow
1375 */
1376 rtlsp->cur_rx = cur_rx;
1377 rtls_reg_set16(rtlsp, RX_CURRENT_READ_ADDR_REG,
1378 cur_rx - READ_ADDR_GAP);
1379 }
1380 mutex_exit(&rtlsp->rtls_rx_lock);
1381
1382 /*
1383 * Upsend packet
1384 */
1385 if (head) {
1386 mac_rx(rtlsp->mh, NULL, head);
1387 }
1388 }
1389
1390 /*
1391 * rtls_intr() -- interrupt from board to inform us that a receive or
1392 * link change.
1393 */
1394 static uint_t
rtls_intr(caddr_t arg)1395 rtls_intr(caddr_t arg)
1396 {
1397 rtls_t *rtlsp = (void *)arg;
1398 uint32_t int_status;
1399 uint32_t val32;
1400 boolean_t resched = B_FALSE;
1401
1402 mutex_enter(&rtlsp->rtls_io_lock);
1403 if (rtlsp->rtls_suspended) {
1404 mutex_exit(&rtlsp->rtls_io_lock);
1405 return (DDI_INTR_UNCLAIMED);
1406 }
1407
1408 /*
1409 * Was this interrupt caused by our device...
1410 */
1411 int_status = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG);
1412 if (!(int_status & rtlsp->int_mask)) {
1413 mutex_exit(&rtlsp->rtls_io_lock);
1414 return (DDI_INTR_UNCLAIMED);
1415 /* indicate it wasn't our interrupt */
1416 }
1417
1418 /*
1419 * Clear interrupt
1420 */
1421 rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, int_status);
1422
1423 /*
1424 * If chip error, restart chip...
1425 */
1426 if (rtlsp->chip_error) {
1427 mutex_enter(&rtlsp->rtls_rx_lock);
1428 mutex_enter(&rtlsp->rtls_tx_lock);
1429 rtls_chip_restart(rtlsp);
1430 rtlsp->chip_error = B_FALSE;
1431 rtlsp->tx_retry = 0;
1432 mutex_exit(&rtlsp->rtls_tx_lock);
1433 mutex_exit(&rtlsp->rtls_rx_lock);
1434 mutex_exit(&rtlsp->rtls_io_lock);
1435 return (DDI_INTR_CLAIMED);
1436 /* no need to hand other interrupts */
1437 }
1438
1439 /*
1440 * Transmit error interrupt
1441 */
1442 if (int_status & TX_ERR_INT) {
1443 val32 = rtls_reg_get32(rtlsp, TX_CONFIG_REG);
1444 val32 |= TX_CLEAR_ABORT;
1445 rtls_reg_set32(rtlsp, TX_CONFIG_REG, val32);
1446 cmn_err(CE_WARN, "%s: transmit abort!!!", mac_name(rtlsp->mh));
1447 }
1448
1449 /*
1450 * Trigger mac_tx_update
1451 */
1452 if (rtlsp->need_sched) {
1453 rtlsp->need_sched = B_FALSE;
1454 resched = B_TRUE;
1455 }
1456
1457 mutex_exit(&rtlsp->rtls_io_lock);
1458
1459 /*
1460 * Receive interrupt
1461 */
1462 if (int_status & RTLS_RX_INT) {
1463 if (int_status & RX_OVERFLOW_INT) {
1464 rtlsp->stats.overflow++;
1465 rtlsp->stats.rcv_err++;
1466 }
1467 rtls_receive(rtlsp);
1468 }
1469
1470 /*
1471 * Link change interrupt.
1472 */
1473 if (int_status & LINK_CHANGE_INT) {
1474 mii_check(rtlsp->mii);
1475 }
1476
1477 if (resched) {
1478 mac_tx_update(rtlsp->mh);
1479 }
1480
1481 return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */
1482 }
1483
1484 /*
1485 * ========== Buffer Management Routines ==========
1486 */
1487
1488 /*
1489 * rtls_alloc_dma_mem() -- allocate an area of memory and a DMA handle
1490 * for accessing it
1491 */
1492 static int
rtls_alloc_dma_mem(rtls_t * rtlsp,size_t memsize,ddi_device_acc_attr_t * attr_p,uint_t dma_flags,dma_area_t * dma_p)1493 rtls_alloc_dma_mem(rtls_t *rtlsp, size_t memsize,
1494 ddi_device_acc_attr_t *attr_p, uint_t dma_flags, dma_area_t *dma_p)
1495 {
1496 caddr_t vaddr;
1497 int err;
1498
1499 /*
1500 * Allocate handle
1501 */
1502 err = ddi_dma_alloc_handle(rtlsp->devinfo, &dma_attr,
1503 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl);
1504 if (err != DDI_SUCCESS) {
1505 cmn_err(CE_WARN,
1506 "%s: rtls_alloc_dma_mem: ddi_dma_alloc_handle failed: %d",
1507 mac_name(rtlsp->mh), err);
1508 dma_p->dma_hdl = NULL;
1509 return (DDI_FAILURE);
1510 }
1511
1512 /*
1513 * Allocate memory
1514 */
1515 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p,
1516 dma_flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING),
1517 DDI_DMA_SLEEP, NULL, &vaddr, &dma_p->alength, &dma_p->acc_hdl);
1518 if (err != DDI_SUCCESS) {
1519 cmn_err(CE_WARN,
1520 "%s: rtls_alloc_dma_mem: ddi_dma_mem_alloc failed: %d",
1521 mac_name(rtlsp->mh), err);
1522 ddi_dma_free_handle(&dma_p->dma_hdl);
1523 dma_p->dma_hdl = NULL;
1524 dma_p->acc_hdl = NULL;
1525 return (DDI_FAILURE);
1526 }
1527
1528 /*
1529 * Bind the two together
1530 */
1531 dma_p->mem_va = vaddr;
1532 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL,
1533 vaddr, dma_p->alength, dma_flags, DDI_DMA_SLEEP, NULL,
1534 &dma_p->cookie, &dma_p->ncookies);
1535 if (err != DDI_DMA_MAPPED || dma_p->ncookies != 1) {
1536 cmn_err(CE_WARN,
1537 "%s: rtls_alloc_dma_mem: "
1538 "ddi_dma_addr_bind_handle failed: %d",
1539 mac_name(rtlsp->mh), err);
1540 ddi_dma_mem_free(&dma_p->acc_hdl);
1541 ddi_dma_free_handle(&dma_p->dma_hdl);
1542 dma_p->acc_hdl = NULL;
1543 dma_p->dma_hdl = NULL;
1544 return (DDI_FAILURE);
1545 }
1546
1547 return (DDI_SUCCESS);
1548 }
1549
1550 /*
1551 * rtls_free_dma_mem() -- free one allocated area of DMAable memory
1552 */
1553 static void
rtls_free_dma_mem(dma_area_t * dma_p)1554 rtls_free_dma_mem(dma_area_t *dma_p)
1555 {
1556 if (dma_p->dma_hdl != NULL) {
1557 if (dma_p->ncookies) {
1558 (void) ddi_dma_unbind_handle(dma_p->dma_hdl);
1559 dma_p->ncookies = 0;
1560 }
1561 ddi_dma_free_handle(&dma_p->dma_hdl);
1562 dma_p->dma_hdl = NULL;
1563 }
1564
1565 if (dma_p->acc_hdl != NULL) {
1566 ddi_dma_mem_free(&dma_p->acc_hdl);
1567 dma_p->acc_hdl = NULL;
1568 }
1569 }
1570
1571 /*
1572 * rtls_alloc_bufs() -- allocate descriptors/buffers for this device instance
1573 */
1574 static int
rtls_alloc_bufs(rtls_t * rtlsp)1575 rtls_alloc_bufs(rtls_t *rtlsp)
1576 {
1577 int i;
1578 int err;
1579
1580 /*
1581 * Allocate memory & handle for Tx buffers
1582 */
1583 for (i = 0; i < RTLS_MAX_TX_DESC; i++) {
1584 err = rtls_alloc_dma_mem(rtlsp,
1585 RTLS_TX_BUF_SIZE,
1586 &rtls_buf_accattr,
1587 DDI_DMA_WRITE | DDI_DMA_STREAMING,
1588 &rtlsp->dma_area_tx[i]);
1589
1590 if (err != DDI_SUCCESS)
1591 return (DDI_FAILURE);
1592
1593 rtlsp->tx_buf[i] = (uint8_t *)rtlsp->dma_area_tx[i].mem_va;
1594 }
1595
1596 /*
1597 * Allocate memory & handle for Rx buffers
1598 */
1599 err = rtls_alloc_dma_mem(rtlsp,
1600 RTLS_RX_BUF_SIZE,
1601 &rtls_buf_accattr,
1602 DDI_DMA_READ | DDI_DMA_STREAMING,
1603 &rtlsp->dma_area_rx);
1604
1605 if (err != DDI_SUCCESS)
1606 return (DDI_FAILURE);
1607
1608 rtlsp->rx_ring = (uint8_t *)rtlsp->dma_area_rx.mem_va;
1609
1610 return (DDI_SUCCESS);
1611 }
1612
1613 /*
1614 * rtls_free_bufs() -- free descriptors/buffers allocated for this
1615 * device instance.
1616 */
1617 static void
rtls_free_bufs(rtls_t * rtlsp)1618 rtls_free_bufs(rtls_t *rtlsp)
1619 {
1620 int i;
1621
1622 for (i = 0; i < RTLS_MAX_TX_DESC; i++) {
1623 rtls_free_dma_mem(&rtlsp->dma_area_tx[i]);
1624 rtlsp->tx_buf[i] = NULL;
1625 }
1626
1627 rtls_free_dma_mem(&rtlsp->dma_area_rx);
1628 rtlsp->rx_ring = NULL;
1629 }
1630
1631 /*
1632 * ========== Chip H/W Operation Routines ==========
1633 */
1634
1635 /*
1636 * rtls_chip_reset() -- reset chip
1637 */
1638 static int
rtls_chip_reset(rtls_t * rtlsp,boolean_t quiesce)1639 rtls_chip_reset(rtls_t *rtlsp, boolean_t quiesce)
1640 {
1641 int i;
1642 uint16_t val16;
1643 uint8_t val8;
1644
1645 /*
1646 * Chip should be in STOP state
1647 */
1648 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG);
1649 val8 &= ~(RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE);
1650 rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8);
1651
1652 /*
1653 * Disable interrupt
1654 */
1655 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG);
1656 rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 & (~RTLS_INT_MASK_ALL));
1657 rtlsp->int_mask = RTLS_INT_MASK_NONE;
1658
1659 /*
1660 * Clear pended interrupt
1661 */
1662 val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG);
1663 rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, val16);
1664
1665 /*
1666 * Reset chip
1667 */
1668 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG);
1669 rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8 | RT_COMMAND_RESET);
1670
1671 /*
1672 * Wait for reset success
1673 */
1674 i = 0;
1675 while (rtls_reg_get8(rtlsp, RT_COMMAND_REG) & RT_COMMAND_RESET) {
1676 if (++i > RTLS_RESET_WAIT_NUM) {
1677 /*
1678 * At quiesce path we can't call cmn_err(), as
1679 * it might block
1680 */
1681 if (!quiesce)
1682 cmn_err(CE_WARN,
1683 "%s: chip reset fail.",
1684 mac_name(rtlsp->mh));
1685 return (DDI_FAILURE);
1686 }
1687 RTLS_RESET_WAIT_INTERVAL;
1688 }
1689
1690 return (DDI_SUCCESS);
1691 }
1692
1693 /*
1694 * rtls_chip_init() -- initialize the specified network board short of
1695 * actually starting the board. Call after rtls_chip_reset().
1696 */
1697 static void
rtls_chip_init(rtls_t * rtlsp)1698 rtls_chip_init(rtls_t *rtlsp)
1699 {
1700 uint32_t val32;
1701 uint16_t val16;
1702 uint8_t val8;
1703
1704 /*
1705 * Initialize internal data structures
1706 */
1707 rtlsp->cur_rx = 0;
1708 rtlsp->tx_current_desc = 0;
1709 rtlsp->tx_first_loop = 0;
1710
1711 /*
1712 * Set DMA physical rx/tx buffer address to register
1713 */
1714 rtls_reg_set32(rtlsp, RX_BUFF_ADDR_REG,
1715 (ulong_t)rtlsp->dma_area_rx.cookie.dmac_address);
1716 rtls_reg_set32(rtlsp, TX_ADDR_DESC0_REG,
1717 (ulong_t)rtlsp->dma_area_tx[0].cookie.dmac_address);
1718 rtls_reg_set32(rtlsp, TX_ADDR_DESC1_REG,
1719 (ulong_t)rtlsp->dma_area_tx[1].cookie.dmac_address);
1720 rtls_reg_set32(rtlsp, TX_ADDR_DESC2_REG,
1721 (ulong_t)rtlsp->dma_area_tx[2].cookie.dmac_address);
1722 rtls_reg_set32(rtlsp, TX_ADDR_DESC3_REG,
1723 (ulong_t)rtlsp->dma_area_tx[3].cookie.dmac_address);
1724
1725 /*
1726 * Start transmit/receive before set tx/rx configuration register
1727 */
1728 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG);
1729 rtls_reg_set8(rtlsp, RT_COMMAND_REG,
1730 val8 | RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE);
1731
1732 /*
1733 * Set transmit configuration register
1734 */
1735 val32 = rtls_reg_get32(rtlsp, TX_CONFIG_REG);
1736 val32 &= TX_CONSIG_REG_RESERVE;
1737 rtls_reg_set32(rtlsp, TX_CONFIG_REG, val32 | TX_CONFIG_DEFAULT);
1738
1739 /*
1740 * Set receive configuration register
1741 */
1742 val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG);
1743 val32 &= RX_CONSIG_REG_RESERVE;
1744 if (rtlsp->promisc)
1745 val32 |= RX_ACCEPT_ALL_PACKET;
1746 rtls_reg_set32(rtlsp, RX_CONFIG_REG, val32 | RX_CONFIG_DEFAULT);
1747
1748 /*
1749 * Set multicast register
1750 */
1751 rtls_reg_set32(rtlsp, MULTICAST_0_REG, rtlsp->multi_hash[0]);
1752 rtls_reg_set32(rtlsp, MULTICAST_4_REG, rtlsp->multi_hash[1]);
1753
1754 /*
1755 * Set unicast address
1756 */
1757 rtls_set_mac_addr(rtlsp, rtlsp->netaddr);
1758
1759 /*
1760 * Set current address of packet read
1761 */
1762 rtls_reg_set16(rtlsp, RX_CURRENT_READ_ADDR_REG, RX_READ_RESET_VAL);
1763
1764 /*
1765 * No early-rx interrupts
1766 */
1767 val16 = rtls_reg_get16(rtlsp, RT_MUL_INTSEL_REG);
1768 val16 &= ~RT_MUL_INTSEL_BITS;
1769 rtls_reg_set16(rtlsp, RT_MUL_INTSEL_REG, val16);
1770 }
1771
1772 /*
1773 * rtls_chip_start() -- start chip
1774 */
1775 static void
rtls_chip_start(rtls_t * rtlsp)1776 rtls_chip_start(rtls_t *rtlsp)
1777 {
1778 uint16_t val16;
1779 uint8_t val8;
1780
1781 /*
1782 * Start transmit/receive
1783 */
1784 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG);
1785 rtls_reg_set8(rtlsp, RT_COMMAND_REG,
1786 val8 | RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE);
1787
1788 /*
1789 * Enable interrupt
1790 */
1791 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG);
1792 rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 | RTLS_INT_MASK);
1793 rtlsp->int_mask = RTLS_INT_MASK;
1794 }
1795
1796 /*
1797 * rtls_chip_restart() -- restart chip
1798 */
1799 static void
rtls_chip_restart(rtls_t * rtlsp)1800 rtls_chip_restart(rtls_t *rtlsp)
1801 {
1802 (void) rtls_chip_reset(rtlsp, B_FALSE);
1803 rtls_chip_init(rtlsp);
1804 rtls_chip_start(rtlsp);
1805 }
1806
1807 /*
1808 * rtls_chip_stop() -- stop board receiving
1809 */
1810 static void
rtls_chip_stop(rtls_t * rtlsp)1811 rtls_chip_stop(rtls_t *rtlsp)
1812 {
1813 uint16_t val16;
1814 uint8_t val8;
1815
1816 /*
1817 * Disable interrupt
1818 */
1819 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG);
1820 rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 & (~RTLS_INT_MASK_ALL));
1821 rtlsp->int_mask = RTLS_INT_MASK_NONE;
1822
1823 /*
1824 * Clear pended interrupt
1825 */
1826 val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG);
1827 rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, val16);
1828
1829 /*
1830 * Stop the board and disable transmit/receive
1831 */
1832 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG);
1833 val8 &= ~(RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE);
1834 rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8);
1835 }
1836
1837 /*
1838 * rtls_get_mac_addr() -- get the physical network address on the board
1839 */
1840 static void
rtls_get_mac_addr(rtls_t * rtlsp,uint8_t * macaddr)1841 rtls_get_mac_addr(rtls_t *rtlsp, uint8_t *macaddr)
1842 {
1843 uint32_t val32;
1844
1845 /*
1846 * Read first 4-byte of mac address
1847 */
1848 val32 = rtls_reg_get32(rtlsp, ID_0_REG);
1849 macaddr[0] = val32 & 0xff;
1850 val32 = val32 >> 8;
1851 macaddr[1] = val32 & 0xff;
1852 val32 = val32 >> 8;
1853 macaddr[2] = val32 & 0xff;
1854 val32 = val32 >> 8;
1855 macaddr[3] = val32 & 0xff;
1856
1857 /*
1858 * Read last 2-byte of mac address
1859 */
1860 val32 = rtls_reg_get32(rtlsp, ID_4_REG);
1861 macaddr[4] = val32 & 0xff;
1862 val32 = val32 >> 8;
1863 macaddr[5] = val32 & 0xff;
1864 }
1865
1866 static void
rtls_set_mac_addr(rtls_t * rtlsp,const uint8_t * macaddr)1867 rtls_set_mac_addr(rtls_t *rtlsp, const uint8_t *macaddr)
1868 {
1869 uint32_t val32;
1870 uint8_t val8;
1871
1872 /*
1873 * Change to config register write enable mode
1874 */
1875 val8 = rtls_reg_get8(rtlsp, RT_93c46_COMMAND_REG);
1876 val8 |= RT_93c46_MODE_CONFIG;
1877 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8);
1878
1879 /*
1880 * Get first 4 bytes of mac address
1881 */
1882 val32 = macaddr[3];
1883 val32 = val32 << 8;
1884 val32 |= macaddr[2];
1885 val32 = val32 << 8;
1886 val32 |= macaddr[1];
1887 val32 = val32 << 8;
1888 val32 |= macaddr[0];
1889
1890 /*
1891 * Set first 4 bytes of mac address
1892 */
1893 rtls_reg_set32(rtlsp, ID_0_REG, val32);
1894
1895 /*
1896 * Get last 2 bytes of mac address
1897 */
1898 val32 = macaddr[5];
1899 val32 = val32 << 8;
1900 val32 |= macaddr[4];
1901
1902 /*
1903 * Set last 2 bytes of mac address
1904 */
1905 val32 |= rtls_reg_get32(rtlsp, ID_4_REG) & ~0xffff;
1906 rtls_reg_set32(rtlsp, ID_4_REG, val32);
1907
1908 /*
1909 * Return to normal network/host communication mode
1910 */
1911 val8 &= ~RT_93c46_MODE_CONFIG;
1912 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8);
1913 }
1914
1915 static uint16_t
rtls_mii_read(void * arg,uint8_t phy,uint8_t reg)1916 rtls_mii_read(void *arg, uint8_t phy, uint8_t reg)
1917 {
1918 rtls_t *rtlsp = arg;
1919 uint16_t val;
1920
1921 if (phy != 1) {
1922 return (0xffff);
1923 }
1924 switch (reg) {
1925 case MII_CONTROL:
1926 val = rtls_reg_get16(rtlsp, BASIC_MODE_CONTROL_REG);
1927 break;
1928 case MII_STATUS:
1929 val = rtls_reg_get16(rtlsp, BASIC_MODE_STATUS_REG);
1930 break;
1931 case MII_AN_ADVERT:
1932 val = rtls_reg_get16(rtlsp, AUTO_NEGO_AD_REG);
1933 break;
1934 case MII_AN_LPABLE:
1935 val = rtls_reg_get16(rtlsp, AUTO_NEGO_LP_REG);
1936 break;
1937 case MII_AN_EXPANSION:
1938 val = rtls_reg_get16(rtlsp, AUTO_NEGO_EXP_REG);
1939 break;
1940 case MII_VENDOR(0):
1941 /*
1942 * We "simulate" a vendor private register so that the
1943 * PHY layer can access it to determine detected link
1944 * speed/duplex.
1945 */
1946 val = rtls_reg_get8(rtlsp, MEDIA_STATUS_REG);
1947 break;
1948 case MII_PHYIDH:
1949 case MII_PHYIDL:
1950 default:
1951 val = 0;
1952 break;
1953 }
1954 return (val);
1955 }
1956
1957 void
rtls_mii_write(void * arg,uint8_t phy,uint8_t reg,uint16_t val)1958 rtls_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val)
1959 {
1960 rtls_t *rtlsp = arg;
1961 uint8_t val8;
1962
1963 if (phy != 1) {
1964 return;
1965 }
1966 switch (reg) {
1967 case MII_CONTROL:
1968 /* Enable writes to all bits of BMCR */
1969 val8 = rtls_reg_get8(rtlsp, RT_93c46_COMMAND_REG);
1970 val8 |= RT_93c46_MODE_CONFIG;
1971 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8);
1972 /* write out the value */
1973 rtls_reg_set16(rtlsp, BASIC_MODE_CONTROL_REG, val);
1974
1975 /* Return to normal network/host communication mode */
1976 val8 &= ~RT_93c46_MODE_CONFIG;
1977 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8);
1978 return;
1979
1980 case MII_STATUS:
1981 rtls_reg_set16(rtlsp, BASIC_MODE_STATUS_REG, val);
1982 break;
1983 case MII_AN_ADVERT:
1984 rtls_reg_set16(rtlsp, AUTO_NEGO_AD_REG, val);
1985 break;
1986 case MII_AN_LPABLE:
1987 rtls_reg_set16(rtlsp, AUTO_NEGO_LP_REG, val);
1988 break;
1989 case MII_AN_EXPANSION:
1990 rtls_reg_set16(rtlsp, AUTO_NEGO_EXP_REG, val);
1991 break;
1992 case MII_PHYIDH:
1993 case MII_PHYIDL:
1994 default:
1995 /* these are not writable */
1996 break;
1997 }
1998 }
1999
2000 void
rtls_mii_notify(void * arg,link_state_t link)2001 rtls_mii_notify(void *arg, link_state_t link)
2002 {
2003 rtls_t *rtlsp = arg;
2004
2005 mac_link_update(rtlsp->mh, link);
2006 }
2007
2008 #ifdef RTLS_DEBUG
2009 /*
2010 * rtls_reg_print() -- print out reg value(for debug use only)
2011 */
2012 static void
rtls_reg_print(rtls_t * rtlsp)2013 rtls_reg_print(rtls_t *rtlsp)
2014 {
2015 uint8_t val8;
2016 uint16_t val16;
2017 uint32_t val32;
2018
2019 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG);
2020 cmn_err(CE_NOTE, "%s: RT_COMMAND_REG = 0x%x",
2021 mac_name(rtlsp->mh), val8);
2022 delay(drv_usectohz(1000));
2023
2024 val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG);
2025 cmn_err(CE_NOTE, "%s: RT_INT_STATUS_REG = 0x%x",
2026 mac_name(rtlsp->mh), val16);
2027 delay(drv_usectohz(1000));
2028
2029 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG);
2030 cmn_err(CE_NOTE, "%s: RT_INT_MASK_REG = 0x%x",
2031 mac_name(rtlsp->mh), val16);
2032 delay(drv_usectohz(1000));
2033
2034 val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG);
2035 cmn_err(CE_NOTE, "%s: RX_CONFIG_REG = 0x%x",
2036 mac_name(rtlsp->mh), val32);
2037 delay(drv_usectohz(1000));
2038
2039 val16 = rtls_reg_get16(rtlsp, TX_DESC_STAUS_REG);
2040 cmn_err(CE_NOTE, "%s: TX_DESC_STAUS_REG = 0x%x, cur_desc = %d",
2041 mac_name(rtlsp->mh), val16, rtlsp->tx_current_desc);
2042 delay(drv_usectohz(1000));
2043
2044 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC0_REG);
2045 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC0_REG = 0x%x",
2046 mac_name(rtlsp->mh), val32);
2047 delay(drv_usectohz(1000));
2048
2049 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC1_REG);
2050 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC1_REG = 0x%x",
2051 mac_name(rtlsp->mh), val32);
2052 delay(drv_usectohz(1000));
2053
2054 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC2_REG);
2055 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC2_REG = 0x%x",
2056 mac_name(rtlsp->mh), val32);
2057 delay(drv_usectohz(1000));
2058
2059 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC3_REG);
2060 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC3_REG = 0x%x",
2061 mac_name(rtlsp->mh), val32);
2062 delay(drv_usectohz(1000));
2063
2064 cmn_err(CE_NOTE, "%s: in = %llu, multicast = %llu, broadcast = %llu",
2065 mac_name(rtlsp->mh),
2066 (unsigned long long)rtlsp->stats.ipackets,
2067 (unsigned long long)rtlsp->stats.multi_rcv,
2068 (unsigned long long)rtlsp->stats.brdcst_rcv);
2069 delay(drv_usectohz(1000));
2070 }
2071 #endif
2072