xref: /illumos-gate/usr/src/uts/common/io/nge/nge_chip.h (revision 9868091d)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _SYS_NGE_CHIP_H
28 #define	_SYS_NGE_CHIP_H
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
34 #include "nge.h"
35 
36 #define	VENDOR_ID_NVIDIA	0x10de
37 
38 #define	DEVICE_ID_MCP04_37	0x37
39 #define	DEVICE_ID_MCP04_38	0x38
40 #define	DEVICE_ID_CK804_56	0x56
41 #define	DEVICE_ID_CK804_57	0x57
42 #define	DEVICE_ID_MCP51_269	0x269
43 #define	DEVICE_ID_MCP51_268	0x268
44 #define	DEVICE_ID_MCP55_373	0x373
45 #define	DEVICE_ID_MCP55_372	0x372
46 #define	DEVICE_ID_MCP61_3EE	0x3ee
47 #define	DEVICE_ID_MCP61_3EF	0x3ef
48 #define	DEVICE_ID_MCP77_760	0x760
49 #define	DEVICE_ID_MCP79_AB0	0xab0
50 #define	DEVICE_ID_NF3_E6	0xe6
51 #define	DEVICE_ID_NF3_DF	0xdf
52 
53 /* Private PCI configuration register for bus config of ck804/mcp55 */
54 #define	PCI_CONF_HT_INTERNAL	0x4c
55 
56 typedef union _nge_interbus_conf {
57 	uint32_t	conf_val;
58 	struct {
59 		uint32_t	unit_id:5;
60 		uint32_t	resv5_23:19;
61 		uint32_t	aux_val:3;
62 		uint32_t	resv27:1;
63 		uint32_t	msi_off:1;
64 		uint32_t	msix_off:1; /* mcp55 only */
65 		uint32_t	resv30_31:2;
66 	} conf_bits;
67 } nge_interbus_conf;
68 
69 /* Private PCI configuration register for MSI mask of mcp55 */
70 #define	PCI_CONF_HT_MSI_MASK	0x60
71 
72 typedef union _nge_msi_mask_conf {
73 	uint32_t	msi_mask_conf_val;
74 	struct {
75 		uint32_t	vec0_off:1;
76 		uint32_t	vec1_off:1;
77 		uint32_t	vec2_off:1;
78 		uint32_t	vec3_off:1;
79 		uint32_t	vec4_off:1;
80 		uint32_t	vec5_off:1;
81 		uint32_t	vec6_off:1;
82 		uint32_t	vec7_off:1;
83 		uint32_t	resv8_31:24;
84 	} msi_mask_bits;
85 } nge_msi_mask_conf;
86 
87 /* Private PCI configuration register for MSI map capability of mcp55 */
88 #define	PCI_CONF_HT_MSI_MAP_CAP	0x6c
89 
90 typedef union _nge_msi_map_cap_conf {
91 	uint32_t	msi_map_cap_conf_val;
92 	struct {
93 		uint32_t	cap_id:8;
94 		uint32_t	next_ptr:8;
95 		uint32_t	map_en:1;
96 		uint32_t	map_fixed:1;
97 		uint32_t	resv18_26:9;
98 		uint32_t	cap_type:5;
99 	} map_cap_conf_bits;
100 } nge_msi_map_cap_conf;
101 
102 /*
103  * Master interrupt
104  */
105 #define	NGE_INTR_SRC		0x000
106 #define	INTR_SRC_ALL		0x00007fff
107 typedef union _nge_intr_src {
108 	uint32_t	intr_val;
109 	struct {
110 		uint32_t	reint:1;
111 		uint32_t	rcint:1;
112 		uint32_t	miss:1;
113 		uint32_t	teint:1;
114 		uint32_t	tcint:1;
115 		uint32_t	stint:1;
116 		uint32_t	mint:1;
117 		uint32_t	rfint:1;
118 		uint32_t	tfint:1;
119 		uint32_t	feint:1;
120 		uint32_t	resv10:1;
121 		uint32_t	resv11:1;
122 		uint32_t	resv12:1;
123 		uint32_t	resv13:1;
124 		uint32_t	phyint:1;
125 		uint32_t	resv15_31:17;
126 	} int_bits;
127 } nge_intr_src;
128 
129 /*
130  * Master interrupt Mask
131  */
132 #define	NGE_INTR_MASK		0x004
133 #define	NGE_INTR_ALL_EN		0x00007fff
134 typedef union _nge_intr_mask {
135 	uint32_t	mask_val;
136 	struct {
137 		uint32_t	reint:1;
138 		uint32_t	rcint:1;
139 		uint32_t	miss:1;
140 		uint32_t	teint:1;
141 		uint32_t	tcint:1;
142 		uint32_t	stint:1;
143 		uint32_t	mint:1;
144 		uint32_t	rfint:1;
145 		uint32_t	tfint:1;
146 		uint32_t	feint:1;
147 		uint32_t	resv10:1;
148 		uint32_t	resv11:1;
149 		uint32_t	resv12:1;
150 		uint32_t	resv13:1;
151 		uint32_t	phyint:1;
152 		uint32_t	resv15_31:17;
153 	} mask_bits;
154 } nge_intr_mask;
155 
156 /*
157  * Software timer control register
158  */
159 #define	NGE_SWTR_CNTL		0x008
160 typedef union _nge_swtr_cntl {
161 	uint8_t	ctrl_val;
162 	struct {
163 		uint8_t	stren:1;
164 		uint8_t	sten:1;
165 		uint8_t	resv2_7:6;
166 	} cntl_bits;
167 } nge_swtr_cntl;
168 
169 /*
170  * Software Timer Interval
171  */
172 #define	NGE_SWTR_ITC		0x00c
173 
174 /* Default timer interval, 97 would mean 1 ms */
175 #define	SWTR_ITC		0x8
176 typedef union _nge_itc {
177 	uint32_t	itc_val;
178 	struct {
179 		uint32_t	sw_intv:16;
180 		uint32_t	sw_cur_val:16;
181 	} itc_bits;
182 } nge_itc;
183 
184 /*
185  * Fatal error register
186  */
187 #define	NGE_REG010		0x010
188 typedef union _nge_reg010 {
189 	uint32_t	reg010_val;
190 	struct {
191 		uint32_t	resv0:1;
192 		uint32_t	resv1:1;
193 		uint32_t	resv2:1;
194 		uint32_t	resv3:1;
195 		uint32_t	resv4:1;
196 		uint32_t	resv5:1;
197 		uint32_t	resv6:1;
198 		uint32_t	resv7:1;
199 		uint32_t	resv8:1;
200 		uint32_t	resv9:1;
201 		uint32_t	resv10:1;
202 		uint32_t	resv11_31:21;
203 	} reg010_bits;
204 } nge_reg010;
205 
206 /*
207  * MSI vector map register 0
208  */
209 #define	NGE_MSI_MAP0		0x020
210 typedef union _nge_msi_map0_vec {
211 	uint32_t msi_map0_val;
212 	struct {
213 		uint32_t reint_vec:4;
214 		uint32_t rcint_vec:4;
215 		uint32_t miss_vec:4;
216 		uint32_t teint_vec:4;
217 		uint32_t tcint_vec:4;
218 		uint32_t stint_vec:4;
219 		uint32_t mint_vec:4;
220 		uint32_t rfint_vec:4;
221 	} vecs_bits;
222 } nge_msi_map0_vec;
223 
224 /*
225  * MSI vector map register 1
226  */
227 #define	NGE_MSI_MAP1		0x024
228 typedef union _nge_msi_map1_vec {
229 	uint32_t msi_map1_val;
230 	struct {
231 		uint32_t tfint_vec:4;
232 		uint32_t feint_vec:4;
233 		uint32_t resv8_11:4;
234 		uint32_t resv12_15:4;
235 		uint32_t resv16_19:4;
236 		uint32_t resv20_23:4;
237 		uint32_t resv24_31:8;
238 	} vecs_bits;
239 } nge_msi_map1_vec;
240 
241 
242 /*
243  * MSI vector map register 2
244  */
245 #define	NGE_MSI_MAP2		0x028
246 
247 /*
248  * MSI vector map register 2
249  */
250 #define	NGE_MSI_MAP3		0x02c
251 
252 /*
253  * MSI mask register for mcp55
254  */
255 #define	NGE_MSI_MASK	0x30
256 typedef union _nge_msi_mask {
257 	uint32_t	msi_mask_val;
258 	struct {
259 		uint32_t	vec0:1;
260 		uint32_t	vec1:1;
261 		uint32_t	vec2:1;
262 		uint32_t	vec3:1;
263 		uint32_t	vec4:1;
264 		uint32_t	vec5:1;
265 		uint32_t	vec6:1;
266 		uint32_t	vec7:1;
267 		uint32_t	resv8_31:24;
268 	}msi_msk_bits;
269 }nge_msi_mask;
270 
271 /*
272  * Software misc register for mcp51
273  */
274 #define	NGE_SOFT_MISC		0x034
275 typedef union _nge_soft_misc {
276 	uint32_t misc_val;
277 	struct {
278 		uint32_t	rx_clk_vx_rst:1;
279 		uint32_t	tx_clk_vx_rst:1;
280 		uint32_t	clk12m_vx_rst:1;
281 		uint32_t	fpci_clk_vx_rst:1;
282 		uint32_t	rx_clk_vc_rst:1;
283 		uint32_t	tx_clk_vc_rst:1;
284 		uint32_t	fs_clk_vc_rst:1;
285 		uint32_t	rst_ex_m2pintf:1;
286 		uint32_t	resv8_31:24;
287 	} misc_bits;
288 } nge_soft_misc;
289 
290 /*
291  * DMA configuration
292  */
293 #define	NGE_DMA_CFG		0x040
294 typedef union _nge_dma_cfg {
295 	uint32_t cfg_val;
296 	struct {
297 		uint32_t	tx_start_pri:3;
298 		uint32_t	tx_start_pri_flag:1;
299 		uint32_t	tx_prd_rpri:3;
300 		uint32_t	tx_prd_rpri_flag:1;
301 		uint32_t	tx_prd_wpri:3;
302 		uint32_t	tx_prd_wpri_flag:1;
303 		uint32_t	rx_start_pri:3;
304 		uint32_t	rx_start_pri_flag:1;
305 		uint32_t	rx_prd_rpri:3;
306 		uint32_t	rx_prd_rpri_flag:1;
307 		uint32_t	rx_prd_wpri:3;
308 		uint32_t	rx_prd_wpri_flag:1;
309 		uint32_t	dma_max_pri:3;
310 		uint32_t	dma_wrr_disable:1;
311 		uint32_t	dma_pri_disable:1;
312 	} cfg_bits;
313 } nge_dma_cfg;
314 
315 /*
316  * Request DMA configuration
317  */
318 #define	NGE_DMA_RCFG		0x044
319 typedef union _nge_dma_rcfg {
320 	uint32_t dma_rcfg_val;
321 	struct {
322 		uint32_t	tx_prd_coh_state:2;
323 		uint32_t	tx_data_coh_state:2;
324 		uint32_t	rx_prd_coh_state:2;
325 		uint32_t	rx_data_coh_state:2;
326 		uint32_t	max_roffset:5;
327 		uint32_t	resv13_31:19;
328 	} rcfg_bis;
329 } nge_dma_rcfg;
330 
331 /*
332  * Hot DMA configuration
333  */
334 #define	NGE_DMA_HOT_CFG		0x048
335 typedef union _nge_dma_hcfg {
336 	uint32_t	dma_hcfg_val;
337 	struct {
338 		uint32_t	resv0_3:4;
339 		uint32_t	noti_wstart_pri:3;
340 		uint32_t	noti_wstart_pri_flag:1;
341 		uint32_t	cmd_rstart_pri:3;
342 		uint32_t	cmd_rstart_pri_flag:1;
343 		uint32_t	cmd_wstart_pri:3;
344 		uint32_t	cmd_wstart_pri_flag:1;
345 		uint32_t	resv16_31:16;
346 	} hcfg_bits;
347 } nge_dma_hcfg;
348 
349 /*
350  * PMU control register 0 for mcp51
351  */
352 #define	NGE_PMU_CNTL0			0x060
353 #define	NGE_PMU_CORE_SPD10_BUSY		0x8
354 #define	NGE_PMU_CORE_SPD10_IDLE		0xB
355 #define	NGE_PMU_CORE_SPD100_BUSY	0x4
356 #define	NGE_PMU_CORE_SPD100_IDLE	0x7
357 #define	NGE_PMU_CORE_SPD1000_BUSY	0x0
358 #define	NGE_PMU_CORE_SPD1000_IDLE	0x3
359 
360 typedef union _nge_pmu_cntl0 {
361 	uint32_t	cntl0_val;
362 	struct {
363 		uint32_t	core_spd10_fp:4;
364 		uint32_t	core_spd10_idle:4;
365 		uint32_t	core_spd100_fp:4;
366 		uint32_t	core_spd100_idle:4;
367 		uint32_t	core_spd1000_fp:4;
368 		uint32_t	core_spd1000_idle:4;
369 		uint32_t	core_sts_cur:8;
370 	} cntl0_bits;
371 } nge_pmu_cntl0;
372 
373 /*
374  * PMU control register 1 for mcp51
375  */
376 #define	NGE_PMU_CNTL1		0x064
377 typedef union _nge_pmu_cntl1 {
378 	uint32_t	cntl1_val;
379 	struct {
380 		uint32_t	dev_fp:4;
381 		uint32_t	dev_idle:4;
382 		uint32_t	resv8_27:20;
383 		uint32_t	dev_sts_cur:4;
384 	} cntl1_bits;
385 } nge_pmu_cntl1;
386 
387 /*
388  * PMU control register 2 for mcp51
389  */
390 #define	NGE_PMU_CNTL2		0x068
391 typedef union _nge_pmu_cntl2 {
392 	uint32_t	cntl2_val;
393 	struct {
394 		uint32_t	core_override:4;
395 		uint32_t	resv4_7:4;
396 		uint32_t	dev_override:4;
397 		uint32_t	resv12_15:4;
398 		uint32_t	core_override_en:1;
399 		uint32_t	dev_override_en:1;
400 		uint32_t	core_enable:1;
401 		uint32_t	dev_enable:1;
402 		uint32_t	rx_wake_dis:1;
403 		uint32_t	cidle_timer:1;
404 		uint32_t	didle_timer:1;
405 		uint32_t	resv23_31:9;
406 	} cntl2_bits;
407 } nge_pmu_cntl2;
408 
409 /*
410  * PMU core idle limit register for mcp51
411  */
412 #define	NGE_PMU_CIDLE_LIMIT	0x06c
413 #define	NGE_PMU_CIDLE_LIMIT_DEF	0xffff
414 
415 /*
416  * PMU device idle limit register for mcp51
417  */
418 #define	NGE_PMU_DIDLE_LIMIT	0x070
419 #define	NGE_PMU_DIDLE_LIMIT_DEF	0xffff
420 
421 /*
422  * PMU core idle count value register for mcp51
423  */
424 #define	NGE_PMU_CIDLE_COUNT	0x074
425 #define	NGE_PMU_CIDEL_COUNT_DEF	0xffff
426 
427 /*
428  * PMU device idle count value register for mcp51
429  */
430 #define	NGE_PMU_DIDLE_COUNT	0x078
431 #define	NGE_PMU_DIDEL_COUNT_DEF	0xffff
432 
433 /*
434  * Transmit control
435  */
436 #define	NGE_TX_CNTL		0x080
437 typedef union _nge_tx_cntl {
438 	uint32_t	cntl_val;
439 	struct {
440 		uint32_t	paen:1; /* only for mcp55, otherwise reserve */
441 		uint32_t	resv1:1;
442 		uint32_t	retry_en:1;
443 		uint32_t	pad_en:1;
444 		uint32_t	fappend_en:1;
445 		uint32_t	two_def_en:1;
446 		uint32_t	resv6_7:2;
447 		uint32_t	max_retry:4;
448 		uint32_t	burst_en:1;
449 		uint32_t	resv13_15:3;
450 		uint32_t	retry_emask:1;
451 		uint32_t	exdef_mask:1;
452 		uint32_t	def_mask:1;
453 		uint32_t	lcar_mask:1;
454 		uint32_t	tlcol_mask:1;
455 		uint32_t	uflo_err_mask:1;
456 		uint32_t	resv22_23:2;
457 		uint32_t	jam_seq_en:1;
458 		uint32_t	resv25_31:7;
459 	} cntl_bits;
460 } nge_tx_cntl;
461 
462 /*
463  * Transmit enable
464  * Note: for ck804 or mcp51, this is 8-bit register;
465  * for mcp55, it is a 32-bit register.
466  */
467 #define	NGE_TX_EN		0x084
468 #define	NGE_SMU_FREE		0x0
469 #define	NGE_SMU_GET		0xf
470 typedef union _nge_tx_en {
471 	uint32_t	val;
472 	struct {
473 		uint32_t	tx_en:1;
474 		uint32_t	resv1_7:7;
475 		uint32_t	smu2mac:4;
476 		uint32_t	mac2smu:4;
477 		uint32_t	resv16_31:16;
478 	} bits;
479 } nge_tx_en;
480 
481 /*
482  * Transmit status
483  */
484 #define	NGE_TX_STA		0x088
485 typedef union _nge_tx_sta {
486 	uint32_t	sta_val;
487 	struct {
488 		uint32_t	tx_chan_sta:1;
489 		uint32_t	resv1_15:15;
490 		uint32_t	retry_err:1;
491 		uint32_t	exdef:1;
492 		uint32_t	def:1;
493 		uint32_t	lcar:1;
494 		uint32_t	tlcol:1;
495 		uint32_t	uflo:1;
496 		uint32_t	resv22_31:10;
497 	} sta_bits;
498 } nge_tx_sta;
499 
500 /*
501  * Receive control
502  */
503 #define	NGE_RX_CNTL0		0x08c
504 typedef union _nge_rx_cntrl0 {
505 	uint32_t	cntl_val;
506 	struct {
507 		uint32_t	resv0:1;
508 		uint32_t	padsen:1;
509 		uint32_t	fcsren:1;
510 		uint32_t	paen:1;
511 		uint32_t	lben:1;
512 		uint32_t	afen:1;
513 		uint32_t	runten:1;
514 		uint32_t	brdis:1;
515 		uint32_t	rdfen:1;
516 		uint32_t	slfb:1;
517 		uint32_t	resv10_15:6;
518 		uint32_t	runtm:1;
519 		uint32_t	rlcolm:1;
520 		uint32_t	maxerm:1;
521 		uint32_t	lferm:1;
522 		uint32_t	crcm:1;
523 		uint32_t	ofolm:1;
524 		uint32_t	framerm:1;
525 		uint32_t	resv23_31:9;
526 	} cntl_bits;
527 } nge_rx_cntrl0;
528 
529 /*
530  * Maximum receive Frame size
531  */
532 #define	NGE_RX_CNTL1		0x090
533 typedef union _nge_rx_cntl1 {
534 	uint32_t	cntl_val;
535 	struct {
536 		uint32_t	length:14;
537 		uint32_t	resv14_31:18;
538 	} cntl_bits;
539 } nge_rx_cntl1;
540 
541 /*
542  * Receive enable register
543  * Note: for ck804 and mcp51, this is a 8-bit register;
544  * for mcp55, it is a 32-bit register.
545  */
546 #define	NGE_RX_EN		0x094
547 typedef union _nge_rx_en {
548 	uint8_t	val;
549 	struct {
550 		uint8_t	rx_en:1;
551 		uint8_t	resv1_7:7;
552 	} bits;
553 } nge_rx_en;
554 
555 /*
556  * Receive status register
557  */
558 #define	NGE_RX_STA		0x098
559 typedef union _nge_rx_sta {
560 	uint32_t	sta_val;
561 	struct {
562 		uint32_t	rx_chan_sta:1;
563 		uint32_t	resv1_15:15;
564 		uint32_t	runt_sta:1;
565 		uint32_t	rlcol_sta:1;
566 		uint32_t	mlen_err:1;
567 		uint32_t	lf_err:1;
568 		uint32_t	crc_err:1;
569 		uint32_t	ofol_err:1;
570 		uint32_t	fram_err:1;
571 		uint32_t	resv23_31:9;
572 	} sta_bits;
573 } nge_rx_sta;
574 
575 /*
576  * Backoff Control
577  */
578 #define	NGE_BKOFF_CNTL		0x09c
579 #define	BKOFF_RSEED		0x8
580 #define	BKOFF_SLIM_GMII		0x3ff
581 #define	BKOFF_SLIM_MII		0x7f
582 typedef union _nge_bkoff_cntl	{
583 	uint32_t	cntl_val;
584 	struct {
585 		uint32_t	rseed:8;
586 		uint32_t	sltm:10;
587 		uint32_t	resv18_30:13;
588 		uint32_t	leg_bk_en:1;
589 	} bkoff_bits;
590 } nge_bkoff_cntl;
591 
592 /*
593  * Transmit defferral timing
594  */
595 #define	NGE_TX_DEF		0x0a0
596 #define	TX_TIFG_MII		0x15
597 #define	TX_IFG_RGMII_1000_FD	0x14
598 #define	TX_IFG_RGMII_OTHER	0x16
599 #define	TX_IFG2_MII		0x5
600 #define	TX_IFG2_RGMII_10_100	0x7
601 #define	TX_IFG2_RGMII_1000	0x5
602 #define	TX_IFG2_DEFAULT		0X0
603 #define	TX_IFG1_DEFAULT		0xf
604 typedef union _nge_tx_def {
605 	uint32_t	def_val;
606 	struct {
607 		uint32_t	ifg1_def:8;
608 		uint32_t	ifg2_def:8;
609 		uint32_t	if_def:8;
610 		uint32_t	resv24_31:8;
611 	} def_bits;
612 } nge_tx_def;
613 
614 /*
615  * Receive defferral timing
616  */
617 #define	NGE_RX_DEf		0x0a4
618 #define	RX_DEF_DEFAULT		0x16
619 typedef union _nge_rx_def {
620 	uint8_t	def_val;
621 	struct {
622 		uint8_t rifg;
623 	} def_bits;
624 } nge_rx_def;
625 
626 /*
627  * Low 32 bit unicast address
628  */
629 #define	NGE_UNI_ADDR0		0x0a8
630 typedef union _nge_uni_addr0 {
631 	uint32_t	addr_val;
632 	struct {
633 		uint32_t	addr;
634 	} addr_bits;
635 } nge_uni_addr0;
636 
637 /*
638  * High 32 bit unicast address
639  */
640 #define	NGE_UNI_ADDR1		0x0ac
641 typedef union _nge_uni_addr1 {
642 	uint32_t	addr_val;
643 	struct {
644 		uint32_t	addr:16;
645 		uint32_t	resv16_31:16;
646 	} addr_bits;
647 } nge_uni_addr1;
648 
649 #define	LOW_24BITS_MASK		0xffffffULL
650 #define	REVERSE_MAC_ELITE	0x211900ULL
651 #define	REVERSE_MAC_GIGABYTE	0xe61600ULL
652 #define	REVERSE_MAC_ASUS	0x601d00ULL
653 
654 /*
655  * Low 32 bit multicast address
656  */
657 #define	NGE_MUL_ADDR0		0x0b0
658 typedef union _nge_mul_addr0 {
659 	uint32_t	addr_val;
660 	struct {
661 		uint32_t	addr;
662 	}addr_bits;
663 } nge_mul_addr0;
664 
665 /*
666  * High 32 bit multicast address
667  */
668 #define	NGE_MUL_ADDR1		0x0b4
669 typedef union _nge_mul_addr1 {
670 	uint32_t	addr_val;
671 	struct {
672 		uint32_t	addr:16;
673 		uint32_t	resv16_31:16;
674 	}addr_bits;
675 } nge_mul_addr1;
676 
677 /*
678  * Low 32 bit multicast mask
679  */
680 #define	NGE_MUL_MASK		0x0b8
681 typedef union _nge_mul_mask0 {
682 	uint32_t	mask_val;
683 	struct {
684 		uint32_t	mask;
685 	} mask_bits;
686 } nge_mul_mask0;
687 
688 /*
689  * High 32 bit multicast mask
690  */
691 #define	NGE_MUL_MASK1		0x0bc
692 typedef union _nge_mul_mask1 {
693 	uint32_t	mask_val;
694 	struct {
695 		uint32_t	mask:16;
696 		uint32_t	resv16_31:16;
697 	} mask_bits;
698 } nge_mul_mask1;
699 
700 /*
701  * Mac-to Phy Interface
702  */
703 #define	NGE_MAC2PHY		0x0c0
704 #define	low_speed		0x0
705 #define	fast_speed		0x1
706 #define	giga_speed		0x2
707 #define	err_speed		0x4
708 #define	MII_IN			0x0
709 #define	RGMII_IN		0x1
710 #define	ERR_IN1			0x3
711 #define	ERR_IN2			0x4
712 typedef union _nge_mac2phy {
713 	uint32_t	m2p_val;
714 	struct {
715 		uint32_t	speed:2;
716 		uint32_t	resv2_7:6;
717 		uint32_t	hdup_en:1;
718 		uint32_t	resv9:1;
719 		uint32_t	phyintr:1;    /* for mcp55 only */
720 		uint32_t	phyintrlvl:1; /* for mcp55 only */
721 		uint32_t	resv12_27:16;
722 		uint32_t	in_type:2;
723 		uint32_t	resv30_31:2;
724 	} m2p_bits;
725 } nge_mac2phy;
726 
727 /*
728  * Transmit Descriptor Ring address
729  */
730 #define	NGE_TX_DADR		0x100
731 typedef union _nge_tx_addr	{
732 	uint32_t	addr_val;
733 	struct {
734 		uint32_t	resv0_2:3;
735 		uint32_t	addr:29;
736 	} addr_bits;
737 } nge_tx_addr;
738 
739 /*
740  * Receive Descriptor Ring address
741  */
742 #define	NGE_RX_DADR		0x104
743 typedef union _nge_rx_addr {
744 	uint32_t	addr_val;
745 	struct {
746 		uint32_t	resv0_2:3;
747 		uint32_t	addr:29;
748 	} addr_bits;
749 } nge_rx_addr;
750 
751 /*
752  * Rx/tx descriptor ring leng
753  * Note: for mcp55, tdlen/rdlen are 14 bit.
754  */
755 #define	NGE_RXTX_DLEN		0x108
756 typedef union _nge_rxtx_dlen {
757 	uint32_t	dlen_val;
758 	struct {
759 		uint32_t	tdlen:14;
760 		uint32_t	resv14_15:2;
761 		uint32_t	rdlen:14;
762 		uint32_t	resv30_31:2;
763 	} dlen_bits;
764 } nge_rxtx_dlen;
765 
766 /*
767  * Transmit polling register
768  */
769 #define	NGE_TX_POLL		0x10c
770 #define	TX_POLL_INTV_1G		10
771 #define	TX_POLL_INTV_100M	100
772 #define	TX_POLL_INTV_10M	1000
773 
774 typedef union _nge_tx_poll {
775 	uint32_t	poll_val;
776 	struct {
777 		uint32_t	tpi:16;
778 		uint32_t	tpen:1;
779 		uint32_t	resv17_31:15;
780 	} poll_bits;
781 } nge_tx_poll;
782 
783 /*
784  * Receive polling register
785  */
786 #define	NGE_RX_POLL		0x110
787 #define	RX_POLL_INTV_1G		10
788 #define	RX_POLL_INTV_100M	100
789 #define	RX_POLL_INTV_10M	1000
790 typedef union _nge_rx_poll {
791 	uint32_t	poll_val;
792 	struct {
793 		uint32_t	rpi:16;
794 		uint32_t	rpen:1;
795 		uint32_t	resv17_31:15;
796 	} poll_bits;
797 } nge_rx_poll;
798 
799 /*
800  * Transmit polling count
801  */
802 #define	NGE_TX_PCNT		0x114
803 typedef union _nge_tx_pcnt {
804 	uint32_t	cnt_val;
805 	struct {
806 		uint32_t	pcnt:32;
807 	} cnt_bits;
808 } nge_tx_pcnt;
809 
810 /*
811  * Receive polling count
812  */
813 #define	NGE_RX_PCNT		0x118
814 typedef union _nge_rx_pcnt {
815 	uint32_t	cnt_val;
816 	struct {
817 		uint32_t	pcnt:32;
818 	} cnt_bits;
819 } nge_rx_pcnt;
820 
821 
822 /*
823  * Current tx's descriptor address
824  */
825 #define	NGE_TX_CUR_DADR		0x11c
826 typedef union _nge_tx_cur_addr {
827 	uint32_t	addr_val;
828 	struct {
829 		uint32_t	resv0_2:3;
830 		uint32_t	addr:29;
831 	} addr_bits;
832 } nge_tx_cur_addr;
833 
834 /*
835  * Current rx's descriptor address
836  */
837 #define	NGE_RX_CUR_DADR		0x120
838 typedef union _nge_rx_cur_addr {
839 	uint32_t	addr_val;
840 	struct {
841 		uint32_t	resv0_2:3;
842 		uint32_t	addr:29;
843 	} addr_bits;
844 } nge_rx_cur_addr;
845 
846 /*
847  * Current tx's data buffer address
848  */
849 #define	NGE_TX_CUR_PRD0		0x124
850 typedef union _nge_tx_cur_prd0 {
851 	uint32_t	prd0_val;
852 	struct {
853 		uint32_t	prd0:32;
854 	} prd0_bits;
855 } nge_tx_cur_prd0;
856 
857 /*
858  * Current tx's data buffer status
859  */
860 #define	NGE_TX_CUR_PRD1		0x128
861 typedef union _nge_tx_cur_prd1 {
862 	uint32_t	prd1_val;
863 	struct {
864 		uint32_t	rebytes:16;
865 		uint32_t	status:16;
866 	} prd1_bits;
867 } nge_tx_cur_prd1;
868 
869 /*
870  * Current rx's data buffer address
871  */
872 #define	NGE_RX_CUR_PRD0		0x12c
873 typedef union _nge_rx_cur_prd0 {
874 	uint32_t	prd0_val;
875 	struct {
876 		uint32_t	prd0:32;
877 	}prd0_bits;
878 } nge_rx_cur_prd0;
879 
880 /*
881  * Current rx's data buffer status
882  */
883 #define	NGE_RX_CUR_PRD1		0x130
884 
885 /*
886  * Next tx's descriptor address
887  */
888 #define	NGE_TX_NXT_DADR		0x134
889 typedef union _nge_tx_nxt_dadr {
890 	uint32_t	dadr_val;
891 	struct {
892 		uint32_t	addr:32;
893 	}addr_bits;
894 } nge_tx_nxt_dadr;
895 
896 /*
897  * Next rx's descriptor address
898  */
899 #define	NGE_RX_NXT_DADR		0x138
900 typedef union _nge_rx_nxt_dadr {
901 	uint32_t	dadr_val;
902 	struct {
903 		uint32_t	addr:32;
904 	} addr_bits;
905 } nge_rx_nxt_dadr;
906 
907 /*
908  * Transmit fifo watermark
909  */
910 #define	NGE_TX_FIFO_WM		0x13c
911 #define	TX_FIFO_TBFW		0
912 #define	TX_FIFO_NOB_WM_MII	1
913 #define	TX_FIFO_NOB_WM_GMII	8
914 #define	TX_FIFO_DATA_LWM	0x20
915 #define	TX_FIFO_PRD_LWM		0x8
916 #define	TX_FIFO_PRD_HWM		0x38
917 typedef union _nge_tx_fifo_wm {
918 	uint32_t	wm_val;
919 	struct {
920 		uint32_t	data_lwm:9;
921 		uint32_t	resv8_11:3;
922 		uint32_t	prd_lwm:6;
923 		uint32_t	uprd_hwm:6;
924 		uint32_t	nbfb_wm:4;
925 		uint32_t	fb_wm:4;
926 	} wm_bits;
927 } nge_tx_fifo_wm;
928 
929 /*
930  * Receive fifo watermark
931  */
932 #define	NGE_RX_FIFO_WM		0x140
933 typedef union _nge_rx_fifo_wm {
934 	uint32_t	wm_val;
935 	struct {
936 		uint32_t	data_hwm:9;
937 		uint32_t	resv9_11:3;
938 		uint32_t	prd_lwm:4;
939 		uint32_t	resv16_17:2;
940 		uint32_t	prd_hwm:4;
941 		uint32_t	resv22_31:10;
942 	} wm_bits;
943 } nge_rx_fifo_wm;
944 
945 /*
946  * Chip mode control
947  */
948 #define	NGE_MODE_CNTL		0x144
949 #define	DESC_MCP1		0x0
950 #define	DESC_OFFLOAD		0x1
951 #define	DESC_HOT		0x2
952 #define	DESC_RESV		0x3
953 #define	MACHINE_BUSY		0x0
954 #define	MACHINE_IDLE		0x1
955 typedef union _nge_mode_cntl {
956 	uint32_t	mode_val;
957 	struct {
958 		uint32_t	txdm:1;
959 		uint32_t	rxdm:1;
960 		uint32_t	dma_dis:1;
961 		uint32_t	dma_status:1;
962 		uint32_t	bm_reset:1;
963 		uint32_t	resv5:1;
964 		uint32_t	vlan_strip:1;	/* mcp55 chip only */
965 		uint32_t	vlan_ins:1;	/* mcp55 chip only */
966 		uint32_t	desc_type:2;
967 		uint32_t	rx_sum_en:1;
968 		uint32_t	tx_prd_cu_en:1;
969 		uint32_t	w64_dis:1;
970 		uint32_t	tx_rcom_en:1;
971 		uint32_t	rx_filter_en:1;
972 		uint32_t	resv15:1;
973 		uint32_t	resv16:1;	/* ck804 and mcp51 only */
974 		uint32_t	resv17:1;	/* ck804 and mcp51 only */
975 		uint32_t	resv18:1;	/* ck804 and mcp51 only */
976 		uint32_t	resv19_21:3;
977 		uint32_t	tx_fetch_prd:1;	/* mcp51/mcp55 only */
978 		uint32_t	rx_fetch_prd:1;	/* mcp51/mcp55 only */
979 		uint32_t	resv24_29:6;
980 		uint32_t	rx_status:1;
981 		uint32_t	tx_status:1;
982 	} mode_bits;
983 } nge_mode_cntl;
984 
985 #define	NGE_TX_DADR_HI		0x148
986 #define	NGE_RX_DADR_HI		0x14c
987 
988 /*
989  * Mii interrupt register
990  * Note: for mcp55, this is a 32-bit register.
991  */
992 #define	NGE_MINTR_SRC		0x180
993 typedef union _nge_mintr_src {
994 	uint8_t	src_val;
995 	struct {
996 		uint8_t	mrei:1;
997 		uint8_t	mcc2:1;
998 		uint8_t	mcc1:1;
999 		uint8_t	mapi:1;
1000 		uint8_t	mpdi:1;
1001 		uint8_t	resv5_7:3;
1002 	} src_bits;
1003 } nge_mintr_src;
1004 
1005 /*
1006  * Mii interrupt mask
1007  * Note: for mcp55, this is a 32-bit register.
1008  */
1009 #define	NGE_MINTR_MASK		0x184
1010 typedef union _nge_mintr_mask {
1011 	uint8_t	mask_val;
1012 	struct {
1013 		uint8_t	mrei:1;
1014 		uint8_t	mcc2:1;
1015 		uint8_t	mcc1:1;
1016 		uint8_t	mapi:1;
1017 		uint8_t	mpdi:1;
1018 		uint8_t	resv5_7:3;
1019 	} mask_bits;
1020 } nge_mintr_mask;
1021 
1022 /*
1023  * Mii control and status
1024  */
1025 #define	NGE_MII_CS		0x188
1026 #define	MII_POLL_INTV		0x4
1027 typedef union _nge_mii_cs {
1028 	uint32_t	cs_val;
1029 	struct {
1030 		uint32_t	excap:1;
1031 		uint32_t	jab_dec:1;
1032 		uint32_t	lk_up:1;
1033 		uint32_t	ana_cap:1;
1034 		uint32_t	rfault:1;
1035 		uint32_t	auto_neg:1;
1036 		uint32_t	mfps:1;
1037 		uint32_t	resv7:1;
1038 		uint32_t	exst:1;
1039 		uint32_t	hdup_100m_t2:1;
1040 		uint32_t	fdup_100m_t2:1;
1041 		uint32_t	hdup_10m:1;
1042 		uint32_t	fdup_10m:1;
1043 		uint32_t	hdup_100m_x:1;
1044 		uint32_t	fdup_100m_x:1;
1045 		uint32_t	cap_100m_t4:1;
1046 		uint32_t	ap_intv:4;
1047 		uint32_t	ap_en:1;
1048 		uint32_t	resv21_23:3;
1049 		uint32_t	ap_paddr:5;
1050 		uint32_t	resv29_31:3;
1051 	} cs_bits;
1052 } nge_mii_cs;
1053 
1054 /*
1055  * Mii Clock timer register
1056  */
1057 #define	NGE_MII_TM		0x18c
1058 typedef union _nge_mii_tm {
1059 	uint16_t	tm_val;
1060 	struct {
1061 		uint16_t	timer_interv:8;
1062 		uint16_t	timer_en:1;
1063 		uint16_t	resv9_14:6;
1064 		uint16_t	timer_status:1;
1065 	} tm_bits;
1066 } nge_mii_tm;
1067 
1068 /*
1069  * Mdio address
1070  */
1071 #define	NGE_MDIO_ADR		0x190
1072 typedef union _nge_mdio_adr {
1073 	uint16_t	adr_val;
1074 	struct {
1075 		uint16_t	phy_reg:5;
1076 		uint16_t	phy_adr:5;
1077 		uint16_t	mdio_rw:1;
1078 		uint16_t	resv11_14:4;
1079 		uint16_t	mdio_clc:1;
1080 	} adr_bits;
1081 } nge_mdio_adr;
1082 
1083 /*
1084  * Mdio data
1085  */
1086 #define	NGE_MDIO_DATA		0x194
1087 
1088 /*
1089  * Power Management and Control
1090  */
1091 #define	NGE_PM_CNTL		0x200
1092 typedef union _nge_pm_cntl {
1093 	uint32_t	cntl_val;
1094 	struct {
1095 		/*
1096 		 * mp_en:  Magic Packet Enable
1097 		 * pm_en:  Pattern Match Enable
1098 		 * lc_en:  Link Change Enable
1099 		 */
1100 		uint32_t	mp_en_d0:1;
1101 		uint32_t	pm_en_d0:1;
1102 		uint32_t	lc_en_d0:1;
1103 		uint32_t	resv3:1;
1104 		uint32_t	mp_en_d1:1;
1105 		uint32_t	pm_en_d1:1;
1106 		uint32_t	lc_en_d1:1;
1107 		uint32_t	resv7:1;
1108 		uint32_t	mp_en_d2:1;
1109 		uint32_t	pm_en_d2:1;
1110 		uint32_t	lc_en_d2:1;
1111 		uint32_t	resv11:1;
1112 		uint32_t	mp_en_d3:1;
1113 		uint32_t	pm_en_d3:1;
1114 		uint32_t	lc_en_d3:1;
1115 		uint32_t	resv15:1;
1116 		uint32_t	pat_match_en:5;
1117 		uint32_t	resv21_23:3;
1118 		uint32_t	pat_match_stat:5;
1119 		uint32_t	magic_status:1;
1120 		uint32_t	netman_status:1;
1121 		uint32_t	resv31:1;
1122 	} cntl_bits;
1123 } nge_pm_cntl;
1124 
1125 #define	NGE_MPT_CRC0	0x204
1126 #define	NGE_PMC_MK00	0x208
1127 #define	NGE_PMC_MK01	0x20C
1128 #define	NGE_PMC_MK02	0x210
1129 #define	NGE_PMC_MK03	0x214
1130 #define	NGE_MPT_CRC1	0x218
1131 #define	NGE_PMC_MK10	0x21c
1132 #define	NGE_PMC_MK11	0x220
1133 #define	NGE_PMC_MK12	0x224
1134 #define	NGE_PMC_MK13	0x228
1135 #define	NGE_MPT_CRC2	0x22c
1136 #define	NGE_PMC_MK20	0x230
1137 #define	NGE_PMC_MK21	0x234
1138 #define	NGE_PMC_MK22	0x238
1139 #define	NGE_PMC_MK23	0x23c
1140 #define	NGE_MPT_CRC3	0x240
1141 #define	NGE_PMC_MK30	0x244
1142 #define	NGE_PMC_MK31	0x248
1143 #define	NGE_PMC_MK32	0x24c
1144 #define	NGE_PMC_MK33	0x250
1145 #define	NGE_MPT_CRC4	0x254
1146 #define	NGE_PMC_MK40	0x258
1147 #define	NGE_PMC_MK41	0x25c
1148 #define	NGE_PMC_MK42	0x260
1149 #define	NGE_PMC_MK43	0x264
1150 #define	NGE_PMC_ALIAS	0x268
1151 #define	NGE_PMCSR_ALIAS	0x26c
1152 
1153 /*
1154  * Seeprom control
1155  */
1156 #define	NGE_EP_CNTL		0x500
1157 #define	EEPROM_CLKDIV		249
1158 #define	EEPROM_WAITCLK		0x7
1159 typedef union _nge_cp_cntl {
1160 	uint32_t	cntl_val;
1161 	struct {
1162 		uint32_t	clkdiv:8;
1163 		uint32_t	rom_size:3;
1164 		uint32_t	resv11:1;
1165 		uint32_t	word_wid:1;
1166 		uint32_t	resv13_15:3;
1167 		uint32_t	wait_slots:4;
1168 		uint32_t	resv20_31:12;
1169 	} cntl_bits;
1170 } nge_cp_cntl;
1171 
1172 /*
1173  * Seeprom cmd control
1174  */
1175 #define	NGE_EP_CMD			0x504
1176 #define	SEEPROM_CMD_READ		0x0
1177 #define	SEEPROM_CMD_WRITE_ENABLE	0x1
1178 #define	SEEPROM_CMD_ERASE		0x2
1179 #define	SEEPROM_CMD_WRITE		0x3
1180 #define	SEEPROM_CMD_ERALSE_ALL		0x4
1181 #define	SEEPROM_CMD_WRITE_ALL		0x5
1182 #define	SEEPROM_CMD_WRITE_DIS		0x6
1183 #define	SEEPROM_READY			0x1
1184 typedef union _nge_ep_cmd {
1185 	uint32_t	cmd_val;
1186 	struct {
1187 		uint32_t	addr:16;
1188 		uint32_t	cmd:3;
1189 		uint32_t	resv19_30:12;
1190 		uint32_t	sts:1;
1191 	} cmd_bits;
1192 } nge_ep_cmd;
1193 
1194 /*
1195  * Seeprom data register
1196  */
1197 #define	NGE_EP_DATA		0x508
1198 typedef union _nge_ep_data {
1199 	uint32_t	data_val;
1200 	struct {
1201 		uint32_t	data:16;
1202 		uint32_t	resv16_31:16;
1203 	} data_bits;
1204 } nge_ep_data;
1205 
1206 /*
1207  * Power management control 2nd register (since MCP51)
1208  */
1209 #define	NGE_PM_CNTL2		0x600
1210 typedef union _nge_pm_cntl2 {
1211 	uint32_t	cntl_val;
1212 	struct {
1213 		uint32_t	phy_coma_set:1;
1214 		uint32_t	phy_coma_status:1;
1215 		uint32_t	resv2_3:2;
1216 		uint32_t	resv4:1;
1217 		uint32_t	resv5_7:3;
1218 		uint32_t	resv8_11:4;
1219 		uint32_t	resv12_15:4;
1220 		uint32_t	pmt5_en:1;
1221 		uint32_t	pmt6_en:1;
1222 		uint32_t	pmt7_en:1;
1223 		uint32_t	resv19_23:5;
1224 		uint32_t	pmt5_status:1;
1225 		uint32_t	pmt6_status:1;
1226 		uint32_t	pmt7_status:1;
1227 		uint32_t	resv27_31:5;
1228 	} cntl_bits;
1229 } nge_pm_cntl2;
1230 
1231 
1232 /*
1233  * ASF RAM 0x800-0xfff
1234  */
1235 
1236 /*
1237  * Hardware-defined Statistics Block Offsets
1238  *
1239  * These are given in the manual as addresses in NIC memory, starting
1240  * from the NIC statistics area base address of 0x2000;
1241  */
1242 
1243 #define	KS_BASE			0x0280
1244 #define	KS_ADDR(x)		(((x)-KS_BASE)/sizeof (uint32_t))
1245 
1246 typedef enum {
1247 	KS_ifHOutOctets = KS_ADDR(0x0280),
1248 	KS_ifHOutZeroRetranCount,
1249 	KS_ifHOutOneRetranCount,
1250 	KS_ifHOutMoreRetranCount,
1251 	KS_ifHOutColCount,
1252 	KS_ifHOutFifoovCount,
1253 	KS_ifHOutLOCCount,
1254 	KS_ifHOutExDecCount,
1255 	KS_ifHOutRetryCount,
1256 
1257 	KS_ifHInFrameErrCount,
1258 	KS_ifHInExtraOctErrCount,
1259 	KS_ifHInLColErrCount,
1260 	KS_ifHInRuntCount,
1261 	KS_ifHInOversizeErrCount,
1262 	KS_ifHInFovErrCount,
1263 	KS_ifHInFCSErrCount,
1264 	KS_ifHInAlignErrCount,
1265 	KS_ifHInLenErrCount,
1266 	KS_ifHInUniPktsCount,
1267 	KS_ifHInBroadPksCount,
1268 	KS_ifHInMulPksCount,
1269 	KS_STATS_SIZE = KS_ADDR(0x2d0)
1270 
1271 } nge_stats_offset_t;
1272 
1273 /*
1274  * Hardware-defined Statistics Block
1275  *
1276  * Another view of the statistic block, as a array and a structure ...
1277  */
1278 
1279 typedef union {
1280 	uint64_t a[KS_STATS_SIZE];
1281 	struct {
1282 	uint64_t OutOctets;
1283 	uint64_t OutZeroRetranCount;
1284 	uint64_t OutOneRetranCount;
1285 	uint64_t OutMoreRetranCount;
1286 	uint64_t OutColCount;
1287 	uint64_t OutFifoovCount;
1288 	uint64_t OutLOCCount;
1289 	uint64_t OutExDecCount;
1290 	uint64_t OutRetryCount;
1291 
1292 	uint64_t InFrameErrCount;
1293 	uint64_t InExtraOctErrCount;
1294 	uint64_t InLColErrCount;
1295 	uint64_t InRuntCount;
1296 	uint64_t InOversizeErrCount;
1297 	uint64_t InFovErrCount;
1298 	uint64_t InFCSErrCount;
1299 	uint64_t InAlignErrCount;
1300 	uint64_t InLenErrCount;
1301 	uint64_t InUniPktsCount;
1302 	uint64_t InBroadPksCount;
1303 	uint64_t InMulPksCount;
1304 	} s;
1305 } nge_hw_statistics_t;
1306 
1307 /*
1308  * MII (PHY) registers, beyond those already defined in <sys/miiregs.h>
1309  */
1310 
1311 #define	NGE_PHY_NUMBER	32
1312 #define	MII_LP_ASYM_PAUSE	0x0800
1313 #define	MII_LP_PAUSE		0x0400
1314 
1315 #define	MII_100BASE_T4		0x0200
1316 #define	MII_100BASET_FD		0x0100
1317 #define	MII_100BASET_HD		0x0080
1318 #define	MII_10BASET_FD		0x0040
1319 #define	MII_10BASET_HD		0x0020
1320 
1321 #define	MII_ID_MARVELL		0x5043
1322 #define	MII_ID_CICADA		0x03f1
1323 #define	MII_IDL_MASK		0xfc00
1324 #define	MII_AN_LPNXTPG		8
1325 
1326 
1327 #define	MII_IEEE_EXT_STATUS	15
1328 
1329 /*
1330  * New bits in the MII_CONTROL register
1331  */
1332 #define	MII_CONTROL_1000MB	0x0040
1333 
1334 /*
1335  * Bits in the MII_1000BASE_T_CONTROL register
1336  *
1337  * The MASTER_CFG bit enables manual configuration of Master/Slave mode
1338  * (otherwise, roles are automatically negotiated).  When this bit is set,
1339  * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced.
1340  */
1341 #define	MII_1000BASE_T_CONTROL		9
1342 #define	MII_1000BT_CTL_MASTER_CFG	0x1000	/* enable role select	*/
1343 #define	MII_1000BT_CTL_MASTER_SEL	0x0800	/* role select bit	*/
1344 #define	MII_1000BT_CTL_ADV_FDX		0x0200
1345 #define	MII_1000BT_CTL_ADV_HDX		0x0100
1346 
1347 /*
1348  * Bits in the MII_1000BASE_T_STATUS register
1349  */
1350 #define	MII_1000BASE_T_STATUS		10
1351 #define	MII_1000BT_STAT_MASTER_FAULT	0x8000
1352 #define	MII_1000BT_STAT_MASTER_MODE	0x4000
1353 #define	MII_1000BT_STAT_LCL_RCV_OK	0x2000
1354 #define	MII_1000BT_STAT_RMT_RCV_OK	0x1000
1355 #define	MII_1000BT_STAT_LP_FDX_CAP	0x0800
1356 #define	MII_1000BT_STAT_LP_HDX_CAP	0x0400
1357 
1358 #define	MII_CICADA_BYPASS_CONTROL	MII_VENDOR(2)
1359 #define	CICADA_125MHZ_CLOCK_ENABLE	0x0001
1360 
1361 #define	MII_CICADA_10BASET_CONTROL	MII_VENDOR(6)
1362 #define	MII_CICADA_DISABLE_ECHO_MODE	0x2000
1363 
1364 #define	MII_CICADA_EXT_CONTROL		MII_VENDOR(7)
1365 #define	MII_CICADA_MODE_SELECT_BITS	0xf000
1366 #define	MII_CICADA_MODE_SELECT_RGMII	0x1000
1367 #define	MII_CICADA_POWER_SUPPLY_BITS	0x0e00
1368 #define	MII_CICADA_POWER_SUPPLY_3_3V	0x0000
1369 #define	MII_CICADA_POWER_SUPPLY_2_5V	0x0200
1370 
1371 #define	MII_CICADA_AUXCTRL_STATUS	MII_VENDOR(12)
1372 #define	MII_CICADA_PIN_PRORITY_SETTING	0x0004
1373 #define	MII_CICADA_PIN_PRORITY_DEFAULT	0x0000
1374 
1375 
1376 #define	NGE_REG_SIZE		0xfff
1377 #define	NGE_MII_SIZE		0x20
1378 #define	NGE_SEEROM_SIZE	0x800
1379 /*
1380  * Legacy rx's bd which does not support
1381  * any hardware offload
1382  */
1383 typedef struct _legacy_rx_bd {
1384 	uint32_t	host_buf_addr;
1385 	union {
1386 		uint32_t	cntl_val;
1387 		struct {
1388 			uint32_t	bcnt:16;
1389 			uint32_t	end:1;
1390 			uint32_t	miss:1;
1391 			uint32_t	extra:1;
1392 			uint32_t	inten:1;
1393 			uint32_t	bam:1;
1394 			uint32_t	mam:1;
1395 			uint32_t	pam:1;
1396 			uint32_t	runt:1;
1397 			uint32_t	lcol:1;
1398 			uint32_t	max:1;
1399 			uint32_t	lfer:1;
1400 			uint32_t	crc:1;
1401 			uint32_t	ofol:1;
1402 			uint32_t	fram:1;
1403 			uint32_t	err:1;
1404 			uint32_t	own:1;
1405 		} cntl_bits;
1406 	} cntl_status;
1407 } legacy_rx_bd, *plegacy_rx_bd;
1408 
1409 /*
1410  * Stand offload rx's bd which supports hareware checksum
1411  * for tcp/ip
1412  */
1413 #define	CK8G_NO_HSUM			0x0
1414 #define	CK8G_TCP_SUM_ERR		0x1
1415 #define	CK8G_UDP_SUM_ERR		0x2
1416 #define	CK8G_IP_HSUM_ERR		0x3
1417 #define	CK8G_IP_HSUM			0x4
1418 #define	CK8G_TCP_SUM			0x5
1419 #define	CK8G_UDP_SUM			0x6
1420 #define	CK8G_RESV			0x7
1421 typedef struct _sum_rx_bd {
1422 	uint32_t	host_buf_addr;
1423 	union {
1424 		uint32_t	cntl_val;
1425 		struct {
1426 			uint32_t	bcnt:14;
1427 			uint32_t	resv14_29:16;
1428 			uint32_t	inten:1;
1429 			uint32_t	own:1;
1430 		} control_bits;
1431 		struct {
1432 			uint32_t	bcnt:14;
1433 			uint32_t	resv14:1;
1434 			uint32_t	bam:1;
1435 			uint32_t	mam:1;
1436 			uint32_t	pam:1;
1437 			uint32_t	runt:1;
1438 			uint32_t	lcol:1;
1439 			uint32_t	max:1;
1440 			uint32_t	lfer:1;
1441 			uint32_t	crc:1;
1442 			uint32_t	ofol:1;
1443 			uint32_t	fram:1;
1444 			uint32_t	extra:1;
1445 			uint32_t	l3_l4_sum:3;
1446 			uint32_t	rend:1;
1447 			uint32_t	err:1;
1448 			uint32_t	own:1;
1449 		} status_bits;
1450 	} cntl_status;
1451 } sum_rx_bd, *psum_rx_bd;
1452 /*
1453  * Hot offload rx's bd which support 64bit access and
1454  * full-tcp hardware offload
1455  */
1456 typedef struct _hot_rx_bd {
1457 	uint32_t	host_buf_addr_hi;
1458 	uint32_t	host_buf_addr_lo;
1459 	uint32_t	sw_tag;
1460 	union {
1461 		uint32_t	cntl_val;
1462 		struct {
1463 			uint32_t	bcnt:14;
1464 			uint32_t	resv14_29:16;
1465 			uint32_t	inten:1;
1466 			uint32_t	own:1;
1467 		} control_bits;
1468 
1469 		struct {
1470 			uint32_t	bcnt:14;
1471 			uint32_t	ctmach_rd:1;
1472 			uint32_t	bam:1;
1473 			uint32_t	mam:1;
1474 			uint32_t	pam:1;
1475 			uint32_t	runt:1;
1476 			uint32_t	lcol:1;
1477 			uint32_t	max:1;
1478 			uint32_t	lfer:1;
1479 			uint32_t	crc:1;
1480 			uint32_t	ofol:1;
1481 			uint32_t	fram:1;
1482 			uint32_t	extra:1;
1483 			uint32_t	l3_l4_sum:3;
1484 			uint32_t	rend:1;
1485 			uint32_t	err:1;
1486 			uint32_t	own:1;
1487 		} status_bits_legacy;
1488 	} cntl_status;
1489 } hot_rx_bd, *phot_rx_bd;
1490 
1491 /*
1492  * Legacy tx's bd which does not support
1493  * any hardware offload
1494  */
1495 typedef struct _legacy_tx_bd {
1496 	uint32_t	host_buf_addr;
1497 	union {
1498 		uint32_t	cntl_val;
1499 		struct {
1500 			uint32_t	bcnt:16;
1501 			uint32_t	end:1;
1502 			uint32_t	resv17_23:7;
1503 			uint32_t	inten:1;
1504 			uint32_t	resv25_30:6;
1505 			uint32_t	own:1;
1506 		} control_bits;
1507 
1508 		struct {
1509 			uint32_t	bcnt:16;
1510 			uint32_t	end:1;
1511 			uint32_t	rtry:1;
1512 			uint32_t	trc:4;
1513 			uint32_t	inten:1;
1514 			uint32_t	exdef:1;
1515 			uint32_t	def:1;
1516 			uint32_t	lcar:1;
1517 			uint32_t	lcol:1;
1518 			uint32_t	uflo:1;
1519 			uint32_t	err:1;
1520 			uint32_t	own:1;
1521 		} status_bits;
1522 	} cntl_status;
1523 } legacy_tx_bd, *plegacy_tx_bd;
1524 
1525 /*
1526  * Stand offload tx's bd which supports hareware checksum
1527  * for tcp/ip
1528  */
1529 typedef struct _sum_tx_bd {
1530 	uint32_t	host_buf_addr;
1531 	union {
1532 		uint32_t	cntl_val;
1533 		struct {
1534 			uint32_t	bcnt:14;
1535 			uint32_t	resv14_25:12;
1536 			uint32_t	tcp_hsum:1;
1537 			uint32_t	ip_hsum:1;
1538 			uint32_t	segen:1;
1539 			uint32_t	end:1;
1540 			uint32_t	inten:1;
1541 			uint32_t	own:1;
1542 		} control_sum_bits;
1543 
1544 		struct {
1545 			uint32_t	bcnt:14;
1546 			uint32_t	mss:14;
1547 			uint32_t	segen:1;
1548 			uint32_t	end:1;
1549 			uint32_t	inten:1;
1550 			uint32_t	own:1;
1551 		} control_tso_bits;
1552 
1553 		struct {
1554 			uint32_t	bcnt:14;
1555 			uint32_t	resv14_17:4;
1556 			uint32_t	rtry:1;
1557 			uint32_t	trc:4;
1558 			uint32_t	inten:1;
1559 			uint32_t	exdef:1;
1560 			uint32_t	def:1;
1561 			uint32_t	lcar:1;
1562 			uint32_t	lcol:1;
1563 			uint32_t	uflo:1;
1564 			uint32_t	end:1;
1565 			uint32_t	err:1;
1566 			uint32_t	own:1;
1567 		} status_bits;
1568 	} control_status;
1569 } sum_tx_bd, *psum_tx_bd;
1570 
1571 /*
1572  * Hot offload tx's bd which support 64bit access and
1573  * full-tcp hardware offload
1574  */
1575 
1576 typedef struct _hot_tx_bd {
1577 	uint32_t	host_buf_addr_hi;
1578 	uint32_t	host_buf_addr_lo;
1579 	union {
1580 		uint32_t	parm_val;
1581 		struct {
1582 			uint32_t	resv0_15:16;
1583 			uint32_t	resv16:1;
1584 			uint32_t	resv17:1;
1585 			uint32_t	resv18_31:14;
1586 		} parm_bits;
1587 	} hot_parms;
1588 
1589 	union {
1590 		uint32_t	cntl_val;
1591 		struct {
1592 			uint32_t	bcnt:14;
1593 			uint32_t	resv14_25:12;
1594 			uint32_t	tcp_hsum:1;
1595 			uint32_t	ip_hsum:1;
1596 			uint32_t	segen:1;
1597 			uint32_t	end:1;
1598 			uint32_t	inten:1;
1599 			uint32_t	own:1;
1600 		} control_sum_bits;
1601 
1602 		struct {
1603 			uint32_t	bcnt:14;
1604 			uint32_t	mss:14;
1605 			uint32_t	segen:1;
1606 			uint32_t	end:1;
1607 			uint32_t	inten:1;
1608 			uint32_t	own:1;
1609 		} control_tso_bits;
1610 
1611 		struct {
1612 			uint32_t	bcnt:14;
1613 			uint32_t	resv14_17:4;
1614 			uint32_t	rtry:1;
1615 			uint32_t	trc:4;
1616 			uint32_t	inten:1;
1617 			uint32_t	exdef:1;
1618 			uint32_t	def:1;
1619 			uint32_t	lcar:1;
1620 			uint32_t	lcol:1;
1621 			uint32_t	uflo:1;
1622 			uint32_t	end:1;
1623 			uint32_t	err:1;
1624 			uint32_t	own:1;
1625 		} status_bits;
1626 	} control_status;
1627 } hot_tx_bd, *phot_tx_bd;
1628 
1629 #ifdef __cplusplus
1630 }
1631 #endif
1632 
1633 #endif	/* _SYS_NGE_CHIP_H */
1634